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r600: add cull distance support
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 53
42
43 #define R600_MAX_IMAGES 8
44 /*
45 * ranges reserved for images on evergreen
46 * first set for the immediate buffers,
47 * second for the actual resources for RESQ.
48 */
49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
51
52 /* read caches */
53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* read-write caches */
57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* engine synchronization */
63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66
67 /* the number of CS dwords for flushing and drawing */
68 #define R600_MAX_FLUSH_CS_DWORDS 18
69 #define R600_MAX_DRAW_CS_DWORDS 58
70 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
71
72 #define R600_MAX_USER_CONST_BUFFERS 13
73 #define R600_MAX_DRIVER_CONST_BUFFERS 3
74 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
75
76 #define EG_MAX_ATOMIC_BUFFERS 8
77
78 /* start driver buffers after user buffers */
79 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
80 #define R600_UCP_SIZE (4*4*8)
81 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
82
83 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
84 /*
85 * Note GS doesn't use a constant buffer binding, just a resource index,
86 * so it's fine to have it exist at index 16.
87 */
88 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
89 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
90 * of 16 const buffers.
91 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
92 *
93 * In order to support d3d 11 mandated minimum of 15 user const buffers
94 * we'd have to squash all use cases into one driver buffer.
95 */
96 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
97
98 /* HW stages */
99 #define R600_HW_STAGE_PS 0
100 #define R600_HW_STAGE_VS 1
101 #define R600_HW_STAGE_GS 2
102 #define R600_HW_STAGE_ES 3
103 #define EG_HW_STAGE_LS 4
104 #define EG_HW_STAGE_HS 5
105
106 #define R600_NUM_HW_STAGES 4
107 #define EG_NUM_HW_STAGES 6
108
109 struct r600_context;
110 struct r600_bytecode;
111 union r600_shader_key;
112
113 /* This is an atom containing GPU commands that never change.
114 * This is supposed to be copied directly into the CS. */
115 struct r600_command_buffer {
116 uint32_t *buf;
117 unsigned num_dw;
118 unsigned max_num_dw;
119 unsigned pkt_flags;
120 };
121
122 struct r600_db_state {
123 struct r600_atom atom;
124 struct r600_surface *rsurf;
125 };
126
127 struct r600_db_misc_state {
128 struct r600_atom atom;
129 bool occlusion_queries_disabled;
130 bool flush_depthstencil_through_cb;
131 bool flush_depth_inplace;
132 bool flush_stencil_inplace;
133 bool copy_depth, copy_stencil;
134 unsigned copy_sample;
135 unsigned log_samples;
136 unsigned db_shader_control;
137 bool htile_clear;
138 uint8_t ps_conservative_z;
139 };
140
141 struct r600_cb_misc_state {
142 struct r600_atom atom;
143 unsigned cb_color_control; /* this comes from blend state */
144 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
145 unsigned nr_cbufs;
146 unsigned nr_ps_color_outputs;
147 unsigned nr_image_rats;
148 bool multiwrite;
149 bool dual_src_blend;
150 };
151
152 struct r600_clip_misc_state {
153 struct r600_atom atom;
154 unsigned pa_cl_clip_cntl; /* from rasterizer */
155 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
156 unsigned clip_plane_enable; /* from rasterizer */
157 unsigned cc_dist_mask; /* from vertex shader */
158 unsigned clip_dist_write; /* from vertex shader */
159 unsigned cull_dist_write; /* from vertex shader */
160 boolean clip_disable; /* from vertex shader */
161 boolean vs_out_viewport; /* from vertex shader */
162 };
163
164 struct r600_alphatest_state {
165 struct r600_atom atom;
166 unsigned sx_alpha_test_control; /* this comes from dsa state */
167 unsigned sx_alpha_ref; /* this comes from dsa state */
168 bool bypass;
169 bool cb0_export_16bpc; /* from set_framebuffer_state */
170 };
171
172 struct r600_vgt_state {
173 struct r600_atom atom;
174 uint32_t vgt_multi_prim_ib_reset_en;
175 uint32_t vgt_multi_prim_ib_reset_indx;
176 uint32_t vgt_indx_offset;
177 bool last_draw_was_indirect;
178 };
179
180 struct r600_blend_color {
181 struct r600_atom atom;
182 struct pipe_blend_color state;
183 };
184
185 struct r600_clip_state {
186 struct r600_atom atom;
187 struct pipe_clip_state state;
188 };
189
190 struct r600_cs_shader_state {
191 struct r600_atom atom;
192 unsigned kernel_index;
193 unsigned pc;
194 struct r600_pipe_compute *shader;
195 };
196
197 struct r600_framebuffer {
198 struct r600_atom atom;
199 struct pipe_framebuffer_state state;
200 unsigned compressed_cb_mask;
201 unsigned nr_samples;
202 bool export_16bpc;
203 bool cb0_is_integer;
204 bool is_msaa_resolve;
205 bool dual_src_blend;
206 bool do_update_surf_dirtiness;
207 };
208
209 struct r600_sample_mask {
210 struct r600_atom atom;
211 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
212 };
213
214 struct r600_config_state {
215 struct r600_atom atom;
216 unsigned sq_gpr_resource_mgmt_1;
217 unsigned sq_gpr_resource_mgmt_2;
218 unsigned sq_gpr_resource_mgmt_3;
219 bool dyn_gpr_enabled;
220 };
221
222 struct r600_stencil_ref
223 {
224 ubyte ref_value[2];
225 ubyte valuemask[2];
226 ubyte writemask[2];
227 };
228
229 struct r600_stencil_ref_state {
230 struct r600_atom atom;
231 struct r600_stencil_ref state;
232 struct pipe_stencil_ref pipe_state;
233 };
234
235 struct r600_shader_stages_state {
236 struct r600_atom atom;
237 unsigned geom_enable;
238 };
239
240 struct r600_gs_rings_state {
241 struct r600_atom atom;
242 unsigned enable;
243 struct pipe_constant_buffer esgs_ring;
244 struct pipe_constant_buffer gsvs_ring;
245 };
246
247 /* This must start from 16. */
248 /* features */
249 #define DBG_NO_CP_DMA (1 << 30)
250 /* shader backend */
251 #define DBG_NO_SB (1 << 21)
252 #define DBG_SB_CS (1 << 22)
253 #define DBG_SB_DRY_RUN (1 << 23)
254 #define DBG_SB_STAT (1 << 24)
255 #define DBG_SB_DUMP (1 << 25)
256 #define DBG_SB_NO_FALLBACK (1 << 26)
257 #define DBG_SB_DISASM (1 << 27)
258 #define DBG_SB_SAFEMATH (1 << 28)
259
260 struct r600_screen {
261 struct r600_common_screen b;
262 bool has_msaa;
263 bool has_compressed_msaa_texturing;
264 bool has_atomics;
265
266 /*for compute global memory binding, we allocate stuff here, instead of
267 * buffers.
268 * XXX: Not sure if this is the best place for global_pool. Also,
269 * it's not thread safe, so it won't work with multiple contexts. */
270 struct compute_memory_pool *global_pool;
271 };
272
273 struct r600_pipe_sampler_view {
274 struct pipe_sampler_view base;
275 struct list_head list;
276 struct r600_resource *tex_resource;
277 uint32_t tex_resource_words[8];
278 bool skip_mip_address_reloc;
279 bool is_stencil_sampler;
280 };
281
282 struct r600_rasterizer_state {
283 struct r600_command_buffer buffer;
284 boolean flatshade;
285 boolean two_side;
286 unsigned sprite_coord_enable;
287 unsigned clip_plane_enable;
288 unsigned pa_sc_line_stipple;
289 unsigned pa_cl_clip_cntl;
290 unsigned pa_su_sc_mode_cntl;
291 float offset_units;
292 float offset_scale;
293 bool offset_enable;
294 bool offset_units_unscaled;
295 bool scissor_enable;
296 bool multisample_enable;
297 bool clip_halfz;
298 bool rasterizer_discard;
299 };
300
301 struct r600_poly_offset_state {
302 struct r600_atom atom;
303 enum pipe_format zs_format;
304 float offset_units;
305 float offset_scale;
306 bool offset_units_unscaled;
307 };
308
309 struct r600_blend_state {
310 struct r600_command_buffer buffer;
311 struct r600_command_buffer buffer_no_blend;
312 unsigned cb_target_mask;
313 unsigned cb_color_control;
314 unsigned cb_color_control_no_blend;
315 bool dual_src_blend;
316 bool alpha_to_one;
317 };
318
319 struct r600_dsa_state {
320 struct r600_command_buffer buffer;
321 unsigned alpha_ref;
322 ubyte valuemask[2];
323 ubyte writemask[2];
324 unsigned zwritemask;
325 unsigned sx_alpha_test_control;
326 };
327
328 struct r600_pipe_shader;
329
330 struct r600_pipe_shader_selector {
331 struct r600_pipe_shader *current;
332
333 struct tgsi_token *tokens;
334 struct pipe_stream_output_info so;
335 struct tgsi_shader_info info;
336
337 unsigned num_shaders;
338
339 enum pipe_shader_type type;
340
341 /* geometry shader properties */
342 enum pipe_prim_type gs_output_prim;
343 unsigned gs_max_out_vertices;
344 unsigned gs_num_invocations;
345
346 /* TCS/VS */
347 uint64_t lds_patch_outputs_written_mask;
348 uint64_t lds_outputs_written_mask;
349 unsigned nr_ps_max_color_exports;
350 };
351
352 struct r600_pipe_sampler_state {
353 uint32_t tex_sampler_words[3];
354 union pipe_color_union border_color;
355 bool border_color_use;
356 bool seamless_cube_map;
357 };
358
359 /* needed for blitter save */
360 #define NUM_TEX_UNITS 16
361
362 struct r600_seamless_cube_map {
363 struct r600_atom atom;
364 bool enabled;
365 };
366
367 struct r600_samplerview_state {
368 struct r600_atom atom;
369 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
370 uint32_t enabled_mask;
371 uint32_t dirty_mask;
372 uint32_t compressed_depthtex_mask; /* which textures are depth */
373 uint32_t compressed_colortex_mask;
374 boolean dirty_buffer_constants;
375 };
376
377 struct r600_sampler_states {
378 struct r600_atom atom;
379 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
380 uint32_t enabled_mask;
381 uint32_t dirty_mask;
382 uint32_t has_bordercolor_mask; /* which states contain the border color */
383 };
384
385 struct r600_textures_info {
386 struct r600_samplerview_state views;
387 struct r600_sampler_states states;
388 bool is_array_sampler[NUM_TEX_UNITS];
389 };
390
391 struct r600_shader_driver_constants_info {
392 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
393 uint32_t *constants;
394 uint32_t alloc_size;
395 bool vs_ucp_dirty;
396 bool texture_const_dirty;
397 bool ps_sample_pos_dirty;
398 };
399
400 struct r600_constbuf_state
401 {
402 struct r600_atom atom;
403 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
404 uint32_t enabled_mask;
405 uint32_t dirty_mask;
406 };
407
408 struct r600_vertexbuf_state
409 {
410 struct r600_atom atom;
411 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
412 uint32_t enabled_mask; /* non-NULL buffers */
413 uint32_t dirty_mask;
414 };
415
416 /* CSO (constant state object, in other words, immutable state). */
417 struct r600_cso_state
418 {
419 struct r600_atom atom;
420 void *cso; /* e.g. r600_blend_state */
421 struct r600_command_buffer *cb;
422 };
423
424 struct r600_fetch_shader {
425 struct r600_resource *buffer;
426 unsigned offset;
427 };
428
429 struct r600_shader_state {
430 struct r600_atom atom;
431 struct r600_pipe_shader *shader;
432 };
433
434 struct r600_atomic_buffer_state {
435 uint32_t enabled_mask;
436 uint32_t dirty_mask;
437 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
438 };
439
440 struct r600_image_view {
441 struct pipe_image_view base;
442 uint32_t cb_color_base;
443 uint32_t cb_color_pitch;
444 uint32_t cb_color_slice;
445 uint32_t cb_color_view;
446 uint32_t cb_color_info;
447 uint32_t cb_color_attrib;
448 uint32_t cb_color_dim;
449 uint32_t cb_color_fmask;
450 uint32_t cb_color_fmask_slice;
451 uint32_t immed_resource_words[8];
452 uint32_t resource_words[8];
453 bool skip_mip_address_reloc;
454 uint32_t buf_size;
455 };
456
457 struct r600_image_state {
458 struct r600_atom atom;
459 uint32_t enabled_mask;
460 uint32_t dirty_mask;
461 uint32_t compressed_depthtex_mask;
462 uint32_t compressed_colortex_mask;
463 boolean dirty_buffer_constants;
464 struct r600_image_view views[R600_MAX_IMAGES];
465 };
466
467 struct r600_context {
468 struct r600_common_context b;
469 struct r600_screen *screen;
470 struct blitter_context *blitter;
471 struct u_suballocator *allocator_fetch_shader;
472
473 /* Hardware info. */
474 boolean has_vertex_cache;
475 unsigned default_gprs[EG_NUM_HW_STAGES];
476 unsigned current_gprs[EG_NUM_HW_STAGES];
477 unsigned r6xx_num_clause_temp_gprs;
478
479 /* Miscellaneous state objects. */
480 void *custom_dsa_flush;
481 void *custom_blend_resolve;
482 void *custom_blend_decompress;
483 void *custom_blend_fastclear;
484 /* With rasterizer discard, there doesn't have to be a pixel shader.
485 * In that case, we bind this one: */
486 void *dummy_pixel_shader;
487 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
488 * bug where valid CMASK and FMASK are required to be present to avoid
489 * a hardlock in certain operations but aren't actually used
490 * for anything useful. */
491 struct r600_resource *dummy_fmask;
492 struct r600_resource *dummy_cmask;
493
494 /* State binding slots are here. */
495 struct r600_atom *atoms[R600_NUM_ATOMS];
496 /* Dirty atom bitmask for fast tests */
497 uint64_t dirty_atoms;
498 /* States for CS initialization. */
499 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
500 /** Compute specific registers initializations. The start_cs_cmd atom
501 * must be emitted before start_compute_cs_cmd. */
502 struct r600_command_buffer start_compute_cs_cmd;
503 /* Register states. */
504 struct r600_alphatest_state alphatest_state;
505 struct r600_cso_state blend_state;
506 struct r600_blend_color blend_color;
507 struct r600_cb_misc_state cb_misc_state;
508 struct r600_clip_misc_state clip_misc_state;
509 struct r600_clip_state clip_state;
510 struct r600_db_misc_state db_misc_state;
511 struct r600_db_state db_state;
512 struct r600_cso_state dsa_state;
513 struct r600_framebuffer framebuffer;
514 struct r600_poly_offset_state poly_offset_state;
515 struct r600_cso_state rasterizer_state;
516 struct r600_sample_mask sample_mask;
517 struct r600_seamless_cube_map seamless_cube_map;
518 struct r600_config_state config_state;
519 struct r600_stencil_ref_state stencil_ref;
520 struct r600_vgt_state vgt_state;
521 struct r600_atomic_buffer_state atomic_buffer_state;
522 /* only have images on fragment shader */
523 struct r600_image_state fragment_images;
524 /* Shaders and shader resources. */
525 struct r600_cso_state vertex_fetch_shader;
526 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
527 struct r600_cs_shader_state cs_shader_state;
528 struct r600_shader_stages_state shader_stages;
529 struct r600_gs_rings_state gs_rings;
530 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
531 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
532
533 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
534
535 /** Vertex buffers for fetch shaders */
536 struct r600_vertexbuf_state vertex_buffer_state;
537 /** Vertex buffers for compute shaders */
538 struct r600_vertexbuf_state cs_vertex_buffer_state;
539
540 /* Additional context states. */
541 unsigned compute_cb_target_mask;
542 struct r600_pipe_shader_selector *ps_shader;
543 struct r600_pipe_shader_selector *vs_shader;
544 struct r600_pipe_shader_selector *gs_shader;
545
546 struct r600_pipe_shader_selector *tcs_shader;
547 struct r600_pipe_shader_selector *tes_shader;
548
549 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
550
551 struct r600_rasterizer_state *rasterizer;
552 bool alpha_to_one;
553 bool force_blend_disable;
554 bool gs_tri_strip_adj_fix;
555 boolean dual_src_blend;
556 unsigned zwritemask;
557 int ps_iter_samples;
558
559 /* The list of all texture buffer objects in this context.
560 * This list is walked when a buffer is invalidated/reallocated and
561 * the GPU addresses are updated. */
562 struct list_head texture_buffers;
563
564 /* Last draw state (-1 = unset). */
565 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
566 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
567 enum pipe_prim_type last_rast_prim;
568 unsigned last_start_instance;
569
570 void *sb_context;
571 struct r600_isa *isa;
572 float sample_positions[4 * 16];
573 float tess_state[8];
574 bool tess_state_dirty;
575 struct r600_pipe_shader_selector *last_ls;
576 struct r600_pipe_shader_selector *last_tcs;
577 unsigned last_num_tcs_input_cp;
578 unsigned lds_alloc;
579
580 /* Debug state. */
581 bool is_debug;
582 struct radeon_saved_cs last_gfx;
583 struct r600_resource *last_trace_buf;
584 struct r600_resource *trace_buf;
585 unsigned trace_id;
586
587 struct pipe_resource *append_fence;
588 uint32_t append_fence_id;
589 };
590
591 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
592 struct r600_command_buffer *cb)
593 {
594 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
595 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
596 cs->current.cdw += cb->num_dw;
597 }
598
599 static inline void r600_set_atom_dirty(struct r600_context *rctx,
600 struct r600_atom *atom,
601 bool dirty)
602 {
603 uint64_t mask;
604
605 assert(atom->id != 0);
606 assert(atom->id < sizeof(mask) * 8);
607 mask = 1ull << atom->id;
608 if (dirty)
609 rctx->dirty_atoms |= mask;
610 else
611 rctx->dirty_atoms &= ~mask;
612 }
613
614 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
615 struct r600_atom *atom)
616 {
617 r600_set_atom_dirty(rctx, atom, true);
618 }
619
620 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
621 {
622 atom->emit(&rctx->b, atom);
623 r600_set_atom_dirty(rctx, atom, false);
624 }
625
626 static inline void r600_set_cso_state(struct r600_context *rctx,
627 struct r600_cso_state *state, void *cso)
628 {
629 state->cso = cso;
630 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
631 }
632
633 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
634 struct r600_cso_state *state, void *cso,
635 struct r600_command_buffer *cb)
636 {
637 state->cb = cb;
638 state->atom.num_dw = cb ? cb->num_dw : 0;
639 r600_set_cso_state(rctx, state, cso);
640 }
641
642 /* compute_memory_pool.c */
643 struct compute_memory_pool;
644 void compute_memory_pool_delete(struct compute_memory_pool* pool);
645 struct compute_memory_pool* compute_memory_pool_new(
646 struct r600_screen *rscreen);
647
648 /* evergreen_state.c */
649 struct pipe_sampler_view *
650 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
651 struct pipe_resource *texture,
652 const struct pipe_sampler_view *state,
653 unsigned width0, unsigned height0,
654 unsigned force_level);
655 void evergreen_init_common_regs(struct r600_context *ctx,
656 struct r600_command_buffer *cb,
657 enum chip_class ctx_chip_class,
658 enum radeon_family ctx_family,
659 int ctx_drm_minor);
660 void cayman_init_common_regs(struct r600_command_buffer *cb,
661 enum chip_class ctx_chip_class,
662 enum radeon_family ctx_family,
663 int ctx_drm_minor);
664
665 void evergreen_init_state_functions(struct r600_context *rctx);
666 void evergreen_init_atom_start_cs(struct r600_context *rctx);
667 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
668 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
669 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
670 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
671 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
672 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
673 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
674 void *evergreen_create_resolve_blend(struct r600_context *rctx);
675 void *evergreen_create_decompress_blend(struct r600_context *rctx);
676 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
677 boolean evergreen_is_format_supported(struct pipe_screen *screen,
678 enum pipe_format format,
679 enum pipe_texture_target target,
680 unsigned sample_count,
681 unsigned usage);
682 void evergreen_init_color_surface(struct r600_context *rctx,
683 struct r600_surface *surf);
684 void evergreen_init_color_surface_rat(struct r600_context *rctx,
685 struct r600_surface *surf);
686 void evergreen_update_db_shader_control(struct r600_context * rctx);
687 bool evergreen_adjust_gprs(struct r600_context *rctx);
688 /* r600_blit.c */
689 void r600_init_blit_functions(struct r600_context *rctx);
690 void r600_decompress_depth_textures(struct r600_context *rctx,
691 struct r600_samplerview_state *textures);
692 void r600_decompress_depth_images(struct r600_context *rctx,
693 struct r600_image_state *images);
694 void r600_decompress_color_textures(struct r600_context *rctx,
695 struct r600_samplerview_state *textures);
696 void r600_decompress_color_images(struct r600_context *rctx,
697 struct r600_image_state *images);
698 void r600_resource_copy_region(struct pipe_context *ctx,
699 struct pipe_resource *dst,
700 unsigned dst_level,
701 unsigned dstx, unsigned dsty, unsigned dstz,
702 struct pipe_resource *src,
703 unsigned src_level,
704 const struct pipe_box *src_box);
705
706 /* r600_shader.c */
707 int r600_pipe_shader_create(struct pipe_context *ctx,
708 struct r600_pipe_shader *shader,
709 union r600_shader_key key);
710
711 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
712
713 /* r600_state.c */
714 struct pipe_sampler_view *
715 r600_create_sampler_view_custom(struct pipe_context *ctx,
716 struct pipe_resource *texture,
717 const struct pipe_sampler_view *state,
718 unsigned width_first_level, unsigned height_first_level);
719 void r600_init_state_functions(struct r600_context *rctx);
720 void r600_init_atom_start_cs(struct r600_context *rctx);
721 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
722 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
723 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
724 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
725 void *r600_create_db_flush_dsa(struct r600_context *rctx);
726 void *r600_create_resolve_blend(struct r600_context *rctx);
727 void *r700_create_resolve_blend(struct r600_context *rctx);
728 void *r600_create_decompress_blend(struct r600_context *rctx);
729 bool r600_adjust_gprs(struct r600_context *rctx);
730 boolean r600_is_format_supported(struct pipe_screen *screen,
731 enum pipe_format format,
732 enum pipe_texture_target target,
733 unsigned sample_count,
734 unsigned usage);
735 void r600_update_db_shader_control(struct r600_context * rctx);
736
737 /* r600_hw_context.c */
738 void r600_context_gfx_flush(void *context, unsigned flags,
739 struct pipe_fence_handle **fence);
740 void r600_begin_new_cs(struct r600_context *ctx);
741 void r600_flush_emit(struct r600_context *ctx);
742 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
743 void r600_emit_pfp_sync_me(struct r600_context *rctx);
744 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
745 struct pipe_resource *dst, uint64_t dst_offset,
746 struct pipe_resource *src, uint64_t src_offset,
747 unsigned size);
748 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
749 struct pipe_resource *dst, uint64_t offset,
750 unsigned size, uint32_t clear_value,
751 enum r600_coherency coher);
752 void r600_dma_copy_buffer(struct r600_context *rctx,
753 struct pipe_resource *dst,
754 struct pipe_resource *src,
755 uint64_t dst_offset,
756 uint64_t src_offset,
757 uint64_t size);
758
759 /*
760 * evergreen_hw_context.c
761 */
762 void evergreen_dma_copy_buffer(struct r600_context *rctx,
763 struct pipe_resource *dst,
764 struct pipe_resource *src,
765 uint64_t dst_offset,
766 uint64_t src_offset,
767 uint64_t size);
768 void evergreen_setup_tess_constants(struct r600_context *rctx,
769 const struct pipe_draw_info *info,
770 unsigned *num_patches);
771 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
772 const struct pipe_draw_info *info,
773 unsigned num_patches);
774 void evergreen_set_ls_hs_config(struct r600_context *rctx,
775 struct radeon_winsys_cs *cs,
776 uint32_t ls_hs_config);
777 void evergreen_set_lds_alloc(struct r600_context *rctx,
778 struct radeon_winsys_cs *cs,
779 uint32_t lds_alloc);
780
781 /* r600_state_common.c */
782 void r600_init_common_state_functions(struct r600_context *rctx);
783 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
784 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
785 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
786 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
787 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
788 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
789 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
790 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
791 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
792 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
793 unsigned num_dw);
794 void r600_vertex_buffers_dirty(struct r600_context *rctx);
795 void r600_sampler_views_dirty(struct r600_context *rctx,
796 struct r600_samplerview_state *state);
797 void r600_sampler_states_dirty(struct r600_context *rctx,
798 struct r600_sampler_states *state);
799 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
800 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
801 uint32_t r600_translate_stencil_op(int s_op);
802 uint32_t r600_translate_fill(uint32_t func);
803 unsigned r600_tex_wrap(unsigned wrap);
804 unsigned r600_tex_mipfilter(unsigned filter);
805 unsigned r600_tex_compare(unsigned compare);
806 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
807 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
808 const unsigned char *swizzle_view,
809 boolean vtx);
810 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
811 const unsigned char *swizzle_view,
812 uint32_t *word4_p, uint32_t *yuv_format_p,
813 bool do_endian_swap);
814 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
815 bool do_endian_swap);
816 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
817
818 /* r600_uvd.c */
819 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
820 const struct pipe_video_codec *decoder);
821
822 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
823 const struct pipe_video_buffer *tmpl);
824
825 /*
826 * Helpers for building command buffers
827 */
828
829 #define PKT3_SET_CONFIG_REG 0x68
830 #define PKT3_SET_CONTEXT_REG 0x69
831 #define PKT3_SET_CTL_CONST 0x6F
832 #define PKT3_SET_LOOP_CONST 0x6C
833
834 #define R600_CONFIG_REG_OFFSET 0x08000
835 #define R600_CONTEXT_REG_OFFSET 0x28000
836 #define R600_CTL_CONST_OFFSET 0x3CFF0
837 #define R600_LOOP_CONST_OFFSET 0X0003E200
838 #define EG_LOOP_CONST_OFFSET 0x0003A200
839
840 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
841 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
842 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
843 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
844 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
845
846 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
847
848 /*Evergreen Compute packet3*/
849 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
850
851 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
852 {
853 cb->buf[cb->num_dw++] = value;
854 }
855
856 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
857 {
858 assert(cb->num_dw+num <= cb->max_num_dw);
859 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
860 cb->num_dw += num;
861 }
862
863 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
864 {
865 assert(reg < R600_CONTEXT_REG_OFFSET);
866 assert(cb->num_dw+2+num <= cb->max_num_dw);
867 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
868 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
869 }
870
871 /**
872 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
873 * shaders.
874 */
875 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
876 {
877 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
878 assert(cb->num_dw+2+num <= cb->max_num_dw);
879 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
880 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
881 }
882
883 /**
884 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
885 * shaders.
886 */
887 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
888 {
889 assert(reg >= R600_CTL_CONST_OFFSET);
890 assert(cb->num_dw+2+num <= cb->max_num_dw);
891 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
892 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
893 }
894
895 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
896 {
897 assert(reg >= R600_LOOP_CONST_OFFSET);
898 assert(cb->num_dw+2+num <= cb->max_num_dw);
899 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
900 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
901 }
902
903 /**
904 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
905 * shaders.
906 */
907 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
908 {
909 assert(reg >= EG_LOOP_CONST_OFFSET);
910 assert(cb->num_dw+2+num <= cb->max_num_dw);
911 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
912 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
913 }
914
915 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
916 {
917 r600_store_config_reg_seq(cb, reg, 1);
918 r600_store_value(cb, value);
919 }
920
921 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
922 {
923 r600_store_context_reg_seq(cb, reg, 1);
924 r600_store_value(cb, value);
925 }
926
927 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
928 {
929 r600_store_ctl_const_seq(cb, reg, 1);
930 r600_store_value(cb, value);
931 }
932
933 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
934 {
935 r600_store_loop_const_seq(cb, reg, 1);
936 r600_store_value(cb, value);
937 }
938
939 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
940 {
941 eg_store_loop_const_seq(cb, reg, 1);
942 r600_store_value(cb, value);
943 }
944
945 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
946 void r600_release_command_buffer(struct r600_command_buffer *cb);
947
948 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
949 {
950 radeon_set_context_reg_seq(cs, reg, num);
951 /* Set the compute bit on the packet header */
952 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
953 }
954
955 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
956 {
957 assert(reg >= R600_CTL_CONST_OFFSET);
958 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
959 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
960 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
961 }
962
963 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
964 {
965 radeon_compute_set_context_reg_seq(cs, reg, 1);
966 radeon_emit(cs, value);
967 }
968
969 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
970 {
971 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
972 radeon_compute_set_context_reg(cs, reg, value);
973 } else {
974 radeon_set_context_reg(cs, reg, value);
975 }
976 }
977
978 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
979 {
980 radeon_set_ctl_const_seq(cs, reg, 1);
981 radeon_emit(cs, value);
982 }
983
984 /*
985 * common helpers
986 */
987
988 /* 12.4 fixed-point */
989 static inline unsigned r600_pack_float_12p4(float x)
990 {
991 return x <= 0 ? 0 :
992 x >= 4096 ? 0xffff : x * 16;
993 }
994
995 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
996 {
997 switch (coher) {
998 default:
999 case R600_COHERENCY_NONE:
1000 return 0;
1001 case R600_COHERENCY_SHADER:
1002 return R600_CONTEXT_INV_CONST_CACHE |
1003 R600_CONTEXT_INV_VERTEX_CACHE |
1004 R600_CONTEXT_INV_TEX_CACHE |
1005 R600_CONTEXT_STREAMOUT_FLUSH;
1006 case R600_COHERENCY_CB_META:
1007 return R600_CONTEXT_FLUSH_AND_INV_CB |
1008 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1009 }
1010 }
1011
1012 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1013 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1014 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1015
1016 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1017
1018 void eg_trace_emit(struct r600_context *rctx);
1019 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1020 unsigned flags);
1021
1022 struct r600_shader_atomic;
1023 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1024 struct r600_shader_atomic *combined_atomics,
1025 uint8_t *atomic_used_mask_p);
1026 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1027 struct r600_shader_atomic *combined_atomics,
1028 uint8_t *atomic_used_mask_p);
1029
1030 #endif