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r600: add support for hw atomic counters. (v3)
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 52
42
43 /* read caches */
44 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
45 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
46 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
47 /* read-write caches */
48 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
49 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
51 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
52 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
53 /* engine synchronization */
54 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
55 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
56 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
57
58 /* the number of CS dwords for flushing and drawing */
59 #define R600_MAX_FLUSH_CS_DWORDS 18
60 #define R600_MAX_DRAW_CS_DWORDS 58
61 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
62
63 #define R600_MAX_USER_CONST_BUFFERS 13
64 #define R600_MAX_DRIVER_CONST_BUFFERS 3
65 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
66
67 #define EG_MAX_ATOMIC_BUFFERS 8
68
69 /* start driver buffers after user buffers */
70 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_UCP_SIZE (4*4*8)
72 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
73
74 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
75 /*
76 * Note GS doesn't use a constant buffer binding, just a resource index,
77 * so it's fine to have it exist at index 16.
78 */
79 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
80 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
81 * of 16 const buffers.
82 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
83 *
84 * In order to support d3d 11 mandated minimum of 15 user const buffers
85 * we'd have to squash all use cases into one driver buffer.
86 */
87 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
88
89 /* HW stages */
90 #define R600_HW_STAGE_PS 0
91 #define R600_HW_STAGE_VS 1
92 #define R600_HW_STAGE_GS 2
93 #define R600_HW_STAGE_ES 3
94 #define EG_HW_STAGE_LS 4
95 #define EG_HW_STAGE_HS 5
96
97 #define R600_NUM_HW_STAGES 4
98 #define EG_NUM_HW_STAGES 6
99
100 struct r600_context;
101 struct r600_bytecode;
102 union r600_shader_key;
103
104 /* This is an atom containing GPU commands that never change.
105 * This is supposed to be copied directly into the CS. */
106 struct r600_command_buffer {
107 uint32_t *buf;
108 unsigned num_dw;
109 unsigned max_num_dw;
110 unsigned pkt_flags;
111 };
112
113 struct r600_db_state {
114 struct r600_atom atom;
115 struct r600_surface *rsurf;
116 };
117
118 struct r600_db_misc_state {
119 struct r600_atom atom;
120 bool occlusion_queries_disabled;
121 bool flush_depthstencil_through_cb;
122 bool flush_depth_inplace;
123 bool flush_stencil_inplace;
124 bool copy_depth, copy_stencil;
125 unsigned copy_sample;
126 unsigned log_samples;
127 unsigned db_shader_control;
128 bool htile_clear;
129 uint8_t ps_conservative_z;
130 };
131
132 struct r600_cb_misc_state {
133 struct r600_atom atom;
134 unsigned cb_color_control; /* this comes from blend state */
135 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
136 unsigned nr_cbufs;
137 unsigned nr_ps_color_outputs;
138 bool multiwrite;
139 bool dual_src_blend;
140 };
141
142 struct r600_clip_misc_state {
143 struct r600_atom atom;
144 unsigned pa_cl_clip_cntl; /* from rasterizer */
145 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
146 unsigned clip_plane_enable; /* from rasterizer */
147 unsigned clip_dist_write; /* from vertex shader */
148 boolean clip_disable; /* from vertex shader */
149 boolean vs_out_viewport; /* from vertex shader */
150 };
151
152 struct r600_alphatest_state {
153 struct r600_atom atom;
154 unsigned sx_alpha_test_control; /* this comes from dsa state */
155 unsigned sx_alpha_ref; /* this comes from dsa state */
156 bool bypass;
157 bool cb0_export_16bpc; /* from set_framebuffer_state */
158 };
159
160 struct r600_vgt_state {
161 struct r600_atom atom;
162 uint32_t vgt_multi_prim_ib_reset_en;
163 uint32_t vgt_multi_prim_ib_reset_indx;
164 uint32_t vgt_indx_offset;
165 bool last_draw_was_indirect;
166 };
167
168 struct r600_blend_color {
169 struct r600_atom atom;
170 struct pipe_blend_color state;
171 };
172
173 struct r600_clip_state {
174 struct r600_atom atom;
175 struct pipe_clip_state state;
176 };
177
178 struct r600_cs_shader_state {
179 struct r600_atom atom;
180 unsigned kernel_index;
181 unsigned pc;
182 struct r600_pipe_compute *shader;
183 };
184
185 struct r600_framebuffer {
186 struct r600_atom atom;
187 struct pipe_framebuffer_state state;
188 unsigned compressed_cb_mask;
189 unsigned nr_samples;
190 bool export_16bpc;
191 bool cb0_is_integer;
192 bool is_msaa_resolve;
193 bool dual_src_blend;
194 bool do_update_surf_dirtiness;
195 };
196
197 struct r600_sample_mask {
198 struct r600_atom atom;
199 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
200 };
201
202 struct r600_config_state {
203 struct r600_atom atom;
204 unsigned sq_gpr_resource_mgmt_1;
205 unsigned sq_gpr_resource_mgmt_2;
206 unsigned sq_gpr_resource_mgmt_3;
207 bool dyn_gpr_enabled;
208 };
209
210 struct r600_stencil_ref
211 {
212 ubyte ref_value[2];
213 ubyte valuemask[2];
214 ubyte writemask[2];
215 };
216
217 struct r600_stencil_ref_state {
218 struct r600_atom atom;
219 struct r600_stencil_ref state;
220 struct pipe_stencil_ref pipe_state;
221 };
222
223 struct r600_shader_stages_state {
224 struct r600_atom atom;
225 unsigned geom_enable;
226 };
227
228 struct r600_gs_rings_state {
229 struct r600_atom atom;
230 unsigned enable;
231 struct pipe_constant_buffer esgs_ring;
232 struct pipe_constant_buffer gsvs_ring;
233 };
234
235 /* This must start from 16. */
236 /* features */
237 #define DBG_NO_CP_DMA (1 << 30)
238 /* shader backend */
239 #define DBG_NO_SB (1 << 21)
240 #define DBG_SB_CS (1 << 22)
241 #define DBG_SB_DRY_RUN (1 << 23)
242 #define DBG_SB_STAT (1 << 24)
243 #define DBG_SB_DUMP (1 << 25)
244 #define DBG_SB_NO_FALLBACK (1 << 26)
245 #define DBG_SB_DISASM (1 << 27)
246 #define DBG_SB_SAFEMATH (1 << 28)
247
248 struct r600_screen {
249 struct r600_common_screen b;
250 bool has_msaa;
251 bool has_compressed_msaa_texturing;
252 bool has_atomics;
253
254 /*for compute global memory binding, we allocate stuff here, instead of
255 * buffers.
256 * XXX: Not sure if this is the best place for global_pool. Also,
257 * it's not thread safe, so it won't work with multiple contexts. */
258 struct compute_memory_pool *global_pool;
259 };
260
261 struct r600_pipe_sampler_view {
262 struct pipe_sampler_view base;
263 struct list_head list;
264 struct r600_resource *tex_resource;
265 uint32_t tex_resource_words[8];
266 bool skip_mip_address_reloc;
267 bool is_stencil_sampler;
268 };
269
270 struct r600_rasterizer_state {
271 struct r600_command_buffer buffer;
272 boolean flatshade;
273 boolean two_side;
274 unsigned sprite_coord_enable;
275 unsigned clip_plane_enable;
276 unsigned pa_sc_line_stipple;
277 unsigned pa_cl_clip_cntl;
278 unsigned pa_su_sc_mode_cntl;
279 float offset_units;
280 float offset_scale;
281 bool offset_enable;
282 bool offset_units_unscaled;
283 bool scissor_enable;
284 bool multisample_enable;
285 bool clip_halfz;
286 bool rasterizer_discard;
287 };
288
289 struct r600_poly_offset_state {
290 struct r600_atom atom;
291 enum pipe_format zs_format;
292 float offset_units;
293 float offset_scale;
294 bool offset_units_unscaled;
295 };
296
297 struct r600_blend_state {
298 struct r600_command_buffer buffer;
299 struct r600_command_buffer buffer_no_blend;
300 unsigned cb_target_mask;
301 unsigned cb_color_control;
302 unsigned cb_color_control_no_blend;
303 bool dual_src_blend;
304 bool alpha_to_one;
305 };
306
307 struct r600_dsa_state {
308 struct r600_command_buffer buffer;
309 unsigned alpha_ref;
310 ubyte valuemask[2];
311 ubyte writemask[2];
312 unsigned zwritemask;
313 unsigned sx_alpha_test_control;
314 };
315
316 struct r600_pipe_shader;
317
318 struct r600_pipe_shader_selector {
319 struct r600_pipe_shader *current;
320
321 struct tgsi_token *tokens;
322 struct pipe_stream_output_info so;
323 struct tgsi_shader_info info;
324
325 unsigned num_shaders;
326
327 enum pipe_shader_type type;
328
329 /* geometry shader properties */
330 enum pipe_prim_type gs_output_prim;
331 unsigned gs_max_out_vertices;
332 unsigned gs_num_invocations;
333
334 /* TCS/VS */
335 uint64_t lds_patch_outputs_written_mask;
336 uint64_t lds_outputs_written_mask;
337 unsigned nr_ps_max_color_exports;
338 };
339
340 struct r600_pipe_sampler_state {
341 uint32_t tex_sampler_words[3];
342 union pipe_color_union border_color;
343 bool border_color_use;
344 bool seamless_cube_map;
345 };
346
347 /* needed for blitter save */
348 #define NUM_TEX_UNITS 16
349
350 struct r600_seamless_cube_map {
351 struct r600_atom atom;
352 bool enabled;
353 };
354
355 struct r600_samplerview_state {
356 struct r600_atom atom;
357 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
358 uint32_t enabled_mask;
359 uint32_t dirty_mask;
360 uint32_t compressed_depthtex_mask; /* which textures are depth */
361 uint32_t compressed_colortex_mask;
362 boolean dirty_buffer_constants;
363 };
364
365 struct r600_sampler_states {
366 struct r600_atom atom;
367 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
368 uint32_t enabled_mask;
369 uint32_t dirty_mask;
370 uint32_t has_bordercolor_mask; /* which states contain the border color */
371 };
372
373 struct r600_textures_info {
374 struct r600_samplerview_state views;
375 struct r600_sampler_states states;
376 bool is_array_sampler[NUM_TEX_UNITS];
377 };
378
379 struct r600_shader_driver_constants_info {
380 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
381 uint32_t *constants;
382 uint32_t alloc_size;
383 bool vs_ucp_dirty;
384 bool texture_const_dirty;
385 bool ps_sample_pos_dirty;
386 };
387
388 struct r600_constbuf_state
389 {
390 struct r600_atom atom;
391 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
392 uint32_t enabled_mask;
393 uint32_t dirty_mask;
394 };
395
396 struct r600_vertexbuf_state
397 {
398 struct r600_atom atom;
399 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
400 uint32_t enabled_mask; /* non-NULL buffers */
401 uint32_t dirty_mask;
402 };
403
404 /* CSO (constant state object, in other words, immutable state). */
405 struct r600_cso_state
406 {
407 struct r600_atom atom;
408 void *cso; /* e.g. r600_blend_state */
409 struct r600_command_buffer *cb;
410 };
411
412 struct r600_fetch_shader {
413 struct r600_resource *buffer;
414 unsigned offset;
415 };
416
417 struct r600_shader_state {
418 struct r600_atom atom;
419 struct r600_pipe_shader *shader;
420 };
421
422 struct r600_atomic_buffer_state {
423 uint32_t enabled_mask;
424 uint32_t dirty_mask;
425 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
426 };
427
428 struct r600_context {
429 struct r600_common_context b;
430 struct r600_screen *screen;
431 struct blitter_context *blitter;
432 struct u_suballocator *allocator_fetch_shader;
433
434 /* Hardware info. */
435 boolean has_vertex_cache;
436 unsigned default_gprs[EG_NUM_HW_STAGES];
437 unsigned current_gprs[EG_NUM_HW_STAGES];
438 unsigned r6xx_num_clause_temp_gprs;
439
440 /* Miscellaneous state objects. */
441 void *custom_dsa_flush;
442 void *custom_blend_resolve;
443 void *custom_blend_decompress;
444 void *custom_blend_fastclear;
445 /* With rasterizer discard, there doesn't have to be a pixel shader.
446 * In that case, we bind this one: */
447 void *dummy_pixel_shader;
448 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
449 * bug where valid CMASK and FMASK are required to be present to avoid
450 * a hardlock in certain operations but aren't actually used
451 * for anything useful. */
452 struct r600_resource *dummy_fmask;
453 struct r600_resource *dummy_cmask;
454
455 /* State binding slots are here. */
456 struct r600_atom *atoms[R600_NUM_ATOMS];
457 /* Dirty atom bitmask for fast tests */
458 uint64_t dirty_atoms;
459 /* States for CS initialization. */
460 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
461 /** Compute specific registers initializations. The start_cs_cmd atom
462 * must be emitted before start_compute_cs_cmd. */
463 struct r600_command_buffer start_compute_cs_cmd;
464 /* Register states. */
465 struct r600_alphatest_state alphatest_state;
466 struct r600_cso_state blend_state;
467 struct r600_blend_color blend_color;
468 struct r600_cb_misc_state cb_misc_state;
469 struct r600_clip_misc_state clip_misc_state;
470 struct r600_clip_state clip_state;
471 struct r600_db_misc_state db_misc_state;
472 struct r600_db_state db_state;
473 struct r600_cso_state dsa_state;
474 struct r600_framebuffer framebuffer;
475 struct r600_poly_offset_state poly_offset_state;
476 struct r600_cso_state rasterizer_state;
477 struct r600_sample_mask sample_mask;
478 struct r600_seamless_cube_map seamless_cube_map;
479 struct r600_config_state config_state;
480 struct r600_stencil_ref_state stencil_ref;
481 struct r600_vgt_state vgt_state;
482 struct r600_atomic_buffer_state atomic_buffer_state;
483 /* Shaders and shader resources. */
484 struct r600_cso_state vertex_fetch_shader;
485 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
486 struct r600_cs_shader_state cs_shader_state;
487 struct r600_shader_stages_state shader_stages;
488 struct r600_gs_rings_state gs_rings;
489 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
490 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
491
492 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
493
494 /** Vertex buffers for fetch shaders */
495 struct r600_vertexbuf_state vertex_buffer_state;
496 /** Vertex buffers for compute shaders */
497 struct r600_vertexbuf_state cs_vertex_buffer_state;
498
499 /* Additional context states. */
500 unsigned compute_cb_target_mask;
501 struct r600_pipe_shader_selector *ps_shader;
502 struct r600_pipe_shader_selector *vs_shader;
503 struct r600_pipe_shader_selector *gs_shader;
504
505 struct r600_pipe_shader_selector *tcs_shader;
506 struct r600_pipe_shader_selector *tes_shader;
507
508 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
509
510 struct r600_rasterizer_state *rasterizer;
511 bool alpha_to_one;
512 bool force_blend_disable;
513 boolean dual_src_blend;
514 unsigned zwritemask;
515 int ps_iter_samples;
516
517 /* The list of all texture buffer objects in this context.
518 * This list is walked when a buffer is invalidated/reallocated and
519 * the GPU addresses are updated. */
520 struct list_head texture_buffers;
521
522 /* Last draw state (-1 = unset). */
523 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
524 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
525 enum pipe_prim_type last_rast_prim;
526 unsigned last_start_instance;
527
528 void *sb_context;
529 struct r600_isa *isa;
530 float sample_positions[4 * 16];
531 float tess_state[8];
532 bool tess_state_dirty;
533 struct r600_pipe_shader_selector *last_ls;
534 struct r600_pipe_shader_selector *last_tcs;
535 unsigned last_num_tcs_input_cp;
536 unsigned lds_alloc;
537
538 /* Debug state. */
539 bool is_debug;
540 struct radeon_saved_cs last_gfx;
541 struct r600_resource *last_trace_buf;
542 struct r600_resource *trace_buf;
543 unsigned trace_id;
544
545 struct pipe_resource *append_fence;
546 uint32_t append_fence_id;
547 };
548
549 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
550 struct r600_command_buffer *cb)
551 {
552 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
553 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
554 cs->current.cdw += cb->num_dw;
555 }
556
557 static inline void r600_set_atom_dirty(struct r600_context *rctx,
558 struct r600_atom *atom,
559 bool dirty)
560 {
561 uint64_t mask;
562
563 assert(atom->id != 0);
564 assert(atom->id < sizeof(mask) * 8);
565 mask = 1ull << atom->id;
566 if (dirty)
567 rctx->dirty_atoms |= mask;
568 else
569 rctx->dirty_atoms &= ~mask;
570 }
571
572 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
573 struct r600_atom *atom)
574 {
575 r600_set_atom_dirty(rctx, atom, true);
576 }
577
578 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
579 {
580 atom->emit(&rctx->b, atom);
581 r600_set_atom_dirty(rctx, atom, false);
582 }
583
584 static inline void r600_set_cso_state(struct r600_context *rctx,
585 struct r600_cso_state *state, void *cso)
586 {
587 state->cso = cso;
588 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
589 }
590
591 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
592 struct r600_cso_state *state, void *cso,
593 struct r600_command_buffer *cb)
594 {
595 state->cb = cb;
596 state->atom.num_dw = cb ? cb->num_dw : 0;
597 r600_set_cso_state(rctx, state, cso);
598 }
599
600 /* compute_memory_pool.c */
601 struct compute_memory_pool;
602 void compute_memory_pool_delete(struct compute_memory_pool* pool);
603 struct compute_memory_pool* compute_memory_pool_new(
604 struct r600_screen *rscreen);
605
606 /* evergreen_state.c */
607 struct pipe_sampler_view *
608 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
609 struct pipe_resource *texture,
610 const struct pipe_sampler_view *state,
611 unsigned width0, unsigned height0,
612 unsigned force_level);
613 void evergreen_init_common_regs(struct r600_context *ctx,
614 struct r600_command_buffer *cb,
615 enum chip_class ctx_chip_class,
616 enum radeon_family ctx_family,
617 int ctx_drm_minor);
618 void cayman_init_common_regs(struct r600_command_buffer *cb,
619 enum chip_class ctx_chip_class,
620 enum radeon_family ctx_family,
621 int ctx_drm_minor);
622
623 void evergreen_init_state_functions(struct r600_context *rctx);
624 void evergreen_init_atom_start_cs(struct r600_context *rctx);
625 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
626 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
627 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
628 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
629 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
630 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
631 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
632 void *evergreen_create_resolve_blend(struct r600_context *rctx);
633 void *evergreen_create_decompress_blend(struct r600_context *rctx);
634 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
635 boolean evergreen_is_format_supported(struct pipe_screen *screen,
636 enum pipe_format format,
637 enum pipe_texture_target target,
638 unsigned sample_count,
639 unsigned usage);
640 void evergreen_init_color_surface(struct r600_context *rctx,
641 struct r600_surface *surf);
642 void evergreen_init_color_surface_rat(struct r600_context *rctx,
643 struct r600_surface *surf);
644 void evergreen_update_db_shader_control(struct r600_context * rctx);
645 bool evergreen_adjust_gprs(struct r600_context *rctx);
646 /* r600_blit.c */
647 void r600_init_blit_functions(struct r600_context *rctx);
648 void r600_decompress_depth_textures(struct r600_context *rctx,
649 struct r600_samplerview_state *textures);
650 void r600_decompress_color_textures(struct r600_context *rctx,
651 struct r600_samplerview_state *textures);
652 void r600_resource_copy_region(struct pipe_context *ctx,
653 struct pipe_resource *dst,
654 unsigned dst_level,
655 unsigned dstx, unsigned dsty, unsigned dstz,
656 struct pipe_resource *src,
657 unsigned src_level,
658 const struct pipe_box *src_box);
659
660 /* r600_shader.c */
661 int r600_pipe_shader_create(struct pipe_context *ctx,
662 struct r600_pipe_shader *shader,
663 union r600_shader_key key);
664
665 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
666
667 /* r600_state.c */
668 struct pipe_sampler_view *
669 r600_create_sampler_view_custom(struct pipe_context *ctx,
670 struct pipe_resource *texture,
671 const struct pipe_sampler_view *state,
672 unsigned width_first_level, unsigned height_first_level);
673 void r600_init_state_functions(struct r600_context *rctx);
674 void r600_init_atom_start_cs(struct r600_context *rctx);
675 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
676 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
677 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
678 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
679 void *r600_create_db_flush_dsa(struct r600_context *rctx);
680 void *r600_create_resolve_blend(struct r600_context *rctx);
681 void *r700_create_resolve_blend(struct r600_context *rctx);
682 void *r600_create_decompress_blend(struct r600_context *rctx);
683 bool r600_adjust_gprs(struct r600_context *rctx);
684 boolean r600_is_format_supported(struct pipe_screen *screen,
685 enum pipe_format format,
686 enum pipe_texture_target target,
687 unsigned sample_count,
688 unsigned usage);
689 void r600_update_db_shader_control(struct r600_context * rctx);
690
691 /* r600_hw_context.c */
692 void r600_context_gfx_flush(void *context, unsigned flags,
693 struct pipe_fence_handle **fence);
694 void r600_begin_new_cs(struct r600_context *ctx);
695 void r600_flush_emit(struct r600_context *ctx);
696 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
697 void r600_emit_pfp_sync_me(struct r600_context *rctx);
698 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
699 struct pipe_resource *dst, uint64_t dst_offset,
700 struct pipe_resource *src, uint64_t src_offset,
701 unsigned size);
702 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
703 struct pipe_resource *dst, uint64_t offset,
704 unsigned size, uint32_t clear_value,
705 enum r600_coherency coher);
706 void r600_dma_copy_buffer(struct r600_context *rctx,
707 struct pipe_resource *dst,
708 struct pipe_resource *src,
709 uint64_t dst_offset,
710 uint64_t src_offset,
711 uint64_t size);
712
713 /*
714 * evergreen_hw_context.c
715 */
716 void evergreen_dma_copy_buffer(struct r600_context *rctx,
717 struct pipe_resource *dst,
718 struct pipe_resource *src,
719 uint64_t dst_offset,
720 uint64_t src_offset,
721 uint64_t size);
722 void evergreen_setup_tess_constants(struct r600_context *rctx,
723 const struct pipe_draw_info *info,
724 unsigned *num_patches);
725 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
726 const struct pipe_draw_info *info,
727 unsigned num_patches);
728 void evergreen_set_ls_hs_config(struct r600_context *rctx,
729 struct radeon_winsys_cs *cs,
730 uint32_t ls_hs_config);
731 void evergreen_set_lds_alloc(struct r600_context *rctx,
732 struct radeon_winsys_cs *cs,
733 uint32_t lds_alloc);
734
735 /* r600_state_common.c */
736 void r600_init_common_state_functions(struct r600_context *rctx);
737 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
738 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
739 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
740 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
741 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
742 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
743 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
744 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
745 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
746 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
747 unsigned num_dw);
748 void r600_vertex_buffers_dirty(struct r600_context *rctx);
749 void r600_sampler_views_dirty(struct r600_context *rctx,
750 struct r600_samplerview_state *state);
751 void r600_sampler_states_dirty(struct r600_context *rctx,
752 struct r600_sampler_states *state);
753 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
754 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
755 uint32_t r600_translate_stencil_op(int s_op);
756 uint32_t r600_translate_fill(uint32_t func);
757 unsigned r600_tex_wrap(unsigned wrap);
758 unsigned r600_tex_mipfilter(unsigned filter);
759 unsigned r600_tex_compare(unsigned compare);
760 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
761 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
762 const unsigned char *swizzle_view,
763 boolean vtx);
764 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
765 const unsigned char *swizzle_view,
766 uint32_t *word4_p, uint32_t *yuv_format_p,
767 bool do_endian_swap);
768 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
769 bool do_endian_swap);
770 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
771
772 /* r600_uvd.c */
773 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
774 const struct pipe_video_codec *decoder);
775
776 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
777 const struct pipe_video_buffer *tmpl);
778
779 /*
780 * Helpers for building command buffers
781 */
782
783 #define PKT3_SET_CONFIG_REG 0x68
784 #define PKT3_SET_CONTEXT_REG 0x69
785 #define PKT3_SET_CTL_CONST 0x6F
786 #define PKT3_SET_LOOP_CONST 0x6C
787
788 #define R600_CONFIG_REG_OFFSET 0x08000
789 #define R600_CONTEXT_REG_OFFSET 0x28000
790 #define R600_CTL_CONST_OFFSET 0x3CFF0
791 #define R600_LOOP_CONST_OFFSET 0X0003E200
792 #define EG_LOOP_CONST_OFFSET 0x0003A200
793
794 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
795 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
796 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
797 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
798 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
799
800 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
801
802 /*Evergreen Compute packet3*/
803 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
804
805 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
806 {
807 cb->buf[cb->num_dw++] = value;
808 }
809
810 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
811 {
812 assert(cb->num_dw+num <= cb->max_num_dw);
813 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
814 cb->num_dw += num;
815 }
816
817 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
818 {
819 assert(reg < R600_CONTEXT_REG_OFFSET);
820 assert(cb->num_dw+2+num <= cb->max_num_dw);
821 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
822 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
823 }
824
825 /**
826 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
827 * shaders.
828 */
829 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
830 {
831 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
832 assert(cb->num_dw+2+num <= cb->max_num_dw);
833 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
834 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
835 }
836
837 /**
838 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
839 * shaders.
840 */
841 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
842 {
843 assert(reg >= R600_CTL_CONST_OFFSET);
844 assert(cb->num_dw+2+num <= cb->max_num_dw);
845 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
846 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
847 }
848
849 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
850 {
851 assert(reg >= R600_LOOP_CONST_OFFSET);
852 assert(cb->num_dw+2+num <= cb->max_num_dw);
853 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
854 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
855 }
856
857 /**
858 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
859 * shaders.
860 */
861 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
862 {
863 assert(reg >= EG_LOOP_CONST_OFFSET);
864 assert(cb->num_dw+2+num <= cb->max_num_dw);
865 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
866 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
867 }
868
869 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
870 {
871 r600_store_config_reg_seq(cb, reg, 1);
872 r600_store_value(cb, value);
873 }
874
875 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
876 {
877 r600_store_context_reg_seq(cb, reg, 1);
878 r600_store_value(cb, value);
879 }
880
881 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
882 {
883 r600_store_ctl_const_seq(cb, reg, 1);
884 r600_store_value(cb, value);
885 }
886
887 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
888 {
889 r600_store_loop_const_seq(cb, reg, 1);
890 r600_store_value(cb, value);
891 }
892
893 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
894 {
895 eg_store_loop_const_seq(cb, reg, 1);
896 r600_store_value(cb, value);
897 }
898
899 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
900 void r600_release_command_buffer(struct r600_command_buffer *cb);
901
902 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
903 {
904 radeon_set_context_reg_seq(cs, reg, num);
905 /* Set the compute bit on the packet header */
906 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
907 }
908
909 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
910 {
911 assert(reg >= R600_CTL_CONST_OFFSET);
912 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
913 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
914 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
915 }
916
917 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
918 {
919 radeon_compute_set_context_reg_seq(cs, reg, 1);
920 radeon_emit(cs, value);
921 }
922
923 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
924 {
925 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
926 radeon_compute_set_context_reg(cs, reg, value);
927 } else {
928 radeon_set_context_reg(cs, reg, value);
929 }
930 }
931
932 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
933 {
934 radeon_set_ctl_const_seq(cs, reg, 1);
935 radeon_emit(cs, value);
936 }
937
938 /*
939 * common helpers
940 */
941
942 /* 12.4 fixed-point */
943 static inline unsigned r600_pack_float_12p4(float x)
944 {
945 return x <= 0 ? 0 :
946 x >= 4096 ? 0xffff : x * 16;
947 }
948
949 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
950 {
951 switch (coher) {
952 default:
953 case R600_COHERENCY_NONE:
954 return 0;
955 case R600_COHERENCY_SHADER:
956 return R600_CONTEXT_INV_CONST_CACHE |
957 R600_CONTEXT_INV_VERTEX_CACHE |
958 R600_CONTEXT_INV_TEX_CACHE |
959 R600_CONTEXT_STREAMOUT_FLUSH;
960 case R600_COHERENCY_CB_META:
961 return R600_CONTEXT_FLUSH_AND_INV_CB |
962 R600_CONTEXT_FLUSH_AND_INV_CB_META;
963 }
964 }
965
966 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
967 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
968 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
969
970 unsigned r600_conv_prim_to_gs_out(unsigned mode);
971
972 void eg_trace_emit(struct r600_context *rctx);
973 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
974 unsigned flags);
975
976 struct r600_shader_atomic;
977 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
978 struct r600_shader_atomic *combined_atomics,
979 uint8_t *atomic_used_mask_p);
980 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
981 struct r600_shader_atomic *combined_atomics,
982 uint8_t *atomic_used_mask_p);
983
984 #endif