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r600/eg: workaround bug with tess shader and dynamic GPRs.
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 52
42
43 #define R600_MAX_VIEWPORTS 16
44
45 /* read caches */
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
59
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 58
63 #define R600_TRACE_CS_DWORDS 7
64
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 3
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
68
69 /* start driver buffers after user buffers */
70 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_UCP_SIZE (4*4*8)
72 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
73
74 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
75 /*
76 * Note GS doesn't use a constant buffer binding, just a resource index,
77 * so it's fine to have it exist at index 16.
78 */
79 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
80 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
81 * of 16 const buffers.
82 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
83 *
84 * In order to support d3d 11 mandated minimum of 15 user const buffers
85 * we'd have to squash all use cases into one driver buffer.
86 */
87 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
88
89 /* HW stages */
90 #define R600_HW_STAGE_PS 0
91 #define R600_HW_STAGE_VS 1
92 #define R600_HW_STAGE_GS 2
93 #define R600_HW_STAGE_ES 3
94 #define EG_HW_STAGE_LS 4
95 #define EG_HW_STAGE_HS 5
96
97 #define R600_NUM_HW_STAGES 4
98 #define EG_NUM_HW_STAGES 6
99
100 #ifdef PIPE_ARCH_BIG_ENDIAN
101 #define R600_BIG_ENDIAN 1
102 #else
103 #define R600_BIG_ENDIAN 0
104 #endif
105
106 struct r600_context;
107 struct r600_bytecode;
108 union r600_shader_key;
109
110 /* This is an atom containing GPU commands that never change.
111 * This is supposed to be copied directly into the CS. */
112 struct r600_command_buffer {
113 uint32_t *buf;
114 unsigned num_dw;
115 unsigned max_num_dw;
116 unsigned pkt_flags;
117 };
118
119 struct r600_db_state {
120 struct r600_atom atom;
121 struct r600_surface *rsurf;
122 };
123
124 struct r600_db_misc_state {
125 struct r600_atom atom;
126 bool occlusion_query_enabled;
127 bool flush_depthstencil_through_cb;
128 bool flush_depth_inplace;
129 bool flush_stencil_inplace;
130 bool copy_depth, copy_stencil;
131 unsigned copy_sample;
132 unsigned log_samples;
133 unsigned db_shader_control;
134 bool htile_clear;
135 uint8_t ps_conservative_z;
136 };
137
138 struct r600_cb_misc_state {
139 struct r600_atom atom;
140 unsigned cb_color_control; /* this comes from blend state */
141 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
142 unsigned nr_cbufs;
143 unsigned nr_ps_color_outputs;
144 bool multiwrite;
145 bool dual_src_blend;
146 };
147
148 struct r600_clip_misc_state {
149 struct r600_atom atom;
150 unsigned pa_cl_clip_cntl; /* from rasterizer */
151 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
152 unsigned clip_plane_enable; /* from rasterizer */
153 unsigned clip_dist_write; /* from vertex shader */
154 boolean clip_disable; /* from vertex shader */
155 };
156
157 struct r600_alphatest_state {
158 struct r600_atom atom;
159 unsigned sx_alpha_test_control; /* this comes from dsa state */
160 unsigned sx_alpha_ref; /* this comes from dsa state */
161 bool bypass;
162 bool cb0_export_16bpc; /* from set_framebuffer_state */
163 };
164
165 struct r600_vgt_state {
166 struct r600_atom atom;
167 uint32_t vgt_multi_prim_ib_reset_en;
168 uint32_t vgt_multi_prim_ib_reset_indx;
169 uint32_t vgt_indx_offset;
170 bool last_draw_was_indirect;
171 };
172
173 struct r600_blend_color {
174 struct r600_atom atom;
175 struct pipe_blend_color state;
176 };
177
178 struct r600_clip_state {
179 struct r600_atom atom;
180 struct pipe_clip_state state;
181 };
182
183 struct r600_cs_shader_state {
184 struct r600_atom atom;
185 unsigned kernel_index;
186 unsigned pc;
187 struct r600_pipe_compute *shader;
188 };
189
190 struct r600_framebuffer {
191 struct r600_atom atom;
192 struct pipe_framebuffer_state state;
193 unsigned compressed_cb_mask;
194 unsigned nr_samples;
195 bool export_16bpc;
196 bool cb0_is_integer;
197 bool is_msaa_resolve;
198 };
199
200 struct r600_sample_mask {
201 struct r600_atom atom;
202 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
203 };
204
205 struct r600_config_state {
206 struct r600_atom atom;
207 unsigned sq_gpr_resource_mgmt_1;
208 unsigned sq_gpr_resource_mgmt_2;
209 unsigned sq_gpr_resource_mgmt_3;
210 bool dyn_gpr_enabled;
211 };
212
213 struct r600_stencil_ref
214 {
215 ubyte ref_value[2];
216 ubyte valuemask[2];
217 ubyte writemask[2];
218 };
219
220 struct r600_stencil_ref_state {
221 struct r600_atom atom;
222 struct r600_stencil_ref state;
223 struct pipe_stencil_ref pipe_state;
224 };
225
226 struct r600_viewport_state {
227 struct r600_atom atom;
228 struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
229 uint32_t dirty_mask;
230 };
231
232 struct r600_shader_stages_state {
233 struct r600_atom atom;
234 unsigned geom_enable;
235 };
236
237 struct r600_gs_rings_state {
238 struct r600_atom atom;
239 unsigned enable;
240 struct pipe_constant_buffer esgs_ring;
241 struct pipe_constant_buffer gsvs_ring;
242 };
243
244 /* This must start from 16. */
245 /* features */
246 #define DBG_LLVM (1 << 29)
247 #define DBG_NO_CP_DMA (1 << 30)
248 /* shader backend */
249 #define DBG_NO_SB (1 << 21)
250 #define DBG_SB_CS (1 << 22)
251 #define DBG_SB_DRY_RUN (1 << 23)
252 #define DBG_SB_STAT (1 << 24)
253 #define DBG_SB_DUMP (1 << 25)
254 #define DBG_SB_NO_FALLBACK (1 << 26)
255 #define DBG_SB_DISASM (1 << 27)
256 #define DBG_SB_SAFEMATH (1 << 28)
257
258 struct r600_screen {
259 struct r600_common_screen b;
260 bool has_msaa;
261 bool has_compressed_msaa_texturing;
262
263 /*for compute global memory binding, we allocate stuff here, instead of
264 * buffers.
265 * XXX: Not sure if this is the best place for global_pool. Also,
266 * it's not thread safe, so it won't work with multiple contexts. */
267 struct compute_memory_pool *global_pool;
268 };
269
270 struct r600_pipe_sampler_view {
271 struct pipe_sampler_view base;
272 struct list_head list;
273 struct r600_resource *tex_resource;
274 uint32_t tex_resource_words[8];
275 bool skip_mip_address_reloc;
276 bool is_stencil_sampler;
277 };
278
279 struct r600_rasterizer_state {
280 struct r600_command_buffer buffer;
281 boolean flatshade;
282 boolean two_side;
283 unsigned sprite_coord_enable;
284 unsigned clip_plane_enable;
285 unsigned pa_sc_line_stipple;
286 unsigned pa_cl_clip_cntl;
287 unsigned pa_su_sc_mode_cntl;
288 float offset_units;
289 float offset_scale;
290 bool offset_enable;
291 bool scissor_enable;
292 bool multisample_enable;
293 };
294
295 struct r600_poly_offset_state {
296 struct r600_atom atom;
297 enum pipe_format zs_format;
298 float offset_units;
299 float offset_scale;
300 };
301
302 struct r600_blend_state {
303 struct r600_command_buffer buffer;
304 struct r600_command_buffer buffer_no_blend;
305 unsigned cb_target_mask;
306 unsigned cb_color_control;
307 unsigned cb_color_control_no_blend;
308 bool dual_src_blend;
309 bool alpha_to_one;
310 };
311
312 struct r600_dsa_state {
313 struct r600_command_buffer buffer;
314 unsigned alpha_ref;
315 ubyte valuemask[2];
316 ubyte writemask[2];
317 unsigned zwritemask;
318 unsigned sx_alpha_test_control;
319 };
320
321 struct r600_pipe_shader;
322
323 struct r600_pipe_shader_selector {
324 struct r600_pipe_shader *current;
325
326 struct tgsi_token *tokens;
327 struct pipe_stream_output_info so;
328 struct tgsi_shader_info info;
329
330 unsigned num_shaders;
331
332 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
333 unsigned type;
334
335 /* geometry shader properties */
336 unsigned gs_output_prim;
337 unsigned gs_max_out_vertices;
338 unsigned gs_num_invocations;
339
340 /* TCS/VS */
341 uint64_t lds_patch_outputs_written_mask;
342 uint64_t lds_outputs_written_mask;
343 unsigned nr_ps_max_color_exports;
344 };
345
346 struct r600_pipe_sampler_state {
347 uint32_t tex_sampler_words[3];
348 union pipe_color_union border_color;
349 bool border_color_use;
350 bool seamless_cube_map;
351 };
352
353 /* needed for blitter save */
354 #define NUM_TEX_UNITS 16
355
356 struct r600_seamless_cube_map {
357 struct r600_atom atom;
358 bool enabled;
359 };
360
361 struct r600_samplerview_state {
362 struct r600_atom atom;
363 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
364 uint32_t enabled_mask;
365 uint32_t dirty_mask;
366 uint32_t compressed_depthtex_mask; /* which textures are depth */
367 uint32_t compressed_colortex_mask;
368 boolean dirty_buffer_constants;
369 };
370
371 struct r600_sampler_states {
372 struct r600_atom atom;
373 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
374 uint32_t enabled_mask;
375 uint32_t dirty_mask;
376 uint32_t has_bordercolor_mask; /* which states contain the border color */
377 };
378
379 struct r600_textures_info {
380 struct r600_samplerview_state views;
381 struct r600_sampler_states states;
382 bool is_array_sampler[NUM_TEX_UNITS];
383 };
384
385 struct r600_shader_driver_constants_info {
386 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
387 uint32_t *constants;
388 uint32_t alloc_size;
389 bool vs_ucp_dirty;
390 bool texture_const_dirty;
391 bool ps_sample_pos_dirty;
392 };
393
394 struct r600_constbuf_state
395 {
396 struct r600_atom atom;
397 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
398 uint32_t enabled_mask;
399 uint32_t dirty_mask;
400 };
401
402 struct r600_vertexbuf_state
403 {
404 struct r600_atom atom;
405 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
406 uint32_t enabled_mask; /* non-NULL buffers */
407 uint32_t dirty_mask;
408 };
409
410 /* CSO (constant state object, in other words, immutable state). */
411 struct r600_cso_state
412 {
413 struct r600_atom atom;
414 void *cso; /* e.g. r600_blend_state */
415 struct r600_command_buffer *cb;
416 };
417
418 struct r600_scissor_state
419 {
420 struct r600_atom atom;
421 struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
422 uint32_t dirty_mask;
423 bool enable; /* r6xx only */
424 };
425
426 struct r600_fetch_shader {
427 struct r600_resource *buffer;
428 unsigned offset;
429 };
430
431 struct r600_shader_state {
432 struct r600_atom atom;
433 struct r600_pipe_shader *shader;
434 };
435
436 struct r600_context {
437 struct r600_common_context b;
438 struct r600_screen *screen;
439 struct blitter_context *blitter;
440 struct u_suballocator *allocator_fetch_shader;
441
442 /* Hardware info. */
443 boolean has_vertex_cache;
444 boolean keep_tiling_flags;
445 unsigned default_gprs[EG_NUM_HW_STAGES];
446 unsigned current_gprs[EG_NUM_HW_STAGES];
447 unsigned r6xx_num_clause_temp_gprs;
448
449 /* Miscellaneous state objects. */
450 void *custom_dsa_flush;
451 void *custom_blend_resolve;
452 void *custom_blend_decompress;
453 void *custom_blend_fastclear;
454 /* With rasterizer discard, there doesn't have to be a pixel shader.
455 * In that case, we bind this one: */
456 void *dummy_pixel_shader;
457 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
458 * bug where valid CMASK and FMASK are required to be present to avoid
459 * a hardlock in certain operations but aren't actually used
460 * for anything useful. */
461 struct r600_resource *dummy_fmask;
462 struct r600_resource *dummy_cmask;
463
464 /* State binding slots are here. */
465 struct r600_atom *atoms[R600_NUM_ATOMS];
466 /* Dirty atom bitmask for fast tests */
467 uint64_t dirty_atoms;
468 /* States for CS initialization. */
469 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
470 /** Compute specific registers initializations. The start_cs_cmd atom
471 * must be emitted before start_compute_cs_cmd. */
472 struct r600_command_buffer start_compute_cs_cmd;
473 /* Register states. */
474 struct r600_alphatest_state alphatest_state;
475 struct r600_cso_state blend_state;
476 struct r600_blend_color blend_color;
477 struct r600_cb_misc_state cb_misc_state;
478 struct r600_clip_misc_state clip_misc_state;
479 struct r600_clip_state clip_state;
480 struct r600_db_misc_state db_misc_state;
481 struct r600_db_state db_state;
482 struct r600_cso_state dsa_state;
483 struct r600_framebuffer framebuffer;
484 struct r600_poly_offset_state poly_offset_state;
485 struct r600_cso_state rasterizer_state;
486 struct r600_sample_mask sample_mask;
487 struct r600_scissor_state scissor;
488 struct r600_seamless_cube_map seamless_cube_map;
489 struct r600_config_state config_state;
490 struct r600_stencil_ref_state stencil_ref;
491 struct r600_vgt_state vgt_state;
492 struct r600_viewport_state viewport;
493 /* Shaders and shader resources. */
494 struct r600_cso_state vertex_fetch_shader;
495 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
496 struct r600_cs_shader_state cs_shader_state;
497 struct r600_shader_stages_state shader_stages;
498 struct r600_gs_rings_state gs_rings;
499 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
500 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
501
502 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
503
504 /** Vertex buffers for fetch shaders */
505 struct r600_vertexbuf_state vertex_buffer_state;
506 /** Vertex buffers for compute shaders */
507 struct r600_vertexbuf_state cs_vertex_buffer_state;
508
509 /* Additional context states. */
510 unsigned compute_cb_target_mask;
511 struct r600_pipe_shader_selector *ps_shader;
512 struct r600_pipe_shader_selector *vs_shader;
513 struct r600_pipe_shader_selector *gs_shader;
514
515 struct r600_pipe_shader_selector *tcs_shader;
516 struct r600_pipe_shader_selector *tes_shader;
517
518 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
519
520 struct r600_rasterizer_state *rasterizer;
521 bool alpha_to_one;
522 bool force_blend_disable;
523 boolean dual_src_blend;
524 unsigned zwritemask;
525 int ps_iter_samples;
526
527 /* Index buffer. */
528 struct pipe_index_buffer index_buffer;
529
530 /* Last draw state (-1 = unset). */
531 int last_primitive_type; /* Last primitive type used in draw_vbo. */
532 int last_start_instance;
533
534 void *sb_context;
535 struct r600_isa *isa;
536 float sample_positions[4 * 16];
537 float tess_state[8];
538 bool tess_state_dirty;
539 struct r600_pipe_shader_selector *last_ls;
540 struct r600_pipe_shader_selector *last_tcs;
541 unsigned last_num_tcs_input_cp;
542 unsigned lds_alloc;
543 };
544
545 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
546 struct r600_command_buffer *cb)
547 {
548 assert(cs->cdw + cb->num_dw <= cs->max_dw);
549 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
550 cs->cdw += cb->num_dw;
551 }
552
553 static inline void r600_set_atom_dirty(struct r600_context *rctx,
554 struct r600_atom *atom,
555 bool dirty)
556 {
557 uint64_t mask;
558
559 assert(atom->id != 0);
560 assert(atom->id < sizeof(mask) * 8);
561 mask = 1ull << atom->id;
562 if (dirty)
563 rctx->dirty_atoms |= mask;
564 else
565 rctx->dirty_atoms &= ~mask;
566 }
567
568 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
569 struct r600_atom *atom)
570 {
571 r600_set_atom_dirty(rctx, atom, true);
572 }
573
574 void r600_trace_emit(struct r600_context *rctx);
575
576 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
577 {
578 atom->emit(&rctx->b, atom);
579 r600_set_atom_dirty(rctx, atom, false);
580 if (rctx->screen->b.trace_bo) {
581 r600_trace_emit(rctx);
582 }
583 }
584
585 static inline void r600_set_cso_state(struct r600_context *rctx,
586 struct r600_cso_state *state, void *cso)
587 {
588 state->cso = cso;
589 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
590 }
591
592 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
593 struct r600_cso_state *state, void *cso,
594 struct r600_command_buffer *cb)
595 {
596 state->cb = cb;
597 state->atom.num_dw = cb ? cb->num_dw : 0;
598 r600_set_cso_state(rctx, state, cso);
599 }
600
601 /* compute_memory_pool.c */
602 struct compute_memory_pool;
603 void compute_memory_pool_delete(struct compute_memory_pool* pool);
604 struct compute_memory_pool* compute_memory_pool_new(
605 struct r600_screen *rscreen);
606
607 /* evergreen_state.c */
608 struct pipe_sampler_view *
609 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
610 struct pipe_resource *texture,
611 const struct pipe_sampler_view *state,
612 unsigned width0, unsigned height0,
613 unsigned force_level);
614 void evergreen_init_common_regs(struct r600_context *ctx,
615 struct r600_command_buffer *cb,
616 enum chip_class ctx_chip_class,
617 enum radeon_family ctx_family,
618 int ctx_drm_minor);
619 void cayman_init_common_regs(struct r600_command_buffer *cb,
620 enum chip_class ctx_chip_class,
621 enum radeon_family ctx_family,
622 int ctx_drm_minor);
623
624 void evergreen_init_state_functions(struct r600_context *rctx);
625 void evergreen_init_atom_start_cs(struct r600_context *rctx);
626 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
627 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
628 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
629 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
630 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
631 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
632 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
633 void *evergreen_create_resolve_blend(struct r600_context *rctx);
634 void *evergreen_create_decompress_blend(struct r600_context *rctx);
635 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
636 boolean evergreen_is_format_supported(struct pipe_screen *screen,
637 enum pipe_format format,
638 enum pipe_texture_target target,
639 unsigned sample_count,
640 unsigned usage);
641 void evergreen_init_color_surface(struct r600_context *rctx,
642 struct r600_surface *surf);
643 void evergreen_init_color_surface_rat(struct r600_context *rctx,
644 struct r600_surface *surf);
645 void evergreen_update_db_shader_control(struct r600_context * rctx);
646 bool evergreen_adjust_gprs(struct r600_context *rctx);
647 /* r600_blit.c */
648 void r600_init_blit_functions(struct r600_context *rctx);
649 void r600_decompress_depth_textures(struct r600_context *rctx,
650 struct r600_samplerview_state *textures);
651 void r600_decompress_color_textures(struct r600_context *rctx,
652 struct r600_samplerview_state *textures);
653 void r600_resource_copy_region(struct pipe_context *ctx,
654 struct pipe_resource *dst,
655 unsigned dst_level,
656 unsigned dstx, unsigned dsty, unsigned dstz,
657 struct pipe_resource *src,
658 unsigned src_level,
659 const struct pipe_box *src_box);
660
661 /* r600_shader.c */
662 int r600_pipe_shader_create(struct pipe_context *ctx,
663 struct r600_pipe_shader *shader,
664 union r600_shader_key key);
665
666 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
667
668 /* r600_state.c */
669 struct pipe_sampler_view *
670 r600_create_sampler_view_custom(struct pipe_context *ctx,
671 struct pipe_resource *texture,
672 const struct pipe_sampler_view *state,
673 unsigned width_first_level, unsigned height_first_level);
674 void r600_init_state_functions(struct r600_context *rctx);
675 void r600_init_atom_start_cs(struct r600_context *rctx);
676 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
677 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
678 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
679 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
680 void *r600_create_db_flush_dsa(struct r600_context *rctx);
681 void *r600_create_resolve_blend(struct r600_context *rctx);
682 void *r700_create_resolve_blend(struct r600_context *rctx);
683 void *r600_create_decompress_blend(struct r600_context *rctx);
684 bool r600_adjust_gprs(struct r600_context *rctx);
685 boolean r600_is_format_supported(struct pipe_screen *screen,
686 enum pipe_format format,
687 enum pipe_texture_target target,
688 unsigned sample_count,
689 unsigned usage);
690 void r600_update_db_shader_control(struct r600_context * rctx);
691
692 /* r600_hw_context.c */
693 void r600_context_gfx_flush(void *context, unsigned flags,
694 struct pipe_fence_handle **fence);
695 void r600_begin_new_cs(struct r600_context *ctx);
696 void r600_flush_emit(struct r600_context *ctx);
697 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
698 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
699 struct pipe_resource *dst, uint64_t dst_offset,
700 struct pipe_resource *src, uint64_t src_offset,
701 unsigned size);
702 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
703 struct pipe_resource *dst, uint64_t offset,
704 unsigned size, uint32_t clear_value);
705 void r600_dma_copy_buffer(struct r600_context *rctx,
706 struct pipe_resource *dst,
707 struct pipe_resource *src,
708 uint64_t dst_offset,
709 uint64_t src_offset,
710 uint64_t size);
711
712 /*
713 * evergreen_hw_context.c
714 */
715 void evergreen_dma_copy_buffer(struct r600_context *rctx,
716 struct pipe_resource *dst,
717 struct pipe_resource *src,
718 uint64_t dst_offset,
719 uint64_t src_offset,
720 uint64_t size);
721 void evergreen_setup_tess_constants(struct r600_context *rctx,
722 const struct pipe_draw_info *info,
723 unsigned *num_patches);
724 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
725 const struct pipe_draw_info *info,
726 unsigned num_patches);
727 void evergreen_set_ls_hs_config(struct r600_context *rctx,
728 struct radeon_winsys_cs *cs,
729 uint32_t ls_hs_config);
730 void evergreen_set_lds_alloc(struct r600_context *rctx,
731 struct radeon_winsys_cs *cs,
732 uint32_t lds_alloc);
733
734 /* r600_state_common.c */
735 void r600_init_common_state_functions(struct r600_context *rctx);
736 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
737 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
738 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
739 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
740 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
741 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
742 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
743 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
744 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
745 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
746 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
747 unsigned num_dw);
748 void r600_vertex_buffers_dirty(struct r600_context *rctx);
749 void r600_sampler_views_dirty(struct r600_context *rctx,
750 struct r600_samplerview_state *state);
751 void r600_sampler_states_dirty(struct r600_context *rctx,
752 struct r600_sampler_states *state);
753 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
754 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
755 uint32_t r600_translate_stencil_op(int s_op);
756 uint32_t r600_translate_fill(uint32_t func);
757 unsigned r600_tex_wrap(unsigned wrap);
758 unsigned r600_tex_filter(unsigned filter);
759 unsigned r600_tex_mipfilter(unsigned filter);
760 unsigned r600_tex_compare(unsigned compare);
761 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
762 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
763 struct pipe_resource *texture,
764 const struct pipe_surface *templ,
765 unsigned width, unsigned height);
766 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
767 const unsigned char *swizzle_view,
768 boolean vtx);
769 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
770 const unsigned char *swizzle_view,
771 uint32_t *word4_p, uint32_t *yuv_format_p);
772 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
773 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
774
775 /* r600_uvd.c */
776 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
777 const struct pipe_video_codec *decoder);
778
779 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
780 const struct pipe_video_buffer *tmpl);
781
782 /*
783 * Helpers for building command buffers
784 */
785
786 #define PKT3_SET_CONFIG_REG 0x68
787 #define PKT3_SET_CONTEXT_REG 0x69
788 #define PKT3_SET_CTL_CONST 0x6F
789 #define PKT3_SET_LOOP_CONST 0x6C
790
791 #define R600_CONFIG_REG_OFFSET 0x08000
792 #define R600_CONTEXT_REG_OFFSET 0x28000
793 #define R600_CTL_CONST_OFFSET 0x3CFF0
794 #define R600_LOOP_CONST_OFFSET 0X0003E200
795 #define EG_LOOP_CONST_OFFSET 0x0003A200
796
797 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
798 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
799 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
800 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
801 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
802
803 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
804
805 /*Evergreen Compute packet3*/
806 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
807
808 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
809 {
810 cb->buf[cb->num_dw++] = value;
811 }
812
813 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
814 {
815 assert(cb->num_dw+num <= cb->max_num_dw);
816 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
817 cb->num_dw += num;
818 }
819
820 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
821 {
822 assert(reg < R600_CONTEXT_REG_OFFSET);
823 assert(cb->num_dw+2+num <= cb->max_num_dw);
824 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
825 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
826 }
827
828 /**
829 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
830 * shaders.
831 */
832 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
833 {
834 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
835 assert(cb->num_dw+2+num <= cb->max_num_dw);
836 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
837 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
838 }
839
840 /**
841 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
842 * shaders.
843 */
844 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
845 {
846 assert(reg >= R600_CTL_CONST_OFFSET);
847 assert(cb->num_dw+2+num <= cb->max_num_dw);
848 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
849 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
850 }
851
852 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
853 {
854 assert(reg >= R600_LOOP_CONST_OFFSET);
855 assert(cb->num_dw+2+num <= cb->max_num_dw);
856 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
857 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
858 }
859
860 /**
861 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
862 * shaders.
863 */
864 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
865 {
866 assert(reg >= EG_LOOP_CONST_OFFSET);
867 assert(cb->num_dw+2+num <= cb->max_num_dw);
868 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
869 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
870 }
871
872 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
873 {
874 r600_store_config_reg_seq(cb, reg, 1);
875 r600_store_value(cb, value);
876 }
877
878 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
879 {
880 r600_store_context_reg_seq(cb, reg, 1);
881 r600_store_value(cb, value);
882 }
883
884 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
885 {
886 r600_store_ctl_const_seq(cb, reg, 1);
887 r600_store_value(cb, value);
888 }
889
890 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
891 {
892 r600_store_loop_const_seq(cb, reg, 1);
893 r600_store_value(cb, value);
894 }
895
896 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
897 {
898 eg_store_loop_const_seq(cb, reg, 1);
899 r600_store_value(cb, value);
900 }
901
902 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
903 void r600_release_command_buffer(struct r600_command_buffer *cb);
904
905 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
906 {
907 radeon_set_context_reg_seq(cs, reg, num);
908 /* Set the compute bit on the packet header */
909 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
910 }
911
912 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
913 {
914 assert(reg >= R600_CTL_CONST_OFFSET);
915 assert(cs->cdw+2+num <= cs->max_dw);
916 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
917 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
918 }
919
920 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
921 {
922 radeon_compute_set_context_reg_seq(cs, reg, 1);
923 radeon_emit(cs, value);
924 }
925
926 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
927 {
928 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
929 radeon_compute_set_context_reg(cs, reg, value);
930 } else {
931 radeon_set_context_reg(cs, reg, value);
932 }
933 }
934
935 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
936 {
937 radeon_set_ctl_const_seq(cs, reg, 1);
938 radeon_emit(cs, value);
939 }
940
941 /*
942 * common helpers
943 */
944 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
945 {
946 return value * (1 << frac_bits);
947 }
948 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
949
950 /* 12.4 fixed-point */
951 static inline unsigned r600_pack_float_12p4(float x)
952 {
953 return x <= 0 ? 0 :
954 x >= 4096 ? 0xffff : x * 16;
955 }
956
957 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
958 static inline bool r600_can_read_depth(struct r600_texture *rtex)
959 {
960 return rtex->resource.b.b.nr_samples <= 1 &&
961 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
962 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
963 }
964
965 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
966 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
967 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
968
969 unsigned r600_conv_prim_to_gs_out(unsigned mode);
970 #endif