2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_atom_flags
{
52 /* When set, atoms are added at the beginning of the dirty list
53 * instead of the end. */
57 /* This encapsulates a state or an operation which can emitted into the GPU
58 * command stream. It's not limited to states only, it can be used for anything
59 * that wants to write commands into the CS (e.g. cache flushes). */
61 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
64 enum r600_atom_flags flags
;
67 struct list_head head
;
70 /* This is an atom containing GPU commands that never change.
71 * This is supposed to be copied directly into the CS. */
72 struct r600_command_buffer
{
73 struct r600_atom atom
;
78 struct r600_atom_surface_sync
{
79 struct r600_atom atom
;
80 unsigned flush_flags
; /* CP_COHER_CNTL */
83 struct r600_atom_db_misc_state
{
84 struct r600_atom atom
;
85 bool occlusion_query_enabled
;
86 bool flush_depthstencil_enabled
;
89 enum r600_pipe_state_id
{
90 R600_PIPE_STATE_BLEND
= 0,
91 R600_PIPE_STATE_BLEND_COLOR
,
92 R600_PIPE_STATE_CONFIG
,
93 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
95 R600_PIPE_STATE_SCISSOR
,
96 R600_PIPE_STATE_VIEWPORT
,
97 R600_PIPE_STATE_RASTERIZER
,
99 R600_PIPE_STATE_FRAMEBUFFER
,
101 R600_PIPE_STATE_STENCIL_REF
,
102 R600_PIPE_STATE_PS_SHADER
,
103 R600_PIPE_STATE_VS_SHADER
,
104 R600_PIPE_STATE_CONSTANT
,
105 R600_PIPE_STATE_SAMPLER
,
106 R600_PIPE_STATE_RESOURCE
,
107 R600_PIPE_STATE_POLYGON_OFFSET
,
108 R600_PIPE_STATE_FETCH_SHADER
,
112 struct r600_pipe_fences
{
113 struct r600_resource
*bo
;
116 /* linked list of preallocated blocks */
117 struct list_head blocks
;
118 /* linked list of freed fences */
119 struct list_head pool
;
124 struct pipe_screen screen
;
125 struct radeon_winsys
*ws
;
127 enum chip_class chip_class
;
128 struct radeon_info info
;
129 struct r600_tiling_info tiling_info
;
130 struct util_slab_mempool pool_buffers
;
131 struct r600_pipe_fences fences
;
133 unsigned num_contexts
;
134 bool use_surface_alloc
;
136 /* for thread-safe write accessing to num_contexts */
137 pipe_mutex mutex_num_contexts
;
140 struct r600_pipe_sampler_view
{
141 struct pipe_sampler_view base
;
142 struct r600_pipe_resource_state state
;
145 struct r600_pipe_rasterizer
{
146 struct r600_pipe_state rstate
;
149 unsigned sprite_coord_enable
;
150 unsigned clip_plane_enable
;
151 unsigned pa_sc_line_stipple
;
152 unsigned pa_cl_clip_cntl
;
157 struct r600_pipe_blend
{
158 struct r600_pipe_state rstate
;
159 unsigned cb_target_mask
;
160 unsigned cb_color_control
;
163 struct r600_pipe_dsa
{
164 struct r600_pipe_state rstate
;
171 struct r600_vertex_element
174 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
175 struct u_vbuf_elements
*vmgr_elements
;
176 struct r600_resource
*fetch_shader
;
178 struct r600_pipe_state rstate
;
179 /* if offset is to big for fetch instructio we need to alterate
180 * offset of vertex buffer, record here the offset need to add
182 unsigned vbuffer_need_offset
;
183 unsigned vbuffer_offset
[PIPE_MAX_ATTRIBS
];
186 struct r600_pipe_shader
{
187 struct r600_shader shader
;
188 struct r600_pipe_state rstate
;
189 struct r600_resource
*bo
;
190 struct r600_resource
*bo_fetch
;
191 struct r600_vertex_element vertex_elements
;
192 struct tgsi_token
*tokens
;
193 unsigned sprite_coord_enable
;
195 unsigned pa_cl_vs_out_cntl
;
196 struct pipe_stream_output_info so
;
199 struct r600_pipe_sampler_state
{
200 struct r600_pipe_state rstate
;
201 boolean seamless_cube_map
;
204 /* needed for blitter save */
205 #define NUM_TEX_UNITS 16
207 struct r600_textures_info
{
208 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
209 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
213 bool is_array_sampler
[NUM_TEX_UNITS
];
217 struct pipe_reference reference
;
218 unsigned index
; /* in the shared bo */
219 struct r600_resource
*sleep_bo
;
220 struct list_head head
;
223 #define FENCE_BLOCK_SIZE 16
225 struct r600_fence_block
{
226 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
227 struct list_head head
;
230 #define R600_CONSTANT_ARRAY_SIZE 256
231 #define R600_RESOURCE_ARRAY_SIZE 160
233 struct r600_stencil_ref
240 struct r600_context
{
241 struct pipe_context context
;
242 struct blitter_context
*blitter
;
243 enum radeon_family family
;
244 enum chip_class chip_class
;
245 unsigned r6xx_num_clause_temp_gprs
;
246 void *custom_dsa_flush
;
247 struct r600_screen
*screen
;
248 struct radeon_winsys
*ws
;
249 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
250 struct r600_vertex_element
*vertex_elements
;
251 struct r600_pipe_resource_state fs_resource
[PIPE_MAX_ATTRIBS
];
252 struct pipe_framebuffer_state framebuffer
;
253 unsigned cb_target_mask
;
254 unsigned cb_color_control
;
255 unsigned pa_sc_line_stipple
;
256 unsigned pa_cl_clip_cntl
;
257 /* for saving when using blitter */
258 struct pipe_stencil_ref stencil_ref
;
259 struct pipe_viewport_state viewport
;
260 struct pipe_clip_state clip
;
261 struct r600_pipe_shader
*ps_shader
;
262 struct r600_pipe_shader
*vs_shader
;
263 struct r600_pipe_state vs_const_buffer
;
264 struct r600_pipe_resource_state vs_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
265 struct r600_pipe_state ps_const_buffer
;
266 struct r600_pipe_resource_state ps_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
267 struct r600_pipe_rasterizer
*rasterizer
;
268 struct r600_pipe_state vgt
;
269 struct r600_pipe_state spi
;
270 struct pipe_query
*current_render_cond
;
271 unsigned current_render_cond_mode
;
272 struct pipe_query
*saved_render_cond
;
273 unsigned saved_render_cond_mode
;
274 /* shader information */
276 unsigned sprite_coord_enable
;
277 boolean export_16bpc
;
279 boolean alpha_ref_dirty
;
281 struct r600_textures_info vs_samplers
;
282 struct r600_textures_info ps_samplers
;
284 struct u_vbuf
*vbuf_mgr
;
285 struct util_slab_mempool pool_transfers
;
286 boolean have_depth_texture
, have_depth_fb
;
288 unsigned default_ps_gprs
, default_vs_gprs
;
290 /* States based on r600_state. */
291 struct list_head dirty_states
;
292 struct r600_command_buffer atom_start_cs
; /* invariant state mostly */
293 struct r600_atom_surface_sync atom_surface_sync
;
294 struct r600_atom atom_r6xx_flush_and_inv
;
295 struct r600_atom_db_misc_state atom_db_misc_state
;
297 /* Below are variables from the old r600_context.
299 struct radeon_winsys_cs
*cs
;
301 struct r600_range
*range
;
303 struct r600_block
**blocks
;
304 struct list_head dirty
;
305 struct list_head resource_dirty
;
306 struct list_head enable_list
;
307 unsigned pm4_dirty_cdwords
;
308 unsigned ctx_pm4_ndwords
;
310 /* The list of active queries. Only one query of each type can be active. */
311 int num_occlusion_queries
;
313 /* Manage queries in two separate groups:
314 * The timer ones and the others (streamout, occlusion).
316 * We do this because we should only suspend non-timer queries for u_blitter,
317 * and later if the non-timer queries are suspended, the context flush should
318 * only suspend and resume the timer queries. */
319 struct list_head active_timer_queries
;
320 unsigned num_cs_dw_timer_queries_suspend
;
321 struct list_head active_nontimer_queries
;
322 unsigned num_cs_dw_nontimer_queries_suspend
;
324 unsigned num_cs_dw_streamout_end
;
326 unsigned backend_mask
;
327 unsigned max_db
; /* for OQ */
329 boolean predicate_drawing
;
330 struct r600_range ps_resources
;
331 struct r600_range vs_resources
;
332 struct r600_range fs_resources
;
333 int num_ps_resources
, num_vs_resources
, num_fs_resources
;
335 unsigned num_so_targets
;
336 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
337 boolean streamout_start
;
338 unsigned streamout_append_bitmask
;
341 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
343 atom
->emit(rctx
, atom
);
345 if (atom
->head
.next
&& atom
->head
.prev
)
346 LIST_DELINIT(&atom
->head
);
349 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
352 if (state
->flags
& EMIT_EARLY
) {
353 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
355 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
361 /* evergreen_state.c */
362 void evergreen_init_state_functions(struct r600_context
*rctx
);
363 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
364 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
365 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
366 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
367 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
368 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
369 void evergreen_pipe_init_buffer_resource(struct r600_context
*rctx
,
370 struct r600_pipe_resource_state
*rstate
);
371 void evergreen_pipe_mod_buffer_resource(struct pipe_context
*ctx
,
372 struct r600_pipe_resource_state
*rstate
,
373 struct r600_resource
*rbuffer
,
374 unsigned offset
, unsigned stride
,
375 enum radeon_bo_usage usage
);
376 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
377 enum pipe_format format
,
378 enum pipe_texture_target target
,
379 unsigned sample_count
,
383 void r600_init_blit_functions(struct r600_context
*rctx
);
384 void r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
385 void r600_blit_push_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
386 void r600_flush_depth_textures(struct r600_context
*rctx
);
389 bool r600_init_resource(struct r600_screen
*rscreen
,
390 struct r600_resource
*res
,
391 unsigned size
, unsigned alignment
,
392 unsigned bind
, unsigned usage
);
393 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
394 const struct pipe_resource
*templ
);
395 struct pipe_resource
*r600_user_buffer_create(struct pipe_screen
*screen
,
396 void *ptr
, unsigned bytes
,
398 void r600_upload_index_buffer(struct r600_context
*rctx
,
399 struct pipe_index_buffer
*ib
, unsigned count
);
403 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
407 void r600_init_query_functions(struct r600_context
*rctx
);
408 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
409 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
410 void r600_suspend_timer_queries(struct r600_context
*ctx
);
411 void r600_resume_timer_queries(struct r600_context
*ctx
);
413 /* r600_resource.c */
414 void r600_init_context_resource_functions(struct r600_context
*r600
);
417 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
418 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
419 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
420 struct r600_shader
*ps
, int id
);
423 void r600_update_sampler_states(struct r600_context
*rctx
);
424 void r600_init_state_functions(struct r600_context
*rctx
);
425 void r600_init_atom_start_cs(struct r600_context
*rctx
);
426 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
427 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
428 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
429 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
430 void r600_polygon_offset_update(struct r600_context
*rctx
);
431 void r600_pipe_init_buffer_resource(struct r600_context
*rctx
,
432 struct r600_pipe_resource_state
*rstate
);
433 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
434 struct r600_resource
*rbuffer
,
435 unsigned offset
, unsigned stride
,
436 enum radeon_bo_usage usage
);
437 void r600_adjust_gprs(struct r600_context
*rctx
);
438 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
439 enum pipe_format format
,
440 enum pipe_texture_target target
,
441 unsigned sample_count
,
445 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
446 void r600_init_surface_functions(struct r600_context
*r600
);
447 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
448 const unsigned char *swizzle_view
,
449 uint32_t *word4_p
, uint32_t *yuv_format_p
);
450 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
451 unsigned level
, unsigned layer
);
453 /* r600_translate.c */
454 void r600_translate_index_buffer(struct r600_context
*r600
,
455 struct pipe_index_buffer
*ib
,
458 /* r600_state_common.c */
459 void r600_init_atom(struct r600_atom
*atom
,
460 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
461 unsigned num_dw
, enum r600_atom_flags flags
);
462 void r600_init_common_atoms(struct r600_context
*rctx
);
463 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
464 void r600_texture_barrier(struct pipe_context
*ctx
);
465 void r600_set_index_buffer(struct pipe_context
*ctx
,
466 const struct pipe_index_buffer
*ib
);
467 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
468 const struct pipe_vertex_buffer
*buffers
);
469 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
471 const struct pipe_vertex_element
*elements
);
472 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
473 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
474 void r600_set_blend_color(struct pipe_context
*ctx
,
475 const struct pipe_blend_color
*state
);
476 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
477 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
478 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
479 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
480 struct pipe_sampler_view
*state
);
481 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
482 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
483 void *r600_create_shader_state(struct pipe_context
*ctx
,
484 const struct pipe_shader_state
*state
);
485 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
486 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
487 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
488 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
489 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
490 struct pipe_resource
*buffer
);
491 struct pipe_stream_output_target
*
492 r600_create_so_target(struct pipe_context
*ctx
,
493 struct pipe_resource
*buffer
,
494 unsigned buffer_offset
,
495 unsigned buffer_size
);
496 void r600_so_target_destroy(struct pipe_context
*ctx
,
497 struct pipe_stream_output_target
*target
);
498 void r600_set_so_targets(struct pipe_context
*ctx
,
499 unsigned num_targets
,
500 struct pipe_stream_output_target
**targets
,
501 unsigned append_bitmask
);
502 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
503 const struct pipe_stencil_ref
*state
);
504 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
505 uint32_t r600_translate_stencil_op(int s_op
);
506 uint32_t r600_translate_fill(uint32_t func
);
507 unsigned r600_tex_wrap(unsigned wrap
);
508 unsigned r600_tex_filter(unsigned filter
);
509 unsigned r600_tex_mipfilter(unsigned filter
);
510 unsigned r600_tex_compare(unsigned compare
);
513 * Helpers for building command buffers
516 #define PKT3_SET_CONFIG_REG 0x68
517 #define PKT3_SET_CONTEXT_REG 0x69
518 #define PKT3_SET_CTL_CONST 0x6F
519 #define PKT3_SET_LOOP_CONST 0x6C
521 #define R600_CONFIG_REG_OFFSET 0x08000
522 #define R600_CONTEXT_REG_OFFSET 0x28000
523 #define R600_CTL_CONST_OFFSET 0x3CFF0
524 #define R600_LOOP_CONST_OFFSET 0X0003E200
525 #define EG_LOOP_CONST_OFFSET 0x0003A200
527 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
528 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
529 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
530 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
531 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
533 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
535 cb
->buf
[cb
->atom
.num_dw
++] = value
;
538 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
540 assert(reg
< R600_CONTEXT_REG_OFFSET
);
541 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
542 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
543 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
546 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
548 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
549 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
550 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
551 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
554 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
556 assert(reg
>= R600_CTL_CONST_OFFSET
);
557 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
558 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
559 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
562 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
564 assert(reg
>= R600_LOOP_CONST_OFFSET
);
565 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
566 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
567 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
570 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
572 assert(reg
>= EG_LOOP_CONST_OFFSET
);
573 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
574 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
575 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
578 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
580 r600_store_config_reg_seq(cb
, reg
, 1);
581 r600_store_value(cb
, value
);
584 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
586 r600_store_context_reg_seq(cb
, reg
, 1);
587 r600_store_value(cb
, value
);
590 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
592 r600_store_ctl_const_seq(cb
, reg
, 1);
593 r600_store_value(cb
, value
);
596 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
598 r600_store_loop_const_seq(cb
, reg
, 1);
599 r600_store_value(cb
, value
);
602 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
604 eg_store_loop_const_seq(cb
, reg
, 1);
605 r600_store_value(cb
, value
);
608 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
609 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
612 * Helpers for emitting state into a command stream directly.
615 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
617 cs
->buf
[cs
->cdw
++] = value
;
620 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
622 assert(reg
< R600_CONTEXT_REG_OFFSET
);
623 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
624 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
625 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
628 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
630 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
631 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
632 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
633 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
636 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
638 assert(reg
>= R600_CTL_CONST_OFFSET
);
639 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
640 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
641 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
644 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
646 r600_write_config_reg_seq(cs
, reg
, 1);
647 r600_write_value(cs
, value
);
650 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
652 r600_write_context_reg_seq(cs
, reg
, 1);
653 r600_write_value(cs
, value
);
656 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
658 r600_write_ctl_const_seq(cs
, reg
, 1);
659 r600_write_value(cs
, value
);
665 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
667 return value
* (1 << frac_bits
);
669 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
671 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
673 if (filter
<= 1) return 0;
674 if (filter
<= 2) return 1;
675 if (filter
<= 4) return 2;
676 if (filter
<= 8) return 3;
680 /* 12.4 fixed-point */
681 static INLINE
unsigned r600_pack_float_12p4(float x
)
684 x
>= 4096 ? 0xffff : x
* 16;