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Merge remote-tracking branch 'public/master' into vulkan
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
36
37 #include "tgsi/tgsi_scan.h"
38
39 #define R600_NUM_ATOMS 52
40
41 /* read caches */
42 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
43 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
44 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
45 /* read-write caches */
46 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
47 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
48 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
49 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
50 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
51 /* engine synchronization */
52 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
53 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
54 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
55
56 /* the number of CS dwords for flushing and drawing */
57 #define R600_MAX_FLUSH_CS_DWORDS 18
58 #define R600_MAX_DRAW_CS_DWORDS 58
59
60 #define R600_MAX_USER_CONST_BUFFERS 13
61 #define R600_MAX_DRIVER_CONST_BUFFERS 3
62 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
63
64 /* start driver buffers after user buffers */
65 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
66 #define R600_UCP_SIZE (4*4*8)
67 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
68
69 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
70 /*
71 * Note GS doesn't use a constant buffer binding, just a resource index,
72 * so it's fine to have it exist at index 16.
73 */
74 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
75 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
76 * of 16 const buffers.
77 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
78 *
79 * In order to support d3d 11 mandated minimum of 15 user const buffers
80 * we'd have to squash all use cases into one driver buffer.
81 */
82 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
83
84 /* HW stages */
85 #define R600_HW_STAGE_PS 0
86 #define R600_HW_STAGE_VS 1
87 #define R600_HW_STAGE_GS 2
88 #define R600_HW_STAGE_ES 3
89 #define EG_HW_STAGE_LS 4
90 #define EG_HW_STAGE_HS 5
91
92 #define R600_NUM_HW_STAGES 4
93 #define EG_NUM_HW_STAGES 6
94
95 #ifdef PIPE_ARCH_BIG_ENDIAN
96 #define R600_BIG_ENDIAN 1
97 #else
98 #define R600_BIG_ENDIAN 0
99 #endif
100
101 struct r600_context;
102 struct r600_bytecode;
103 union r600_shader_key;
104
105 /* This is an atom containing GPU commands that never change.
106 * This is supposed to be copied directly into the CS. */
107 struct r600_command_buffer {
108 uint32_t *buf;
109 unsigned num_dw;
110 unsigned max_num_dw;
111 unsigned pkt_flags;
112 };
113
114 struct r600_db_state {
115 struct r600_atom atom;
116 struct r600_surface *rsurf;
117 };
118
119 struct r600_db_misc_state {
120 struct r600_atom atom;
121 bool occlusion_queries_disabled;
122 bool flush_depthstencil_through_cb;
123 bool flush_depth_inplace;
124 bool flush_stencil_inplace;
125 bool copy_depth, copy_stencil;
126 unsigned copy_sample;
127 unsigned log_samples;
128 unsigned db_shader_control;
129 bool htile_clear;
130 uint8_t ps_conservative_z;
131 };
132
133 struct r600_cb_misc_state {
134 struct r600_atom atom;
135 unsigned cb_color_control; /* this comes from blend state */
136 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
137 unsigned nr_cbufs;
138 unsigned nr_ps_color_outputs;
139 bool multiwrite;
140 bool dual_src_blend;
141 };
142
143 struct r600_clip_misc_state {
144 struct r600_atom atom;
145 unsigned pa_cl_clip_cntl; /* from rasterizer */
146 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
147 unsigned clip_plane_enable; /* from rasterizer */
148 unsigned clip_dist_write; /* from vertex shader */
149 boolean clip_disable; /* from vertex shader */
150 boolean vs_out_viewport; /* from vertex shader */
151 };
152
153 struct r600_alphatest_state {
154 struct r600_atom atom;
155 unsigned sx_alpha_test_control; /* this comes from dsa state */
156 unsigned sx_alpha_ref; /* this comes from dsa state */
157 bool bypass;
158 bool cb0_export_16bpc; /* from set_framebuffer_state */
159 };
160
161 struct r600_vgt_state {
162 struct r600_atom atom;
163 uint32_t vgt_multi_prim_ib_reset_en;
164 uint32_t vgt_multi_prim_ib_reset_indx;
165 uint32_t vgt_indx_offset;
166 bool last_draw_was_indirect;
167 };
168
169 struct r600_blend_color {
170 struct r600_atom atom;
171 struct pipe_blend_color state;
172 };
173
174 struct r600_clip_state {
175 struct r600_atom atom;
176 struct pipe_clip_state state;
177 };
178
179 struct r600_cs_shader_state {
180 struct r600_atom atom;
181 unsigned kernel_index;
182 unsigned pc;
183 struct r600_pipe_compute *shader;
184 };
185
186 struct r600_framebuffer {
187 struct r600_atom atom;
188 struct pipe_framebuffer_state state;
189 unsigned compressed_cb_mask;
190 unsigned nr_samples;
191 bool export_16bpc;
192 bool cb0_is_integer;
193 bool is_msaa_resolve;
194 };
195
196 struct r600_sample_mask {
197 struct r600_atom atom;
198 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
199 };
200
201 struct r600_config_state {
202 struct r600_atom atom;
203 unsigned sq_gpr_resource_mgmt_1;
204 unsigned sq_gpr_resource_mgmt_2;
205 unsigned sq_gpr_resource_mgmt_3;
206 bool dyn_gpr_enabled;
207 };
208
209 struct r600_stencil_ref
210 {
211 ubyte ref_value[2];
212 ubyte valuemask[2];
213 ubyte writemask[2];
214 };
215
216 struct r600_stencil_ref_state {
217 struct r600_atom atom;
218 struct r600_stencil_ref state;
219 struct pipe_stencil_ref pipe_state;
220 };
221
222 struct r600_shader_stages_state {
223 struct r600_atom atom;
224 unsigned geom_enable;
225 };
226
227 struct r600_gs_rings_state {
228 struct r600_atom atom;
229 unsigned enable;
230 struct pipe_constant_buffer esgs_ring;
231 struct pipe_constant_buffer gsvs_ring;
232 };
233
234 /* This must start from 16. */
235 /* features */
236 #define DBG_NO_CP_DMA (1 << 30)
237 /* shader backend */
238 #define DBG_NO_SB (1 << 21)
239 #define DBG_SB_CS (1 << 22)
240 #define DBG_SB_DRY_RUN (1 << 23)
241 #define DBG_SB_STAT (1 << 24)
242 #define DBG_SB_DUMP (1 << 25)
243 #define DBG_SB_NO_FALLBACK (1 << 26)
244 #define DBG_SB_DISASM (1 << 27)
245 #define DBG_SB_SAFEMATH (1 << 28)
246
247 struct r600_screen {
248 struct r600_common_screen b;
249 bool has_msaa;
250 bool has_compressed_msaa_texturing;
251
252 /*for compute global memory binding, we allocate stuff here, instead of
253 * buffers.
254 * XXX: Not sure if this is the best place for global_pool. Also,
255 * it's not thread safe, so it won't work with multiple contexts. */
256 struct compute_memory_pool *global_pool;
257 };
258
259 struct r600_pipe_sampler_view {
260 struct pipe_sampler_view base;
261 struct list_head list;
262 struct r600_resource *tex_resource;
263 uint32_t tex_resource_words[8];
264 bool skip_mip_address_reloc;
265 bool is_stencil_sampler;
266 };
267
268 struct r600_rasterizer_state {
269 struct r600_command_buffer buffer;
270 boolean flatshade;
271 boolean two_side;
272 unsigned sprite_coord_enable;
273 unsigned clip_plane_enable;
274 unsigned pa_sc_line_stipple;
275 unsigned pa_cl_clip_cntl;
276 unsigned pa_su_sc_mode_cntl;
277 float offset_units;
278 float offset_scale;
279 bool offset_enable;
280 bool scissor_enable;
281 bool multisample_enable;
282 };
283
284 struct r600_poly_offset_state {
285 struct r600_atom atom;
286 enum pipe_format zs_format;
287 float offset_units;
288 float offset_scale;
289 };
290
291 struct r600_blend_state {
292 struct r600_command_buffer buffer;
293 struct r600_command_buffer buffer_no_blend;
294 unsigned cb_target_mask;
295 unsigned cb_color_control;
296 unsigned cb_color_control_no_blend;
297 bool dual_src_blend;
298 bool alpha_to_one;
299 };
300
301 struct r600_dsa_state {
302 struct r600_command_buffer buffer;
303 unsigned alpha_ref;
304 ubyte valuemask[2];
305 ubyte writemask[2];
306 unsigned zwritemask;
307 unsigned sx_alpha_test_control;
308 };
309
310 struct r600_pipe_shader;
311
312 struct r600_pipe_shader_selector {
313 struct r600_pipe_shader *current;
314
315 struct tgsi_token *tokens;
316 struct pipe_stream_output_info so;
317 struct tgsi_shader_info info;
318
319 unsigned num_shaders;
320
321 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
322 unsigned type;
323
324 /* geometry shader properties */
325 unsigned gs_output_prim;
326 unsigned gs_max_out_vertices;
327 unsigned gs_num_invocations;
328
329 /* TCS/VS */
330 uint64_t lds_patch_outputs_written_mask;
331 uint64_t lds_outputs_written_mask;
332 unsigned nr_ps_max_color_exports;
333 };
334
335 struct r600_pipe_sampler_state {
336 uint32_t tex_sampler_words[3];
337 union pipe_color_union border_color;
338 bool border_color_use;
339 bool seamless_cube_map;
340 };
341
342 /* needed for blitter save */
343 #define NUM_TEX_UNITS 16
344
345 struct r600_seamless_cube_map {
346 struct r600_atom atom;
347 bool enabled;
348 };
349
350 struct r600_samplerview_state {
351 struct r600_atom atom;
352 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
353 uint32_t enabled_mask;
354 uint32_t dirty_mask;
355 uint32_t compressed_depthtex_mask; /* which textures are depth */
356 uint32_t compressed_colortex_mask;
357 boolean dirty_buffer_constants;
358 };
359
360 struct r600_sampler_states {
361 struct r600_atom atom;
362 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
363 uint32_t enabled_mask;
364 uint32_t dirty_mask;
365 uint32_t has_bordercolor_mask; /* which states contain the border color */
366 };
367
368 struct r600_textures_info {
369 struct r600_samplerview_state views;
370 struct r600_sampler_states states;
371 bool is_array_sampler[NUM_TEX_UNITS];
372 };
373
374 struct r600_shader_driver_constants_info {
375 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
376 uint32_t *constants;
377 uint32_t alloc_size;
378 bool vs_ucp_dirty;
379 bool texture_const_dirty;
380 bool ps_sample_pos_dirty;
381 };
382
383 struct r600_constbuf_state
384 {
385 struct r600_atom atom;
386 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
387 uint32_t enabled_mask;
388 uint32_t dirty_mask;
389 };
390
391 struct r600_vertexbuf_state
392 {
393 struct r600_atom atom;
394 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
395 uint32_t enabled_mask; /* non-NULL buffers */
396 uint32_t dirty_mask;
397 };
398
399 /* CSO (constant state object, in other words, immutable state). */
400 struct r600_cso_state
401 {
402 struct r600_atom atom;
403 void *cso; /* e.g. r600_blend_state */
404 struct r600_command_buffer *cb;
405 };
406
407 struct r600_fetch_shader {
408 struct r600_resource *buffer;
409 unsigned offset;
410 };
411
412 struct r600_shader_state {
413 struct r600_atom atom;
414 struct r600_pipe_shader *shader;
415 };
416
417 struct r600_context {
418 struct r600_common_context b;
419 struct r600_screen *screen;
420 struct blitter_context *blitter;
421 struct u_suballocator *allocator_fetch_shader;
422
423 /* Hardware info. */
424 boolean has_vertex_cache;
425 unsigned default_gprs[EG_NUM_HW_STAGES];
426 unsigned current_gprs[EG_NUM_HW_STAGES];
427 unsigned r6xx_num_clause_temp_gprs;
428
429 /* Miscellaneous state objects. */
430 void *custom_dsa_flush;
431 void *custom_blend_resolve;
432 void *custom_blend_decompress;
433 void *custom_blend_fastclear;
434 /* With rasterizer discard, there doesn't have to be a pixel shader.
435 * In that case, we bind this one: */
436 void *dummy_pixel_shader;
437 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
438 * bug where valid CMASK and FMASK are required to be present to avoid
439 * a hardlock in certain operations but aren't actually used
440 * for anything useful. */
441 struct r600_resource *dummy_fmask;
442 struct r600_resource *dummy_cmask;
443
444 /* State binding slots are here. */
445 struct r600_atom *atoms[R600_NUM_ATOMS];
446 /* Dirty atom bitmask for fast tests */
447 uint64_t dirty_atoms;
448 /* States for CS initialization. */
449 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
450 /** Compute specific registers initializations. The start_cs_cmd atom
451 * must be emitted before start_compute_cs_cmd. */
452 struct r600_command_buffer start_compute_cs_cmd;
453 /* Register states. */
454 struct r600_alphatest_state alphatest_state;
455 struct r600_cso_state blend_state;
456 struct r600_blend_color blend_color;
457 struct r600_cb_misc_state cb_misc_state;
458 struct r600_clip_misc_state clip_misc_state;
459 struct r600_clip_state clip_state;
460 struct r600_db_misc_state db_misc_state;
461 struct r600_db_state db_state;
462 struct r600_cso_state dsa_state;
463 struct r600_framebuffer framebuffer;
464 struct r600_poly_offset_state poly_offset_state;
465 struct r600_cso_state rasterizer_state;
466 struct r600_sample_mask sample_mask;
467 struct r600_seamless_cube_map seamless_cube_map;
468 struct r600_config_state config_state;
469 struct r600_stencil_ref_state stencil_ref;
470 struct r600_vgt_state vgt_state;
471 /* Shaders and shader resources. */
472 struct r600_cso_state vertex_fetch_shader;
473 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
474 struct r600_cs_shader_state cs_shader_state;
475 struct r600_shader_stages_state shader_stages;
476 struct r600_gs_rings_state gs_rings;
477 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
478 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
479
480 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
481
482 /** Vertex buffers for fetch shaders */
483 struct r600_vertexbuf_state vertex_buffer_state;
484 /** Vertex buffers for compute shaders */
485 struct r600_vertexbuf_state cs_vertex_buffer_state;
486
487 /* Additional context states. */
488 unsigned compute_cb_target_mask;
489 struct r600_pipe_shader_selector *ps_shader;
490 struct r600_pipe_shader_selector *vs_shader;
491 struct r600_pipe_shader_selector *gs_shader;
492
493 struct r600_pipe_shader_selector *tcs_shader;
494 struct r600_pipe_shader_selector *tes_shader;
495
496 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
497
498 struct r600_rasterizer_state *rasterizer;
499 bool alpha_to_one;
500 bool force_blend_disable;
501 boolean dual_src_blend;
502 unsigned zwritemask;
503 int ps_iter_samples;
504
505 /* Index buffer. */
506 struct pipe_index_buffer index_buffer;
507
508 /* Last draw state (-1 = unset). */
509 int last_primitive_type; /* Last primitive type used in draw_vbo. */
510 int last_start_instance;
511
512 void *sb_context;
513 struct r600_isa *isa;
514 float sample_positions[4 * 16];
515 float tess_state[8];
516 bool tess_state_dirty;
517 struct r600_pipe_shader_selector *last_ls;
518 struct r600_pipe_shader_selector *last_tcs;
519 unsigned last_num_tcs_input_cp;
520 unsigned lds_alloc;
521 };
522
523 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
524 struct r600_command_buffer *cb)
525 {
526 assert(cs->cdw + cb->num_dw <= cs->max_dw);
527 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
528 cs->cdw += cb->num_dw;
529 }
530
531 static inline void r600_set_atom_dirty(struct r600_context *rctx,
532 struct r600_atom *atom,
533 bool dirty)
534 {
535 uint64_t mask;
536
537 assert(atom->id != 0);
538 assert(atom->id < sizeof(mask) * 8);
539 mask = 1ull << atom->id;
540 if (dirty)
541 rctx->dirty_atoms |= mask;
542 else
543 rctx->dirty_atoms &= ~mask;
544 }
545
546 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
547 struct r600_atom *atom)
548 {
549 r600_set_atom_dirty(rctx, atom, true);
550 }
551
552 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
553 {
554 atom->emit(&rctx->b, atom);
555 r600_set_atom_dirty(rctx, atom, false);
556 }
557
558 static inline void r600_set_cso_state(struct r600_context *rctx,
559 struct r600_cso_state *state, void *cso)
560 {
561 state->cso = cso;
562 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
563 }
564
565 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
566 struct r600_cso_state *state, void *cso,
567 struct r600_command_buffer *cb)
568 {
569 state->cb = cb;
570 state->atom.num_dw = cb ? cb->num_dw : 0;
571 r600_set_cso_state(rctx, state, cso);
572 }
573
574 /* compute_memory_pool.c */
575 struct compute_memory_pool;
576 void compute_memory_pool_delete(struct compute_memory_pool* pool);
577 struct compute_memory_pool* compute_memory_pool_new(
578 struct r600_screen *rscreen);
579
580 /* evergreen_state.c */
581 struct pipe_sampler_view *
582 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
583 struct pipe_resource *texture,
584 const struct pipe_sampler_view *state,
585 unsigned width0, unsigned height0,
586 unsigned force_level);
587 void evergreen_init_common_regs(struct r600_context *ctx,
588 struct r600_command_buffer *cb,
589 enum chip_class ctx_chip_class,
590 enum radeon_family ctx_family,
591 int ctx_drm_minor);
592 void cayman_init_common_regs(struct r600_command_buffer *cb,
593 enum chip_class ctx_chip_class,
594 enum radeon_family ctx_family,
595 int ctx_drm_minor);
596
597 void evergreen_init_state_functions(struct r600_context *rctx);
598 void evergreen_init_atom_start_cs(struct r600_context *rctx);
599 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
600 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
601 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
602 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
603 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
604 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
605 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
606 void *evergreen_create_resolve_blend(struct r600_context *rctx);
607 void *evergreen_create_decompress_blend(struct r600_context *rctx);
608 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
609 boolean evergreen_is_format_supported(struct pipe_screen *screen,
610 enum pipe_format format,
611 enum pipe_texture_target target,
612 unsigned sample_count,
613 unsigned usage);
614 void evergreen_init_color_surface(struct r600_context *rctx,
615 struct r600_surface *surf);
616 void evergreen_init_color_surface_rat(struct r600_context *rctx,
617 struct r600_surface *surf);
618 void evergreen_update_db_shader_control(struct r600_context * rctx);
619 bool evergreen_adjust_gprs(struct r600_context *rctx);
620 /* r600_blit.c */
621 void r600_init_blit_functions(struct r600_context *rctx);
622 void r600_decompress_depth_textures(struct r600_context *rctx,
623 struct r600_samplerview_state *textures);
624 void r600_decompress_color_textures(struct r600_context *rctx,
625 struct r600_samplerview_state *textures);
626 void r600_resource_copy_region(struct pipe_context *ctx,
627 struct pipe_resource *dst,
628 unsigned dst_level,
629 unsigned dstx, unsigned dsty, unsigned dstz,
630 struct pipe_resource *src,
631 unsigned src_level,
632 const struct pipe_box *src_box);
633
634 /* r600_shader.c */
635 int r600_pipe_shader_create(struct pipe_context *ctx,
636 struct r600_pipe_shader *shader,
637 union r600_shader_key key);
638
639 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
640
641 /* r600_state.c */
642 struct pipe_sampler_view *
643 r600_create_sampler_view_custom(struct pipe_context *ctx,
644 struct pipe_resource *texture,
645 const struct pipe_sampler_view *state,
646 unsigned width_first_level, unsigned height_first_level);
647 void r600_init_state_functions(struct r600_context *rctx);
648 void r600_init_atom_start_cs(struct r600_context *rctx);
649 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
650 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
651 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
652 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
653 void *r600_create_db_flush_dsa(struct r600_context *rctx);
654 void *r600_create_resolve_blend(struct r600_context *rctx);
655 void *r700_create_resolve_blend(struct r600_context *rctx);
656 void *r600_create_decompress_blend(struct r600_context *rctx);
657 bool r600_adjust_gprs(struct r600_context *rctx);
658 boolean r600_is_format_supported(struct pipe_screen *screen,
659 enum pipe_format format,
660 enum pipe_texture_target target,
661 unsigned sample_count,
662 unsigned usage);
663 void r600_update_db_shader_control(struct r600_context * rctx);
664
665 /* r600_hw_context.c */
666 void r600_context_gfx_flush(void *context, unsigned flags,
667 struct pipe_fence_handle **fence);
668 void r600_begin_new_cs(struct r600_context *ctx);
669 void r600_flush_emit(struct r600_context *ctx);
670 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
671 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
672 struct pipe_resource *dst, uint64_t dst_offset,
673 struct pipe_resource *src, uint64_t src_offset,
674 unsigned size);
675 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
676 struct pipe_resource *dst, uint64_t offset,
677 unsigned size, uint32_t clear_value);
678 void r600_dma_copy_buffer(struct r600_context *rctx,
679 struct pipe_resource *dst,
680 struct pipe_resource *src,
681 uint64_t dst_offset,
682 uint64_t src_offset,
683 uint64_t size);
684
685 /*
686 * evergreen_hw_context.c
687 */
688 void evergreen_dma_copy_buffer(struct r600_context *rctx,
689 struct pipe_resource *dst,
690 struct pipe_resource *src,
691 uint64_t dst_offset,
692 uint64_t src_offset,
693 uint64_t size);
694 void evergreen_setup_tess_constants(struct r600_context *rctx,
695 const struct pipe_draw_info *info,
696 unsigned *num_patches);
697 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
698 const struct pipe_draw_info *info,
699 unsigned num_patches);
700 void evergreen_set_ls_hs_config(struct r600_context *rctx,
701 struct radeon_winsys_cs *cs,
702 uint32_t ls_hs_config);
703 void evergreen_set_lds_alloc(struct r600_context *rctx,
704 struct radeon_winsys_cs *cs,
705 uint32_t lds_alloc);
706
707 /* r600_state_common.c */
708 void r600_init_common_state_functions(struct r600_context *rctx);
709 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
710 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
711 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
712 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
713 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
714 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
715 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
716 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
717 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
718 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
719 unsigned num_dw);
720 void r600_vertex_buffers_dirty(struct r600_context *rctx);
721 void r600_sampler_views_dirty(struct r600_context *rctx,
722 struct r600_samplerview_state *state);
723 void r600_sampler_states_dirty(struct r600_context *rctx,
724 struct r600_sampler_states *state);
725 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
726 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
727 uint32_t r600_translate_stencil_op(int s_op);
728 uint32_t r600_translate_fill(uint32_t func);
729 unsigned r600_tex_wrap(unsigned wrap);
730 unsigned r600_tex_mipfilter(unsigned filter);
731 unsigned r600_tex_compare(unsigned compare);
732 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
733 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
734 struct pipe_resource *texture,
735 const struct pipe_surface *templ,
736 unsigned width, unsigned height);
737 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
738 const unsigned char *swizzle_view,
739 boolean vtx);
740 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
741 const unsigned char *swizzle_view,
742 uint32_t *word4_p, uint32_t *yuv_format_p);
743 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
744 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
745
746 /* r600_uvd.c */
747 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
748 const struct pipe_video_codec *decoder);
749
750 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
751 const struct pipe_video_buffer *tmpl);
752
753 /*
754 * Helpers for building command buffers
755 */
756
757 #define PKT3_SET_CONFIG_REG 0x68
758 #define PKT3_SET_CONTEXT_REG 0x69
759 #define PKT3_SET_CTL_CONST 0x6F
760 #define PKT3_SET_LOOP_CONST 0x6C
761
762 #define R600_CONFIG_REG_OFFSET 0x08000
763 #define R600_CONTEXT_REG_OFFSET 0x28000
764 #define R600_CTL_CONST_OFFSET 0x3CFF0
765 #define R600_LOOP_CONST_OFFSET 0X0003E200
766 #define EG_LOOP_CONST_OFFSET 0x0003A200
767
768 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
769 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
770 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
771 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
772 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
773
774 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
775
776 /*Evergreen Compute packet3*/
777 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
778
779 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
780 {
781 cb->buf[cb->num_dw++] = value;
782 }
783
784 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
785 {
786 assert(cb->num_dw+num <= cb->max_num_dw);
787 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
788 cb->num_dw += num;
789 }
790
791 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
792 {
793 assert(reg < R600_CONTEXT_REG_OFFSET);
794 assert(cb->num_dw+2+num <= cb->max_num_dw);
795 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
796 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
797 }
798
799 /**
800 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
801 * shaders.
802 */
803 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
804 {
805 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
806 assert(cb->num_dw+2+num <= cb->max_num_dw);
807 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
808 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
809 }
810
811 /**
812 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
813 * shaders.
814 */
815 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
816 {
817 assert(reg >= R600_CTL_CONST_OFFSET);
818 assert(cb->num_dw+2+num <= cb->max_num_dw);
819 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
820 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
821 }
822
823 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
824 {
825 assert(reg >= R600_LOOP_CONST_OFFSET);
826 assert(cb->num_dw+2+num <= cb->max_num_dw);
827 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
828 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
829 }
830
831 /**
832 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
833 * shaders.
834 */
835 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
836 {
837 assert(reg >= EG_LOOP_CONST_OFFSET);
838 assert(cb->num_dw+2+num <= cb->max_num_dw);
839 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
840 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
841 }
842
843 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
844 {
845 r600_store_config_reg_seq(cb, reg, 1);
846 r600_store_value(cb, value);
847 }
848
849 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
850 {
851 r600_store_context_reg_seq(cb, reg, 1);
852 r600_store_value(cb, value);
853 }
854
855 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
856 {
857 r600_store_ctl_const_seq(cb, reg, 1);
858 r600_store_value(cb, value);
859 }
860
861 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
862 {
863 r600_store_loop_const_seq(cb, reg, 1);
864 r600_store_value(cb, value);
865 }
866
867 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
868 {
869 eg_store_loop_const_seq(cb, reg, 1);
870 r600_store_value(cb, value);
871 }
872
873 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
874 void r600_release_command_buffer(struct r600_command_buffer *cb);
875
876 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
877 {
878 radeon_set_context_reg_seq(cs, reg, num);
879 /* Set the compute bit on the packet header */
880 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
881 }
882
883 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
884 {
885 assert(reg >= R600_CTL_CONST_OFFSET);
886 assert(cs->cdw+2+num <= cs->max_dw);
887 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
888 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
889 }
890
891 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
892 {
893 radeon_compute_set_context_reg_seq(cs, reg, 1);
894 radeon_emit(cs, value);
895 }
896
897 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
898 {
899 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
900 radeon_compute_set_context_reg(cs, reg, value);
901 } else {
902 radeon_set_context_reg(cs, reg, value);
903 }
904 }
905
906 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
907 {
908 radeon_set_ctl_const_seq(cs, reg, 1);
909 radeon_emit(cs, value);
910 }
911
912 /*
913 * common helpers
914 */
915 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
916 {
917 return value * (1 << frac_bits);
918 }
919
920 /* 12.4 fixed-point */
921 static inline unsigned r600_pack_float_12p4(float x)
922 {
923 return x <= 0 ? 0 :
924 x >= 4096 ? 0xffff : x * 16;
925 }
926
927 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
928 static inline bool r600_can_read_depth(struct r600_texture *rtex)
929 {
930 return rtex->resource.b.b.nr_samples <= 1 &&
931 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
932 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
933 }
934
935 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
936 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
937 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
938
939 unsigned r600_conv_prim_to_gs_out(unsigned mode);
940 #endif