2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
31 #include "util/u_suballoc.h"
33 #include "r600_llvm.h"
34 #include "r600_public.h"
35 #include "r600_resource.h"
37 #define R600_NUM_ATOMS 38
39 #define R600_TRACE_CS 0
41 #define R600_MAX_USER_CONST_BUFFERS 13
42 #define R600_MAX_DRIVER_CONST_BUFFERS 3
43 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
45 /* start driver buffers after user buffers */
46 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
47 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
48 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
50 #define R600_MAX_CONST_BUFFER_SIZE 4096
52 #ifdef PIPE_ARCH_BIG_ENDIAN
53 #define R600_BIG_ENDIAN 1
55 #define R600_BIG_ENDIAN 0
58 #define R600_MAP_BUFFER_ALIGNMENT 64
61 struct r600_shader_key
;
63 /* This encapsulates a state or an operation which can emitted into the GPU
64 * command stream. It's not limited to states only, it can be used for anything
65 * that wants to write commands into the CS (e.g. cache flushes). */
67 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
73 /* This is an atom containing GPU commands that never change.
74 * This is supposed to be copied directly into the CS. */
75 struct r600_command_buffer
{
82 struct r600_db_state
{
83 struct r600_atom atom
;
84 struct r600_surface
*rsurf
;
87 struct r600_db_misc_state
{
88 struct r600_atom atom
;
89 bool occlusion_query_enabled
;
90 bool flush_depthstencil_through_cb
;
91 bool flush_depthstencil_in_place
;
92 bool copy_depth
, copy_stencil
;
95 unsigned db_shader_control
;
99 struct r600_cb_misc_state
{
100 struct r600_atom atom
;
101 unsigned cb_color_control
; /* this comes from blend state */
102 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
104 unsigned nr_ps_color_outputs
;
109 struct r600_clip_misc_state
{
110 struct r600_atom atom
;
111 unsigned pa_cl_clip_cntl
; /* from rasterizer */
112 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
113 unsigned clip_plane_enable
; /* from rasterizer */
114 unsigned clip_dist_write
; /* from vertex shader */
117 struct r600_alphatest_state
{
118 struct r600_atom atom
;
119 unsigned sx_alpha_test_control
; /* this comes from dsa state */
120 unsigned sx_alpha_ref
; /* this comes from dsa state */
122 bool cb0_export_16bpc
; /* from set_framebuffer_state */
125 struct r600_vgt_state
{
126 struct r600_atom atom
;
127 uint32_t vgt_multi_prim_ib_reset_en
;
128 uint32_t vgt_multi_prim_ib_reset_indx
;
129 uint32_t vgt_indx_offset
;
132 struct r600_blend_color
{
133 struct r600_atom atom
;
134 struct pipe_blend_color state
;
137 struct r600_clip_state
{
138 struct r600_atom atom
;
139 struct pipe_clip_state state
;
142 struct r600_cs_shader_state
{
143 struct r600_atom atom
;
144 unsigned kernel_index
;
145 struct r600_pipe_compute
*shader
;
148 struct r600_framebuffer
{
149 struct r600_atom atom
;
150 struct pipe_framebuffer_state state
;
151 unsigned compressed_cb_mask
;
155 bool is_msaa_resolve
;
158 struct r600_sample_mask
{
159 struct r600_atom atom
;
160 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
163 struct r600_config_state
{
164 struct r600_atom atom
;
165 unsigned sq_gpr_resource_mgmt_1
;
168 struct r600_stencil_ref
175 struct r600_stencil_ref_state
{
176 struct r600_atom atom
;
177 struct r600_stencil_ref state
;
178 struct pipe_stencil_ref pipe_state
;
181 struct r600_viewport_state
{
182 struct r600_atom atom
;
183 struct pipe_viewport_state state
;
186 struct compute_memory_pool
;
187 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
188 struct compute_memory_pool
* compute_memory_pool_new(
189 struct r600_screen
*rscreen
);
191 struct r600_pipe_fences
{
192 struct r600_resource
*bo
;
195 /* linked list of preallocated blocks */
196 struct list_head blocks
;
197 /* linked list of freed fences */
198 struct list_head pool
;
202 enum r600_msaa_texture_mode
{
203 /* If the hw can fetch the first sample only (no decompression available).
204 * This means MSAA texturing is not fully implemented. */
205 MSAA_TEXTURE_SAMPLE_ZERO
,
207 /* If the hw can fetch decompressed MSAA textures.
208 * Supported families: R600, R700, Evergreen.
209 * Cayman cannot use this, because it cannot do the decompression. */
210 MSAA_TEXTURE_DECOMPRESSED
,
212 /* If the hw can fetch compressed MSAA textures, which means shaders can
213 * read resolved FMASK. This yields the best performance.
214 * Supported families: Evergreen, Cayman. */
215 MSAA_TEXTURE_COMPRESSED
218 typedef boolean (*r600g_dma_blit_t
)(struct pipe_context
*ctx
,
219 struct pipe_resource
*dst
,
221 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
222 struct pipe_resource
*src
,
224 const struct pipe_box
*src_box
);
227 #define DBG_TEX_DEPTH (1 << 0)
228 #define DBG_COMPUTE (1 << 1)
230 #define DBG_FS (1 << 8)
231 #define DBG_VS (1 << 9)
232 #define DBG_GS (1 << 10)
233 #define DBG_PS (1 << 11)
234 #define DBG_CS (1 << 12)
236 #define DBG_NO_HYPERZ (1 << 16)
237 #define DBG_NO_LLVM (1 << 17)
240 struct pipe_screen screen
;
241 struct radeon_winsys
*ws
;
242 unsigned debug_flags
;
244 enum chip_class chip_class
;
245 struct radeon_info info
;
249 enum r600_msaa_texture_mode msaa_texture_support
;
250 struct r600_tiling_info tiling_info
;
251 struct r600_pipe_fences fences
;
253 /*for compute global memory binding, we allocate stuff here, instead of
255 * XXX: Not sure if this is the best place for global_pool. Also,
256 * it's not thread safe, so it won't work with multiple contexts. */
257 struct compute_memory_pool
*global_pool
;
259 struct r600_resource
*trace_bo
;
263 r600g_dma_blit_t dma_blit
;
266 struct r600_pipe_sampler_view
{
267 struct pipe_sampler_view base
;
268 struct r600_resource
*tex_resource
;
269 uint32_t tex_resource_words
[8];
270 bool skip_mip_address_reloc
;
273 struct r600_rasterizer_state
{
274 struct r600_command_buffer buffer
;
277 unsigned sprite_coord_enable
;
278 unsigned clip_plane_enable
;
279 unsigned pa_sc_line_stipple
;
280 unsigned pa_cl_clip_cntl
;
285 bool multisample_enable
;
288 struct r600_poly_offset_state
{
289 struct r600_atom atom
;
290 enum pipe_format zs_format
;
295 struct r600_blend_state
{
296 struct r600_command_buffer buffer
;
297 struct r600_command_buffer buffer_no_blend
;
298 unsigned cb_target_mask
;
299 unsigned cb_color_control
;
300 unsigned cb_color_control_no_blend
;
305 struct r600_dsa_state
{
306 struct r600_command_buffer buffer
;
311 unsigned sx_alpha_test_control
;
314 struct r600_pipe_shader
;
316 struct r600_pipe_shader_selector
{
317 struct r600_pipe_shader
*current
;
319 struct tgsi_token
*tokens
;
320 struct pipe_stream_output_info so
;
322 unsigned num_shaders
;
324 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
327 unsigned nr_ps_max_color_exports
;
330 struct r600_pipe_sampler_state
{
331 uint32_t tex_sampler_words
[3];
332 union pipe_color_union border_color
;
333 bool border_color_use
;
334 bool seamless_cube_map
;
337 /* needed for blitter save */
338 #define NUM_TEX_UNITS 16
340 struct r600_seamless_cube_map
{
341 struct r600_atom atom
;
345 struct r600_samplerview_state
{
346 struct r600_atom atom
;
347 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
348 uint32_t enabled_mask
;
350 uint32_t compressed_depthtex_mask
; /* which textures are depth */
351 uint32_t compressed_colortex_mask
;
352 boolean dirty_txq_constants
;
353 boolean dirty_buffer_constants
;
356 struct r600_sampler_states
{
357 struct r600_atom atom
;
358 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
359 uint32_t enabled_mask
;
361 uint32_t has_bordercolor_mask
; /* which states contain the border color */
364 struct r600_textures_info
{
365 struct r600_samplerview_state views
;
366 struct r600_sampler_states states
;
367 bool is_array_sampler
[NUM_TEX_UNITS
];
369 /* cube array txq workaround */
370 uint32_t *txq_constants
;
371 /* buffer related workarounds */
372 uint32_t *buffer_constants
;
376 struct pipe_reference reference
;
377 unsigned index
; /* in the shared bo */
378 struct r600_resource
*sleep_bo
;
379 struct list_head head
;
382 #define FENCE_BLOCK_SIZE 16
384 struct r600_fence_block
{
385 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
386 struct list_head head
;
389 #define R600_CONSTANT_ARRAY_SIZE 256
390 #define R600_RESOURCE_ARRAY_SIZE 160
392 struct r600_constbuf_state
394 struct r600_atom atom
;
395 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
396 uint32_t enabled_mask
;
400 struct r600_vertexbuf_state
402 struct r600_atom atom
;
403 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
404 uint32_t enabled_mask
; /* non-NULL buffers */
408 /* CSO (constant state object, in other words, immutable state). */
409 struct r600_cso_state
411 struct r600_atom atom
;
412 void *cso
; /* e.g. r600_blend_state */
413 struct r600_command_buffer
*cb
;
416 struct r600_scissor_state
418 struct r600_atom atom
;
419 struct pipe_scissor_state scissor
;
420 bool enable
; /* r6xx only */
423 struct r600_fetch_shader
{
424 struct r600_resource
*buffer
;
428 struct r600_streamout
{
429 struct r600_atom begin_atom
;
431 unsigned num_dw_for_end
;
433 unsigned enabled_mask
;
434 unsigned num_targets
;
435 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
437 unsigned append_bitmask
;
442 struct radeon_winsys_cs
*cs
;
444 void (*flush
)(void *ctx
, unsigned flags
);
448 struct r600_ring gfx
;
449 struct r600_ring dma
;
452 struct r600_context
{
453 struct pipe_context context
;
454 struct r600_screen
*screen
;
455 struct radeon_winsys
*ws
;
456 struct r600_rings rings
;
457 struct blitter_context
*blitter
;
458 struct u_upload_mgr
*uploader
;
459 struct u_suballocator
*allocator_so_filled_size
;
460 struct u_suballocator
*allocator_fetch_shader
;
461 struct util_slab_mempool pool_transfers
;
464 enum radeon_family family
;
465 enum chip_class chip_class
;
466 boolean has_vertex_cache
;
467 boolean keep_tiling_flags
;
468 unsigned default_ps_gprs
, default_vs_gprs
;
469 unsigned r6xx_num_clause_temp_gprs
;
470 unsigned backend_mask
;
471 unsigned max_db
; /* for OQ */
473 /* current unaccounted memory usage */
477 /* Miscellaneous state objects. */
478 void *custom_dsa_flush
;
479 void *custom_blend_resolve
;
480 void *custom_blend_decompress
;
481 void *custom_blend_fmask_decompress
;
482 /* With rasterizer discard, there doesn't have to be a pixel shader.
483 * In that case, we bind this one: */
484 void *dummy_pixel_shader
;
485 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
486 * bug where valid CMASK and FMASK are required to be present to avoid
487 * a hardlock in certain operations but aren't actually used
488 * for anything useful. */
489 struct r600_resource
*dummy_fmask
;
490 struct r600_resource
*dummy_cmask
;
492 /* State binding slots are here. */
493 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
494 /* States for CS initialization. */
495 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
496 /** Compute specific registers initializations. The start_cs_cmd atom
497 * must be emitted before start_compute_cs_cmd. */
498 struct r600_command_buffer start_compute_cs_cmd
;
499 /* Register states. */
500 struct r600_alphatest_state alphatest_state
;
501 struct r600_cso_state blend_state
;
502 struct r600_blend_color blend_color
;
503 struct r600_cb_misc_state cb_misc_state
;
504 struct r600_clip_misc_state clip_misc_state
;
505 struct r600_clip_state clip_state
;
506 struct r600_db_misc_state db_misc_state
;
507 struct r600_db_state db_state
;
508 struct r600_cso_state dsa_state
;
509 struct r600_framebuffer framebuffer
;
510 struct r600_poly_offset_state poly_offset_state
;
511 struct r600_cso_state rasterizer_state
;
512 struct r600_sample_mask sample_mask
;
513 struct r600_scissor_state scissor
;
514 struct r600_seamless_cube_map seamless_cube_map
;
515 struct r600_config_state config_state
;
516 struct r600_stencil_ref_state stencil_ref
;
517 struct r600_vgt_state vgt_state
;
518 struct r600_viewport_state viewport
;
519 /* Shaders and shader resources. */
520 struct r600_cso_state vertex_fetch_shader
;
521 struct r600_cs_shader_state cs_shader_state
;
522 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
523 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
524 /** Vertex buffers for fetch shaders */
525 struct r600_vertexbuf_state vertex_buffer_state
;
526 /** Vertex buffers for compute shaders */
527 struct r600_vertexbuf_state cs_vertex_buffer_state
;
528 struct r600_streamout streamout
;
530 /* Additional context states. */
532 unsigned compute_cb_target_mask
;
533 struct r600_pipe_shader_selector
*ps_shader
;
534 struct r600_pipe_shader_selector
*vs_shader
;
535 struct r600_rasterizer_state
*rasterizer
;
537 bool force_blend_disable
;
538 boolean dual_src_blend
;
542 struct pipe_index_buffer index_buffer
;
544 /* Last draw state (-1 = unset). */
545 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
546 int last_start_instance
;
549 /* The list of active queries. Only one query of each type can be active. */
550 int num_occlusion_queries
;
551 /* Keep track of non-timer queries, because they should be suspended
552 * during context flushing.
553 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
554 struct list_head active_nontimer_queries
;
555 unsigned num_cs_dw_nontimer_queries_suspend
;
556 /* If queries have been suspended. */
557 bool nontimer_queries_suspended
;
559 /* Render condition. */
560 struct pipe_query
*current_render_cond
;
561 unsigned current_render_cond_mode
;
562 boolean predicate_drawing
;
564 /* Deprecated state management. */
565 struct r600_range
*range
;
567 struct r600_block
**blocks
;
568 struct list_head dirty
;
569 struct list_head enable_list
;
570 unsigned pm4_dirty_cdwords
;
572 struct r600_isa
*isa
;
575 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
576 struct r600_command_buffer
*cb
)
578 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
579 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
580 cs
->cdw
+= cb
->num_dw
;
584 void r600_trace_emit(struct r600_context
*rctx
);
587 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
589 atom
->emit(rctx
, atom
);
592 if (rctx
->screen
->trace_bo
) {
593 r600_trace_emit(rctx
);
598 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
601 state
->atom
.dirty
= cso
!= NULL
;
604 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
605 struct r600_command_buffer
*cb
)
608 state
->atom
.num_dw
= cb
->num_dw
;
609 r600_set_cso_state(state
, cso
);
612 /* evergreen_state.c */
613 struct pipe_sampler_view
*
614 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
615 struct pipe_resource
*texture
,
616 const struct pipe_sampler_view
*state
,
617 unsigned width0
, unsigned height0
);
618 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
619 enum chip_class ctx_chip_class
,
620 enum radeon_family ctx_family
,
622 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
623 enum chip_class ctx_chip_class
,
624 enum radeon_family ctx_family
,
627 void evergreen_init_state_functions(struct r600_context
*rctx
);
628 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
629 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
630 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
631 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
632 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
633 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
634 void *evergreen_create_fmask_decompress_blend(struct r600_context
*rctx
);
635 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
636 enum pipe_format format
,
637 enum pipe_texture_target target
,
638 unsigned sample_count
,
640 void evergreen_init_color_surface(struct r600_context
*rctx
,
641 struct r600_surface
*surf
);
642 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
643 struct r600_surface
*surf
);
644 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
647 void r600_copy_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dstx
,
648 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
649 void r600_init_blit_functions(struct r600_context
*rctx
);
650 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
651 struct r600_texture
*texture
,
652 struct r600_texture
*staging
,
653 unsigned first_level
, unsigned last_level
,
654 unsigned first_layer
, unsigned last_layer
,
655 unsigned first_sample
, unsigned last_sample
);
656 void r600_decompress_depth_textures(struct r600_context
*rctx
,
657 struct r600_samplerview_state
*textures
);
658 void r600_decompress_color_textures(struct r600_context
*rctx
,
659 struct r600_samplerview_state
*textures
);
662 bool r600_init_resource(struct r600_screen
*rscreen
,
663 struct r600_resource
*res
,
664 unsigned size
, unsigned alignment
,
665 bool use_reusable_pool
, unsigned usage
);
666 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
667 const struct pipe_resource
*templ
,
671 boolean
r600_rings_is_buffer_referenced(struct r600_context
*ctx
,
672 struct radeon_winsys_cs_handle
*buf
,
673 enum radeon_bo_usage usage
);
674 void *r600_buffer_mmap_sync_with_rings(struct r600_context
*ctx
,
675 struct r600_resource
*resource
,
679 void r600_init_query_functions(struct r600_context
*rctx
);
680 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
681 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
683 /* r600_resource.c */
684 void r600_init_context_resource_functions(struct r600_context
*r600
);
687 int r600_pipe_shader_create(struct pipe_context
*ctx
,
688 struct r600_pipe_shader
*shader
,
689 struct r600_shader_key key
);
691 int r600_compute_shader_create(struct pipe_context
* ctx
,
692 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
694 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
697 struct pipe_sampler_view
*
698 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
699 struct pipe_resource
*texture
,
700 const struct pipe_sampler_view
*state
,
701 unsigned width_first_level
, unsigned height_first_level
);
702 void r600_init_state_functions(struct r600_context
*rctx
);
703 void r600_init_atom_start_cs(struct r600_context
*rctx
);
704 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
705 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
706 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
707 void *r600_create_resolve_blend(struct r600_context
*rctx
);
708 void *r700_create_resolve_blend(struct r600_context
*rctx
);
709 void *r600_create_decompress_blend(struct r600_context
*rctx
);
710 bool r600_adjust_gprs(struct r600_context
*rctx
);
711 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
712 enum pipe_format format
,
713 enum pipe_texture_target target
,
714 unsigned sample_count
,
716 void r600_update_db_shader_control(struct r600_context
* rctx
);
719 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
720 void r600_init_surface_functions(struct r600_context
*r600
);
721 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
722 const unsigned char *swizzle_view
,
723 uint32_t *word4_p
, uint32_t *yuv_format_p
);
724 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
725 unsigned level
, unsigned layer
);
726 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
727 struct pipe_resource
*texture
,
728 const struct pipe_surface
*templ
,
729 unsigned width
, unsigned height
);
731 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
732 const unsigned char *swizzle_view
,
735 /* r600_hw_context.c */
736 void r600_emit_streamout_begin(struct r600_context
*ctx
, struct r600_atom
*atom
);
737 void r600_emit_streamout_end(struct r600_context
*ctx
);
739 /* r600_state_common.c */
740 void r600_init_common_state_functions(struct r600_context
*rctx
);
741 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
742 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
743 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
744 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
745 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
746 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
747 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
748 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
749 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
751 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
752 void r600_sampler_views_dirty(struct r600_context
*rctx
,
753 struct r600_samplerview_state
*state
);
754 void r600_sampler_states_dirty(struct r600_context
*rctx
,
755 struct r600_sampler_states
*state
);
756 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
757 void r600_streamout_buffers_dirty(struct r600_context
*rctx
);
758 void r600_draw_rectangle(struct blitter_context
*blitter
,
759 int x1
, int y1
, int x2
, int y2
, float depth
,
760 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
761 uint32_t r600_translate_stencil_op(int s_op
);
762 uint32_t r600_translate_fill(uint32_t func
);
763 unsigned r600_tex_wrap(unsigned wrap
);
764 unsigned r600_tex_filter(unsigned filter
);
765 unsigned r600_tex_mipfilter(unsigned filter
);
766 unsigned r600_tex_compare(unsigned compare
);
767 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
770 * Helpers for building command buffers
773 #define PKT3_SET_CONFIG_REG 0x68
774 #define PKT3_SET_CONTEXT_REG 0x69
775 #define PKT3_SET_CTL_CONST 0x6F
776 #define PKT3_SET_LOOP_CONST 0x6C
778 #define R600_CONFIG_REG_OFFSET 0x08000
779 #define R600_CONTEXT_REG_OFFSET 0x28000
780 #define R600_CTL_CONST_OFFSET 0x3CFF0
781 #define R600_LOOP_CONST_OFFSET 0X0003E200
782 #define EG_LOOP_CONST_OFFSET 0x0003A200
784 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
785 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
786 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
787 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
788 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
790 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
792 /*Evergreen Compute packet3*/
793 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
795 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
797 cb
->buf
[cb
->num_dw
++] = value
;
800 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
802 assert(reg
< R600_CONTEXT_REG_OFFSET
);
803 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
804 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
805 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
809 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
812 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
814 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
815 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
816 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
817 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
821 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
824 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
826 assert(reg
>= R600_CTL_CONST_OFFSET
);
827 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
828 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
829 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
832 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
834 assert(reg
>= R600_LOOP_CONST_OFFSET
);
835 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
836 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
837 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
841 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
844 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
846 assert(reg
>= EG_LOOP_CONST_OFFSET
);
847 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
848 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
849 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
852 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
854 r600_store_config_reg_seq(cb
, reg
, 1);
855 r600_store_value(cb
, value
);
858 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
860 r600_store_context_reg_seq(cb
, reg
, 1);
861 r600_store_value(cb
, value
);
864 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
866 r600_store_ctl_const_seq(cb
, reg
, 1);
867 r600_store_value(cb
, value
);
870 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
872 r600_store_loop_const_seq(cb
, reg
, 1);
873 r600_store_value(cb
, value
);
876 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
878 eg_store_loop_const_seq(cb
, reg
, 1);
879 r600_store_value(cb
, value
);
882 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
883 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
886 * Helpers for emitting state into a command stream directly.
888 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
,
889 struct r600_ring
*ring
,
890 struct r600_resource
*rbo
,
891 enum radeon_bo_usage usage
)
894 /* make sure that all previous ring use are flushed so everything
895 * look serialized from driver pov
897 if (!ring
->flushing
) {
898 if (ring
== &ctx
->rings
.gfx
) {
899 if (ctx
->rings
.dma
.cs
) {
901 ctx
->rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
);
905 ctx
->rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
);
908 return ctx
->ws
->cs_add_reloc(ring
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
911 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
913 cs
->buf
[cs
->cdw
++] = value
;
916 static INLINE
void r600_write_array(struct radeon_winsys_cs
*cs
, unsigned num
, unsigned *ptr
)
918 assert(cs
->cdw
+num
<= RADEON_MAX_CMDBUF_DWORDS
);
919 memcpy(&cs
->buf
[cs
->cdw
], ptr
, num
* sizeof(ptr
[0]));
923 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
925 assert(reg
< R600_CONTEXT_REG_OFFSET
);
926 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
927 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
928 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
931 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
933 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
934 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
935 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
936 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
939 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
941 r600_write_context_reg_seq(cs
, reg
, num
);
942 /* Set the compute bit on the packet header */
943 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
946 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
948 assert(reg
>= R600_CTL_CONST_OFFSET
);
949 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
950 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
951 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
954 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
956 r600_write_config_reg_seq(cs
, reg
, 1);
957 r600_write_value(cs
, value
);
960 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
962 r600_write_context_reg_seq(cs
, reg
, 1);
963 r600_write_value(cs
, value
);
966 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
968 r600_write_compute_context_reg_seq(cs
, reg
, 1);
969 r600_write_value(cs
, value
);
972 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
974 r600_write_ctl_const_seq(cs
, reg
, 1);
975 r600_write_value(cs
, value
);
981 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
983 return value
* (1 << frac_bits
);
985 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
987 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
989 if (filter
<= 1) return 0;
990 if (filter
<= 2) return 1;
991 if (filter
<= 4) return 2;
992 if (filter
<= 8) return 3;
996 /* 12.4 fixed-point */
997 static INLINE
unsigned r600_pack_float_12p4(float x
)
1000 x
>= 4096 ? 0xffff : x
* 16;
1003 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
1005 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1006 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
1008 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);
1011 static INLINE
void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
1013 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1014 struct r600_resource
*rr
= (struct r600_resource
*)r
;
1021 * The idea is to compute a gross estimate of memory requirement of
1022 * each draw call. After each draw call, memory will be precisely
1023 * accounted. So the uncertainty is only on the current draw call.
1024 * In practice this gave very good estimate (+/- 10% of the target
1027 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
1028 rctx
->gtt
+= rr
->buf
->size
;
1030 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
1031 rctx
->vram
+= rr
->buf
->size
;