2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../radeon/r600_pipe_common.h"
30 #include "../radeon/r600_cs.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34 #include "r600_resource.h"
36 #include "util/u_blitter.h"
37 #include "util/u_slab.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_double_list.h"
40 #include "util/u_transfer.h"
42 #define R600_NUM_ATOMS 41
44 /* the number of CS dwords for flushing and drawing */
45 #define R600_MAX_FLUSH_CS_DWORDS 16
46 #define R600_MAX_DRAW_CS_DWORDS 34
47 #define R600_TRACE_CS_DWORDS 7
49 #define R600_MAX_USER_CONST_BUFFERS 13
50 #define R600_MAX_DRIVER_CONST_BUFFERS 3
51 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
53 /* start driver buffers after user buffers */
54 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
55 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
56 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
58 #define R600_MAX_CONST_BUFFER_SIZE 4096
60 #ifdef PIPE_ARCH_BIG_ENDIAN
61 #define R600_BIG_ENDIAN 1
63 #define R600_BIG_ENDIAN 0
66 #define R600_MAP_BUFFER_ALIGNMENT 64
68 #define R600_ERR(fmt, args...) \
69 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
71 #define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
72 #define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
73 #define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
74 #define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
78 struct r600_shader_key
;
80 /* This is an atom containing GPU commands that never change.
81 * This is supposed to be copied directly into the CS. */
82 struct r600_command_buffer
{
89 struct r600_db_state
{
90 struct r600_atom atom
;
91 struct r600_surface
*rsurf
;
94 struct r600_db_misc_state
{
95 struct r600_atom atom
;
96 bool occlusion_query_enabled
;
97 bool flush_depthstencil_through_cb
;
98 bool flush_depthstencil_in_place
;
99 bool copy_depth
, copy_stencil
;
100 unsigned copy_sample
;
101 unsigned log_samples
;
102 unsigned db_shader_control
;
106 struct r600_cb_misc_state
{
107 struct r600_atom atom
;
108 unsigned cb_color_control
; /* this comes from blend state */
109 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
111 unsigned nr_ps_color_outputs
;
116 struct r600_clip_misc_state
{
117 struct r600_atom atom
;
118 unsigned pa_cl_clip_cntl
; /* from rasterizer */
119 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
120 unsigned clip_plane_enable
; /* from rasterizer */
121 unsigned clip_dist_write
; /* from vertex shader */
124 struct r600_alphatest_state
{
125 struct r600_atom atom
;
126 unsigned sx_alpha_test_control
; /* this comes from dsa state */
127 unsigned sx_alpha_ref
; /* this comes from dsa state */
129 bool cb0_export_16bpc
; /* from set_framebuffer_state */
132 struct r600_vgt_state
{
133 struct r600_atom atom
;
134 uint32_t vgt_multi_prim_ib_reset_en
;
135 uint32_t vgt_multi_prim_ib_reset_indx
;
136 uint32_t vgt_indx_offset
;
139 struct r600_blend_color
{
140 struct r600_atom atom
;
141 struct pipe_blend_color state
;
144 struct r600_clip_state
{
145 struct r600_atom atom
;
146 struct pipe_clip_state state
;
149 struct r600_cs_shader_state
{
150 struct r600_atom atom
;
151 unsigned kernel_index
;
152 struct r600_pipe_compute
*shader
;
155 struct r600_framebuffer
{
156 struct r600_atom atom
;
157 struct pipe_framebuffer_state state
;
158 unsigned compressed_cb_mask
;
162 bool is_msaa_resolve
;
165 struct r600_sample_mask
{
166 struct r600_atom atom
;
167 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
170 struct r600_config_state
{
171 struct r600_atom atom
;
172 unsigned sq_gpr_resource_mgmt_1
;
175 struct r600_stencil_ref
182 struct r600_stencil_ref_state
{
183 struct r600_atom atom
;
184 struct r600_stencil_ref state
;
185 struct pipe_stencil_ref pipe_state
;
188 struct r600_viewport_state
{
189 struct r600_atom atom
;
190 struct pipe_viewport_state state
;
193 struct r600_pipe_fences
{
194 struct r600_resource
*bo
;
197 /* linked list of preallocated blocks */
198 struct list_head blocks
;
199 /* linked list of freed fences */
200 struct list_head pool
;
205 /* This must start from 16. */
206 #define DBG_NO_HYPERZ (1 << 16)
207 #define DBG_NO_LLVM (1 << 17)
208 #define DBG_NO_CP_DMA (1 << 18)
209 #define DBG_NO_ASYNC_DMA (1 << 19)
210 #define DBG_NO_DISCARD_RANGE (1 << 20)
212 #define DBG_NO_SB (1 << 21)
213 #define DBG_SB_CS (1 << 22)
214 #define DBG_SB_DRY_RUN (1 << 23)
215 #define DBG_SB_STAT (1 << 24)
216 #define DBG_SB_DUMP (1 << 25)
217 #define DBG_SB_NO_FALLBACK (1 << 26)
218 #define DBG_SB_DISASM (1 << 27)
219 #define DBG_SB_SAFEMATH (1 << 28)
222 struct r600_common_screen b
;
226 bool has_compressed_msaa_texturing
;
227 struct r600_pipe_fences fences
;
229 /*for compute global memory binding, we allocate stuff here, instead of
231 * XXX: Not sure if this is the best place for global_pool. Also,
232 * it's not thread safe, so it won't work with multiple contexts. */
233 struct compute_memory_pool
*global_pool
;
234 struct r600_resource
*trace_bo
;
239 struct r600_pipe_sampler_view
{
240 struct pipe_sampler_view base
;
241 struct r600_resource
*tex_resource
;
242 uint32_t tex_resource_words
[8];
243 bool skip_mip_address_reloc
;
246 struct r600_rasterizer_state
{
247 struct r600_command_buffer buffer
;
250 unsigned sprite_coord_enable
;
251 unsigned clip_plane_enable
;
252 unsigned pa_sc_line_stipple
;
253 unsigned pa_cl_clip_cntl
;
258 bool multisample_enable
;
261 struct r600_poly_offset_state
{
262 struct r600_atom atom
;
263 enum pipe_format zs_format
;
268 struct r600_blend_state
{
269 struct r600_command_buffer buffer
;
270 struct r600_command_buffer buffer_no_blend
;
271 unsigned cb_target_mask
;
272 unsigned cb_color_control
;
273 unsigned cb_color_control_no_blend
;
278 struct r600_dsa_state
{
279 struct r600_command_buffer buffer
;
284 unsigned sx_alpha_test_control
;
287 struct r600_pipe_shader
;
289 struct r600_pipe_shader_selector
{
290 struct r600_pipe_shader
*current
;
292 struct tgsi_token
*tokens
;
293 struct pipe_stream_output_info so
;
295 unsigned num_shaders
;
297 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
300 unsigned nr_ps_max_color_exports
;
303 struct r600_pipe_sampler_state
{
304 uint32_t tex_sampler_words
[3];
305 union pipe_color_union border_color
;
306 bool border_color_use
;
307 bool seamless_cube_map
;
310 /* needed for blitter save */
311 #define NUM_TEX_UNITS 16
313 struct r600_seamless_cube_map
{
314 struct r600_atom atom
;
318 struct r600_samplerview_state
{
319 struct r600_atom atom
;
320 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
321 uint32_t enabled_mask
;
323 uint32_t compressed_depthtex_mask
; /* which textures are depth */
324 uint32_t compressed_colortex_mask
;
325 boolean dirty_txq_constants
;
326 boolean dirty_buffer_constants
;
329 struct r600_sampler_states
{
330 struct r600_atom atom
;
331 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
332 uint32_t enabled_mask
;
334 uint32_t has_bordercolor_mask
; /* which states contain the border color */
337 struct r600_textures_info
{
338 struct r600_samplerview_state views
;
339 struct r600_sampler_states states
;
340 bool is_array_sampler
[NUM_TEX_UNITS
];
342 /* cube array txq workaround */
343 uint32_t *txq_constants
;
344 /* buffer related workarounds */
345 uint32_t *buffer_constants
;
349 struct pipe_reference reference
;
350 unsigned index
; /* in the shared bo */
351 struct r600_resource
*sleep_bo
;
352 struct list_head head
;
355 #define FENCE_BLOCK_SIZE 16
357 struct r600_fence_block
{
358 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
359 struct list_head head
;
362 struct r600_constbuf_state
364 struct r600_atom atom
;
365 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
366 uint32_t enabled_mask
;
370 struct r600_vertexbuf_state
372 struct r600_atom atom
;
373 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
374 uint32_t enabled_mask
; /* non-NULL buffers */
378 /* CSO (constant state object, in other words, immutable state). */
379 struct r600_cso_state
381 struct r600_atom atom
;
382 void *cso
; /* e.g. r600_blend_state */
383 struct r600_command_buffer
*cb
;
386 struct r600_scissor_state
388 struct r600_atom atom
;
389 struct pipe_scissor_state scissor
;
390 bool enable
; /* r6xx only */
393 struct r600_fetch_shader
{
394 struct r600_resource
*buffer
;
398 struct r600_shader_state
{
399 struct r600_atom atom
;
400 struct r600_pipe_shader_selector
*shader
;
403 struct r600_query_buffer
{
404 /* The buffer where query results are stored. */
405 struct r600_resource
*buf
;
406 /* Offset of the next free result after current query data */
407 unsigned results_end
;
408 /* If a query buffer is full, a new buffer is created and the old one
409 * is put in here. When we calculate the result, we sum up the samples
410 * from all buffers. */
411 struct r600_query_buffer
*previous
;
415 /* The query buffer and how many results are in it. */
416 struct r600_query_buffer buffer
;
417 /* The type of query */
419 /* Size of the result in memory for both begin_query and end_query,
420 * this can be one or two numbers, or it could even be a size of a structure. */
421 unsigned result_size
;
422 /* The number of dwords for begin_query or end_query. */
424 /* linked list of queries */
425 struct list_head list
;
426 /* for custom non-GPU queries */
427 uint64_t begin_result
;
431 struct r600_context
{
432 struct r600_common_context b
;
433 struct r600_screen
*screen
;
434 struct blitter_context
*blitter
;
435 struct u_upload_mgr
*uploader
;
436 struct u_suballocator
*allocator_fetch_shader
;
437 struct util_slab_mempool pool_transfers
;
438 unsigned initial_gfx_cs_size
;
441 boolean has_vertex_cache
;
442 boolean keep_tiling_flags
;
443 unsigned default_ps_gprs
, default_vs_gprs
;
444 unsigned r6xx_num_clause_temp_gprs
;
445 unsigned backend_mask
;
446 unsigned max_db
; /* for OQ */
448 /* Miscellaneous state objects. */
449 void *custom_dsa_flush
;
450 void *custom_blend_resolve
;
451 void *custom_blend_decompress
;
452 void *custom_blend_fastclear
;
453 /* With rasterizer discard, there doesn't have to be a pixel shader.
454 * In that case, we bind this one: */
455 void *dummy_pixel_shader
;
456 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
457 * bug where valid CMASK and FMASK are required to be present to avoid
458 * a hardlock in certain operations but aren't actually used
459 * for anything useful. */
460 struct r600_resource
*dummy_fmask
;
461 struct r600_resource
*dummy_cmask
;
463 /* State binding slots are here. */
464 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
465 /* States for CS initialization. */
466 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
467 /** Compute specific registers initializations. The start_cs_cmd atom
468 * must be emitted before start_compute_cs_cmd. */
469 struct r600_command_buffer start_compute_cs_cmd
;
470 /* Register states. */
471 struct r600_alphatest_state alphatest_state
;
472 struct r600_cso_state blend_state
;
473 struct r600_blend_color blend_color
;
474 struct r600_cb_misc_state cb_misc_state
;
475 struct r600_clip_misc_state clip_misc_state
;
476 struct r600_clip_state clip_state
;
477 struct r600_db_misc_state db_misc_state
;
478 struct r600_db_state db_state
;
479 struct r600_cso_state dsa_state
;
480 struct r600_framebuffer framebuffer
;
481 struct r600_poly_offset_state poly_offset_state
;
482 struct r600_cso_state rasterizer_state
;
483 struct r600_sample_mask sample_mask
;
484 struct r600_scissor_state scissor
;
485 struct r600_seamless_cube_map seamless_cube_map
;
486 struct r600_config_state config_state
;
487 struct r600_stencil_ref_state stencil_ref
;
488 struct r600_vgt_state vgt_state
;
489 struct r600_viewport_state viewport
;
490 /* Shaders and shader resources. */
491 struct r600_cso_state vertex_fetch_shader
;
492 struct r600_shader_state vertex_shader
;
493 struct r600_shader_state pixel_shader
;
494 struct r600_cs_shader_state cs_shader_state
;
495 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
496 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
497 /** Vertex buffers for fetch shaders */
498 struct r600_vertexbuf_state vertex_buffer_state
;
499 /** Vertex buffers for compute shaders */
500 struct r600_vertexbuf_state cs_vertex_buffer_state
;
502 /* Additional context states. */
503 unsigned compute_cb_target_mask
;
504 struct r600_pipe_shader_selector
*ps_shader
;
505 struct r600_pipe_shader_selector
*vs_shader
;
506 struct r600_rasterizer_state
*rasterizer
;
508 bool force_blend_disable
;
509 boolean dual_src_blend
;
513 struct pipe_index_buffer index_buffer
;
515 /* Last draw state (-1 = unset). */
516 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
517 int last_start_instance
;
520 /* The list of active queries. Only one query of each type can be active. */
521 int num_occlusion_queries
;
522 int num_pipelinestat_queries
;
523 /* Keep track of non-timer queries, because they should be suspended
524 * during context flushing.
525 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
526 struct list_head active_nontimer_queries
;
527 unsigned num_cs_dw_nontimer_queries_suspend
;
528 /* If queries have been suspended. */
529 bool nontimer_queries_suspended
;
530 unsigned num_draw_calls
;
532 /* Render condition. */
533 struct pipe_query
*current_render_cond
;
534 unsigned current_render_cond_mode
;
535 boolean current_render_cond_cond
;
536 boolean predicate_drawing
;
539 struct r600_isa
*isa
;
542 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
543 struct r600_command_buffer
*cb
)
545 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
546 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
547 cs
->cdw
+= cb
->num_dw
;
550 void r600_trace_emit(struct r600_context
*rctx
);
552 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
554 atom
->emit(&rctx
->b
, atom
);
556 if (rctx
->screen
->trace_bo
) {
557 r600_trace_emit(rctx
);
561 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
564 state
->atom
.dirty
= cso
!= NULL
;
567 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
568 struct r600_command_buffer
*cb
)
571 state
->atom
.num_dw
= cb
->num_dw
;
572 r600_set_cso_state(state
, cso
);
575 /* compute_memory_pool.c */
576 struct compute_memory_pool
;
577 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
578 struct compute_memory_pool
* compute_memory_pool_new(
579 struct r600_screen
*rscreen
);
581 /* evergreen_state.c */
582 struct pipe_sampler_view
*
583 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
584 struct pipe_resource
*texture
,
585 const struct pipe_sampler_view
*state
,
586 unsigned width0
, unsigned height0
);
587 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
588 enum chip_class ctx_chip_class
,
589 enum radeon_family ctx_family
,
591 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
592 enum chip_class ctx_chip_class
,
593 enum radeon_family ctx_family
,
596 void evergreen_init_state_functions(struct r600_context
*rctx
);
597 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
598 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
599 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
600 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
601 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
602 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
603 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
604 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
605 enum pipe_format format
,
606 enum pipe_texture_target target
,
607 unsigned sample_count
,
609 void evergreen_init_color_surface(struct r600_context
*rctx
,
610 struct r600_surface
*surf
);
611 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
612 struct r600_surface
*surf
);
613 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
616 void r600_copy_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dstx
,
617 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
618 void r600_init_blit_functions(struct r600_context
*rctx
);
619 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
620 struct r600_texture
*texture
,
621 struct r600_texture
*staging
,
622 unsigned first_level
, unsigned last_level
,
623 unsigned first_layer
, unsigned last_layer
,
624 unsigned first_sample
, unsigned last_sample
);
625 void r600_decompress_depth_textures(struct r600_context
*rctx
,
626 struct r600_samplerview_state
*textures
);
627 void r600_decompress_color_textures(struct r600_context
*rctx
,
628 struct r600_samplerview_state
*textures
);
631 bool r600_init_resource(struct r600_screen
*rscreen
,
632 struct r600_resource
*res
,
633 unsigned size
, unsigned alignment
,
634 bool use_reusable_pool
, unsigned usage
);
635 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
636 const struct pipe_resource
*templ
,
640 boolean
r600_rings_is_buffer_referenced(struct r600_context
*ctx
,
641 struct radeon_winsys_cs_handle
*buf
,
642 enum radeon_bo_usage usage
);
643 void *r600_buffer_mmap_sync_with_rings(struct r600_context
*ctx
,
644 struct r600_resource
*resource
,
646 const char * r600_llvm_gpu_string(enum radeon_family family
);
650 void r600_init_query_functions(struct r600_context
*rctx
);
651 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
652 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
654 /* r600_resource.c */
655 void r600_init_context_resource_functions(struct r600_context
*r600
);
658 int r600_pipe_shader_create(struct pipe_context
*ctx
,
659 struct r600_pipe_shader
*shader
,
660 struct r600_shader_key key
);
662 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
665 struct pipe_sampler_view
*
666 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
667 struct pipe_resource
*texture
,
668 const struct pipe_sampler_view
*state
,
669 unsigned width_first_level
, unsigned height_first_level
);
670 void r600_init_state_functions(struct r600_context
*rctx
);
671 void r600_init_atom_start_cs(struct r600_context
*rctx
);
672 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
673 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
674 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
675 void *r600_create_resolve_blend(struct r600_context
*rctx
);
676 void *r700_create_resolve_blend(struct r600_context
*rctx
);
677 void *r600_create_decompress_blend(struct r600_context
*rctx
);
678 bool r600_adjust_gprs(struct r600_context
*rctx
);
679 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
680 enum pipe_format format
,
681 enum pipe_texture_target target
,
682 unsigned sample_count
,
684 void r600_update_db_shader_control(struct r600_context
* rctx
);
686 /* r600_hw_context.c */
687 void r600_get_backend_mask(struct r600_context
*ctx
);
688 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
);
689 void r600_begin_new_cs(struct r600_context
*ctx
);
690 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_resource
*fence
,
691 unsigned offset
, unsigned value
);
692 void r600_flush_emit(struct r600_context
*ctx
);
693 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
694 void r600_need_dma_space(struct r600_context
*ctx
, unsigned num_dw
);
695 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
696 struct pipe_resource
*dst
, uint64_t dst_offset
,
697 struct pipe_resource
*src
, uint64_t src_offset
,
699 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
700 struct pipe_resource
*dst
, uint64_t offset
,
701 unsigned size
, uint32_t clear_value
);
702 void r600_dma_copy(struct r600_context
*rctx
,
703 struct pipe_resource
*dst
,
704 struct pipe_resource
*src
,
708 void r600_flag_resource_cache_flush(struct r600_context
*rctx
,
709 struct pipe_resource
*res
);
712 * evergreen_hw_context.c
714 void evergreen_dma_copy(struct r600_context
*rctx
,
715 struct pipe_resource
*dst
,
716 struct pipe_resource
*src
,
721 /* r600_state_common.c */
722 void r600_init_common_state_functions(struct r600_context
*rctx
);
723 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
724 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
725 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
726 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
727 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
728 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
729 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
730 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
731 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
732 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
734 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
735 void r600_sampler_views_dirty(struct r600_context
*rctx
,
736 struct r600_samplerview_state
*state
);
737 void r600_sampler_states_dirty(struct r600_context
*rctx
,
738 struct r600_sampler_states
*state
);
739 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
740 void r600_draw_rectangle(struct blitter_context
*blitter
,
741 int x1
, int y1
, int x2
, int y2
, float depth
,
742 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
743 uint32_t r600_translate_stencil_op(int s_op
);
744 uint32_t r600_translate_fill(uint32_t func
);
745 unsigned r600_tex_wrap(unsigned wrap
);
746 unsigned r600_tex_filter(unsigned filter
);
747 unsigned r600_tex_mipfilter(unsigned filter
);
748 unsigned r600_tex_compare(unsigned compare
);
749 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
750 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
751 struct pipe_resource
*texture
,
752 const struct pipe_surface
*templ
,
753 unsigned width
, unsigned height
);
754 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
755 const unsigned char *swizzle_view
,
757 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
758 const unsigned char *swizzle_view
,
759 uint32_t *word4_p
, uint32_t *yuv_format_p
);
762 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
763 const struct pipe_video_codec
*decoder
);
765 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
766 const struct pipe_video_buffer
*tmpl
);
769 * Helpers for building command buffers
772 #define PKT3_SET_CONFIG_REG 0x68
773 #define PKT3_SET_CONTEXT_REG 0x69
774 #define PKT3_SET_CTL_CONST 0x6F
775 #define PKT3_SET_LOOP_CONST 0x6C
777 #define R600_CONFIG_REG_OFFSET 0x08000
778 #define R600_CONTEXT_REG_OFFSET 0x28000
779 #define R600_CTL_CONST_OFFSET 0x3CFF0
780 #define R600_LOOP_CONST_OFFSET 0X0003E200
781 #define EG_LOOP_CONST_OFFSET 0x0003A200
783 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
784 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
785 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
786 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
787 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
789 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
791 /*Evergreen Compute packet3*/
792 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
794 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
796 cb
->buf
[cb
->num_dw
++] = value
;
799 static INLINE
void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
801 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
802 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
806 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
808 assert(reg
< R600_CONTEXT_REG_OFFSET
);
809 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
810 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
811 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
815 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
818 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
820 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
821 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
822 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
823 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
827 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
830 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
832 assert(reg
>= R600_CTL_CONST_OFFSET
);
833 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
834 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
835 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
838 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
840 assert(reg
>= R600_LOOP_CONST_OFFSET
);
841 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
842 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
843 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
847 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
850 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
852 assert(reg
>= EG_LOOP_CONST_OFFSET
);
853 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
854 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
855 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
858 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
860 r600_store_config_reg_seq(cb
, reg
, 1);
861 r600_store_value(cb
, value
);
864 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
866 r600_store_context_reg_seq(cb
, reg
, 1);
867 r600_store_value(cb
, value
);
870 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
872 r600_store_ctl_const_seq(cb
, reg
, 1);
873 r600_store_value(cb
, value
);
876 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
878 r600_store_loop_const_seq(cb
, reg
, 1);
879 r600_store_value(cb
, value
);
882 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
884 eg_store_loop_const_seq(cb
, reg
, 1);
885 r600_store_value(cb
, value
);
888 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
889 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
891 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
893 r600_write_context_reg_seq(cs
, reg
, num
);
894 /* Set the compute bit on the packet header */
895 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
898 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
900 assert(reg
>= R600_CTL_CONST_OFFSET
);
901 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
902 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
903 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
906 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
908 r600_write_compute_context_reg_seq(cs
, reg
, 1);
909 radeon_emit(cs
, value
);
912 static INLINE
void r600_write_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
914 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
915 r600_write_compute_context_reg(cs
, reg
, value
);
917 r600_write_context_reg(cs
, reg
, value
);
921 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
923 r600_write_ctl_const_seq(cs
, reg
, 1);
924 radeon_emit(cs
, value
);
930 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
932 return value
* (1 << frac_bits
);
934 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
936 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
938 if (filter
<= 1) return 0;
939 if (filter
<= 2) return 1;
940 if (filter
<= 4) return 2;
941 if (filter
<= 8) return 3;
945 /* 12.4 fixed-point */
946 static INLINE
unsigned r600_pack_float_12p4(float x
)
949 x
>= 4096 ? 0xffff : x
* 16;