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radeonsi: move scissor and viewport states into gallium/radeon
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
36
37 #include "tgsi/tgsi_scan.h"
38
39 #define R600_NUM_ATOMS 52
40
41 /* read caches */
42 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
43 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
44 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
45 /* read-write caches */
46 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
47 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
48 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
49 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
50 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
51 /* engine synchronization */
52 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
53 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
54 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
55
56 /* the number of CS dwords for flushing and drawing */
57 #define R600_MAX_FLUSH_CS_DWORDS 18
58 #define R600_MAX_DRAW_CS_DWORDS 58
59
60 #define R600_MAX_USER_CONST_BUFFERS 13
61 #define R600_MAX_DRIVER_CONST_BUFFERS 3
62 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
63
64 /* start driver buffers after user buffers */
65 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
66 #define R600_UCP_SIZE (4*4*8)
67 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
68
69 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
70 /*
71 * Note GS doesn't use a constant buffer binding, just a resource index,
72 * so it's fine to have it exist at index 16.
73 */
74 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
75 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
76 * of 16 const buffers.
77 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
78 *
79 * In order to support d3d 11 mandated minimum of 15 user const buffers
80 * we'd have to squash all use cases into one driver buffer.
81 */
82 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
83
84 /* HW stages */
85 #define R600_HW_STAGE_PS 0
86 #define R600_HW_STAGE_VS 1
87 #define R600_HW_STAGE_GS 2
88 #define R600_HW_STAGE_ES 3
89 #define EG_HW_STAGE_LS 4
90 #define EG_HW_STAGE_HS 5
91
92 #define R600_NUM_HW_STAGES 4
93 #define EG_NUM_HW_STAGES 6
94
95 #ifdef PIPE_ARCH_BIG_ENDIAN
96 #define R600_BIG_ENDIAN 1
97 #else
98 #define R600_BIG_ENDIAN 0
99 #endif
100
101 struct r600_context;
102 struct r600_bytecode;
103 union r600_shader_key;
104
105 /* This is an atom containing GPU commands that never change.
106 * This is supposed to be copied directly into the CS. */
107 struct r600_command_buffer {
108 uint32_t *buf;
109 unsigned num_dw;
110 unsigned max_num_dw;
111 unsigned pkt_flags;
112 };
113
114 struct r600_db_state {
115 struct r600_atom atom;
116 struct r600_surface *rsurf;
117 };
118
119 struct r600_db_misc_state {
120 struct r600_atom atom;
121 bool occlusion_queries_disabled;
122 bool flush_depthstencil_through_cb;
123 bool flush_depth_inplace;
124 bool flush_stencil_inplace;
125 bool copy_depth, copy_stencil;
126 unsigned copy_sample;
127 unsigned log_samples;
128 unsigned db_shader_control;
129 bool htile_clear;
130 uint8_t ps_conservative_z;
131 };
132
133 struct r600_cb_misc_state {
134 struct r600_atom atom;
135 unsigned cb_color_control; /* this comes from blend state */
136 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
137 unsigned nr_cbufs;
138 unsigned nr_ps_color_outputs;
139 bool multiwrite;
140 bool dual_src_blend;
141 };
142
143 struct r600_clip_misc_state {
144 struct r600_atom atom;
145 unsigned pa_cl_clip_cntl; /* from rasterizer */
146 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
147 unsigned clip_plane_enable; /* from rasterizer */
148 unsigned clip_dist_write; /* from vertex shader */
149 boolean clip_disable; /* from vertex shader */
150 boolean vs_out_viewport; /* from vertex shader */
151 };
152
153 struct r600_alphatest_state {
154 struct r600_atom atom;
155 unsigned sx_alpha_test_control; /* this comes from dsa state */
156 unsigned sx_alpha_ref; /* this comes from dsa state */
157 bool bypass;
158 bool cb0_export_16bpc; /* from set_framebuffer_state */
159 };
160
161 struct r600_vgt_state {
162 struct r600_atom atom;
163 uint32_t vgt_multi_prim_ib_reset_en;
164 uint32_t vgt_multi_prim_ib_reset_indx;
165 uint32_t vgt_indx_offset;
166 bool last_draw_was_indirect;
167 };
168
169 struct r600_blend_color {
170 struct r600_atom atom;
171 struct pipe_blend_color state;
172 };
173
174 struct r600_clip_state {
175 struct r600_atom atom;
176 struct pipe_clip_state state;
177 };
178
179 struct r600_cs_shader_state {
180 struct r600_atom atom;
181 unsigned kernel_index;
182 unsigned pc;
183 struct r600_pipe_compute *shader;
184 };
185
186 struct r600_framebuffer {
187 struct r600_atom atom;
188 struct pipe_framebuffer_state state;
189 unsigned compressed_cb_mask;
190 unsigned nr_samples;
191 bool export_16bpc;
192 bool cb0_is_integer;
193 bool is_msaa_resolve;
194 };
195
196 struct r600_sample_mask {
197 struct r600_atom atom;
198 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
199 };
200
201 struct r600_config_state {
202 struct r600_atom atom;
203 unsigned sq_gpr_resource_mgmt_1;
204 unsigned sq_gpr_resource_mgmt_2;
205 unsigned sq_gpr_resource_mgmt_3;
206 bool dyn_gpr_enabled;
207 };
208
209 struct r600_stencil_ref
210 {
211 ubyte ref_value[2];
212 ubyte valuemask[2];
213 ubyte writemask[2];
214 };
215
216 struct r600_stencil_ref_state {
217 struct r600_atom atom;
218 struct r600_stencil_ref state;
219 struct pipe_stencil_ref pipe_state;
220 };
221
222 struct r600_viewport_state {
223 struct r600_atom atom;
224 struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
225 uint32_t dirty_mask;
226 };
227
228 struct r600_shader_stages_state {
229 struct r600_atom atom;
230 unsigned geom_enable;
231 };
232
233 struct r600_gs_rings_state {
234 struct r600_atom atom;
235 unsigned enable;
236 struct pipe_constant_buffer esgs_ring;
237 struct pipe_constant_buffer gsvs_ring;
238 };
239
240 /* This must start from 16. */
241 /* features */
242 #define DBG_NO_CP_DMA (1 << 30)
243 /* shader backend */
244 #define DBG_NO_SB (1 << 21)
245 #define DBG_SB_CS (1 << 22)
246 #define DBG_SB_DRY_RUN (1 << 23)
247 #define DBG_SB_STAT (1 << 24)
248 #define DBG_SB_DUMP (1 << 25)
249 #define DBG_SB_NO_FALLBACK (1 << 26)
250 #define DBG_SB_DISASM (1 << 27)
251 #define DBG_SB_SAFEMATH (1 << 28)
252
253 struct r600_screen {
254 struct r600_common_screen b;
255 bool has_msaa;
256 bool has_compressed_msaa_texturing;
257
258 /*for compute global memory binding, we allocate stuff here, instead of
259 * buffers.
260 * XXX: Not sure if this is the best place for global_pool. Also,
261 * it's not thread safe, so it won't work with multiple contexts. */
262 struct compute_memory_pool *global_pool;
263 };
264
265 struct r600_pipe_sampler_view {
266 struct pipe_sampler_view base;
267 struct list_head list;
268 struct r600_resource *tex_resource;
269 uint32_t tex_resource_words[8];
270 bool skip_mip_address_reloc;
271 bool is_stencil_sampler;
272 };
273
274 struct r600_rasterizer_state {
275 struct r600_command_buffer buffer;
276 boolean flatshade;
277 boolean two_side;
278 unsigned sprite_coord_enable;
279 unsigned clip_plane_enable;
280 unsigned pa_sc_line_stipple;
281 unsigned pa_cl_clip_cntl;
282 unsigned pa_su_sc_mode_cntl;
283 float offset_units;
284 float offset_scale;
285 bool offset_enable;
286 bool scissor_enable;
287 bool multisample_enable;
288 };
289
290 struct r600_poly_offset_state {
291 struct r600_atom atom;
292 enum pipe_format zs_format;
293 float offset_units;
294 float offset_scale;
295 };
296
297 struct r600_blend_state {
298 struct r600_command_buffer buffer;
299 struct r600_command_buffer buffer_no_blend;
300 unsigned cb_target_mask;
301 unsigned cb_color_control;
302 unsigned cb_color_control_no_blend;
303 bool dual_src_blend;
304 bool alpha_to_one;
305 };
306
307 struct r600_dsa_state {
308 struct r600_command_buffer buffer;
309 unsigned alpha_ref;
310 ubyte valuemask[2];
311 ubyte writemask[2];
312 unsigned zwritemask;
313 unsigned sx_alpha_test_control;
314 };
315
316 struct r600_pipe_shader;
317
318 struct r600_pipe_shader_selector {
319 struct r600_pipe_shader *current;
320
321 struct tgsi_token *tokens;
322 struct pipe_stream_output_info so;
323 struct tgsi_shader_info info;
324
325 unsigned num_shaders;
326
327 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
328 unsigned type;
329
330 /* geometry shader properties */
331 unsigned gs_output_prim;
332 unsigned gs_max_out_vertices;
333 unsigned gs_num_invocations;
334
335 /* TCS/VS */
336 uint64_t lds_patch_outputs_written_mask;
337 uint64_t lds_outputs_written_mask;
338 unsigned nr_ps_max_color_exports;
339 };
340
341 struct r600_pipe_sampler_state {
342 uint32_t tex_sampler_words[3];
343 union pipe_color_union border_color;
344 bool border_color_use;
345 bool seamless_cube_map;
346 };
347
348 /* needed for blitter save */
349 #define NUM_TEX_UNITS 16
350
351 struct r600_seamless_cube_map {
352 struct r600_atom atom;
353 bool enabled;
354 };
355
356 struct r600_samplerview_state {
357 struct r600_atom atom;
358 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
359 uint32_t enabled_mask;
360 uint32_t dirty_mask;
361 uint32_t compressed_depthtex_mask; /* which textures are depth */
362 uint32_t compressed_colortex_mask;
363 boolean dirty_buffer_constants;
364 };
365
366 struct r600_sampler_states {
367 struct r600_atom atom;
368 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
369 uint32_t enabled_mask;
370 uint32_t dirty_mask;
371 uint32_t has_bordercolor_mask; /* which states contain the border color */
372 };
373
374 struct r600_textures_info {
375 struct r600_samplerview_state views;
376 struct r600_sampler_states states;
377 bool is_array_sampler[NUM_TEX_UNITS];
378 };
379
380 struct r600_shader_driver_constants_info {
381 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
382 uint32_t *constants;
383 uint32_t alloc_size;
384 bool vs_ucp_dirty;
385 bool texture_const_dirty;
386 bool ps_sample_pos_dirty;
387 };
388
389 struct r600_constbuf_state
390 {
391 struct r600_atom atom;
392 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
393 uint32_t enabled_mask;
394 uint32_t dirty_mask;
395 };
396
397 struct r600_vertexbuf_state
398 {
399 struct r600_atom atom;
400 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
401 uint32_t enabled_mask; /* non-NULL buffers */
402 uint32_t dirty_mask;
403 };
404
405 /* CSO (constant state object, in other words, immutable state). */
406 struct r600_cso_state
407 {
408 struct r600_atom atom;
409 void *cso; /* e.g. r600_blend_state */
410 struct r600_command_buffer *cb;
411 };
412
413 struct r600_scissor_state
414 {
415 struct r600_atom atom;
416 struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
417 uint32_t dirty_mask;
418 bool enable; /* r6xx only */
419 };
420
421 struct r600_fetch_shader {
422 struct r600_resource *buffer;
423 unsigned offset;
424 };
425
426 struct r600_shader_state {
427 struct r600_atom atom;
428 struct r600_pipe_shader *shader;
429 };
430
431 struct r600_context {
432 struct r600_common_context b;
433 struct r600_screen *screen;
434 struct blitter_context *blitter;
435 struct u_suballocator *allocator_fetch_shader;
436
437 /* Hardware info. */
438 boolean has_vertex_cache;
439 unsigned default_gprs[EG_NUM_HW_STAGES];
440 unsigned current_gprs[EG_NUM_HW_STAGES];
441 unsigned r6xx_num_clause_temp_gprs;
442
443 /* Miscellaneous state objects. */
444 void *custom_dsa_flush;
445 void *custom_blend_resolve;
446 void *custom_blend_decompress;
447 void *custom_blend_fastclear;
448 /* With rasterizer discard, there doesn't have to be a pixel shader.
449 * In that case, we bind this one: */
450 void *dummy_pixel_shader;
451 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
452 * bug where valid CMASK and FMASK are required to be present to avoid
453 * a hardlock in certain operations but aren't actually used
454 * for anything useful. */
455 struct r600_resource *dummy_fmask;
456 struct r600_resource *dummy_cmask;
457
458 /* State binding slots are here. */
459 struct r600_atom *atoms[R600_NUM_ATOMS];
460 /* Dirty atom bitmask for fast tests */
461 uint64_t dirty_atoms;
462 /* States for CS initialization. */
463 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
464 /** Compute specific registers initializations. The start_cs_cmd atom
465 * must be emitted before start_compute_cs_cmd. */
466 struct r600_command_buffer start_compute_cs_cmd;
467 /* Register states. */
468 struct r600_alphatest_state alphatest_state;
469 struct r600_cso_state blend_state;
470 struct r600_blend_color blend_color;
471 struct r600_cb_misc_state cb_misc_state;
472 struct r600_clip_misc_state clip_misc_state;
473 struct r600_clip_state clip_state;
474 struct r600_db_misc_state db_misc_state;
475 struct r600_db_state db_state;
476 struct r600_cso_state dsa_state;
477 struct r600_framebuffer framebuffer;
478 struct r600_poly_offset_state poly_offset_state;
479 struct r600_cso_state rasterizer_state;
480 struct r600_sample_mask sample_mask;
481 struct r600_scissor_state scissor;
482 struct r600_seamless_cube_map seamless_cube_map;
483 struct r600_config_state config_state;
484 struct r600_stencil_ref_state stencil_ref;
485 struct r600_vgt_state vgt_state;
486 struct r600_viewport_state viewport;
487 /* Shaders and shader resources. */
488 struct r600_cso_state vertex_fetch_shader;
489 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
490 struct r600_cs_shader_state cs_shader_state;
491 struct r600_shader_stages_state shader_stages;
492 struct r600_gs_rings_state gs_rings;
493 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
494 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
495
496 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
497
498 /** Vertex buffers for fetch shaders */
499 struct r600_vertexbuf_state vertex_buffer_state;
500 /** Vertex buffers for compute shaders */
501 struct r600_vertexbuf_state cs_vertex_buffer_state;
502
503 /* Additional context states. */
504 unsigned compute_cb_target_mask;
505 struct r600_pipe_shader_selector *ps_shader;
506 struct r600_pipe_shader_selector *vs_shader;
507 struct r600_pipe_shader_selector *gs_shader;
508
509 struct r600_pipe_shader_selector *tcs_shader;
510 struct r600_pipe_shader_selector *tes_shader;
511
512 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
513
514 struct r600_rasterizer_state *rasterizer;
515 bool alpha_to_one;
516 bool force_blend_disable;
517 boolean dual_src_blend;
518 unsigned zwritemask;
519 int ps_iter_samples;
520
521 /* Index buffer. */
522 struct pipe_index_buffer index_buffer;
523
524 /* Last draw state (-1 = unset). */
525 int last_primitive_type; /* Last primitive type used in draw_vbo. */
526 int last_start_instance;
527
528 void *sb_context;
529 struct r600_isa *isa;
530 float sample_positions[4 * 16];
531 float tess_state[8];
532 bool tess_state_dirty;
533 struct r600_pipe_shader_selector *last_ls;
534 struct r600_pipe_shader_selector *last_tcs;
535 unsigned last_num_tcs_input_cp;
536 unsigned lds_alloc;
537 };
538
539 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
540 struct r600_command_buffer *cb)
541 {
542 assert(cs->cdw + cb->num_dw <= cs->max_dw);
543 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
544 cs->cdw += cb->num_dw;
545 }
546
547 static inline void r600_set_atom_dirty(struct r600_context *rctx,
548 struct r600_atom *atom,
549 bool dirty)
550 {
551 uint64_t mask;
552
553 assert(atom->id != 0);
554 assert(atom->id < sizeof(mask) * 8);
555 mask = 1ull << atom->id;
556 if (dirty)
557 rctx->dirty_atoms |= mask;
558 else
559 rctx->dirty_atoms &= ~mask;
560 }
561
562 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
563 struct r600_atom *atom)
564 {
565 r600_set_atom_dirty(rctx, atom, true);
566 }
567
568 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
569 {
570 atom->emit(&rctx->b, atom);
571 r600_set_atom_dirty(rctx, atom, false);
572 }
573
574 static inline void r600_set_cso_state(struct r600_context *rctx,
575 struct r600_cso_state *state, void *cso)
576 {
577 state->cso = cso;
578 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
579 }
580
581 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
582 struct r600_cso_state *state, void *cso,
583 struct r600_command_buffer *cb)
584 {
585 state->cb = cb;
586 state->atom.num_dw = cb ? cb->num_dw : 0;
587 r600_set_cso_state(rctx, state, cso);
588 }
589
590 /* compute_memory_pool.c */
591 struct compute_memory_pool;
592 void compute_memory_pool_delete(struct compute_memory_pool* pool);
593 struct compute_memory_pool* compute_memory_pool_new(
594 struct r600_screen *rscreen);
595
596 /* evergreen_state.c */
597 struct pipe_sampler_view *
598 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
599 struct pipe_resource *texture,
600 const struct pipe_sampler_view *state,
601 unsigned width0, unsigned height0,
602 unsigned force_level);
603 void evergreen_init_common_regs(struct r600_context *ctx,
604 struct r600_command_buffer *cb,
605 enum chip_class ctx_chip_class,
606 enum radeon_family ctx_family,
607 int ctx_drm_minor);
608 void cayman_init_common_regs(struct r600_command_buffer *cb,
609 enum chip_class ctx_chip_class,
610 enum radeon_family ctx_family,
611 int ctx_drm_minor);
612
613 void evergreen_init_state_functions(struct r600_context *rctx);
614 void evergreen_init_atom_start_cs(struct r600_context *rctx);
615 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
616 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
617 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
618 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
619 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
620 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
621 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
622 void *evergreen_create_resolve_blend(struct r600_context *rctx);
623 void *evergreen_create_decompress_blend(struct r600_context *rctx);
624 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
625 boolean evergreen_is_format_supported(struct pipe_screen *screen,
626 enum pipe_format format,
627 enum pipe_texture_target target,
628 unsigned sample_count,
629 unsigned usage);
630 void evergreen_init_color_surface(struct r600_context *rctx,
631 struct r600_surface *surf);
632 void evergreen_init_color_surface_rat(struct r600_context *rctx,
633 struct r600_surface *surf);
634 void evergreen_update_db_shader_control(struct r600_context * rctx);
635 bool evergreen_adjust_gprs(struct r600_context *rctx);
636 /* r600_blit.c */
637 void r600_init_blit_functions(struct r600_context *rctx);
638 void r600_decompress_depth_textures(struct r600_context *rctx,
639 struct r600_samplerview_state *textures);
640 void r600_decompress_color_textures(struct r600_context *rctx,
641 struct r600_samplerview_state *textures);
642 void r600_resource_copy_region(struct pipe_context *ctx,
643 struct pipe_resource *dst,
644 unsigned dst_level,
645 unsigned dstx, unsigned dsty, unsigned dstz,
646 struct pipe_resource *src,
647 unsigned src_level,
648 const struct pipe_box *src_box);
649
650 /* r600_shader.c */
651 int r600_pipe_shader_create(struct pipe_context *ctx,
652 struct r600_pipe_shader *shader,
653 union r600_shader_key key);
654
655 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
656
657 /* r600_state.c */
658 struct pipe_sampler_view *
659 r600_create_sampler_view_custom(struct pipe_context *ctx,
660 struct pipe_resource *texture,
661 const struct pipe_sampler_view *state,
662 unsigned width_first_level, unsigned height_first_level);
663 void r600_init_state_functions(struct r600_context *rctx);
664 void r600_init_atom_start_cs(struct r600_context *rctx);
665 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
666 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
667 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
668 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
669 void *r600_create_db_flush_dsa(struct r600_context *rctx);
670 void *r600_create_resolve_blend(struct r600_context *rctx);
671 void *r700_create_resolve_blend(struct r600_context *rctx);
672 void *r600_create_decompress_blend(struct r600_context *rctx);
673 bool r600_adjust_gprs(struct r600_context *rctx);
674 boolean r600_is_format_supported(struct pipe_screen *screen,
675 enum pipe_format format,
676 enum pipe_texture_target target,
677 unsigned sample_count,
678 unsigned usage);
679 void r600_update_db_shader_control(struct r600_context * rctx);
680
681 /* r600_hw_context.c */
682 void r600_context_gfx_flush(void *context, unsigned flags,
683 struct pipe_fence_handle **fence);
684 void r600_begin_new_cs(struct r600_context *ctx);
685 void r600_flush_emit(struct r600_context *ctx);
686 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
687 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
688 struct pipe_resource *dst, uint64_t dst_offset,
689 struct pipe_resource *src, uint64_t src_offset,
690 unsigned size);
691 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
692 struct pipe_resource *dst, uint64_t offset,
693 unsigned size, uint32_t clear_value);
694 void r600_dma_copy_buffer(struct r600_context *rctx,
695 struct pipe_resource *dst,
696 struct pipe_resource *src,
697 uint64_t dst_offset,
698 uint64_t src_offset,
699 uint64_t size);
700
701 /*
702 * evergreen_hw_context.c
703 */
704 void evergreen_dma_copy_buffer(struct r600_context *rctx,
705 struct pipe_resource *dst,
706 struct pipe_resource *src,
707 uint64_t dst_offset,
708 uint64_t src_offset,
709 uint64_t size);
710 void evergreen_setup_tess_constants(struct r600_context *rctx,
711 const struct pipe_draw_info *info,
712 unsigned *num_patches);
713 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
714 const struct pipe_draw_info *info,
715 unsigned num_patches);
716 void evergreen_set_ls_hs_config(struct r600_context *rctx,
717 struct radeon_winsys_cs *cs,
718 uint32_t ls_hs_config);
719 void evergreen_set_lds_alloc(struct r600_context *rctx,
720 struct radeon_winsys_cs *cs,
721 uint32_t lds_alloc);
722
723 /* r600_state_common.c */
724 void r600_init_common_state_functions(struct r600_context *rctx);
725 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
726 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
727 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
728 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
729 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
730 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
731 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
732 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
733 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
734 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
735 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
736 unsigned num_dw);
737 void r600_vertex_buffers_dirty(struct r600_context *rctx);
738 void r600_sampler_views_dirty(struct r600_context *rctx,
739 struct r600_samplerview_state *state);
740 void r600_sampler_states_dirty(struct r600_context *rctx,
741 struct r600_sampler_states *state);
742 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
743 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
744 uint32_t r600_translate_stencil_op(int s_op);
745 uint32_t r600_translate_fill(uint32_t func);
746 unsigned r600_tex_wrap(unsigned wrap);
747 unsigned r600_tex_mipfilter(unsigned filter);
748 unsigned r600_tex_compare(unsigned compare);
749 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
750 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
751 struct pipe_resource *texture,
752 const struct pipe_surface *templ,
753 unsigned width, unsigned height);
754 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
755 const unsigned char *swizzle_view,
756 boolean vtx);
757 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
758 const unsigned char *swizzle_view,
759 uint32_t *word4_p, uint32_t *yuv_format_p);
760 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
761 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
762
763 /* r600_uvd.c */
764 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
765 const struct pipe_video_codec *decoder);
766
767 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
768 const struct pipe_video_buffer *tmpl);
769
770 /*
771 * Helpers for building command buffers
772 */
773
774 #define PKT3_SET_CONFIG_REG 0x68
775 #define PKT3_SET_CONTEXT_REG 0x69
776 #define PKT3_SET_CTL_CONST 0x6F
777 #define PKT3_SET_LOOP_CONST 0x6C
778
779 #define R600_CONFIG_REG_OFFSET 0x08000
780 #define R600_CONTEXT_REG_OFFSET 0x28000
781 #define R600_CTL_CONST_OFFSET 0x3CFF0
782 #define R600_LOOP_CONST_OFFSET 0X0003E200
783 #define EG_LOOP_CONST_OFFSET 0x0003A200
784
785 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
786 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
787 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
788 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
789 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
790
791 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
792
793 /*Evergreen Compute packet3*/
794 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
795
796 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
797 {
798 cb->buf[cb->num_dw++] = value;
799 }
800
801 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
802 {
803 assert(cb->num_dw+num <= cb->max_num_dw);
804 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
805 cb->num_dw += num;
806 }
807
808 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
809 {
810 assert(reg < R600_CONTEXT_REG_OFFSET);
811 assert(cb->num_dw+2+num <= cb->max_num_dw);
812 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
813 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
814 }
815
816 /**
817 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
818 * shaders.
819 */
820 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
821 {
822 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
823 assert(cb->num_dw+2+num <= cb->max_num_dw);
824 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
825 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
826 }
827
828 /**
829 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
830 * shaders.
831 */
832 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
833 {
834 assert(reg >= R600_CTL_CONST_OFFSET);
835 assert(cb->num_dw+2+num <= cb->max_num_dw);
836 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
837 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
838 }
839
840 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
841 {
842 assert(reg >= R600_LOOP_CONST_OFFSET);
843 assert(cb->num_dw+2+num <= cb->max_num_dw);
844 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
845 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
846 }
847
848 /**
849 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
850 * shaders.
851 */
852 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
853 {
854 assert(reg >= EG_LOOP_CONST_OFFSET);
855 assert(cb->num_dw+2+num <= cb->max_num_dw);
856 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
857 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
858 }
859
860 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
861 {
862 r600_store_config_reg_seq(cb, reg, 1);
863 r600_store_value(cb, value);
864 }
865
866 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
867 {
868 r600_store_context_reg_seq(cb, reg, 1);
869 r600_store_value(cb, value);
870 }
871
872 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
873 {
874 r600_store_ctl_const_seq(cb, reg, 1);
875 r600_store_value(cb, value);
876 }
877
878 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
879 {
880 r600_store_loop_const_seq(cb, reg, 1);
881 r600_store_value(cb, value);
882 }
883
884 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
885 {
886 eg_store_loop_const_seq(cb, reg, 1);
887 r600_store_value(cb, value);
888 }
889
890 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
891 void r600_release_command_buffer(struct r600_command_buffer *cb);
892
893 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
894 {
895 radeon_set_context_reg_seq(cs, reg, num);
896 /* Set the compute bit on the packet header */
897 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
898 }
899
900 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
901 {
902 assert(reg >= R600_CTL_CONST_OFFSET);
903 assert(cs->cdw+2+num <= cs->max_dw);
904 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
905 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
906 }
907
908 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
909 {
910 radeon_compute_set_context_reg_seq(cs, reg, 1);
911 radeon_emit(cs, value);
912 }
913
914 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
915 {
916 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
917 radeon_compute_set_context_reg(cs, reg, value);
918 } else {
919 radeon_set_context_reg(cs, reg, value);
920 }
921 }
922
923 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
924 {
925 radeon_set_ctl_const_seq(cs, reg, 1);
926 radeon_emit(cs, value);
927 }
928
929 /*
930 * common helpers
931 */
932 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
933 {
934 return value * (1 << frac_bits);
935 }
936
937 /* 12.4 fixed-point */
938 static inline unsigned r600_pack_float_12p4(float x)
939 {
940 return x <= 0 ? 0 :
941 x >= 4096 ? 0xffff : x * 16;
942 }
943
944 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
945 static inline bool r600_can_read_depth(struct r600_texture *rtex)
946 {
947 return rtex->resource.b.b.nr_samples <= 1 &&
948 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
949 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
950 }
951
952 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
953 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
954 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
955
956 unsigned r600_conv_prim_to_gs_out(unsigned mode);
957 #endif