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r600: work out target mask at framebuffer bind.
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 56
42
43 #define R600_MAX_IMAGES 8
44 /*
45 * ranges reserved for images on evergreen
46 * first set for the immediate buffers,
47 * second for the actual resources for RESQ.
48 */
49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
51
52 /* read caches */
53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* read-write caches */
57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* engine synchronization */
63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66 #define R600_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
67
68 /* the number of CS dwords for flushing and drawing */
69 #define R600_MAX_FLUSH_CS_DWORDS 18
70 #define R600_MAX_DRAW_CS_DWORDS 58
71 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
72
73 #define EG_MAX_ATOMIC_BUFFERS 8
74
75 #define R600_MAX_USER_CONST_BUFFERS 15
76 #define R600_MAX_DRIVER_CONST_BUFFERS 3
77 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
78 #define R600_MAX_HW_CONST_BUFFERS 16
79
80 /* start driver buffers after user buffers */
81 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
82 #define R600_UCP_SIZE (4*4*8)
83 #define R600_CS_BLOCK_GRID_SIZE (8 * 4)
84 #define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4)
85 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
86
87 /*
88 * We only access this buffer through vtx clauses hence it's fine to exist
89 * at index beyond 15.
90 */
91 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
92 /*
93 * Note GS doesn't use a constant buffer binding, just a resource index,
94 * so it's fine to have it exist at index beyond 15. I.e. it's not actually
95 * a const buffer, just a buffer resource.
96 */
97 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
98 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
99 * of 16 const buffers.
100 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
101 *
102 * In order to support d3d 11 mandated minimum of 15 user const buffers
103 * we'd have to squash all use cases into one driver buffer.
104 */
105 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
106
107 /* HW stages */
108 #define R600_HW_STAGE_PS 0
109 #define R600_HW_STAGE_VS 1
110 #define R600_HW_STAGE_GS 2
111 #define R600_HW_STAGE_ES 3
112 #define EG_HW_STAGE_LS 4
113 #define EG_HW_STAGE_HS 5
114
115 #define R600_NUM_HW_STAGES 4
116 #define EG_NUM_HW_STAGES 6
117
118 struct r600_context;
119 struct r600_bytecode;
120 union r600_shader_key;
121
122 /* This is an atom containing GPU commands that never change.
123 * This is supposed to be copied directly into the CS. */
124 struct r600_command_buffer {
125 uint32_t *buf;
126 unsigned num_dw;
127 unsigned max_num_dw;
128 unsigned pkt_flags;
129 };
130
131 struct r600_db_state {
132 struct r600_atom atom;
133 struct r600_surface *rsurf;
134 };
135
136 struct r600_db_misc_state {
137 struct r600_atom atom;
138 bool occlusion_queries_disabled;
139 bool flush_depthstencil_through_cb;
140 bool flush_depth_inplace;
141 bool flush_stencil_inplace;
142 bool copy_depth, copy_stencil;
143 unsigned copy_sample;
144 unsigned log_samples;
145 unsigned db_shader_control;
146 bool htile_clear;
147 uint8_t ps_conservative_z;
148 };
149
150 struct r600_cb_misc_state {
151 struct r600_atom atom;
152 unsigned cb_color_control; /* this comes from blend state */
153 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
154 unsigned nr_cbufs;
155 unsigned bound_cbufs_target_mask;
156 unsigned nr_ps_color_outputs;
157 unsigned ps_color_export_mask;
158 unsigned image_rat_enabled_mask;
159 unsigned buffer_rat_enabled_mask;
160 bool multiwrite;
161 bool dual_src_blend;
162 };
163
164 struct r600_clip_misc_state {
165 struct r600_atom atom;
166 unsigned pa_cl_clip_cntl; /* from rasterizer */
167 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
168 unsigned clip_plane_enable; /* from rasterizer */
169 unsigned cc_dist_mask; /* from vertex shader */
170 unsigned clip_dist_write; /* from vertex shader */
171 unsigned cull_dist_write; /* from vertex shader */
172 boolean clip_disable; /* from vertex shader */
173 boolean vs_out_viewport; /* from vertex shader */
174 };
175
176 struct r600_alphatest_state {
177 struct r600_atom atom;
178 unsigned sx_alpha_test_control; /* this comes from dsa state */
179 unsigned sx_alpha_ref; /* this comes from dsa state */
180 bool bypass;
181 bool cb0_export_16bpc; /* from set_framebuffer_state */
182 };
183
184 struct r600_vgt_state {
185 struct r600_atom atom;
186 uint32_t vgt_multi_prim_ib_reset_en;
187 uint32_t vgt_multi_prim_ib_reset_indx;
188 uint32_t vgt_indx_offset;
189 bool last_draw_was_indirect;
190 };
191
192 struct r600_blend_color {
193 struct r600_atom atom;
194 struct pipe_blend_color state;
195 };
196
197 struct r600_clip_state {
198 struct r600_atom atom;
199 struct pipe_clip_state state;
200 };
201
202 struct r600_cs_shader_state {
203 struct r600_atom atom;
204 unsigned kernel_index;
205 unsigned pc;
206 struct r600_pipe_compute *shader;
207 };
208
209 struct r600_framebuffer {
210 struct r600_atom atom;
211 struct pipe_framebuffer_state state;
212 unsigned compressed_cb_mask;
213 unsigned nr_samples;
214 bool export_16bpc;
215 bool cb0_is_integer;
216 bool is_msaa_resolve;
217 bool dual_src_blend;
218 bool do_update_surf_dirtiness;
219 };
220
221 struct r600_sample_mask {
222 struct r600_atom atom;
223 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
224 };
225
226 struct r600_config_state {
227 struct r600_atom atom;
228 unsigned sq_gpr_resource_mgmt_1;
229 unsigned sq_gpr_resource_mgmt_2;
230 unsigned sq_gpr_resource_mgmt_3;
231 bool dyn_gpr_enabled;
232 };
233
234 struct r600_stencil_ref
235 {
236 ubyte ref_value[2];
237 ubyte valuemask[2];
238 ubyte writemask[2];
239 };
240
241 struct r600_stencil_ref_state {
242 struct r600_atom atom;
243 struct r600_stencil_ref state;
244 struct pipe_stencil_ref pipe_state;
245 };
246
247 struct r600_shader_stages_state {
248 struct r600_atom atom;
249 unsigned geom_enable;
250 };
251
252 struct r600_gs_rings_state {
253 struct r600_atom atom;
254 unsigned enable;
255 struct pipe_constant_buffer esgs_ring;
256 struct pipe_constant_buffer gsvs_ring;
257 };
258
259 /* This must start from 16. */
260 /* features */
261 #define DBG_NO_CP_DMA (1 << 30)
262 /* shader backend */
263 #define DBG_NO_SB (1 << 21)
264 #define DBG_SB_CS (1 << 22)
265 #define DBG_SB_DRY_RUN (1 << 23)
266 #define DBG_SB_STAT (1 << 24)
267 #define DBG_SB_DUMP (1 << 25)
268 #define DBG_SB_NO_FALLBACK (1 << 26)
269 #define DBG_SB_DISASM (1 << 27)
270 #define DBG_SB_SAFEMATH (1 << 28)
271
272 struct r600_screen {
273 struct r600_common_screen b;
274 bool has_msaa;
275 bool has_compressed_msaa_texturing;
276 bool has_atomics;
277
278 /*for compute global memory binding, we allocate stuff here, instead of
279 * buffers.
280 * XXX: Not sure if this is the best place for global_pool. Also,
281 * it's not thread safe, so it won't work with multiple contexts. */
282 struct compute_memory_pool *global_pool;
283 };
284
285 struct r600_pipe_sampler_view {
286 struct pipe_sampler_view base;
287 struct list_head list;
288 struct r600_resource *tex_resource;
289 uint32_t tex_resource_words[8];
290 bool skip_mip_address_reloc;
291 bool is_stencil_sampler;
292 };
293
294 struct r600_rasterizer_state {
295 struct r600_command_buffer buffer;
296 boolean flatshade;
297 boolean two_side;
298 unsigned sprite_coord_enable;
299 unsigned clip_plane_enable;
300 unsigned pa_sc_line_stipple;
301 unsigned pa_cl_clip_cntl;
302 unsigned pa_su_sc_mode_cntl;
303 float offset_units;
304 float offset_scale;
305 bool offset_enable;
306 bool offset_units_unscaled;
307 bool scissor_enable;
308 bool multisample_enable;
309 bool clip_halfz;
310 bool rasterizer_discard;
311 };
312
313 struct r600_poly_offset_state {
314 struct r600_atom atom;
315 enum pipe_format zs_format;
316 float offset_units;
317 float offset_scale;
318 bool offset_units_unscaled;
319 };
320
321 struct r600_blend_state {
322 struct r600_command_buffer buffer;
323 struct r600_command_buffer buffer_no_blend;
324 unsigned cb_target_mask;
325 unsigned cb_color_control;
326 unsigned cb_color_control_no_blend;
327 bool dual_src_blend;
328 bool alpha_to_one;
329 };
330
331 struct r600_dsa_state {
332 struct r600_command_buffer buffer;
333 unsigned alpha_ref;
334 ubyte valuemask[2];
335 ubyte writemask[2];
336 unsigned zwritemask;
337 unsigned sx_alpha_test_control;
338 };
339
340 struct r600_pipe_shader;
341
342 struct r600_pipe_shader_selector {
343 struct r600_pipe_shader *current;
344
345 struct tgsi_token *tokens;
346 struct pipe_stream_output_info so;
347 struct tgsi_shader_info info;
348
349 unsigned num_shaders;
350
351 enum pipe_shader_type type;
352
353 /* geometry shader properties */
354 enum pipe_prim_type gs_output_prim;
355 unsigned gs_max_out_vertices;
356 unsigned gs_num_invocations;
357
358 /* TCS/VS */
359 uint64_t lds_patch_outputs_written_mask;
360 uint64_t lds_outputs_written_mask;
361 unsigned nr_ps_max_color_exports;
362 };
363
364 struct r600_pipe_sampler_state {
365 uint32_t tex_sampler_words[3];
366 union pipe_color_union border_color;
367 bool border_color_use;
368 bool seamless_cube_map;
369 };
370
371 /* needed for blitter save */
372 #define NUM_TEX_UNITS 16
373
374 struct r600_seamless_cube_map {
375 struct r600_atom atom;
376 bool enabled;
377 };
378
379 struct r600_samplerview_state {
380 struct r600_atom atom;
381 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
382 uint32_t enabled_mask;
383 uint32_t dirty_mask;
384 uint32_t compressed_depthtex_mask; /* which textures are depth */
385 uint32_t compressed_colortex_mask;
386 boolean dirty_buffer_constants;
387 };
388
389 struct r600_sampler_states {
390 struct r600_atom atom;
391 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
392 uint32_t enabled_mask;
393 uint32_t dirty_mask;
394 uint32_t has_bordercolor_mask; /* which states contain the border color */
395 };
396
397 struct r600_textures_info {
398 struct r600_samplerview_state views;
399 struct r600_sampler_states states;
400 bool is_array_sampler[NUM_TEX_UNITS];
401 };
402
403 struct r600_shader_driver_constants_info {
404 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
405 uint32_t *constants;
406 uint32_t alloc_size;
407 bool texture_const_dirty;
408 bool vs_ucp_dirty;
409 bool ps_sample_pos_dirty;
410 bool cs_block_grid_size_dirty;
411 bool tcs_default_levels_dirty;
412 };
413
414 struct r600_constbuf_state
415 {
416 struct r600_atom atom;
417 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
418 uint32_t enabled_mask;
419 uint32_t dirty_mask;
420 };
421
422 struct r600_vertexbuf_state
423 {
424 struct r600_atom atom;
425 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
426 uint32_t enabled_mask; /* non-NULL buffers */
427 uint32_t dirty_mask;
428 };
429
430 /* CSO (constant state object, in other words, immutable state). */
431 struct r600_cso_state
432 {
433 struct r600_atom atom;
434 void *cso; /* e.g. r600_blend_state */
435 struct r600_command_buffer *cb;
436 };
437
438 struct r600_fetch_shader {
439 struct r600_resource *buffer;
440 unsigned offset;
441 };
442
443 struct r600_shader_state {
444 struct r600_atom atom;
445 struct r600_pipe_shader *shader;
446 };
447
448 struct r600_atomic_buffer_state {
449 uint32_t enabled_mask;
450 uint32_t dirty_mask;
451 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
452 };
453
454 struct r600_image_view {
455 struct pipe_image_view base;
456 uint32_t cb_color_base;
457 uint32_t cb_color_pitch;
458 uint32_t cb_color_slice;
459 uint32_t cb_color_view;
460 uint32_t cb_color_info;
461 uint32_t cb_color_attrib;
462 uint32_t cb_color_dim;
463 uint32_t cb_color_fmask;
464 uint32_t cb_color_fmask_slice;
465 uint32_t immed_resource_words[8];
466 uint32_t resource_words[8];
467 bool skip_mip_address_reloc;
468 uint32_t buf_size;
469 };
470
471 struct r600_image_state {
472 struct r600_atom atom;
473 uint32_t enabled_mask;
474 uint32_t dirty_mask;
475 uint32_t compressed_depthtex_mask;
476 uint32_t compressed_colortex_mask;
477 boolean dirty_buffer_constants;
478 struct r600_image_view views[R600_MAX_IMAGES];
479 };
480
481 struct r600_context {
482 struct r600_common_context b;
483 struct r600_screen *screen;
484 struct blitter_context *blitter;
485 struct u_suballocator *allocator_fetch_shader;
486
487 /* Hardware info. */
488 boolean has_vertex_cache;
489 unsigned default_gprs[EG_NUM_HW_STAGES];
490 unsigned current_gprs[EG_NUM_HW_STAGES];
491 unsigned r6xx_num_clause_temp_gprs;
492
493 /* Miscellaneous state objects. */
494 void *custom_dsa_flush;
495 void *custom_blend_resolve;
496 void *custom_blend_decompress;
497 void *custom_blend_fastclear;
498 /* With rasterizer discard, there doesn't have to be a pixel shader.
499 * In that case, we bind this one: */
500 void *dummy_pixel_shader;
501 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
502 * bug where valid CMASK and FMASK are required to be present to avoid
503 * a hardlock in certain operations but aren't actually used
504 * for anything useful. */
505 struct r600_resource *dummy_fmask;
506 struct r600_resource *dummy_cmask;
507
508 /* State binding slots are here. */
509 struct r600_atom *atoms[R600_NUM_ATOMS];
510 /* Dirty atom bitmask for fast tests */
511 uint64_t dirty_atoms;
512 /* States for CS initialization. */
513 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
514 /** Compute specific registers initializations. The start_cs_cmd atom
515 * must be emitted before start_compute_cs_cmd. */
516 struct r600_command_buffer start_compute_cs_cmd;
517 /* Register states. */
518 struct r600_alphatest_state alphatest_state;
519 struct r600_cso_state blend_state;
520 struct r600_blend_color blend_color;
521 struct r600_cb_misc_state cb_misc_state;
522 struct r600_clip_misc_state clip_misc_state;
523 struct r600_clip_state clip_state;
524 struct r600_db_misc_state db_misc_state;
525 struct r600_db_state db_state;
526 struct r600_cso_state dsa_state;
527 struct r600_framebuffer framebuffer;
528 struct r600_poly_offset_state poly_offset_state;
529 struct r600_cso_state rasterizer_state;
530 struct r600_sample_mask sample_mask;
531 struct r600_seamless_cube_map seamless_cube_map;
532 struct r600_config_state config_state;
533 struct r600_stencil_ref_state stencil_ref;
534 struct r600_vgt_state vgt_state;
535 struct r600_atomic_buffer_state atomic_buffer_state;
536 /* only have images on fragment shader */
537 struct r600_image_state fragment_images;
538 struct r600_image_state compute_images;
539 struct r600_image_state fragment_buffers;
540 struct r600_image_state compute_buffers;
541 /* Shaders and shader resources. */
542 struct r600_cso_state vertex_fetch_shader;
543 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
544 struct r600_cs_shader_state cs_shader_state;
545 struct r600_shader_stages_state shader_stages;
546 struct r600_gs_rings_state gs_rings;
547 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
548 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
549
550 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
551
552 /** Vertex buffers for fetch shaders */
553 struct r600_vertexbuf_state vertex_buffer_state;
554 /** Vertex buffers for compute shaders */
555 struct r600_vertexbuf_state cs_vertex_buffer_state;
556
557 /* Additional context states. */
558 unsigned compute_cb_target_mask;
559 struct r600_pipe_shader_selector *ps_shader;
560 struct r600_pipe_shader_selector *vs_shader;
561 struct r600_pipe_shader_selector *gs_shader;
562
563 struct r600_pipe_shader_selector *tcs_shader;
564 struct r600_pipe_shader_selector *tes_shader;
565
566 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
567
568 struct r600_rasterizer_state *rasterizer;
569 bool alpha_to_one;
570 bool force_blend_disable;
571 bool gs_tri_strip_adj_fix;
572 boolean dual_src_blend;
573 unsigned zwritemask;
574 int ps_iter_samples;
575
576 /* The list of all texture buffer objects in this context.
577 * This list is walked when a buffer is invalidated/reallocated and
578 * the GPU addresses are updated. */
579 struct list_head texture_buffers;
580
581 /* Last draw state (-1 = unset). */
582 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
583 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
584 enum pipe_prim_type last_rast_prim;
585 unsigned last_start_instance;
586
587 void *sb_context;
588 struct r600_isa *isa;
589 float sample_positions[4 * 16];
590 float tess_state[8];
591 uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/
592 struct r600_pipe_shader_selector *last_ls;
593 struct r600_pipe_shader_selector *last_tcs;
594 unsigned last_num_tcs_input_cp;
595 unsigned lds_alloc;
596
597 /* Debug state. */
598 bool is_debug;
599 struct radeon_saved_cs last_gfx;
600 struct r600_resource *last_trace_buf;
601 struct r600_resource *trace_buf;
602 unsigned trace_id;
603
604 bool cmd_buf_is_compute;
605 struct pipe_resource *append_fence;
606 uint32_t append_fence_id;
607 };
608
609 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
610 struct r600_command_buffer *cb)
611 {
612 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
613 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
614 cs->current.cdw += cb->num_dw;
615 }
616
617 static inline void r600_set_atom_dirty(struct r600_context *rctx,
618 struct r600_atom *atom,
619 bool dirty)
620 {
621 uint64_t mask;
622
623 assert(atom->id != 0);
624 assert(atom->id < sizeof(mask) * 8);
625 mask = 1ull << atom->id;
626 if (dirty)
627 rctx->dirty_atoms |= mask;
628 else
629 rctx->dirty_atoms &= ~mask;
630 }
631
632 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
633 struct r600_atom *atom)
634 {
635 r600_set_atom_dirty(rctx, atom, true);
636 }
637
638 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
639 {
640 atom->emit(&rctx->b, atom);
641 r600_set_atom_dirty(rctx, atom, false);
642 }
643
644 static inline void r600_set_cso_state(struct r600_context *rctx,
645 struct r600_cso_state *state, void *cso)
646 {
647 state->cso = cso;
648 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
649 }
650
651 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
652 struct r600_cso_state *state, void *cso,
653 struct r600_command_buffer *cb)
654 {
655 state->cb = cb;
656 state->atom.num_dw = cb ? cb->num_dw : 0;
657 r600_set_cso_state(rctx, state, cso);
658 }
659
660 /* compute_memory_pool.c */
661 struct compute_memory_pool;
662 void compute_memory_pool_delete(struct compute_memory_pool* pool);
663 struct compute_memory_pool* compute_memory_pool_new(
664 struct r600_screen *rscreen);
665
666 /* evergreen_state.c */
667 struct pipe_sampler_view *
668 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
669 struct pipe_resource *texture,
670 const struct pipe_sampler_view *state,
671 unsigned width0, unsigned height0,
672 unsigned force_level);
673 void evergreen_init_common_regs(struct r600_context *ctx,
674 struct r600_command_buffer *cb,
675 enum chip_class ctx_chip_class,
676 enum radeon_family ctx_family,
677 int ctx_drm_minor);
678 void cayman_init_common_regs(struct r600_command_buffer *cb,
679 enum chip_class ctx_chip_class,
680 enum radeon_family ctx_family,
681 int ctx_drm_minor);
682
683 void evergreen_init_state_functions(struct r600_context *rctx);
684 void evergreen_init_atom_start_cs(struct r600_context *rctx);
685 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
686 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
687 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
688 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
689 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
690 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
691 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
692 void *evergreen_create_resolve_blend(struct r600_context *rctx);
693 void *evergreen_create_decompress_blend(struct r600_context *rctx);
694 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
695 boolean evergreen_is_format_supported(struct pipe_screen *screen,
696 enum pipe_format format,
697 enum pipe_texture_target target,
698 unsigned sample_count,
699 unsigned usage);
700 void evergreen_init_color_surface(struct r600_context *rctx,
701 struct r600_surface *surf);
702 void evergreen_init_color_surface_rat(struct r600_context *rctx,
703 struct r600_surface *surf);
704 void evergreen_update_db_shader_control(struct r600_context * rctx);
705 bool evergreen_adjust_gprs(struct r600_context *rctx);
706
707 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
708 unsigned nr_cbufs);
709 /* r600_blit.c */
710 void r600_init_blit_functions(struct r600_context *rctx);
711 void r600_decompress_depth_textures(struct r600_context *rctx,
712 struct r600_samplerview_state *textures);
713 void r600_decompress_depth_images(struct r600_context *rctx,
714 struct r600_image_state *images);
715 void r600_decompress_color_textures(struct r600_context *rctx,
716 struct r600_samplerview_state *textures);
717 void r600_decompress_color_images(struct r600_context *rctx,
718 struct r600_image_state *images);
719 void r600_resource_copy_region(struct pipe_context *ctx,
720 struct pipe_resource *dst,
721 unsigned dst_level,
722 unsigned dstx, unsigned dsty, unsigned dstz,
723 struct pipe_resource *src,
724 unsigned src_level,
725 const struct pipe_box *src_box);
726
727 /* r600_shader.c */
728 int r600_pipe_shader_create(struct pipe_context *ctx,
729 struct r600_pipe_shader *shader,
730 union r600_shader_key key);
731
732 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
733
734 /* r600_state.c */
735 struct pipe_sampler_view *
736 r600_create_sampler_view_custom(struct pipe_context *ctx,
737 struct pipe_resource *texture,
738 const struct pipe_sampler_view *state,
739 unsigned width_first_level, unsigned height_first_level);
740 void r600_init_state_functions(struct r600_context *rctx);
741 void r600_init_atom_start_cs(struct r600_context *rctx);
742 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
743 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
744 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
745 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
746 void *r600_create_db_flush_dsa(struct r600_context *rctx);
747 void *r600_create_resolve_blend(struct r600_context *rctx);
748 void *r700_create_resolve_blend(struct r600_context *rctx);
749 void *r600_create_decompress_blend(struct r600_context *rctx);
750 bool r600_adjust_gprs(struct r600_context *rctx);
751 boolean r600_is_format_supported(struct pipe_screen *screen,
752 enum pipe_format format,
753 enum pipe_texture_target target,
754 unsigned sample_count,
755 unsigned usage);
756 void r600_update_db_shader_control(struct r600_context * rctx);
757
758 /* r600_hw_context.c */
759 void r600_context_gfx_flush(void *context, unsigned flags,
760 struct pipe_fence_handle **fence);
761 void r600_begin_new_cs(struct r600_context *ctx);
762 void r600_flush_emit(struct r600_context *ctx);
763 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
764 void r600_emit_pfp_sync_me(struct r600_context *rctx);
765 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
766 struct pipe_resource *dst, uint64_t dst_offset,
767 struct pipe_resource *src, uint64_t src_offset,
768 unsigned size);
769 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
770 struct pipe_resource *dst, uint64_t offset,
771 unsigned size, uint32_t clear_value,
772 enum r600_coherency coher);
773 void r600_dma_copy_buffer(struct r600_context *rctx,
774 struct pipe_resource *dst,
775 struct pipe_resource *src,
776 uint64_t dst_offset,
777 uint64_t src_offset,
778 uint64_t size);
779
780 /*
781 * evergreen_hw_context.c
782 */
783 void evergreen_dma_copy_buffer(struct r600_context *rctx,
784 struct pipe_resource *dst,
785 struct pipe_resource *src,
786 uint64_t dst_offset,
787 uint64_t src_offset,
788 uint64_t size);
789 void evergreen_setup_tess_constants(struct r600_context *rctx,
790 const struct pipe_draw_info *info,
791 unsigned *num_patches);
792 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
793 const struct pipe_draw_info *info,
794 unsigned num_patches);
795 void evergreen_set_ls_hs_config(struct r600_context *rctx,
796 struct radeon_winsys_cs *cs,
797 uint32_t ls_hs_config);
798 void evergreen_set_lds_alloc(struct r600_context *rctx,
799 struct radeon_winsys_cs *cs,
800 uint32_t lds_alloc);
801
802 /* r600_state_common.c */
803 void r600_init_common_state_functions(struct r600_context *rctx);
804 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
805 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
806 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
807 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
808 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
809 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
810 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
811 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
812 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
813 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
814 unsigned num_dw);
815 void r600_vertex_buffers_dirty(struct r600_context *rctx);
816 void r600_sampler_views_dirty(struct r600_context *rctx,
817 struct r600_samplerview_state *state);
818 void r600_sampler_states_dirty(struct r600_context *rctx,
819 struct r600_sampler_states *state);
820 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
821 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
822 uint32_t r600_translate_stencil_op(int s_op);
823 uint32_t r600_translate_fill(uint32_t func);
824 unsigned r600_tex_wrap(unsigned wrap);
825 unsigned r600_tex_mipfilter(unsigned filter);
826 unsigned r600_tex_compare(unsigned compare);
827 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
828 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
829 const unsigned char *swizzle_view,
830 boolean vtx);
831 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
832 const unsigned char *swizzle_view,
833 uint32_t *word4_p, uint32_t *yuv_format_p,
834 bool do_endian_swap);
835 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
836 bool do_endian_swap);
837 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
838
839 /* r600_uvd.c */
840 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
841 const struct pipe_video_codec *decoder);
842
843 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
844 const struct pipe_video_buffer *tmpl);
845
846 /*
847 * Helpers for building command buffers
848 */
849
850 #define PKT3_SET_CONFIG_REG 0x68
851 #define PKT3_SET_CONTEXT_REG 0x69
852 #define PKT3_SET_CTL_CONST 0x6F
853 #define PKT3_SET_LOOP_CONST 0x6C
854
855 #define R600_CONFIG_REG_OFFSET 0x08000
856 #define R600_CONTEXT_REG_OFFSET 0x28000
857 #define R600_CTL_CONST_OFFSET 0x3CFF0
858 #define R600_LOOP_CONST_OFFSET 0X0003E200
859 #define EG_LOOP_CONST_OFFSET 0x0003A200
860
861 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
862 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
863 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
864 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
865 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
866
867 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
868
869 /*Evergreen Compute packet3*/
870 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
871
872 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
873 {
874 cb->buf[cb->num_dw++] = value;
875 }
876
877 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
878 {
879 assert(cb->num_dw+num <= cb->max_num_dw);
880 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
881 cb->num_dw += num;
882 }
883
884 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
885 {
886 assert(reg < R600_CONTEXT_REG_OFFSET);
887 assert(cb->num_dw+2+num <= cb->max_num_dw);
888 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
889 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
890 }
891
892 /**
893 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
894 * shaders.
895 */
896 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
897 {
898 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
899 assert(cb->num_dw+2+num <= cb->max_num_dw);
900 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
901 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
902 }
903
904 /**
905 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
906 * shaders.
907 */
908 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
909 {
910 assert(reg >= R600_CTL_CONST_OFFSET);
911 assert(cb->num_dw+2+num <= cb->max_num_dw);
912 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
913 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
914 }
915
916 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
917 {
918 assert(reg >= R600_LOOP_CONST_OFFSET);
919 assert(cb->num_dw+2+num <= cb->max_num_dw);
920 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
921 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
922 }
923
924 /**
925 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
926 * shaders.
927 */
928 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
929 {
930 assert(reg >= EG_LOOP_CONST_OFFSET);
931 assert(cb->num_dw+2+num <= cb->max_num_dw);
932 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
933 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
934 }
935
936 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
937 {
938 r600_store_config_reg_seq(cb, reg, 1);
939 r600_store_value(cb, value);
940 }
941
942 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
943 {
944 r600_store_context_reg_seq(cb, reg, 1);
945 r600_store_value(cb, value);
946 }
947
948 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
949 {
950 r600_store_ctl_const_seq(cb, reg, 1);
951 r600_store_value(cb, value);
952 }
953
954 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
955 {
956 r600_store_loop_const_seq(cb, reg, 1);
957 r600_store_value(cb, value);
958 }
959
960 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
961 {
962 eg_store_loop_const_seq(cb, reg, 1);
963 r600_store_value(cb, value);
964 }
965
966 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
967 void r600_release_command_buffer(struct r600_command_buffer *cb);
968
969 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
970 {
971 radeon_set_context_reg_seq(cs, reg, num);
972 /* Set the compute bit on the packet header */
973 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
974 }
975
976 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
977 {
978 assert(reg >= R600_CTL_CONST_OFFSET);
979 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
980 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
981 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
982 }
983
984 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
985 {
986 radeon_compute_set_context_reg_seq(cs, reg, 1);
987 radeon_emit(cs, value);
988 }
989
990 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
991 {
992 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
993 radeon_compute_set_context_reg(cs, reg, value);
994 } else {
995 radeon_set_context_reg(cs, reg, value);
996 }
997 }
998
999 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1000 {
1001 radeon_set_ctl_const_seq(cs, reg, 1);
1002 radeon_emit(cs, value);
1003 }
1004
1005 /*
1006 * common helpers
1007 */
1008
1009 /* 12.4 fixed-point */
1010 static inline unsigned r600_pack_float_12p4(float x)
1011 {
1012 return x <= 0 ? 0 :
1013 x >= 4096 ? 0xffff : x * 16;
1014 }
1015
1016 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
1017 {
1018 switch (coher) {
1019 default:
1020 case R600_COHERENCY_NONE:
1021 return 0;
1022 case R600_COHERENCY_SHADER:
1023 return R600_CONTEXT_INV_CONST_CACHE |
1024 R600_CONTEXT_INV_VERTEX_CACHE |
1025 R600_CONTEXT_INV_TEX_CACHE |
1026 R600_CONTEXT_STREAMOUT_FLUSH;
1027 case R600_COHERENCY_CB_META:
1028 return R600_CONTEXT_FLUSH_AND_INV_CB |
1029 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1030 }
1031 }
1032
1033 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1034 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1035 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1036
1037 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1038
1039 void eg_trace_emit(struct r600_context *rctx);
1040 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1041 unsigned flags);
1042
1043 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
1044 const struct tgsi_token *tokens,
1045 unsigned pipe_shader_type);
1046 int r600_shader_select(struct pipe_context *ctx,
1047 struct r600_pipe_shader_selector* sel,
1048 bool *dirty);
1049
1050 void r600_delete_shader_selector(struct pipe_context *ctx,
1051 struct r600_pipe_shader_selector *sel);
1052
1053 struct r600_shader_atomic;
1054 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1055 struct r600_pipe_shader *cs_shader,
1056 struct r600_shader_atomic *combined_atomics,
1057 uint8_t *atomic_used_mask_p);
1058 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1059 bool is_compute,
1060 struct r600_shader_atomic *combined_atomics,
1061 uint8_t *atomic_used_mask_p);
1062 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only);
1063
1064 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type);
1065 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only);
1066 #endif