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r600g: cleanup create_sampler_state functions
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
31 #include "r600.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
36
37 #define R600_NUM_ATOMS 36
38
39 #define R600_MAX_CONST_BUFFERS 2
40 #define R600_MAX_CONST_BUFFER_SIZE 4096
41
42 #ifdef PIPE_ARCH_BIG_ENDIAN
43 #define R600_BIG_ENDIAN 1
44 #else
45 #define R600_BIG_ENDIAN 0
46 #endif
47
48 struct r600_shader_key;
49
50 /* This encapsulates a state or an operation which can emitted into the GPU
51 * command stream. It's not limited to states only, it can be used for anything
52 * that wants to write commands into the CS (e.g. cache flushes). */
53 struct r600_atom {
54 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
55 unsigned id;
56 unsigned num_dw;
57 bool dirty;
58 };
59
60 /* This is an atom containing GPU commands that never change.
61 * This is supposed to be copied directly into the CS. */
62 struct r600_command_buffer {
63 uint32_t *buf;
64 unsigned num_dw;
65 unsigned max_num_dw;
66 unsigned pkt_flags;
67 };
68
69 struct r600_db_misc_state {
70 struct r600_atom atom;
71 bool occlusion_query_enabled;
72 bool flush_depthstencil_through_cb;
73 bool copy_depth, copy_stencil;
74 unsigned copy_sample;
75 unsigned log_samples;
76 unsigned db_shader_control;
77 };
78
79 struct r600_cb_misc_state {
80 struct r600_atom atom;
81 unsigned cb_color_control; /* this comes from blend state */
82 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
83 unsigned nr_cbufs;
84 unsigned nr_ps_color_outputs;
85 bool multiwrite;
86 bool dual_src_blend;
87 };
88
89 struct r600_clip_misc_state {
90 struct r600_atom atom;
91 unsigned pa_cl_clip_cntl; /* from rasterizer */
92 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
93 unsigned clip_plane_enable; /* from rasterizer */
94 unsigned clip_dist_write; /* from vertex shader */
95 };
96
97 struct r600_alphatest_state {
98 struct r600_atom atom;
99 unsigned sx_alpha_test_control; /* this comes from dsa state */
100 unsigned sx_alpha_ref; /* this comes from dsa state */
101 bool bypass;
102 bool cb0_export_16bpc; /* from set_framebuffer_state */
103 };
104
105 struct r600_vgt_state {
106 struct r600_atom atom;
107 uint32_t vgt_multi_prim_ib_reset_en;
108 uint32_t vgt_multi_prim_ib_reset_indx;
109 };
110
111 struct r600_vgt2_state {
112 struct r600_atom atom;
113 uint32_t vgt_indx_offset;
114 };
115
116 struct r600_blend_color {
117 struct r600_atom atom;
118 struct pipe_blend_color state;
119 };
120
121 struct r600_clip_state {
122 struct r600_atom atom;
123 struct pipe_clip_state state;
124 };
125
126 struct r600_cs_shader_state {
127 struct r600_atom atom;
128 unsigned kernel_index;
129 struct r600_pipe_compute *shader;
130 };
131
132 struct r600_framebuffer {
133 struct r600_atom atom;
134 struct pipe_framebuffer_state state;
135 unsigned compressed_cb_mask;
136 unsigned nr_samples;
137 bool export_16bpc;
138 bool cb0_is_integer;
139 bool is_msaa_resolve;
140 };
141
142 struct r600_sample_mask {
143 struct r600_atom atom;
144 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
145 };
146
147 struct r600_config_state {
148 struct r600_atom atom;
149 unsigned sq_gpr_resource_mgmt_1;
150 };
151
152 struct r600_stencil_ref
153 {
154 ubyte ref_value[2];
155 ubyte valuemask[2];
156 ubyte writemask[2];
157 };
158
159 struct r600_stencil_ref_state {
160 struct r600_atom atom;
161 struct r600_stencil_ref state;
162 struct pipe_stencil_ref pipe_state;
163 };
164
165 struct r600_viewport_state {
166 struct r600_atom atom;
167 struct pipe_viewport_state state;
168 };
169
170 struct compute_memory_pool;
171 void compute_memory_pool_delete(struct compute_memory_pool* pool);
172 struct compute_memory_pool* compute_memory_pool_new(
173 struct r600_screen *rscreen);
174
175 struct r600_pipe_fences {
176 struct r600_resource *bo;
177 unsigned *data;
178 unsigned next_index;
179 /* linked list of preallocated blocks */
180 struct list_head blocks;
181 /* linked list of freed fences */
182 struct list_head pool;
183 pipe_mutex mutex;
184 };
185
186 struct r600_screen {
187 struct pipe_screen screen;
188 struct radeon_winsys *ws;
189 unsigned family;
190 enum chip_class chip_class;
191 struct radeon_info info;
192 bool has_streamout;
193 struct r600_tiling_info tiling_info;
194 struct r600_pipe_fences fences;
195
196 /*for compute global memory binding, we allocate stuff here, instead of
197 * buffers.
198 * XXX: Not sure if this is the best place for global_pool. Also,
199 * it's not thread safe, so it won't work with multiple contexts. */
200 struct compute_memory_pool *global_pool;
201 };
202
203 struct r600_pipe_sampler_view {
204 struct pipe_sampler_view base;
205 struct r600_resource *tex_resource;
206 uint32_t tex_resource_words[8];
207 };
208
209 struct r600_rasterizer_state {
210 struct r600_command_buffer buffer;
211 boolean flatshade;
212 boolean two_side;
213 unsigned sprite_coord_enable;
214 unsigned clip_plane_enable;
215 unsigned pa_sc_line_stipple;
216 unsigned pa_cl_clip_cntl;
217 float offset_units;
218 float offset_scale;
219 bool offset_enable;
220 bool scissor_enable;
221 bool multisample_enable;
222 };
223
224 struct r600_poly_offset_state {
225 struct r600_atom atom;
226 enum pipe_format zs_format;
227 float offset_units;
228 float offset_scale;
229 };
230
231 struct r600_blend_state {
232 struct r600_command_buffer buffer;
233 struct r600_command_buffer buffer_no_blend;
234 unsigned cb_target_mask;
235 unsigned cb_color_control;
236 unsigned cb_color_control_no_blend;
237 bool dual_src_blend;
238 bool alpha_to_one;
239 };
240
241 struct r600_dsa_state {
242 struct r600_command_buffer buffer;
243 unsigned alpha_ref;
244 ubyte valuemask[2];
245 ubyte writemask[2];
246 unsigned sx_alpha_test_control;
247 };
248
249 struct r600_pipe_shader;
250
251 struct r600_pipe_shader_selector {
252 struct r600_pipe_shader *current;
253
254 struct tgsi_token *tokens;
255 struct pipe_stream_output_info so;
256
257 unsigned num_shaders;
258
259 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
260 unsigned type;
261
262 unsigned nr_ps_max_color_exports;
263 };
264
265 struct r600_pipe_sampler_state {
266 uint32_t tex_sampler_words[3];
267 union pipe_color_union border_color;
268 bool border_color_use;
269 bool seamless_cube_map;
270 };
271
272 /* needed for blitter save */
273 #define NUM_TEX_UNITS 16
274
275 struct r600_seamless_cube_map {
276 struct r600_atom atom;
277 bool enabled;
278 };
279
280 struct r600_samplerview_state {
281 struct r600_atom atom;
282 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
283 uint32_t enabled_mask;
284 uint32_t dirty_mask;
285 uint32_t compressed_depthtex_mask; /* which textures are depth */
286 uint32_t compressed_colortex_mask;
287 };
288
289 struct r600_sampler_states {
290 struct r600_atom atom;
291 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
292 uint32_t enabled_mask;
293 uint32_t dirty_mask;
294 uint32_t has_bordercolor_mask; /* which states contain the border color */
295 };
296
297 struct r600_textures_info {
298 struct r600_samplerview_state views;
299 struct r600_sampler_states states;
300 bool is_array_sampler[NUM_TEX_UNITS];
301 };
302
303 struct r600_fence {
304 struct pipe_reference reference;
305 unsigned index; /* in the shared bo */
306 struct r600_resource *sleep_bo;
307 struct list_head head;
308 };
309
310 #define FENCE_BLOCK_SIZE 16
311
312 struct r600_fence_block {
313 struct r600_fence fences[FENCE_BLOCK_SIZE];
314 struct list_head head;
315 };
316
317 #define R600_CONSTANT_ARRAY_SIZE 256
318 #define R600_RESOURCE_ARRAY_SIZE 160
319
320 struct r600_constbuf_state
321 {
322 struct r600_atom atom;
323 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
324 uint32_t enabled_mask;
325 uint32_t dirty_mask;
326 };
327
328 struct r600_vertexbuf_state
329 {
330 struct r600_atom atom;
331 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
332 uint32_t enabled_mask; /* non-NULL buffers */
333 uint32_t dirty_mask;
334 };
335
336 /* CSO (constant state object, in other words, immutable state). */
337 struct r600_cso_state
338 {
339 struct r600_atom atom;
340 void *cso; /* e.g. r600_blend_state */
341 struct r600_command_buffer *cb;
342 };
343
344 struct r600_scissor_state
345 {
346 struct r600_atom atom;
347 struct pipe_scissor_state scissor;
348 bool enable; /* r6xx only */
349 };
350
351 struct r600_context {
352 struct pipe_context context;
353 struct r600_screen *screen;
354 struct radeon_winsys *ws;
355 struct radeon_winsys_cs *cs;
356 struct blitter_context *blitter;
357 struct u_upload_mgr *uploader;
358 struct util_slab_mempool pool_transfers;
359
360 /* Hardware info. */
361 enum radeon_family family;
362 enum chip_class chip_class;
363 boolean has_vertex_cache;
364 boolean keep_tiling_flags;
365 unsigned default_ps_gprs, default_vs_gprs;
366 unsigned r6xx_num_clause_temp_gprs;
367 unsigned backend_mask;
368 unsigned max_db; /* for OQ */
369
370 /* Miscellaneous state objects. */
371 void *custom_dsa_flush;
372 void *custom_blend_resolve;
373 void *custom_blend_decompress;
374 /* With rasterizer discard, there doesn't have to be a pixel shader.
375 * In that case, we bind this one: */
376 void *dummy_pixel_shader;
377 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
378 * bug where valid CMASK and FMASK are required to be present to avoid
379 * a hardlock in certain operations but aren't actually used
380 * for anything useful. */
381 struct r600_resource *dummy_fmask;
382 struct r600_resource *dummy_cmask;
383
384 /* State binding slots are here. */
385 struct r600_atom *atoms[R600_NUM_ATOMS];
386 /* States for CS initialization. */
387 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
388 /** Compute specific registers initializations. The start_cs_cmd atom
389 * must be emitted before start_compute_cs_cmd. */
390 struct r600_command_buffer start_compute_cs_cmd;
391 /* Register states. */
392 struct r600_alphatest_state alphatest_state;
393 struct r600_cso_state blend_state;
394 struct r600_blend_color blend_color;
395 struct r600_cb_misc_state cb_misc_state;
396 struct r600_clip_misc_state clip_misc_state;
397 struct r600_clip_state clip_state;
398 struct r600_db_misc_state db_misc_state;
399 struct r600_cso_state dsa_state;
400 struct r600_framebuffer framebuffer;
401 struct r600_poly_offset_state poly_offset_state;
402 struct r600_cso_state rasterizer_state;
403 struct r600_sample_mask sample_mask;
404 struct r600_scissor_state scissor;
405 struct r600_seamless_cube_map seamless_cube_map;
406 struct r600_config_state config_state;
407 struct r600_stencil_ref_state stencil_ref;
408 struct r600_vgt_state vgt_state;
409 struct r600_vgt2_state vgt2_state;
410 struct r600_viewport_state viewport;
411 /* Shaders and shader resources. */
412 struct r600_cso_state vertex_fetch_shader;
413 struct r600_cs_shader_state cs_shader_state;
414 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
415 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
416 /** Vertex buffers for fetch shaders */
417 struct r600_vertexbuf_state vertex_buffer_state;
418 /** Vertex buffers for compute shaders */
419 struct r600_vertexbuf_state cs_vertex_buffer_state;
420
421 /* Additional context states. */
422 unsigned flags;
423 unsigned compute_cb_target_mask;
424 struct r600_pipe_shader_selector *ps_shader;
425 struct r600_pipe_shader_selector *vs_shader;
426 struct r600_rasterizer_state *rasterizer;
427 bool alpha_to_one;
428 bool force_blend_disable;
429 boolean dual_src_blend;
430
431 /* Index buffer. */
432 struct pipe_index_buffer index_buffer;
433
434 /* Last draw state (-1 = unset). */
435 int last_primitive_type; /* Last primitive type used in draw_vbo. */
436 int last_start_instance;
437
438 /* Queries. */
439 /* The list of active queries. Only one query of each type can be active. */
440 int num_occlusion_queries;
441 /* Manage queries in two separate groups:
442 * The timer ones and the others (streamout, occlusion).
443 *
444 * We do this because we should only suspend non-timer queries for u_blitter,
445 * and later if the non-timer queries are suspended, the context flush should
446 * only suspend and resume the timer queries. */
447 struct list_head active_timer_queries;
448 unsigned num_cs_dw_timer_queries_suspend;
449 struct list_head active_nontimer_queries;
450 unsigned num_cs_dw_nontimer_queries_suspend;
451 /* Flags if queries have been suspended. */
452 bool timer_queries_suspended;
453 bool nontimer_queries_suspended;
454
455 /* Render condition. */
456 struct pipe_query *current_render_cond;
457 unsigned current_render_cond_mode;
458 boolean predicate_drawing;
459
460 /* Streamout state. */
461 unsigned num_cs_dw_streamout_end;
462 unsigned num_so_targets;
463 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
464 boolean streamout_start;
465 unsigned streamout_append_bitmask;
466 bool streamout_suspended;
467
468 /* Deprecated state management. */
469 struct r600_range *range;
470 unsigned nblocks;
471 struct r600_block **blocks;
472 struct list_head dirty;
473 struct list_head enable_list;
474 unsigned pm4_dirty_cdwords;
475 };
476
477 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
478 struct r600_command_buffer *cb)
479 {
480 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
481 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
482 cs->cdw += cb->num_dw;
483 }
484
485 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
486 {
487 atom->emit(rctx, atom);
488 atom->dirty = false;
489 }
490
491 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
492 {
493 state->cso = cso;
494 state->atom.dirty = cso != NULL;
495 }
496
497 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
498 struct r600_command_buffer *cb)
499 {
500 state->cb = cb;
501 state->atom.num_dw = cb->num_dw;
502 r600_set_cso_state(state, cso);
503 }
504
505 /* evergreen_state.c */
506 struct pipe_sampler_view *
507 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
508 struct pipe_resource *texture,
509 const struct pipe_sampler_view *state,
510 unsigned width0, unsigned height0);
511 void evergreen_init_common_regs(struct r600_command_buffer *cb,
512 enum chip_class ctx_chip_class,
513 enum radeon_family ctx_family,
514 int ctx_drm_minor);
515
516 void evergreen_init_state_functions(struct r600_context *rctx);
517 void evergreen_init_atom_start_cs(struct r600_context *rctx);
518 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
519 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
520 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
521 void *evergreen_create_resolve_blend(struct r600_context *rctx);
522 void *evergreen_create_decompress_blend(struct r600_context *rctx);
523 boolean evergreen_is_format_supported(struct pipe_screen *screen,
524 enum pipe_format format,
525 enum pipe_texture_target target,
526 unsigned sample_count,
527 unsigned usage);
528 void evergreen_init_color_surface(struct r600_context *rctx,
529 struct r600_surface *surf);
530 void evergreen_init_color_surface_rat(struct r600_context *rctx,
531 struct r600_surface *surf);
532 void evergreen_update_db_shader_control(struct r600_context * rctx);
533
534 /* r600_blit.c */
535 void r600_copy_buffer(struct pipe_context *ctx, struct
536 pipe_resource *dst, unsigned dstx,
537 struct pipe_resource *src, const struct pipe_box *src_box);
538 void r600_init_blit_functions(struct r600_context *rctx);
539 void r600_blit_decompress_depth(struct pipe_context *ctx,
540 struct r600_texture *texture,
541 struct r600_texture *staging,
542 unsigned first_level, unsigned last_level,
543 unsigned first_layer, unsigned last_layer,
544 unsigned first_sample, unsigned last_sample);
545 void r600_decompress_depth_textures(struct r600_context *rctx,
546 struct r600_samplerview_state *textures);
547 void r600_decompress_color_textures(struct r600_context *rctx,
548 struct r600_samplerview_state *textures);
549
550 /* r600_buffer.c */
551 bool r600_init_resource(struct r600_screen *rscreen,
552 struct r600_resource *res,
553 unsigned size, unsigned alignment,
554 unsigned bind, unsigned usage);
555 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
556 const struct pipe_resource *templ,
557 unsigned alignment);
558
559 /* r600_pipe.c */
560 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
561 unsigned flags);
562
563 /* r600_query.c */
564 void r600_init_query_functions(struct r600_context *rctx);
565 void r600_suspend_nontimer_queries(struct r600_context *ctx);
566 void r600_resume_nontimer_queries(struct r600_context *ctx);
567 void r600_suspend_timer_queries(struct r600_context *ctx);
568 void r600_resume_timer_queries(struct r600_context *ctx);
569
570 /* r600_resource.c */
571 void r600_init_context_resource_functions(struct r600_context *r600);
572
573 /* r600_shader.c */
574 int r600_pipe_shader_create(struct pipe_context *ctx,
575 struct r600_pipe_shader *shader,
576 struct r600_shader_key key);
577 #ifdef HAVE_OPENCL
578 int r600_compute_shader_create(struct pipe_context * ctx,
579 LLVMModuleRef mod, struct r600_bytecode * bytecode);
580 #endif
581 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
582
583 /* r600_state.c */
584 struct pipe_sampler_view *
585 r600_create_sampler_view_custom(struct pipe_context *ctx,
586 struct pipe_resource *texture,
587 const struct pipe_sampler_view *state,
588 unsigned width_first_level, unsigned height_first_level);
589 void r600_init_state_functions(struct r600_context *rctx);
590 void r600_init_atom_start_cs(struct r600_context *rctx);
591 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
592 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
593 void *r600_create_db_flush_dsa(struct r600_context *rctx);
594 void *r600_create_resolve_blend(struct r600_context *rctx);
595 void *r700_create_resolve_blend(struct r600_context *rctx);
596 void *r600_create_decompress_blend(struct r600_context *rctx);
597 void r600_adjust_gprs(struct r600_context *rctx);
598 boolean r600_is_format_supported(struct pipe_screen *screen,
599 enum pipe_format format,
600 enum pipe_texture_target target,
601 unsigned sample_count,
602 unsigned usage);
603 void r600_update_db_shader_control(struct r600_context * rctx);
604
605 /* r600_texture.c */
606 void r600_init_screen_texture_functions(struct pipe_screen *screen);
607 void r600_init_surface_functions(struct r600_context *r600);
608 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
609 const unsigned char *swizzle_view,
610 uint32_t *word4_p, uint32_t *yuv_format_p);
611 unsigned r600_texture_get_offset(struct r600_texture *rtex,
612 unsigned level, unsigned layer);
613 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
614 struct pipe_resource *texture,
615 const struct pipe_surface *templ,
616 unsigned width, unsigned height);
617
618 /* r600_state_common.c */
619 void r600_init_common_state_functions(struct r600_context *rctx);
620 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
621 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
622 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
623 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
624 void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom);
625 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
626 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
627 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
628 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
629 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
630 unsigned num_dw);
631 void r600_vertex_buffers_dirty(struct r600_context *rctx);
632 void r600_sampler_views_dirty(struct r600_context *rctx,
633 struct r600_samplerview_state *state);
634 void r600_sampler_states_dirty(struct r600_context *rctx,
635 struct r600_sampler_states *state);
636 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
637 void r600_draw_rectangle(struct blitter_context *blitter,
638 int x1, int y1, int x2, int y2, float depth,
639 enum blitter_attrib_type type, const union pipe_color_union *attrib);
640 uint32_t r600_translate_stencil_op(int s_op);
641 uint32_t r600_translate_fill(uint32_t func);
642 unsigned r600_tex_wrap(unsigned wrap);
643 unsigned r600_tex_filter(unsigned filter);
644 unsigned r600_tex_mipfilter(unsigned filter);
645 unsigned r600_tex_compare(unsigned compare);
646
647 /*
648 * Helpers for building command buffers
649 */
650
651 #define PKT3_SET_CONFIG_REG 0x68
652 #define PKT3_SET_CONTEXT_REG 0x69
653 #define PKT3_SET_CTL_CONST 0x6F
654 #define PKT3_SET_LOOP_CONST 0x6C
655
656 #define R600_CONFIG_REG_OFFSET 0x08000
657 #define R600_CONTEXT_REG_OFFSET 0x28000
658 #define R600_CTL_CONST_OFFSET 0x3CFF0
659 #define R600_LOOP_CONST_OFFSET 0X0003E200
660 #define EG_LOOP_CONST_OFFSET 0x0003A200
661
662 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
663 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
664 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
665 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
666 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
667
668 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
669
670 /*Evergreen Compute packet3*/
671 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
672
673 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
674 {
675 cb->buf[cb->num_dw++] = value;
676 }
677
678 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
679 {
680 assert(reg < R600_CONTEXT_REG_OFFSET);
681 assert(cb->num_dw+2+num <= cb->max_num_dw);
682 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
683 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
684 }
685
686 /**
687 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
688 * shaders.
689 */
690 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
691 {
692 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
693 assert(cb->num_dw+2+num <= cb->max_num_dw);
694 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
695 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
696 }
697
698 /**
699 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
700 * shaders.
701 */
702 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
703 {
704 assert(reg >= R600_CTL_CONST_OFFSET);
705 assert(cb->num_dw+2+num <= cb->max_num_dw);
706 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
707 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
708 }
709
710 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
711 {
712 assert(reg >= R600_LOOP_CONST_OFFSET);
713 assert(cb->num_dw+2+num <= cb->max_num_dw);
714 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
715 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
716 }
717
718 /**
719 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
720 * shaders.
721 */
722 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
723 {
724 assert(reg >= EG_LOOP_CONST_OFFSET);
725 assert(cb->num_dw+2+num <= cb->max_num_dw);
726 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
727 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
728 }
729
730 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
731 {
732 r600_store_config_reg_seq(cb, reg, 1);
733 r600_store_value(cb, value);
734 }
735
736 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
737 {
738 r600_store_context_reg_seq(cb, reg, 1);
739 r600_store_value(cb, value);
740 }
741
742 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
743 {
744 r600_store_ctl_const_seq(cb, reg, 1);
745 r600_store_value(cb, value);
746 }
747
748 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
749 {
750 r600_store_loop_const_seq(cb, reg, 1);
751 r600_store_value(cb, value);
752 }
753
754 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
755 {
756 eg_store_loop_const_seq(cb, reg, 1);
757 r600_store_value(cb, value);
758 }
759
760 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
761 void r600_release_command_buffer(struct r600_command_buffer *cb);
762
763 /*
764 * Helpers for emitting state into a command stream directly.
765 */
766
767 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
768 enum radeon_bo_usage usage)
769 {
770 assert(usage);
771 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
772 }
773
774 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
775 {
776 cs->buf[cs->cdw++] = value;
777 }
778
779 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
780 {
781 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
782 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
783 cs->cdw += num;
784 }
785
786 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
787 {
788 assert(reg < R600_CONTEXT_REG_OFFSET);
789 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
790 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
791 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
792 }
793
794 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
795 {
796 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
797 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
798 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
799 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
800 }
801
802 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
803 {
804 r600_write_context_reg_seq(cs, reg, num);
805 /* Set the compute bit on the packet header */
806 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
807 }
808
809 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
810 {
811 assert(reg >= R600_CTL_CONST_OFFSET);
812 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
813 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
814 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
815 }
816
817 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
818 {
819 r600_write_config_reg_seq(cs, reg, 1);
820 r600_write_value(cs, value);
821 }
822
823 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
824 {
825 r600_write_context_reg_seq(cs, reg, 1);
826 r600_write_value(cs, value);
827 }
828
829 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
830 {
831 r600_write_compute_context_reg_seq(cs, reg, 1);
832 r600_write_value(cs, value);
833 }
834
835 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
836 {
837 r600_write_ctl_const_seq(cs, reg, 1);
838 r600_write_value(cs, value);
839 }
840
841 /*
842 * common helpers
843 */
844 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
845 {
846 return value * (1 << frac_bits);
847 }
848 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
849
850 static inline unsigned r600_tex_aniso_filter(unsigned filter)
851 {
852 if (filter <= 1) return 0;
853 if (filter <= 2) return 1;
854 if (filter <= 4) return 2;
855 if (filter <= 8) return 3;
856 /* else */ return 4;
857 }
858
859 /* 12.4 fixed-point */
860 static INLINE unsigned r600_pack_float_12p4(float x)
861 {
862 return x <= 0 ? 0 :
863 x >= 4096 ? 0xffff : x * 16;
864 }
865
866 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
867 {
868 struct r600_screen *rscreen = (struct r600_screen*)screen;
869 struct r600_resource *rresource = (struct r600_resource*)resource;
870
871 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
872 }
873
874 #endif