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radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
36 #include "util/u_memory.h"
37
38 #include "tgsi/tgsi_scan.h"
39
40 #define R600_NUM_ATOMS 52
41
42 /* read caches */
43 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
44 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
45 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
46 /* read-write caches */
47 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
48 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
49 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
52 /* engine synchronization */
53 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
54 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
55 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
56
57 /* the number of CS dwords for flushing and drawing */
58 #define R600_MAX_FLUSH_CS_DWORDS 18
59 #define R600_MAX_DRAW_CS_DWORDS 58
60 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
61
62 #define R600_MAX_USER_CONST_BUFFERS 13
63 #define R600_MAX_DRIVER_CONST_BUFFERS 3
64 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
65
66 /* start driver buffers after user buffers */
67 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
68 #define R600_UCP_SIZE (4*4*8)
69 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
70
71 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
72 /*
73 * Note GS doesn't use a constant buffer binding, just a resource index,
74 * so it's fine to have it exist at index 16.
75 */
76 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
77 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
78 * of 16 const buffers.
79 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
80 *
81 * In order to support d3d 11 mandated minimum of 15 user const buffers
82 * we'd have to squash all use cases into one driver buffer.
83 */
84 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
85
86 /* HW stages */
87 #define R600_HW_STAGE_PS 0
88 #define R600_HW_STAGE_VS 1
89 #define R600_HW_STAGE_GS 2
90 #define R600_HW_STAGE_ES 3
91 #define EG_HW_STAGE_LS 4
92 #define EG_HW_STAGE_HS 5
93
94 #define R600_NUM_HW_STAGES 4
95 #define EG_NUM_HW_STAGES 6
96
97 struct r600_context;
98 struct r600_bytecode;
99 union r600_shader_key;
100
101 /* This is an atom containing GPU commands that never change.
102 * This is supposed to be copied directly into the CS. */
103 struct r600_command_buffer {
104 uint32_t *buf;
105 unsigned num_dw;
106 unsigned max_num_dw;
107 unsigned pkt_flags;
108 };
109
110 struct r600_db_state {
111 struct r600_atom atom;
112 struct r600_surface *rsurf;
113 };
114
115 struct r600_db_misc_state {
116 struct r600_atom atom;
117 bool occlusion_queries_disabled;
118 bool flush_depthstencil_through_cb;
119 bool flush_depth_inplace;
120 bool flush_stencil_inplace;
121 bool copy_depth, copy_stencil;
122 unsigned copy_sample;
123 unsigned log_samples;
124 unsigned db_shader_control;
125 bool htile_clear;
126 uint8_t ps_conservative_z;
127 };
128
129 struct r600_cb_misc_state {
130 struct r600_atom atom;
131 unsigned cb_color_control; /* this comes from blend state */
132 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
133 unsigned nr_cbufs;
134 unsigned nr_ps_color_outputs;
135 bool multiwrite;
136 bool dual_src_blend;
137 };
138
139 struct r600_clip_misc_state {
140 struct r600_atom atom;
141 unsigned pa_cl_clip_cntl; /* from rasterizer */
142 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
143 unsigned clip_plane_enable; /* from rasterizer */
144 unsigned clip_dist_write; /* from vertex shader */
145 boolean clip_disable; /* from vertex shader */
146 boolean vs_out_viewport; /* from vertex shader */
147 };
148
149 struct r600_alphatest_state {
150 struct r600_atom atom;
151 unsigned sx_alpha_test_control; /* this comes from dsa state */
152 unsigned sx_alpha_ref; /* this comes from dsa state */
153 bool bypass;
154 bool cb0_export_16bpc; /* from set_framebuffer_state */
155 };
156
157 struct r600_vgt_state {
158 struct r600_atom atom;
159 uint32_t vgt_multi_prim_ib_reset_en;
160 uint32_t vgt_multi_prim_ib_reset_indx;
161 uint32_t vgt_indx_offset;
162 bool last_draw_was_indirect;
163 };
164
165 struct r600_blend_color {
166 struct r600_atom atom;
167 struct pipe_blend_color state;
168 };
169
170 struct r600_clip_state {
171 struct r600_atom atom;
172 struct pipe_clip_state state;
173 };
174
175 struct r600_cs_shader_state {
176 struct r600_atom atom;
177 unsigned kernel_index;
178 unsigned pc;
179 struct r600_pipe_compute *shader;
180 };
181
182 struct r600_framebuffer {
183 struct r600_atom atom;
184 struct pipe_framebuffer_state state;
185 unsigned compressed_cb_mask;
186 unsigned nr_samples;
187 bool export_16bpc;
188 bool cb0_is_integer;
189 bool is_msaa_resolve;
190 bool dual_src_blend;
191 };
192
193 struct r600_sample_mask {
194 struct r600_atom atom;
195 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
196 };
197
198 struct r600_config_state {
199 struct r600_atom atom;
200 unsigned sq_gpr_resource_mgmt_1;
201 unsigned sq_gpr_resource_mgmt_2;
202 unsigned sq_gpr_resource_mgmt_3;
203 bool dyn_gpr_enabled;
204 };
205
206 struct r600_stencil_ref
207 {
208 ubyte ref_value[2];
209 ubyte valuemask[2];
210 ubyte writemask[2];
211 };
212
213 struct r600_stencil_ref_state {
214 struct r600_atom atom;
215 struct r600_stencil_ref state;
216 struct pipe_stencil_ref pipe_state;
217 };
218
219 struct r600_shader_stages_state {
220 struct r600_atom atom;
221 unsigned geom_enable;
222 };
223
224 struct r600_gs_rings_state {
225 struct r600_atom atom;
226 unsigned enable;
227 struct pipe_constant_buffer esgs_ring;
228 struct pipe_constant_buffer gsvs_ring;
229 };
230
231 /* This must start from 16. */
232 /* features */
233 #define DBG_NO_CP_DMA (1 << 30)
234 /* shader backend */
235 #define DBG_NO_SB (1 << 21)
236 #define DBG_SB_CS (1 << 22)
237 #define DBG_SB_DRY_RUN (1 << 23)
238 #define DBG_SB_STAT (1 << 24)
239 #define DBG_SB_DUMP (1 << 25)
240 #define DBG_SB_NO_FALLBACK (1 << 26)
241 #define DBG_SB_DISASM (1 << 27)
242 #define DBG_SB_SAFEMATH (1 << 28)
243
244 struct r600_screen {
245 struct r600_common_screen b;
246 bool has_msaa;
247 bool has_compressed_msaa_texturing;
248
249 /*for compute global memory binding, we allocate stuff here, instead of
250 * buffers.
251 * XXX: Not sure if this is the best place for global_pool. Also,
252 * it's not thread safe, so it won't work with multiple contexts. */
253 struct compute_memory_pool *global_pool;
254 };
255
256 struct r600_pipe_sampler_view {
257 struct pipe_sampler_view base;
258 struct list_head list;
259 struct r600_resource *tex_resource;
260 uint32_t tex_resource_words[8];
261 bool skip_mip_address_reloc;
262 bool is_stencil_sampler;
263 };
264
265 struct r600_rasterizer_state {
266 struct r600_command_buffer buffer;
267 boolean flatshade;
268 boolean two_side;
269 unsigned sprite_coord_enable;
270 unsigned clip_plane_enable;
271 unsigned pa_sc_line_stipple;
272 unsigned pa_cl_clip_cntl;
273 unsigned pa_su_sc_mode_cntl;
274 float offset_units;
275 float offset_scale;
276 bool offset_enable;
277 bool offset_units_unscaled;
278 bool scissor_enable;
279 bool multisample_enable;
280 bool clip_halfz;
281 };
282
283 struct r600_poly_offset_state {
284 struct r600_atom atom;
285 enum pipe_format zs_format;
286 float offset_units;
287 float offset_scale;
288 bool offset_units_unscaled;
289 };
290
291 struct r600_blend_state {
292 struct r600_command_buffer buffer;
293 struct r600_command_buffer buffer_no_blend;
294 unsigned cb_target_mask;
295 unsigned cb_color_control;
296 unsigned cb_color_control_no_blend;
297 bool dual_src_blend;
298 bool alpha_to_one;
299 };
300
301 struct r600_dsa_state {
302 struct r600_command_buffer buffer;
303 unsigned alpha_ref;
304 ubyte valuemask[2];
305 ubyte writemask[2];
306 unsigned zwritemask;
307 unsigned sx_alpha_test_control;
308 };
309
310 struct r600_pipe_shader;
311
312 struct r600_pipe_shader_selector {
313 struct r600_pipe_shader *current;
314
315 struct tgsi_token *tokens;
316 struct pipe_stream_output_info so;
317 struct tgsi_shader_info info;
318
319 unsigned num_shaders;
320
321 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
322 unsigned type;
323
324 /* geometry shader properties */
325 unsigned gs_output_prim;
326 unsigned gs_max_out_vertices;
327 unsigned gs_num_invocations;
328
329 /* TCS/VS */
330 uint64_t lds_patch_outputs_written_mask;
331 uint64_t lds_outputs_written_mask;
332 unsigned nr_ps_max_color_exports;
333 };
334
335 struct r600_pipe_sampler_state {
336 uint32_t tex_sampler_words[3];
337 union pipe_color_union border_color;
338 bool border_color_use;
339 bool seamless_cube_map;
340 };
341
342 /* needed for blitter save */
343 #define NUM_TEX_UNITS 16
344
345 struct r600_seamless_cube_map {
346 struct r600_atom atom;
347 bool enabled;
348 };
349
350 struct r600_samplerview_state {
351 struct r600_atom atom;
352 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
353 uint32_t enabled_mask;
354 uint32_t dirty_mask;
355 uint32_t compressed_depthtex_mask; /* which textures are depth */
356 uint32_t compressed_colortex_mask;
357 boolean dirty_buffer_constants;
358 };
359
360 struct r600_sampler_states {
361 struct r600_atom atom;
362 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
363 uint32_t enabled_mask;
364 uint32_t dirty_mask;
365 uint32_t has_bordercolor_mask; /* which states contain the border color */
366 };
367
368 struct r600_textures_info {
369 struct r600_samplerview_state views;
370 struct r600_sampler_states states;
371 bool is_array_sampler[NUM_TEX_UNITS];
372 };
373
374 struct r600_shader_driver_constants_info {
375 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
376 uint32_t *constants;
377 uint32_t alloc_size;
378 bool vs_ucp_dirty;
379 bool texture_const_dirty;
380 bool ps_sample_pos_dirty;
381 };
382
383 struct r600_constbuf_state
384 {
385 struct r600_atom atom;
386 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
387 uint32_t enabled_mask;
388 uint32_t dirty_mask;
389 };
390
391 struct r600_vertexbuf_state
392 {
393 struct r600_atom atom;
394 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
395 uint32_t enabled_mask; /* non-NULL buffers */
396 uint32_t dirty_mask;
397 };
398
399 /* CSO (constant state object, in other words, immutable state). */
400 struct r600_cso_state
401 {
402 struct r600_atom atom;
403 void *cso; /* e.g. r600_blend_state */
404 struct r600_command_buffer *cb;
405 };
406
407 struct r600_fetch_shader {
408 struct r600_resource *buffer;
409 unsigned offset;
410 };
411
412 struct r600_shader_state {
413 struct r600_atom atom;
414 struct r600_pipe_shader *shader;
415 };
416
417 struct r600_context {
418 struct r600_common_context b;
419 struct r600_screen *screen;
420 struct blitter_context *blitter;
421 struct u_suballocator *allocator_fetch_shader;
422
423 /* Hardware info. */
424 boolean has_vertex_cache;
425 unsigned default_gprs[EG_NUM_HW_STAGES];
426 unsigned current_gprs[EG_NUM_HW_STAGES];
427 unsigned r6xx_num_clause_temp_gprs;
428
429 /* Miscellaneous state objects. */
430 void *custom_dsa_flush;
431 void *custom_blend_resolve;
432 void *custom_blend_decompress;
433 void *custom_blend_fastclear;
434 /* With rasterizer discard, there doesn't have to be a pixel shader.
435 * In that case, we bind this one: */
436 void *dummy_pixel_shader;
437 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
438 * bug where valid CMASK and FMASK are required to be present to avoid
439 * a hardlock in certain operations but aren't actually used
440 * for anything useful. */
441 struct r600_resource *dummy_fmask;
442 struct r600_resource *dummy_cmask;
443
444 /* State binding slots are here. */
445 struct r600_atom *atoms[R600_NUM_ATOMS];
446 /* Dirty atom bitmask for fast tests */
447 uint64_t dirty_atoms;
448 /* States for CS initialization. */
449 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
450 /** Compute specific registers initializations. The start_cs_cmd atom
451 * must be emitted before start_compute_cs_cmd. */
452 struct r600_command_buffer start_compute_cs_cmd;
453 /* Register states. */
454 struct r600_alphatest_state alphatest_state;
455 struct r600_cso_state blend_state;
456 struct r600_blend_color blend_color;
457 struct r600_cb_misc_state cb_misc_state;
458 struct r600_clip_misc_state clip_misc_state;
459 struct r600_clip_state clip_state;
460 struct r600_db_misc_state db_misc_state;
461 struct r600_db_state db_state;
462 struct r600_cso_state dsa_state;
463 struct r600_framebuffer framebuffer;
464 struct r600_poly_offset_state poly_offset_state;
465 struct r600_cso_state rasterizer_state;
466 struct r600_sample_mask sample_mask;
467 struct r600_seamless_cube_map seamless_cube_map;
468 struct r600_config_state config_state;
469 struct r600_stencil_ref_state stencil_ref;
470 struct r600_vgt_state vgt_state;
471 /* Shaders and shader resources. */
472 struct r600_cso_state vertex_fetch_shader;
473 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
474 struct r600_cs_shader_state cs_shader_state;
475 struct r600_shader_stages_state shader_stages;
476 struct r600_gs_rings_state gs_rings;
477 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
478 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
479
480 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
481
482 /** Vertex buffers for fetch shaders */
483 struct r600_vertexbuf_state vertex_buffer_state;
484 /** Vertex buffers for compute shaders */
485 struct r600_vertexbuf_state cs_vertex_buffer_state;
486
487 /* Additional context states. */
488 unsigned compute_cb_target_mask;
489 struct r600_pipe_shader_selector *ps_shader;
490 struct r600_pipe_shader_selector *vs_shader;
491 struct r600_pipe_shader_selector *gs_shader;
492
493 struct r600_pipe_shader_selector *tcs_shader;
494 struct r600_pipe_shader_selector *tes_shader;
495
496 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
497
498 struct r600_rasterizer_state *rasterizer;
499 bool alpha_to_one;
500 bool force_blend_disable;
501 boolean dual_src_blend;
502 unsigned zwritemask;
503 int ps_iter_samples;
504
505 /* The list of all texture buffer objects in this context.
506 * This list is walked when a buffer is invalidated/reallocated and
507 * the GPU addresses are updated. */
508 struct list_head texture_buffers;
509
510 /* Index buffer. */
511 struct pipe_index_buffer index_buffer;
512
513 /* Last draw state (-1 = unset). */
514 int last_primitive_type; /* Last primitive type used in draw_vbo. */
515 int last_start_instance;
516
517 void *sb_context;
518 struct r600_isa *isa;
519 float sample_positions[4 * 16];
520 float tess_state[8];
521 bool tess_state_dirty;
522 struct r600_pipe_shader_selector *last_ls;
523 struct r600_pipe_shader_selector *last_tcs;
524 unsigned last_num_tcs_input_cp;
525 unsigned lds_alloc;
526 };
527
528 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
529 struct r600_command_buffer *cb)
530 {
531 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
532 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
533 cs->current.cdw += cb->num_dw;
534 }
535
536 static inline void r600_set_atom_dirty(struct r600_context *rctx,
537 struct r600_atom *atom,
538 bool dirty)
539 {
540 uint64_t mask;
541
542 assert(atom->id != 0);
543 assert(atom->id < sizeof(mask) * 8);
544 mask = 1ull << atom->id;
545 if (dirty)
546 rctx->dirty_atoms |= mask;
547 else
548 rctx->dirty_atoms &= ~mask;
549 }
550
551 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
552 struct r600_atom *atom)
553 {
554 r600_set_atom_dirty(rctx, atom, true);
555 }
556
557 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
558 {
559 atom->emit(&rctx->b, atom);
560 r600_set_atom_dirty(rctx, atom, false);
561 }
562
563 static inline void r600_set_cso_state(struct r600_context *rctx,
564 struct r600_cso_state *state, void *cso)
565 {
566 state->cso = cso;
567 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
568 }
569
570 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
571 struct r600_cso_state *state, void *cso,
572 struct r600_command_buffer *cb)
573 {
574 state->cb = cb;
575 state->atom.num_dw = cb ? cb->num_dw : 0;
576 r600_set_cso_state(rctx, state, cso);
577 }
578
579 /* compute_memory_pool.c */
580 struct compute_memory_pool;
581 void compute_memory_pool_delete(struct compute_memory_pool* pool);
582 struct compute_memory_pool* compute_memory_pool_new(
583 struct r600_screen *rscreen);
584
585 /* evergreen_state.c */
586 struct pipe_sampler_view *
587 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
588 struct pipe_resource *texture,
589 const struct pipe_sampler_view *state,
590 unsigned width0, unsigned height0,
591 unsigned force_level);
592 void evergreen_init_common_regs(struct r600_context *ctx,
593 struct r600_command_buffer *cb,
594 enum chip_class ctx_chip_class,
595 enum radeon_family ctx_family,
596 int ctx_drm_minor);
597 void cayman_init_common_regs(struct r600_command_buffer *cb,
598 enum chip_class ctx_chip_class,
599 enum radeon_family ctx_family,
600 int ctx_drm_minor);
601
602 void evergreen_init_state_functions(struct r600_context *rctx);
603 void evergreen_init_atom_start_cs(struct r600_context *rctx);
604 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
605 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
606 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
607 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
608 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
609 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
610 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
611 void *evergreen_create_resolve_blend(struct r600_context *rctx);
612 void *evergreen_create_decompress_blend(struct r600_context *rctx);
613 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
614 boolean evergreen_is_format_supported(struct pipe_screen *screen,
615 enum pipe_format format,
616 enum pipe_texture_target target,
617 unsigned sample_count,
618 unsigned usage);
619 void evergreen_init_color_surface(struct r600_context *rctx,
620 struct r600_surface *surf);
621 void evergreen_init_color_surface_rat(struct r600_context *rctx,
622 struct r600_surface *surf);
623 void evergreen_update_db_shader_control(struct r600_context * rctx);
624 bool evergreen_adjust_gprs(struct r600_context *rctx);
625 /* r600_blit.c */
626 void r600_init_blit_functions(struct r600_context *rctx);
627 void r600_decompress_depth_textures(struct r600_context *rctx,
628 struct r600_samplerview_state *textures);
629 void r600_decompress_color_textures(struct r600_context *rctx,
630 struct r600_samplerview_state *textures);
631 void r600_resource_copy_region(struct pipe_context *ctx,
632 struct pipe_resource *dst,
633 unsigned dst_level,
634 unsigned dstx, unsigned dsty, unsigned dstz,
635 struct pipe_resource *src,
636 unsigned src_level,
637 const struct pipe_box *src_box);
638
639 /* r600_shader.c */
640 int r600_pipe_shader_create(struct pipe_context *ctx,
641 struct r600_pipe_shader *shader,
642 union r600_shader_key key);
643
644 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
645
646 /* r600_state.c */
647 struct pipe_sampler_view *
648 r600_create_sampler_view_custom(struct pipe_context *ctx,
649 struct pipe_resource *texture,
650 const struct pipe_sampler_view *state,
651 unsigned width_first_level, unsigned height_first_level);
652 void r600_init_state_functions(struct r600_context *rctx);
653 void r600_init_atom_start_cs(struct r600_context *rctx);
654 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
655 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
656 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
657 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
658 void *r600_create_db_flush_dsa(struct r600_context *rctx);
659 void *r600_create_resolve_blend(struct r600_context *rctx);
660 void *r700_create_resolve_blend(struct r600_context *rctx);
661 void *r600_create_decompress_blend(struct r600_context *rctx);
662 bool r600_adjust_gprs(struct r600_context *rctx);
663 boolean r600_is_format_supported(struct pipe_screen *screen,
664 enum pipe_format format,
665 enum pipe_texture_target target,
666 unsigned sample_count,
667 unsigned usage);
668 void r600_update_db_shader_control(struct r600_context * rctx);
669
670 /* r600_hw_context.c */
671 void r600_context_gfx_flush(void *context, unsigned flags,
672 struct pipe_fence_handle **fence);
673 void r600_begin_new_cs(struct r600_context *ctx);
674 void r600_flush_emit(struct r600_context *ctx);
675 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
676 void r600_emit_pfp_sync_me(struct r600_context *rctx);
677 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
678 struct pipe_resource *dst, uint64_t dst_offset,
679 struct pipe_resource *src, uint64_t src_offset,
680 unsigned size);
681 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
682 struct pipe_resource *dst, uint64_t offset,
683 unsigned size, uint32_t clear_value,
684 enum r600_coherency coher);
685 void r600_dma_copy_buffer(struct r600_context *rctx,
686 struct pipe_resource *dst,
687 struct pipe_resource *src,
688 uint64_t dst_offset,
689 uint64_t src_offset,
690 uint64_t size);
691
692 /*
693 * evergreen_hw_context.c
694 */
695 void evergreen_dma_copy_buffer(struct r600_context *rctx,
696 struct pipe_resource *dst,
697 struct pipe_resource *src,
698 uint64_t dst_offset,
699 uint64_t src_offset,
700 uint64_t size);
701 void evergreen_setup_tess_constants(struct r600_context *rctx,
702 const struct pipe_draw_info *info,
703 unsigned *num_patches);
704 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
705 const struct pipe_draw_info *info,
706 unsigned num_patches);
707 void evergreen_set_ls_hs_config(struct r600_context *rctx,
708 struct radeon_winsys_cs *cs,
709 uint32_t ls_hs_config);
710 void evergreen_set_lds_alloc(struct r600_context *rctx,
711 struct radeon_winsys_cs *cs,
712 uint32_t lds_alloc);
713
714 /* r600_state_common.c */
715 void r600_init_common_state_functions(struct r600_context *rctx);
716 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
717 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
718 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
719 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
720 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
721 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
722 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
723 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
724 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
725 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
726 unsigned num_dw);
727 void r600_vertex_buffers_dirty(struct r600_context *rctx);
728 void r600_sampler_views_dirty(struct r600_context *rctx,
729 struct r600_samplerview_state *state);
730 void r600_sampler_states_dirty(struct r600_context *rctx,
731 struct r600_sampler_states *state);
732 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
733 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
734 uint32_t r600_translate_stencil_op(int s_op);
735 uint32_t r600_translate_fill(uint32_t func);
736 unsigned r600_tex_wrap(unsigned wrap);
737 unsigned r600_tex_mipfilter(unsigned filter);
738 unsigned r600_tex_compare(unsigned compare);
739 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
740 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
741 const unsigned char *swizzle_view,
742 boolean vtx);
743 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
744 const unsigned char *swizzle_view,
745 uint32_t *word4_p, uint32_t *yuv_format_p,
746 bool do_endian_swap);
747 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
748 bool do_endian_swap);
749 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
750
751 /* r600_uvd.c */
752 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
753 const struct pipe_video_codec *decoder);
754
755 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
756 const struct pipe_video_buffer *tmpl);
757
758 /*
759 * Helpers for building command buffers
760 */
761
762 #define PKT3_SET_CONFIG_REG 0x68
763 #define PKT3_SET_CONTEXT_REG 0x69
764 #define PKT3_SET_CTL_CONST 0x6F
765 #define PKT3_SET_LOOP_CONST 0x6C
766
767 #define R600_CONFIG_REG_OFFSET 0x08000
768 #define R600_CONTEXT_REG_OFFSET 0x28000
769 #define R600_CTL_CONST_OFFSET 0x3CFF0
770 #define R600_LOOP_CONST_OFFSET 0X0003E200
771 #define EG_LOOP_CONST_OFFSET 0x0003A200
772
773 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
774 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
775 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
776 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
777 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
778
779 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
780
781 /*Evergreen Compute packet3*/
782 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
783
784 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
785 {
786 cb->buf[cb->num_dw++] = value;
787 }
788
789 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
790 {
791 assert(cb->num_dw+num <= cb->max_num_dw);
792 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
793 cb->num_dw += num;
794 }
795
796 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
797 {
798 assert(reg < R600_CONTEXT_REG_OFFSET);
799 assert(cb->num_dw+2+num <= cb->max_num_dw);
800 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
801 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
802 }
803
804 /**
805 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
806 * shaders.
807 */
808 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
809 {
810 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
811 assert(cb->num_dw+2+num <= cb->max_num_dw);
812 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
813 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
814 }
815
816 /**
817 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
818 * shaders.
819 */
820 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
821 {
822 assert(reg >= R600_CTL_CONST_OFFSET);
823 assert(cb->num_dw+2+num <= cb->max_num_dw);
824 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
825 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
826 }
827
828 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
829 {
830 assert(reg >= R600_LOOP_CONST_OFFSET);
831 assert(cb->num_dw+2+num <= cb->max_num_dw);
832 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
833 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
834 }
835
836 /**
837 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
838 * shaders.
839 */
840 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
841 {
842 assert(reg >= EG_LOOP_CONST_OFFSET);
843 assert(cb->num_dw+2+num <= cb->max_num_dw);
844 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
845 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
846 }
847
848 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
849 {
850 r600_store_config_reg_seq(cb, reg, 1);
851 r600_store_value(cb, value);
852 }
853
854 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
855 {
856 r600_store_context_reg_seq(cb, reg, 1);
857 r600_store_value(cb, value);
858 }
859
860 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
861 {
862 r600_store_ctl_const_seq(cb, reg, 1);
863 r600_store_value(cb, value);
864 }
865
866 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
867 {
868 r600_store_loop_const_seq(cb, reg, 1);
869 r600_store_value(cb, value);
870 }
871
872 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
873 {
874 eg_store_loop_const_seq(cb, reg, 1);
875 r600_store_value(cb, value);
876 }
877
878 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
879 void r600_release_command_buffer(struct r600_command_buffer *cb);
880
881 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
882 {
883 radeon_set_context_reg_seq(cs, reg, num);
884 /* Set the compute bit on the packet header */
885 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
886 }
887
888 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
889 {
890 assert(reg >= R600_CTL_CONST_OFFSET);
891 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
892 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
893 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
894 }
895
896 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
897 {
898 radeon_compute_set_context_reg_seq(cs, reg, 1);
899 radeon_emit(cs, value);
900 }
901
902 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
903 {
904 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
905 radeon_compute_set_context_reg(cs, reg, value);
906 } else {
907 radeon_set_context_reg(cs, reg, value);
908 }
909 }
910
911 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
912 {
913 radeon_set_ctl_const_seq(cs, reg, 1);
914 radeon_emit(cs, value);
915 }
916
917 /*
918 * common helpers
919 */
920 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
921 {
922 return value * (1 << frac_bits);
923 }
924
925 /* 12.4 fixed-point */
926 static inline unsigned r600_pack_float_12p4(float x)
927 {
928 return x <= 0 ? 0 :
929 x >= 4096 ? 0xffff : x * 16;
930 }
931
932 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
933 {
934 switch (coher) {
935 default:
936 case R600_COHERENCY_NONE:
937 return 0;
938 case R600_COHERENCY_SHADER:
939 return R600_CONTEXT_INV_CONST_CACHE |
940 R600_CONTEXT_INV_VERTEX_CACHE |
941 R600_CONTEXT_INV_TEX_CACHE |
942 R600_CONTEXT_STREAMOUT_FLUSH;
943 case R600_COHERENCY_CB_META:
944 return R600_CONTEXT_FLUSH_AND_INV_CB |
945 R600_CONTEXT_FLUSH_AND_INV_CB_META;
946 }
947 }
948
949 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
950 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
951 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
952
953 unsigned r600_conv_prim_to_gs_out(unsigned mode);
954 #endif