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r600: add set_tess_state callback.
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 51
42
43 #define R600_MAX_VIEWPORTS 16
44
45 /* read caches */
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
59
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 52
63 #define R600_TRACE_CS_DWORDS 7
64
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 2
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
68
69 /* start driver buffers after user buffers */
70 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_UCP_SIZE (4*4*8)
72 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
73
74 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
75 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
76 * of 16 const buffers.
77 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
78 *
79 * In order to support d3d 11 mandated minimum of 15 user const buffers
80 * we'd have to squash all use cases into one driver buffer.
81 */
82 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
83
84 /* HW stages */
85 #define R600_HW_STAGE_PS 0
86 #define R600_HW_STAGE_VS 1
87 #define R600_HW_STAGE_GS 2
88 #define R600_HW_STAGE_ES 3
89 #define EG_HW_STAGE_LS 4
90 #define EG_HW_STAGE_HS 5
91
92 #define R600_NUM_HW_STAGES 4
93 #define EG_NUM_HW_STAGES 6
94
95 #ifdef PIPE_ARCH_BIG_ENDIAN
96 #define R600_BIG_ENDIAN 1
97 #else
98 #define R600_BIG_ENDIAN 0
99 #endif
100
101 struct r600_context;
102 struct r600_bytecode;
103 union r600_shader_key;
104
105 /* This is an atom containing GPU commands that never change.
106 * This is supposed to be copied directly into the CS. */
107 struct r600_command_buffer {
108 uint32_t *buf;
109 unsigned num_dw;
110 unsigned max_num_dw;
111 unsigned pkt_flags;
112 };
113
114 struct r600_db_state {
115 struct r600_atom atom;
116 struct r600_surface *rsurf;
117 };
118
119 struct r600_db_misc_state {
120 struct r600_atom atom;
121 bool occlusion_query_enabled;
122 bool flush_depthstencil_through_cb;
123 bool flush_depth_inplace;
124 bool flush_stencil_inplace;
125 bool copy_depth, copy_stencil;
126 unsigned copy_sample;
127 unsigned log_samples;
128 unsigned db_shader_control;
129 bool htile_clear;
130 uint8_t ps_conservative_z;
131 };
132
133 struct r600_cb_misc_state {
134 struct r600_atom atom;
135 unsigned cb_color_control; /* this comes from blend state */
136 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
137 unsigned nr_cbufs;
138 unsigned nr_ps_color_outputs;
139 bool multiwrite;
140 bool dual_src_blend;
141 };
142
143 struct r600_clip_misc_state {
144 struct r600_atom atom;
145 unsigned pa_cl_clip_cntl; /* from rasterizer */
146 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
147 unsigned clip_plane_enable; /* from rasterizer */
148 unsigned clip_dist_write; /* from vertex shader */
149 boolean clip_disable; /* from vertex shader */
150 };
151
152 struct r600_alphatest_state {
153 struct r600_atom atom;
154 unsigned sx_alpha_test_control; /* this comes from dsa state */
155 unsigned sx_alpha_ref; /* this comes from dsa state */
156 bool bypass;
157 bool cb0_export_16bpc; /* from set_framebuffer_state */
158 };
159
160 struct r600_vgt_state {
161 struct r600_atom atom;
162 uint32_t vgt_multi_prim_ib_reset_en;
163 uint32_t vgt_multi_prim_ib_reset_indx;
164 uint32_t vgt_indx_offset;
165 bool last_draw_was_indirect;
166 };
167
168 struct r600_blend_color {
169 struct r600_atom atom;
170 struct pipe_blend_color state;
171 };
172
173 struct r600_clip_state {
174 struct r600_atom atom;
175 struct pipe_clip_state state;
176 };
177
178 struct r600_cs_shader_state {
179 struct r600_atom atom;
180 unsigned kernel_index;
181 unsigned pc;
182 struct r600_pipe_compute *shader;
183 };
184
185 struct r600_framebuffer {
186 struct r600_atom atom;
187 struct pipe_framebuffer_state state;
188 unsigned compressed_cb_mask;
189 unsigned nr_samples;
190 bool export_16bpc;
191 bool cb0_is_integer;
192 bool is_msaa_resolve;
193 };
194
195 struct r600_sample_mask {
196 struct r600_atom atom;
197 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
198 };
199
200 struct r600_config_state {
201 struct r600_atom atom;
202 unsigned sq_gpr_resource_mgmt_1;
203 unsigned sq_gpr_resource_mgmt_2;
204 };
205
206 struct r600_stencil_ref
207 {
208 ubyte ref_value[2];
209 ubyte valuemask[2];
210 ubyte writemask[2];
211 };
212
213 struct r600_stencil_ref_state {
214 struct r600_atom atom;
215 struct r600_stencil_ref state;
216 struct pipe_stencil_ref pipe_state;
217 };
218
219 struct r600_viewport_state {
220 struct r600_atom atom;
221 struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
222 uint32_t dirty_mask;
223 };
224
225 struct r600_shader_stages_state {
226 struct r600_atom atom;
227 unsigned geom_enable;
228 };
229
230 struct r600_gs_rings_state {
231 struct r600_atom atom;
232 unsigned enable;
233 struct pipe_constant_buffer esgs_ring;
234 struct pipe_constant_buffer gsvs_ring;
235 };
236
237 /* This must start from 16. */
238 /* features */
239 #define DBG_LLVM (1 << 29)
240 #define DBG_NO_CP_DMA (1 << 30)
241 /* shader backend */
242 #define DBG_NO_SB (1 << 21)
243 #define DBG_SB_CS (1 << 22)
244 #define DBG_SB_DRY_RUN (1 << 23)
245 #define DBG_SB_STAT (1 << 24)
246 #define DBG_SB_DUMP (1 << 25)
247 #define DBG_SB_NO_FALLBACK (1 << 26)
248 #define DBG_SB_DISASM (1 << 27)
249 #define DBG_SB_SAFEMATH (1 << 28)
250
251 struct r600_screen {
252 struct r600_common_screen b;
253 bool has_msaa;
254 bool has_compressed_msaa_texturing;
255
256 /*for compute global memory binding, we allocate stuff here, instead of
257 * buffers.
258 * XXX: Not sure if this is the best place for global_pool. Also,
259 * it's not thread safe, so it won't work with multiple contexts. */
260 struct compute_memory_pool *global_pool;
261 };
262
263 struct r600_pipe_sampler_view {
264 struct pipe_sampler_view base;
265 struct list_head list;
266 struct r600_resource *tex_resource;
267 uint32_t tex_resource_words[8];
268 bool skip_mip_address_reloc;
269 bool is_stencil_sampler;
270 };
271
272 struct r600_rasterizer_state {
273 struct r600_command_buffer buffer;
274 boolean flatshade;
275 boolean two_side;
276 unsigned sprite_coord_enable;
277 unsigned clip_plane_enable;
278 unsigned pa_sc_line_stipple;
279 unsigned pa_cl_clip_cntl;
280 unsigned pa_su_sc_mode_cntl;
281 float offset_units;
282 float offset_scale;
283 bool offset_enable;
284 bool scissor_enable;
285 bool multisample_enable;
286 };
287
288 struct r600_poly_offset_state {
289 struct r600_atom atom;
290 enum pipe_format zs_format;
291 float offset_units;
292 float offset_scale;
293 };
294
295 struct r600_blend_state {
296 struct r600_command_buffer buffer;
297 struct r600_command_buffer buffer_no_blend;
298 unsigned cb_target_mask;
299 unsigned cb_color_control;
300 unsigned cb_color_control_no_blend;
301 bool dual_src_blend;
302 bool alpha_to_one;
303 };
304
305 struct r600_dsa_state {
306 struct r600_command_buffer buffer;
307 unsigned alpha_ref;
308 ubyte valuemask[2];
309 ubyte writemask[2];
310 unsigned zwritemask;
311 unsigned sx_alpha_test_control;
312 };
313
314 struct r600_pipe_shader;
315
316 struct r600_pipe_shader_selector {
317 struct r600_pipe_shader *current;
318
319 struct tgsi_token *tokens;
320 struct pipe_stream_output_info so;
321 struct tgsi_shader_info info;
322
323 unsigned num_shaders;
324
325 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
326 unsigned type;
327
328 /* geometry shader properties */
329 unsigned gs_output_prim;
330 unsigned gs_max_out_vertices;
331 unsigned gs_num_invocations;
332
333 unsigned nr_ps_max_color_exports;
334 };
335
336 struct r600_pipe_sampler_state {
337 uint32_t tex_sampler_words[3];
338 union pipe_color_union border_color;
339 bool border_color_use;
340 bool seamless_cube_map;
341 };
342
343 /* needed for blitter save */
344 #define NUM_TEX_UNITS 16
345
346 struct r600_seamless_cube_map {
347 struct r600_atom atom;
348 bool enabled;
349 };
350
351 struct r600_samplerview_state {
352 struct r600_atom atom;
353 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
354 uint32_t enabled_mask;
355 uint32_t dirty_mask;
356 uint32_t compressed_depthtex_mask; /* which textures are depth */
357 uint32_t compressed_colortex_mask;
358 boolean dirty_buffer_constants;
359 };
360
361 struct r600_sampler_states {
362 struct r600_atom atom;
363 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
364 uint32_t enabled_mask;
365 uint32_t dirty_mask;
366 uint32_t has_bordercolor_mask; /* which states contain the border color */
367 };
368
369 struct r600_textures_info {
370 struct r600_samplerview_state views;
371 struct r600_sampler_states states;
372 bool is_array_sampler[NUM_TEX_UNITS];
373 };
374
375 struct r600_shader_driver_constants_info {
376 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
377 uint32_t *constants;
378 uint32_t alloc_size;
379 bool vs_ucp_dirty;
380 bool texture_const_dirty;
381 bool ps_sample_pos_dirty;
382 };
383
384 struct r600_constbuf_state
385 {
386 struct r600_atom atom;
387 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
388 uint32_t enabled_mask;
389 uint32_t dirty_mask;
390 };
391
392 struct r600_vertexbuf_state
393 {
394 struct r600_atom atom;
395 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
396 uint32_t enabled_mask; /* non-NULL buffers */
397 uint32_t dirty_mask;
398 };
399
400 /* CSO (constant state object, in other words, immutable state). */
401 struct r600_cso_state
402 {
403 struct r600_atom atom;
404 void *cso; /* e.g. r600_blend_state */
405 struct r600_command_buffer *cb;
406 };
407
408 struct r600_scissor_state
409 {
410 struct r600_atom atom;
411 struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
412 uint32_t dirty_mask;
413 bool enable; /* r6xx only */
414 };
415
416 struct r600_fetch_shader {
417 struct r600_resource *buffer;
418 unsigned offset;
419 };
420
421 struct r600_shader_state {
422 struct r600_atom atom;
423 struct r600_pipe_shader *shader;
424 };
425
426 struct r600_context {
427 struct r600_common_context b;
428 struct r600_screen *screen;
429 struct blitter_context *blitter;
430 struct u_suballocator *allocator_fetch_shader;
431
432 /* Hardware info. */
433 boolean has_vertex_cache;
434 boolean keep_tiling_flags;
435 unsigned default_gprs[EG_NUM_HW_STAGES];
436 unsigned r6xx_num_clause_temp_gprs;
437
438 /* Miscellaneous state objects. */
439 void *custom_dsa_flush;
440 void *custom_blend_resolve;
441 void *custom_blend_decompress;
442 void *custom_blend_fastclear;
443 /* With rasterizer discard, there doesn't have to be a pixel shader.
444 * In that case, we bind this one: */
445 void *dummy_pixel_shader;
446 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
447 * bug where valid CMASK and FMASK are required to be present to avoid
448 * a hardlock in certain operations but aren't actually used
449 * for anything useful. */
450 struct r600_resource *dummy_fmask;
451 struct r600_resource *dummy_cmask;
452
453 /* State binding slots are here. */
454 struct r600_atom *atoms[R600_NUM_ATOMS];
455 /* Dirty atom bitmask for fast tests */
456 uint64_t dirty_atoms;
457 /* States for CS initialization. */
458 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
459 /** Compute specific registers initializations. The start_cs_cmd atom
460 * must be emitted before start_compute_cs_cmd. */
461 struct r600_command_buffer start_compute_cs_cmd;
462 /* Register states. */
463 struct r600_alphatest_state alphatest_state;
464 struct r600_cso_state blend_state;
465 struct r600_blend_color blend_color;
466 struct r600_cb_misc_state cb_misc_state;
467 struct r600_clip_misc_state clip_misc_state;
468 struct r600_clip_state clip_state;
469 struct r600_db_misc_state db_misc_state;
470 struct r600_db_state db_state;
471 struct r600_cso_state dsa_state;
472 struct r600_framebuffer framebuffer;
473 struct r600_poly_offset_state poly_offset_state;
474 struct r600_cso_state rasterizer_state;
475 struct r600_sample_mask sample_mask;
476 struct r600_scissor_state scissor;
477 struct r600_seamless_cube_map seamless_cube_map;
478 struct r600_config_state config_state;
479 struct r600_stencil_ref_state stencil_ref;
480 struct r600_vgt_state vgt_state;
481 struct r600_viewport_state viewport;
482 /* Shaders and shader resources. */
483 struct r600_cso_state vertex_fetch_shader;
484 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
485 struct r600_cs_shader_state cs_shader_state;
486 struct r600_shader_stages_state shader_stages;
487 struct r600_gs_rings_state gs_rings;
488 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
489 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
490
491 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
492
493 /** Vertex buffers for fetch shaders */
494 struct r600_vertexbuf_state vertex_buffer_state;
495 /** Vertex buffers for compute shaders */
496 struct r600_vertexbuf_state cs_vertex_buffer_state;
497
498 /* Additional context states. */
499 unsigned compute_cb_target_mask;
500 struct r600_pipe_shader_selector *ps_shader;
501 struct r600_pipe_shader_selector *vs_shader;
502 struct r600_pipe_shader_selector *gs_shader;
503
504 struct r600_pipe_shader_selector *tcs_shader;
505 struct r600_pipe_shader_selector *tes_shader;
506
507 struct r600_rasterizer_state *rasterizer;
508 bool alpha_to_one;
509 bool force_blend_disable;
510 boolean dual_src_blend;
511 unsigned zwritemask;
512 int ps_iter_samples;
513
514 /* Index buffer. */
515 struct pipe_index_buffer index_buffer;
516
517 /* Last draw state (-1 = unset). */
518 int last_primitive_type; /* Last primitive type used in draw_vbo. */
519 int last_start_instance;
520
521 void *sb_context;
522 struct r600_isa *isa;
523 float sample_positions[4 * 16];
524 float tess_state[8];
525 };
526
527 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
528 struct r600_command_buffer *cb)
529 {
530 assert(cs->cdw + cb->num_dw <= cs->max_dw);
531 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
532 cs->cdw += cb->num_dw;
533 }
534
535 static inline void r600_set_atom_dirty(struct r600_context *rctx,
536 struct r600_atom *atom,
537 bool dirty)
538 {
539 uint64_t mask;
540
541 assert(atom->id != 0);
542 assert(atom->id < sizeof(mask) * 8);
543 mask = 1ull << atom->id;
544 if (dirty)
545 rctx->dirty_atoms |= mask;
546 else
547 rctx->dirty_atoms &= ~mask;
548 }
549
550 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
551 struct r600_atom *atom)
552 {
553 r600_set_atom_dirty(rctx, atom, true);
554 }
555
556 void r600_trace_emit(struct r600_context *rctx);
557
558 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
559 {
560 atom->emit(&rctx->b, atom);
561 r600_set_atom_dirty(rctx, atom, false);
562 if (rctx->screen->b.trace_bo) {
563 r600_trace_emit(rctx);
564 }
565 }
566
567 static inline void r600_set_cso_state(struct r600_context *rctx,
568 struct r600_cso_state *state, void *cso)
569 {
570 state->cso = cso;
571 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
572 }
573
574 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
575 struct r600_cso_state *state, void *cso,
576 struct r600_command_buffer *cb)
577 {
578 state->cb = cb;
579 state->atom.num_dw = cb ? cb->num_dw : 0;
580 r600_set_cso_state(rctx, state, cso);
581 }
582
583 /* compute_memory_pool.c */
584 struct compute_memory_pool;
585 void compute_memory_pool_delete(struct compute_memory_pool* pool);
586 struct compute_memory_pool* compute_memory_pool_new(
587 struct r600_screen *rscreen);
588
589 /* evergreen_state.c */
590 struct pipe_sampler_view *
591 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
592 struct pipe_resource *texture,
593 const struct pipe_sampler_view *state,
594 unsigned width0, unsigned height0,
595 unsigned force_level);
596 void evergreen_init_common_regs(struct r600_command_buffer *cb,
597 enum chip_class ctx_chip_class,
598 enum radeon_family ctx_family,
599 int ctx_drm_minor);
600 void cayman_init_common_regs(struct r600_command_buffer *cb,
601 enum chip_class ctx_chip_class,
602 enum radeon_family ctx_family,
603 int ctx_drm_minor);
604
605 void evergreen_init_state_functions(struct r600_context *rctx);
606 void evergreen_init_atom_start_cs(struct r600_context *rctx);
607 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
608 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
609 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
610 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
611 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
612 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
613 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
614 void *evergreen_create_resolve_blend(struct r600_context *rctx);
615 void *evergreen_create_decompress_blend(struct r600_context *rctx);
616 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
617 boolean evergreen_is_format_supported(struct pipe_screen *screen,
618 enum pipe_format format,
619 enum pipe_texture_target target,
620 unsigned sample_count,
621 unsigned usage);
622 void evergreen_init_color_surface(struct r600_context *rctx,
623 struct r600_surface *surf);
624 void evergreen_init_color_surface_rat(struct r600_context *rctx,
625 struct r600_surface *surf);
626 void evergreen_update_db_shader_control(struct r600_context * rctx);
627
628 /* r600_blit.c */
629 void r600_init_blit_functions(struct r600_context *rctx);
630 void r600_decompress_depth_textures(struct r600_context *rctx,
631 struct r600_samplerview_state *textures);
632 void r600_decompress_color_textures(struct r600_context *rctx,
633 struct r600_samplerview_state *textures);
634 void r600_resource_copy_region(struct pipe_context *ctx,
635 struct pipe_resource *dst,
636 unsigned dst_level,
637 unsigned dstx, unsigned dsty, unsigned dstz,
638 struct pipe_resource *src,
639 unsigned src_level,
640 const struct pipe_box *src_box);
641
642 /* r600_shader.c */
643 int r600_pipe_shader_create(struct pipe_context *ctx,
644 struct r600_pipe_shader *shader,
645 union r600_shader_key key);
646
647 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
648
649 /* r600_state.c */
650 struct pipe_sampler_view *
651 r600_create_sampler_view_custom(struct pipe_context *ctx,
652 struct pipe_resource *texture,
653 const struct pipe_sampler_view *state,
654 unsigned width_first_level, unsigned height_first_level);
655 void r600_init_state_functions(struct r600_context *rctx);
656 void r600_init_atom_start_cs(struct r600_context *rctx);
657 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
658 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
659 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
660 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
661 void *r600_create_db_flush_dsa(struct r600_context *rctx);
662 void *r600_create_resolve_blend(struct r600_context *rctx);
663 void *r700_create_resolve_blend(struct r600_context *rctx);
664 void *r600_create_decompress_blend(struct r600_context *rctx);
665 bool r600_adjust_gprs(struct r600_context *rctx);
666 boolean r600_is_format_supported(struct pipe_screen *screen,
667 enum pipe_format format,
668 enum pipe_texture_target target,
669 unsigned sample_count,
670 unsigned usage);
671 void r600_update_db_shader_control(struct r600_context * rctx);
672
673 /* r600_hw_context.c */
674 void r600_context_gfx_flush(void *context, unsigned flags,
675 struct pipe_fence_handle **fence);
676 void r600_begin_new_cs(struct r600_context *ctx);
677 void r600_flush_emit(struct r600_context *ctx);
678 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
679 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
680 struct pipe_resource *dst, uint64_t dst_offset,
681 struct pipe_resource *src, uint64_t src_offset,
682 unsigned size);
683 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
684 struct pipe_resource *dst, uint64_t offset,
685 unsigned size, uint32_t clear_value);
686 void r600_dma_copy_buffer(struct r600_context *rctx,
687 struct pipe_resource *dst,
688 struct pipe_resource *src,
689 uint64_t dst_offset,
690 uint64_t src_offset,
691 uint64_t size);
692
693 /*
694 * evergreen_hw_context.c
695 */
696 void evergreen_dma_copy_buffer(struct r600_context *rctx,
697 struct pipe_resource *dst,
698 struct pipe_resource *src,
699 uint64_t dst_offset,
700 uint64_t src_offset,
701 uint64_t size);
702
703 /* r600_state_common.c */
704 void r600_init_common_state_functions(struct r600_context *rctx);
705 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
706 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
707 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
708 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
709 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
710 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
711 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
712 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
713 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
714 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
715 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
716 unsigned num_dw);
717 void r600_vertex_buffers_dirty(struct r600_context *rctx);
718 void r600_sampler_views_dirty(struct r600_context *rctx,
719 struct r600_samplerview_state *state);
720 void r600_sampler_states_dirty(struct r600_context *rctx,
721 struct r600_sampler_states *state);
722 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
723 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
724 uint32_t r600_translate_stencil_op(int s_op);
725 uint32_t r600_translate_fill(uint32_t func);
726 unsigned r600_tex_wrap(unsigned wrap);
727 unsigned r600_tex_filter(unsigned filter);
728 unsigned r600_tex_mipfilter(unsigned filter);
729 unsigned r600_tex_compare(unsigned compare);
730 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
731 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
732 struct pipe_resource *texture,
733 const struct pipe_surface *templ,
734 unsigned width, unsigned height);
735 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
736 const unsigned char *swizzle_view,
737 boolean vtx);
738 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
739 const unsigned char *swizzle_view,
740 uint32_t *word4_p, uint32_t *yuv_format_p);
741 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
742 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
743
744 /* r600_uvd.c */
745 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
746 const struct pipe_video_codec *decoder);
747
748 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
749 const struct pipe_video_buffer *tmpl);
750
751 /*
752 * Helpers for building command buffers
753 */
754
755 #define PKT3_SET_CONFIG_REG 0x68
756 #define PKT3_SET_CONTEXT_REG 0x69
757 #define PKT3_SET_CTL_CONST 0x6F
758 #define PKT3_SET_LOOP_CONST 0x6C
759
760 #define R600_CONFIG_REG_OFFSET 0x08000
761 #define R600_CONTEXT_REG_OFFSET 0x28000
762 #define R600_CTL_CONST_OFFSET 0x3CFF0
763 #define R600_LOOP_CONST_OFFSET 0X0003E200
764 #define EG_LOOP_CONST_OFFSET 0x0003A200
765
766 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
767 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
768 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
769 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
770 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
771
772 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
773
774 /*Evergreen Compute packet3*/
775 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
776
777 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
778 {
779 cb->buf[cb->num_dw++] = value;
780 }
781
782 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
783 {
784 assert(cb->num_dw+num <= cb->max_num_dw);
785 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
786 cb->num_dw += num;
787 }
788
789 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
790 {
791 assert(reg < R600_CONTEXT_REG_OFFSET);
792 assert(cb->num_dw+2+num <= cb->max_num_dw);
793 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
794 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
795 }
796
797 /**
798 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
799 * shaders.
800 */
801 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
802 {
803 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
804 assert(cb->num_dw+2+num <= cb->max_num_dw);
805 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
806 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
807 }
808
809 /**
810 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
811 * shaders.
812 */
813 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
814 {
815 assert(reg >= R600_CTL_CONST_OFFSET);
816 assert(cb->num_dw+2+num <= cb->max_num_dw);
817 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
818 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
819 }
820
821 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
822 {
823 assert(reg >= R600_LOOP_CONST_OFFSET);
824 assert(cb->num_dw+2+num <= cb->max_num_dw);
825 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
826 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
827 }
828
829 /**
830 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
831 * shaders.
832 */
833 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
834 {
835 assert(reg >= EG_LOOP_CONST_OFFSET);
836 assert(cb->num_dw+2+num <= cb->max_num_dw);
837 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
838 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
839 }
840
841 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
842 {
843 r600_store_config_reg_seq(cb, reg, 1);
844 r600_store_value(cb, value);
845 }
846
847 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
848 {
849 r600_store_context_reg_seq(cb, reg, 1);
850 r600_store_value(cb, value);
851 }
852
853 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
854 {
855 r600_store_ctl_const_seq(cb, reg, 1);
856 r600_store_value(cb, value);
857 }
858
859 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
860 {
861 r600_store_loop_const_seq(cb, reg, 1);
862 r600_store_value(cb, value);
863 }
864
865 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
866 {
867 eg_store_loop_const_seq(cb, reg, 1);
868 r600_store_value(cb, value);
869 }
870
871 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
872 void r600_release_command_buffer(struct r600_command_buffer *cb);
873
874 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
875 {
876 radeon_set_context_reg_seq(cs, reg, num);
877 /* Set the compute bit on the packet header */
878 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
879 }
880
881 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
882 {
883 assert(reg >= R600_CTL_CONST_OFFSET);
884 assert(cs->cdw+2+num <= cs->max_dw);
885 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
886 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
887 }
888
889 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
890 {
891 radeon_compute_set_context_reg_seq(cs, reg, 1);
892 radeon_emit(cs, value);
893 }
894
895 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
896 {
897 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
898 radeon_compute_set_context_reg(cs, reg, value);
899 } else {
900 radeon_set_context_reg(cs, reg, value);
901 }
902 }
903
904 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
905 {
906 radeon_set_ctl_const_seq(cs, reg, 1);
907 radeon_emit(cs, value);
908 }
909
910 /*
911 * common helpers
912 */
913 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
914 {
915 return value * (1 << frac_bits);
916 }
917 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
918
919 /* 12.4 fixed-point */
920 static inline unsigned r600_pack_float_12p4(float x)
921 {
922 return x <= 0 ? 0 :
923 x >= 4096 ? 0xffff : x * 16;
924 }
925
926 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
927 static inline bool r600_can_read_depth(struct r600_texture *rtex)
928 {
929 return rtex->resource.b.b.nr_samples <= 1 &&
930 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
931 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
932 }
933
934 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
935 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
936 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
937
938 unsigned r600_conv_prim_to_gs_out(unsigned mode);
939 #endif