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r600g: make all viewport states use single atom
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 45
42
43 #define R600_MAX_VIEWPORTS 16
44
45 /* read caches */
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
59
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 47
63 #define R600_TRACE_CS_DWORDS 7
64
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 3
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
68
69 /* start driver buffers after user buffers */
70 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
72 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
73 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
74 * of 16 const buffers.
75 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
76 *
77 * In order to support d3d 11 mandated minimum of 15 user const buffers
78 * we'd have to squash all use cases into one driver buffer.
79 */
80 #define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
81
82 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
83
84 #ifdef PIPE_ARCH_BIG_ENDIAN
85 #define R600_BIG_ENDIAN 1
86 #else
87 #define R600_BIG_ENDIAN 0
88 #endif
89
90 #define R600_DIRTY_ATOM_WORD_BITS (sizeof(unsigned long) * 8)
91 #define R600_DIRTY_ATOM_ARRAY_LEN DIV_ROUND_UP(R600_NUM_ATOMS, R600_DIRTY_ATOM_WORD_BITS)
92
93 struct r600_context;
94 struct r600_bytecode;
95 union r600_shader_key;
96
97 /* This is an atom containing GPU commands that never change.
98 * This is supposed to be copied directly into the CS. */
99 struct r600_command_buffer {
100 uint32_t *buf;
101 unsigned num_dw;
102 unsigned max_num_dw;
103 unsigned pkt_flags;
104 };
105
106 struct r600_db_state {
107 struct r600_atom atom;
108 struct r600_surface *rsurf;
109 };
110
111 struct r600_db_misc_state {
112 struct r600_atom atom;
113 bool occlusion_query_enabled;
114 bool flush_depthstencil_through_cb;
115 bool flush_depthstencil_in_place;
116 bool copy_depth, copy_stencil;
117 unsigned copy_sample;
118 unsigned log_samples;
119 unsigned db_shader_control;
120 bool htile_clear;
121 };
122
123 struct r600_cb_misc_state {
124 struct r600_atom atom;
125 unsigned cb_color_control; /* this comes from blend state */
126 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
127 unsigned nr_cbufs;
128 unsigned nr_ps_color_outputs;
129 bool multiwrite;
130 bool dual_src_blend;
131 };
132
133 struct r600_clip_misc_state {
134 struct r600_atom atom;
135 unsigned pa_cl_clip_cntl; /* from rasterizer */
136 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
137 unsigned clip_plane_enable; /* from rasterizer */
138 unsigned clip_dist_write; /* from vertex shader */
139 boolean clip_disable; /* from vertex shader */
140 };
141
142 struct r600_alphatest_state {
143 struct r600_atom atom;
144 unsigned sx_alpha_test_control; /* this comes from dsa state */
145 unsigned sx_alpha_ref; /* this comes from dsa state */
146 bool bypass;
147 bool cb0_export_16bpc; /* from set_framebuffer_state */
148 };
149
150 struct r600_vgt_state {
151 struct r600_atom atom;
152 uint32_t vgt_multi_prim_ib_reset_en;
153 uint32_t vgt_multi_prim_ib_reset_indx;
154 uint32_t vgt_indx_offset;
155 bool last_draw_was_indirect;
156 };
157
158 struct r600_blend_color {
159 struct r600_atom atom;
160 struct pipe_blend_color state;
161 };
162
163 struct r600_clip_state {
164 struct r600_atom atom;
165 struct pipe_clip_state state;
166 };
167
168 struct r600_cs_shader_state {
169 struct r600_atom atom;
170 unsigned kernel_index;
171 unsigned pc;
172 struct r600_pipe_compute *shader;
173 };
174
175 struct r600_framebuffer {
176 struct r600_atom atom;
177 struct pipe_framebuffer_state state;
178 unsigned compressed_cb_mask;
179 unsigned nr_samples;
180 bool export_16bpc;
181 bool cb0_is_integer;
182 bool is_msaa_resolve;
183 };
184
185 struct r600_sample_mask {
186 struct r600_atom atom;
187 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
188 };
189
190 struct r600_config_state {
191 struct r600_atom atom;
192 unsigned sq_gpr_resource_mgmt_1;
193 unsigned sq_gpr_resource_mgmt_2;
194 };
195
196 struct r600_stencil_ref
197 {
198 ubyte ref_value[2];
199 ubyte valuemask[2];
200 ubyte writemask[2];
201 };
202
203 struct r600_stencil_ref_state {
204 struct r600_atom atom;
205 struct r600_stencil_ref state;
206 struct pipe_stencil_ref pipe_state;
207 };
208
209 struct r600_viewport_state {
210 struct r600_atom atom;
211 struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
212 uint32_t dirty_mask;
213 };
214
215 struct r600_shader_stages_state {
216 struct r600_atom atom;
217 unsigned geom_enable;
218 };
219
220 struct r600_gs_rings_state {
221 struct r600_atom atom;
222 unsigned enable;
223 struct pipe_constant_buffer esgs_ring;
224 struct pipe_constant_buffer gsvs_ring;
225 };
226
227 /* This must start from 16. */
228 /* features */
229 #define DBG_LLVM (1 << 29)
230 #define DBG_NO_CP_DMA (1 << 30)
231 /* shader backend */
232 #define DBG_NO_SB (1 << 21)
233 #define DBG_SB_CS (1 << 22)
234 #define DBG_SB_DRY_RUN (1 << 23)
235 #define DBG_SB_STAT (1 << 24)
236 #define DBG_SB_DUMP (1 << 25)
237 #define DBG_SB_NO_FALLBACK (1 << 26)
238 #define DBG_SB_DISASM (1 << 27)
239 #define DBG_SB_SAFEMATH (1 << 28)
240
241 struct r600_screen {
242 struct r600_common_screen b;
243 bool has_msaa;
244 bool has_compressed_msaa_texturing;
245
246 /*for compute global memory binding, we allocate stuff here, instead of
247 * buffers.
248 * XXX: Not sure if this is the best place for global_pool. Also,
249 * it's not thread safe, so it won't work with multiple contexts. */
250 struct compute_memory_pool *global_pool;
251 };
252
253 struct r600_pipe_sampler_view {
254 struct pipe_sampler_view base;
255 struct list_head list;
256 struct r600_resource *tex_resource;
257 uint32_t tex_resource_words[8];
258 bool skip_mip_address_reloc;
259 };
260
261 struct r600_rasterizer_state {
262 struct r600_command_buffer buffer;
263 boolean flatshade;
264 boolean two_side;
265 unsigned sprite_coord_enable;
266 unsigned clip_plane_enable;
267 unsigned pa_sc_line_stipple;
268 unsigned pa_cl_clip_cntl;
269 unsigned pa_su_sc_mode_cntl;
270 float offset_units;
271 float offset_scale;
272 bool offset_enable;
273 bool scissor_enable;
274 bool multisample_enable;
275 };
276
277 struct r600_poly_offset_state {
278 struct r600_atom atom;
279 enum pipe_format zs_format;
280 float offset_units;
281 float offset_scale;
282 };
283
284 struct r600_blend_state {
285 struct r600_command_buffer buffer;
286 struct r600_command_buffer buffer_no_blend;
287 unsigned cb_target_mask;
288 unsigned cb_color_control;
289 unsigned cb_color_control_no_blend;
290 bool dual_src_blend;
291 bool alpha_to_one;
292 };
293
294 struct r600_dsa_state {
295 struct r600_command_buffer buffer;
296 unsigned alpha_ref;
297 ubyte valuemask[2];
298 ubyte writemask[2];
299 unsigned zwritemask;
300 unsigned sx_alpha_test_control;
301 };
302
303 struct r600_pipe_shader;
304
305 struct r600_pipe_shader_selector {
306 struct r600_pipe_shader *current;
307
308 struct tgsi_token *tokens;
309 struct pipe_stream_output_info so;
310 struct tgsi_shader_info info;
311
312 unsigned num_shaders;
313
314 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
315 unsigned type;
316
317 /* geometry shader properties */
318 unsigned gs_output_prim;
319 unsigned gs_max_out_vertices;
320 unsigned gs_num_invocations;
321
322 unsigned nr_ps_max_color_exports;
323 };
324
325 struct r600_pipe_sampler_state {
326 uint32_t tex_sampler_words[3];
327 union pipe_color_union border_color;
328 bool border_color_use;
329 bool seamless_cube_map;
330 };
331
332 /* needed for blitter save */
333 #define NUM_TEX_UNITS 16
334
335 struct r600_seamless_cube_map {
336 struct r600_atom atom;
337 bool enabled;
338 };
339
340 struct r600_samplerview_state {
341 struct r600_atom atom;
342 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
343 uint32_t enabled_mask;
344 uint32_t dirty_mask;
345 uint32_t compressed_depthtex_mask; /* which textures are depth */
346 uint32_t compressed_colortex_mask;
347 boolean dirty_buffer_constants;
348 };
349
350 struct r600_sampler_states {
351 struct r600_atom atom;
352 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
353 uint32_t enabled_mask;
354 uint32_t dirty_mask;
355 uint32_t has_bordercolor_mask; /* which states contain the border color */
356 };
357
358 struct r600_textures_info {
359 struct r600_samplerview_state views;
360 struct r600_sampler_states states;
361 bool is_array_sampler[NUM_TEX_UNITS];
362
363 /* cube array txq workaround */
364 uint32_t *txq_constants;
365 /* buffer related workarounds */
366 uint32_t *buffer_constants;
367 };
368
369 struct r600_constbuf_state
370 {
371 struct r600_atom atom;
372 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
373 uint32_t enabled_mask;
374 uint32_t dirty_mask;
375 };
376
377 struct r600_vertexbuf_state
378 {
379 struct r600_atom atom;
380 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
381 uint32_t enabled_mask; /* non-NULL buffers */
382 uint32_t dirty_mask;
383 };
384
385 /* CSO (constant state object, in other words, immutable state). */
386 struct r600_cso_state
387 {
388 struct r600_atom atom;
389 void *cso; /* e.g. r600_blend_state */
390 struct r600_command_buffer *cb;
391 };
392
393 struct r600_scissor_state
394 {
395 struct r600_atom atom;
396 struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
397 uint32_t dirty_mask;
398 bool enable; /* r6xx only */
399 };
400
401 struct r600_fetch_shader {
402 struct r600_resource *buffer;
403 unsigned offset;
404 };
405
406 struct r600_shader_state {
407 struct r600_atom atom;
408 struct r600_pipe_shader *shader;
409 };
410
411 struct r600_context {
412 struct r600_common_context b;
413 struct r600_screen *screen;
414 struct blitter_context *blitter;
415 struct u_suballocator *allocator_fetch_shader;
416
417 /* Hardware info. */
418 boolean has_vertex_cache;
419 boolean keep_tiling_flags;
420 unsigned default_ps_gprs, default_vs_gprs;
421 unsigned r6xx_num_clause_temp_gprs;
422
423 /* Miscellaneous state objects. */
424 void *custom_dsa_flush;
425 void *custom_blend_resolve;
426 void *custom_blend_decompress;
427 void *custom_blend_fastclear;
428 /* With rasterizer discard, there doesn't have to be a pixel shader.
429 * In that case, we bind this one: */
430 void *dummy_pixel_shader;
431 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
432 * bug where valid CMASK and FMASK are required to be present to avoid
433 * a hardlock in certain operations but aren't actually used
434 * for anything useful. */
435 struct r600_resource *dummy_fmask;
436 struct r600_resource *dummy_cmask;
437
438 /* State binding slots are here. */
439 struct r600_atom *atoms[R600_NUM_ATOMS];
440 /* Dirty atom bitmask for fast tests */
441 unsigned long dirty_atoms[R600_DIRTY_ATOM_ARRAY_LEN];
442 /* States for CS initialization. */
443 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
444 /** Compute specific registers initializations. The start_cs_cmd atom
445 * must be emitted before start_compute_cs_cmd. */
446 struct r600_command_buffer start_compute_cs_cmd;
447 /* Register states. */
448 struct r600_alphatest_state alphatest_state;
449 struct r600_cso_state blend_state;
450 struct r600_blend_color blend_color;
451 struct r600_cb_misc_state cb_misc_state;
452 struct r600_clip_misc_state clip_misc_state;
453 struct r600_clip_state clip_state;
454 struct r600_db_misc_state db_misc_state;
455 struct r600_db_state db_state;
456 struct r600_cso_state dsa_state;
457 struct r600_framebuffer framebuffer;
458 struct r600_poly_offset_state poly_offset_state;
459 struct r600_cso_state rasterizer_state;
460 struct r600_sample_mask sample_mask;
461 struct r600_scissor_state scissor;
462 struct r600_seamless_cube_map seamless_cube_map;
463 struct r600_config_state config_state;
464 struct r600_stencil_ref_state stencil_ref;
465 struct r600_vgt_state vgt_state;
466 struct r600_viewport_state viewport;
467 /* Shaders and shader resources. */
468 struct r600_cso_state vertex_fetch_shader;
469 struct r600_shader_state vertex_shader;
470 struct r600_shader_state pixel_shader;
471 struct r600_shader_state geometry_shader;
472 struct r600_shader_state export_shader;
473 struct r600_cs_shader_state cs_shader_state;
474 struct r600_shader_stages_state shader_stages;
475 struct r600_gs_rings_state gs_rings;
476 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
477 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
478 /** Vertex buffers for fetch shaders */
479 struct r600_vertexbuf_state vertex_buffer_state;
480 /** Vertex buffers for compute shaders */
481 struct r600_vertexbuf_state cs_vertex_buffer_state;
482
483 /* Additional context states. */
484 unsigned compute_cb_target_mask;
485 struct r600_pipe_shader_selector *ps_shader;
486 struct r600_pipe_shader_selector *vs_shader;
487 struct r600_pipe_shader_selector *gs_shader;
488 struct r600_rasterizer_state *rasterizer;
489 bool alpha_to_one;
490 bool force_blend_disable;
491 boolean dual_src_blend;
492 unsigned zwritemask;
493 int ps_iter_samples;
494
495 /* Index buffer. */
496 struct pipe_index_buffer index_buffer;
497
498 /* Last draw state (-1 = unset). */
499 int last_primitive_type; /* Last primitive type used in draw_vbo. */
500 int last_start_instance;
501
502 void *sb_context;
503 struct r600_isa *isa;
504 };
505
506 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
507 struct r600_command_buffer *cb)
508 {
509 assert(cs->cdw + cb->num_dw <= cs->max_dw);
510 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
511 cs->cdw += cb->num_dw;
512 }
513
514 static inline void r600_set_atom_dirty(struct r600_context *rctx,
515 struct r600_atom *atom,
516 bool dirty)
517 {
518 unsigned long mask;
519 unsigned int w;
520
521 atom->dirty = dirty;
522
523 assert(atom->id != 0);
524 w = atom->id / R600_DIRTY_ATOM_WORD_BITS;
525 mask = 1ul << (atom->id % R600_DIRTY_ATOM_WORD_BITS);
526 if (dirty)
527 rctx->dirty_atoms[w] |= mask;
528 else
529 rctx->dirty_atoms[w] &= ~mask;
530 }
531
532 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
533 struct r600_atom *atom)
534 {
535 r600_set_atom_dirty(rctx, atom, true);
536 }
537
538 static inline unsigned int r600_next_dirty_atom(struct r600_context *rctx,
539 unsigned int id)
540 {
541 #if !defined(DEBUG) && defined(HAVE___BUILTIN_CTZ)
542 unsigned int w = id / R600_DIRTY_ATOM_WORD_BITS;
543 unsigned int bit = id % R600_DIRTY_ATOM_WORD_BITS;
544 unsigned long bits, mask = (1ul << bit) - 1;
545
546 for (; w < R600_DIRTY_ATOM_ARRAY_LEN; w++, mask = 0ul) {
547 bits = rctx->dirty_atoms[w] & ~mask;
548 if (bits == 0)
549 continue;
550 return w * R600_DIRTY_ATOM_WORD_BITS + __builtin_ctzl(bits);
551 }
552
553 return R600_NUM_ATOMS;
554 #else
555 for (; id < R600_NUM_ATOMS; id++) {
556 bool dirty = !!(rctx->dirty_atoms[id / R600_DIRTY_ATOM_WORD_BITS] &
557 (1ul << (id % R600_DIRTY_ATOM_WORD_BITS)));
558 assert(dirty == (rctx->atoms[id] && rctx->atoms[id]->dirty));
559 if (dirty)
560 break;
561 }
562
563 return id;
564 #endif
565 }
566
567 void r600_trace_emit(struct r600_context *rctx);
568
569 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
570 {
571 atom->emit(&rctx->b, atom);
572 r600_set_atom_dirty(rctx, atom, false);
573 if (rctx->screen->b.trace_bo) {
574 r600_trace_emit(rctx);
575 }
576 }
577
578 static inline void r600_set_cso_state(struct r600_context *rctx,
579 struct r600_cso_state *state, void *cso)
580 {
581 state->cso = cso;
582 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
583 }
584
585 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
586 struct r600_cso_state *state, void *cso,
587 struct r600_command_buffer *cb)
588 {
589 state->cb = cb;
590 state->atom.num_dw = cb ? cb->num_dw : 0;
591 r600_set_cso_state(rctx, state, cso);
592 }
593
594 /* compute_memory_pool.c */
595 struct compute_memory_pool;
596 void compute_memory_pool_delete(struct compute_memory_pool* pool);
597 struct compute_memory_pool* compute_memory_pool_new(
598 struct r600_screen *rscreen);
599
600 /* evergreen_state.c */
601 struct pipe_sampler_view *
602 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
603 struct pipe_resource *texture,
604 const struct pipe_sampler_view *state,
605 unsigned width0, unsigned height0,
606 unsigned force_level);
607 void evergreen_init_common_regs(struct r600_command_buffer *cb,
608 enum chip_class ctx_chip_class,
609 enum radeon_family ctx_family,
610 int ctx_drm_minor);
611 void cayman_init_common_regs(struct r600_command_buffer *cb,
612 enum chip_class ctx_chip_class,
613 enum radeon_family ctx_family,
614 int ctx_drm_minor);
615
616 void evergreen_init_state_functions(struct r600_context *rctx);
617 void evergreen_init_atom_start_cs(struct r600_context *rctx);
618 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
619 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
620 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
621 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
622 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
623 void *evergreen_create_resolve_blend(struct r600_context *rctx);
624 void *evergreen_create_decompress_blend(struct r600_context *rctx);
625 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
626 boolean evergreen_is_format_supported(struct pipe_screen *screen,
627 enum pipe_format format,
628 enum pipe_texture_target target,
629 unsigned sample_count,
630 unsigned usage);
631 void evergreen_init_color_surface(struct r600_context *rctx,
632 struct r600_surface *surf);
633 void evergreen_init_color_surface_rat(struct r600_context *rctx,
634 struct r600_surface *surf);
635 void evergreen_update_db_shader_control(struct r600_context * rctx);
636
637 /* r600_blit.c */
638 void r600_init_blit_functions(struct r600_context *rctx);
639 void r600_decompress_depth_textures(struct r600_context *rctx,
640 struct r600_samplerview_state *textures);
641 void r600_decompress_color_textures(struct r600_context *rctx,
642 struct r600_samplerview_state *textures);
643 void r600_resource_copy_region(struct pipe_context *ctx,
644 struct pipe_resource *dst,
645 unsigned dst_level,
646 unsigned dstx, unsigned dsty, unsigned dstz,
647 struct pipe_resource *src,
648 unsigned src_level,
649 const struct pipe_box *src_box);
650
651 /* r600_shader.c */
652 int r600_pipe_shader_create(struct pipe_context *ctx,
653 struct r600_pipe_shader *shader,
654 union r600_shader_key key);
655
656 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
657
658 /* r600_state.c */
659 struct pipe_sampler_view *
660 r600_create_sampler_view_custom(struct pipe_context *ctx,
661 struct pipe_resource *texture,
662 const struct pipe_sampler_view *state,
663 unsigned width_first_level, unsigned height_first_level);
664 void r600_init_state_functions(struct r600_context *rctx);
665 void r600_init_atom_start_cs(struct r600_context *rctx);
666 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
667 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
668 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
669 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
670 void *r600_create_db_flush_dsa(struct r600_context *rctx);
671 void *r600_create_resolve_blend(struct r600_context *rctx);
672 void *r700_create_resolve_blend(struct r600_context *rctx);
673 void *r600_create_decompress_blend(struct r600_context *rctx);
674 bool r600_adjust_gprs(struct r600_context *rctx);
675 boolean r600_is_format_supported(struct pipe_screen *screen,
676 enum pipe_format format,
677 enum pipe_texture_target target,
678 unsigned sample_count,
679 unsigned usage);
680 void r600_update_db_shader_control(struct r600_context * rctx);
681
682 /* r600_hw_context.c */
683 void r600_context_gfx_flush(void *context, unsigned flags,
684 struct pipe_fence_handle **fence);
685 void r600_begin_new_cs(struct r600_context *ctx);
686 void r600_flush_emit(struct r600_context *ctx);
687 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
688 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
689 struct pipe_resource *dst, uint64_t dst_offset,
690 struct pipe_resource *src, uint64_t src_offset,
691 unsigned size);
692 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
693 struct pipe_resource *dst, uint64_t offset,
694 unsigned size, uint32_t clear_value);
695 void r600_dma_copy_buffer(struct r600_context *rctx,
696 struct pipe_resource *dst,
697 struct pipe_resource *src,
698 uint64_t dst_offset,
699 uint64_t src_offset,
700 uint64_t size);
701
702 /*
703 * evergreen_hw_context.c
704 */
705 void evergreen_dma_copy_buffer(struct r600_context *rctx,
706 struct pipe_resource *dst,
707 struct pipe_resource *src,
708 uint64_t dst_offset,
709 uint64_t src_offset,
710 uint64_t size);
711
712 /* r600_state_common.c */
713 void r600_init_common_state_functions(struct r600_context *rctx);
714 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
715 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
716 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
717 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
718 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
719 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
720 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
721 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
722 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
723 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
724 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
725 unsigned num_dw);
726 void r600_vertex_buffers_dirty(struct r600_context *rctx);
727 void r600_sampler_views_dirty(struct r600_context *rctx,
728 struct r600_samplerview_state *state);
729 void r600_sampler_states_dirty(struct r600_context *rctx,
730 struct r600_sampler_states *state);
731 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
732 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
733 uint32_t r600_translate_stencil_op(int s_op);
734 uint32_t r600_translate_fill(uint32_t func);
735 unsigned r600_tex_wrap(unsigned wrap);
736 unsigned r600_tex_filter(unsigned filter);
737 unsigned r600_tex_mipfilter(unsigned filter);
738 unsigned r600_tex_compare(unsigned compare);
739 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
740 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
741 struct pipe_resource *texture,
742 const struct pipe_surface *templ,
743 unsigned width, unsigned height);
744 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
745 const unsigned char *swizzle_view,
746 boolean vtx);
747 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
748 const unsigned char *swizzle_view,
749 uint32_t *word4_p, uint32_t *yuv_format_p);
750 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
751 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
752
753 /* r600_uvd.c */
754 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
755 const struct pipe_video_codec *decoder);
756
757 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
758 const struct pipe_video_buffer *tmpl);
759
760 /*
761 * Helpers for building command buffers
762 */
763
764 #define PKT3_SET_CONFIG_REG 0x68
765 #define PKT3_SET_CONTEXT_REG 0x69
766 #define PKT3_SET_CTL_CONST 0x6F
767 #define PKT3_SET_LOOP_CONST 0x6C
768
769 #define R600_CONFIG_REG_OFFSET 0x08000
770 #define R600_CONTEXT_REG_OFFSET 0x28000
771 #define R600_CTL_CONST_OFFSET 0x3CFF0
772 #define R600_LOOP_CONST_OFFSET 0X0003E200
773 #define EG_LOOP_CONST_OFFSET 0x0003A200
774
775 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
776 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
777 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
778 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
779 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
780
781 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
782
783 /*Evergreen Compute packet3*/
784 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
785
786 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
787 {
788 cb->buf[cb->num_dw++] = value;
789 }
790
791 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
792 {
793 assert(cb->num_dw+num <= cb->max_num_dw);
794 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
795 cb->num_dw += num;
796 }
797
798 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
799 {
800 assert(reg < R600_CONTEXT_REG_OFFSET);
801 assert(cb->num_dw+2+num <= cb->max_num_dw);
802 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
803 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
804 }
805
806 /**
807 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
808 * shaders.
809 */
810 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
811 {
812 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
813 assert(cb->num_dw+2+num <= cb->max_num_dw);
814 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
815 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
816 }
817
818 /**
819 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
820 * shaders.
821 */
822 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
823 {
824 assert(reg >= R600_CTL_CONST_OFFSET);
825 assert(cb->num_dw+2+num <= cb->max_num_dw);
826 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
827 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
828 }
829
830 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
831 {
832 assert(reg >= R600_LOOP_CONST_OFFSET);
833 assert(cb->num_dw+2+num <= cb->max_num_dw);
834 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
835 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
836 }
837
838 /**
839 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
840 * shaders.
841 */
842 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
843 {
844 assert(reg >= EG_LOOP_CONST_OFFSET);
845 assert(cb->num_dw+2+num <= cb->max_num_dw);
846 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
847 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
848 }
849
850 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
851 {
852 r600_store_config_reg_seq(cb, reg, 1);
853 r600_store_value(cb, value);
854 }
855
856 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
857 {
858 r600_store_context_reg_seq(cb, reg, 1);
859 r600_store_value(cb, value);
860 }
861
862 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
863 {
864 r600_store_ctl_const_seq(cb, reg, 1);
865 r600_store_value(cb, value);
866 }
867
868 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
869 {
870 r600_store_loop_const_seq(cb, reg, 1);
871 r600_store_value(cb, value);
872 }
873
874 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
875 {
876 eg_store_loop_const_seq(cb, reg, 1);
877 r600_store_value(cb, value);
878 }
879
880 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
881 void r600_release_command_buffer(struct r600_command_buffer *cb);
882
883 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
884 {
885 radeon_set_context_reg_seq(cs, reg, num);
886 /* Set the compute bit on the packet header */
887 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
888 }
889
890 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
891 {
892 assert(reg >= R600_CTL_CONST_OFFSET);
893 assert(cs->cdw+2+num <= cs->max_dw);
894 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
895 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
896 }
897
898 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
899 {
900 radeon_compute_set_context_reg_seq(cs, reg, 1);
901 radeon_emit(cs, value);
902 }
903
904 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
905 {
906 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
907 radeon_compute_set_context_reg(cs, reg, value);
908 } else {
909 radeon_set_context_reg(cs, reg, value);
910 }
911 }
912
913 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
914 {
915 radeon_set_ctl_const_seq(cs, reg, 1);
916 radeon_emit(cs, value);
917 }
918
919 /*
920 * common helpers
921 */
922 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
923 {
924 return value * (1 << frac_bits);
925 }
926 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
927
928 /* 12.4 fixed-point */
929 static inline unsigned r600_pack_float_12p4(float x)
930 {
931 return x <= 0 ? 0 :
932 x >= 4096 ? 0xffff : x * 16;
933 }
934
935 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
936 static inline bool r600_can_read_depth(struct r600_texture *rtex)
937 {
938 return rtex->resource.b.b.nr_samples <= 1 &&
939 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
940 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
941 }
942
943 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
944 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
945 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
946
947 unsigned r600_conv_prim_to_gs_out(unsigned mode);
948 #endif