2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
39 #include "tgsi/tgsi_scan.h"
41 #define R600_NUM_ATOMS 52
44 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
45 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
46 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
47 /* read-write caches */
48 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
49 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
51 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
52 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
53 /* engine synchronization */
54 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
55 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
56 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
58 /* the number of CS dwords for flushing and drawing */
59 #define R600_MAX_FLUSH_CS_DWORDS 18
60 #define R600_MAX_DRAW_CS_DWORDS 58
61 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
63 #define R600_MAX_USER_CONST_BUFFERS 13
64 #define R600_MAX_DRIVER_CONST_BUFFERS 3
65 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
67 /* start driver buffers after user buffers */
68 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
69 #define R600_UCP_SIZE (4*4*8)
70 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
72 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
74 * Note GS doesn't use a constant buffer binding, just a resource index,
75 * so it's fine to have it exist at index 16.
77 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
78 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
79 * of 16 const buffers.
80 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
82 * In order to support d3d 11 mandated minimum of 15 user const buffers
83 * we'd have to squash all use cases into one driver buffer.
85 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
88 #define R600_HW_STAGE_PS 0
89 #define R600_HW_STAGE_VS 1
90 #define R600_HW_STAGE_GS 2
91 #define R600_HW_STAGE_ES 3
92 #define EG_HW_STAGE_LS 4
93 #define EG_HW_STAGE_HS 5
95 #define R600_NUM_HW_STAGES 4
96 #define EG_NUM_HW_STAGES 6
100 union r600_shader_key
;
102 /* This is an atom containing GPU commands that never change.
103 * This is supposed to be copied directly into the CS. */
104 struct r600_command_buffer
{
111 struct r600_db_state
{
112 struct r600_atom atom
;
113 struct r600_surface
*rsurf
;
116 struct r600_db_misc_state
{
117 struct r600_atom atom
;
118 bool occlusion_queries_disabled
;
119 bool flush_depthstencil_through_cb
;
120 bool flush_depth_inplace
;
121 bool flush_stencil_inplace
;
122 bool copy_depth
, copy_stencil
;
123 unsigned copy_sample
;
124 unsigned log_samples
;
125 unsigned db_shader_control
;
127 uint8_t ps_conservative_z
;
130 struct r600_cb_misc_state
{
131 struct r600_atom atom
;
132 unsigned cb_color_control
; /* this comes from blend state */
133 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
135 unsigned nr_ps_color_outputs
;
140 struct r600_clip_misc_state
{
141 struct r600_atom atom
;
142 unsigned pa_cl_clip_cntl
; /* from rasterizer */
143 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
144 unsigned clip_plane_enable
; /* from rasterizer */
145 unsigned clip_dist_write
; /* from vertex shader */
146 boolean clip_disable
; /* from vertex shader */
147 boolean vs_out_viewport
; /* from vertex shader */
150 struct r600_alphatest_state
{
151 struct r600_atom atom
;
152 unsigned sx_alpha_test_control
; /* this comes from dsa state */
153 unsigned sx_alpha_ref
; /* this comes from dsa state */
155 bool cb0_export_16bpc
; /* from set_framebuffer_state */
158 struct r600_vgt_state
{
159 struct r600_atom atom
;
160 uint32_t vgt_multi_prim_ib_reset_en
;
161 uint32_t vgt_multi_prim_ib_reset_indx
;
162 uint32_t vgt_indx_offset
;
163 bool last_draw_was_indirect
;
166 struct r600_blend_color
{
167 struct r600_atom atom
;
168 struct pipe_blend_color state
;
171 struct r600_clip_state
{
172 struct r600_atom atom
;
173 struct pipe_clip_state state
;
176 struct r600_cs_shader_state
{
177 struct r600_atom atom
;
178 unsigned kernel_index
;
180 struct r600_pipe_compute
*shader
;
183 struct r600_framebuffer
{
184 struct r600_atom atom
;
185 struct pipe_framebuffer_state state
;
186 unsigned compressed_cb_mask
;
190 bool is_msaa_resolve
;
194 struct r600_sample_mask
{
195 struct r600_atom atom
;
196 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
199 struct r600_config_state
{
200 struct r600_atom atom
;
201 unsigned sq_gpr_resource_mgmt_1
;
202 unsigned sq_gpr_resource_mgmt_2
;
203 unsigned sq_gpr_resource_mgmt_3
;
204 bool dyn_gpr_enabled
;
207 struct r600_stencil_ref
214 struct r600_stencil_ref_state
{
215 struct r600_atom atom
;
216 struct r600_stencil_ref state
;
217 struct pipe_stencil_ref pipe_state
;
220 struct r600_shader_stages_state
{
221 struct r600_atom atom
;
222 unsigned geom_enable
;
225 struct r600_gs_rings_state
{
226 struct r600_atom atom
;
228 struct pipe_constant_buffer esgs_ring
;
229 struct pipe_constant_buffer gsvs_ring
;
232 /* This must start from 16. */
234 #define DBG_NO_CP_DMA (1 << 30)
236 #define DBG_NO_SB (1 << 21)
237 #define DBG_SB_CS (1 << 22)
238 #define DBG_SB_DRY_RUN (1 << 23)
239 #define DBG_SB_STAT (1 << 24)
240 #define DBG_SB_DUMP (1 << 25)
241 #define DBG_SB_NO_FALLBACK (1 << 26)
242 #define DBG_SB_DISASM (1 << 27)
243 #define DBG_SB_SAFEMATH (1 << 28)
246 struct r600_common_screen b
;
248 bool has_compressed_msaa_texturing
;
250 /*for compute global memory binding, we allocate stuff here, instead of
252 * XXX: Not sure if this is the best place for global_pool. Also,
253 * it's not thread safe, so it won't work with multiple contexts. */
254 struct compute_memory_pool
*global_pool
;
257 struct r600_pipe_sampler_view
{
258 struct pipe_sampler_view base
;
259 struct list_head list
;
260 struct r600_resource
*tex_resource
;
261 uint32_t tex_resource_words
[8];
262 bool skip_mip_address_reloc
;
263 bool is_stencil_sampler
;
266 struct r600_rasterizer_state
{
267 struct r600_command_buffer buffer
;
270 unsigned sprite_coord_enable
;
271 unsigned clip_plane_enable
;
272 unsigned pa_sc_line_stipple
;
273 unsigned pa_cl_clip_cntl
;
274 unsigned pa_su_sc_mode_cntl
;
278 bool offset_units_unscaled
;
280 bool multisample_enable
;
282 bool rasterizer_discard
;
285 struct r600_poly_offset_state
{
286 struct r600_atom atom
;
287 enum pipe_format zs_format
;
290 bool offset_units_unscaled
;
293 struct r600_blend_state
{
294 struct r600_command_buffer buffer
;
295 struct r600_command_buffer buffer_no_blend
;
296 unsigned cb_target_mask
;
297 unsigned cb_color_control
;
298 unsigned cb_color_control_no_blend
;
303 struct r600_dsa_state
{
304 struct r600_command_buffer buffer
;
309 unsigned sx_alpha_test_control
;
312 struct r600_pipe_shader
;
314 struct r600_pipe_shader_selector
{
315 struct r600_pipe_shader
*current
;
317 struct tgsi_token
*tokens
;
318 struct pipe_stream_output_info so
;
319 struct tgsi_shader_info info
;
321 unsigned num_shaders
;
323 enum pipe_shader_type type
;
325 /* geometry shader properties */
326 enum pipe_prim_type gs_output_prim
;
327 unsigned gs_max_out_vertices
;
328 unsigned gs_num_invocations
;
331 uint64_t lds_patch_outputs_written_mask
;
332 uint64_t lds_outputs_written_mask
;
333 unsigned nr_ps_max_color_exports
;
336 struct r600_pipe_sampler_state
{
337 uint32_t tex_sampler_words
[3];
338 union pipe_color_union border_color
;
339 bool border_color_use
;
340 bool seamless_cube_map
;
343 /* needed for blitter save */
344 #define NUM_TEX_UNITS 16
346 struct r600_seamless_cube_map
{
347 struct r600_atom atom
;
351 struct r600_samplerview_state
{
352 struct r600_atom atom
;
353 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
354 uint32_t enabled_mask
;
356 uint32_t compressed_depthtex_mask
; /* which textures are depth */
357 uint32_t compressed_colortex_mask
;
358 boolean dirty_buffer_constants
;
361 struct r600_sampler_states
{
362 struct r600_atom atom
;
363 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
364 uint32_t enabled_mask
;
366 uint32_t has_bordercolor_mask
; /* which states contain the border color */
369 struct r600_textures_info
{
370 struct r600_samplerview_state views
;
371 struct r600_sampler_states states
;
372 bool is_array_sampler
[NUM_TEX_UNITS
];
375 struct r600_shader_driver_constants_info
{
376 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
380 bool texture_const_dirty
;
381 bool ps_sample_pos_dirty
;
384 struct r600_constbuf_state
386 struct r600_atom atom
;
387 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
388 uint32_t enabled_mask
;
392 struct r600_vertexbuf_state
394 struct r600_atom atom
;
395 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
396 uint32_t enabled_mask
; /* non-NULL buffers */
400 /* CSO (constant state object, in other words, immutable state). */
401 struct r600_cso_state
403 struct r600_atom atom
;
404 void *cso
; /* e.g. r600_blend_state */
405 struct r600_command_buffer
*cb
;
408 struct r600_fetch_shader
{
409 struct r600_resource
*buffer
;
413 struct r600_shader_state
{
414 struct r600_atom atom
;
415 struct r600_pipe_shader
*shader
;
418 struct r600_context
{
419 struct r600_common_context b
;
420 struct r600_screen
*screen
;
421 struct blitter_context
*blitter
;
422 struct u_suballocator
*allocator_fetch_shader
;
425 boolean has_vertex_cache
;
426 unsigned default_gprs
[EG_NUM_HW_STAGES
];
427 unsigned current_gprs
[EG_NUM_HW_STAGES
];
428 unsigned r6xx_num_clause_temp_gprs
;
430 /* Miscellaneous state objects. */
431 void *custom_dsa_flush
;
432 void *custom_blend_resolve
;
433 void *custom_blend_decompress
;
434 void *custom_blend_fastclear
;
435 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
436 * bug where valid CMASK and FMASK are required to be present to avoid
437 * a hardlock in certain operations but aren't actually used
438 * for anything useful. */
439 struct r600_resource
*dummy_fmask
;
440 struct r600_resource
*dummy_cmask
;
442 /* State binding slots are here. */
443 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
444 /* Dirty atom bitmask for fast tests */
445 uint64_t dirty_atoms
;
446 /* States for CS initialization. */
447 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
448 /** Compute specific registers initializations. The start_cs_cmd atom
449 * must be emitted before start_compute_cs_cmd. */
450 struct r600_command_buffer start_compute_cs_cmd
;
451 /* Register states. */
452 struct r600_alphatest_state alphatest_state
;
453 struct r600_cso_state blend_state
;
454 struct r600_blend_color blend_color
;
455 struct r600_cb_misc_state cb_misc_state
;
456 struct r600_clip_misc_state clip_misc_state
;
457 struct r600_clip_state clip_state
;
458 struct r600_db_misc_state db_misc_state
;
459 struct r600_db_state db_state
;
460 struct r600_cso_state dsa_state
;
461 struct r600_framebuffer framebuffer
;
462 struct r600_poly_offset_state poly_offset_state
;
463 struct r600_cso_state rasterizer_state
;
464 struct r600_sample_mask sample_mask
;
465 struct r600_seamless_cube_map seamless_cube_map
;
466 struct r600_config_state config_state
;
467 struct r600_stencil_ref_state stencil_ref
;
468 struct r600_vgt_state vgt_state
;
469 /* Shaders and shader resources. */
470 struct r600_cso_state vertex_fetch_shader
;
471 struct r600_shader_state hw_shader_stages
[EG_NUM_HW_STAGES
];
472 struct r600_cs_shader_state cs_shader_state
;
473 struct r600_shader_stages_state shader_stages
;
474 struct r600_gs_rings_state gs_rings
;
475 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
476 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
478 struct r600_shader_driver_constants_info driver_consts
[PIPE_SHADER_TYPES
];
480 /** Vertex buffers for fetch shaders */
481 struct r600_vertexbuf_state vertex_buffer_state
;
482 /** Vertex buffers for compute shaders */
483 struct r600_vertexbuf_state cs_vertex_buffer_state
;
485 /* Additional context states. */
486 unsigned compute_cb_target_mask
;
487 struct r600_pipe_shader_selector
*ps_shader
;
488 struct r600_pipe_shader_selector
*vs_shader
;
489 struct r600_pipe_shader_selector
*gs_shader
;
491 struct r600_pipe_shader_selector
*tcs_shader
;
492 struct r600_pipe_shader_selector
*tes_shader
;
494 struct r600_pipe_shader_selector
*fixed_func_tcs_shader
;
496 struct r600_rasterizer_state
*rasterizer
;
498 bool force_blend_disable
;
499 boolean dual_src_blend
;
503 /* The list of all texture buffer objects in this context.
504 * This list is walked when a buffer is invalidated/reallocated and
505 * the GPU addresses are updated. */
506 struct list_head texture_buffers
;
509 struct pipe_index_buffer index_buffer
;
511 /* Last draw state (-1 = unset). */
512 enum pipe_prim_type last_primitive_type
; /* Last primitive type used in draw_vbo. */
513 enum pipe_prim_type current_rast_prim
; /* primitive type after TES, GS */
514 enum pipe_prim_type last_rast_prim
;
515 unsigned last_start_instance
;
518 struct r600_isa
*isa
;
519 float sample_positions
[4 * 16];
521 bool tess_state_dirty
;
522 struct r600_pipe_shader_selector
*last_ls
;
523 struct r600_pipe_shader_selector
*last_tcs
;
524 unsigned last_num_tcs_input_cp
;
528 static inline void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
529 struct r600_command_buffer
*cb
)
531 assert(cs
->current
.cdw
+ cb
->num_dw
<= cs
->current
.max_dw
);
532 memcpy(cs
->current
.buf
+ cs
->current
.cdw
, cb
->buf
, 4 * cb
->num_dw
);
533 cs
->current
.cdw
+= cb
->num_dw
;
536 static inline void r600_set_atom_dirty(struct r600_context
*rctx
,
537 struct r600_atom
*atom
,
542 assert(atom
->id
!= 0);
543 assert(atom
->id
< sizeof(mask
) * 8);
544 mask
= 1ull << atom
->id
;
546 rctx
->dirty_atoms
|= mask
;
548 rctx
->dirty_atoms
&= ~mask
;
551 static inline void r600_mark_atom_dirty(struct r600_context
*rctx
,
552 struct r600_atom
*atom
)
554 r600_set_atom_dirty(rctx
, atom
, true);
557 static inline void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
559 atom
->emit(&rctx
->b
, atom
);
560 r600_set_atom_dirty(rctx
, atom
, false);
563 static inline void r600_set_cso_state(struct r600_context
*rctx
,
564 struct r600_cso_state
*state
, void *cso
)
567 r600_set_atom_dirty(rctx
, &state
->atom
, cso
!= NULL
);
570 static inline void r600_set_cso_state_with_cb(struct r600_context
*rctx
,
571 struct r600_cso_state
*state
, void *cso
,
572 struct r600_command_buffer
*cb
)
575 state
->atom
.num_dw
= cb
? cb
->num_dw
: 0;
576 r600_set_cso_state(rctx
, state
, cso
);
579 /* compute_memory_pool.c */
580 struct compute_memory_pool
;
581 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
582 struct compute_memory_pool
* compute_memory_pool_new(
583 struct r600_screen
*rscreen
);
585 /* evergreen_state.c */
586 struct pipe_sampler_view
*
587 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
588 struct pipe_resource
*texture
,
589 const struct pipe_sampler_view
*state
,
590 unsigned width0
, unsigned height0
,
591 unsigned force_level
);
592 void evergreen_init_common_regs(struct r600_context
*ctx
,
593 struct r600_command_buffer
*cb
,
594 enum chip_class ctx_chip_class
,
595 enum radeon_family ctx_family
,
597 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
598 enum chip_class ctx_chip_class
,
599 enum radeon_family ctx_family
,
602 void evergreen_init_state_functions(struct r600_context
*rctx
);
603 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
604 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
605 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
606 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
607 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
608 void evergreen_update_ls_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
609 void evergreen_update_hs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
610 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
611 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
612 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
613 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
614 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
615 enum pipe_format format
,
616 enum pipe_texture_target target
,
617 unsigned sample_count
,
619 void evergreen_init_color_surface(struct r600_context
*rctx
,
620 struct r600_surface
*surf
);
621 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
622 struct r600_surface
*surf
);
623 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
624 bool evergreen_adjust_gprs(struct r600_context
*rctx
);
626 void r600_init_blit_functions(struct r600_context
*rctx
);
627 void r600_decompress_depth_textures(struct r600_context
*rctx
,
628 struct r600_samplerview_state
*textures
);
629 void r600_decompress_color_textures(struct r600_context
*rctx
,
630 struct r600_samplerview_state
*textures
);
631 void r600_resource_copy_region(struct pipe_context
*ctx
,
632 struct pipe_resource
*dst
,
634 unsigned dstx
, unsigned dsty
, unsigned dstz
,
635 struct pipe_resource
*src
,
637 const struct pipe_box
*src_box
);
640 int r600_pipe_shader_create(struct pipe_context
*ctx
,
641 struct r600_pipe_shader
*shader
,
642 union r600_shader_key key
);
644 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
647 struct pipe_sampler_view
*
648 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
649 struct pipe_resource
*texture
,
650 const struct pipe_sampler_view
*state
,
651 unsigned width_first_level
, unsigned height_first_level
);
652 void r600_init_state_functions(struct r600_context
*rctx
);
653 void r600_init_atom_start_cs(struct r600_context
*rctx
);
654 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
655 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
656 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
657 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
658 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
659 void *r600_create_resolve_blend(struct r600_context
*rctx
);
660 void *r700_create_resolve_blend(struct r600_context
*rctx
);
661 void *r600_create_decompress_blend(struct r600_context
*rctx
);
662 bool r600_adjust_gprs(struct r600_context
*rctx
);
663 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
664 enum pipe_format format
,
665 enum pipe_texture_target target
,
666 unsigned sample_count
,
668 void r600_update_db_shader_control(struct r600_context
* rctx
);
670 /* r600_hw_context.c */
671 void r600_context_gfx_flush(void *context
, unsigned flags
,
672 struct pipe_fence_handle
**fence
);
673 void r600_begin_new_cs(struct r600_context
*ctx
);
674 void r600_flush_emit(struct r600_context
*ctx
);
675 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
676 void r600_emit_pfp_sync_me(struct r600_context
*rctx
);
677 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
678 struct pipe_resource
*dst
, uint64_t dst_offset
,
679 struct pipe_resource
*src
, uint64_t src_offset
,
681 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
682 struct pipe_resource
*dst
, uint64_t offset
,
683 unsigned size
, uint32_t clear_value
,
684 enum r600_coherency coher
);
685 void r600_dma_copy_buffer(struct r600_context
*rctx
,
686 struct pipe_resource
*dst
,
687 struct pipe_resource
*src
,
693 * evergreen_hw_context.c
695 void evergreen_dma_copy_buffer(struct r600_context
*rctx
,
696 struct pipe_resource
*dst
,
697 struct pipe_resource
*src
,
701 void evergreen_setup_tess_constants(struct r600_context
*rctx
,
702 const struct pipe_draw_info
*info
,
703 unsigned *num_patches
);
704 uint32_t evergreen_get_ls_hs_config(struct r600_context
*rctx
,
705 const struct pipe_draw_info
*info
,
706 unsigned num_patches
);
707 void evergreen_set_ls_hs_config(struct r600_context
*rctx
,
708 struct radeon_winsys_cs
*cs
,
709 uint32_t ls_hs_config
);
710 void evergreen_set_lds_alloc(struct r600_context
*rctx
,
711 struct radeon_winsys_cs
*cs
,
714 /* r600_state_common.c */
715 void r600_init_common_state_functions(struct r600_context
*rctx
);
716 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
717 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
718 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
719 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
720 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
721 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
722 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
723 void r600_add_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
);
724 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
725 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
727 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
728 void r600_sampler_views_dirty(struct r600_context
*rctx
,
729 struct r600_samplerview_state
*state
);
730 void r600_sampler_states_dirty(struct r600_context
*rctx
,
731 struct r600_sampler_states
*state
);
732 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
733 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
);
734 uint32_t r600_translate_stencil_op(int s_op
);
735 uint32_t r600_translate_fill(uint32_t func
);
736 unsigned r600_tex_wrap(unsigned wrap
);
737 unsigned r600_tex_mipfilter(unsigned filter
);
738 unsigned r600_tex_compare(unsigned compare
);
739 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
740 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
741 const unsigned char *swizzle_view
,
743 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
744 const unsigned char *swizzle_view
,
745 uint32_t *word4_p
, uint32_t *yuv_format_p
,
746 bool do_endian_swap
);
747 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
,
748 bool do_endian_swap
);
749 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
, bool do_endian_swap
);
752 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
753 const struct pipe_video_codec
*decoder
);
755 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
756 const struct pipe_video_buffer
*tmpl
);
759 * Helpers for building command buffers
762 #define PKT3_SET_CONFIG_REG 0x68
763 #define PKT3_SET_CONTEXT_REG 0x69
764 #define PKT3_SET_CTL_CONST 0x6F
765 #define PKT3_SET_LOOP_CONST 0x6C
767 #define R600_CONFIG_REG_OFFSET 0x08000
768 #define R600_CONTEXT_REG_OFFSET 0x28000
769 #define R600_CTL_CONST_OFFSET 0x3CFF0
770 #define R600_LOOP_CONST_OFFSET 0X0003E200
771 #define EG_LOOP_CONST_OFFSET 0x0003A200
773 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
774 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
775 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
776 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
777 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
779 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
781 /*Evergreen Compute packet3*/
782 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
784 static inline void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
786 cb
->buf
[cb
->num_dw
++] = value
;
789 static inline void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
791 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
792 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
796 static inline void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
798 assert(reg
< R600_CONTEXT_REG_OFFSET
);
799 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
800 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
801 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
805 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
808 static inline void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
810 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
811 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
812 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
813 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
817 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
820 static inline void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
822 assert(reg
>= R600_CTL_CONST_OFFSET
);
823 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
824 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
825 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
828 static inline void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
830 assert(reg
>= R600_LOOP_CONST_OFFSET
);
831 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
832 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
833 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
837 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
840 static inline void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
842 assert(reg
>= EG_LOOP_CONST_OFFSET
);
843 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
844 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
845 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
848 static inline void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
850 r600_store_config_reg_seq(cb
, reg
, 1);
851 r600_store_value(cb
, value
);
854 static inline void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
856 r600_store_context_reg_seq(cb
, reg
, 1);
857 r600_store_value(cb
, value
);
860 static inline void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
862 r600_store_ctl_const_seq(cb
, reg
, 1);
863 r600_store_value(cb
, value
);
866 static inline void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
868 r600_store_loop_const_seq(cb
, reg
, 1);
869 r600_store_value(cb
, value
);
872 static inline void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
874 eg_store_loop_const_seq(cb
, reg
, 1);
875 r600_store_value(cb
, value
);
878 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
879 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
881 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
883 radeon_set_context_reg_seq(cs
, reg
, num
);
884 /* Set the compute bit on the packet header */
885 cs
->current
.buf
[cs
->current
.cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
888 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
890 assert(reg
>= R600_CTL_CONST_OFFSET
);
891 assert(cs
->current
.cdw
+ 2 + num
<= cs
->current
.max_dw
);
892 radeon_emit(cs
, PKT3(PKT3_SET_CTL_CONST
, num
, 0));
893 radeon_emit(cs
, (reg
- R600_CTL_CONST_OFFSET
) >> 2);
896 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
898 radeon_compute_set_context_reg_seq(cs
, reg
, 1);
899 radeon_emit(cs
, value
);
902 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
904 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
905 radeon_compute_set_context_reg(cs
, reg
, value
);
907 radeon_set_context_reg(cs
, reg
, value
);
911 static inline void radeon_set_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
913 radeon_set_ctl_const_seq(cs
, reg
, 1);
914 radeon_emit(cs
, value
);
920 static inline uint32_t S_FIXED(float value
, uint32_t frac_bits
)
922 return value
* (1 << frac_bits
);
925 /* 12.4 fixed-point */
926 static inline unsigned r600_pack_float_12p4(float x
)
929 x
>= 4096 ? 0xffff : x
* 16;
932 static inline unsigned r600_get_flush_flags(enum r600_coherency coher
)
936 case R600_COHERENCY_NONE
:
938 case R600_COHERENCY_SHADER
:
939 return R600_CONTEXT_INV_CONST_CACHE
|
940 R600_CONTEXT_INV_VERTEX_CACHE
|
941 R600_CONTEXT_INV_TEX_CACHE
|
942 R600_CONTEXT_STREAMOUT_FLUSH
;
943 case R600_COHERENCY_CB_META
:
944 return R600_CONTEXT_FLUSH_AND_INV_CB
|
945 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
949 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
950 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
951 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
953 unsigned r600_conv_prim_to_gs_out(unsigned mode
);