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gallium/radeon: move r600_common_context::texture_buffers to r600g
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
36 #include "util/u_memory.h"
37
38 #include "tgsi/tgsi_scan.h"
39
40 #define R600_NUM_ATOMS 52
41
42 /* read caches */
43 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
44 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
45 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
46 /* read-write caches */
47 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
48 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
49 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
52 /* engine synchronization */
53 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
54 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
55 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
56
57 /* the number of CS dwords for flushing and drawing */
58 #define R600_MAX_FLUSH_CS_DWORDS 18
59 #define R600_MAX_DRAW_CS_DWORDS 58
60 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
61
62 #define R600_MAX_USER_CONST_BUFFERS 13
63 #define R600_MAX_DRIVER_CONST_BUFFERS 3
64 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
65
66 /* start driver buffers after user buffers */
67 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
68 #define R600_UCP_SIZE (4*4*8)
69 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
70
71 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
72 /*
73 * Note GS doesn't use a constant buffer binding, just a resource index,
74 * so it's fine to have it exist at index 16.
75 */
76 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
77 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
78 * of 16 const buffers.
79 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
80 *
81 * In order to support d3d 11 mandated minimum of 15 user const buffers
82 * we'd have to squash all use cases into one driver buffer.
83 */
84 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
85
86 /* HW stages */
87 #define R600_HW_STAGE_PS 0
88 #define R600_HW_STAGE_VS 1
89 #define R600_HW_STAGE_GS 2
90 #define R600_HW_STAGE_ES 3
91 #define EG_HW_STAGE_LS 4
92 #define EG_HW_STAGE_HS 5
93
94 #define R600_NUM_HW_STAGES 4
95 #define EG_NUM_HW_STAGES 6
96
97 struct r600_context;
98 struct r600_bytecode;
99 union r600_shader_key;
100
101 /* This is an atom containing GPU commands that never change.
102 * This is supposed to be copied directly into the CS. */
103 struct r600_command_buffer {
104 uint32_t *buf;
105 unsigned num_dw;
106 unsigned max_num_dw;
107 unsigned pkt_flags;
108 };
109
110 struct r600_db_state {
111 struct r600_atom atom;
112 struct r600_surface *rsurf;
113 };
114
115 struct r600_db_misc_state {
116 struct r600_atom atom;
117 bool occlusion_queries_disabled;
118 bool flush_depthstencil_through_cb;
119 bool flush_depth_inplace;
120 bool flush_stencil_inplace;
121 bool copy_depth, copy_stencil;
122 unsigned copy_sample;
123 unsigned log_samples;
124 unsigned db_shader_control;
125 bool htile_clear;
126 uint8_t ps_conservative_z;
127 };
128
129 struct r600_cb_misc_state {
130 struct r600_atom atom;
131 unsigned cb_color_control; /* this comes from blend state */
132 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
133 unsigned nr_cbufs;
134 unsigned nr_ps_color_outputs;
135 bool multiwrite;
136 bool dual_src_blend;
137 };
138
139 struct r600_clip_misc_state {
140 struct r600_atom atom;
141 unsigned pa_cl_clip_cntl; /* from rasterizer */
142 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
143 unsigned clip_plane_enable; /* from rasterizer */
144 unsigned clip_dist_write; /* from vertex shader */
145 boolean clip_disable; /* from vertex shader */
146 boolean vs_out_viewport; /* from vertex shader */
147 };
148
149 struct r600_alphatest_state {
150 struct r600_atom atom;
151 unsigned sx_alpha_test_control; /* this comes from dsa state */
152 unsigned sx_alpha_ref; /* this comes from dsa state */
153 bool bypass;
154 bool cb0_export_16bpc; /* from set_framebuffer_state */
155 };
156
157 struct r600_vgt_state {
158 struct r600_atom atom;
159 uint32_t vgt_multi_prim_ib_reset_en;
160 uint32_t vgt_multi_prim_ib_reset_indx;
161 uint32_t vgt_indx_offset;
162 bool last_draw_was_indirect;
163 };
164
165 struct r600_blend_color {
166 struct r600_atom atom;
167 struct pipe_blend_color state;
168 };
169
170 struct r600_clip_state {
171 struct r600_atom atom;
172 struct pipe_clip_state state;
173 };
174
175 struct r600_cs_shader_state {
176 struct r600_atom atom;
177 unsigned kernel_index;
178 unsigned pc;
179 struct r600_pipe_compute *shader;
180 };
181
182 struct r600_framebuffer {
183 struct r600_atom atom;
184 struct pipe_framebuffer_state state;
185 unsigned compressed_cb_mask;
186 unsigned nr_samples;
187 bool export_16bpc;
188 bool cb0_is_integer;
189 bool is_msaa_resolve;
190 };
191
192 struct r600_sample_mask {
193 struct r600_atom atom;
194 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
195 };
196
197 struct r600_config_state {
198 struct r600_atom atom;
199 unsigned sq_gpr_resource_mgmt_1;
200 unsigned sq_gpr_resource_mgmt_2;
201 unsigned sq_gpr_resource_mgmt_3;
202 bool dyn_gpr_enabled;
203 };
204
205 struct r600_stencil_ref
206 {
207 ubyte ref_value[2];
208 ubyte valuemask[2];
209 ubyte writemask[2];
210 };
211
212 struct r600_stencil_ref_state {
213 struct r600_atom atom;
214 struct r600_stencil_ref state;
215 struct pipe_stencil_ref pipe_state;
216 };
217
218 struct r600_shader_stages_state {
219 struct r600_atom atom;
220 unsigned geom_enable;
221 };
222
223 struct r600_gs_rings_state {
224 struct r600_atom atom;
225 unsigned enable;
226 struct pipe_constant_buffer esgs_ring;
227 struct pipe_constant_buffer gsvs_ring;
228 };
229
230 /* This must start from 16. */
231 /* features */
232 #define DBG_NO_CP_DMA (1 << 30)
233 /* shader backend */
234 #define DBG_NO_SB (1 << 21)
235 #define DBG_SB_CS (1 << 22)
236 #define DBG_SB_DRY_RUN (1 << 23)
237 #define DBG_SB_STAT (1 << 24)
238 #define DBG_SB_DUMP (1 << 25)
239 #define DBG_SB_NO_FALLBACK (1 << 26)
240 #define DBG_SB_DISASM (1 << 27)
241 #define DBG_SB_SAFEMATH (1 << 28)
242
243 struct r600_screen {
244 struct r600_common_screen b;
245 bool has_msaa;
246 bool has_compressed_msaa_texturing;
247
248 /*for compute global memory binding, we allocate stuff here, instead of
249 * buffers.
250 * XXX: Not sure if this is the best place for global_pool. Also,
251 * it's not thread safe, so it won't work with multiple contexts. */
252 struct compute_memory_pool *global_pool;
253 };
254
255 struct r600_pipe_sampler_view {
256 struct pipe_sampler_view base;
257 struct list_head list;
258 struct r600_resource *tex_resource;
259 uint32_t tex_resource_words[8];
260 bool skip_mip_address_reloc;
261 bool is_stencil_sampler;
262 };
263
264 struct r600_rasterizer_state {
265 struct r600_command_buffer buffer;
266 boolean flatshade;
267 boolean two_side;
268 unsigned sprite_coord_enable;
269 unsigned clip_plane_enable;
270 unsigned pa_sc_line_stipple;
271 unsigned pa_cl_clip_cntl;
272 unsigned pa_su_sc_mode_cntl;
273 float offset_units;
274 float offset_scale;
275 bool offset_enable;
276 bool offset_units_unscaled;
277 bool scissor_enable;
278 bool multisample_enable;
279 bool clip_halfz;
280 };
281
282 struct r600_poly_offset_state {
283 struct r600_atom atom;
284 enum pipe_format zs_format;
285 float offset_units;
286 float offset_scale;
287 bool offset_units_unscaled;
288 };
289
290 struct r600_blend_state {
291 struct r600_command_buffer buffer;
292 struct r600_command_buffer buffer_no_blend;
293 unsigned cb_target_mask;
294 unsigned cb_color_control;
295 unsigned cb_color_control_no_blend;
296 bool dual_src_blend;
297 bool alpha_to_one;
298 };
299
300 struct r600_dsa_state {
301 struct r600_command_buffer buffer;
302 unsigned alpha_ref;
303 ubyte valuemask[2];
304 ubyte writemask[2];
305 unsigned zwritemask;
306 unsigned sx_alpha_test_control;
307 };
308
309 struct r600_pipe_shader;
310
311 struct r600_pipe_shader_selector {
312 struct r600_pipe_shader *current;
313
314 struct tgsi_token *tokens;
315 struct pipe_stream_output_info so;
316 struct tgsi_shader_info info;
317
318 unsigned num_shaders;
319
320 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
321 unsigned type;
322
323 /* geometry shader properties */
324 unsigned gs_output_prim;
325 unsigned gs_max_out_vertices;
326 unsigned gs_num_invocations;
327
328 /* TCS/VS */
329 uint64_t lds_patch_outputs_written_mask;
330 uint64_t lds_outputs_written_mask;
331 unsigned nr_ps_max_color_exports;
332 };
333
334 struct r600_pipe_sampler_state {
335 uint32_t tex_sampler_words[3];
336 union pipe_color_union border_color;
337 bool border_color_use;
338 bool seamless_cube_map;
339 };
340
341 /* needed for blitter save */
342 #define NUM_TEX_UNITS 16
343
344 struct r600_seamless_cube_map {
345 struct r600_atom atom;
346 bool enabled;
347 };
348
349 struct r600_samplerview_state {
350 struct r600_atom atom;
351 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
352 uint32_t enabled_mask;
353 uint32_t dirty_mask;
354 uint32_t compressed_depthtex_mask; /* which textures are depth */
355 uint32_t compressed_colortex_mask;
356 boolean dirty_buffer_constants;
357 };
358
359 struct r600_sampler_states {
360 struct r600_atom atom;
361 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
362 uint32_t enabled_mask;
363 uint32_t dirty_mask;
364 uint32_t has_bordercolor_mask; /* which states contain the border color */
365 };
366
367 struct r600_textures_info {
368 struct r600_samplerview_state views;
369 struct r600_sampler_states states;
370 bool is_array_sampler[NUM_TEX_UNITS];
371 };
372
373 struct r600_shader_driver_constants_info {
374 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
375 uint32_t *constants;
376 uint32_t alloc_size;
377 bool vs_ucp_dirty;
378 bool texture_const_dirty;
379 bool ps_sample_pos_dirty;
380 };
381
382 struct r600_constbuf_state
383 {
384 struct r600_atom atom;
385 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
386 uint32_t enabled_mask;
387 uint32_t dirty_mask;
388 };
389
390 struct r600_vertexbuf_state
391 {
392 struct r600_atom atom;
393 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
394 uint32_t enabled_mask; /* non-NULL buffers */
395 uint32_t dirty_mask;
396 };
397
398 /* CSO (constant state object, in other words, immutable state). */
399 struct r600_cso_state
400 {
401 struct r600_atom atom;
402 void *cso; /* e.g. r600_blend_state */
403 struct r600_command_buffer *cb;
404 };
405
406 struct r600_fetch_shader {
407 struct r600_resource *buffer;
408 unsigned offset;
409 };
410
411 struct r600_shader_state {
412 struct r600_atom atom;
413 struct r600_pipe_shader *shader;
414 };
415
416 struct r600_context {
417 struct r600_common_context b;
418 struct r600_screen *screen;
419 struct blitter_context *blitter;
420 struct u_suballocator *allocator_fetch_shader;
421
422 /* Hardware info. */
423 boolean has_vertex_cache;
424 unsigned default_gprs[EG_NUM_HW_STAGES];
425 unsigned current_gprs[EG_NUM_HW_STAGES];
426 unsigned r6xx_num_clause_temp_gprs;
427
428 /* Miscellaneous state objects. */
429 void *custom_dsa_flush;
430 void *custom_blend_resolve;
431 void *custom_blend_decompress;
432 void *custom_blend_fastclear;
433 /* With rasterizer discard, there doesn't have to be a pixel shader.
434 * In that case, we bind this one: */
435 void *dummy_pixel_shader;
436 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
437 * bug where valid CMASK and FMASK are required to be present to avoid
438 * a hardlock in certain operations but aren't actually used
439 * for anything useful. */
440 struct r600_resource *dummy_fmask;
441 struct r600_resource *dummy_cmask;
442
443 /* State binding slots are here. */
444 struct r600_atom *atoms[R600_NUM_ATOMS];
445 /* Dirty atom bitmask for fast tests */
446 uint64_t dirty_atoms;
447 /* States for CS initialization. */
448 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
449 /** Compute specific registers initializations. The start_cs_cmd atom
450 * must be emitted before start_compute_cs_cmd. */
451 struct r600_command_buffer start_compute_cs_cmd;
452 /* Register states. */
453 struct r600_alphatest_state alphatest_state;
454 struct r600_cso_state blend_state;
455 struct r600_blend_color blend_color;
456 struct r600_cb_misc_state cb_misc_state;
457 struct r600_clip_misc_state clip_misc_state;
458 struct r600_clip_state clip_state;
459 struct r600_db_misc_state db_misc_state;
460 struct r600_db_state db_state;
461 struct r600_cso_state dsa_state;
462 struct r600_framebuffer framebuffer;
463 struct r600_poly_offset_state poly_offset_state;
464 struct r600_cso_state rasterizer_state;
465 struct r600_sample_mask sample_mask;
466 struct r600_seamless_cube_map seamless_cube_map;
467 struct r600_config_state config_state;
468 struct r600_stencil_ref_state stencil_ref;
469 struct r600_vgt_state vgt_state;
470 /* Shaders and shader resources. */
471 struct r600_cso_state vertex_fetch_shader;
472 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
473 struct r600_cs_shader_state cs_shader_state;
474 struct r600_shader_stages_state shader_stages;
475 struct r600_gs_rings_state gs_rings;
476 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
477 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
478
479 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
480
481 /** Vertex buffers for fetch shaders */
482 struct r600_vertexbuf_state vertex_buffer_state;
483 /** Vertex buffers for compute shaders */
484 struct r600_vertexbuf_state cs_vertex_buffer_state;
485
486 /* Additional context states. */
487 unsigned compute_cb_target_mask;
488 struct r600_pipe_shader_selector *ps_shader;
489 struct r600_pipe_shader_selector *vs_shader;
490 struct r600_pipe_shader_selector *gs_shader;
491
492 struct r600_pipe_shader_selector *tcs_shader;
493 struct r600_pipe_shader_selector *tes_shader;
494
495 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
496
497 struct r600_rasterizer_state *rasterizer;
498 bool alpha_to_one;
499 bool force_blend_disable;
500 boolean dual_src_blend;
501 unsigned zwritemask;
502 int ps_iter_samples;
503
504 /* The list of all texture buffer objects in this context.
505 * This list is walked when a buffer is invalidated/reallocated and
506 * the GPU addresses are updated. */
507 struct list_head texture_buffers;
508
509 /* Index buffer. */
510 struct pipe_index_buffer index_buffer;
511
512 /* Last draw state (-1 = unset). */
513 int last_primitive_type; /* Last primitive type used in draw_vbo. */
514 int last_start_instance;
515
516 void *sb_context;
517 struct r600_isa *isa;
518 float sample_positions[4 * 16];
519 float tess_state[8];
520 bool tess_state_dirty;
521 struct r600_pipe_shader_selector *last_ls;
522 struct r600_pipe_shader_selector *last_tcs;
523 unsigned last_num_tcs_input_cp;
524 unsigned lds_alloc;
525 };
526
527 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
528 struct r600_command_buffer *cb)
529 {
530 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
531 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
532 cs->current.cdw += cb->num_dw;
533 }
534
535 static inline void r600_set_atom_dirty(struct r600_context *rctx,
536 struct r600_atom *atom,
537 bool dirty)
538 {
539 uint64_t mask;
540
541 assert(atom->id != 0);
542 assert(atom->id < sizeof(mask) * 8);
543 mask = 1ull << atom->id;
544 if (dirty)
545 rctx->dirty_atoms |= mask;
546 else
547 rctx->dirty_atoms &= ~mask;
548 }
549
550 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
551 struct r600_atom *atom)
552 {
553 r600_set_atom_dirty(rctx, atom, true);
554 }
555
556 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
557 {
558 atom->emit(&rctx->b, atom);
559 r600_set_atom_dirty(rctx, atom, false);
560 }
561
562 static inline void r600_set_cso_state(struct r600_context *rctx,
563 struct r600_cso_state *state, void *cso)
564 {
565 state->cso = cso;
566 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
567 }
568
569 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
570 struct r600_cso_state *state, void *cso,
571 struct r600_command_buffer *cb)
572 {
573 state->cb = cb;
574 state->atom.num_dw = cb ? cb->num_dw : 0;
575 r600_set_cso_state(rctx, state, cso);
576 }
577
578 /* compute_memory_pool.c */
579 struct compute_memory_pool;
580 void compute_memory_pool_delete(struct compute_memory_pool* pool);
581 struct compute_memory_pool* compute_memory_pool_new(
582 struct r600_screen *rscreen);
583
584 /* evergreen_state.c */
585 struct pipe_sampler_view *
586 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
587 struct pipe_resource *texture,
588 const struct pipe_sampler_view *state,
589 unsigned width0, unsigned height0,
590 unsigned force_level);
591 void evergreen_init_common_regs(struct r600_context *ctx,
592 struct r600_command_buffer *cb,
593 enum chip_class ctx_chip_class,
594 enum radeon_family ctx_family,
595 int ctx_drm_minor);
596 void cayman_init_common_regs(struct r600_command_buffer *cb,
597 enum chip_class ctx_chip_class,
598 enum radeon_family ctx_family,
599 int ctx_drm_minor);
600
601 void evergreen_init_state_functions(struct r600_context *rctx);
602 void evergreen_init_atom_start_cs(struct r600_context *rctx);
603 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
604 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
605 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
606 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
607 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
608 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
609 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
610 void *evergreen_create_resolve_blend(struct r600_context *rctx);
611 void *evergreen_create_decompress_blend(struct r600_context *rctx);
612 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
613 boolean evergreen_is_format_supported(struct pipe_screen *screen,
614 enum pipe_format format,
615 enum pipe_texture_target target,
616 unsigned sample_count,
617 unsigned usage);
618 void evergreen_init_color_surface(struct r600_context *rctx,
619 struct r600_surface *surf);
620 void evergreen_init_color_surface_rat(struct r600_context *rctx,
621 struct r600_surface *surf);
622 void evergreen_update_db_shader_control(struct r600_context * rctx);
623 bool evergreen_adjust_gprs(struct r600_context *rctx);
624 /* r600_blit.c */
625 void r600_init_blit_functions(struct r600_context *rctx);
626 void r600_decompress_depth_textures(struct r600_context *rctx,
627 struct r600_samplerview_state *textures);
628 void r600_decompress_color_textures(struct r600_context *rctx,
629 struct r600_samplerview_state *textures);
630 void r600_resource_copy_region(struct pipe_context *ctx,
631 struct pipe_resource *dst,
632 unsigned dst_level,
633 unsigned dstx, unsigned dsty, unsigned dstz,
634 struct pipe_resource *src,
635 unsigned src_level,
636 const struct pipe_box *src_box);
637
638 /* r600_shader.c */
639 int r600_pipe_shader_create(struct pipe_context *ctx,
640 struct r600_pipe_shader *shader,
641 union r600_shader_key key);
642
643 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
644
645 /* r600_state.c */
646 struct pipe_sampler_view *
647 r600_create_sampler_view_custom(struct pipe_context *ctx,
648 struct pipe_resource *texture,
649 const struct pipe_sampler_view *state,
650 unsigned width_first_level, unsigned height_first_level);
651 void r600_init_state_functions(struct r600_context *rctx);
652 void r600_init_atom_start_cs(struct r600_context *rctx);
653 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
654 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
655 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
656 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
657 void *r600_create_db_flush_dsa(struct r600_context *rctx);
658 void *r600_create_resolve_blend(struct r600_context *rctx);
659 void *r700_create_resolve_blend(struct r600_context *rctx);
660 void *r600_create_decompress_blend(struct r600_context *rctx);
661 bool r600_adjust_gprs(struct r600_context *rctx);
662 boolean r600_is_format_supported(struct pipe_screen *screen,
663 enum pipe_format format,
664 enum pipe_texture_target target,
665 unsigned sample_count,
666 unsigned usage);
667 void r600_update_db_shader_control(struct r600_context * rctx);
668
669 /* r600_hw_context.c */
670 void r600_context_gfx_flush(void *context, unsigned flags,
671 struct pipe_fence_handle **fence);
672 void r600_begin_new_cs(struct r600_context *ctx);
673 void r600_flush_emit(struct r600_context *ctx);
674 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
675 void r600_emit_pfp_sync_me(struct r600_context *rctx);
676 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
677 struct pipe_resource *dst, uint64_t dst_offset,
678 struct pipe_resource *src, uint64_t src_offset,
679 unsigned size);
680 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
681 struct pipe_resource *dst, uint64_t offset,
682 unsigned size, uint32_t clear_value,
683 enum r600_coherency coher);
684 void r600_dma_copy_buffer(struct r600_context *rctx,
685 struct pipe_resource *dst,
686 struct pipe_resource *src,
687 uint64_t dst_offset,
688 uint64_t src_offset,
689 uint64_t size);
690
691 /*
692 * evergreen_hw_context.c
693 */
694 void evergreen_dma_copy_buffer(struct r600_context *rctx,
695 struct pipe_resource *dst,
696 struct pipe_resource *src,
697 uint64_t dst_offset,
698 uint64_t src_offset,
699 uint64_t size);
700 void evergreen_setup_tess_constants(struct r600_context *rctx,
701 const struct pipe_draw_info *info,
702 unsigned *num_patches);
703 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
704 const struct pipe_draw_info *info,
705 unsigned num_patches);
706 void evergreen_set_ls_hs_config(struct r600_context *rctx,
707 struct radeon_winsys_cs *cs,
708 uint32_t ls_hs_config);
709 void evergreen_set_lds_alloc(struct r600_context *rctx,
710 struct radeon_winsys_cs *cs,
711 uint32_t lds_alloc);
712
713 /* r600_state_common.c */
714 void r600_init_common_state_functions(struct r600_context *rctx);
715 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
716 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
717 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
718 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
719 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
720 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
721 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
722 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
723 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
724 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
725 unsigned num_dw);
726 void r600_vertex_buffers_dirty(struct r600_context *rctx);
727 void r600_sampler_views_dirty(struct r600_context *rctx,
728 struct r600_samplerview_state *state);
729 void r600_sampler_states_dirty(struct r600_context *rctx,
730 struct r600_sampler_states *state);
731 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
732 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
733 uint32_t r600_translate_stencil_op(int s_op);
734 uint32_t r600_translate_fill(uint32_t func);
735 unsigned r600_tex_wrap(unsigned wrap);
736 unsigned r600_tex_mipfilter(unsigned filter);
737 unsigned r600_tex_compare(unsigned compare);
738 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
739 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
740 struct pipe_resource *texture,
741 const struct pipe_surface *templ,
742 unsigned width, unsigned height);
743 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
744 const unsigned char *swizzle_view,
745 boolean vtx);
746 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
747 const unsigned char *swizzle_view,
748 uint32_t *word4_p, uint32_t *yuv_format_p,
749 bool do_endian_swap);
750 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
751 bool do_endian_swap);
752 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
753
754 /* r600_uvd.c */
755 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
756 const struct pipe_video_codec *decoder);
757
758 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
759 const struct pipe_video_buffer *tmpl);
760
761 /*
762 * Helpers for building command buffers
763 */
764
765 #define PKT3_SET_CONFIG_REG 0x68
766 #define PKT3_SET_CONTEXT_REG 0x69
767 #define PKT3_SET_CTL_CONST 0x6F
768 #define PKT3_SET_LOOP_CONST 0x6C
769
770 #define R600_CONFIG_REG_OFFSET 0x08000
771 #define R600_CONTEXT_REG_OFFSET 0x28000
772 #define R600_CTL_CONST_OFFSET 0x3CFF0
773 #define R600_LOOP_CONST_OFFSET 0X0003E200
774 #define EG_LOOP_CONST_OFFSET 0x0003A200
775
776 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
777 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
778 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
779 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
780 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
781
782 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
783
784 /*Evergreen Compute packet3*/
785 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
786
787 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
788 {
789 cb->buf[cb->num_dw++] = value;
790 }
791
792 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
793 {
794 assert(cb->num_dw+num <= cb->max_num_dw);
795 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
796 cb->num_dw += num;
797 }
798
799 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
800 {
801 assert(reg < R600_CONTEXT_REG_OFFSET);
802 assert(cb->num_dw+2+num <= cb->max_num_dw);
803 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
804 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
805 }
806
807 /**
808 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
809 * shaders.
810 */
811 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
812 {
813 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
814 assert(cb->num_dw+2+num <= cb->max_num_dw);
815 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
816 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
817 }
818
819 /**
820 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
821 * shaders.
822 */
823 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
824 {
825 assert(reg >= R600_CTL_CONST_OFFSET);
826 assert(cb->num_dw+2+num <= cb->max_num_dw);
827 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
828 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
829 }
830
831 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
832 {
833 assert(reg >= R600_LOOP_CONST_OFFSET);
834 assert(cb->num_dw+2+num <= cb->max_num_dw);
835 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
836 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
837 }
838
839 /**
840 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
841 * shaders.
842 */
843 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
844 {
845 assert(reg >= EG_LOOP_CONST_OFFSET);
846 assert(cb->num_dw+2+num <= cb->max_num_dw);
847 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
848 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
849 }
850
851 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
852 {
853 r600_store_config_reg_seq(cb, reg, 1);
854 r600_store_value(cb, value);
855 }
856
857 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
858 {
859 r600_store_context_reg_seq(cb, reg, 1);
860 r600_store_value(cb, value);
861 }
862
863 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
864 {
865 r600_store_ctl_const_seq(cb, reg, 1);
866 r600_store_value(cb, value);
867 }
868
869 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
870 {
871 r600_store_loop_const_seq(cb, reg, 1);
872 r600_store_value(cb, value);
873 }
874
875 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
876 {
877 eg_store_loop_const_seq(cb, reg, 1);
878 r600_store_value(cb, value);
879 }
880
881 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
882 void r600_release_command_buffer(struct r600_command_buffer *cb);
883
884 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
885 {
886 radeon_set_context_reg_seq(cs, reg, num);
887 /* Set the compute bit on the packet header */
888 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
889 }
890
891 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
892 {
893 assert(reg >= R600_CTL_CONST_OFFSET);
894 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
895 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
896 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
897 }
898
899 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
900 {
901 radeon_compute_set_context_reg_seq(cs, reg, 1);
902 radeon_emit(cs, value);
903 }
904
905 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
906 {
907 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
908 radeon_compute_set_context_reg(cs, reg, value);
909 } else {
910 radeon_set_context_reg(cs, reg, value);
911 }
912 }
913
914 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
915 {
916 radeon_set_ctl_const_seq(cs, reg, 1);
917 radeon_emit(cs, value);
918 }
919
920 /*
921 * common helpers
922 */
923 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
924 {
925 return value * (1 << frac_bits);
926 }
927
928 /* 12.4 fixed-point */
929 static inline unsigned r600_pack_float_12p4(float x)
930 {
931 return x <= 0 ? 0 :
932 x >= 4096 ? 0xffff : x * 16;
933 }
934
935 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
936 {
937 switch (coher) {
938 default:
939 case R600_COHERENCY_NONE:
940 return 0;
941 case R600_COHERENCY_SHADER:
942 return R600_CONTEXT_INV_CONST_CACHE |
943 R600_CONTEXT_INV_VERTEX_CACHE |
944 R600_CONTEXT_INV_TEX_CACHE |
945 R600_CONTEXT_STREAMOUT_FLUSH;
946 case R600_COHERENCY_CB_META:
947 return R600_CONTEXT_FLUSH_AND_INV_CB |
948 R600_CONTEXT_FLUSH_AND_INV_CB_META;
949 }
950 }
951
952 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
953 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
954 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
955
956 unsigned r600_conv_prim_to_gs_out(unsigned mode);
957 #endif