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gallium/radeon: remove 'dirty' member from r600_atom
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 42
42
43 #define R600_MAX_VIEWPORTS 16
44
45 /* read caches */
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
59
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 47
63 #define R600_TRACE_CS_DWORDS 7
64
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 3
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
68
69 /* start driver buffers after user buffers */
70 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
72 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
73 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
74 * of 16 const buffers.
75 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
76 *
77 * In order to support d3d 11 mandated minimum of 15 user const buffers
78 * we'd have to squash all use cases into one driver buffer.
79 */
80 #define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
81
82 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
83
84 #ifdef PIPE_ARCH_BIG_ENDIAN
85 #define R600_BIG_ENDIAN 1
86 #else
87 #define R600_BIG_ENDIAN 0
88 #endif
89
90 struct r600_context;
91 struct r600_bytecode;
92 union r600_shader_key;
93
94 /* This is an atom containing GPU commands that never change.
95 * This is supposed to be copied directly into the CS. */
96 struct r600_command_buffer {
97 uint32_t *buf;
98 unsigned num_dw;
99 unsigned max_num_dw;
100 unsigned pkt_flags;
101 };
102
103 struct r600_db_state {
104 struct r600_atom atom;
105 struct r600_surface *rsurf;
106 };
107
108 struct r600_db_misc_state {
109 struct r600_atom atom;
110 bool occlusion_query_enabled;
111 bool flush_depthstencil_through_cb;
112 bool flush_depthstencil_in_place;
113 bool copy_depth, copy_stencil;
114 unsigned copy_sample;
115 unsigned log_samples;
116 unsigned db_shader_control;
117 bool htile_clear;
118 };
119
120 struct r600_cb_misc_state {
121 struct r600_atom atom;
122 unsigned cb_color_control; /* this comes from blend state */
123 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
124 unsigned nr_cbufs;
125 unsigned nr_ps_color_outputs;
126 bool multiwrite;
127 bool dual_src_blend;
128 };
129
130 struct r600_clip_misc_state {
131 struct r600_atom atom;
132 unsigned pa_cl_clip_cntl; /* from rasterizer */
133 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
134 unsigned clip_plane_enable; /* from rasterizer */
135 unsigned clip_dist_write; /* from vertex shader */
136 boolean clip_disable; /* from vertex shader */
137 };
138
139 struct r600_alphatest_state {
140 struct r600_atom atom;
141 unsigned sx_alpha_test_control; /* this comes from dsa state */
142 unsigned sx_alpha_ref; /* this comes from dsa state */
143 bool bypass;
144 bool cb0_export_16bpc; /* from set_framebuffer_state */
145 };
146
147 struct r600_vgt_state {
148 struct r600_atom atom;
149 uint32_t vgt_multi_prim_ib_reset_en;
150 uint32_t vgt_multi_prim_ib_reset_indx;
151 uint32_t vgt_indx_offset;
152 bool last_draw_was_indirect;
153 };
154
155 struct r600_blend_color {
156 struct r600_atom atom;
157 struct pipe_blend_color state;
158 };
159
160 struct r600_clip_state {
161 struct r600_atom atom;
162 struct pipe_clip_state state;
163 };
164
165 struct r600_cs_shader_state {
166 struct r600_atom atom;
167 unsigned kernel_index;
168 unsigned pc;
169 struct r600_pipe_compute *shader;
170 };
171
172 struct r600_framebuffer {
173 struct r600_atom atom;
174 struct pipe_framebuffer_state state;
175 unsigned compressed_cb_mask;
176 unsigned nr_samples;
177 bool export_16bpc;
178 bool cb0_is_integer;
179 bool is_msaa_resolve;
180 };
181
182 struct r600_sample_mask {
183 struct r600_atom atom;
184 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
185 };
186
187 struct r600_config_state {
188 struct r600_atom atom;
189 unsigned sq_gpr_resource_mgmt_1;
190 unsigned sq_gpr_resource_mgmt_2;
191 };
192
193 struct r600_stencil_ref
194 {
195 ubyte ref_value[2];
196 ubyte valuemask[2];
197 ubyte writemask[2];
198 };
199
200 struct r600_stencil_ref_state {
201 struct r600_atom atom;
202 struct r600_stencil_ref state;
203 struct pipe_stencil_ref pipe_state;
204 };
205
206 struct r600_viewport_state {
207 struct r600_atom atom;
208 struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
209 uint32_t dirty_mask;
210 };
211
212 struct r600_shader_stages_state {
213 struct r600_atom atom;
214 unsigned geom_enable;
215 };
216
217 struct r600_gs_rings_state {
218 struct r600_atom atom;
219 unsigned enable;
220 struct pipe_constant_buffer esgs_ring;
221 struct pipe_constant_buffer gsvs_ring;
222 };
223
224 /* This must start from 16. */
225 /* features */
226 #define DBG_LLVM (1 << 29)
227 #define DBG_NO_CP_DMA (1 << 30)
228 /* shader backend */
229 #define DBG_NO_SB (1 << 21)
230 #define DBG_SB_CS (1 << 22)
231 #define DBG_SB_DRY_RUN (1 << 23)
232 #define DBG_SB_STAT (1 << 24)
233 #define DBG_SB_DUMP (1 << 25)
234 #define DBG_SB_NO_FALLBACK (1 << 26)
235 #define DBG_SB_DISASM (1 << 27)
236 #define DBG_SB_SAFEMATH (1 << 28)
237
238 struct r600_screen {
239 struct r600_common_screen b;
240 bool has_msaa;
241 bool has_compressed_msaa_texturing;
242
243 /*for compute global memory binding, we allocate stuff here, instead of
244 * buffers.
245 * XXX: Not sure if this is the best place for global_pool. Also,
246 * it's not thread safe, so it won't work with multiple contexts. */
247 struct compute_memory_pool *global_pool;
248 };
249
250 struct r600_pipe_sampler_view {
251 struct pipe_sampler_view base;
252 struct list_head list;
253 struct r600_resource *tex_resource;
254 uint32_t tex_resource_words[8];
255 bool skip_mip_address_reloc;
256 };
257
258 struct r600_rasterizer_state {
259 struct r600_command_buffer buffer;
260 boolean flatshade;
261 boolean two_side;
262 unsigned sprite_coord_enable;
263 unsigned clip_plane_enable;
264 unsigned pa_sc_line_stipple;
265 unsigned pa_cl_clip_cntl;
266 unsigned pa_su_sc_mode_cntl;
267 float offset_units;
268 float offset_scale;
269 bool offset_enable;
270 bool scissor_enable;
271 bool multisample_enable;
272 };
273
274 struct r600_poly_offset_state {
275 struct r600_atom atom;
276 enum pipe_format zs_format;
277 float offset_units;
278 float offset_scale;
279 };
280
281 struct r600_blend_state {
282 struct r600_command_buffer buffer;
283 struct r600_command_buffer buffer_no_blend;
284 unsigned cb_target_mask;
285 unsigned cb_color_control;
286 unsigned cb_color_control_no_blend;
287 bool dual_src_blend;
288 bool alpha_to_one;
289 };
290
291 struct r600_dsa_state {
292 struct r600_command_buffer buffer;
293 unsigned alpha_ref;
294 ubyte valuemask[2];
295 ubyte writemask[2];
296 unsigned zwritemask;
297 unsigned sx_alpha_test_control;
298 };
299
300 struct r600_pipe_shader;
301
302 struct r600_pipe_shader_selector {
303 struct r600_pipe_shader *current;
304
305 struct tgsi_token *tokens;
306 struct pipe_stream_output_info so;
307 struct tgsi_shader_info info;
308
309 unsigned num_shaders;
310
311 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
312 unsigned type;
313
314 /* geometry shader properties */
315 unsigned gs_output_prim;
316 unsigned gs_max_out_vertices;
317 unsigned gs_num_invocations;
318
319 unsigned nr_ps_max_color_exports;
320 };
321
322 struct r600_pipe_sampler_state {
323 uint32_t tex_sampler_words[3];
324 union pipe_color_union border_color;
325 bool border_color_use;
326 bool seamless_cube_map;
327 };
328
329 /* needed for blitter save */
330 #define NUM_TEX_UNITS 16
331
332 struct r600_seamless_cube_map {
333 struct r600_atom atom;
334 bool enabled;
335 };
336
337 struct r600_samplerview_state {
338 struct r600_atom atom;
339 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
340 uint32_t enabled_mask;
341 uint32_t dirty_mask;
342 uint32_t compressed_depthtex_mask; /* which textures are depth */
343 uint32_t compressed_colortex_mask;
344 boolean dirty_buffer_constants;
345 };
346
347 struct r600_sampler_states {
348 struct r600_atom atom;
349 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
350 uint32_t enabled_mask;
351 uint32_t dirty_mask;
352 uint32_t has_bordercolor_mask; /* which states contain the border color */
353 };
354
355 struct r600_textures_info {
356 struct r600_samplerview_state views;
357 struct r600_sampler_states states;
358 bool is_array_sampler[NUM_TEX_UNITS];
359
360 /* cube array txq workaround */
361 uint32_t *txq_constants;
362 /* buffer related workarounds */
363 uint32_t *buffer_constants;
364 };
365
366 struct r600_constbuf_state
367 {
368 struct r600_atom atom;
369 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
370 uint32_t enabled_mask;
371 uint32_t dirty_mask;
372 };
373
374 struct r600_vertexbuf_state
375 {
376 struct r600_atom atom;
377 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
378 uint32_t enabled_mask; /* non-NULL buffers */
379 uint32_t dirty_mask;
380 };
381
382 /* CSO (constant state object, in other words, immutable state). */
383 struct r600_cso_state
384 {
385 struct r600_atom atom;
386 void *cso; /* e.g. r600_blend_state */
387 struct r600_command_buffer *cb;
388 };
389
390 struct r600_scissor_state
391 {
392 struct r600_atom atom;
393 struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
394 uint32_t dirty_mask;
395 bool enable; /* r6xx only */
396 };
397
398 struct r600_fetch_shader {
399 struct r600_resource *buffer;
400 unsigned offset;
401 };
402
403 struct r600_shader_state {
404 struct r600_atom atom;
405 struct r600_pipe_shader *shader;
406 };
407
408 struct r600_context {
409 struct r600_common_context b;
410 struct r600_screen *screen;
411 struct blitter_context *blitter;
412 struct u_suballocator *allocator_fetch_shader;
413
414 /* Hardware info. */
415 boolean has_vertex_cache;
416 boolean keep_tiling_flags;
417 unsigned default_ps_gprs, default_vs_gprs;
418 unsigned r6xx_num_clause_temp_gprs;
419
420 /* Miscellaneous state objects. */
421 void *custom_dsa_flush;
422 void *custom_blend_resolve;
423 void *custom_blend_decompress;
424 void *custom_blend_fastclear;
425 /* With rasterizer discard, there doesn't have to be a pixel shader.
426 * In that case, we bind this one: */
427 void *dummy_pixel_shader;
428 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
429 * bug where valid CMASK and FMASK are required to be present to avoid
430 * a hardlock in certain operations but aren't actually used
431 * for anything useful. */
432 struct r600_resource *dummy_fmask;
433 struct r600_resource *dummy_cmask;
434
435 /* State binding slots are here. */
436 struct r600_atom *atoms[R600_NUM_ATOMS];
437 /* Dirty atom bitmask for fast tests */
438 uint64_t dirty_atoms;
439 /* States for CS initialization. */
440 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
441 /** Compute specific registers initializations. The start_cs_cmd atom
442 * must be emitted before start_compute_cs_cmd. */
443 struct r600_command_buffer start_compute_cs_cmd;
444 /* Register states. */
445 struct r600_alphatest_state alphatest_state;
446 struct r600_cso_state blend_state;
447 struct r600_blend_color blend_color;
448 struct r600_cb_misc_state cb_misc_state;
449 struct r600_clip_misc_state clip_misc_state;
450 struct r600_clip_state clip_state;
451 struct r600_db_misc_state db_misc_state;
452 struct r600_db_state db_state;
453 struct r600_cso_state dsa_state;
454 struct r600_framebuffer framebuffer;
455 struct r600_poly_offset_state poly_offset_state;
456 struct r600_cso_state rasterizer_state;
457 struct r600_sample_mask sample_mask;
458 struct r600_scissor_state scissor;
459 struct r600_seamless_cube_map seamless_cube_map;
460 struct r600_config_state config_state;
461 struct r600_stencil_ref_state stencil_ref;
462 struct r600_vgt_state vgt_state;
463 struct r600_viewport_state viewport;
464 /* Shaders and shader resources. */
465 struct r600_cso_state vertex_fetch_shader;
466 struct r600_shader_state vertex_shader;
467 struct r600_shader_state pixel_shader;
468 struct r600_shader_state geometry_shader;
469 struct r600_shader_state export_shader;
470 struct r600_cs_shader_state cs_shader_state;
471 struct r600_shader_stages_state shader_stages;
472 struct r600_gs_rings_state gs_rings;
473 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
474 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
475 /** Vertex buffers for fetch shaders */
476 struct r600_vertexbuf_state vertex_buffer_state;
477 /** Vertex buffers for compute shaders */
478 struct r600_vertexbuf_state cs_vertex_buffer_state;
479
480 /* Additional context states. */
481 unsigned compute_cb_target_mask;
482 struct r600_pipe_shader_selector *ps_shader;
483 struct r600_pipe_shader_selector *vs_shader;
484 struct r600_pipe_shader_selector *gs_shader;
485 struct r600_rasterizer_state *rasterizer;
486 bool alpha_to_one;
487 bool force_blend_disable;
488 boolean dual_src_blend;
489 unsigned zwritemask;
490 int ps_iter_samples;
491
492 /* Index buffer. */
493 struct pipe_index_buffer index_buffer;
494
495 /* Last draw state (-1 = unset). */
496 int last_primitive_type; /* Last primitive type used in draw_vbo. */
497 int last_start_instance;
498
499 void *sb_context;
500 struct r600_isa *isa;
501 };
502
503 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
504 struct r600_command_buffer *cb)
505 {
506 assert(cs->cdw + cb->num_dw <= cs->max_dw);
507 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
508 cs->cdw += cb->num_dw;
509 }
510
511 static inline void r600_set_atom_dirty(struct r600_context *rctx,
512 struct r600_atom *atom,
513 bool dirty)
514 {
515 uint64_t mask;
516
517 assert(atom->id != 0);
518 assert(atom->id < sizeof(mask) * 8);
519 mask = 1ull << atom->id;
520 if (dirty)
521 rctx->dirty_atoms |= mask;
522 else
523 rctx->dirty_atoms &= ~mask;
524 }
525
526 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
527 struct r600_atom *atom)
528 {
529 r600_set_atom_dirty(rctx, atom, true);
530 }
531
532 void r600_trace_emit(struct r600_context *rctx);
533
534 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
535 {
536 atom->emit(&rctx->b, atom);
537 r600_set_atom_dirty(rctx, atom, false);
538 if (rctx->screen->b.trace_bo) {
539 r600_trace_emit(rctx);
540 }
541 }
542
543 static inline void r600_set_cso_state(struct r600_context *rctx,
544 struct r600_cso_state *state, void *cso)
545 {
546 state->cso = cso;
547 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
548 }
549
550 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
551 struct r600_cso_state *state, void *cso,
552 struct r600_command_buffer *cb)
553 {
554 state->cb = cb;
555 state->atom.num_dw = cb ? cb->num_dw : 0;
556 r600_set_cso_state(rctx, state, cso);
557 }
558
559 /* compute_memory_pool.c */
560 struct compute_memory_pool;
561 void compute_memory_pool_delete(struct compute_memory_pool* pool);
562 struct compute_memory_pool* compute_memory_pool_new(
563 struct r600_screen *rscreen);
564
565 /* evergreen_state.c */
566 struct pipe_sampler_view *
567 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
568 struct pipe_resource *texture,
569 const struct pipe_sampler_view *state,
570 unsigned width0, unsigned height0,
571 unsigned force_level);
572 void evergreen_init_common_regs(struct r600_command_buffer *cb,
573 enum chip_class ctx_chip_class,
574 enum radeon_family ctx_family,
575 int ctx_drm_minor);
576 void cayman_init_common_regs(struct r600_command_buffer *cb,
577 enum chip_class ctx_chip_class,
578 enum radeon_family ctx_family,
579 int ctx_drm_minor);
580
581 void evergreen_init_state_functions(struct r600_context *rctx);
582 void evergreen_init_atom_start_cs(struct r600_context *rctx);
583 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
584 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
585 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
586 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
587 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
588 void *evergreen_create_resolve_blend(struct r600_context *rctx);
589 void *evergreen_create_decompress_blend(struct r600_context *rctx);
590 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
591 boolean evergreen_is_format_supported(struct pipe_screen *screen,
592 enum pipe_format format,
593 enum pipe_texture_target target,
594 unsigned sample_count,
595 unsigned usage);
596 void evergreen_init_color_surface(struct r600_context *rctx,
597 struct r600_surface *surf);
598 void evergreen_init_color_surface_rat(struct r600_context *rctx,
599 struct r600_surface *surf);
600 void evergreen_update_db_shader_control(struct r600_context * rctx);
601
602 /* r600_blit.c */
603 void r600_init_blit_functions(struct r600_context *rctx);
604 void r600_decompress_depth_textures(struct r600_context *rctx,
605 struct r600_samplerview_state *textures);
606 void r600_decompress_color_textures(struct r600_context *rctx,
607 struct r600_samplerview_state *textures);
608 void r600_resource_copy_region(struct pipe_context *ctx,
609 struct pipe_resource *dst,
610 unsigned dst_level,
611 unsigned dstx, unsigned dsty, unsigned dstz,
612 struct pipe_resource *src,
613 unsigned src_level,
614 const struct pipe_box *src_box);
615
616 /* r600_shader.c */
617 int r600_pipe_shader_create(struct pipe_context *ctx,
618 struct r600_pipe_shader *shader,
619 union r600_shader_key key);
620
621 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
622
623 /* r600_state.c */
624 struct pipe_sampler_view *
625 r600_create_sampler_view_custom(struct pipe_context *ctx,
626 struct pipe_resource *texture,
627 const struct pipe_sampler_view *state,
628 unsigned width_first_level, unsigned height_first_level);
629 void r600_init_state_functions(struct r600_context *rctx);
630 void r600_init_atom_start_cs(struct r600_context *rctx);
631 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
632 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
633 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
634 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
635 void *r600_create_db_flush_dsa(struct r600_context *rctx);
636 void *r600_create_resolve_blend(struct r600_context *rctx);
637 void *r700_create_resolve_blend(struct r600_context *rctx);
638 void *r600_create_decompress_blend(struct r600_context *rctx);
639 bool r600_adjust_gprs(struct r600_context *rctx);
640 boolean r600_is_format_supported(struct pipe_screen *screen,
641 enum pipe_format format,
642 enum pipe_texture_target target,
643 unsigned sample_count,
644 unsigned usage);
645 void r600_update_db_shader_control(struct r600_context * rctx);
646
647 /* r600_hw_context.c */
648 void r600_context_gfx_flush(void *context, unsigned flags,
649 struct pipe_fence_handle **fence);
650 void r600_begin_new_cs(struct r600_context *ctx);
651 void r600_flush_emit(struct r600_context *ctx);
652 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
653 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
654 struct pipe_resource *dst, uint64_t dst_offset,
655 struct pipe_resource *src, uint64_t src_offset,
656 unsigned size);
657 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
658 struct pipe_resource *dst, uint64_t offset,
659 unsigned size, uint32_t clear_value);
660 void r600_dma_copy_buffer(struct r600_context *rctx,
661 struct pipe_resource *dst,
662 struct pipe_resource *src,
663 uint64_t dst_offset,
664 uint64_t src_offset,
665 uint64_t size);
666
667 /*
668 * evergreen_hw_context.c
669 */
670 void evergreen_dma_copy_buffer(struct r600_context *rctx,
671 struct pipe_resource *dst,
672 struct pipe_resource *src,
673 uint64_t dst_offset,
674 uint64_t src_offset,
675 uint64_t size);
676
677 /* r600_state_common.c */
678 void r600_init_common_state_functions(struct r600_context *rctx);
679 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
680 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
681 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
682 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
683 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
684 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
685 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
686 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
687 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
688 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
689 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
690 unsigned num_dw);
691 void r600_vertex_buffers_dirty(struct r600_context *rctx);
692 void r600_sampler_views_dirty(struct r600_context *rctx,
693 struct r600_samplerview_state *state);
694 void r600_sampler_states_dirty(struct r600_context *rctx,
695 struct r600_sampler_states *state);
696 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
697 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
698 uint32_t r600_translate_stencil_op(int s_op);
699 uint32_t r600_translate_fill(uint32_t func);
700 unsigned r600_tex_wrap(unsigned wrap);
701 unsigned r600_tex_filter(unsigned filter);
702 unsigned r600_tex_mipfilter(unsigned filter);
703 unsigned r600_tex_compare(unsigned compare);
704 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
705 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
706 struct pipe_resource *texture,
707 const struct pipe_surface *templ,
708 unsigned width, unsigned height);
709 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
710 const unsigned char *swizzle_view,
711 boolean vtx);
712 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
713 const unsigned char *swizzle_view,
714 uint32_t *word4_p, uint32_t *yuv_format_p);
715 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
716 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
717
718 /* r600_uvd.c */
719 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
720 const struct pipe_video_codec *decoder);
721
722 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
723 const struct pipe_video_buffer *tmpl);
724
725 /*
726 * Helpers for building command buffers
727 */
728
729 #define PKT3_SET_CONFIG_REG 0x68
730 #define PKT3_SET_CONTEXT_REG 0x69
731 #define PKT3_SET_CTL_CONST 0x6F
732 #define PKT3_SET_LOOP_CONST 0x6C
733
734 #define R600_CONFIG_REG_OFFSET 0x08000
735 #define R600_CONTEXT_REG_OFFSET 0x28000
736 #define R600_CTL_CONST_OFFSET 0x3CFF0
737 #define R600_LOOP_CONST_OFFSET 0X0003E200
738 #define EG_LOOP_CONST_OFFSET 0x0003A200
739
740 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
741 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
742 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
743 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
744 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
745
746 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
747
748 /*Evergreen Compute packet3*/
749 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
750
751 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
752 {
753 cb->buf[cb->num_dw++] = value;
754 }
755
756 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
757 {
758 assert(cb->num_dw+num <= cb->max_num_dw);
759 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
760 cb->num_dw += num;
761 }
762
763 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
764 {
765 assert(reg < R600_CONTEXT_REG_OFFSET);
766 assert(cb->num_dw+2+num <= cb->max_num_dw);
767 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
768 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
769 }
770
771 /**
772 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
773 * shaders.
774 */
775 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
776 {
777 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
778 assert(cb->num_dw+2+num <= cb->max_num_dw);
779 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
780 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
781 }
782
783 /**
784 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
785 * shaders.
786 */
787 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
788 {
789 assert(reg >= R600_CTL_CONST_OFFSET);
790 assert(cb->num_dw+2+num <= cb->max_num_dw);
791 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
792 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
793 }
794
795 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
796 {
797 assert(reg >= R600_LOOP_CONST_OFFSET);
798 assert(cb->num_dw+2+num <= cb->max_num_dw);
799 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
800 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
801 }
802
803 /**
804 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
805 * shaders.
806 */
807 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
808 {
809 assert(reg >= EG_LOOP_CONST_OFFSET);
810 assert(cb->num_dw+2+num <= cb->max_num_dw);
811 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
812 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
813 }
814
815 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
816 {
817 r600_store_config_reg_seq(cb, reg, 1);
818 r600_store_value(cb, value);
819 }
820
821 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
822 {
823 r600_store_context_reg_seq(cb, reg, 1);
824 r600_store_value(cb, value);
825 }
826
827 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
828 {
829 r600_store_ctl_const_seq(cb, reg, 1);
830 r600_store_value(cb, value);
831 }
832
833 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
834 {
835 r600_store_loop_const_seq(cb, reg, 1);
836 r600_store_value(cb, value);
837 }
838
839 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
840 {
841 eg_store_loop_const_seq(cb, reg, 1);
842 r600_store_value(cb, value);
843 }
844
845 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
846 void r600_release_command_buffer(struct r600_command_buffer *cb);
847
848 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
849 {
850 radeon_set_context_reg_seq(cs, reg, num);
851 /* Set the compute bit on the packet header */
852 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
853 }
854
855 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
856 {
857 assert(reg >= R600_CTL_CONST_OFFSET);
858 assert(cs->cdw+2+num <= cs->max_dw);
859 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
860 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
861 }
862
863 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
864 {
865 radeon_compute_set_context_reg_seq(cs, reg, 1);
866 radeon_emit(cs, value);
867 }
868
869 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
870 {
871 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
872 radeon_compute_set_context_reg(cs, reg, value);
873 } else {
874 radeon_set_context_reg(cs, reg, value);
875 }
876 }
877
878 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
879 {
880 radeon_set_ctl_const_seq(cs, reg, 1);
881 radeon_emit(cs, value);
882 }
883
884 /*
885 * common helpers
886 */
887 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
888 {
889 return value * (1 << frac_bits);
890 }
891 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
892
893 /* 12.4 fixed-point */
894 static inline unsigned r600_pack_float_12p4(float x)
895 {
896 return x <= 0 ? 0 :
897 x >= 4096 ? 0xffff : x * 16;
898 }
899
900 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
901 static inline bool r600_can_read_depth(struct r600_texture *rtex)
902 {
903 return rtex->resource.b.b.nr_samples <= 1 &&
904 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
905 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
906 }
907
908 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
909 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
910 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
911
912 unsigned r600_conv_prim_to_gs_out(unsigned mode);
913 #endif