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r600g: extract a code into a r600_emit_rasterizer_prim_state()
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 52
42
43 /* read caches */
44 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
45 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
46 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
47 /* read-write caches */
48 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
49 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
51 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
52 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
53 /* engine synchronization */
54 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
55 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
56 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
57
58 /* the number of CS dwords for flushing and drawing */
59 #define R600_MAX_FLUSH_CS_DWORDS 18
60 #define R600_MAX_DRAW_CS_DWORDS 58
61 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
62
63 #define R600_MAX_USER_CONST_BUFFERS 13
64 #define R600_MAX_DRIVER_CONST_BUFFERS 3
65 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
66
67 /* start driver buffers after user buffers */
68 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
69 #define R600_UCP_SIZE (4*4*8)
70 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
71
72 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
73 /*
74 * Note GS doesn't use a constant buffer binding, just a resource index,
75 * so it's fine to have it exist at index 16.
76 */
77 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
78 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
79 * of 16 const buffers.
80 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
81 *
82 * In order to support d3d 11 mandated minimum of 15 user const buffers
83 * we'd have to squash all use cases into one driver buffer.
84 */
85 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
86
87 /* HW stages */
88 #define R600_HW_STAGE_PS 0
89 #define R600_HW_STAGE_VS 1
90 #define R600_HW_STAGE_GS 2
91 #define R600_HW_STAGE_ES 3
92 #define EG_HW_STAGE_LS 4
93 #define EG_HW_STAGE_HS 5
94
95 #define R600_NUM_HW_STAGES 4
96 #define EG_NUM_HW_STAGES 6
97
98 struct r600_context;
99 struct r600_bytecode;
100 union r600_shader_key;
101
102 /* This is an atom containing GPU commands that never change.
103 * This is supposed to be copied directly into the CS. */
104 struct r600_command_buffer {
105 uint32_t *buf;
106 unsigned num_dw;
107 unsigned max_num_dw;
108 unsigned pkt_flags;
109 };
110
111 struct r600_db_state {
112 struct r600_atom atom;
113 struct r600_surface *rsurf;
114 };
115
116 struct r600_db_misc_state {
117 struct r600_atom atom;
118 bool occlusion_queries_disabled;
119 bool flush_depthstencil_through_cb;
120 bool flush_depth_inplace;
121 bool flush_stencil_inplace;
122 bool copy_depth, copy_stencil;
123 unsigned copy_sample;
124 unsigned log_samples;
125 unsigned db_shader_control;
126 bool htile_clear;
127 uint8_t ps_conservative_z;
128 };
129
130 struct r600_cb_misc_state {
131 struct r600_atom atom;
132 unsigned cb_color_control; /* this comes from blend state */
133 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
134 unsigned nr_cbufs;
135 unsigned nr_ps_color_outputs;
136 bool multiwrite;
137 bool dual_src_blend;
138 };
139
140 struct r600_clip_misc_state {
141 struct r600_atom atom;
142 unsigned pa_cl_clip_cntl; /* from rasterizer */
143 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
144 unsigned clip_plane_enable; /* from rasterizer */
145 unsigned clip_dist_write; /* from vertex shader */
146 boolean clip_disable; /* from vertex shader */
147 boolean vs_out_viewport; /* from vertex shader */
148 };
149
150 struct r600_alphatest_state {
151 struct r600_atom atom;
152 unsigned sx_alpha_test_control; /* this comes from dsa state */
153 unsigned sx_alpha_ref; /* this comes from dsa state */
154 bool bypass;
155 bool cb0_export_16bpc; /* from set_framebuffer_state */
156 };
157
158 struct r600_vgt_state {
159 struct r600_atom atom;
160 uint32_t vgt_multi_prim_ib_reset_en;
161 uint32_t vgt_multi_prim_ib_reset_indx;
162 uint32_t vgt_indx_offset;
163 bool last_draw_was_indirect;
164 };
165
166 struct r600_blend_color {
167 struct r600_atom atom;
168 struct pipe_blend_color state;
169 };
170
171 struct r600_clip_state {
172 struct r600_atom atom;
173 struct pipe_clip_state state;
174 };
175
176 struct r600_cs_shader_state {
177 struct r600_atom atom;
178 unsigned kernel_index;
179 unsigned pc;
180 struct r600_pipe_compute *shader;
181 };
182
183 struct r600_framebuffer {
184 struct r600_atom atom;
185 struct pipe_framebuffer_state state;
186 unsigned compressed_cb_mask;
187 unsigned nr_samples;
188 bool export_16bpc;
189 bool cb0_is_integer;
190 bool is_msaa_resolve;
191 bool dual_src_blend;
192 };
193
194 struct r600_sample_mask {
195 struct r600_atom atom;
196 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
197 };
198
199 struct r600_config_state {
200 struct r600_atom atom;
201 unsigned sq_gpr_resource_mgmt_1;
202 unsigned sq_gpr_resource_mgmt_2;
203 unsigned sq_gpr_resource_mgmt_3;
204 bool dyn_gpr_enabled;
205 };
206
207 struct r600_stencil_ref
208 {
209 ubyte ref_value[2];
210 ubyte valuemask[2];
211 ubyte writemask[2];
212 };
213
214 struct r600_stencil_ref_state {
215 struct r600_atom atom;
216 struct r600_stencil_ref state;
217 struct pipe_stencil_ref pipe_state;
218 };
219
220 struct r600_shader_stages_state {
221 struct r600_atom atom;
222 unsigned geom_enable;
223 };
224
225 struct r600_gs_rings_state {
226 struct r600_atom atom;
227 unsigned enable;
228 struct pipe_constant_buffer esgs_ring;
229 struct pipe_constant_buffer gsvs_ring;
230 };
231
232 /* This must start from 16. */
233 /* features */
234 #define DBG_NO_CP_DMA (1 << 30)
235 /* shader backend */
236 #define DBG_NO_SB (1 << 21)
237 #define DBG_SB_CS (1 << 22)
238 #define DBG_SB_DRY_RUN (1 << 23)
239 #define DBG_SB_STAT (1 << 24)
240 #define DBG_SB_DUMP (1 << 25)
241 #define DBG_SB_NO_FALLBACK (1 << 26)
242 #define DBG_SB_DISASM (1 << 27)
243 #define DBG_SB_SAFEMATH (1 << 28)
244
245 struct r600_screen {
246 struct r600_common_screen b;
247 bool has_msaa;
248 bool has_compressed_msaa_texturing;
249
250 /*for compute global memory binding, we allocate stuff here, instead of
251 * buffers.
252 * XXX: Not sure if this is the best place for global_pool. Also,
253 * it's not thread safe, so it won't work with multiple contexts. */
254 struct compute_memory_pool *global_pool;
255 };
256
257 struct r600_pipe_sampler_view {
258 struct pipe_sampler_view base;
259 struct list_head list;
260 struct r600_resource *tex_resource;
261 uint32_t tex_resource_words[8];
262 bool skip_mip_address_reloc;
263 bool is_stencil_sampler;
264 };
265
266 struct r600_rasterizer_state {
267 struct r600_command_buffer buffer;
268 boolean flatshade;
269 boolean two_side;
270 unsigned sprite_coord_enable;
271 unsigned clip_plane_enable;
272 unsigned pa_sc_line_stipple;
273 unsigned pa_cl_clip_cntl;
274 unsigned pa_su_sc_mode_cntl;
275 float offset_units;
276 float offset_scale;
277 bool offset_enable;
278 bool offset_units_unscaled;
279 bool scissor_enable;
280 bool multisample_enable;
281 bool clip_halfz;
282 };
283
284 struct r600_poly_offset_state {
285 struct r600_atom atom;
286 enum pipe_format zs_format;
287 float offset_units;
288 float offset_scale;
289 bool offset_units_unscaled;
290 };
291
292 struct r600_blend_state {
293 struct r600_command_buffer buffer;
294 struct r600_command_buffer buffer_no_blend;
295 unsigned cb_target_mask;
296 unsigned cb_color_control;
297 unsigned cb_color_control_no_blend;
298 bool dual_src_blend;
299 bool alpha_to_one;
300 };
301
302 struct r600_dsa_state {
303 struct r600_command_buffer buffer;
304 unsigned alpha_ref;
305 ubyte valuemask[2];
306 ubyte writemask[2];
307 unsigned zwritemask;
308 unsigned sx_alpha_test_control;
309 };
310
311 struct r600_pipe_shader;
312
313 struct r600_pipe_shader_selector {
314 struct r600_pipe_shader *current;
315
316 struct tgsi_token *tokens;
317 struct pipe_stream_output_info so;
318 struct tgsi_shader_info info;
319
320 unsigned num_shaders;
321
322 enum pipe_shader_type type;
323
324 /* geometry shader properties */
325 enum pipe_prim_type gs_output_prim;
326 unsigned gs_max_out_vertices;
327 unsigned gs_num_invocations;
328
329 /* TCS/VS */
330 uint64_t lds_patch_outputs_written_mask;
331 uint64_t lds_outputs_written_mask;
332 unsigned nr_ps_max_color_exports;
333 };
334
335 struct r600_pipe_sampler_state {
336 uint32_t tex_sampler_words[3];
337 union pipe_color_union border_color;
338 bool border_color_use;
339 bool seamless_cube_map;
340 };
341
342 /* needed for blitter save */
343 #define NUM_TEX_UNITS 16
344
345 struct r600_seamless_cube_map {
346 struct r600_atom atom;
347 bool enabled;
348 };
349
350 struct r600_samplerview_state {
351 struct r600_atom atom;
352 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
353 uint32_t enabled_mask;
354 uint32_t dirty_mask;
355 uint32_t compressed_depthtex_mask; /* which textures are depth */
356 uint32_t compressed_colortex_mask;
357 boolean dirty_buffer_constants;
358 };
359
360 struct r600_sampler_states {
361 struct r600_atom atom;
362 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
363 uint32_t enabled_mask;
364 uint32_t dirty_mask;
365 uint32_t has_bordercolor_mask; /* which states contain the border color */
366 };
367
368 struct r600_textures_info {
369 struct r600_samplerview_state views;
370 struct r600_sampler_states states;
371 bool is_array_sampler[NUM_TEX_UNITS];
372 };
373
374 struct r600_shader_driver_constants_info {
375 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
376 uint32_t *constants;
377 uint32_t alloc_size;
378 bool vs_ucp_dirty;
379 bool texture_const_dirty;
380 bool ps_sample_pos_dirty;
381 };
382
383 struct r600_constbuf_state
384 {
385 struct r600_atom atom;
386 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
387 uint32_t enabled_mask;
388 uint32_t dirty_mask;
389 };
390
391 struct r600_vertexbuf_state
392 {
393 struct r600_atom atom;
394 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
395 uint32_t enabled_mask; /* non-NULL buffers */
396 uint32_t dirty_mask;
397 };
398
399 /* CSO (constant state object, in other words, immutable state). */
400 struct r600_cso_state
401 {
402 struct r600_atom atom;
403 void *cso; /* e.g. r600_blend_state */
404 struct r600_command_buffer *cb;
405 };
406
407 struct r600_fetch_shader {
408 struct r600_resource *buffer;
409 unsigned offset;
410 };
411
412 struct r600_shader_state {
413 struct r600_atom atom;
414 struct r600_pipe_shader *shader;
415 };
416
417 struct r600_context {
418 struct r600_common_context b;
419 struct r600_screen *screen;
420 struct blitter_context *blitter;
421 struct u_suballocator *allocator_fetch_shader;
422
423 /* Hardware info. */
424 boolean has_vertex_cache;
425 unsigned default_gprs[EG_NUM_HW_STAGES];
426 unsigned current_gprs[EG_NUM_HW_STAGES];
427 unsigned r6xx_num_clause_temp_gprs;
428
429 /* Miscellaneous state objects. */
430 void *custom_dsa_flush;
431 void *custom_blend_resolve;
432 void *custom_blend_decompress;
433 void *custom_blend_fastclear;
434 /* With rasterizer discard, there doesn't have to be a pixel shader.
435 * In that case, we bind this one: */
436 void *dummy_pixel_shader;
437 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
438 * bug where valid CMASK and FMASK are required to be present to avoid
439 * a hardlock in certain operations but aren't actually used
440 * for anything useful. */
441 struct r600_resource *dummy_fmask;
442 struct r600_resource *dummy_cmask;
443
444 /* State binding slots are here. */
445 struct r600_atom *atoms[R600_NUM_ATOMS];
446 /* Dirty atom bitmask for fast tests */
447 uint64_t dirty_atoms;
448 /* States for CS initialization. */
449 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
450 /** Compute specific registers initializations. The start_cs_cmd atom
451 * must be emitted before start_compute_cs_cmd. */
452 struct r600_command_buffer start_compute_cs_cmd;
453 /* Register states. */
454 struct r600_alphatest_state alphatest_state;
455 struct r600_cso_state blend_state;
456 struct r600_blend_color blend_color;
457 struct r600_cb_misc_state cb_misc_state;
458 struct r600_clip_misc_state clip_misc_state;
459 struct r600_clip_state clip_state;
460 struct r600_db_misc_state db_misc_state;
461 struct r600_db_state db_state;
462 struct r600_cso_state dsa_state;
463 struct r600_framebuffer framebuffer;
464 struct r600_poly_offset_state poly_offset_state;
465 struct r600_cso_state rasterizer_state;
466 struct r600_sample_mask sample_mask;
467 struct r600_seamless_cube_map seamless_cube_map;
468 struct r600_config_state config_state;
469 struct r600_stencil_ref_state stencil_ref;
470 struct r600_vgt_state vgt_state;
471 /* Shaders and shader resources. */
472 struct r600_cso_state vertex_fetch_shader;
473 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
474 struct r600_cs_shader_state cs_shader_state;
475 struct r600_shader_stages_state shader_stages;
476 struct r600_gs_rings_state gs_rings;
477 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
478 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
479
480 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
481
482 /** Vertex buffers for fetch shaders */
483 struct r600_vertexbuf_state vertex_buffer_state;
484 /** Vertex buffers for compute shaders */
485 struct r600_vertexbuf_state cs_vertex_buffer_state;
486
487 /* Additional context states. */
488 unsigned compute_cb_target_mask;
489 struct r600_pipe_shader_selector *ps_shader;
490 struct r600_pipe_shader_selector *vs_shader;
491 struct r600_pipe_shader_selector *gs_shader;
492
493 struct r600_pipe_shader_selector *tcs_shader;
494 struct r600_pipe_shader_selector *tes_shader;
495
496 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
497
498 struct r600_rasterizer_state *rasterizer;
499 bool alpha_to_one;
500 bool force_blend_disable;
501 boolean dual_src_blend;
502 unsigned zwritemask;
503 int ps_iter_samples;
504
505 /* The list of all texture buffer objects in this context.
506 * This list is walked when a buffer is invalidated/reallocated and
507 * the GPU addresses are updated. */
508 struct list_head texture_buffers;
509
510 /* Index buffer. */
511 struct pipe_index_buffer index_buffer;
512
513 /* Last draw state (-1 = unset). */
514 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
515 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
516 enum pipe_prim_type last_rast_prim;
517 unsigned last_start_instance;
518
519 void *sb_context;
520 struct r600_isa *isa;
521 float sample_positions[4 * 16];
522 float tess_state[8];
523 bool tess_state_dirty;
524 struct r600_pipe_shader_selector *last_ls;
525 struct r600_pipe_shader_selector *last_tcs;
526 unsigned last_num_tcs_input_cp;
527 unsigned lds_alloc;
528 };
529
530 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
531 struct r600_command_buffer *cb)
532 {
533 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
534 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
535 cs->current.cdw += cb->num_dw;
536 }
537
538 static inline void r600_set_atom_dirty(struct r600_context *rctx,
539 struct r600_atom *atom,
540 bool dirty)
541 {
542 uint64_t mask;
543
544 assert(atom->id != 0);
545 assert(atom->id < sizeof(mask) * 8);
546 mask = 1ull << atom->id;
547 if (dirty)
548 rctx->dirty_atoms |= mask;
549 else
550 rctx->dirty_atoms &= ~mask;
551 }
552
553 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
554 struct r600_atom *atom)
555 {
556 r600_set_atom_dirty(rctx, atom, true);
557 }
558
559 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
560 {
561 atom->emit(&rctx->b, atom);
562 r600_set_atom_dirty(rctx, atom, false);
563 }
564
565 static inline void r600_set_cso_state(struct r600_context *rctx,
566 struct r600_cso_state *state, void *cso)
567 {
568 state->cso = cso;
569 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
570 }
571
572 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
573 struct r600_cso_state *state, void *cso,
574 struct r600_command_buffer *cb)
575 {
576 state->cb = cb;
577 state->atom.num_dw = cb ? cb->num_dw : 0;
578 r600_set_cso_state(rctx, state, cso);
579 }
580
581 /* compute_memory_pool.c */
582 struct compute_memory_pool;
583 void compute_memory_pool_delete(struct compute_memory_pool* pool);
584 struct compute_memory_pool* compute_memory_pool_new(
585 struct r600_screen *rscreen);
586
587 /* evergreen_state.c */
588 struct pipe_sampler_view *
589 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
590 struct pipe_resource *texture,
591 const struct pipe_sampler_view *state,
592 unsigned width0, unsigned height0,
593 unsigned force_level);
594 void evergreen_init_common_regs(struct r600_context *ctx,
595 struct r600_command_buffer *cb,
596 enum chip_class ctx_chip_class,
597 enum radeon_family ctx_family,
598 int ctx_drm_minor);
599 void cayman_init_common_regs(struct r600_command_buffer *cb,
600 enum chip_class ctx_chip_class,
601 enum radeon_family ctx_family,
602 int ctx_drm_minor);
603
604 void evergreen_init_state_functions(struct r600_context *rctx);
605 void evergreen_init_atom_start_cs(struct r600_context *rctx);
606 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
607 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
608 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
609 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
610 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
611 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
612 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
613 void *evergreen_create_resolve_blend(struct r600_context *rctx);
614 void *evergreen_create_decompress_blend(struct r600_context *rctx);
615 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
616 boolean evergreen_is_format_supported(struct pipe_screen *screen,
617 enum pipe_format format,
618 enum pipe_texture_target target,
619 unsigned sample_count,
620 unsigned usage);
621 void evergreen_init_color_surface(struct r600_context *rctx,
622 struct r600_surface *surf);
623 void evergreen_init_color_surface_rat(struct r600_context *rctx,
624 struct r600_surface *surf);
625 void evergreen_update_db_shader_control(struct r600_context * rctx);
626 bool evergreen_adjust_gprs(struct r600_context *rctx);
627 /* r600_blit.c */
628 void r600_init_blit_functions(struct r600_context *rctx);
629 void r600_decompress_depth_textures(struct r600_context *rctx,
630 struct r600_samplerview_state *textures);
631 void r600_decompress_color_textures(struct r600_context *rctx,
632 struct r600_samplerview_state *textures);
633 void r600_resource_copy_region(struct pipe_context *ctx,
634 struct pipe_resource *dst,
635 unsigned dst_level,
636 unsigned dstx, unsigned dsty, unsigned dstz,
637 struct pipe_resource *src,
638 unsigned src_level,
639 const struct pipe_box *src_box);
640
641 /* r600_shader.c */
642 int r600_pipe_shader_create(struct pipe_context *ctx,
643 struct r600_pipe_shader *shader,
644 union r600_shader_key key);
645
646 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
647
648 /* r600_state.c */
649 struct pipe_sampler_view *
650 r600_create_sampler_view_custom(struct pipe_context *ctx,
651 struct pipe_resource *texture,
652 const struct pipe_sampler_view *state,
653 unsigned width_first_level, unsigned height_first_level);
654 void r600_init_state_functions(struct r600_context *rctx);
655 void r600_init_atom_start_cs(struct r600_context *rctx);
656 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
657 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
658 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
659 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
660 void *r600_create_db_flush_dsa(struct r600_context *rctx);
661 void *r600_create_resolve_blend(struct r600_context *rctx);
662 void *r700_create_resolve_blend(struct r600_context *rctx);
663 void *r600_create_decompress_blend(struct r600_context *rctx);
664 bool r600_adjust_gprs(struct r600_context *rctx);
665 boolean r600_is_format_supported(struct pipe_screen *screen,
666 enum pipe_format format,
667 enum pipe_texture_target target,
668 unsigned sample_count,
669 unsigned usage);
670 void r600_update_db_shader_control(struct r600_context * rctx);
671
672 /* r600_hw_context.c */
673 void r600_context_gfx_flush(void *context, unsigned flags,
674 struct pipe_fence_handle **fence);
675 void r600_begin_new_cs(struct r600_context *ctx);
676 void r600_flush_emit(struct r600_context *ctx);
677 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
678 void r600_emit_pfp_sync_me(struct r600_context *rctx);
679 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
680 struct pipe_resource *dst, uint64_t dst_offset,
681 struct pipe_resource *src, uint64_t src_offset,
682 unsigned size);
683 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
684 struct pipe_resource *dst, uint64_t offset,
685 unsigned size, uint32_t clear_value,
686 enum r600_coherency coher);
687 void r600_dma_copy_buffer(struct r600_context *rctx,
688 struct pipe_resource *dst,
689 struct pipe_resource *src,
690 uint64_t dst_offset,
691 uint64_t src_offset,
692 uint64_t size);
693
694 /*
695 * evergreen_hw_context.c
696 */
697 void evergreen_dma_copy_buffer(struct r600_context *rctx,
698 struct pipe_resource *dst,
699 struct pipe_resource *src,
700 uint64_t dst_offset,
701 uint64_t src_offset,
702 uint64_t size);
703 void evergreen_setup_tess_constants(struct r600_context *rctx,
704 const struct pipe_draw_info *info,
705 unsigned *num_patches);
706 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
707 const struct pipe_draw_info *info,
708 unsigned num_patches);
709 void evergreen_set_ls_hs_config(struct r600_context *rctx,
710 struct radeon_winsys_cs *cs,
711 uint32_t ls_hs_config);
712 void evergreen_set_lds_alloc(struct r600_context *rctx,
713 struct radeon_winsys_cs *cs,
714 uint32_t lds_alloc);
715
716 /* r600_state_common.c */
717 void r600_init_common_state_functions(struct r600_context *rctx);
718 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
719 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
720 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
721 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
722 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
723 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
724 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
725 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
726 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
727 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
728 unsigned num_dw);
729 void r600_vertex_buffers_dirty(struct r600_context *rctx);
730 void r600_sampler_views_dirty(struct r600_context *rctx,
731 struct r600_samplerview_state *state);
732 void r600_sampler_states_dirty(struct r600_context *rctx,
733 struct r600_sampler_states *state);
734 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
735 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
736 uint32_t r600_translate_stencil_op(int s_op);
737 uint32_t r600_translate_fill(uint32_t func);
738 unsigned r600_tex_wrap(unsigned wrap);
739 unsigned r600_tex_mipfilter(unsigned filter);
740 unsigned r600_tex_compare(unsigned compare);
741 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
742 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
743 const unsigned char *swizzle_view,
744 boolean vtx);
745 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
746 const unsigned char *swizzle_view,
747 uint32_t *word4_p, uint32_t *yuv_format_p,
748 bool do_endian_swap);
749 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
750 bool do_endian_swap);
751 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
752
753 /* r600_uvd.c */
754 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
755 const struct pipe_video_codec *decoder);
756
757 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
758 const struct pipe_video_buffer *tmpl);
759
760 /*
761 * Helpers for building command buffers
762 */
763
764 #define PKT3_SET_CONFIG_REG 0x68
765 #define PKT3_SET_CONTEXT_REG 0x69
766 #define PKT3_SET_CTL_CONST 0x6F
767 #define PKT3_SET_LOOP_CONST 0x6C
768
769 #define R600_CONFIG_REG_OFFSET 0x08000
770 #define R600_CONTEXT_REG_OFFSET 0x28000
771 #define R600_CTL_CONST_OFFSET 0x3CFF0
772 #define R600_LOOP_CONST_OFFSET 0X0003E200
773 #define EG_LOOP_CONST_OFFSET 0x0003A200
774
775 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
776 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
777 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
778 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
779 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
780
781 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
782
783 /*Evergreen Compute packet3*/
784 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
785
786 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
787 {
788 cb->buf[cb->num_dw++] = value;
789 }
790
791 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
792 {
793 assert(cb->num_dw+num <= cb->max_num_dw);
794 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
795 cb->num_dw += num;
796 }
797
798 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
799 {
800 assert(reg < R600_CONTEXT_REG_OFFSET);
801 assert(cb->num_dw+2+num <= cb->max_num_dw);
802 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
803 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
804 }
805
806 /**
807 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
808 * shaders.
809 */
810 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
811 {
812 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
813 assert(cb->num_dw+2+num <= cb->max_num_dw);
814 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
815 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
816 }
817
818 /**
819 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
820 * shaders.
821 */
822 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
823 {
824 assert(reg >= R600_CTL_CONST_OFFSET);
825 assert(cb->num_dw+2+num <= cb->max_num_dw);
826 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
827 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
828 }
829
830 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
831 {
832 assert(reg >= R600_LOOP_CONST_OFFSET);
833 assert(cb->num_dw+2+num <= cb->max_num_dw);
834 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
835 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
836 }
837
838 /**
839 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
840 * shaders.
841 */
842 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
843 {
844 assert(reg >= EG_LOOP_CONST_OFFSET);
845 assert(cb->num_dw+2+num <= cb->max_num_dw);
846 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
847 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
848 }
849
850 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
851 {
852 r600_store_config_reg_seq(cb, reg, 1);
853 r600_store_value(cb, value);
854 }
855
856 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
857 {
858 r600_store_context_reg_seq(cb, reg, 1);
859 r600_store_value(cb, value);
860 }
861
862 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
863 {
864 r600_store_ctl_const_seq(cb, reg, 1);
865 r600_store_value(cb, value);
866 }
867
868 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
869 {
870 r600_store_loop_const_seq(cb, reg, 1);
871 r600_store_value(cb, value);
872 }
873
874 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
875 {
876 eg_store_loop_const_seq(cb, reg, 1);
877 r600_store_value(cb, value);
878 }
879
880 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
881 void r600_release_command_buffer(struct r600_command_buffer *cb);
882
883 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
884 {
885 radeon_set_context_reg_seq(cs, reg, num);
886 /* Set the compute bit on the packet header */
887 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
888 }
889
890 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
891 {
892 assert(reg >= R600_CTL_CONST_OFFSET);
893 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
894 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
895 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
896 }
897
898 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
899 {
900 radeon_compute_set_context_reg_seq(cs, reg, 1);
901 radeon_emit(cs, value);
902 }
903
904 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
905 {
906 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
907 radeon_compute_set_context_reg(cs, reg, value);
908 } else {
909 radeon_set_context_reg(cs, reg, value);
910 }
911 }
912
913 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
914 {
915 radeon_set_ctl_const_seq(cs, reg, 1);
916 radeon_emit(cs, value);
917 }
918
919 /*
920 * common helpers
921 */
922 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
923 {
924 return value * (1 << frac_bits);
925 }
926
927 /* 12.4 fixed-point */
928 static inline unsigned r600_pack_float_12p4(float x)
929 {
930 return x <= 0 ? 0 :
931 x >= 4096 ? 0xffff : x * 16;
932 }
933
934 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
935 {
936 switch (coher) {
937 default:
938 case R600_COHERENCY_NONE:
939 return 0;
940 case R600_COHERENCY_SHADER:
941 return R600_CONTEXT_INV_CONST_CACHE |
942 R600_CONTEXT_INV_VERTEX_CACHE |
943 R600_CONTEXT_INV_TEX_CACHE |
944 R600_CONTEXT_STREAMOUT_FLUSH;
945 case R600_COHERENCY_CB_META:
946 return R600_CONTEXT_FLUSH_AND_INV_CB |
947 R600_CONTEXT_FLUSH_AND_INV_CB_META;
948 }
949 }
950
951 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
952 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
953 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
954
955 unsigned r600_conv_prim_to_gs_out(unsigned mode);
956 #endif