2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_shader.h"
32 #include "r600_resource.h"
34 #define R600_MAX_CONST_BUFFERS 2
35 #define R600_MAX_CONST_BUFFER_SIZE 4096
37 #ifdef PIPE_ARCH_BIG_ENDIAN
38 #define R600_BIG_ENDIAN 1
40 #define R600_BIG_ENDIAN 0
43 enum r600_atom_flags
{
44 /* When set, atoms are added at the beginning of the dirty list
45 * instead of the end. */
49 /* This encapsulates a state or an operation which can emitted into the GPU
50 * command stream. It's not limited to states only, it can be used for anything
51 * that wants to write commands into the CS (e.g. cache flushes). */
53 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
56 enum r600_atom_flags flags
;
59 struct list_head head
;
62 /* This is an atom containing GPU commands that never change.
63 * This is supposed to be copied directly into the CS. */
64 struct r600_command_buffer
{
65 struct r600_atom atom
;
70 struct r600_surface_sync_cmd
{
71 struct r600_atom atom
;
72 unsigned flush_flags
; /* CP_COHER_CNTL */
75 struct r600_db_misc_state
{
76 struct r600_atom atom
;
77 bool occlusion_query_enabled
;
78 bool flush_depthstencil_enabled
;
81 enum r600_pipe_state_id
{
82 R600_PIPE_STATE_BLEND
= 0,
83 R600_PIPE_STATE_BLEND_COLOR
,
84 R600_PIPE_STATE_CONFIG
,
85 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
87 R600_PIPE_STATE_SCISSOR
,
88 R600_PIPE_STATE_VIEWPORT
,
89 R600_PIPE_STATE_RASTERIZER
,
91 R600_PIPE_STATE_FRAMEBUFFER
,
93 R600_PIPE_STATE_STENCIL_REF
,
94 R600_PIPE_STATE_PS_SHADER
,
95 R600_PIPE_STATE_VS_SHADER
,
96 R600_PIPE_STATE_CONSTANT
,
97 R600_PIPE_STATE_SAMPLER
,
98 R600_PIPE_STATE_RESOURCE
,
99 R600_PIPE_STATE_POLYGON_OFFSET
,
100 R600_PIPE_STATE_FETCH_SHADER
,
104 struct r600_pipe_fences
{
105 struct r600_resource
*bo
;
108 /* linked list of preallocated blocks */
109 struct list_head blocks
;
110 /* linked list of freed fences */
111 struct list_head pool
;
116 struct pipe_screen screen
;
117 struct radeon_winsys
*ws
;
119 enum chip_class chip_class
;
120 struct radeon_info info
;
121 struct r600_tiling_info tiling_info
;
122 struct util_slab_mempool pool_buffers
;
123 struct r600_pipe_fences fences
;
125 unsigned num_contexts
;
126 bool use_surface_alloc
;
128 /* for thread-safe write accessing to num_contexts */
129 pipe_mutex mutex_num_contexts
;
132 struct r600_pipe_sampler_view
{
133 struct pipe_sampler_view base
;
134 struct r600_pipe_resource_state state
;
137 struct r600_pipe_rasterizer
{
138 struct r600_pipe_state rstate
;
141 unsigned sprite_coord_enable
;
142 unsigned clip_plane_enable
;
143 unsigned pa_sc_line_stipple
;
144 unsigned pa_cl_clip_cntl
;
150 struct r600_pipe_blend
{
151 struct r600_pipe_state rstate
;
152 unsigned cb_target_mask
;
153 unsigned cb_color_control
;
156 struct r600_pipe_dsa
{
157 struct r600_pipe_state rstate
;
164 struct r600_vertex_element
167 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
168 struct u_vbuf_elements
*vmgr_elements
;
169 struct r600_resource
*fetch_shader
;
171 struct r600_pipe_state rstate
;
172 /* if offset is to big for fetch instructio we need to alterate
173 * offset of vertex buffer, record here the offset need to add
175 unsigned vbuffer_need_offset
;
176 unsigned vbuffer_offset
[PIPE_MAX_ATTRIBS
];
179 struct r600_pipe_shader
{
180 struct r600_shader shader
;
181 struct r600_pipe_state rstate
;
182 struct r600_resource
*bo
;
183 struct r600_resource
*bo_fetch
;
184 struct r600_vertex_element vertex_elements
;
185 struct tgsi_token
*tokens
;
186 unsigned sprite_coord_enable
;
188 unsigned pa_cl_vs_out_cntl
;
189 struct pipe_stream_output_info so
;
192 struct r600_pipe_sampler_state
{
193 struct r600_pipe_state rstate
;
194 boolean seamless_cube_map
;
197 /* needed for blitter save */
198 #define NUM_TEX_UNITS 16
200 struct r600_textures_info
{
201 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
202 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
206 bool is_array_sampler
[NUM_TEX_UNITS
];
210 struct pipe_reference reference
;
211 unsigned index
; /* in the shared bo */
212 struct r600_resource
*sleep_bo
;
213 struct list_head head
;
216 #define FENCE_BLOCK_SIZE 16
218 struct r600_fence_block
{
219 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
220 struct list_head head
;
223 #define R600_CONSTANT_ARRAY_SIZE 256
224 #define R600_RESOURCE_ARRAY_SIZE 160
226 struct r600_stencil_ref
233 struct r600_context
{
234 struct pipe_context context
;
235 struct blitter_context
*blitter
;
236 enum radeon_family family
;
237 enum chip_class chip_class
;
238 unsigned r6xx_num_clause_temp_gprs
;
239 void *custom_dsa_flush
;
240 struct r600_screen
*screen
;
241 struct radeon_winsys
*ws
;
242 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
243 struct r600_vertex_element
*vertex_elements
;
244 struct r600_pipe_resource_state fs_resource
[PIPE_MAX_ATTRIBS
];
245 struct pipe_framebuffer_state framebuffer
;
246 unsigned cb_target_mask
;
247 unsigned cb_color_control
;
248 unsigned pa_sc_line_stipple
;
249 unsigned pa_cl_clip_cntl
;
250 /* for saving when using blitter */
251 struct pipe_stencil_ref stencil_ref
;
252 struct pipe_viewport_state viewport
;
253 struct pipe_clip_state clip
;
254 struct r600_pipe_shader
*ps_shader
;
255 struct r600_pipe_shader
*vs_shader
;
256 struct r600_pipe_state vs_const_buffer
;
257 struct r600_pipe_resource_state vs_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
258 struct r600_pipe_state ps_const_buffer
;
259 struct r600_pipe_resource_state ps_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
260 struct r600_pipe_rasterizer
*rasterizer
;
261 struct r600_pipe_state vgt
;
262 struct r600_pipe_state spi
;
263 struct pipe_query
*current_render_cond
;
264 unsigned current_render_cond_mode
;
265 struct pipe_query
*saved_render_cond
;
266 unsigned saved_render_cond_mode
;
267 /* shader information */
269 unsigned sprite_coord_enable
;
270 boolean export_16bpc
;
272 boolean alpha_ref_dirty
;
274 struct r600_textures_info vs_samplers
;
275 struct r600_textures_info ps_samplers
;
277 struct u_vbuf
*vbuf_mgr
;
278 struct util_slab_mempool pool_transfers
;
279 boolean have_depth_texture
, have_depth_fb
;
281 unsigned default_ps_gprs
, default_vs_gprs
;
283 /* States based on r600_atom. */
284 struct list_head dirty_states
;
285 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
286 struct r600_surface_sync_cmd surface_sync_cmd
;
287 struct r600_atom r6xx_flush_and_inv_cmd
;
288 struct r600_db_misc_state db_misc_state
;
290 /* Below are variables from the old r600_context.
292 struct radeon_winsys_cs
*cs
;
294 struct r600_range
*range
;
296 struct r600_block
**blocks
;
297 struct list_head dirty
;
298 struct list_head resource_dirty
;
299 struct list_head enable_list
;
300 unsigned pm4_dirty_cdwords
;
301 unsigned ctx_pm4_ndwords
;
303 /* The list of active queries. Only one query of each type can be active. */
304 int num_occlusion_queries
;
306 /* Manage queries in two separate groups:
307 * The timer ones and the others (streamout, occlusion).
309 * We do this because we should only suspend non-timer queries for u_blitter,
310 * and later if the non-timer queries are suspended, the context flush should
311 * only suspend and resume the timer queries. */
312 struct list_head active_timer_queries
;
313 unsigned num_cs_dw_timer_queries_suspend
;
314 struct list_head active_nontimer_queries
;
315 unsigned num_cs_dw_nontimer_queries_suspend
;
317 unsigned num_cs_dw_streamout_end
;
319 unsigned backend_mask
;
320 unsigned max_db
; /* for OQ */
322 boolean predicate_drawing
;
323 struct r600_range ps_resources
;
324 struct r600_range vs_resources
;
325 struct r600_range fs_resources
;
326 int num_ps_resources
, num_vs_resources
, num_fs_resources
;
328 unsigned num_so_targets
;
329 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
330 boolean streamout_start
;
331 unsigned streamout_append_bitmask
;
333 /* There is no scissor enable bit on r6xx, so we must use a workaround.
334 * These track the current scissor state. */
336 struct pipe_scissor_state scissor_state
;
338 /* With rasterizer discard, there doesn't have to be a pixel shader.
339 * In that case, we bind this one: */
340 void *dummy_pixel_shader
;
343 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
345 atom
->emit(rctx
, atom
);
347 if (atom
->head
.next
&& atom
->head
.prev
)
348 LIST_DELINIT(&atom
->head
);
351 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
354 if (state
->flags
& EMIT_EARLY
) {
355 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
357 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
363 /* evergreen_state.c */
364 void evergreen_init_state_functions(struct r600_context
*rctx
);
365 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
366 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
367 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
368 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
369 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
370 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
371 void evergreen_pipe_init_buffer_resource(struct r600_context
*rctx
,
372 struct r600_pipe_resource_state
*rstate
);
373 void evergreen_pipe_mod_buffer_resource(struct pipe_context
*ctx
,
374 struct r600_pipe_resource_state
*rstate
,
375 struct r600_resource
*rbuffer
,
376 unsigned offset
, unsigned stride
,
377 enum radeon_bo_usage usage
);
378 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
379 enum pipe_format format
,
380 enum pipe_texture_target target
,
381 unsigned sample_count
,
385 void r600_init_blit_functions(struct r600_context
*rctx
);
386 void r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
387 void r600_blit_push_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
388 void r600_flush_depth_textures(struct r600_context
*rctx
);
391 bool r600_init_resource(struct r600_screen
*rscreen
,
392 struct r600_resource
*res
,
393 unsigned size
, unsigned alignment
,
394 unsigned bind
, unsigned usage
);
395 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
396 const struct pipe_resource
*templ
);
397 struct pipe_resource
*r600_user_buffer_create(struct pipe_screen
*screen
,
398 void *ptr
, unsigned bytes
,
400 void r600_upload_index_buffer(struct r600_context
*rctx
,
401 struct pipe_index_buffer
*ib
, unsigned count
);
405 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
409 void r600_init_query_functions(struct r600_context
*rctx
);
410 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
411 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
412 void r600_suspend_timer_queries(struct r600_context
*ctx
);
413 void r600_resume_timer_queries(struct r600_context
*ctx
);
415 /* r600_resource.c */
416 void r600_init_context_resource_functions(struct r600_context
*r600
);
419 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
420 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
421 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
422 struct r600_shader
*ps
, int id
);
425 void r600_set_scissor_state(struct r600_context
*rctx
,
426 const struct pipe_scissor_state
*state
);
427 void r600_update_sampler_states(struct r600_context
*rctx
);
428 void r600_init_state_functions(struct r600_context
*rctx
);
429 void r600_init_atom_start_cs(struct r600_context
*rctx
);
430 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
431 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
432 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
433 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
434 void r600_polygon_offset_update(struct r600_context
*rctx
);
435 void r600_pipe_init_buffer_resource(struct r600_context
*rctx
,
436 struct r600_pipe_resource_state
*rstate
);
437 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
438 struct r600_resource
*rbuffer
,
439 unsigned offset
, unsigned stride
,
440 enum radeon_bo_usage usage
);
441 void r600_adjust_gprs(struct r600_context
*rctx
);
442 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
443 enum pipe_format format
,
444 enum pipe_texture_target target
,
445 unsigned sample_count
,
449 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
450 void r600_init_surface_functions(struct r600_context
*r600
);
451 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
452 const unsigned char *swizzle_view
,
453 uint32_t *word4_p
, uint32_t *yuv_format_p
);
454 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
455 unsigned level
, unsigned layer
);
457 /* r600_translate.c */
458 void r600_translate_index_buffer(struct r600_context
*r600
,
459 struct pipe_index_buffer
*ib
,
462 /* r600_state_common.c */
463 void r600_init_atom(struct r600_atom
*atom
,
464 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
465 unsigned num_dw
, enum r600_atom_flags flags
);
466 void r600_init_common_atoms(struct r600_context
*rctx
);
467 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
468 void r600_texture_barrier(struct pipe_context
*ctx
);
469 void r600_set_index_buffer(struct pipe_context
*ctx
,
470 const struct pipe_index_buffer
*ib
);
471 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
472 const struct pipe_vertex_buffer
*buffers
);
473 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
475 const struct pipe_vertex_element
*elements
);
476 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
477 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
478 void r600_set_blend_color(struct pipe_context
*ctx
,
479 const struct pipe_blend_color
*state
);
480 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
481 void r600_set_max_scissor(struct r600_context
*rctx
);
482 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
483 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
484 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
485 struct pipe_sampler_view
*state
);
486 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
487 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
488 void *r600_create_shader_state(struct pipe_context
*ctx
,
489 const struct pipe_shader_state
*state
);
490 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
491 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
492 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
493 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
494 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
495 struct pipe_resource
*buffer
);
496 struct pipe_stream_output_target
*
497 r600_create_so_target(struct pipe_context
*ctx
,
498 struct pipe_resource
*buffer
,
499 unsigned buffer_offset
,
500 unsigned buffer_size
);
501 void r600_so_target_destroy(struct pipe_context
*ctx
,
502 struct pipe_stream_output_target
*target
);
503 void r600_set_so_targets(struct pipe_context
*ctx
,
504 unsigned num_targets
,
505 struct pipe_stream_output_target
**targets
,
506 unsigned append_bitmask
);
507 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
508 const struct pipe_stencil_ref
*state
);
509 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
510 uint32_t r600_translate_stencil_op(int s_op
);
511 uint32_t r600_translate_fill(uint32_t func
);
512 unsigned r600_tex_wrap(unsigned wrap
);
513 unsigned r600_tex_filter(unsigned filter
);
514 unsigned r600_tex_mipfilter(unsigned filter
);
515 unsigned r600_tex_compare(unsigned compare
);
518 * Helpers for building command buffers
521 #define PKT3_SET_CONFIG_REG 0x68
522 #define PKT3_SET_CONTEXT_REG 0x69
523 #define PKT3_SET_CTL_CONST 0x6F
524 #define PKT3_SET_LOOP_CONST 0x6C
526 #define R600_CONFIG_REG_OFFSET 0x08000
527 #define R600_CONTEXT_REG_OFFSET 0x28000
528 #define R600_CTL_CONST_OFFSET 0x3CFF0
529 #define R600_LOOP_CONST_OFFSET 0X0003E200
530 #define EG_LOOP_CONST_OFFSET 0x0003A200
532 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
533 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
534 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
535 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
536 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
538 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
540 cb
->buf
[cb
->atom
.num_dw
++] = value
;
543 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
545 assert(reg
< R600_CONTEXT_REG_OFFSET
);
546 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
547 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
548 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
551 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
553 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
554 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
555 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
556 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
559 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
561 assert(reg
>= R600_CTL_CONST_OFFSET
);
562 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
563 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
564 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
567 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
569 assert(reg
>= R600_LOOP_CONST_OFFSET
);
570 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
571 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
572 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
575 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
577 assert(reg
>= EG_LOOP_CONST_OFFSET
);
578 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
579 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
580 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
583 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
585 r600_store_config_reg_seq(cb
, reg
, 1);
586 r600_store_value(cb
, value
);
589 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
591 r600_store_context_reg_seq(cb
, reg
, 1);
592 r600_store_value(cb
, value
);
595 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
597 r600_store_ctl_const_seq(cb
, reg
, 1);
598 r600_store_value(cb
, value
);
601 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
603 r600_store_loop_const_seq(cb
, reg
, 1);
604 r600_store_value(cb
, value
);
607 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
609 eg_store_loop_const_seq(cb
, reg
, 1);
610 r600_store_value(cb
, value
);
613 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
614 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
617 * Helpers for emitting state into a command stream directly.
620 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
621 enum radeon_bo_usage usage
)
624 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
627 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
629 cs
->buf
[cs
->cdw
++] = value
;
632 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
634 assert(reg
< R600_CONTEXT_REG_OFFSET
);
635 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
636 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
637 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
640 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
642 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
643 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
644 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
645 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
648 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
650 assert(reg
>= R600_CTL_CONST_OFFSET
);
651 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
652 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
653 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
656 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
658 r600_write_config_reg_seq(cs
, reg
, 1);
659 r600_write_value(cs
, value
);
662 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
664 r600_write_context_reg_seq(cs
, reg
, 1);
665 r600_write_value(cs
, value
);
668 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
670 r600_write_ctl_const_seq(cs
, reg
, 1);
671 r600_write_value(cs
, value
);
677 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
679 return value
* (1 << frac_bits
);
681 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
683 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
685 if (filter
<= 1) return 0;
686 if (filter
<= 2) return 1;
687 if (filter
<= 4) return 2;
688 if (filter
<= 8) return 3;
692 /* 12.4 fixed-point */
693 static INLINE
unsigned r600_pack_float_12p4(float x
)
696 x
>= 4096 ? 0xffff : x
* 16;