src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_math.h"
  35 #include "util/u_slab.h"
  36 #include "util/u_vbuf_mgr.h"
  37 #include "r600.h"
  38 #include "r600_public.h"
  39 #include "r600_shader.h"
  40 #include "r600_resource.h"
  41
  42 #define R600_MAX_CONST_BUFFERS 1
  43 #define R600_MAX_CONST_BUFFER_SIZE 4096
  44
  45 #ifdef PIPE_ARCH_BIG_ENDIAN
  46 #define R600_BIG_ENDIAN 1
  47 #else
  48 #define R600_BIG_ENDIAN 0
  49 #endif
  50
  51 enum r600_pipe_state_id {
  52         R600_PIPE_STATE_BLEND = 0,
  53         R600_PIPE_STATE_BLEND_COLOR,
  54         R600_PIPE_STATE_CONFIG,
  55         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  56         R600_PIPE_STATE_CLIP,
  57         R600_PIPE_STATE_SCISSOR,
  58         R600_PIPE_STATE_VIEWPORT,
  59         R600_PIPE_STATE_RASTERIZER,
  60         R600_PIPE_STATE_VGT,
  61         R600_PIPE_STATE_FRAMEBUFFER,
  62         R600_PIPE_STATE_DSA,
  63         R600_PIPE_STATE_STENCIL_REF,
  64         R600_PIPE_STATE_PS_SHADER,
  65         R600_PIPE_STATE_VS_SHADER,
  66         R600_PIPE_STATE_CONSTANT,
  67         R600_PIPE_STATE_SAMPLER,
  68         R600_PIPE_STATE_RESOURCE,
  69         R600_PIPE_STATE_POLYGON_OFFSET,
  70         R600_PIPE_STATE_FETCH_SHADER,
  71         R600_PIPE_STATE_SPI,
  72         R600_PIPE_NSTATES
  73 };
  74
  75 struct r600_screen {
  76         struct pipe_screen              screen;
  77         struct radeon_winsys            *ws;
  78         unsigned                        family;
  79         enum chip_class                 chip_class;
  80         struct radeon_info              info;
  81         struct r600_tiling_info         tiling_info;
  82         struct util_slab_mempool        pool_buffers;
  83         unsigned                        num_contexts;
  84
  85         /* for thread-safe write accessing to num_contexts */
  86         pipe_mutex                      mutex_num_contexts;
  87 };
  88
  89 struct r600_pipe_sampler_view {
  90         struct pipe_sampler_view        base;
  91         struct r600_pipe_resource_state         state;
  92 };
  93
  94 struct r600_pipe_rasterizer {
  95         struct r600_pipe_state          rstate;
  96         boolean                         clamp_vertex_color;
  97         boolean                         clamp_fragment_color;
  98         boolean                         flatshade;
  99         unsigned                        sprite_coord_enable;
 100         float                           offset_units;
 101         float                           offset_scale;
 102 };
 103
 104 struct r600_pipe_blend {
 105         struct r600_pipe_state          rstate;
 106         unsigned                        cb_target_mask;
 107 };
 108
 109 struct r600_pipe_dsa {
 110         struct r600_pipe_state          rstate;
 111         unsigned                        alpha_ref;
 112 };
 113
 114 struct r600_vertex_element
 115 {
 116         unsigned                        count;
 117         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 118         struct u_vbuf_elements          *vmgr_elements;
 119         struct r600_resource            *fetch_shader;
 120         unsigned                        fs_size;
 121         struct r600_pipe_state          rstate;
 122         /* if offset is to big for fetch instructio we need to alterate
 123          * offset of vertex buffer, record here the offset need to add
 124          */
 125         unsigned                        vbuffer_need_offset;
 126         unsigned                        vbuffer_offset[PIPE_MAX_ATTRIBS];
 127 };
 128
 129 struct r600_pipe_shader {
 130         struct r600_shader              shader;
 131         struct r600_pipe_state          rstate;
 132         struct r600_resource            *bo;
 133         struct r600_resource            *bo_fetch;
 134         struct r600_vertex_element      vertex_elements;
 135         struct tgsi_token               *tokens;
 136 };
 137
 138 struct r600_pipe_sampler_state {
 139         struct r600_pipe_state          rstate;
 140         boolean seamless_cube_map;
 141 };
 142
 143 /* needed for blitter save */
 144 #define NUM_TEX_UNITS 16
 145
 146 struct r600_textures_info {
 147         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 148         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 149         unsigned                        n_views;
 150         unsigned                        n_samplers;
 151         bool                            samplers_dirty;
 152         bool                            is_array_sampler[NUM_TEX_UNITS];
 153 };
 154
 155 struct r600_fence {
 156         struct pipe_reference           reference;
 157         struct r600_pipe_context        *ctx;
 158         unsigned                        index; /* in the shared bo */
 159         struct list_head                head;
 160 };
 161
 162 #define FENCE_BLOCK_SIZE 16
 163
 164 struct r600_fence_block {
 165         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 166         struct list_head                head;
 167 };
 168
 169 struct r600_pipe_fences {
 170         struct r600_resource            *bo;
 171         unsigned                        *data;
 172         unsigned                        next_index;
 173         /* linked list of preallocated blocks */
 174         struct list_head                blocks;
 175         /* linked list of freed fences */
 176         struct list_head                pool;
 177 };
 178
 179 #define R600_CONSTANT_ARRAY_SIZE 256
 180 #define R600_RESOURCE_ARRAY_SIZE 160
 181
 182 struct r600_pipe_context {
 183         struct pipe_context             context;
 184         struct blitter_context          *blitter;
 185         enum radeon_family              family;
 186         enum chip_class                 chip_class;
 187         void                            *custom_dsa_flush;
 188         struct r600_screen              *screen;
 189         struct radeon_winsys            *ws;
 190         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 191         struct r600_context             ctx;
 192         struct r600_vertex_element      *vertex_elements;
 193         struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
 194         struct pipe_framebuffer_state   framebuffer;
 195         struct pipe_index_buffer        index_buffer;
 196         unsigned                        cb_target_mask;
 197         /* for saving when using blitter */
 198         struct pipe_stencil_ref         stencil_ref;
 199         struct pipe_viewport_state      viewport;
 200         struct pipe_clip_state          clip;
 201         struct r600_pipe_state          config;
 202         struct r600_pipe_shader         *ps_shader;
 203         struct r600_pipe_shader         *vs_shader;
 204         struct r600_pipe_state          vs_const_buffer;
 205         struct r600_pipe_resource_state         vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 206         struct r600_pipe_state          ps_const_buffer;
 207         struct r600_pipe_resource_state         ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 208         struct r600_pipe_rasterizer     *rasterizer;
 209         struct r600_pipe_state          vgt;
 210         struct r600_pipe_state          spi;
 211         struct pipe_query               *current_render_cond;
 212         unsigned                        current_render_cond_mode;
 213         struct pipe_query               *saved_render_cond;
 214         unsigned                        saved_render_cond_mode;
 215         /* shader information */
 216         boolean                         clamp_vertex_color;
 217         boolean                         clamp_fragment_color;
 218         boolean                         spi_dirty;
 219         unsigned                        sprite_coord_enable;
 220         boolean                         flatshade;
 221         boolean                         export_16bpc;
 222         unsigned                        alpha_ref;
 223         boolean                         alpha_ref_dirty;
 224         unsigned                        nr_cbufs;
 225         struct r600_textures_info       vs_samplers;
 226         struct r600_textures_info       ps_samplers;
 227
 228         struct r600_pipe_fences         fences;
 229
 230         struct u_vbuf_mgr               *vbuf_mgr;
 231         struct util_slab_mempool        pool_transfers;
 232         boolean                         blit;
 233         boolean                         have_depth_texture, have_depth_fb;
 234
 235         unsigned default_ps_gprs, default_vs_gprs;
 236 };
 237
 238 struct r600_drawl {
 239         struct pipe_draw_info   info;
 240         struct pipe_context     *ctx;
 241         unsigned                index_size;
 242         unsigned                index_buffer_offset;
 243         struct pipe_resource    *index_buffer;
 244 };
 245
 246 /* evergreen_state.c */
 247 void evergreen_init_state_functions(struct r600_pipe_context *rctx);
 248 void evergreen_init_config(struct r600_pipe_context *rctx);
 249 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 250 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 251 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 252 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
 253 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx);
 254 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
 255                                          struct r600_pipe_resource_state *rstate);
 256 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 257                                         struct r600_resource *rbuffer,
 258                                         unsigned offset, unsigned stride,
 259                                         enum radeon_bo_usage usage);
 260 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 261                                       enum pipe_format format,
 262                                       enum pipe_texture_target target,
 263                                       unsigned sample_count,
 264                                       unsigned usage);
 265
 266 /* r600_blit.c */
 267 void r600_init_blit_functions(struct r600_pipe_context *rctx);
 268 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 269 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 270 void r600_flush_depth_textures(struct r600_pipe_context *rctx);
 271
 272 /* r600_buffer.c */
 273 bool r600_init_resource(struct r600_screen *rscreen,
 274                         struct r600_resource *res,
 275                         unsigned size, unsigned alignment,
 276                         unsigned bind, unsigned usage);
 277 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 278                                          const struct pipe_resource *templ);
 279 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 280                                               void *ptr, unsigned bytes,
 281                                               unsigned bind);
 282 void r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw);
 283
 284
 285 /* r600_pipe.c */
 286 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 287                 unsigned flags);
 288
 289 /* r600_query.c */
 290 void r600_init_query_functions(struct r600_pipe_context *rctx);
 291
 292 /* r600_resource.c */
 293 void r600_init_context_resource_functions(struct r600_pipe_context *r600);
 294
 295 /* r600_shader.c */
 296 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 297 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 298 int r600_find_vs_semantic_index(struct r600_shader *vs,
 299                                 struct r600_shader *ps, int id);
 300
 301 /* r600_state.c */
 302 void r600_update_sampler_states(struct r600_pipe_context *rctx);
 303 void r600_init_state_functions(struct r600_pipe_context *rctx);
 304 void r600_init_config(struct r600_pipe_context *rctx);
 305 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 306 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 307 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 308 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
 309 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
 310 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
 311                                     struct r600_pipe_resource_state *rstate);
 312 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 313                                    struct r600_resource *rbuffer,
 314                                    unsigned offset, unsigned stride,
 315                                    enum radeon_bo_usage usage);
 316 void r600_adjust_gprs(struct r600_pipe_context *rctx);
 317 boolean r600_is_format_supported(struct pipe_screen *screen,
 318                                  enum pipe_format format,
 319                                  enum pipe_texture_target target,
 320                                  unsigned sample_count,
 321                                  unsigned usage);
 322
 323 /* r600_texture.c */
 324 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 325 void r600_init_surface_functions(struct r600_pipe_context *r600);
 326 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 327                                   const unsigned char *swizzle_view,
 328                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 329 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 330                                         unsigned level, unsigned layer);
 331
 332 /* r600_translate.c */
 333 void r600_translate_index_buffer(struct r600_pipe_context *r600,
 334                                  struct pipe_resource **index_buffer,
 335                                  unsigned *index_size,
 336                                  unsigned *start, unsigned count);
 337
 338 /* r600_state_common.c */
 339 void r600_set_index_buffer(struct pipe_context *ctx,
 340                            const struct pipe_index_buffer *ib);
 341 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 342                              const struct pipe_vertex_buffer *buffers);
 343 void *r600_create_vertex_elements(struct pipe_context *ctx,
 344                                   unsigned count,
 345                                   const struct pipe_vertex_element *elements);
 346 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 347 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 348 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 349 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 350 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 351 void r600_sampler_view_destroy(struct pipe_context *ctx,
 352                                struct pipe_sampler_view *state);
 353 void r600_delete_state(struct pipe_context *ctx, void *state);
 354 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 355 void *r600_create_shader_state(struct pipe_context *ctx,
 356                                const struct pipe_shader_state *state);
 357 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 358 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 359 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 360 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 361 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 362                               struct pipe_resource *buffer);
 363 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 364
 365 /*
 366  * common helpers
 367  */
 368 static INLINE u32 S_FIXED(float value, u32 frac_bits)
 369 {
 370         return value * (1 << frac_bits);
 371 }
 372 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 373
 374 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 375 {
 376         if (filter <= 1)   return 0;
 377         if (filter <= 2)   return 1;
 378         if (filter <= 4)   return 2;
 379         if (filter <= 8)   return 3;
 380          /* else */        return 4;
 381 }
 382
 383 #endif