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r600g: only do necessary cache flushes in cp_dma_clear_buffer
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
36 #include "util/u_memory.h"
37
38 #include "tgsi/tgsi_scan.h"
39
40 #define R600_NUM_ATOMS 52
41
42 /* read caches */
43 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
44 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
45 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
46 /* read-write caches */
47 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
48 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
49 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
52 /* engine synchronization */
53 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
54 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
55 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
56
57 /* the number of CS dwords for flushing and drawing */
58 #define R600_MAX_FLUSH_CS_DWORDS 18
59 #define R600_MAX_DRAW_CS_DWORDS 58
60 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
61
62 #define R600_MAX_USER_CONST_BUFFERS 13
63 #define R600_MAX_DRIVER_CONST_BUFFERS 3
64 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
65
66 /* start driver buffers after user buffers */
67 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
68 #define R600_UCP_SIZE (4*4*8)
69 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
70
71 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
72 /*
73 * Note GS doesn't use a constant buffer binding, just a resource index,
74 * so it's fine to have it exist at index 16.
75 */
76 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
77 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
78 * of 16 const buffers.
79 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
80 *
81 * In order to support d3d 11 mandated minimum of 15 user const buffers
82 * we'd have to squash all use cases into one driver buffer.
83 */
84 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
85
86 /* HW stages */
87 #define R600_HW_STAGE_PS 0
88 #define R600_HW_STAGE_VS 1
89 #define R600_HW_STAGE_GS 2
90 #define R600_HW_STAGE_ES 3
91 #define EG_HW_STAGE_LS 4
92 #define EG_HW_STAGE_HS 5
93
94 #define R600_NUM_HW_STAGES 4
95 #define EG_NUM_HW_STAGES 6
96
97 struct r600_context;
98 struct r600_bytecode;
99 union r600_shader_key;
100
101 /* This is an atom containing GPU commands that never change.
102 * This is supposed to be copied directly into the CS. */
103 struct r600_command_buffer {
104 uint32_t *buf;
105 unsigned num_dw;
106 unsigned max_num_dw;
107 unsigned pkt_flags;
108 };
109
110 struct r600_db_state {
111 struct r600_atom atom;
112 struct r600_surface *rsurf;
113 };
114
115 struct r600_db_misc_state {
116 struct r600_atom atom;
117 bool occlusion_queries_disabled;
118 bool flush_depthstencil_through_cb;
119 bool flush_depth_inplace;
120 bool flush_stencil_inplace;
121 bool copy_depth, copy_stencil;
122 unsigned copy_sample;
123 unsigned log_samples;
124 unsigned db_shader_control;
125 bool htile_clear;
126 uint8_t ps_conservative_z;
127 };
128
129 struct r600_cb_misc_state {
130 struct r600_atom atom;
131 unsigned cb_color_control; /* this comes from blend state */
132 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
133 unsigned nr_cbufs;
134 unsigned nr_ps_color_outputs;
135 bool multiwrite;
136 bool dual_src_blend;
137 };
138
139 struct r600_clip_misc_state {
140 struct r600_atom atom;
141 unsigned pa_cl_clip_cntl; /* from rasterizer */
142 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
143 unsigned clip_plane_enable; /* from rasterizer */
144 unsigned clip_dist_write; /* from vertex shader */
145 boolean clip_disable; /* from vertex shader */
146 boolean vs_out_viewport; /* from vertex shader */
147 };
148
149 struct r600_alphatest_state {
150 struct r600_atom atom;
151 unsigned sx_alpha_test_control; /* this comes from dsa state */
152 unsigned sx_alpha_ref; /* this comes from dsa state */
153 bool bypass;
154 bool cb0_export_16bpc; /* from set_framebuffer_state */
155 };
156
157 struct r600_vgt_state {
158 struct r600_atom atom;
159 uint32_t vgt_multi_prim_ib_reset_en;
160 uint32_t vgt_multi_prim_ib_reset_indx;
161 uint32_t vgt_indx_offset;
162 bool last_draw_was_indirect;
163 };
164
165 struct r600_blend_color {
166 struct r600_atom atom;
167 struct pipe_blend_color state;
168 };
169
170 struct r600_clip_state {
171 struct r600_atom atom;
172 struct pipe_clip_state state;
173 };
174
175 struct r600_cs_shader_state {
176 struct r600_atom atom;
177 unsigned kernel_index;
178 unsigned pc;
179 struct r600_pipe_compute *shader;
180 };
181
182 struct r600_framebuffer {
183 struct r600_atom atom;
184 struct pipe_framebuffer_state state;
185 unsigned compressed_cb_mask;
186 unsigned nr_samples;
187 bool export_16bpc;
188 bool cb0_is_integer;
189 bool is_msaa_resolve;
190 };
191
192 struct r600_sample_mask {
193 struct r600_atom atom;
194 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
195 };
196
197 struct r600_config_state {
198 struct r600_atom atom;
199 unsigned sq_gpr_resource_mgmt_1;
200 unsigned sq_gpr_resource_mgmt_2;
201 unsigned sq_gpr_resource_mgmt_3;
202 bool dyn_gpr_enabled;
203 };
204
205 struct r600_stencil_ref
206 {
207 ubyte ref_value[2];
208 ubyte valuemask[2];
209 ubyte writemask[2];
210 };
211
212 struct r600_stencil_ref_state {
213 struct r600_atom atom;
214 struct r600_stencil_ref state;
215 struct pipe_stencil_ref pipe_state;
216 };
217
218 struct r600_shader_stages_state {
219 struct r600_atom atom;
220 unsigned geom_enable;
221 };
222
223 struct r600_gs_rings_state {
224 struct r600_atom atom;
225 unsigned enable;
226 struct pipe_constant_buffer esgs_ring;
227 struct pipe_constant_buffer gsvs_ring;
228 };
229
230 /* This must start from 16. */
231 /* features */
232 #define DBG_NO_CP_DMA (1 << 30)
233 /* shader backend */
234 #define DBG_NO_SB (1 << 21)
235 #define DBG_SB_CS (1 << 22)
236 #define DBG_SB_DRY_RUN (1 << 23)
237 #define DBG_SB_STAT (1 << 24)
238 #define DBG_SB_DUMP (1 << 25)
239 #define DBG_SB_NO_FALLBACK (1 << 26)
240 #define DBG_SB_DISASM (1 << 27)
241 #define DBG_SB_SAFEMATH (1 << 28)
242
243 struct r600_screen {
244 struct r600_common_screen b;
245 bool has_msaa;
246 bool has_compressed_msaa_texturing;
247
248 /*for compute global memory binding, we allocate stuff here, instead of
249 * buffers.
250 * XXX: Not sure if this is the best place for global_pool. Also,
251 * it's not thread safe, so it won't work with multiple contexts. */
252 struct compute_memory_pool *global_pool;
253 };
254
255 struct r600_pipe_sampler_view {
256 struct pipe_sampler_view base;
257 struct list_head list;
258 struct r600_resource *tex_resource;
259 uint32_t tex_resource_words[8];
260 bool skip_mip_address_reloc;
261 bool is_stencil_sampler;
262 };
263
264 struct r600_rasterizer_state {
265 struct r600_command_buffer buffer;
266 boolean flatshade;
267 boolean two_side;
268 unsigned sprite_coord_enable;
269 unsigned clip_plane_enable;
270 unsigned pa_sc_line_stipple;
271 unsigned pa_cl_clip_cntl;
272 unsigned pa_su_sc_mode_cntl;
273 float offset_units;
274 float offset_scale;
275 bool offset_enable;
276 bool scissor_enable;
277 bool multisample_enable;
278 };
279
280 struct r600_poly_offset_state {
281 struct r600_atom atom;
282 enum pipe_format zs_format;
283 float offset_units;
284 float offset_scale;
285 };
286
287 struct r600_blend_state {
288 struct r600_command_buffer buffer;
289 struct r600_command_buffer buffer_no_blend;
290 unsigned cb_target_mask;
291 unsigned cb_color_control;
292 unsigned cb_color_control_no_blend;
293 bool dual_src_blend;
294 bool alpha_to_one;
295 };
296
297 struct r600_dsa_state {
298 struct r600_command_buffer buffer;
299 unsigned alpha_ref;
300 ubyte valuemask[2];
301 ubyte writemask[2];
302 unsigned zwritemask;
303 unsigned sx_alpha_test_control;
304 };
305
306 struct r600_pipe_shader;
307
308 struct r600_pipe_shader_selector {
309 struct r600_pipe_shader *current;
310
311 struct tgsi_token *tokens;
312 struct pipe_stream_output_info so;
313 struct tgsi_shader_info info;
314
315 unsigned num_shaders;
316
317 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
318 unsigned type;
319
320 /* geometry shader properties */
321 unsigned gs_output_prim;
322 unsigned gs_max_out_vertices;
323 unsigned gs_num_invocations;
324
325 /* TCS/VS */
326 uint64_t lds_patch_outputs_written_mask;
327 uint64_t lds_outputs_written_mask;
328 unsigned nr_ps_max_color_exports;
329 };
330
331 struct r600_pipe_sampler_state {
332 uint32_t tex_sampler_words[3];
333 union pipe_color_union border_color;
334 bool border_color_use;
335 bool seamless_cube_map;
336 };
337
338 /* needed for blitter save */
339 #define NUM_TEX_UNITS 16
340
341 struct r600_seamless_cube_map {
342 struct r600_atom atom;
343 bool enabled;
344 };
345
346 struct r600_samplerview_state {
347 struct r600_atom atom;
348 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
349 uint32_t enabled_mask;
350 uint32_t dirty_mask;
351 uint32_t compressed_depthtex_mask; /* which textures are depth */
352 uint32_t compressed_colortex_mask;
353 boolean dirty_buffer_constants;
354 };
355
356 struct r600_sampler_states {
357 struct r600_atom atom;
358 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
359 uint32_t enabled_mask;
360 uint32_t dirty_mask;
361 uint32_t has_bordercolor_mask; /* which states contain the border color */
362 };
363
364 struct r600_textures_info {
365 struct r600_samplerview_state views;
366 struct r600_sampler_states states;
367 bool is_array_sampler[NUM_TEX_UNITS];
368 };
369
370 struct r600_shader_driver_constants_info {
371 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
372 uint32_t *constants;
373 uint32_t alloc_size;
374 bool vs_ucp_dirty;
375 bool texture_const_dirty;
376 bool ps_sample_pos_dirty;
377 };
378
379 struct r600_constbuf_state
380 {
381 struct r600_atom atom;
382 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
383 uint32_t enabled_mask;
384 uint32_t dirty_mask;
385 };
386
387 struct r600_vertexbuf_state
388 {
389 struct r600_atom atom;
390 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
391 uint32_t enabled_mask; /* non-NULL buffers */
392 uint32_t dirty_mask;
393 };
394
395 /* CSO (constant state object, in other words, immutable state). */
396 struct r600_cso_state
397 {
398 struct r600_atom atom;
399 void *cso; /* e.g. r600_blend_state */
400 struct r600_command_buffer *cb;
401 };
402
403 struct r600_fetch_shader {
404 struct r600_resource *buffer;
405 unsigned offset;
406 };
407
408 struct r600_shader_state {
409 struct r600_atom atom;
410 struct r600_pipe_shader *shader;
411 };
412
413 struct r600_context {
414 struct r600_common_context b;
415 struct r600_screen *screen;
416 struct blitter_context *blitter;
417 struct u_suballocator *allocator_fetch_shader;
418
419 /* Hardware info. */
420 boolean has_vertex_cache;
421 unsigned default_gprs[EG_NUM_HW_STAGES];
422 unsigned current_gprs[EG_NUM_HW_STAGES];
423 unsigned r6xx_num_clause_temp_gprs;
424
425 /* Miscellaneous state objects. */
426 void *custom_dsa_flush;
427 void *custom_blend_resolve;
428 void *custom_blend_decompress;
429 void *custom_blend_fastclear;
430 /* With rasterizer discard, there doesn't have to be a pixel shader.
431 * In that case, we bind this one: */
432 void *dummy_pixel_shader;
433 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
434 * bug where valid CMASK and FMASK are required to be present to avoid
435 * a hardlock in certain operations but aren't actually used
436 * for anything useful. */
437 struct r600_resource *dummy_fmask;
438 struct r600_resource *dummy_cmask;
439
440 /* State binding slots are here. */
441 struct r600_atom *atoms[R600_NUM_ATOMS];
442 /* Dirty atom bitmask for fast tests */
443 uint64_t dirty_atoms;
444 /* States for CS initialization. */
445 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
446 /** Compute specific registers initializations. The start_cs_cmd atom
447 * must be emitted before start_compute_cs_cmd. */
448 struct r600_command_buffer start_compute_cs_cmd;
449 /* Register states. */
450 struct r600_alphatest_state alphatest_state;
451 struct r600_cso_state blend_state;
452 struct r600_blend_color blend_color;
453 struct r600_cb_misc_state cb_misc_state;
454 struct r600_clip_misc_state clip_misc_state;
455 struct r600_clip_state clip_state;
456 struct r600_db_misc_state db_misc_state;
457 struct r600_db_state db_state;
458 struct r600_cso_state dsa_state;
459 struct r600_framebuffer framebuffer;
460 struct r600_poly_offset_state poly_offset_state;
461 struct r600_cso_state rasterizer_state;
462 struct r600_sample_mask sample_mask;
463 struct r600_seamless_cube_map seamless_cube_map;
464 struct r600_config_state config_state;
465 struct r600_stencil_ref_state stencil_ref;
466 struct r600_vgt_state vgt_state;
467 /* Shaders and shader resources. */
468 struct r600_cso_state vertex_fetch_shader;
469 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
470 struct r600_cs_shader_state cs_shader_state;
471 struct r600_shader_stages_state shader_stages;
472 struct r600_gs_rings_state gs_rings;
473 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
474 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
475
476 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
477
478 /** Vertex buffers for fetch shaders */
479 struct r600_vertexbuf_state vertex_buffer_state;
480 /** Vertex buffers for compute shaders */
481 struct r600_vertexbuf_state cs_vertex_buffer_state;
482
483 /* Additional context states. */
484 unsigned compute_cb_target_mask;
485 struct r600_pipe_shader_selector *ps_shader;
486 struct r600_pipe_shader_selector *vs_shader;
487 struct r600_pipe_shader_selector *gs_shader;
488
489 struct r600_pipe_shader_selector *tcs_shader;
490 struct r600_pipe_shader_selector *tes_shader;
491
492 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
493
494 struct r600_rasterizer_state *rasterizer;
495 bool alpha_to_one;
496 bool force_blend_disable;
497 boolean dual_src_blend;
498 unsigned zwritemask;
499 int ps_iter_samples;
500
501 /* Index buffer. */
502 struct pipe_index_buffer index_buffer;
503
504 /* Last draw state (-1 = unset). */
505 int last_primitive_type; /* Last primitive type used in draw_vbo. */
506 int last_start_instance;
507
508 void *sb_context;
509 struct r600_isa *isa;
510 float sample_positions[4 * 16];
511 float tess_state[8];
512 bool tess_state_dirty;
513 struct r600_pipe_shader_selector *last_ls;
514 struct r600_pipe_shader_selector *last_tcs;
515 unsigned last_num_tcs_input_cp;
516 unsigned lds_alloc;
517 };
518
519 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
520 struct r600_command_buffer *cb)
521 {
522 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
523 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
524 cs->current.cdw += cb->num_dw;
525 }
526
527 static inline void r600_set_atom_dirty(struct r600_context *rctx,
528 struct r600_atom *atom,
529 bool dirty)
530 {
531 uint64_t mask;
532
533 assert(atom->id != 0);
534 assert(atom->id < sizeof(mask) * 8);
535 mask = 1ull << atom->id;
536 if (dirty)
537 rctx->dirty_atoms |= mask;
538 else
539 rctx->dirty_atoms &= ~mask;
540 }
541
542 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
543 struct r600_atom *atom)
544 {
545 r600_set_atom_dirty(rctx, atom, true);
546 }
547
548 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
549 {
550 atom->emit(&rctx->b, atom);
551 r600_set_atom_dirty(rctx, atom, false);
552 }
553
554 static inline void r600_set_cso_state(struct r600_context *rctx,
555 struct r600_cso_state *state, void *cso)
556 {
557 state->cso = cso;
558 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
559 }
560
561 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
562 struct r600_cso_state *state, void *cso,
563 struct r600_command_buffer *cb)
564 {
565 state->cb = cb;
566 state->atom.num_dw = cb ? cb->num_dw : 0;
567 r600_set_cso_state(rctx, state, cso);
568 }
569
570 /* compute_memory_pool.c */
571 struct compute_memory_pool;
572 void compute_memory_pool_delete(struct compute_memory_pool* pool);
573 struct compute_memory_pool* compute_memory_pool_new(
574 struct r600_screen *rscreen);
575
576 /* evergreen_state.c */
577 struct pipe_sampler_view *
578 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
579 struct pipe_resource *texture,
580 const struct pipe_sampler_view *state,
581 unsigned width0, unsigned height0,
582 unsigned force_level);
583 void evergreen_init_common_regs(struct r600_context *ctx,
584 struct r600_command_buffer *cb,
585 enum chip_class ctx_chip_class,
586 enum radeon_family ctx_family,
587 int ctx_drm_minor);
588 void cayman_init_common_regs(struct r600_command_buffer *cb,
589 enum chip_class ctx_chip_class,
590 enum radeon_family ctx_family,
591 int ctx_drm_minor);
592
593 void evergreen_init_state_functions(struct r600_context *rctx);
594 void evergreen_init_atom_start_cs(struct r600_context *rctx);
595 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
596 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
597 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
598 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
599 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
600 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
601 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
602 void *evergreen_create_resolve_blend(struct r600_context *rctx);
603 void *evergreen_create_decompress_blend(struct r600_context *rctx);
604 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
605 boolean evergreen_is_format_supported(struct pipe_screen *screen,
606 enum pipe_format format,
607 enum pipe_texture_target target,
608 unsigned sample_count,
609 unsigned usage);
610 void evergreen_init_color_surface(struct r600_context *rctx,
611 struct r600_surface *surf);
612 void evergreen_init_color_surface_rat(struct r600_context *rctx,
613 struct r600_surface *surf);
614 void evergreen_update_db_shader_control(struct r600_context * rctx);
615 bool evergreen_adjust_gprs(struct r600_context *rctx);
616 /* r600_blit.c */
617 void r600_init_blit_functions(struct r600_context *rctx);
618 void r600_decompress_depth_textures(struct r600_context *rctx,
619 struct r600_samplerview_state *textures);
620 void r600_decompress_color_textures(struct r600_context *rctx,
621 struct r600_samplerview_state *textures);
622 void r600_resource_copy_region(struct pipe_context *ctx,
623 struct pipe_resource *dst,
624 unsigned dst_level,
625 unsigned dstx, unsigned dsty, unsigned dstz,
626 struct pipe_resource *src,
627 unsigned src_level,
628 const struct pipe_box *src_box);
629
630 /* r600_shader.c */
631 int r600_pipe_shader_create(struct pipe_context *ctx,
632 struct r600_pipe_shader *shader,
633 union r600_shader_key key);
634
635 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
636
637 /* r600_state.c */
638 struct pipe_sampler_view *
639 r600_create_sampler_view_custom(struct pipe_context *ctx,
640 struct pipe_resource *texture,
641 const struct pipe_sampler_view *state,
642 unsigned width_first_level, unsigned height_first_level);
643 void r600_init_state_functions(struct r600_context *rctx);
644 void r600_init_atom_start_cs(struct r600_context *rctx);
645 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
646 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
647 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
648 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
649 void *r600_create_db_flush_dsa(struct r600_context *rctx);
650 void *r600_create_resolve_blend(struct r600_context *rctx);
651 void *r700_create_resolve_blend(struct r600_context *rctx);
652 void *r600_create_decompress_blend(struct r600_context *rctx);
653 bool r600_adjust_gprs(struct r600_context *rctx);
654 boolean r600_is_format_supported(struct pipe_screen *screen,
655 enum pipe_format format,
656 enum pipe_texture_target target,
657 unsigned sample_count,
658 unsigned usage);
659 void r600_update_db_shader_control(struct r600_context * rctx);
660
661 /* r600_hw_context.c */
662 void r600_context_gfx_flush(void *context, unsigned flags,
663 struct pipe_fence_handle **fence);
664 void r600_begin_new_cs(struct r600_context *ctx);
665 void r600_flush_emit(struct r600_context *ctx);
666 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
667 void r600_emit_pfp_sync_me(struct r600_context *rctx);
668 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
669 struct pipe_resource *dst, uint64_t dst_offset,
670 struct pipe_resource *src, uint64_t src_offset,
671 unsigned size);
672 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
673 struct pipe_resource *dst, uint64_t offset,
674 unsigned size, uint32_t clear_value,
675 enum r600_coherency coher);
676 void r600_dma_copy_buffer(struct r600_context *rctx,
677 struct pipe_resource *dst,
678 struct pipe_resource *src,
679 uint64_t dst_offset,
680 uint64_t src_offset,
681 uint64_t size);
682
683 /*
684 * evergreen_hw_context.c
685 */
686 void evergreen_dma_copy_buffer(struct r600_context *rctx,
687 struct pipe_resource *dst,
688 struct pipe_resource *src,
689 uint64_t dst_offset,
690 uint64_t src_offset,
691 uint64_t size);
692 void evergreen_setup_tess_constants(struct r600_context *rctx,
693 const struct pipe_draw_info *info,
694 unsigned *num_patches);
695 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
696 const struct pipe_draw_info *info,
697 unsigned num_patches);
698 void evergreen_set_ls_hs_config(struct r600_context *rctx,
699 struct radeon_winsys_cs *cs,
700 uint32_t ls_hs_config);
701 void evergreen_set_lds_alloc(struct r600_context *rctx,
702 struct radeon_winsys_cs *cs,
703 uint32_t lds_alloc);
704
705 /* r600_state_common.c */
706 void r600_init_common_state_functions(struct r600_context *rctx);
707 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
708 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
709 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
710 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
711 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
712 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
713 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
714 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
715 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
716 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
717 unsigned num_dw);
718 void r600_vertex_buffers_dirty(struct r600_context *rctx);
719 void r600_sampler_views_dirty(struct r600_context *rctx,
720 struct r600_samplerview_state *state);
721 void r600_sampler_states_dirty(struct r600_context *rctx,
722 struct r600_sampler_states *state);
723 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
724 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
725 uint32_t r600_translate_stencil_op(int s_op);
726 uint32_t r600_translate_fill(uint32_t func);
727 unsigned r600_tex_wrap(unsigned wrap);
728 unsigned r600_tex_mipfilter(unsigned filter);
729 unsigned r600_tex_compare(unsigned compare);
730 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
731 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
732 struct pipe_resource *texture,
733 const struct pipe_surface *templ,
734 unsigned width, unsigned height);
735 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
736 const unsigned char *swizzle_view,
737 boolean vtx);
738 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
739 const unsigned char *swizzle_view,
740 uint32_t *word4_p, uint32_t *yuv_format_p,
741 bool do_endian_swap);
742 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
743 bool do_endian_swap);
744 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
745
746 /* r600_uvd.c */
747 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
748 const struct pipe_video_codec *decoder);
749
750 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
751 const struct pipe_video_buffer *tmpl);
752
753 /*
754 * Helpers for building command buffers
755 */
756
757 #define PKT3_SET_CONFIG_REG 0x68
758 #define PKT3_SET_CONTEXT_REG 0x69
759 #define PKT3_SET_CTL_CONST 0x6F
760 #define PKT3_SET_LOOP_CONST 0x6C
761
762 #define R600_CONFIG_REG_OFFSET 0x08000
763 #define R600_CONTEXT_REG_OFFSET 0x28000
764 #define R600_CTL_CONST_OFFSET 0x3CFF0
765 #define R600_LOOP_CONST_OFFSET 0X0003E200
766 #define EG_LOOP_CONST_OFFSET 0x0003A200
767
768 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
769 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
770 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
771 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
772 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
773
774 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
775
776 /*Evergreen Compute packet3*/
777 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
778
779 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
780 {
781 cb->buf[cb->num_dw++] = value;
782 }
783
784 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
785 {
786 assert(cb->num_dw+num <= cb->max_num_dw);
787 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
788 cb->num_dw += num;
789 }
790
791 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
792 {
793 assert(reg < R600_CONTEXT_REG_OFFSET);
794 assert(cb->num_dw+2+num <= cb->max_num_dw);
795 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
796 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
797 }
798
799 /**
800 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
801 * shaders.
802 */
803 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
804 {
805 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
806 assert(cb->num_dw+2+num <= cb->max_num_dw);
807 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
808 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
809 }
810
811 /**
812 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
813 * shaders.
814 */
815 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
816 {
817 assert(reg >= R600_CTL_CONST_OFFSET);
818 assert(cb->num_dw+2+num <= cb->max_num_dw);
819 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
820 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
821 }
822
823 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
824 {
825 assert(reg >= R600_LOOP_CONST_OFFSET);
826 assert(cb->num_dw+2+num <= cb->max_num_dw);
827 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
828 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
829 }
830
831 /**
832 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
833 * shaders.
834 */
835 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
836 {
837 assert(reg >= EG_LOOP_CONST_OFFSET);
838 assert(cb->num_dw+2+num <= cb->max_num_dw);
839 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
840 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
841 }
842
843 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
844 {
845 r600_store_config_reg_seq(cb, reg, 1);
846 r600_store_value(cb, value);
847 }
848
849 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
850 {
851 r600_store_context_reg_seq(cb, reg, 1);
852 r600_store_value(cb, value);
853 }
854
855 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
856 {
857 r600_store_ctl_const_seq(cb, reg, 1);
858 r600_store_value(cb, value);
859 }
860
861 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
862 {
863 r600_store_loop_const_seq(cb, reg, 1);
864 r600_store_value(cb, value);
865 }
866
867 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
868 {
869 eg_store_loop_const_seq(cb, reg, 1);
870 r600_store_value(cb, value);
871 }
872
873 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
874 void r600_release_command_buffer(struct r600_command_buffer *cb);
875
876 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
877 {
878 radeon_set_context_reg_seq(cs, reg, num);
879 /* Set the compute bit on the packet header */
880 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
881 }
882
883 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
884 {
885 assert(reg >= R600_CTL_CONST_OFFSET);
886 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
887 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
888 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
889 }
890
891 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
892 {
893 radeon_compute_set_context_reg_seq(cs, reg, 1);
894 radeon_emit(cs, value);
895 }
896
897 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
898 {
899 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
900 radeon_compute_set_context_reg(cs, reg, value);
901 } else {
902 radeon_set_context_reg(cs, reg, value);
903 }
904 }
905
906 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
907 {
908 radeon_set_ctl_const_seq(cs, reg, 1);
909 radeon_emit(cs, value);
910 }
911
912 /*
913 * common helpers
914 */
915 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
916 {
917 return value * (1 << frac_bits);
918 }
919
920 /* 12.4 fixed-point */
921 static inline unsigned r600_pack_float_12p4(float x)
922 {
923 return x <= 0 ? 0 :
924 x >= 4096 ? 0xffff : x * 16;
925 }
926
927 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
928 static inline bool r600_can_read_depth(struct r600_texture *rtex)
929 {
930 return rtex->resource.b.b.nr_samples <= 1 &&
931 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
932 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
933 }
934
935 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
936 {
937 switch (coher) {
938 default:
939 case R600_COHERENCY_NONE:
940 return 0;
941 case R600_COHERENCY_SHADER:
942 return R600_CONTEXT_INV_CONST_CACHE |
943 R600_CONTEXT_INV_VERTEX_CACHE |
944 R600_CONTEXT_INV_TEX_CACHE |
945 R600_CONTEXT_STREAMOUT_FLUSH;
946 case R600_COHERENCY_CB_META:
947 return R600_CONTEXT_FLUSH_AND_INV_CB |
948 R600_CONTEXT_FLUSH_AND_INV_CB_META;
949 }
950 }
951
952 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
953 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
954 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
955
956 unsigned r600_conv_prim_to_gs_out(unsigned mode);
957 #endif