2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
35 #include "util/u_suballoc.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
39 #define R600_NUM_ATOMS 73
41 /* the number of CS dwords for flushing and drawing */
42 #define R600_MAX_FLUSH_CS_DWORDS 16
43 #define R600_MAX_DRAW_CS_DWORDS 40
44 #define R600_TRACE_CS_DWORDS 7
46 #define R600_MAX_USER_CONST_BUFFERS 13
47 #define R600_MAX_DRIVER_CONST_BUFFERS 4
48 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
50 /* start driver buffers after user buffers */
51 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
52 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
53 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
54 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3)
55 /* Currently R600_MAX_CONST_BUFFERS is too large, the hardware only has 16 buffers, but the driver is
56 * trying to use 17. Avoid accidentally aliasing with user UBOs for SAMPLE_POSITIONS by using an id<16.
57 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
59 * Fixing this properly would require the driver to combine its buffers into a single hardware buffer,
60 * which would also allow supporting the d3d 11 mandated minimum of 15 user const buffers.
62 #define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
64 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
66 #ifdef PIPE_ARCH_BIG_ENDIAN
67 #define R600_BIG_ENDIAN 1
69 #define R600_BIG_ENDIAN 0
74 struct r600_shader_key
;
76 /* This is an atom containing GPU commands that never change.
77 * This is supposed to be copied directly into the CS. */
78 struct r600_command_buffer
{
85 struct r600_db_state
{
86 struct r600_atom atom
;
87 struct r600_surface
*rsurf
;
90 struct r600_db_misc_state
{
91 struct r600_atom atom
;
92 bool occlusion_query_enabled
;
93 bool flush_depthstencil_through_cb
;
94 bool flush_depthstencil_in_place
;
95 bool copy_depth
, copy_stencil
;
98 unsigned db_shader_control
;
102 struct r600_cb_misc_state
{
103 struct r600_atom atom
;
104 unsigned cb_color_control
; /* this comes from blend state */
105 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
107 unsigned nr_ps_color_outputs
;
112 struct r600_clip_misc_state
{
113 struct r600_atom atom
;
114 unsigned pa_cl_clip_cntl
; /* from rasterizer */
115 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
116 unsigned clip_plane_enable
; /* from rasterizer */
117 unsigned clip_dist_write
; /* from vertex shader */
118 boolean clip_disable
; /* from vertex shader */
121 struct r600_alphatest_state
{
122 struct r600_atom atom
;
123 unsigned sx_alpha_test_control
; /* this comes from dsa state */
124 unsigned sx_alpha_ref
; /* this comes from dsa state */
126 bool cb0_export_16bpc
; /* from set_framebuffer_state */
129 struct r600_vgt_state
{
130 struct r600_atom atom
;
131 uint32_t vgt_multi_prim_ib_reset_en
;
132 uint32_t vgt_multi_prim_ib_reset_indx
;
133 uint32_t vgt_indx_offset
;
136 struct r600_blend_color
{
137 struct r600_atom atom
;
138 struct pipe_blend_color state
;
141 struct r600_clip_state
{
142 struct r600_atom atom
;
143 struct pipe_clip_state state
;
146 struct r600_cs_shader_state
{
147 struct r600_atom atom
;
148 unsigned kernel_index
;
149 struct r600_pipe_compute
*shader
;
152 struct r600_framebuffer
{
153 struct r600_atom atom
;
154 struct pipe_framebuffer_state state
;
155 unsigned compressed_cb_mask
;
159 bool is_msaa_resolve
;
162 struct r600_sample_mask
{
163 struct r600_atom atom
;
164 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
167 struct r600_config_state
{
168 struct r600_atom atom
;
169 unsigned sq_gpr_resource_mgmt_1
;
170 unsigned sq_gpr_resource_mgmt_2
;
173 struct r600_stencil_ref
180 struct r600_stencil_ref_state
{
181 struct r600_atom atom
;
182 struct r600_stencil_ref state
;
183 struct pipe_stencil_ref pipe_state
;
186 struct r600_viewport_state
{
187 struct r600_atom atom
;
188 struct pipe_viewport_state state
;
192 struct r600_shader_stages_state
{
193 struct r600_atom atom
;
194 unsigned geom_enable
;
197 struct r600_gs_rings_state
{
198 struct r600_atom atom
;
200 struct pipe_constant_buffer esgs_ring
;
201 struct pipe_constant_buffer gsvs_ring
;
204 /* This must start from 16. */
206 #define DBG_LLVM (1 << 29)
207 #define DBG_NO_CP_DMA (1 << 30)
209 #define DBG_NO_SB (1 << 21)
210 #define DBG_SB_CS (1 << 22)
211 #define DBG_SB_DRY_RUN (1 << 23)
212 #define DBG_SB_STAT (1 << 24)
213 #define DBG_SB_DUMP (1 << 25)
214 #define DBG_SB_NO_FALLBACK (1 << 26)
215 #define DBG_SB_DISASM (1 << 27)
216 #define DBG_SB_SAFEMATH (1 << 28)
219 struct r600_common_screen b
;
221 bool has_compressed_msaa_texturing
;
223 /*for compute global memory binding, we allocate stuff here, instead of
225 * XXX: Not sure if this is the best place for global_pool. Also,
226 * it's not thread safe, so it won't work with multiple contexts. */
227 struct compute_memory_pool
*global_pool
;
230 struct r600_pipe_sampler_view
{
231 struct pipe_sampler_view base
;
232 struct list_head list
;
233 struct r600_resource
*tex_resource
;
234 uint32_t tex_resource_words
[8];
235 bool skip_mip_address_reloc
;
238 struct r600_rasterizer_state
{
239 struct r600_command_buffer buffer
;
242 unsigned sprite_coord_enable
;
243 unsigned clip_plane_enable
;
244 unsigned pa_sc_line_stipple
;
245 unsigned pa_cl_clip_cntl
;
246 unsigned pa_su_sc_mode_cntl
;
251 bool multisample_enable
;
254 struct r600_poly_offset_state
{
255 struct r600_atom atom
;
256 enum pipe_format zs_format
;
261 struct r600_blend_state
{
262 struct r600_command_buffer buffer
;
263 struct r600_command_buffer buffer_no_blend
;
264 unsigned cb_target_mask
;
265 unsigned cb_color_control
;
266 unsigned cb_color_control_no_blend
;
271 struct r600_dsa_state
{
272 struct r600_command_buffer buffer
;
277 unsigned sx_alpha_test_control
;
280 struct r600_pipe_shader
;
282 struct r600_pipe_shader_selector
{
283 struct r600_pipe_shader
*current
;
285 struct tgsi_token
*tokens
;
286 struct pipe_stream_output_info so
;
288 unsigned num_shaders
;
290 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
293 unsigned nr_ps_max_color_exports
;
296 struct r600_pipe_sampler_state
{
297 uint32_t tex_sampler_words
[3];
298 union pipe_color_union border_color
;
299 bool border_color_use
;
300 bool seamless_cube_map
;
303 /* needed for blitter save */
304 #define NUM_TEX_UNITS 16
306 struct r600_seamless_cube_map
{
307 struct r600_atom atom
;
311 struct r600_samplerview_state
{
312 struct r600_atom atom
;
313 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
314 uint32_t enabled_mask
;
316 uint32_t compressed_depthtex_mask
; /* which textures are depth */
317 uint32_t compressed_colortex_mask
;
318 boolean dirty_txq_constants
;
319 boolean dirty_buffer_constants
;
322 struct r600_sampler_states
{
323 struct r600_atom atom
;
324 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
325 uint32_t enabled_mask
;
327 uint32_t has_bordercolor_mask
; /* which states contain the border color */
330 struct r600_textures_info
{
331 struct r600_samplerview_state views
;
332 struct r600_sampler_states states
;
333 bool is_array_sampler
[NUM_TEX_UNITS
];
335 /* cube array txq workaround */
336 uint32_t *txq_constants
;
337 /* buffer related workarounds */
338 uint32_t *buffer_constants
;
341 struct r600_constbuf_state
343 struct r600_atom atom
;
344 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
345 uint32_t enabled_mask
;
349 struct r600_vertexbuf_state
351 struct r600_atom atom
;
352 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
353 uint32_t enabled_mask
; /* non-NULL buffers */
357 /* CSO (constant state object, in other words, immutable state). */
358 struct r600_cso_state
360 struct r600_atom atom
;
361 void *cso
; /* e.g. r600_blend_state */
362 struct r600_command_buffer
*cb
;
365 struct r600_scissor_state
367 struct r600_atom atom
;
368 struct pipe_scissor_state scissor
;
369 bool enable
; /* r6xx only */
373 struct r600_fetch_shader
{
374 struct r600_resource
*buffer
;
378 struct r600_shader_state
{
379 struct r600_atom atom
;
380 struct r600_pipe_shader
*shader
;
383 struct r600_context
{
384 struct r600_common_context b
;
385 struct r600_screen
*screen
;
386 struct blitter_context
*blitter
;
387 struct u_suballocator
*allocator_fetch_shader
;
390 boolean has_vertex_cache
;
391 boolean keep_tiling_flags
;
392 unsigned default_ps_gprs
, default_vs_gprs
;
393 unsigned r6xx_num_clause_temp_gprs
;
395 /* Miscellaneous state objects. */
396 void *custom_dsa_flush
;
397 void *custom_blend_resolve
;
398 void *custom_blend_decompress
;
399 void *custom_blend_fastclear
;
400 /* With rasterizer discard, there doesn't have to be a pixel shader.
401 * In that case, we bind this one: */
402 void *dummy_pixel_shader
;
403 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
404 * bug where valid CMASK and FMASK are required to be present to avoid
405 * a hardlock in certain operations but aren't actually used
406 * for anything useful. */
407 struct r600_resource
*dummy_fmask
;
408 struct r600_resource
*dummy_cmask
;
410 /* State binding slots are here. */
411 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
412 /* States for CS initialization. */
413 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
414 /** Compute specific registers initializations. The start_cs_cmd atom
415 * must be emitted before start_compute_cs_cmd. */
416 struct r600_command_buffer start_compute_cs_cmd
;
417 /* Register states. */
418 struct r600_alphatest_state alphatest_state
;
419 struct r600_cso_state blend_state
;
420 struct r600_blend_color blend_color
;
421 struct r600_cb_misc_state cb_misc_state
;
422 struct r600_clip_misc_state clip_misc_state
;
423 struct r600_clip_state clip_state
;
424 struct r600_db_misc_state db_misc_state
;
425 struct r600_db_state db_state
;
426 struct r600_cso_state dsa_state
;
427 struct r600_framebuffer framebuffer
;
428 struct r600_poly_offset_state poly_offset_state
;
429 struct r600_cso_state rasterizer_state
;
430 struct r600_sample_mask sample_mask
;
431 struct r600_scissor_state scissor
[16];
432 struct r600_seamless_cube_map seamless_cube_map
;
433 struct r600_config_state config_state
;
434 struct r600_stencil_ref_state stencil_ref
;
435 struct r600_vgt_state vgt_state
;
436 struct r600_viewport_state viewport
[16];
437 /* Shaders and shader resources. */
438 struct r600_cso_state vertex_fetch_shader
;
439 struct r600_shader_state vertex_shader
;
440 struct r600_shader_state pixel_shader
;
441 struct r600_shader_state geometry_shader
;
442 struct r600_shader_state export_shader
;
443 struct r600_cs_shader_state cs_shader_state
;
444 struct r600_shader_stages_state shader_stages
;
445 struct r600_gs_rings_state gs_rings
;
446 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
447 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
448 /** Vertex buffers for fetch shaders */
449 struct r600_vertexbuf_state vertex_buffer_state
;
450 /** Vertex buffers for compute shaders */
451 struct r600_vertexbuf_state cs_vertex_buffer_state
;
453 /* Additional context states. */
454 unsigned compute_cb_target_mask
;
455 struct r600_pipe_shader_selector
*ps_shader
;
456 struct r600_pipe_shader_selector
*vs_shader
;
457 struct r600_pipe_shader_selector
*gs_shader
;
458 struct r600_rasterizer_state
*rasterizer
;
460 bool force_blend_disable
;
461 boolean dual_src_blend
;
466 struct pipe_index_buffer index_buffer
;
468 /* Last draw state (-1 = unset). */
469 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
470 int last_start_instance
;
473 struct r600_isa
*isa
;
476 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
477 struct r600_command_buffer
*cb
)
479 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
480 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
481 cs
->cdw
+= cb
->num_dw
;
484 void r600_trace_emit(struct r600_context
*rctx
);
486 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
488 atom
->emit(&rctx
->b
, atom
);
490 if (rctx
->screen
->b
.trace_bo
) {
491 r600_trace_emit(rctx
);
495 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
498 state
->atom
.dirty
= cso
!= NULL
;
501 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
502 struct r600_command_buffer
*cb
)
505 state
->atom
.num_dw
= cb
? cb
->num_dw
: 0;
506 r600_set_cso_state(state
, cso
);
509 /* compute_memory_pool.c */
510 struct compute_memory_pool
;
511 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
512 struct compute_memory_pool
* compute_memory_pool_new(
513 struct r600_screen
*rscreen
);
515 /* evergreen_compute.c */
516 void evergreen_set_cs_sampler_view(struct pipe_context
*ctx_
,
517 unsigned start_slot
, unsigned count
,
518 struct pipe_sampler_view
**views
);
520 /* evergreen_state.c */
521 struct pipe_sampler_view
*
522 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
523 struct pipe_resource
*texture
,
524 const struct pipe_sampler_view
*state
,
525 unsigned width0
, unsigned height0
,
526 unsigned force_level
);
527 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
528 enum chip_class ctx_chip_class
,
529 enum radeon_family ctx_family
,
531 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
532 enum chip_class ctx_chip_class
,
533 enum radeon_family ctx_family
,
536 void evergreen_init_state_functions(struct r600_context
*rctx
);
537 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
538 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
539 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
540 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
541 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
542 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
543 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
544 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
545 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
546 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
547 enum pipe_format format
,
548 enum pipe_texture_target target
,
549 unsigned sample_count
,
551 void evergreen_init_color_surface(struct r600_context
*rctx
,
552 struct r600_surface
*surf
);
553 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
554 struct r600_surface
*surf
);
555 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
558 void r600_init_blit_functions(struct r600_context
*rctx
);
559 void r600_decompress_depth_textures(struct r600_context
*rctx
,
560 struct r600_samplerview_state
*textures
);
561 void r600_decompress_color_textures(struct r600_context
*rctx
,
562 struct r600_samplerview_state
*textures
);
563 void r600_resource_copy_region(struct pipe_context
*ctx
,
564 struct pipe_resource
*dst
,
566 unsigned dstx
, unsigned dsty
, unsigned dstz
,
567 struct pipe_resource
*src
,
569 const struct pipe_box
*src_box
);
572 int r600_pipe_shader_create(struct pipe_context
*ctx
,
573 struct r600_pipe_shader
*shader
,
574 struct r600_shader_key key
);
576 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
579 struct pipe_sampler_view
*
580 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
581 struct pipe_resource
*texture
,
582 const struct pipe_sampler_view
*state
,
583 unsigned width_first_level
, unsigned height_first_level
);
584 void r600_init_state_functions(struct r600_context
*rctx
);
585 void r600_init_atom_start_cs(struct r600_context
*rctx
);
586 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
587 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
588 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
589 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
590 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
591 void *r600_create_resolve_blend(struct r600_context
*rctx
);
592 void *r700_create_resolve_blend(struct r600_context
*rctx
);
593 void *r600_create_decompress_blend(struct r600_context
*rctx
);
594 bool r600_adjust_gprs(struct r600_context
*rctx
);
595 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
596 enum pipe_format format
,
597 enum pipe_texture_target target
,
598 unsigned sample_count
,
600 void r600_update_db_shader_control(struct r600_context
* rctx
);
602 /* r600_hw_context.c */
603 void r600_context_gfx_flush(void *context
, unsigned flags
,
604 struct pipe_fence_handle
**fence
);
605 void r600_begin_new_cs(struct r600_context
*ctx
);
606 void r600_flush_emit(struct r600_context
*ctx
);
607 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
608 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
609 struct pipe_resource
*dst
, uint64_t dst_offset
,
610 struct pipe_resource
*src
, uint64_t src_offset
,
612 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
613 struct pipe_resource
*dst
, uint64_t offset
,
614 unsigned size
, uint32_t clear_value
);
615 void r600_dma_copy_buffer(struct r600_context
*rctx
,
616 struct pipe_resource
*dst
,
617 struct pipe_resource
*src
,
623 * evergreen_hw_context.c
625 void evergreen_dma_copy_buffer(struct r600_context
*rctx
,
626 struct pipe_resource
*dst
,
627 struct pipe_resource
*src
,
632 /* r600_state_common.c */
633 void r600_init_common_state_functions(struct r600_context
*rctx
);
634 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
635 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
636 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
637 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
638 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
639 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
640 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
641 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
642 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
643 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
645 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
646 void r600_sampler_views_dirty(struct r600_context
*rctx
,
647 struct r600_samplerview_state
*state
);
648 void r600_sampler_states_dirty(struct r600_context
*rctx
,
649 struct r600_sampler_states
*state
);
650 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
651 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
);
652 uint32_t r600_translate_stencil_op(int s_op
);
653 uint32_t r600_translate_fill(uint32_t func
);
654 unsigned r600_tex_wrap(unsigned wrap
);
655 unsigned r600_tex_filter(unsigned filter
);
656 unsigned r600_tex_mipfilter(unsigned filter
);
657 unsigned r600_tex_compare(unsigned compare
);
658 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
659 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
660 struct pipe_resource
*texture
,
661 const struct pipe_surface
*templ
,
662 unsigned width
, unsigned height
);
663 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
664 const unsigned char *swizzle_view
,
666 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
667 const unsigned char *swizzle_view
,
668 uint32_t *word4_p
, uint32_t *yuv_format_p
);
669 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
);
670 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
);
673 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
674 const struct pipe_video_codec
*decoder
);
676 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
677 const struct pipe_video_buffer
*tmpl
);
680 * Helpers for building command buffers
683 #define PKT3_SET_CONFIG_REG 0x68
684 #define PKT3_SET_CONTEXT_REG 0x69
685 #define PKT3_SET_CTL_CONST 0x6F
686 #define PKT3_SET_LOOP_CONST 0x6C
688 #define R600_CONFIG_REG_OFFSET 0x08000
689 #define R600_CONTEXT_REG_OFFSET 0x28000
690 #define R600_CTL_CONST_OFFSET 0x3CFF0
691 #define R600_LOOP_CONST_OFFSET 0X0003E200
692 #define EG_LOOP_CONST_OFFSET 0x0003A200
694 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
695 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
696 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
697 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
698 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
700 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
702 /*Evergreen Compute packet3*/
703 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
705 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
707 cb
->buf
[cb
->num_dw
++] = value
;
710 static INLINE
void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
712 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
713 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
717 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
719 assert(reg
< R600_CONTEXT_REG_OFFSET
);
720 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
721 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
722 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
726 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
729 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
731 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
732 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
733 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
734 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
738 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
741 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
743 assert(reg
>= R600_CTL_CONST_OFFSET
);
744 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
745 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
746 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
749 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
751 assert(reg
>= R600_LOOP_CONST_OFFSET
);
752 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
753 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
754 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
758 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
761 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
763 assert(reg
>= EG_LOOP_CONST_OFFSET
);
764 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
765 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
766 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
769 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
771 r600_store_config_reg_seq(cb
, reg
, 1);
772 r600_store_value(cb
, value
);
775 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
777 r600_store_context_reg_seq(cb
, reg
, 1);
778 r600_store_value(cb
, value
);
781 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
783 r600_store_ctl_const_seq(cb
, reg
, 1);
784 r600_store_value(cb
, value
);
787 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
789 r600_store_loop_const_seq(cb
, reg
, 1);
790 r600_store_value(cb
, value
);
793 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
795 eg_store_loop_const_seq(cb
, reg
, 1);
796 r600_store_value(cb
, value
);
799 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
800 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
802 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
804 r600_write_context_reg_seq(cs
, reg
, num
);
805 /* Set the compute bit on the packet header */
806 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
809 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
811 assert(reg
>= R600_CTL_CONST_OFFSET
);
812 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
813 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
814 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
817 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
819 r600_write_compute_context_reg_seq(cs
, reg
, 1);
820 radeon_emit(cs
, value
);
823 static INLINE
void r600_write_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
825 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
826 r600_write_compute_context_reg(cs
, reg
, value
);
828 r600_write_context_reg(cs
, reg
, value
);
832 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
834 r600_write_ctl_const_seq(cs
, reg
, 1);
835 radeon_emit(cs
, value
);
841 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
843 return value
* (1 << frac_bits
);
845 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
847 /* 12.4 fixed-point */
848 static INLINE
unsigned r600_pack_float_12p4(float x
)
851 x
>= 4096 ? 0xffff : x
* 16;
854 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
855 static INLINE
bool r600_can_read_depth(struct r600_texture
*rtex
)
857 return rtex
->resource
.b
.b
.nr_samples
<= 1 &&
858 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
859 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
);
862 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
863 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
864 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
866 static INLINE
unsigned r600_conv_prim_to_gs_out(unsigned mode
)
868 static const int prim_conv
[] = {
869 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
870 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
871 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
872 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
873 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
874 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
875 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
876 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
877 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
878 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
879 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
880 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
881 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
882 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
883 V_028A6C_OUTPRIM_TYPE_TRISTRIP
885 assert(mode
< Elements(prim_conv
));
887 return prim_conv
[mode
];