2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_pipe_state_id
{
52 R600_PIPE_STATE_BLEND
= 0,
53 R600_PIPE_STATE_BLEND_COLOR
,
54 R600_PIPE_STATE_CONFIG
,
55 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
57 R600_PIPE_STATE_SCISSOR
,
58 R600_PIPE_STATE_VIEWPORT
,
59 R600_PIPE_STATE_RASTERIZER
,
61 R600_PIPE_STATE_FRAMEBUFFER
,
63 R600_PIPE_STATE_STENCIL_REF
,
64 R600_PIPE_STATE_PS_SHADER
,
65 R600_PIPE_STATE_VS_SHADER
,
66 R600_PIPE_STATE_CONSTANT
,
67 R600_PIPE_STATE_SAMPLER
,
68 R600_PIPE_STATE_RESOURCE
,
69 R600_PIPE_STATE_POLYGON_OFFSET
,
70 R600_PIPE_STATE_FETCH_SHADER
,
74 struct r600_pipe_fences
{
75 struct r600_resource
*bo
;
78 /* linked list of preallocated blocks */
79 struct list_head blocks
;
80 /* linked list of freed fences */
81 struct list_head pool
;
86 struct pipe_screen screen
;
87 struct radeon_winsys
*ws
;
89 enum chip_class chip_class
;
90 struct radeon_info info
;
91 struct r600_tiling_info tiling_info
;
92 struct util_slab_mempool pool_buffers
;
93 struct r600_pipe_fences fences
;
95 unsigned num_contexts
;
97 /* for thread-safe write accessing to num_contexts */
98 pipe_mutex mutex_num_contexts
;
101 struct r600_pipe_sampler_view
{
102 struct pipe_sampler_view base
;
103 struct r600_pipe_resource_state state
;
106 struct r600_pipe_rasterizer
{
107 struct r600_pipe_state rstate
;
110 unsigned sprite_coord_enable
;
111 unsigned clip_plane_enable
;
112 unsigned pa_sc_line_stipple
;
113 unsigned pa_su_sc_mode_cntl
;
114 unsigned pa_cl_clip_cntl
;
119 struct r600_pipe_blend
{
120 struct r600_pipe_state rstate
;
121 unsigned cb_target_mask
;
122 unsigned cb_color_control
;
125 struct r600_pipe_dsa
{
126 struct r600_pipe_state rstate
;
132 struct r600_vertex_element
135 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
136 struct u_vbuf_elements
*vmgr_elements
;
137 struct r600_resource
*fetch_shader
;
139 struct r600_pipe_state rstate
;
140 /* if offset is to big for fetch instructio we need to alterate
141 * offset of vertex buffer, record here the offset need to add
143 unsigned vbuffer_need_offset
;
144 unsigned vbuffer_offset
[PIPE_MAX_ATTRIBS
];
147 struct r600_pipe_shader
{
148 struct r600_shader shader
;
149 struct r600_pipe_state rstate
;
150 struct r600_resource
*bo
;
151 struct r600_resource
*bo_fetch
;
152 struct r600_vertex_element vertex_elements
;
153 struct tgsi_token
*tokens
;
154 unsigned sprite_coord_enable
;
156 unsigned pa_cl_vs_out_cntl
;
157 struct pipe_stream_output_info so
;
160 struct r600_pipe_sampler_state
{
161 struct r600_pipe_state rstate
;
162 boolean seamless_cube_map
;
165 /* needed for blitter save */
166 #define NUM_TEX_UNITS 16
168 struct r600_textures_info
{
169 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
170 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
174 bool is_array_sampler
[NUM_TEX_UNITS
];
178 struct pipe_reference reference
;
179 unsigned index
; /* in the shared bo */
180 struct list_head head
;
183 #define FENCE_BLOCK_SIZE 16
185 struct r600_fence_block
{
186 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
187 struct list_head head
;
190 #define R600_CONSTANT_ARRAY_SIZE 256
191 #define R600_RESOURCE_ARRAY_SIZE 160
193 struct r600_stencil_ref
200 struct r600_pipe_context
{
201 struct pipe_context context
;
202 struct blitter_context
*blitter
;
203 enum radeon_family family
;
204 enum chip_class chip_class
;
205 unsigned r6xx_num_clause_temp_gprs
;
206 void *custom_dsa_flush
;
207 struct r600_screen
*screen
;
208 struct radeon_winsys
*ws
;
209 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
210 struct r600_context ctx
;
211 struct r600_vertex_element
*vertex_elements
;
212 struct r600_pipe_resource_state fs_resource
[PIPE_MAX_ATTRIBS
];
213 struct pipe_framebuffer_state framebuffer
;
214 unsigned cb_target_mask
;
215 unsigned cb_color_control
;
216 unsigned pa_sc_line_stipple
;
217 unsigned pa_su_sc_mode_cntl
;
218 unsigned pa_cl_clip_cntl
;
219 /* for saving when using blitter */
220 struct pipe_stencil_ref stencil_ref
;
221 struct pipe_viewport_state viewport
;
222 struct pipe_clip_state clip
;
223 struct r600_pipe_state config
;
224 struct r600_pipe_shader
*ps_shader
;
225 struct r600_pipe_shader
*vs_shader
;
226 struct r600_pipe_state vs_const_buffer
;
227 struct r600_pipe_resource_state vs_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
228 struct r600_pipe_state ps_const_buffer
;
229 struct r600_pipe_resource_state ps_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
230 struct r600_pipe_rasterizer
*rasterizer
;
231 struct r600_pipe_state vgt
;
232 struct r600_pipe_state spi
;
233 struct pipe_query
*current_render_cond
;
234 unsigned current_render_cond_mode
;
235 struct pipe_query
*saved_render_cond
;
236 unsigned saved_render_cond_mode
;
237 /* shader information */
239 unsigned sprite_coord_enable
;
240 boolean export_16bpc
;
242 boolean alpha_ref_dirty
;
244 struct r600_textures_info vs_samplers
;
245 struct r600_textures_info ps_samplers
;
247 struct u_vbuf
*vbuf_mgr
;
248 struct util_slab_mempool pool_transfers
;
249 boolean have_depth_texture
, have_depth_fb
;
251 unsigned default_ps_gprs
, default_vs_gprs
;
254 /* evergreen_state.c */
255 void evergreen_init_state_functions(struct r600_pipe_context
*rctx
);
256 void evergreen_init_config(struct r600_pipe_context
*rctx
);
257 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
258 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
259 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
260 void *evergreen_create_db_flush_dsa(struct r600_pipe_context
*rctx
);
261 void evergreen_polygon_offset_update(struct r600_pipe_context
*rctx
);
262 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
263 struct r600_pipe_resource_state
*rstate
);
264 void evergreen_pipe_mod_buffer_resource(struct pipe_context
*ctx
,
265 struct r600_pipe_resource_state
*rstate
,
266 struct r600_resource
*rbuffer
,
267 unsigned offset
, unsigned stride
,
268 enum radeon_bo_usage usage
);
269 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
270 enum pipe_format format
,
271 enum pipe_texture_target target
,
272 unsigned sample_count
,
276 void r600_init_blit_functions(struct r600_pipe_context
*rctx
);
277 void r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
278 void r600_blit_push_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
279 void r600_flush_depth_textures(struct r600_pipe_context
*rctx
);
282 bool r600_init_resource(struct r600_screen
*rscreen
,
283 struct r600_resource
*res
,
284 unsigned size
, unsigned alignment
,
285 unsigned bind
, unsigned usage
);
286 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
287 const struct pipe_resource
*templ
);
288 struct pipe_resource
*r600_user_buffer_create(struct pipe_screen
*screen
,
289 void *ptr
, unsigned bytes
,
291 void r600_upload_index_buffer(struct r600_pipe_context
*rctx
,
292 struct pipe_index_buffer
*ib
, unsigned count
);
296 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
300 void r600_init_query_functions(struct r600_pipe_context
*rctx
);
302 /* r600_resource.c */
303 void r600_init_context_resource_functions(struct r600_pipe_context
*r600
);
306 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
307 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
308 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
309 struct r600_shader
*ps
, int id
);
312 void r600_update_sampler_states(struct r600_pipe_context
*rctx
);
313 void r600_init_state_functions(struct r600_pipe_context
*rctx
);
314 void r600_init_config(struct r600_pipe_context
*rctx
);
315 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
316 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
317 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
318 void *r600_create_db_flush_dsa(struct r600_pipe_context
*rctx
);
319 void r600_polygon_offset_update(struct r600_pipe_context
*rctx
);
320 void r600_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
321 struct r600_pipe_resource_state
*rstate
);
322 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
323 struct r600_resource
*rbuffer
,
324 unsigned offset
, unsigned stride
,
325 enum radeon_bo_usage usage
);
326 void r600_adjust_gprs(struct r600_pipe_context
*rctx
);
327 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
328 enum pipe_format format
,
329 enum pipe_texture_target target
,
330 unsigned sample_count
,
334 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
335 void r600_init_surface_functions(struct r600_pipe_context
*r600
);
336 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
337 const unsigned char *swizzle_view
,
338 uint32_t *word4_p
, uint32_t *yuv_format_p
);
339 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
340 unsigned level
, unsigned layer
);
342 /* r600_translate.c */
343 void r600_translate_index_buffer(struct r600_pipe_context
*r600
,
344 struct pipe_index_buffer
*ib
,
347 /* r600_state_common.c */
348 void r600_set_index_buffer(struct pipe_context
*ctx
,
349 const struct pipe_index_buffer
*ib
);
350 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
351 const struct pipe_vertex_buffer
*buffers
);
352 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
354 const struct pipe_vertex_element
*elements
);
355 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
356 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
357 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
358 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
359 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
360 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
361 struct pipe_sampler_view
*state
);
362 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
363 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
364 void *r600_create_shader_state(struct pipe_context
*ctx
,
365 const struct pipe_shader_state
*state
);
366 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
367 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
368 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
369 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
370 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
371 struct pipe_resource
*buffer
);
372 struct pipe_stream_output_target
*
373 r600_create_so_target(struct pipe_context
*ctx
,
374 struct pipe_resource
*buffer
,
375 unsigned buffer_offset
,
376 unsigned buffer_size
);
377 void r600_so_target_destroy(struct pipe_context
*ctx
,
378 struct pipe_stream_output_target
*target
);
379 void r600_set_so_targets(struct pipe_context
*ctx
,
380 unsigned num_targets
,
381 struct pipe_stream_output_target
**targets
,
382 unsigned append_bitmask
);
383 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
384 const struct pipe_stencil_ref
*state
);
385 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
390 static INLINE u32
S_FIXED(float value
, u32 frac_bits
)
392 return value
* (1 << frac_bits
);
394 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
396 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
398 if (filter
<= 1) return 0;
399 if (filter
<= 2) return 1;
400 if (filter
<= 4) return 2;
401 if (filter
<= 8) return 3;
405 /* 12.4 fixed-point */
406 static INLINE
unsigned r600_pack_float_12p4(float x
)
409 x
>= 4096 ? 0xffff : x
* 16;