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r600: SMX returns CONTEXT_DONE early workaround
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 43
42
43 #define R600_MAX_VIEWPORTS 16
44
45 /* read caches */
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
59
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 52
63 #define R600_TRACE_CS_DWORDS 7
64
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 2
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
68
69 /* start driver buffers after user buffers */
70 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_UCP_SIZE (4*4*8)
72 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
73
74 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
75 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
76 * of 16 const buffers.
77 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
78 *
79 * In order to support d3d 11 mandated minimum of 15 user const buffers
80 * we'd have to squash all use cases into one driver buffer.
81 */
82 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
83
84 #ifdef PIPE_ARCH_BIG_ENDIAN
85 #define R600_BIG_ENDIAN 1
86 #else
87 #define R600_BIG_ENDIAN 0
88 #endif
89
90 struct r600_context;
91 struct r600_bytecode;
92 union r600_shader_key;
93
94 /* This is an atom containing GPU commands that never change.
95 * This is supposed to be copied directly into the CS. */
96 struct r600_command_buffer {
97 uint32_t *buf;
98 unsigned num_dw;
99 unsigned max_num_dw;
100 unsigned pkt_flags;
101 };
102
103 struct r600_db_state {
104 struct r600_atom atom;
105 struct r600_surface *rsurf;
106 };
107
108 struct r600_db_misc_state {
109 struct r600_atom atom;
110 bool occlusion_query_enabled;
111 bool flush_depthstencil_through_cb;
112 bool flush_depth_inplace;
113 bool flush_stencil_inplace;
114 bool copy_depth, copy_stencil;
115 unsigned copy_sample;
116 unsigned log_samples;
117 unsigned db_shader_control;
118 bool htile_clear;
119 uint8_t ps_conservative_z;
120 };
121
122 struct r600_cb_misc_state {
123 struct r600_atom atom;
124 unsigned cb_color_control; /* this comes from blend state */
125 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
126 unsigned nr_cbufs;
127 unsigned nr_ps_color_outputs;
128 bool multiwrite;
129 bool dual_src_blend;
130 };
131
132 struct r600_clip_misc_state {
133 struct r600_atom atom;
134 unsigned pa_cl_clip_cntl; /* from rasterizer */
135 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
136 unsigned clip_plane_enable; /* from rasterizer */
137 unsigned clip_dist_write; /* from vertex shader */
138 boolean clip_disable; /* from vertex shader */
139 };
140
141 struct r600_alphatest_state {
142 struct r600_atom atom;
143 unsigned sx_alpha_test_control; /* this comes from dsa state */
144 unsigned sx_alpha_ref; /* this comes from dsa state */
145 bool bypass;
146 bool cb0_export_16bpc; /* from set_framebuffer_state */
147 };
148
149 struct r600_vgt_state {
150 struct r600_atom atom;
151 uint32_t vgt_multi_prim_ib_reset_en;
152 uint32_t vgt_multi_prim_ib_reset_indx;
153 uint32_t vgt_indx_offset;
154 bool last_draw_was_indirect;
155 };
156
157 struct r600_blend_color {
158 struct r600_atom atom;
159 struct pipe_blend_color state;
160 };
161
162 struct r600_clip_state {
163 struct r600_atom atom;
164 struct pipe_clip_state state;
165 };
166
167 struct r600_cs_shader_state {
168 struct r600_atom atom;
169 unsigned kernel_index;
170 unsigned pc;
171 struct r600_pipe_compute *shader;
172 };
173
174 struct r600_framebuffer {
175 struct r600_atom atom;
176 struct pipe_framebuffer_state state;
177 unsigned compressed_cb_mask;
178 unsigned nr_samples;
179 bool export_16bpc;
180 bool cb0_is_integer;
181 bool is_msaa_resolve;
182 };
183
184 struct r600_sample_mask {
185 struct r600_atom atom;
186 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
187 };
188
189 struct r600_config_state {
190 struct r600_atom atom;
191 unsigned sq_gpr_resource_mgmt_1;
192 unsigned sq_gpr_resource_mgmt_2;
193 };
194
195 struct r600_stencil_ref
196 {
197 ubyte ref_value[2];
198 ubyte valuemask[2];
199 ubyte writemask[2];
200 };
201
202 struct r600_stencil_ref_state {
203 struct r600_atom atom;
204 struct r600_stencil_ref state;
205 struct pipe_stencil_ref pipe_state;
206 };
207
208 struct r600_viewport_state {
209 struct r600_atom atom;
210 struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
211 uint32_t dirty_mask;
212 };
213
214 struct r600_shader_stages_state {
215 struct r600_atom atom;
216 unsigned geom_enable;
217 };
218
219 struct r600_gs_rings_state {
220 struct r600_atom atom;
221 unsigned enable;
222 struct pipe_constant_buffer esgs_ring;
223 struct pipe_constant_buffer gsvs_ring;
224 };
225
226 /* This must start from 16. */
227 /* features */
228 #define DBG_LLVM (1 << 29)
229 #define DBG_NO_CP_DMA (1 << 30)
230 /* shader backend */
231 #define DBG_NO_SB (1 << 21)
232 #define DBG_SB_CS (1 << 22)
233 #define DBG_SB_DRY_RUN (1 << 23)
234 #define DBG_SB_STAT (1 << 24)
235 #define DBG_SB_DUMP (1 << 25)
236 #define DBG_SB_NO_FALLBACK (1 << 26)
237 #define DBG_SB_DISASM (1 << 27)
238 #define DBG_SB_SAFEMATH (1 << 28)
239
240 struct r600_screen {
241 struct r600_common_screen b;
242 bool has_msaa;
243 bool has_compressed_msaa_texturing;
244
245 /*for compute global memory binding, we allocate stuff here, instead of
246 * buffers.
247 * XXX: Not sure if this is the best place for global_pool. Also,
248 * it's not thread safe, so it won't work with multiple contexts. */
249 struct compute_memory_pool *global_pool;
250 };
251
252 struct r600_pipe_sampler_view {
253 struct pipe_sampler_view base;
254 struct list_head list;
255 struct r600_resource *tex_resource;
256 uint32_t tex_resource_words[8];
257 bool skip_mip_address_reloc;
258 bool is_stencil_sampler;
259 };
260
261 struct r600_rasterizer_state {
262 struct r600_command_buffer buffer;
263 boolean flatshade;
264 boolean two_side;
265 unsigned sprite_coord_enable;
266 unsigned clip_plane_enable;
267 unsigned pa_sc_line_stipple;
268 unsigned pa_cl_clip_cntl;
269 unsigned pa_su_sc_mode_cntl;
270 float offset_units;
271 float offset_scale;
272 bool offset_enable;
273 bool scissor_enable;
274 bool multisample_enable;
275 };
276
277 struct r600_poly_offset_state {
278 struct r600_atom atom;
279 enum pipe_format zs_format;
280 float offset_units;
281 float offset_scale;
282 };
283
284 struct r600_blend_state {
285 struct r600_command_buffer buffer;
286 struct r600_command_buffer buffer_no_blend;
287 unsigned cb_target_mask;
288 unsigned cb_color_control;
289 unsigned cb_color_control_no_blend;
290 bool dual_src_blend;
291 bool alpha_to_one;
292 };
293
294 struct r600_dsa_state {
295 struct r600_command_buffer buffer;
296 unsigned alpha_ref;
297 ubyte valuemask[2];
298 ubyte writemask[2];
299 unsigned zwritemask;
300 unsigned sx_alpha_test_control;
301 };
302
303 struct r600_pipe_shader;
304
305 struct r600_pipe_shader_selector {
306 struct r600_pipe_shader *current;
307
308 struct tgsi_token *tokens;
309 struct pipe_stream_output_info so;
310 struct tgsi_shader_info info;
311
312 unsigned num_shaders;
313
314 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
315 unsigned type;
316
317 /* geometry shader properties */
318 unsigned gs_output_prim;
319 unsigned gs_max_out_vertices;
320 unsigned gs_num_invocations;
321
322 unsigned nr_ps_max_color_exports;
323 };
324
325 struct r600_pipe_sampler_state {
326 uint32_t tex_sampler_words[3];
327 union pipe_color_union border_color;
328 bool border_color_use;
329 bool seamless_cube_map;
330 };
331
332 /* needed for blitter save */
333 #define NUM_TEX_UNITS 16
334
335 struct r600_seamless_cube_map {
336 struct r600_atom atom;
337 bool enabled;
338 };
339
340 struct r600_samplerview_state {
341 struct r600_atom atom;
342 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
343 uint32_t enabled_mask;
344 uint32_t dirty_mask;
345 uint32_t compressed_depthtex_mask; /* which textures are depth */
346 uint32_t compressed_colortex_mask;
347 boolean dirty_buffer_constants;
348 };
349
350 struct r600_sampler_states {
351 struct r600_atom atom;
352 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
353 uint32_t enabled_mask;
354 uint32_t dirty_mask;
355 uint32_t has_bordercolor_mask; /* which states contain the border color */
356 };
357
358 struct r600_textures_info {
359 struct r600_samplerview_state views;
360 struct r600_sampler_states states;
361 bool is_array_sampler[NUM_TEX_UNITS];
362 };
363
364 struct r600_shader_driver_constants_info {
365 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
366 uint32_t *constants;
367 uint32_t alloc_size;
368 bool vs_ucp_dirty;
369 bool texture_const_dirty;
370 bool ps_sample_pos_dirty;
371 };
372
373 struct r600_constbuf_state
374 {
375 struct r600_atom atom;
376 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
377 uint32_t enabled_mask;
378 uint32_t dirty_mask;
379 };
380
381 struct r600_vertexbuf_state
382 {
383 struct r600_atom atom;
384 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
385 uint32_t enabled_mask; /* non-NULL buffers */
386 uint32_t dirty_mask;
387 };
388
389 /* CSO (constant state object, in other words, immutable state). */
390 struct r600_cso_state
391 {
392 struct r600_atom atom;
393 void *cso; /* e.g. r600_blend_state */
394 struct r600_command_buffer *cb;
395 };
396
397 struct r600_scissor_state
398 {
399 struct r600_atom atom;
400 struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
401 uint32_t dirty_mask;
402 bool enable; /* r6xx only */
403 };
404
405 struct r600_fetch_shader {
406 struct r600_resource *buffer;
407 unsigned offset;
408 };
409
410 struct r600_shader_state {
411 struct r600_atom atom;
412 struct r600_pipe_shader *shader;
413 };
414
415 struct r600_context {
416 struct r600_common_context b;
417 struct r600_screen *screen;
418 struct blitter_context *blitter;
419 struct u_suballocator *allocator_fetch_shader;
420
421 /* Hardware info. */
422 boolean has_vertex_cache;
423 boolean keep_tiling_flags;
424 unsigned default_ps_gprs, default_vs_gprs;
425 unsigned r6xx_num_clause_temp_gprs;
426
427 /* Miscellaneous state objects. */
428 void *custom_dsa_flush;
429 void *custom_blend_resolve;
430 void *custom_blend_decompress;
431 void *custom_blend_fastclear;
432 /* With rasterizer discard, there doesn't have to be a pixel shader.
433 * In that case, we bind this one: */
434 void *dummy_pixel_shader;
435 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
436 * bug where valid CMASK and FMASK are required to be present to avoid
437 * a hardlock in certain operations but aren't actually used
438 * for anything useful. */
439 struct r600_resource *dummy_fmask;
440 struct r600_resource *dummy_cmask;
441
442 /* State binding slots are here. */
443 struct r600_atom *atoms[R600_NUM_ATOMS];
444 /* Dirty atom bitmask for fast tests */
445 uint64_t dirty_atoms;
446 /* States for CS initialization. */
447 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
448 /** Compute specific registers initializations. The start_cs_cmd atom
449 * must be emitted before start_compute_cs_cmd. */
450 struct r600_command_buffer start_compute_cs_cmd;
451 /* Register states. */
452 struct r600_alphatest_state alphatest_state;
453 struct r600_cso_state blend_state;
454 struct r600_blend_color blend_color;
455 struct r600_cb_misc_state cb_misc_state;
456 struct r600_clip_misc_state clip_misc_state;
457 struct r600_clip_state clip_state;
458 struct r600_db_misc_state db_misc_state;
459 struct r600_db_state db_state;
460 struct r600_cso_state dsa_state;
461 struct r600_framebuffer framebuffer;
462 struct r600_poly_offset_state poly_offset_state;
463 struct r600_cso_state rasterizer_state;
464 struct r600_sample_mask sample_mask;
465 struct r600_scissor_state scissor;
466 struct r600_seamless_cube_map seamless_cube_map;
467 struct r600_config_state config_state;
468 struct r600_stencil_ref_state stencil_ref;
469 struct r600_vgt_state vgt_state;
470 struct r600_viewport_state viewport;
471 /* Shaders and shader resources. */
472 struct r600_cso_state vertex_fetch_shader;
473 struct r600_shader_state vertex_shader;
474 struct r600_shader_state pixel_shader;
475 struct r600_shader_state geometry_shader;
476 struct r600_shader_state export_shader;
477 struct r600_cs_shader_state cs_shader_state;
478 struct r600_shader_stages_state shader_stages;
479 struct r600_gs_rings_state gs_rings;
480 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
481 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
482
483 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
484
485 /** Vertex buffers for fetch shaders */
486 struct r600_vertexbuf_state vertex_buffer_state;
487 /** Vertex buffers for compute shaders */
488 struct r600_vertexbuf_state cs_vertex_buffer_state;
489
490 /* Additional context states. */
491 unsigned compute_cb_target_mask;
492 struct r600_pipe_shader_selector *ps_shader;
493 struct r600_pipe_shader_selector *vs_shader;
494 struct r600_pipe_shader_selector *gs_shader;
495 struct r600_rasterizer_state *rasterizer;
496 bool alpha_to_one;
497 bool force_blend_disable;
498 boolean dual_src_blend;
499 unsigned zwritemask;
500 int ps_iter_samples;
501
502 /* Index buffer. */
503 struct pipe_index_buffer index_buffer;
504
505 /* Last draw state (-1 = unset). */
506 int last_primitive_type; /* Last primitive type used in draw_vbo. */
507 int last_start_instance;
508
509 void *sb_context;
510 struct r600_isa *isa;
511 float sample_positions[4 * 16];
512 };
513
514 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
515 struct r600_command_buffer *cb)
516 {
517 assert(cs->cdw + cb->num_dw <= cs->max_dw);
518 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
519 cs->cdw += cb->num_dw;
520 }
521
522 static inline void r600_set_atom_dirty(struct r600_context *rctx,
523 struct r600_atom *atom,
524 bool dirty)
525 {
526 uint64_t mask;
527
528 assert(atom->id != 0);
529 assert(atom->id < sizeof(mask) * 8);
530 mask = 1ull << atom->id;
531 if (dirty)
532 rctx->dirty_atoms |= mask;
533 else
534 rctx->dirty_atoms &= ~mask;
535 }
536
537 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
538 struct r600_atom *atom)
539 {
540 r600_set_atom_dirty(rctx, atom, true);
541 }
542
543 void r600_trace_emit(struct r600_context *rctx);
544
545 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
546 {
547 atom->emit(&rctx->b, atom);
548 r600_set_atom_dirty(rctx, atom, false);
549 if (rctx->screen->b.trace_bo) {
550 r600_trace_emit(rctx);
551 }
552 }
553
554 static inline void r600_set_cso_state(struct r600_context *rctx,
555 struct r600_cso_state *state, void *cso)
556 {
557 state->cso = cso;
558 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
559 }
560
561 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
562 struct r600_cso_state *state, void *cso,
563 struct r600_command_buffer *cb)
564 {
565 state->cb = cb;
566 state->atom.num_dw = cb ? cb->num_dw : 0;
567 r600_set_cso_state(rctx, state, cso);
568 }
569
570 /* compute_memory_pool.c */
571 struct compute_memory_pool;
572 void compute_memory_pool_delete(struct compute_memory_pool* pool);
573 struct compute_memory_pool* compute_memory_pool_new(
574 struct r600_screen *rscreen);
575
576 /* evergreen_state.c */
577 struct pipe_sampler_view *
578 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
579 struct pipe_resource *texture,
580 const struct pipe_sampler_view *state,
581 unsigned width0, unsigned height0,
582 unsigned force_level);
583 void evergreen_init_common_regs(struct r600_command_buffer *cb,
584 enum chip_class ctx_chip_class,
585 enum radeon_family ctx_family,
586 int ctx_drm_minor);
587 void cayman_init_common_regs(struct r600_command_buffer *cb,
588 enum chip_class ctx_chip_class,
589 enum radeon_family ctx_family,
590 int ctx_drm_minor);
591
592 void evergreen_init_state_functions(struct r600_context *rctx);
593 void evergreen_init_atom_start_cs(struct r600_context *rctx);
594 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
595 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
596 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
597 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
598 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
599 void *evergreen_create_resolve_blend(struct r600_context *rctx);
600 void *evergreen_create_decompress_blend(struct r600_context *rctx);
601 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
602 boolean evergreen_is_format_supported(struct pipe_screen *screen,
603 enum pipe_format format,
604 enum pipe_texture_target target,
605 unsigned sample_count,
606 unsigned usage);
607 void evergreen_init_color_surface(struct r600_context *rctx,
608 struct r600_surface *surf);
609 void evergreen_init_color_surface_rat(struct r600_context *rctx,
610 struct r600_surface *surf);
611 void evergreen_update_db_shader_control(struct r600_context * rctx);
612
613 /* r600_blit.c */
614 void r600_init_blit_functions(struct r600_context *rctx);
615 void r600_decompress_depth_textures(struct r600_context *rctx,
616 struct r600_samplerview_state *textures);
617 void r600_decompress_color_textures(struct r600_context *rctx,
618 struct r600_samplerview_state *textures);
619 void r600_resource_copy_region(struct pipe_context *ctx,
620 struct pipe_resource *dst,
621 unsigned dst_level,
622 unsigned dstx, unsigned dsty, unsigned dstz,
623 struct pipe_resource *src,
624 unsigned src_level,
625 const struct pipe_box *src_box);
626
627 /* r600_shader.c */
628 int r600_pipe_shader_create(struct pipe_context *ctx,
629 struct r600_pipe_shader *shader,
630 union r600_shader_key key);
631
632 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
633
634 /* r600_state.c */
635 struct pipe_sampler_view *
636 r600_create_sampler_view_custom(struct pipe_context *ctx,
637 struct pipe_resource *texture,
638 const struct pipe_sampler_view *state,
639 unsigned width_first_level, unsigned height_first_level);
640 void r600_init_state_functions(struct r600_context *rctx);
641 void r600_init_atom_start_cs(struct r600_context *rctx);
642 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
643 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
644 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
645 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
646 void *r600_create_db_flush_dsa(struct r600_context *rctx);
647 void *r600_create_resolve_blend(struct r600_context *rctx);
648 void *r700_create_resolve_blend(struct r600_context *rctx);
649 void *r600_create_decompress_blend(struct r600_context *rctx);
650 bool r600_adjust_gprs(struct r600_context *rctx);
651 boolean r600_is_format_supported(struct pipe_screen *screen,
652 enum pipe_format format,
653 enum pipe_texture_target target,
654 unsigned sample_count,
655 unsigned usage);
656 void r600_update_db_shader_control(struct r600_context * rctx);
657
658 /* r600_hw_context.c */
659 void r600_context_gfx_flush(void *context, unsigned flags,
660 struct pipe_fence_handle **fence);
661 void r600_begin_new_cs(struct r600_context *ctx);
662 void r600_flush_emit(struct r600_context *ctx);
663 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
664 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
665 struct pipe_resource *dst, uint64_t dst_offset,
666 struct pipe_resource *src, uint64_t src_offset,
667 unsigned size);
668 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
669 struct pipe_resource *dst, uint64_t offset,
670 unsigned size, uint32_t clear_value);
671 void r600_dma_copy_buffer(struct r600_context *rctx,
672 struct pipe_resource *dst,
673 struct pipe_resource *src,
674 uint64_t dst_offset,
675 uint64_t src_offset,
676 uint64_t size);
677
678 /*
679 * evergreen_hw_context.c
680 */
681 void evergreen_dma_copy_buffer(struct r600_context *rctx,
682 struct pipe_resource *dst,
683 struct pipe_resource *src,
684 uint64_t dst_offset,
685 uint64_t src_offset,
686 uint64_t size);
687
688 /* r600_state_common.c */
689 void r600_init_common_state_functions(struct r600_context *rctx);
690 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
691 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
692 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
693 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
694 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
695 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
696 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
697 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
698 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
699 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
700 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
701 unsigned num_dw);
702 void r600_vertex_buffers_dirty(struct r600_context *rctx);
703 void r600_sampler_views_dirty(struct r600_context *rctx,
704 struct r600_samplerview_state *state);
705 void r600_sampler_states_dirty(struct r600_context *rctx,
706 struct r600_sampler_states *state);
707 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
708 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
709 uint32_t r600_translate_stencil_op(int s_op);
710 uint32_t r600_translate_fill(uint32_t func);
711 unsigned r600_tex_wrap(unsigned wrap);
712 unsigned r600_tex_filter(unsigned filter);
713 unsigned r600_tex_mipfilter(unsigned filter);
714 unsigned r600_tex_compare(unsigned compare);
715 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
716 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
717 struct pipe_resource *texture,
718 const struct pipe_surface *templ,
719 unsigned width, unsigned height);
720 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
721 const unsigned char *swizzle_view,
722 boolean vtx);
723 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
724 const unsigned char *swizzle_view,
725 uint32_t *word4_p, uint32_t *yuv_format_p);
726 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
727 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
728
729 /* r600_uvd.c */
730 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
731 const struct pipe_video_codec *decoder);
732
733 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
734 const struct pipe_video_buffer *tmpl);
735
736 /*
737 * Helpers for building command buffers
738 */
739
740 #define PKT3_SET_CONFIG_REG 0x68
741 #define PKT3_SET_CONTEXT_REG 0x69
742 #define PKT3_SET_CTL_CONST 0x6F
743 #define PKT3_SET_LOOP_CONST 0x6C
744
745 #define R600_CONFIG_REG_OFFSET 0x08000
746 #define R600_CONTEXT_REG_OFFSET 0x28000
747 #define R600_CTL_CONST_OFFSET 0x3CFF0
748 #define R600_LOOP_CONST_OFFSET 0X0003E200
749 #define EG_LOOP_CONST_OFFSET 0x0003A200
750
751 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
752 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
753 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
754 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
755 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
756
757 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
758
759 /*Evergreen Compute packet3*/
760 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
761
762 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
763 {
764 cb->buf[cb->num_dw++] = value;
765 }
766
767 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
768 {
769 assert(cb->num_dw+num <= cb->max_num_dw);
770 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
771 cb->num_dw += num;
772 }
773
774 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
775 {
776 assert(reg < R600_CONTEXT_REG_OFFSET);
777 assert(cb->num_dw+2+num <= cb->max_num_dw);
778 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
779 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
780 }
781
782 /**
783 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
784 * shaders.
785 */
786 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
787 {
788 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
789 assert(cb->num_dw+2+num <= cb->max_num_dw);
790 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
791 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
792 }
793
794 /**
795 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
796 * shaders.
797 */
798 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
799 {
800 assert(reg >= R600_CTL_CONST_OFFSET);
801 assert(cb->num_dw+2+num <= cb->max_num_dw);
802 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
803 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
804 }
805
806 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
807 {
808 assert(reg >= R600_LOOP_CONST_OFFSET);
809 assert(cb->num_dw+2+num <= cb->max_num_dw);
810 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
811 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
812 }
813
814 /**
815 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
816 * shaders.
817 */
818 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
819 {
820 assert(reg >= EG_LOOP_CONST_OFFSET);
821 assert(cb->num_dw+2+num <= cb->max_num_dw);
822 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
823 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
824 }
825
826 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
827 {
828 r600_store_config_reg_seq(cb, reg, 1);
829 r600_store_value(cb, value);
830 }
831
832 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
833 {
834 r600_store_context_reg_seq(cb, reg, 1);
835 r600_store_value(cb, value);
836 }
837
838 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
839 {
840 r600_store_ctl_const_seq(cb, reg, 1);
841 r600_store_value(cb, value);
842 }
843
844 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
845 {
846 r600_store_loop_const_seq(cb, reg, 1);
847 r600_store_value(cb, value);
848 }
849
850 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
851 {
852 eg_store_loop_const_seq(cb, reg, 1);
853 r600_store_value(cb, value);
854 }
855
856 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
857 void r600_release_command_buffer(struct r600_command_buffer *cb);
858
859 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
860 {
861 radeon_set_context_reg_seq(cs, reg, num);
862 /* Set the compute bit on the packet header */
863 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
864 }
865
866 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
867 {
868 assert(reg >= R600_CTL_CONST_OFFSET);
869 assert(cs->cdw+2+num <= cs->max_dw);
870 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
871 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
872 }
873
874 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
875 {
876 radeon_compute_set_context_reg_seq(cs, reg, 1);
877 radeon_emit(cs, value);
878 }
879
880 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
881 {
882 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
883 radeon_compute_set_context_reg(cs, reg, value);
884 } else {
885 radeon_set_context_reg(cs, reg, value);
886 }
887 }
888
889 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
890 {
891 radeon_set_ctl_const_seq(cs, reg, 1);
892 radeon_emit(cs, value);
893 }
894
895 /*
896 * common helpers
897 */
898 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
899 {
900 return value * (1 << frac_bits);
901 }
902 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
903
904 /* 12.4 fixed-point */
905 static inline unsigned r600_pack_float_12p4(float x)
906 {
907 return x <= 0 ? 0 :
908 x >= 4096 ? 0xffff : x * 16;
909 }
910
911 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
912 static inline bool r600_can_read_depth(struct r600_texture *rtex)
913 {
914 return rtex->resource.b.b.nr_samples <= 1 &&
915 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
916 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
917 }
918
919 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
920 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
921 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
922
923 unsigned r600_conv_prim_to_gs_out(unsigned mode);
924 #endif