2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
39 #include "tgsi/tgsi_scan.h"
41 #define R600_NUM_ATOMS 51
43 #define R600_MAX_VIEWPORTS 16
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 58
63 #define R600_TRACE_CS_DWORDS 7
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 3
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
69 /* start driver buffers after user buffers */
70 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_UCP_SIZE (4*4*8)
72 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
74 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
76 * Note GS doesn't use a constant buffer binding, just a resource index,
77 * so it's fine to have it exist at index 16.
79 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
80 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
81 * of 16 const buffers.
82 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
84 * In order to support d3d 11 mandated minimum of 15 user const buffers
85 * we'd have to squash all use cases into one driver buffer.
87 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
90 #define R600_HW_STAGE_PS 0
91 #define R600_HW_STAGE_VS 1
92 #define R600_HW_STAGE_GS 2
93 #define R600_HW_STAGE_ES 3
94 #define EG_HW_STAGE_LS 4
95 #define EG_HW_STAGE_HS 5
97 #define R600_NUM_HW_STAGES 4
98 #define EG_NUM_HW_STAGES 6
100 #ifdef PIPE_ARCH_BIG_ENDIAN
101 #define R600_BIG_ENDIAN 1
103 #define R600_BIG_ENDIAN 0
107 struct r600_bytecode
;
108 union r600_shader_key
;
110 /* This is an atom containing GPU commands that never change.
111 * This is supposed to be copied directly into the CS. */
112 struct r600_command_buffer
{
119 struct r600_db_state
{
120 struct r600_atom atom
;
121 struct r600_surface
*rsurf
;
124 struct r600_db_misc_state
{
125 struct r600_atom atom
;
126 bool occlusion_query_enabled
;
127 bool flush_depthstencil_through_cb
;
128 bool flush_depth_inplace
;
129 bool flush_stencil_inplace
;
130 bool copy_depth
, copy_stencil
;
131 unsigned copy_sample
;
132 unsigned log_samples
;
133 unsigned db_shader_control
;
135 uint8_t ps_conservative_z
;
138 struct r600_cb_misc_state
{
139 struct r600_atom atom
;
140 unsigned cb_color_control
; /* this comes from blend state */
141 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
143 unsigned nr_ps_color_outputs
;
148 struct r600_clip_misc_state
{
149 struct r600_atom atom
;
150 unsigned pa_cl_clip_cntl
; /* from rasterizer */
151 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
152 unsigned clip_plane_enable
; /* from rasterizer */
153 unsigned clip_dist_write
; /* from vertex shader */
154 boolean clip_disable
; /* from vertex shader */
157 struct r600_alphatest_state
{
158 struct r600_atom atom
;
159 unsigned sx_alpha_test_control
; /* this comes from dsa state */
160 unsigned sx_alpha_ref
; /* this comes from dsa state */
162 bool cb0_export_16bpc
; /* from set_framebuffer_state */
165 struct r600_vgt_state
{
166 struct r600_atom atom
;
167 uint32_t vgt_multi_prim_ib_reset_en
;
168 uint32_t vgt_multi_prim_ib_reset_indx
;
169 uint32_t vgt_indx_offset
;
170 bool last_draw_was_indirect
;
173 struct r600_blend_color
{
174 struct r600_atom atom
;
175 struct pipe_blend_color state
;
178 struct r600_clip_state
{
179 struct r600_atom atom
;
180 struct pipe_clip_state state
;
183 struct r600_cs_shader_state
{
184 struct r600_atom atom
;
185 unsigned kernel_index
;
187 struct r600_pipe_compute
*shader
;
190 struct r600_framebuffer
{
191 struct r600_atom atom
;
192 struct pipe_framebuffer_state state
;
193 unsigned compressed_cb_mask
;
197 bool is_msaa_resolve
;
200 struct r600_sample_mask
{
201 struct r600_atom atom
;
202 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
205 struct r600_config_state
{
206 struct r600_atom atom
;
207 unsigned sq_gpr_resource_mgmt_1
;
208 unsigned sq_gpr_resource_mgmt_2
;
211 struct r600_stencil_ref
218 struct r600_stencil_ref_state
{
219 struct r600_atom atom
;
220 struct r600_stencil_ref state
;
221 struct pipe_stencil_ref pipe_state
;
224 struct r600_viewport_state
{
225 struct r600_atom atom
;
226 struct pipe_viewport_state state
[R600_MAX_VIEWPORTS
];
230 struct r600_shader_stages_state
{
231 struct r600_atom atom
;
232 unsigned geom_enable
;
235 struct r600_gs_rings_state
{
236 struct r600_atom atom
;
238 struct pipe_constant_buffer esgs_ring
;
239 struct pipe_constant_buffer gsvs_ring
;
242 /* This must start from 16. */
244 #define DBG_LLVM (1 << 29)
245 #define DBG_NO_CP_DMA (1 << 30)
247 #define DBG_NO_SB (1 << 21)
248 #define DBG_SB_CS (1 << 22)
249 #define DBG_SB_DRY_RUN (1 << 23)
250 #define DBG_SB_STAT (1 << 24)
251 #define DBG_SB_DUMP (1 << 25)
252 #define DBG_SB_NO_FALLBACK (1 << 26)
253 #define DBG_SB_DISASM (1 << 27)
254 #define DBG_SB_SAFEMATH (1 << 28)
257 struct r600_common_screen b
;
259 bool has_compressed_msaa_texturing
;
261 /*for compute global memory binding, we allocate stuff here, instead of
263 * XXX: Not sure if this is the best place for global_pool. Also,
264 * it's not thread safe, so it won't work with multiple contexts. */
265 struct compute_memory_pool
*global_pool
;
268 struct r600_pipe_sampler_view
{
269 struct pipe_sampler_view base
;
270 struct list_head list
;
271 struct r600_resource
*tex_resource
;
272 uint32_t tex_resource_words
[8];
273 bool skip_mip_address_reloc
;
274 bool is_stencil_sampler
;
277 struct r600_rasterizer_state
{
278 struct r600_command_buffer buffer
;
281 unsigned sprite_coord_enable
;
282 unsigned clip_plane_enable
;
283 unsigned pa_sc_line_stipple
;
284 unsigned pa_cl_clip_cntl
;
285 unsigned pa_su_sc_mode_cntl
;
290 bool multisample_enable
;
293 struct r600_poly_offset_state
{
294 struct r600_atom atom
;
295 enum pipe_format zs_format
;
300 struct r600_blend_state
{
301 struct r600_command_buffer buffer
;
302 struct r600_command_buffer buffer_no_blend
;
303 unsigned cb_target_mask
;
304 unsigned cb_color_control
;
305 unsigned cb_color_control_no_blend
;
310 struct r600_dsa_state
{
311 struct r600_command_buffer buffer
;
316 unsigned sx_alpha_test_control
;
319 struct r600_pipe_shader
;
321 struct r600_pipe_shader_selector
{
322 struct r600_pipe_shader
*current
;
324 struct tgsi_token
*tokens
;
325 struct pipe_stream_output_info so
;
326 struct tgsi_shader_info info
;
328 unsigned num_shaders
;
330 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
333 /* geometry shader properties */
334 unsigned gs_output_prim
;
335 unsigned gs_max_out_vertices
;
336 unsigned gs_num_invocations
;
339 uint64_t lds_patch_outputs_written_mask
;
340 uint64_t lds_outputs_written_mask
;
341 unsigned nr_ps_max_color_exports
;
344 struct r600_pipe_sampler_state
{
345 uint32_t tex_sampler_words
[3];
346 union pipe_color_union border_color
;
347 bool border_color_use
;
348 bool seamless_cube_map
;
351 /* needed for blitter save */
352 #define NUM_TEX_UNITS 16
354 struct r600_seamless_cube_map
{
355 struct r600_atom atom
;
359 struct r600_samplerview_state
{
360 struct r600_atom atom
;
361 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
362 uint32_t enabled_mask
;
364 uint32_t compressed_depthtex_mask
; /* which textures are depth */
365 uint32_t compressed_colortex_mask
;
366 boolean dirty_buffer_constants
;
369 struct r600_sampler_states
{
370 struct r600_atom atom
;
371 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
372 uint32_t enabled_mask
;
374 uint32_t has_bordercolor_mask
; /* which states contain the border color */
377 struct r600_textures_info
{
378 struct r600_samplerview_state views
;
379 struct r600_sampler_states states
;
380 bool is_array_sampler
[NUM_TEX_UNITS
];
383 struct r600_shader_driver_constants_info
{
384 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
388 bool texture_const_dirty
;
389 bool ps_sample_pos_dirty
;
392 struct r600_constbuf_state
394 struct r600_atom atom
;
395 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
396 uint32_t enabled_mask
;
400 struct r600_vertexbuf_state
402 struct r600_atom atom
;
403 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
404 uint32_t enabled_mask
; /* non-NULL buffers */
408 /* CSO (constant state object, in other words, immutable state). */
409 struct r600_cso_state
411 struct r600_atom atom
;
412 void *cso
; /* e.g. r600_blend_state */
413 struct r600_command_buffer
*cb
;
416 struct r600_scissor_state
418 struct r600_atom atom
;
419 struct pipe_scissor_state scissor
[R600_MAX_VIEWPORTS
];
421 bool enable
; /* r6xx only */
424 struct r600_fetch_shader
{
425 struct r600_resource
*buffer
;
429 struct r600_shader_state
{
430 struct r600_atom atom
;
431 struct r600_pipe_shader
*shader
;
434 struct r600_context
{
435 struct r600_common_context b
;
436 struct r600_screen
*screen
;
437 struct blitter_context
*blitter
;
438 struct u_suballocator
*allocator_fetch_shader
;
441 boolean has_vertex_cache
;
442 boolean keep_tiling_flags
;
443 unsigned default_gprs
[EG_NUM_HW_STAGES
];
444 unsigned r6xx_num_clause_temp_gprs
;
446 /* Miscellaneous state objects. */
447 void *custom_dsa_flush
;
448 void *custom_blend_resolve
;
449 void *custom_blend_decompress
;
450 void *custom_blend_fastclear
;
451 /* With rasterizer discard, there doesn't have to be a pixel shader.
452 * In that case, we bind this one: */
453 void *dummy_pixel_shader
;
454 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
455 * bug where valid CMASK and FMASK are required to be present to avoid
456 * a hardlock in certain operations but aren't actually used
457 * for anything useful. */
458 struct r600_resource
*dummy_fmask
;
459 struct r600_resource
*dummy_cmask
;
461 /* State binding slots are here. */
462 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
463 /* Dirty atom bitmask for fast tests */
464 uint64_t dirty_atoms
;
465 /* States for CS initialization. */
466 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
467 /** Compute specific registers initializations. The start_cs_cmd atom
468 * must be emitted before start_compute_cs_cmd. */
469 struct r600_command_buffer start_compute_cs_cmd
;
470 /* Register states. */
471 struct r600_alphatest_state alphatest_state
;
472 struct r600_cso_state blend_state
;
473 struct r600_blend_color blend_color
;
474 struct r600_cb_misc_state cb_misc_state
;
475 struct r600_clip_misc_state clip_misc_state
;
476 struct r600_clip_state clip_state
;
477 struct r600_db_misc_state db_misc_state
;
478 struct r600_db_state db_state
;
479 struct r600_cso_state dsa_state
;
480 struct r600_framebuffer framebuffer
;
481 struct r600_poly_offset_state poly_offset_state
;
482 struct r600_cso_state rasterizer_state
;
483 struct r600_sample_mask sample_mask
;
484 struct r600_scissor_state scissor
;
485 struct r600_seamless_cube_map seamless_cube_map
;
486 struct r600_config_state config_state
;
487 struct r600_stencil_ref_state stencil_ref
;
488 struct r600_vgt_state vgt_state
;
489 struct r600_viewport_state viewport
;
490 /* Shaders and shader resources. */
491 struct r600_cso_state vertex_fetch_shader
;
492 struct r600_shader_state hw_shader_stages
[EG_NUM_HW_STAGES
];
493 struct r600_cs_shader_state cs_shader_state
;
494 struct r600_shader_stages_state shader_stages
;
495 struct r600_gs_rings_state gs_rings
;
496 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
497 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
499 struct r600_shader_driver_constants_info driver_consts
[PIPE_SHADER_TYPES
];
501 /** Vertex buffers for fetch shaders */
502 struct r600_vertexbuf_state vertex_buffer_state
;
503 /** Vertex buffers for compute shaders */
504 struct r600_vertexbuf_state cs_vertex_buffer_state
;
506 /* Additional context states. */
507 unsigned compute_cb_target_mask
;
508 struct r600_pipe_shader_selector
*ps_shader
;
509 struct r600_pipe_shader_selector
*vs_shader
;
510 struct r600_pipe_shader_selector
*gs_shader
;
512 struct r600_pipe_shader_selector
*tcs_shader
;
513 struct r600_pipe_shader_selector
*tes_shader
;
515 struct r600_pipe_shader_selector
*fixed_func_tcs_shader
;
517 struct r600_rasterizer_state
*rasterizer
;
519 bool force_blend_disable
;
520 boolean dual_src_blend
;
525 struct pipe_index_buffer index_buffer
;
527 /* Last draw state (-1 = unset). */
528 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
529 int last_start_instance
;
532 struct r600_isa
*isa
;
533 float sample_positions
[4 * 16];
535 bool tess_state_dirty
;
536 struct r600_pipe_shader_selector
*last_ls
;
537 struct r600_pipe_shader_selector
*last_tcs
;
538 unsigned last_num_tcs_input_cp
;
542 static inline void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
543 struct r600_command_buffer
*cb
)
545 assert(cs
->cdw
+ cb
->num_dw
<= cs
->max_dw
);
546 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
547 cs
->cdw
+= cb
->num_dw
;
550 static inline void r600_set_atom_dirty(struct r600_context
*rctx
,
551 struct r600_atom
*atom
,
556 assert(atom
->id
!= 0);
557 assert(atom
->id
< sizeof(mask
) * 8);
558 mask
= 1ull << atom
->id
;
560 rctx
->dirty_atoms
|= mask
;
562 rctx
->dirty_atoms
&= ~mask
;
565 static inline void r600_mark_atom_dirty(struct r600_context
*rctx
,
566 struct r600_atom
*atom
)
568 r600_set_atom_dirty(rctx
, atom
, true);
571 void r600_trace_emit(struct r600_context
*rctx
);
573 static inline void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
575 atom
->emit(&rctx
->b
, atom
);
576 r600_set_atom_dirty(rctx
, atom
, false);
577 if (rctx
->screen
->b
.trace_bo
) {
578 r600_trace_emit(rctx
);
582 static inline void r600_set_cso_state(struct r600_context
*rctx
,
583 struct r600_cso_state
*state
, void *cso
)
586 r600_set_atom_dirty(rctx
, &state
->atom
, cso
!= NULL
);
589 static inline void r600_set_cso_state_with_cb(struct r600_context
*rctx
,
590 struct r600_cso_state
*state
, void *cso
,
591 struct r600_command_buffer
*cb
)
594 state
->atom
.num_dw
= cb
? cb
->num_dw
: 0;
595 r600_set_cso_state(rctx
, state
, cso
);
598 /* compute_memory_pool.c */
599 struct compute_memory_pool
;
600 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
601 struct compute_memory_pool
* compute_memory_pool_new(
602 struct r600_screen
*rscreen
);
604 /* evergreen_state.c */
605 struct pipe_sampler_view
*
606 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
607 struct pipe_resource
*texture
,
608 const struct pipe_sampler_view
*state
,
609 unsigned width0
, unsigned height0
,
610 unsigned force_level
);
611 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
612 enum chip_class ctx_chip_class
,
613 enum radeon_family ctx_family
,
615 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
616 enum chip_class ctx_chip_class
,
617 enum radeon_family ctx_family
,
620 void evergreen_init_state_functions(struct r600_context
*rctx
);
621 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
622 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
623 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
624 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
625 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
626 void evergreen_update_ls_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
627 void evergreen_update_hs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
628 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
629 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
630 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
631 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
632 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
633 enum pipe_format format
,
634 enum pipe_texture_target target
,
635 unsigned sample_count
,
637 void evergreen_init_color_surface(struct r600_context
*rctx
,
638 struct r600_surface
*surf
);
639 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
640 struct r600_surface
*surf
);
641 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
644 void r600_init_blit_functions(struct r600_context
*rctx
);
645 void r600_decompress_depth_textures(struct r600_context
*rctx
,
646 struct r600_samplerview_state
*textures
);
647 void r600_decompress_color_textures(struct r600_context
*rctx
,
648 struct r600_samplerview_state
*textures
);
649 void r600_resource_copy_region(struct pipe_context
*ctx
,
650 struct pipe_resource
*dst
,
652 unsigned dstx
, unsigned dsty
, unsigned dstz
,
653 struct pipe_resource
*src
,
655 const struct pipe_box
*src_box
);
658 int r600_pipe_shader_create(struct pipe_context
*ctx
,
659 struct r600_pipe_shader
*shader
,
660 union r600_shader_key key
);
662 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
665 struct pipe_sampler_view
*
666 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
667 struct pipe_resource
*texture
,
668 const struct pipe_sampler_view
*state
,
669 unsigned width_first_level
, unsigned height_first_level
);
670 void r600_init_state_functions(struct r600_context
*rctx
);
671 void r600_init_atom_start_cs(struct r600_context
*rctx
);
672 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
673 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
674 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
675 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
676 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
677 void *r600_create_resolve_blend(struct r600_context
*rctx
);
678 void *r700_create_resolve_blend(struct r600_context
*rctx
);
679 void *r600_create_decompress_blend(struct r600_context
*rctx
);
680 bool r600_adjust_gprs(struct r600_context
*rctx
);
681 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
682 enum pipe_format format
,
683 enum pipe_texture_target target
,
684 unsigned sample_count
,
686 void r600_update_db_shader_control(struct r600_context
* rctx
);
688 /* r600_hw_context.c */
689 void r600_context_gfx_flush(void *context
, unsigned flags
,
690 struct pipe_fence_handle
**fence
);
691 void r600_begin_new_cs(struct r600_context
*ctx
);
692 void r600_flush_emit(struct r600_context
*ctx
);
693 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
694 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
695 struct pipe_resource
*dst
, uint64_t dst_offset
,
696 struct pipe_resource
*src
, uint64_t src_offset
,
698 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
699 struct pipe_resource
*dst
, uint64_t offset
,
700 unsigned size
, uint32_t clear_value
);
701 void r600_dma_copy_buffer(struct r600_context
*rctx
,
702 struct pipe_resource
*dst
,
703 struct pipe_resource
*src
,
709 * evergreen_hw_context.c
711 void evergreen_dma_copy_buffer(struct r600_context
*rctx
,
712 struct pipe_resource
*dst
,
713 struct pipe_resource
*src
,
717 void evergreen_setup_tess_constants(struct r600_context
*rctx
,
718 const struct pipe_draw_info
*info
,
719 unsigned *num_patches
);
720 uint32_t evergreen_get_ls_hs_config(struct r600_context
*rctx
,
721 const struct pipe_draw_info
*info
,
722 unsigned num_patches
);
723 void evergreen_set_ls_hs_config(struct r600_context
*rctx
,
724 struct radeon_winsys_cs
*cs
,
725 uint32_t ls_hs_config
);
726 void evergreen_set_lds_alloc(struct r600_context
*rctx
,
727 struct radeon_winsys_cs
*cs
,
730 /* r600_state_common.c */
731 void r600_init_common_state_functions(struct r600_context
*rctx
);
732 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
733 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
734 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
735 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
736 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
737 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
738 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
739 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
740 void r600_add_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
);
741 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
742 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
744 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
745 void r600_sampler_views_dirty(struct r600_context
*rctx
,
746 struct r600_samplerview_state
*state
);
747 void r600_sampler_states_dirty(struct r600_context
*rctx
,
748 struct r600_sampler_states
*state
);
749 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
750 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
);
751 uint32_t r600_translate_stencil_op(int s_op
);
752 uint32_t r600_translate_fill(uint32_t func
);
753 unsigned r600_tex_wrap(unsigned wrap
);
754 unsigned r600_tex_filter(unsigned filter
);
755 unsigned r600_tex_mipfilter(unsigned filter
);
756 unsigned r600_tex_compare(unsigned compare
);
757 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
758 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
759 struct pipe_resource
*texture
,
760 const struct pipe_surface
*templ
,
761 unsigned width
, unsigned height
);
762 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
763 const unsigned char *swizzle_view
,
765 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
766 const unsigned char *swizzle_view
,
767 uint32_t *word4_p
, uint32_t *yuv_format_p
);
768 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
);
769 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
);
772 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
773 const struct pipe_video_codec
*decoder
);
775 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
776 const struct pipe_video_buffer
*tmpl
);
779 * Helpers for building command buffers
782 #define PKT3_SET_CONFIG_REG 0x68
783 #define PKT3_SET_CONTEXT_REG 0x69
784 #define PKT3_SET_CTL_CONST 0x6F
785 #define PKT3_SET_LOOP_CONST 0x6C
787 #define R600_CONFIG_REG_OFFSET 0x08000
788 #define R600_CONTEXT_REG_OFFSET 0x28000
789 #define R600_CTL_CONST_OFFSET 0x3CFF0
790 #define R600_LOOP_CONST_OFFSET 0X0003E200
791 #define EG_LOOP_CONST_OFFSET 0x0003A200
793 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
794 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
795 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
796 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
797 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
799 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
801 /*Evergreen Compute packet3*/
802 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
804 static inline void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
806 cb
->buf
[cb
->num_dw
++] = value
;
809 static inline void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
811 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
812 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
816 static inline void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
818 assert(reg
< R600_CONTEXT_REG_OFFSET
);
819 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
820 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
821 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
825 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
828 static inline void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
830 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
831 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
832 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
833 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
837 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
840 static inline void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
842 assert(reg
>= R600_CTL_CONST_OFFSET
);
843 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
844 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
845 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
848 static inline void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
850 assert(reg
>= R600_LOOP_CONST_OFFSET
);
851 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
852 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
853 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
857 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
860 static inline void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
862 assert(reg
>= EG_LOOP_CONST_OFFSET
);
863 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
864 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
865 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
868 static inline void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
870 r600_store_config_reg_seq(cb
, reg
, 1);
871 r600_store_value(cb
, value
);
874 static inline void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
876 r600_store_context_reg_seq(cb
, reg
, 1);
877 r600_store_value(cb
, value
);
880 static inline void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
882 r600_store_ctl_const_seq(cb
, reg
, 1);
883 r600_store_value(cb
, value
);
886 static inline void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
888 r600_store_loop_const_seq(cb
, reg
, 1);
889 r600_store_value(cb
, value
);
892 static inline void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
894 eg_store_loop_const_seq(cb
, reg
, 1);
895 r600_store_value(cb
, value
);
898 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
899 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
901 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
903 radeon_set_context_reg_seq(cs
, reg
, num
);
904 /* Set the compute bit on the packet header */
905 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
908 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
910 assert(reg
>= R600_CTL_CONST_OFFSET
);
911 assert(cs
->cdw
+2+num
<= cs
->max_dw
);
912 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
913 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
916 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
918 radeon_compute_set_context_reg_seq(cs
, reg
, 1);
919 radeon_emit(cs
, value
);
922 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
924 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
925 radeon_compute_set_context_reg(cs
, reg
, value
);
927 radeon_set_context_reg(cs
, reg
, value
);
931 static inline void radeon_set_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
933 radeon_set_ctl_const_seq(cs
, reg
, 1);
934 radeon_emit(cs
, value
);
940 static inline uint32_t S_FIXED(float value
, uint32_t frac_bits
)
942 return value
* (1 << frac_bits
);
944 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
946 /* 12.4 fixed-point */
947 static inline unsigned r600_pack_float_12p4(float x
)
950 x
>= 4096 ? 0xffff : x
* 16;
953 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
954 static inline bool r600_can_read_depth(struct r600_texture
*rtex
)
956 return rtex
->resource
.b
.b
.nr_samples
<= 1 &&
957 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
958 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
);
961 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
962 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
963 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
965 unsigned r600_conv_prim_to_gs_out(unsigned mode
);