2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
37 #include "tgsi/tgsi_scan.h"
39 #define R600_NUM_ATOMS 52
41 #define R600_MAX_VIEWPORTS 16
44 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
45 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
46 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
47 /* read-write caches */
48 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
49 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
51 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
52 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
53 /* engine synchronization */
54 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
55 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
56 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
58 /* the number of CS dwords for flushing and drawing */
59 #define R600_MAX_FLUSH_CS_DWORDS 16
60 #define R600_MAX_DRAW_CS_DWORDS 58
62 #define R600_MAX_USER_CONST_BUFFERS 13
63 #define R600_MAX_DRIVER_CONST_BUFFERS 3
64 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
66 /* start driver buffers after user buffers */
67 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
68 #define R600_UCP_SIZE (4*4*8)
69 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
71 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
73 * Note GS doesn't use a constant buffer binding, just a resource index,
74 * so it's fine to have it exist at index 16.
76 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
77 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
78 * of 16 const buffers.
79 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
81 * In order to support d3d 11 mandated minimum of 15 user const buffers
82 * we'd have to squash all use cases into one driver buffer.
84 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
87 #define R600_HW_STAGE_PS 0
88 #define R600_HW_STAGE_VS 1
89 #define R600_HW_STAGE_GS 2
90 #define R600_HW_STAGE_ES 3
91 #define EG_HW_STAGE_LS 4
92 #define EG_HW_STAGE_HS 5
94 #define R600_NUM_HW_STAGES 4
95 #define EG_NUM_HW_STAGES 6
97 #ifdef PIPE_ARCH_BIG_ENDIAN
98 #define R600_BIG_ENDIAN 1
100 #define R600_BIG_ENDIAN 0
104 struct r600_bytecode
;
105 union r600_shader_key
;
107 /* This is an atom containing GPU commands that never change.
108 * This is supposed to be copied directly into the CS. */
109 struct r600_command_buffer
{
116 struct r600_db_state
{
117 struct r600_atom atom
;
118 struct r600_surface
*rsurf
;
121 struct r600_db_misc_state
{
122 struct r600_atom atom
;
123 bool occlusion_queries_disabled
;
124 bool flush_depthstencil_through_cb
;
125 bool flush_depth_inplace
;
126 bool flush_stencil_inplace
;
127 bool copy_depth
, copy_stencil
;
128 unsigned copy_sample
;
129 unsigned log_samples
;
130 unsigned db_shader_control
;
132 uint8_t ps_conservative_z
;
135 struct r600_cb_misc_state
{
136 struct r600_atom atom
;
137 unsigned cb_color_control
; /* this comes from blend state */
138 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
140 unsigned nr_ps_color_outputs
;
145 struct r600_clip_misc_state
{
146 struct r600_atom atom
;
147 unsigned pa_cl_clip_cntl
; /* from rasterizer */
148 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
149 unsigned clip_plane_enable
; /* from rasterizer */
150 unsigned clip_dist_write
; /* from vertex shader */
151 boolean clip_disable
; /* from vertex shader */
152 boolean vs_out_viewport
; /* from vertex shader */
155 struct r600_alphatest_state
{
156 struct r600_atom atom
;
157 unsigned sx_alpha_test_control
; /* this comes from dsa state */
158 unsigned sx_alpha_ref
; /* this comes from dsa state */
160 bool cb0_export_16bpc
; /* from set_framebuffer_state */
163 struct r600_vgt_state
{
164 struct r600_atom atom
;
165 uint32_t vgt_multi_prim_ib_reset_en
;
166 uint32_t vgt_multi_prim_ib_reset_indx
;
167 uint32_t vgt_indx_offset
;
168 bool last_draw_was_indirect
;
171 struct r600_blend_color
{
172 struct r600_atom atom
;
173 struct pipe_blend_color state
;
176 struct r600_clip_state
{
177 struct r600_atom atom
;
178 struct pipe_clip_state state
;
181 struct r600_cs_shader_state
{
182 struct r600_atom atom
;
183 unsigned kernel_index
;
185 struct r600_pipe_compute
*shader
;
188 struct r600_framebuffer
{
189 struct r600_atom atom
;
190 struct pipe_framebuffer_state state
;
191 unsigned compressed_cb_mask
;
195 bool is_msaa_resolve
;
198 struct r600_sample_mask
{
199 struct r600_atom atom
;
200 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
203 struct r600_config_state
{
204 struct r600_atom atom
;
205 unsigned sq_gpr_resource_mgmt_1
;
206 unsigned sq_gpr_resource_mgmt_2
;
207 unsigned sq_gpr_resource_mgmt_3
;
208 bool dyn_gpr_enabled
;
211 struct r600_stencil_ref
218 struct r600_stencil_ref_state
{
219 struct r600_atom atom
;
220 struct r600_stencil_ref state
;
221 struct pipe_stencil_ref pipe_state
;
224 struct r600_viewport_state
{
225 struct r600_atom atom
;
226 struct pipe_viewport_state state
[R600_MAX_VIEWPORTS
];
230 struct r600_shader_stages_state
{
231 struct r600_atom atom
;
232 unsigned geom_enable
;
235 struct r600_gs_rings_state
{
236 struct r600_atom atom
;
238 struct pipe_constant_buffer esgs_ring
;
239 struct pipe_constant_buffer gsvs_ring
;
242 /* This must start from 16. */
244 #define DBG_NO_CP_DMA (1 << 30)
246 #define DBG_NO_SB (1 << 21)
247 #define DBG_SB_CS (1 << 22)
248 #define DBG_SB_DRY_RUN (1 << 23)
249 #define DBG_SB_STAT (1 << 24)
250 #define DBG_SB_DUMP (1 << 25)
251 #define DBG_SB_NO_FALLBACK (1 << 26)
252 #define DBG_SB_DISASM (1 << 27)
253 #define DBG_SB_SAFEMATH (1 << 28)
256 struct r600_common_screen b
;
258 bool has_compressed_msaa_texturing
;
260 /*for compute global memory binding, we allocate stuff here, instead of
262 * XXX: Not sure if this is the best place for global_pool. Also,
263 * it's not thread safe, so it won't work with multiple contexts. */
264 struct compute_memory_pool
*global_pool
;
267 struct r600_pipe_sampler_view
{
268 struct pipe_sampler_view base
;
269 struct list_head list
;
270 struct r600_resource
*tex_resource
;
271 uint32_t tex_resource_words
[8];
272 bool skip_mip_address_reloc
;
273 bool is_stencil_sampler
;
276 struct r600_rasterizer_state
{
277 struct r600_command_buffer buffer
;
280 unsigned sprite_coord_enable
;
281 unsigned clip_plane_enable
;
282 unsigned pa_sc_line_stipple
;
283 unsigned pa_cl_clip_cntl
;
284 unsigned pa_su_sc_mode_cntl
;
289 bool multisample_enable
;
292 struct r600_poly_offset_state
{
293 struct r600_atom atom
;
294 enum pipe_format zs_format
;
299 struct r600_blend_state
{
300 struct r600_command_buffer buffer
;
301 struct r600_command_buffer buffer_no_blend
;
302 unsigned cb_target_mask
;
303 unsigned cb_color_control
;
304 unsigned cb_color_control_no_blend
;
309 struct r600_dsa_state
{
310 struct r600_command_buffer buffer
;
315 unsigned sx_alpha_test_control
;
318 struct r600_pipe_shader
;
320 struct r600_pipe_shader_selector
{
321 struct r600_pipe_shader
*current
;
323 struct tgsi_token
*tokens
;
324 struct pipe_stream_output_info so
;
325 struct tgsi_shader_info info
;
327 unsigned num_shaders
;
329 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
332 /* geometry shader properties */
333 unsigned gs_output_prim
;
334 unsigned gs_max_out_vertices
;
335 unsigned gs_num_invocations
;
338 uint64_t lds_patch_outputs_written_mask
;
339 uint64_t lds_outputs_written_mask
;
340 unsigned nr_ps_max_color_exports
;
343 struct r600_pipe_sampler_state
{
344 uint32_t tex_sampler_words
[3];
345 union pipe_color_union border_color
;
346 bool border_color_use
;
347 bool seamless_cube_map
;
350 /* needed for blitter save */
351 #define NUM_TEX_UNITS 16
353 struct r600_seamless_cube_map
{
354 struct r600_atom atom
;
358 struct r600_samplerview_state
{
359 struct r600_atom atom
;
360 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
361 uint32_t enabled_mask
;
363 uint32_t compressed_depthtex_mask
; /* which textures are depth */
364 uint32_t compressed_colortex_mask
;
365 boolean dirty_buffer_constants
;
368 struct r600_sampler_states
{
369 struct r600_atom atom
;
370 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
371 uint32_t enabled_mask
;
373 uint32_t has_bordercolor_mask
; /* which states contain the border color */
376 struct r600_textures_info
{
377 struct r600_samplerview_state views
;
378 struct r600_sampler_states states
;
379 bool is_array_sampler
[NUM_TEX_UNITS
];
382 struct r600_shader_driver_constants_info
{
383 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
387 bool texture_const_dirty
;
388 bool ps_sample_pos_dirty
;
391 struct r600_constbuf_state
393 struct r600_atom atom
;
394 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
395 uint32_t enabled_mask
;
399 struct r600_vertexbuf_state
401 struct r600_atom atom
;
402 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
403 uint32_t enabled_mask
; /* non-NULL buffers */
407 /* CSO (constant state object, in other words, immutable state). */
408 struct r600_cso_state
410 struct r600_atom atom
;
411 void *cso
; /* e.g. r600_blend_state */
412 struct r600_command_buffer
*cb
;
415 struct r600_scissor_state
417 struct r600_atom atom
;
418 struct pipe_scissor_state scissor
[R600_MAX_VIEWPORTS
];
420 bool enable
; /* r6xx only */
423 struct r600_fetch_shader
{
424 struct r600_resource
*buffer
;
428 struct r600_shader_state
{
429 struct r600_atom atom
;
430 struct r600_pipe_shader
*shader
;
433 struct r600_context
{
434 struct r600_common_context b
;
435 struct r600_screen
*screen
;
436 struct blitter_context
*blitter
;
437 struct u_suballocator
*allocator_fetch_shader
;
440 boolean has_vertex_cache
;
441 unsigned default_gprs
[EG_NUM_HW_STAGES
];
442 unsigned current_gprs
[EG_NUM_HW_STAGES
];
443 unsigned r6xx_num_clause_temp_gprs
;
445 /* Miscellaneous state objects. */
446 void *custom_dsa_flush
;
447 void *custom_blend_resolve
;
448 void *custom_blend_decompress
;
449 void *custom_blend_fastclear
;
450 /* With rasterizer discard, there doesn't have to be a pixel shader.
451 * In that case, we bind this one: */
452 void *dummy_pixel_shader
;
453 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
454 * bug where valid CMASK and FMASK are required to be present to avoid
455 * a hardlock in certain operations but aren't actually used
456 * for anything useful. */
457 struct r600_resource
*dummy_fmask
;
458 struct r600_resource
*dummy_cmask
;
460 /* State binding slots are here. */
461 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
462 /* Dirty atom bitmask for fast tests */
463 uint64_t dirty_atoms
;
464 /* States for CS initialization. */
465 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
466 /** Compute specific registers initializations. The start_cs_cmd atom
467 * must be emitted before start_compute_cs_cmd. */
468 struct r600_command_buffer start_compute_cs_cmd
;
469 /* Register states. */
470 struct r600_alphatest_state alphatest_state
;
471 struct r600_cso_state blend_state
;
472 struct r600_blend_color blend_color
;
473 struct r600_cb_misc_state cb_misc_state
;
474 struct r600_clip_misc_state clip_misc_state
;
475 struct r600_clip_state clip_state
;
476 struct r600_db_misc_state db_misc_state
;
477 struct r600_db_state db_state
;
478 struct r600_cso_state dsa_state
;
479 struct r600_framebuffer framebuffer
;
480 struct r600_poly_offset_state poly_offset_state
;
481 struct r600_cso_state rasterizer_state
;
482 struct r600_sample_mask sample_mask
;
483 struct r600_scissor_state scissor
;
484 struct r600_seamless_cube_map seamless_cube_map
;
485 struct r600_config_state config_state
;
486 struct r600_stencil_ref_state stencil_ref
;
487 struct r600_vgt_state vgt_state
;
488 struct r600_viewport_state viewport
;
489 /* Shaders and shader resources. */
490 struct r600_cso_state vertex_fetch_shader
;
491 struct r600_shader_state hw_shader_stages
[EG_NUM_HW_STAGES
];
492 struct r600_cs_shader_state cs_shader_state
;
493 struct r600_shader_stages_state shader_stages
;
494 struct r600_gs_rings_state gs_rings
;
495 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
496 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
498 struct r600_shader_driver_constants_info driver_consts
[PIPE_SHADER_TYPES
];
500 /** Vertex buffers for fetch shaders */
501 struct r600_vertexbuf_state vertex_buffer_state
;
502 /** Vertex buffers for compute shaders */
503 struct r600_vertexbuf_state cs_vertex_buffer_state
;
505 /* Additional context states. */
506 unsigned compute_cb_target_mask
;
507 struct r600_pipe_shader_selector
*ps_shader
;
508 struct r600_pipe_shader_selector
*vs_shader
;
509 struct r600_pipe_shader_selector
*gs_shader
;
511 struct r600_pipe_shader_selector
*tcs_shader
;
512 struct r600_pipe_shader_selector
*tes_shader
;
514 struct r600_pipe_shader_selector
*fixed_func_tcs_shader
;
516 struct r600_rasterizer_state
*rasterizer
;
518 bool force_blend_disable
;
519 boolean dual_src_blend
;
524 struct pipe_index_buffer index_buffer
;
526 /* Last draw state (-1 = unset). */
527 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
528 int last_start_instance
;
531 struct r600_isa
*isa
;
532 float sample_positions
[4 * 16];
534 bool tess_state_dirty
;
535 struct r600_pipe_shader_selector
*last_ls
;
536 struct r600_pipe_shader_selector
*last_tcs
;
537 unsigned last_num_tcs_input_cp
;
541 static inline void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
542 struct r600_command_buffer
*cb
)
544 assert(cs
->cdw
+ cb
->num_dw
<= cs
->max_dw
);
545 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
546 cs
->cdw
+= cb
->num_dw
;
549 static inline void r600_set_atom_dirty(struct r600_context
*rctx
,
550 struct r600_atom
*atom
,
555 assert(atom
->id
!= 0);
556 assert(atom
->id
< sizeof(mask
) * 8);
557 mask
= 1ull << atom
->id
;
559 rctx
->dirty_atoms
|= mask
;
561 rctx
->dirty_atoms
&= ~mask
;
564 static inline void r600_mark_atom_dirty(struct r600_context
*rctx
,
565 struct r600_atom
*atom
)
567 r600_set_atom_dirty(rctx
, atom
, true);
570 static inline void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
572 atom
->emit(&rctx
->b
, atom
);
573 r600_set_atom_dirty(rctx
, atom
, false);
576 static inline void r600_set_cso_state(struct r600_context
*rctx
,
577 struct r600_cso_state
*state
, void *cso
)
580 r600_set_atom_dirty(rctx
, &state
->atom
, cso
!= NULL
);
583 static inline void r600_set_cso_state_with_cb(struct r600_context
*rctx
,
584 struct r600_cso_state
*state
, void *cso
,
585 struct r600_command_buffer
*cb
)
588 state
->atom
.num_dw
= cb
? cb
->num_dw
: 0;
589 r600_set_cso_state(rctx
, state
, cso
);
592 /* compute_memory_pool.c */
593 struct compute_memory_pool
;
594 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
595 struct compute_memory_pool
* compute_memory_pool_new(
596 struct r600_screen
*rscreen
);
598 /* evergreen_state.c */
599 struct pipe_sampler_view
*
600 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
601 struct pipe_resource
*texture
,
602 const struct pipe_sampler_view
*state
,
603 unsigned width0
, unsigned height0
,
604 unsigned force_level
);
605 void evergreen_init_common_regs(struct r600_context
*ctx
,
606 struct r600_command_buffer
*cb
,
607 enum chip_class ctx_chip_class
,
608 enum radeon_family ctx_family
,
610 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
611 enum chip_class ctx_chip_class
,
612 enum radeon_family ctx_family
,
615 void evergreen_init_state_functions(struct r600_context
*rctx
);
616 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
617 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
618 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
619 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
620 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
621 void evergreen_update_ls_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
622 void evergreen_update_hs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
623 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
624 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
625 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
626 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
627 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
628 enum pipe_format format
,
629 enum pipe_texture_target target
,
630 unsigned sample_count
,
632 void evergreen_init_color_surface(struct r600_context
*rctx
,
633 struct r600_surface
*surf
);
634 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
635 struct r600_surface
*surf
);
636 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
637 bool evergreen_adjust_gprs(struct r600_context
*rctx
);
639 void r600_init_blit_functions(struct r600_context
*rctx
);
640 void r600_decompress_depth_textures(struct r600_context
*rctx
,
641 struct r600_samplerview_state
*textures
);
642 void r600_decompress_color_textures(struct r600_context
*rctx
,
643 struct r600_samplerview_state
*textures
);
644 void r600_resource_copy_region(struct pipe_context
*ctx
,
645 struct pipe_resource
*dst
,
647 unsigned dstx
, unsigned dsty
, unsigned dstz
,
648 struct pipe_resource
*src
,
650 const struct pipe_box
*src_box
);
653 int r600_pipe_shader_create(struct pipe_context
*ctx
,
654 struct r600_pipe_shader
*shader
,
655 union r600_shader_key key
);
657 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
660 struct pipe_sampler_view
*
661 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
662 struct pipe_resource
*texture
,
663 const struct pipe_sampler_view
*state
,
664 unsigned width_first_level
, unsigned height_first_level
);
665 void r600_init_state_functions(struct r600_context
*rctx
);
666 void r600_init_atom_start_cs(struct r600_context
*rctx
);
667 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
668 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
669 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
670 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
671 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
672 void *r600_create_resolve_blend(struct r600_context
*rctx
);
673 void *r700_create_resolve_blend(struct r600_context
*rctx
);
674 void *r600_create_decompress_blend(struct r600_context
*rctx
);
675 bool r600_adjust_gprs(struct r600_context
*rctx
);
676 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
677 enum pipe_format format
,
678 enum pipe_texture_target target
,
679 unsigned sample_count
,
681 void r600_update_db_shader_control(struct r600_context
* rctx
);
683 /* r600_hw_context.c */
684 void r600_context_gfx_flush(void *context
, unsigned flags
,
685 struct pipe_fence_handle
**fence
);
686 void r600_begin_new_cs(struct r600_context
*ctx
);
687 void r600_flush_emit(struct r600_context
*ctx
);
688 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
689 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
690 struct pipe_resource
*dst
, uint64_t dst_offset
,
691 struct pipe_resource
*src
, uint64_t src_offset
,
693 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
694 struct pipe_resource
*dst
, uint64_t offset
,
695 unsigned size
, uint32_t clear_value
);
696 void r600_dma_copy_buffer(struct r600_context
*rctx
,
697 struct pipe_resource
*dst
,
698 struct pipe_resource
*src
,
704 * evergreen_hw_context.c
706 void evergreen_dma_copy_buffer(struct r600_context
*rctx
,
707 struct pipe_resource
*dst
,
708 struct pipe_resource
*src
,
712 void evergreen_setup_tess_constants(struct r600_context
*rctx
,
713 const struct pipe_draw_info
*info
,
714 unsigned *num_patches
);
715 uint32_t evergreen_get_ls_hs_config(struct r600_context
*rctx
,
716 const struct pipe_draw_info
*info
,
717 unsigned num_patches
);
718 void evergreen_set_ls_hs_config(struct r600_context
*rctx
,
719 struct radeon_winsys_cs
*cs
,
720 uint32_t ls_hs_config
);
721 void evergreen_set_lds_alloc(struct r600_context
*rctx
,
722 struct radeon_winsys_cs
*cs
,
725 /* r600_state_common.c */
726 void r600_init_common_state_functions(struct r600_context
*rctx
);
727 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
728 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
729 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
730 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
731 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
732 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
733 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
734 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
735 void r600_add_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
);
736 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
737 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
739 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
740 void r600_sampler_views_dirty(struct r600_context
*rctx
,
741 struct r600_samplerview_state
*state
);
742 void r600_sampler_states_dirty(struct r600_context
*rctx
,
743 struct r600_sampler_states
*state
);
744 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
745 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
);
746 uint32_t r600_translate_stencil_op(int s_op
);
747 uint32_t r600_translate_fill(uint32_t func
);
748 unsigned r600_tex_wrap(unsigned wrap
);
749 unsigned r600_tex_filter(unsigned filter
);
750 unsigned r600_tex_mipfilter(unsigned filter
);
751 unsigned r600_tex_compare(unsigned compare
);
752 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
753 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
754 struct pipe_resource
*texture
,
755 const struct pipe_surface
*templ
,
756 unsigned width
, unsigned height
);
757 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
758 const unsigned char *swizzle_view
,
760 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
761 const unsigned char *swizzle_view
,
762 uint32_t *word4_p
, uint32_t *yuv_format_p
);
763 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
);
764 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
);
767 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
768 const struct pipe_video_codec
*decoder
);
770 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
771 const struct pipe_video_buffer
*tmpl
);
774 * Helpers for building command buffers
777 #define PKT3_SET_CONFIG_REG 0x68
778 #define PKT3_SET_CONTEXT_REG 0x69
779 #define PKT3_SET_CTL_CONST 0x6F
780 #define PKT3_SET_LOOP_CONST 0x6C
782 #define R600_CONFIG_REG_OFFSET 0x08000
783 #define R600_CONTEXT_REG_OFFSET 0x28000
784 #define R600_CTL_CONST_OFFSET 0x3CFF0
785 #define R600_LOOP_CONST_OFFSET 0X0003E200
786 #define EG_LOOP_CONST_OFFSET 0x0003A200
788 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
789 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
790 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
791 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
792 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
794 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
796 /*Evergreen Compute packet3*/
797 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
799 static inline void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
801 cb
->buf
[cb
->num_dw
++] = value
;
804 static inline void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
806 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
807 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
811 static inline void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
813 assert(reg
< R600_CONTEXT_REG_OFFSET
);
814 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
815 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
816 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
820 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
823 static inline void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
825 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
826 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
827 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
828 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
832 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
835 static inline void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
837 assert(reg
>= R600_CTL_CONST_OFFSET
);
838 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
839 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
840 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
843 static inline void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
845 assert(reg
>= R600_LOOP_CONST_OFFSET
);
846 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
847 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
848 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
852 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
855 static inline void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
857 assert(reg
>= EG_LOOP_CONST_OFFSET
);
858 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
859 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
860 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
863 static inline void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
865 r600_store_config_reg_seq(cb
, reg
, 1);
866 r600_store_value(cb
, value
);
869 static inline void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
871 r600_store_context_reg_seq(cb
, reg
, 1);
872 r600_store_value(cb
, value
);
875 static inline void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
877 r600_store_ctl_const_seq(cb
, reg
, 1);
878 r600_store_value(cb
, value
);
881 static inline void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
883 r600_store_loop_const_seq(cb
, reg
, 1);
884 r600_store_value(cb
, value
);
887 static inline void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
889 eg_store_loop_const_seq(cb
, reg
, 1);
890 r600_store_value(cb
, value
);
893 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
894 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
896 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
898 radeon_set_context_reg_seq(cs
, reg
, num
);
899 /* Set the compute bit on the packet header */
900 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
903 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
905 assert(reg
>= R600_CTL_CONST_OFFSET
);
906 assert(cs
->cdw
+2+num
<= cs
->max_dw
);
907 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
908 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
911 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
913 radeon_compute_set_context_reg_seq(cs
, reg
, 1);
914 radeon_emit(cs
, value
);
917 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
919 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
920 radeon_compute_set_context_reg(cs
, reg
, value
);
922 radeon_set_context_reg(cs
, reg
, value
);
926 static inline void radeon_set_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
928 radeon_set_ctl_const_seq(cs
, reg
, 1);
929 radeon_emit(cs
, value
);
935 static inline uint32_t S_FIXED(float value
, uint32_t frac_bits
)
937 return value
* (1 << frac_bits
);
940 /* 12.4 fixed-point */
941 static inline unsigned r600_pack_float_12p4(float x
)
944 x
>= 4096 ? 0xffff : x
* 16;
947 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
948 static inline bool r600_can_read_depth(struct r600_texture
*rtex
)
950 return rtex
->resource
.b
.b
.nr_samples
<= 1 &&
951 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
952 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
);
955 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
956 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
957 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
959 unsigned r600_conv_prim_to_gs_out(unsigned mode
);