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Merge ../mesa into vulkan
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 52
42
43 #define R600_MAX_VIEWPORTS 16
44
45 /* read caches */
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
59
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 58
63 #define R600_TRACE_CS_DWORDS 7
64
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 3
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
68
69 /* start driver buffers after user buffers */
70 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_UCP_SIZE (4*4*8)
72 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
73
74 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
75 /*
76 * Note GS doesn't use a constant buffer binding, just a resource index,
77 * so it's fine to have it exist at index 16.
78 */
79 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
80 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
81 * of 16 const buffers.
82 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
83 *
84 * In order to support d3d 11 mandated minimum of 15 user const buffers
85 * we'd have to squash all use cases into one driver buffer.
86 */
87 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
88
89 /* HW stages */
90 #define R600_HW_STAGE_PS 0
91 #define R600_HW_STAGE_VS 1
92 #define R600_HW_STAGE_GS 2
93 #define R600_HW_STAGE_ES 3
94 #define EG_HW_STAGE_LS 4
95 #define EG_HW_STAGE_HS 5
96
97 #define R600_NUM_HW_STAGES 4
98 #define EG_NUM_HW_STAGES 6
99
100 #ifdef PIPE_ARCH_BIG_ENDIAN
101 #define R600_BIG_ENDIAN 1
102 #else
103 #define R600_BIG_ENDIAN 0
104 #endif
105
106 struct r600_context;
107 struct r600_bytecode;
108 union r600_shader_key;
109
110 /* This is an atom containing GPU commands that never change.
111 * This is supposed to be copied directly into the CS. */
112 struct r600_command_buffer {
113 uint32_t *buf;
114 unsigned num_dw;
115 unsigned max_num_dw;
116 unsigned pkt_flags;
117 };
118
119 struct r600_db_state {
120 struct r600_atom atom;
121 struct r600_surface *rsurf;
122 };
123
124 struct r600_db_misc_state {
125 struct r600_atom atom;
126 bool occlusion_query_enabled;
127 bool flush_depthstencil_through_cb;
128 bool flush_depth_inplace;
129 bool flush_stencil_inplace;
130 bool copy_depth, copy_stencil;
131 unsigned copy_sample;
132 unsigned log_samples;
133 unsigned db_shader_control;
134 bool htile_clear;
135 uint8_t ps_conservative_z;
136 };
137
138 struct r600_cb_misc_state {
139 struct r600_atom atom;
140 unsigned cb_color_control; /* this comes from blend state */
141 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
142 unsigned nr_cbufs;
143 unsigned nr_ps_color_outputs;
144 bool multiwrite;
145 bool dual_src_blend;
146 };
147
148 struct r600_clip_misc_state {
149 struct r600_atom atom;
150 unsigned pa_cl_clip_cntl; /* from rasterizer */
151 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
152 unsigned clip_plane_enable; /* from rasterizer */
153 unsigned clip_dist_write; /* from vertex shader */
154 boolean clip_disable; /* from vertex shader */
155 boolean vs_out_viewport; /* from vertex shader */
156 };
157
158 struct r600_alphatest_state {
159 struct r600_atom atom;
160 unsigned sx_alpha_test_control; /* this comes from dsa state */
161 unsigned sx_alpha_ref; /* this comes from dsa state */
162 bool bypass;
163 bool cb0_export_16bpc; /* from set_framebuffer_state */
164 };
165
166 struct r600_vgt_state {
167 struct r600_atom atom;
168 uint32_t vgt_multi_prim_ib_reset_en;
169 uint32_t vgt_multi_prim_ib_reset_indx;
170 uint32_t vgt_indx_offset;
171 bool last_draw_was_indirect;
172 };
173
174 struct r600_blend_color {
175 struct r600_atom atom;
176 struct pipe_blend_color state;
177 };
178
179 struct r600_clip_state {
180 struct r600_atom atom;
181 struct pipe_clip_state state;
182 };
183
184 struct r600_cs_shader_state {
185 struct r600_atom atom;
186 unsigned kernel_index;
187 unsigned pc;
188 struct r600_pipe_compute *shader;
189 };
190
191 struct r600_framebuffer {
192 struct r600_atom atom;
193 struct pipe_framebuffer_state state;
194 unsigned compressed_cb_mask;
195 unsigned nr_samples;
196 bool export_16bpc;
197 bool cb0_is_integer;
198 bool is_msaa_resolve;
199 };
200
201 struct r600_sample_mask {
202 struct r600_atom atom;
203 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
204 };
205
206 struct r600_config_state {
207 struct r600_atom atom;
208 unsigned sq_gpr_resource_mgmt_1;
209 unsigned sq_gpr_resource_mgmt_2;
210 unsigned sq_gpr_resource_mgmt_3;
211 bool dyn_gpr_enabled;
212 };
213
214 struct r600_stencil_ref
215 {
216 ubyte ref_value[2];
217 ubyte valuemask[2];
218 ubyte writemask[2];
219 };
220
221 struct r600_stencil_ref_state {
222 struct r600_atom atom;
223 struct r600_stencil_ref state;
224 struct pipe_stencil_ref pipe_state;
225 };
226
227 struct r600_viewport_state {
228 struct r600_atom atom;
229 struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
230 uint32_t dirty_mask;
231 };
232
233 struct r600_shader_stages_state {
234 struct r600_atom atom;
235 unsigned geom_enable;
236 };
237
238 struct r600_gs_rings_state {
239 struct r600_atom atom;
240 unsigned enable;
241 struct pipe_constant_buffer esgs_ring;
242 struct pipe_constant_buffer gsvs_ring;
243 };
244
245 /* This must start from 16. */
246 /* features */
247 #define DBG_LLVM (1 << 29)
248 #define DBG_NO_CP_DMA (1 << 30)
249 /* shader backend */
250 #define DBG_NO_SB (1 << 21)
251 #define DBG_SB_CS (1 << 22)
252 #define DBG_SB_DRY_RUN (1 << 23)
253 #define DBG_SB_STAT (1 << 24)
254 #define DBG_SB_DUMP (1 << 25)
255 #define DBG_SB_NO_FALLBACK (1 << 26)
256 #define DBG_SB_DISASM (1 << 27)
257 #define DBG_SB_SAFEMATH (1 << 28)
258
259 struct r600_screen {
260 struct r600_common_screen b;
261 bool has_msaa;
262 bool has_compressed_msaa_texturing;
263
264 /*for compute global memory binding, we allocate stuff here, instead of
265 * buffers.
266 * XXX: Not sure if this is the best place for global_pool. Also,
267 * it's not thread safe, so it won't work with multiple contexts. */
268 struct compute_memory_pool *global_pool;
269 };
270
271 struct r600_pipe_sampler_view {
272 struct pipe_sampler_view base;
273 struct list_head list;
274 struct r600_resource *tex_resource;
275 uint32_t tex_resource_words[8];
276 bool skip_mip_address_reloc;
277 bool is_stencil_sampler;
278 };
279
280 struct r600_rasterizer_state {
281 struct r600_command_buffer buffer;
282 boolean flatshade;
283 boolean two_side;
284 unsigned sprite_coord_enable;
285 unsigned clip_plane_enable;
286 unsigned pa_sc_line_stipple;
287 unsigned pa_cl_clip_cntl;
288 unsigned pa_su_sc_mode_cntl;
289 float offset_units;
290 float offset_scale;
291 bool offset_enable;
292 bool scissor_enable;
293 bool multisample_enable;
294 };
295
296 struct r600_poly_offset_state {
297 struct r600_atom atom;
298 enum pipe_format zs_format;
299 float offset_units;
300 float offset_scale;
301 };
302
303 struct r600_blend_state {
304 struct r600_command_buffer buffer;
305 struct r600_command_buffer buffer_no_blend;
306 unsigned cb_target_mask;
307 unsigned cb_color_control;
308 unsigned cb_color_control_no_blend;
309 bool dual_src_blend;
310 bool alpha_to_one;
311 };
312
313 struct r600_dsa_state {
314 struct r600_command_buffer buffer;
315 unsigned alpha_ref;
316 ubyte valuemask[2];
317 ubyte writemask[2];
318 unsigned zwritemask;
319 unsigned sx_alpha_test_control;
320 };
321
322 struct r600_pipe_shader;
323
324 struct r600_pipe_shader_selector {
325 struct r600_pipe_shader *current;
326
327 struct tgsi_token *tokens;
328 struct pipe_stream_output_info so;
329 struct tgsi_shader_info info;
330
331 unsigned num_shaders;
332
333 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
334 unsigned type;
335
336 /* geometry shader properties */
337 unsigned gs_output_prim;
338 unsigned gs_max_out_vertices;
339 unsigned gs_num_invocations;
340
341 /* TCS/VS */
342 uint64_t lds_patch_outputs_written_mask;
343 uint64_t lds_outputs_written_mask;
344 unsigned nr_ps_max_color_exports;
345 };
346
347 struct r600_pipe_sampler_state {
348 uint32_t tex_sampler_words[3];
349 union pipe_color_union border_color;
350 bool border_color_use;
351 bool seamless_cube_map;
352 };
353
354 /* needed for blitter save */
355 #define NUM_TEX_UNITS 16
356
357 struct r600_seamless_cube_map {
358 struct r600_atom atom;
359 bool enabled;
360 };
361
362 struct r600_samplerview_state {
363 struct r600_atom atom;
364 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
365 uint32_t enabled_mask;
366 uint32_t dirty_mask;
367 uint32_t compressed_depthtex_mask; /* which textures are depth */
368 uint32_t compressed_colortex_mask;
369 boolean dirty_buffer_constants;
370 };
371
372 struct r600_sampler_states {
373 struct r600_atom atom;
374 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
375 uint32_t enabled_mask;
376 uint32_t dirty_mask;
377 uint32_t has_bordercolor_mask; /* which states contain the border color */
378 };
379
380 struct r600_textures_info {
381 struct r600_samplerview_state views;
382 struct r600_sampler_states states;
383 bool is_array_sampler[NUM_TEX_UNITS];
384 };
385
386 struct r600_shader_driver_constants_info {
387 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
388 uint32_t *constants;
389 uint32_t alloc_size;
390 bool vs_ucp_dirty;
391 bool texture_const_dirty;
392 bool ps_sample_pos_dirty;
393 };
394
395 struct r600_constbuf_state
396 {
397 struct r600_atom atom;
398 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
399 uint32_t enabled_mask;
400 uint32_t dirty_mask;
401 };
402
403 struct r600_vertexbuf_state
404 {
405 struct r600_atom atom;
406 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
407 uint32_t enabled_mask; /* non-NULL buffers */
408 uint32_t dirty_mask;
409 };
410
411 /* CSO (constant state object, in other words, immutable state). */
412 struct r600_cso_state
413 {
414 struct r600_atom atom;
415 void *cso; /* e.g. r600_blend_state */
416 struct r600_command_buffer *cb;
417 };
418
419 struct r600_scissor_state
420 {
421 struct r600_atom atom;
422 struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
423 uint32_t dirty_mask;
424 bool enable; /* r6xx only */
425 };
426
427 struct r600_fetch_shader {
428 struct r600_resource *buffer;
429 unsigned offset;
430 };
431
432 struct r600_shader_state {
433 struct r600_atom atom;
434 struct r600_pipe_shader *shader;
435 };
436
437 struct r600_context {
438 struct r600_common_context b;
439 struct r600_screen *screen;
440 struct blitter_context *blitter;
441 struct u_suballocator *allocator_fetch_shader;
442
443 /* Hardware info. */
444 boolean has_vertex_cache;
445 boolean keep_tiling_flags;
446 unsigned default_gprs[EG_NUM_HW_STAGES];
447 unsigned current_gprs[EG_NUM_HW_STAGES];
448 unsigned r6xx_num_clause_temp_gprs;
449
450 /* Miscellaneous state objects. */
451 void *custom_dsa_flush;
452 void *custom_blend_resolve;
453 void *custom_blend_decompress;
454 void *custom_blend_fastclear;
455 /* With rasterizer discard, there doesn't have to be a pixel shader.
456 * In that case, we bind this one: */
457 void *dummy_pixel_shader;
458 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
459 * bug where valid CMASK and FMASK are required to be present to avoid
460 * a hardlock in certain operations but aren't actually used
461 * for anything useful. */
462 struct r600_resource *dummy_fmask;
463 struct r600_resource *dummy_cmask;
464
465 /* State binding slots are here. */
466 struct r600_atom *atoms[R600_NUM_ATOMS];
467 /* Dirty atom bitmask for fast tests */
468 uint64_t dirty_atoms;
469 /* States for CS initialization. */
470 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
471 /** Compute specific registers initializations. The start_cs_cmd atom
472 * must be emitted before start_compute_cs_cmd. */
473 struct r600_command_buffer start_compute_cs_cmd;
474 /* Register states. */
475 struct r600_alphatest_state alphatest_state;
476 struct r600_cso_state blend_state;
477 struct r600_blend_color blend_color;
478 struct r600_cb_misc_state cb_misc_state;
479 struct r600_clip_misc_state clip_misc_state;
480 struct r600_clip_state clip_state;
481 struct r600_db_misc_state db_misc_state;
482 struct r600_db_state db_state;
483 struct r600_cso_state dsa_state;
484 struct r600_framebuffer framebuffer;
485 struct r600_poly_offset_state poly_offset_state;
486 struct r600_cso_state rasterizer_state;
487 struct r600_sample_mask sample_mask;
488 struct r600_scissor_state scissor;
489 struct r600_seamless_cube_map seamless_cube_map;
490 struct r600_config_state config_state;
491 struct r600_stencil_ref_state stencil_ref;
492 struct r600_vgt_state vgt_state;
493 struct r600_viewport_state viewport;
494 /* Shaders and shader resources. */
495 struct r600_cso_state vertex_fetch_shader;
496 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
497 struct r600_cs_shader_state cs_shader_state;
498 struct r600_shader_stages_state shader_stages;
499 struct r600_gs_rings_state gs_rings;
500 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
501 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
502
503 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
504
505 /** Vertex buffers for fetch shaders */
506 struct r600_vertexbuf_state vertex_buffer_state;
507 /** Vertex buffers for compute shaders */
508 struct r600_vertexbuf_state cs_vertex_buffer_state;
509
510 /* Additional context states. */
511 unsigned compute_cb_target_mask;
512 struct r600_pipe_shader_selector *ps_shader;
513 struct r600_pipe_shader_selector *vs_shader;
514 struct r600_pipe_shader_selector *gs_shader;
515
516 struct r600_pipe_shader_selector *tcs_shader;
517 struct r600_pipe_shader_selector *tes_shader;
518
519 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
520
521 struct r600_rasterizer_state *rasterizer;
522 bool alpha_to_one;
523 bool force_blend_disable;
524 boolean dual_src_blend;
525 unsigned zwritemask;
526 int ps_iter_samples;
527
528 /* Index buffer. */
529 struct pipe_index_buffer index_buffer;
530
531 /* Last draw state (-1 = unset). */
532 int last_primitive_type; /* Last primitive type used in draw_vbo. */
533 int last_start_instance;
534
535 void *sb_context;
536 struct r600_isa *isa;
537 float sample_positions[4 * 16];
538 float tess_state[8];
539 bool tess_state_dirty;
540 struct r600_pipe_shader_selector *last_ls;
541 struct r600_pipe_shader_selector *last_tcs;
542 unsigned last_num_tcs_input_cp;
543 unsigned lds_alloc;
544 };
545
546 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
547 struct r600_command_buffer *cb)
548 {
549 assert(cs->cdw + cb->num_dw <= cs->max_dw);
550 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
551 cs->cdw += cb->num_dw;
552 }
553
554 static inline void r600_set_atom_dirty(struct r600_context *rctx,
555 struct r600_atom *atom,
556 bool dirty)
557 {
558 uint64_t mask;
559
560 assert(atom->id != 0);
561 assert(atom->id < sizeof(mask) * 8);
562 mask = 1ull << atom->id;
563 if (dirty)
564 rctx->dirty_atoms |= mask;
565 else
566 rctx->dirty_atoms &= ~mask;
567 }
568
569 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
570 struct r600_atom *atom)
571 {
572 r600_set_atom_dirty(rctx, atom, true);
573 }
574
575 void r600_trace_emit(struct r600_context *rctx);
576
577 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
578 {
579 atom->emit(&rctx->b, atom);
580 r600_set_atom_dirty(rctx, atom, false);
581 if (rctx->screen->b.trace_bo) {
582 r600_trace_emit(rctx);
583 }
584 }
585
586 static inline void r600_set_cso_state(struct r600_context *rctx,
587 struct r600_cso_state *state, void *cso)
588 {
589 state->cso = cso;
590 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
591 }
592
593 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
594 struct r600_cso_state *state, void *cso,
595 struct r600_command_buffer *cb)
596 {
597 state->cb = cb;
598 state->atom.num_dw = cb ? cb->num_dw : 0;
599 r600_set_cso_state(rctx, state, cso);
600 }
601
602 /* compute_memory_pool.c */
603 struct compute_memory_pool;
604 void compute_memory_pool_delete(struct compute_memory_pool* pool);
605 struct compute_memory_pool* compute_memory_pool_new(
606 struct r600_screen *rscreen);
607
608 /* evergreen_state.c */
609 struct pipe_sampler_view *
610 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
611 struct pipe_resource *texture,
612 const struct pipe_sampler_view *state,
613 unsigned width0, unsigned height0,
614 unsigned force_level);
615 void evergreen_init_common_regs(struct r600_context *ctx,
616 struct r600_command_buffer *cb,
617 enum chip_class ctx_chip_class,
618 enum radeon_family ctx_family,
619 int ctx_drm_minor);
620 void cayman_init_common_regs(struct r600_command_buffer *cb,
621 enum chip_class ctx_chip_class,
622 enum radeon_family ctx_family,
623 int ctx_drm_minor);
624
625 void evergreen_init_state_functions(struct r600_context *rctx);
626 void evergreen_init_atom_start_cs(struct r600_context *rctx);
627 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
628 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
629 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
630 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
631 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
632 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
633 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
634 void *evergreen_create_resolve_blend(struct r600_context *rctx);
635 void *evergreen_create_decompress_blend(struct r600_context *rctx);
636 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
637 boolean evergreen_is_format_supported(struct pipe_screen *screen,
638 enum pipe_format format,
639 enum pipe_texture_target target,
640 unsigned sample_count,
641 unsigned usage);
642 void evergreen_init_color_surface(struct r600_context *rctx,
643 struct r600_surface *surf);
644 void evergreen_init_color_surface_rat(struct r600_context *rctx,
645 struct r600_surface *surf);
646 void evergreen_update_db_shader_control(struct r600_context * rctx);
647 bool evergreen_adjust_gprs(struct r600_context *rctx);
648 /* r600_blit.c */
649 void r600_init_blit_functions(struct r600_context *rctx);
650 void r600_decompress_depth_textures(struct r600_context *rctx,
651 struct r600_samplerview_state *textures);
652 void r600_decompress_color_textures(struct r600_context *rctx,
653 struct r600_samplerview_state *textures);
654 void r600_resource_copy_region(struct pipe_context *ctx,
655 struct pipe_resource *dst,
656 unsigned dst_level,
657 unsigned dstx, unsigned dsty, unsigned dstz,
658 struct pipe_resource *src,
659 unsigned src_level,
660 const struct pipe_box *src_box);
661
662 /* r600_shader.c */
663 int r600_pipe_shader_create(struct pipe_context *ctx,
664 struct r600_pipe_shader *shader,
665 union r600_shader_key key);
666
667 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
668
669 /* r600_state.c */
670 struct pipe_sampler_view *
671 r600_create_sampler_view_custom(struct pipe_context *ctx,
672 struct pipe_resource *texture,
673 const struct pipe_sampler_view *state,
674 unsigned width_first_level, unsigned height_first_level);
675 void r600_init_state_functions(struct r600_context *rctx);
676 void r600_init_atom_start_cs(struct r600_context *rctx);
677 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
678 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
679 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
680 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
681 void *r600_create_db_flush_dsa(struct r600_context *rctx);
682 void *r600_create_resolve_blend(struct r600_context *rctx);
683 void *r700_create_resolve_blend(struct r600_context *rctx);
684 void *r600_create_decompress_blend(struct r600_context *rctx);
685 bool r600_adjust_gprs(struct r600_context *rctx);
686 boolean r600_is_format_supported(struct pipe_screen *screen,
687 enum pipe_format format,
688 enum pipe_texture_target target,
689 unsigned sample_count,
690 unsigned usage);
691 void r600_update_db_shader_control(struct r600_context * rctx);
692
693 /* r600_hw_context.c */
694 void r600_context_gfx_flush(void *context, unsigned flags,
695 struct pipe_fence_handle **fence);
696 void r600_begin_new_cs(struct r600_context *ctx);
697 void r600_flush_emit(struct r600_context *ctx);
698 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
699 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
700 struct pipe_resource *dst, uint64_t dst_offset,
701 struct pipe_resource *src, uint64_t src_offset,
702 unsigned size);
703 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
704 struct pipe_resource *dst, uint64_t offset,
705 unsigned size, uint32_t clear_value);
706 void r600_dma_copy_buffer(struct r600_context *rctx,
707 struct pipe_resource *dst,
708 struct pipe_resource *src,
709 uint64_t dst_offset,
710 uint64_t src_offset,
711 uint64_t size);
712
713 /*
714 * evergreen_hw_context.c
715 */
716 void evergreen_dma_copy_buffer(struct r600_context *rctx,
717 struct pipe_resource *dst,
718 struct pipe_resource *src,
719 uint64_t dst_offset,
720 uint64_t src_offset,
721 uint64_t size);
722 void evergreen_setup_tess_constants(struct r600_context *rctx,
723 const struct pipe_draw_info *info,
724 unsigned *num_patches);
725 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
726 const struct pipe_draw_info *info,
727 unsigned num_patches);
728 void evergreen_set_ls_hs_config(struct r600_context *rctx,
729 struct radeon_winsys_cs *cs,
730 uint32_t ls_hs_config);
731 void evergreen_set_lds_alloc(struct r600_context *rctx,
732 struct radeon_winsys_cs *cs,
733 uint32_t lds_alloc);
734
735 /* r600_state_common.c */
736 void r600_init_common_state_functions(struct r600_context *rctx);
737 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
738 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
739 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
740 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
741 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
742 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
743 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
744 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
745 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
746 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
747 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
748 unsigned num_dw);
749 void r600_vertex_buffers_dirty(struct r600_context *rctx);
750 void r600_sampler_views_dirty(struct r600_context *rctx,
751 struct r600_samplerview_state *state);
752 void r600_sampler_states_dirty(struct r600_context *rctx,
753 struct r600_sampler_states *state);
754 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
755 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
756 uint32_t r600_translate_stencil_op(int s_op);
757 uint32_t r600_translate_fill(uint32_t func);
758 unsigned r600_tex_wrap(unsigned wrap);
759 unsigned r600_tex_filter(unsigned filter);
760 unsigned r600_tex_mipfilter(unsigned filter);
761 unsigned r600_tex_compare(unsigned compare);
762 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
763 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
764 struct pipe_resource *texture,
765 const struct pipe_surface *templ,
766 unsigned width, unsigned height);
767 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
768 const unsigned char *swizzle_view,
769 boolean vtx);
770 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
771 const unsigned char *swizzle_view,
772 uint32_t *word4_p, uint32_t *yuv_format_p);
773 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
774 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
775
776 /* r600_uvd.c */
777 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
778 const struct pipe_video_codec *decoder);
779
780 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
781 const struct pipe_video_buffer *tmpl);
782
783 /*
784 * Helpers for building command buffers
785 */
786
787 #define PKT3_SET_CONFIG_REG 0x68
788 #define PKT3_SET_CONTEXT_REG 0x69
789 #define PKT3_SET_CTL_CONST 0x6F
790 #define PKT3_SET_LOOP_CONST 0x6C
791
792 #define R600_CONFIG_REG_OFFSET 0x08000
793 #define R600_CONTEXT_REG_OFFSET 0x28000
794 #define R600_CTL_CONST_OFFSET 0x3CFF0
795 #define R600_LOOP_CONST_OFFSET 0X0003E200
796 #define EG_LOOP_CONST_OFFSET 0x0003A200
797
798 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
799 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
800 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
801 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
802 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
803
804 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
805
806 /*Evergreen Compute packet3*/
807 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
808
809 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
810 {
811 cb->buf[cb->num_dw++] = value;
812 }
813
814 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
815 {
816 assert(cb->num_dw+num <= cb->max_num_dw);
817 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
818 cb->num_dw += num;
819 }
820
821 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
822 {
823 assert(reg < R600_CONTEXT_REG_OFFSET);
824 assert(cb->num_dw+2+num <= cb->max_num_dw);
825 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
826 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
827 }
828
829 /**
830 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
831 * shaders.
832 */
833 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
834 {
835 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
836 assert(cb->num_dw+2+num <= cb->max_num_dw);
837 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
838 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
839 }
840
841 /**
842 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
843 * shaders.
844 */
845 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
846 {
847 assert(reg >= R600_CTL_CONST_OFFSET);
848 assert(cb->num_dw+2+num <= cb->max_num_dw);
849 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
850 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
851 }
852
853 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
854 {
855 assert(reg >= R600_LOOP_CONST_OFFSET);
856 assert(cb->num_dw+2+num <= cb->max_num_dw);
857 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
858 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
859 }
860
861 /**
862 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
863 * shaders.
864 */
865 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
866 {
867 assert(reg >= EG_LOOP_CONST_OFFSET);
868 assert(cb->num_dw+2+num <= cb->max_num_dw);
869 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
870 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
871 }
872
873 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
874 {
875 r600_store_config_reg_seq(cb, reg, 1);
876 r600_store_value(cb, value);
877 }
878
879 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
880 {
881 r600_store_context_reg_seq(cb, reg, 1);
882 r600_store_value(cb, value);
883 }
884
885 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
886 {
887 r600_store_ctl_const_seq(cb, reg, 1);
888 r600_store_value(cb, value);
889 }
890
891 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
892 {
893 r600_store_loop_const_seq(cb, reg, 1);
894 r600_store_value(cb, value);
895 }
896
897 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
898 {
899 eg_store_loop_const_seq(cb, reg, 1);
900 r600_store_value(cb, value);
901 }
902
903 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
904 void r600_release_command_buffer(struct r600_command_buffer *cb);
905
906 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
907 {
908 radeon_set_context_reg_seq(cs, reg, num);
909 /* Set the compute bit on the packet header */
910 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
911 }
912
913 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
914 {
915 assert(reg >= R600_CTL_CONST_OFFSET);
916 assert(cs->cdw+2+num <= cs->max_dw);
917 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
918 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
919 }
920
921 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
922 {
923 radeon_compute_set_context_reg_seq(cs, reg, 1);
924 radeon_emit(cs, value);
925 }
926
927 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
928 {
929 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
930 radeon_compute_set_context_reg(cs, reg, value);
931 } else {
932 radeon_set_context_reg(cs, reg, value);
933 }
934 }
935
936 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
937 {
938 radeon_set_ctl_const_seq(cs, reg, 1);
939 radeon_emit(cs, value);
940 }
941
942 /*
943 * common helpers
944 */
945 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
946 {
947 return value * (1 << frac_bits);
948 }
949
950 /* 12.4 fixed-point */
951 static inline unsigned r600_pack_float_12p4(float x)
952 {
953 return x <= 0 ? 0 :
954 x >= 4096 ? 0xffff : x * 16;
955 }
956
957 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
958 static inline bool r600_can_read_depth(struct r600_texture *rtex)
959 {
960 return rtex->resource.b.b.nr_samples <= 1 &&
961 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
962 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
963 }
964
965 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
966 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
967 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
968
969 unsigned r600_conv_prim_to_gs_out(unsigned mode);
970 #endif