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r600g: Implement POLYGON_OFFSET_UNITS_UNSCALED
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
36 #include "util/u_memory.h"
37
38 #include "tgsi/tgsi_scan.h"
39
40 #define R600_NUM_ATOMS 52
41
42 /* read caches */
43 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
44 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
45 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
46 /* read-write caches */
47 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
48 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
49 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
52 /* engine synchronization */
53 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
54 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
55 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
56
57 /* the number of CS dwords for flushing and drawing */
58 #define R600_MAX_FLUSH_CS_DWORDS 18
59 #define R600_MAX_DRAW_CS_DWORDS 58
60 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
61
62 #define R600_MAX_USER_CONST_BUFFERS 13
63 #define R600_MAX_DRIVER_CONST_BUFFERS 3
64 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
65
66 /* start driver buffers after user buffers */
67 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
68 #define R600_UCP_SIZE (4*4*8)
69 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
70
71 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
72 /*
73 * Note GS doesn't use a constant buffer binding, just a resource index,
74 * so it's fine to have it exist at index 16.
75 */
76 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
77 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
78 * of 16 const buffers.
79 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
80 *
81 * In order to support d3d 11 mandated minimum of 15 user const buffers
82 * we'd have to squash all use cases into one driver buffer.
83 */
84 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
85
86 /* HW stages */
87 #define R600_HW_STAGE_PS 0
88 #define R600_HW_STAGE_VS 1
89 #define R600_HW_STAGE_GS 2
90 #define R600_HW_STAGE_ES 3
91 #define EG_HW_STAGE_LS 4
92 #define EG_HW_STAGE_HS 5
93
94 #define R600_NUM_HW_STAGES 4
95 #define EG_NUM_HW_STAGES 6
96
97 struct r600_context;
98 struct r600_bytecode;
99 union r600_shader_key;
100
101 /* This is an atom containing GPU commands that never change.
102 * This is supposed to be copied directly into the CS. */
103 struct r600_command_buffer {
104 uint32_t *buf;
105 unsigned num_dw;
106 unsigned max_num_dw;
107 unsigned pkt_flags;
108 };
109
110 struct r600_db_state {
111 struct r600_atom atom;
112 struct r600_surface *rsurf;
113 };
114
115 struct r600_db_misc_state {
116 struct r600_atom atom;
117 bool occlusion_queries_disabled;
118 bool flush_depthstencil_through_cb;
119 bool flush_depth_inplace;
120 bool flush_stencil_inplace;
121 bool copy_depth, copy_stencil;
122 unsigned copy_sample;
123 unsigned log_samples;
124 unsigned db_shader_control;
125 bool htile_clear;
126 uint8_t ps_conservative_z;
127 };
128
129 struct r600_cb_misc_state {
130 struct r600_atom atom;
131 unsigned cb_color_control; /* this comes from blend state */
132 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
133 unsigned nr_cbufs;
134 unsigned nr_ps_color_outputs;
135 bool multiwrite;
136 bool dual_src_blend;
137 };
138
139 struct r600_clip_misc_state {
140 struct r600_atom atom;
141 unsigned pa_cl_clip_cntl; /* from rasterizer */
142 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
143 unsigned clip_plane_enable; /* from rasterizer */
144 unsigned clip_dist_write; /* from vertex shader */
145 boolean clip_disable; /* from vertex shader */
146 boolean vs_out_viewport; /* from vertex shader */
147 };
148
149 struct r600_alphatest_state {
150 struct r600_atom atom;
151 unsigned sx_alpha_test_control; /* this comes from dsa state */
152 unsigned sx_alpha_ref; /* this comes from dsa state */
153 bool bypass;
154 bool cb0_export_16bpc; /* from set_framebuffer_state */
155 };
156
157 struct r600_vgt_state {
158 struct r600_atom atom;
159 uint32_t vgt_multi_prim_ib_reset_en;
160 uint32_t vgt_multi_prim_ib_reset_indx;
161 uint32_t vgt_indx_offset;
162 bool last_draw_was_indirect;
163 };
164
165 struct r600_blend_color {
166 struct r600_atom atom;
167 struct pipe_blend_color state;
168 };
169
170 struct r600_clip_state {
171 struct r600_atom atom;
172 struct pipe_clip_state state;
173 };
174
175 struct r600_cs_shader_state {
176 struct r600_atom atom;
177 unsigned kernel_index;
178 unsigned pc;
179 struct r600_pipe_compute *shader;
180 };
181
182 struct r600_framebuffer {
183 struct r600_atom atom;
184 struct pipe_framebuffer_state state;
185 unsigned compressed_cb_mask;
186 unsigned nr_samples;
187 bool export_16bpc;
188 bool cb0_is_integer;
189 bool is_msaa_resolve;
190 };
191
192 struct r600_sample_mask {
193 struct r600_atom atom;
194 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
195 };
196
197 struct r600_config_state {
198 struct r600_atom atom;
199 unsigned sq_gpr_resource_mgmt_1;
200 unsigned sq_gpr_resource_mgmt_2;
201 unsigned sq_gpr_resource_mgmt_3;
202 bool dyn_gpr_enabled;
203 };
204
205 struct r600_stencil_ref
206 {
207 ubyte ref_value[2];
208 ubyte valuemask[2];
209 ubyte writemask[2];
210 };
211
212 struct r600_stencil_ref_state {
213 struct r600_atom atom;
214 struct r600_stencil_ref state;
215 struct pipe_stencil_ref pipe_state;
216 };
217
218 struct r600_shader_stages_state {
219 struct r600_atom atom;
220 unsigned geom_enable;
221 };
222
223 struct r600_gs_rings_state {
224 struct r600_atom atom;
225 unsigned enable;
226 struct pipe_constant_buffer esgs_ring;
227 struct pipe_constant_buffer gsvs_ring;
228 };
229
230 /* This must start from 16. */
231 /* features */
232 #define DBG_NO_CP_DMA (1 << 30)
233 /* shader backend */
234 #define DBG_NO_SB (1 << 21)
235 #define DBG_SB_CS (1 << 22)
236 #define DBG_SB_DRY_RUN (1 << 23)
237 #define DBG_SB_STAT (1 << 24)
238 #define DBG_SB_DUMP (1 << 25)
239 #define DBG_SB_NO_FALLBACK (1 << 26)
240 #define DBG_SB_DISASM (1 << 27)
241 #define DBG_SB_SAFEMATH (1 << 28)
242
243 struct r600_screen {
244 struct r600_common_screen b;
245 bool has_msaa;
246 bool has_compressed_msaa_texturing;
247
248 /*for compute global memory binding, we allocate stuff here, instead of
249 * buffers.
250 * XXX: Not sure if this is the best place for global_pool. Also,
251 * it's not thread safe, so it won't work with multiple contexts. */
252 struct compute_memory_pool *global_pool;
253 };
254
255 struct r600_pipe_sampler_view {
256 struct pipe_sampler_view base;
257 struct list_head list;
258 struct r600_resource *tex_resource;
259 uint32_t tex_resource_words[8];
260 bool skip_mip_address_reloc;
261 bool is_stencil_sampler;
262 };
263
264 struct r600_rasterizer_state {
265 struct r600_command_buffer buffer;
266 boolean flatshade;
267 boolean two_side;
268 unsigned sprite_coord_enable;
269 unsigned clip_plane_enable;
270 unsigned pa_sc_line_stipple;
271 unsigned pa_cl_clip_cntl;
272 unsigned pa_su_sc_mode_cntl;
273 float offset_units;
274 float offset_scale;
275 bool offset_enable;
276 bool offset_units_unscaled;
277 bool scissor_enable;
278 bool multisample_enable;
279 };
280
281 struct r600_poly_offset_state {
282 struct r600_atom atom;
283 enum pipe_format zs_format;
284 float offset_units;
285 float offset_scale;
286 bool offset_units_unscaled;
287 };
288
289 struct r600_blend_state {
290 struct r600_command_buffer buffer;
291 struct r600_command_buffer buffer_no_blend;
292 unsigned cb_target_mask;
293 unsigned cb_color_control;
294 unsigned cb_color_control_no_blend;
295 bool dual_src_blend;
296 bool alpha_to_one;
297 };
298
299 struct r600_dsa_state {
300 struct r600_command_buffer buffer;
301 unsigned alpha_ref;
302 ubyte valuemask[2];
303 ubyte writemask[2];
304 unsigned zwritemask;
305 unsigned sx_alpha_test_control;
306 };
307
308 struct r600_pipe_shader;
309
310 struct r600_pipe_shader_selector {
311 struct r600_pipe_shader *current;
312
313 struct tgsi_token *tokens;
314 struct pipe_stream_output_info so;
315 struct tgsi_shader_info info;
316
317 unsigned num_shaders;
318
319 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
320 unsigned type;
321
322 /* geometry shader properties */
323 unsigned gs_output_prim;
324 unsigned gs_max_out_vertices;
325 unsigned gs_num_invocations;
326
327 /* TCS/VS */
328 uint64_t lds_patch_outputs_written_mask;
329 uint64_t lds_outputs_written_mask;
330 unsigned nr_ps_max_color_exports;
331 };
332
333 struct r600_pipe_sampler_state {
334 uint32_t tex_sampler_words[3];
335 union pipe_color_union border_color;
336 bool border_color_use;
337 bool seamless_cube_map;
338 };
339
340 /* needed for blitter save */
341 #define NUM_TEX_UNITS 16
342
343 struct r600_seamless_cube_map {
344 struct r600_atom atom;
345 bool enabled;
346 };
347
348 struct r600_samplerview_state {
349 struct r600_atom atom;
350 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
351 uint32_t enabled_mask;
352 uint32_t dirty_mask;
353 uint32_t compressed_depthtex_mask; /* which textures are depth */
354 uint32_t compressed_colortex_mask;
355 boolean dirty_buffer_constants;
356 };
357
358 struct r600_sampler_states {
359 struct r600_atom atom;
360 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
361 uint32_t enabled_mask;
362 uint32_t dirty_mask;
363 uint32_t has_bordercolor_mask; /* which states contain the border color */
364 };
365
366 struct r600_textures_info {
367 struct r600_samplerview_state views;
368 struct r600_sampler_states states;
369 bool is_array_sampler[NUM_TEX_UNITS];
370 };
371
372 struct r600_shader_driver_constants_info {
373 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
374 uint32_t *constants;
375 uint32_t alloc_size;
376 bool vs_ucp_dirty;
377 bool texture_const_dirty;
378 bool ps_sample_pos_dirty;
379 };
380
381 struct r600_constbuf_state
382 {
383 struct r600_atom atom;
384 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
385 uint32_t enabled_mask;
386 uint32_t dirty_mask;
387 };
388
389 struct r600_vertexbuf_state
390 {
391 struct r600_atom atom;
392 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
393 uint32_t enabled_mask; /* non-NULL buffers */
394 uint32_t dirty_mask;
395 };
396
397 /* CSO (constant state object, in other words, immutable state). */
398 struct r600_cso_state
399 {
400 struct r600_atom atom;
401 void *cso; /* e.g. r600_blend_state */
402 struct r600_command_buffer *cb;
403 };
404
405 struct r600_fetch_shader {
406 struct r600_resource *buffer;
407 unsigned offset;
408 };
409
410 struct r600_shader_state {
411 struct r600_atom atom;
412 struct r600_pipe_shader *shader;
413 };
414
415 struct r600_context {
416 struct r600_common_context b;
417 struct r600_screen *screen;
418 struct blitter_context *blitter;
419 struct u_suballocator *allocator_fetch_shader;
420
421 /* Hardware info. */
422 boolean has_vertex_cache;
423 unsigned default_gprs[EG_NUM_HW_STAGES];
424 unsigned current_gprs[EG_NUM_HW_STAGES];
425 unsigned r6xx_num_clause_temp_gprs;
426
427 /* Miscellaneous state objects. */
428 void *custom_dsa_flush;
429 void *custom_blend_resolve;
430 void *custom_blend_decompress;
431 void *custom_blend_fastclear;
432 /* With rasterizer discard, there doesn't have to be a pixel shader.
433 * In that case, we bind this one: */
434 void *dummy_pixel_shader;
435 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
436 * bug where valid CMASK and FMASK are required to be present to avoid
437 * a hardlock in certain operations but aren't actually used
438 * for anything useful. */
439 struct r600_resource *dummy_fmask;
440 struct r600_resource *dummy_cmask;
441
442 /* State binding slots are here. */
443 struct r600_atom *atoms[R600_NUM_ATOMS];
444 /* Dirty atom bitmask for fast tests */
445 uint64_t dirty_atoms;
446 /* States for CS initialization. */
447 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
448 /** Compute specific registers initializations. The start_cs_cmd atom
449 * must be emitted before start_compute_cs_cmd. */
450 struct r600_command_buffer start_compute_cs_cmd;
451 /* Register states. */
452 struct r600_alphatest_state alphatest_state;
453 struct r600_cso_state blend_state;
454 struct r600_blend_color blend_color;
455 struct r600_cb_misc_state cb_misc_state;
456 struct r600_clip_misc_state clip_misc_state;
457 struct r600_clip_state clip_state;
458 struct r600_db_misc_state db_misc_state;
459 struct r600_db_state db_state;
460 struct r600_cso_state dsa_state;
461 struct r600_framebuffer framebuffer;
462 struct r600_poly_offset_state poly_offset_state;
463 struct r600_cso_state rasterizer_state;
464 struct r600_sample_mask sample_mask;
465 struct r600_seamless_cube_map seamless_cube_map;
466 struct r600_config_state config_state;
467 struct r600_stencil_ref_state stencil_ref;
468 struct r600_vgt_state vgt_state;
469 /* Shaders and shader resources. */
470 struct r600_cso_state vertex_fetch_shader;
471 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
472 struct r600_cs_shader_state cs_shader_state;
473 struct r600_shader_stages_state shader_stages;
474 struct r600_gs_rings_state gs_rings;
475 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
476 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
477
478 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
479
480 /** Vertex buffers for fetch shaders */
481 struct r600_vertexbuf_state vertex_buffer_state;
482 /** Vertex buffers for compute shaders */
483 struct r600_vertexbuf_state cs_vertex_buffer_state;
484
485 /* Additional context states. */
486 unsigned compute_cb_target_mask;
487 struct r600_pipe_shader_selector *ps_shader;
488 struct r600_pipe_shader_selector *vs_shader;
489 struct r600_pipe_shader_selector *gs_shader;
490
491 struct r600_pipe_shader_selector *tcs_shader;
492 struct r600_pipe_shader_selector *tes_shader;
493
494 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
495
496 struct r600_rasterizer_state *rasterizer;
497 bool alpha_to_one;
498 bool force_blend_disable;
499 boolean dual_src_blend;
500 unsigned zwritemask;
501 int ps_iter_samples;
502
503 /* Index buffer. */
504 struct pipe_index_buffer index_buffer;
505
506 /* Last draw state (-1 = unset). */
507 int last_primitive_type; /* Last primitive type used in draw_vbo. */
508 int last_start_instance;
509
510 void *sb_context;
511 struct r600_isa *isa;
512 float sample_positions[4 * 16];
513 float tess_state[8];
514 bool tess_state_dirty;
515 struct r600_pipe_shader_selector *last_ls;
516 struct r600_pipe_shader_selector *last_tcs;
517 unsigned last_num_tcs_input_cp;
518 unsigned lds_alloc;
519 };
520
521 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
522 struct r600_command_buffer *cb)
523 {
524 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
525 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
526 cs->current.cdw += cb->num_dw;
527 }
528
529 static inline void r600_set_atom_dirty(struct r600_context *rctx,
530 struct r600_atom *atom,
531 bool dirty)
532 {
533 uint64_t mask;
534
535 assert(atom->id != 0);
536 assert(atom->id < sizeof(mask) * 8);
537 mask = 1ull << atom->id;
538 if (dirty)
539 rctx->dirty_atoms |= mask;
540 else
541 rctx->dirty_atoms &= ~mask;
542 }
543
544 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
545 struct r600_atom *atom)
546 {
547 r600_set_atom_dirty(rctx, atom, true);
548 }
549
550 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
551 {
552 atom->emit(&rctx->b, atom);
553 r600_set_atom_dirty(rctx, atom, false);
554 }
555
556 static inline void r600_set_cso_state(struct r600_context *rctx,
557 struct r600_cso_state *state, void *cso)
558 {
559 state->cso = cso;
560 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
561 }
562
563 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
564 struct r600_cso_state *state, void *cso,
565 struct r600_command_buffer *cb)
566 {
567 state->cb = cb;
568 state->atom.num_dw = cb ? cb->num_dw : 0;
569 r600_set_cso_state(rctx, state, cso);
570 }
571
572 /* compute_memory_pool.c */
573 struct compute_memory_pool;
574 void compute_memory_pool_delete(struct compute_memory_pool* pool);
575 struct compute_memory_pool* compute_memory_pool_new(
576 struct r600_screen *rscreen);
577
578 /* evergreen_state.c */
579 struct pipe_sampler_view *
580 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
581 struct pipe_resource *texture,
582 const struct pipe_sampler_view *state,
583 unsigned width0, unsigned height0,
584 unsigned force_level);
585 void evergreen_init_common_regs(struct r600_context *ctx,
586 struct r600_command_buffer *cb,
587 enum chip_class ctx_chip_class,
588 enum radeon_family ctx_family,
589 int ctx_drm_minor);
590 void cayman_init_common_regs(struct r600_command_buffer *cb,
591 enum chip_class ctx_chip_class,
592 enum radeon_family ctx_family,
593 int ctx_drm_minor);
594
595 void evergreen_init_state_functions(struct r600_context *rctx);
596 void evergreen_init_atom_start_cs(struct r600_context *rctx);
597 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
598 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
599 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
600 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
601 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
602 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
603 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
604 void *evergreen_create_resolve_blend(struct r600_context *rctx);
605 void *evergreen_create_decompress_blend(struct r600_context *rctx);
606 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
607 boolean evergreen_is_format_supported(struct pipe_screen *screen,
608 enum pipe_format format,
609 enum pipe_texture_target target,
610 unsigned sample_count,
611 unsigned usage);
612 void evergreen_init_color_surface(struct r600_context *rctx,
613 struct r600_surface *surf);
614 void evergreen_init_color_surface_rat(struct r600_context *rctx,
615 struct r600_surface *surf);
616 void evergreen_update_db_shader_control(struct r600_context * rctx);
617 bool evergreen_adjust_gprs(struct r600_context *rctx);
618 /* r600_blit.c */
619 void r600_init_blit_functions(struct r600_context *rctx);
620 void r600_decompress_depth_textures(struct r600_context *rctx,
621 struct r600_samplerview_state *textures);
622 void r600_decompress_color_textures(struct r600_context *rctx,
623 struct r600_samplerview_state *textures);
624 void r600_resource_copy_region(struct pipe_context *ctx,
625 struct pipe_resource *dst,
626 unsigned dst_level,
627 unsigned dstx, unsigned dsty, unsigned dstz,
628 struct pipe_resource *src,
629 unsigned src_level,
630 const struct pipe_box *src_box);
631
632 /* r600_shader.c */
633 int r600_pipe_shader_create(struct pipe_context *ctx,
634 struct r600_pipe_shader *shader,
635 union r600_shader_key key);
636
637 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
638
639 /* r600_state.c */
640 struct pipe_sampler_view *
641 r600_create_sampler_view_custom(struct pipe_context *ctx,
642 struct pipe_resource *texture,
643 const struct pipe_sampler_view *state,
644 unsigned width_first_level, unsigned height_first_level);
645 void r600_init_state_functions(struct r600_context *rctx);
646 void r600_init_atom_start_cs(struct r600_context *rctx);
647 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
648 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
649 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
650 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
651 void *r600_create_db_flush_dsa(struct r600_context *rctx);
652 void *r600_create_resolve_blend(struct r600_context *rctx);
653 void *r700_create_resolve_blend(struct r600_context *rctx);
654 void *r600_create_decompress_blend(struct r600_context *rctx);
655 bool r600_adjust_gprs(struct r600_context *rctx);
656 boolean r600_is_format_supported(struct pipe_screen *screen,
657 enum pipe_format format,
658 enum pipe_texture_target target,
659 unsigned sample_count,
660 unsigned usage);
661 void r600_update_db_shader_control(struct r600_context * rctx);
662
663 /* r600_hw_context.c */
664 void r600_context_gfx_flush(void *context, unsigned flags,
665 struct pipe_fence_handle **fence);
666 void r600_begin_new_cs(struct r600_context *ctx);
667 void r600_flush_emit(struct r600_context *ctx);
668 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
669 void r600_emit_pfp_sync_me(struct r600_context *rctx);
670 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
671 struct pipe_resource *dst, uint64_t dst_offset,
672 struct pipe_resource *src, uint64_t src_offset,
673 unsigned size);
674 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
675 struct pipe_resource *dst, uint64_t offset,
676 unsigned size, uint32_t clear_value,
677 enum r600_coherency coher);
678 void r600_dma_copy_buffer(struct r600_context *rctx,
679 struct pipe_resource *dst,
680 struct pipe_resource *src,
681 uint64_t dst_offset,
682 uint64_t src_offset,
683 uint64_t size);
684
685 /*
686 * evergreen_hw_context.c
687 */
688 void evergreen_dma_copy_buffer(struct r600_context *rctx,
689 struct pipe_resource *dst,
690 struct pipe_resource *src,
691 uint64_t dst_offset,
692 uint64_t src_offset,
693 uint64_t size);
694 void evergreen_setup_tess_constants(struct r600_context *rctx,
695 const struct pipe_draw_info *info,
696 unsigned *num_patches);
697 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
698 const struct pipe_draw_info *info,
699 unsigned num_patches);
700 void evergreen_set_ls_hs_config(struct r600_context *rctx,
701 struct radeon_winsys_cs *cs,
702 uint32_t ls_hs_config);
703 void evergreen_set_lds_alloc(struct r600_context *rctx,
704 struct radeon_winsys_cs *cs,
705 uint32_t lds_alloc);
706
707 /* r600_state_common.c */
708 void r600_init_common_state_functions(struct r600_context *rctx);
709 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
710 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
711 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
712 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
713 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
714 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
715 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
716 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
717 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
718 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
719 unsigned num_dw);
720 void r600_vertex_buffers_dirty(struct r600_context *rctx);
721 void r600_sampler_views_dirty(struct r600_context *rctx,
722 struct r600_samplerview_state *state);
723 void r600_sampler_states_dirty(struct r600_context *rctx,
724 struct r600_sampler_states *state);
725 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
726 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
727 uint32_t r600_translate_stencil_op(int s_op);
728 uint32_t r600_translate_fill(uint32_t func);
729 unsigned r600_tex_wrap(unsigned wrap);
730 unsigned r600_tex_mipfilter(unsigned filter);
731 unsigned r600_tex_compare(unsigned compare);
732 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
733 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
734 struct pipe_resource *texture,
735 const struct pipe_surface *templ,
736 unsigned width, unsigned height);
737 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
738 const unsigned char *swizzle_view,
739 boolean vtx);
740 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
741 const unsigned char *swizzle_view,
742 uint32_t *word4_p, uint32_t *yuv_format_p,
743 bool do_endian_swap);
744 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
745 bool do_endian_swap);
746 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
747
748 /* r600_uvd.c */
749 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
750 const struct pipe_video_codec *decoder);
751
752 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
753 const struct pipe_video_buffer *tmpl);
754
755 /*
756 * Helpers for building command buffers
757 */
758
759 #define PKT3_SET_CONFIG_REG 0x68
760 #define PKT3_SET_CONTEXT_REG 0x69
761 #define PKT3_SET_CTL_CONST 0x6F
762 #define PKT3_SET_LOOP_CONST 0x6C
763
764 #define R600_CONFIG_REG_OFFSET 0x08000
765 #define R600_CONTEXT_REG_OFFSET 0x28000
766 #define R600_CTL_CONST_OFFSET 0x3CFF0
767 #define R600_LOOP_CONST_OFFSET 0X0003E200
768 #define EG_LOOP_CONST_OFFSET 0x0003A200
769
770 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
771 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
772 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
773 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
774 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
775
776 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
777
778 /*Evergreen Compute packet3*/
779 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
780
781 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
782 {
783 cb->buf[cb->num_dw++] = value;
784 }
785
786 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
787 {
788 assert(cb->num_dw+num <= cb->max_num_dw);
789 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
790 cb->num_dw += num;
791 }
792
793 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
794 {
795 assert(reg < R600_CONTEXT_REG_OFFSET);
796 assert(cb->num_dw+2+num <= cb->max_num_dw);
797 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
798 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
799 }
800
801 /**
802 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
803 * shaders.
804 */
805 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
806 {
807 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
808 assert(cb->num_dw+2+num <= cb->max_num_dw);
809 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
810 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
811 }
812
813 /**
814 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
815 * shaders.
816 */
817 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
818 {
819 assert(reg >= R600_CTL_CONST_OFFSET);
820 assert(cb->num_dw+2+num <= cb->max_num_dw);
821 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
822 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
823 }
824
825 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
826 {
827 assert(reg >= R600_LOOP_CONST_OFFSET);
828 assert(cb->num_dw+2+num <= cb->max_num_dw);
829 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
830 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
831 }
832
833 /**
834 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
835 * shaders.
836 */
837 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
838 {
839 assert(reg >= EG_LOOP_CONST_OFFSET);
840 assert(cb->num_dw+2+num <= cb->max_num_dw);
841 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
842 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
843 }
844
845 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
846 {
847 r600_store_config_reg_seq(cb, reg, 1);
848 r600_store_value(cb, value);
849 }
850
851 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
852 {
853 r600_store_context_reg_seq(cb, reg, 1);
854 r600_store_value(cb, value);
855 }
856
857 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
858 {
859 r600_store_ctl_const_seq(cb, reg, 1);
860 r600_store_value(cb, value);
861 }
862
863 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
864 {
865 r600_store_loop_const_seq(cb, reg, 1);
866 r600_store_value(cb, value);
867 }
868
869 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
870 {
871 eg_store_loop_const_seq(cb, reg, 1);
872 r600_store_value(cb, value);
873 }
874
875 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
876 void r600_release_command_buffer(struct r600_command_buffer *cb);
877
878 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
879 {
880 radeon_set_context_reg_seq(cs, reg, num);
881 /* Set the compute bit on the packet header */
882 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
883 }
884
885 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
886 {
887 assert(reg >= R600_CTL_CONST_OFFSET);
888 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
889 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
890 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
891 }
892
893 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
894 {
895 radeon_compute_set_context_reg_seq(cs, reg, 1);
896 radeon_emit(cs, value);
897 }
898
899 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
900 {
901 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
902 radeon_compute_set_context_reg(cs, reg, value);
903 } else {
904 radeon_set_context_reg(cs, reg, value);
905 }
906 }
907
908 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
909 {
910 radeon_set_ctl_const_seq(cs, reg, 1);
911 radeon_emit(cs, value);
912 }
913
914 /*
915 * common helpers
916 */
917 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
918 {
919 return value * (1 << frac_bits);
920 }
921
922 /* 12.4 fixed-point */
923 static inline unsigned r600_pack_float_12p4(float x)
924 {
925 return x <= 0 ? 0 :
926 x >= 4096 ? 0xffff : x * 16;
927 }
928
929 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
930 static inline bool r600_can_read_depth(struct r600_texture *rtex)
931 {
932 return rtex->resource.b.b.nr_samples <= 1 &&
933 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
934 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
935 }
936
937 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
938 {
939 switch (coher) {
940 default:
941 case R600_COHERENCY_NONE:
942 return 0;
943 case R600_COHERENCY_SHADER:
944 return R600_CONTEXT_INV_CONST_CACHE |
945 R600_CONTEXT_INV_VERTEX_CACHE |
946 R600_CONTEXT_INV_TEX_CACHE |
947 R600_CONTEXT_STREAMOUT_FLUSH;
948 case R600_COHERENCY_CB_META:
949 return R600_CONTEXT_FLUSH_AND_INV_CB |
950 R600_CONTEXT_FLUSH_AND_INV_CB_META;
951 }
952 }
953
954 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
955 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
956 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
957
958 unsigned r600_conv_prim_to_gs_out(unsigned mode);
959 #endif