2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon_video.h"
40 #include <sys/utsname.h>
47 #include <llvm-c/TargetMachine.h>
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
54 struct r600_multi_fence
{
55 struct pipe_reference reference
;
56 struct pipe_fence_handle
*gfx
;
57 struct pipe_fence_handle
*sdma
;
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
61 struct r600_common_context
*ctx
;
67 * shader binary helpers.
69 void radeon_shader_binary_init(struct ac_shader_binary
*b
)
71 memset(b
, 0, sizeof(*b
));
74 void radeon_shader_binary_clean(struct ac_shader_binary
*b
)
81 FREE(b
->global_symbol_offsets
);
83 FREE(b
->disasm_string
);
84 FREE(b
->llvm_ir_string
);
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
102 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
103 unsigned event
, unsigned event_flags
,
105 struct r600_resource
*buf
, uint64_t va
,
106 uint32_t new_fence
, unsigned query_type
)
108 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
109 unsigned op
= EVENT_TYPE(event
) |
112 unsigned sel
= EOP_DATA_SEL(data_sel
);
114 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
117 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
118 radeon_emit(cs
, new_fence
); /* immediate data */
119 radeon_emit(cs
, 0); /* unused */
122 r600_emit_reloc(ctx
, &ctx
->gfx
, buf
, RADEON_USAGE_WRITE
,
126 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
)
130 if (!screen
->info
.has_virtual_memory
)
136 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
137 uint64_t va
, uint32_t ref
, uint32_t mask
)
139 struct radeon_winsys_cs
*cs
= ctx
->gfx
.cs
;
141 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
142 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
144 radeon_emit(cs
, va
>> 32);
145 radeon_emit(cs
, ref
); /* reference value */
146 radeon_emit(cs
, mask
); /* mask */
147 radeon_emit(cs
, 4); /* poll interval */
150 void r600_draw_rectangle(struct blitter_context
*blitter
,
151 void *vertex_elements_cso
,
152 blitter_get_vs_func get_vs
,
153 int x1
, int y1
, int x2
, int y2
,
154 float depth
, unsigned num_instances
,
155 enum blitter_attrib_type type
,
156 const union blitter_attrib
*attrib
)
158 struct r600_common_context
*rctx
=
159 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
160 struct pipe_viewport_state viewport
;
161 struct pipe_resource
*buf
= NULL
;
165 rctx
->b
.bind_vertex_elements_state(&rctx
->b
, vertex_elements_cso
);
166 rctx
->b
.bind_vs_state(&rctx
->b
, get_vs(blitter
));
168 /* Some operations (like color resolve on r6xx) don't work
169 * with the conventional primitive types.
170 * One that works is PT_RECTLIST, which we use here. */
173 viewport
.scale
[0] = 1.0f
;
174 viewport
.scale
[1] = 1.0f
;
175 viewport
.scale
[2] = 1.0f
;
176 viewport
.translate
[0] = 0.0f
;
177 viewport
.translate
[1] = 0.0f
;
178 viewport
.translate
[2] = 0.0f
;
179 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
181 /* Upload vertices. The hw rectangle has only 3 vertices,
182 * The 4th one is derived from the first 3.
183 * The vertex specification should match u_blitter's vertex element state. */
184 u_upload_alloc(rctx
->b
.stream_uploader
, 0, sizeof(float) * 24,
185 rctx
->screen
->info
.tcc_cache_line_size
,
186 &offset
, &buf
, (void**)&vb
);
206 case UTIL_BLITTER_ATTRIB_COLOR
:
207 memcpy(vb
+4, attrib
->color
, sizeof(float)*4);
208 memcpy(vb
+12, attrib
->color
, sizeof(float)*4);
209 memcpy(vb
+20, attrib
->color
, sizeof(float)*4);
211 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
212 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
213 vb
[6] = vb
[14] = vb
[22] = attrib
->texcoord
.z
;
214 vb
[7] = vb
[15] = vb
[23] = attrib
->texcoord
.w
;
216 vb
[4] = attrib
->texcoord
.x1
;
217 vb
[5] = attrib
->texcoord
.y1
;
218 vb
[12] = attrib
->texcoord
.x1
;
219 vb
[13] = attrib
->texcoord
.y2
;
220 vb
[20] = attrib
->texcoord
.x2
;
221 vb
[21] = attrib
->texcoord
.y1
;
223 default:; /* Nothing to do. */
227 struct pipe_vertex_buffer vbuffer
= {};
228 vbuffer
.buffer
.resource
= buf
;
229 vbuffer
.stride
= 2 * 4 * sizeof(float); /* vertex size */
230 vbuffer
.buffer_offset
= offset
;
232 rctx
->b
.set_vertex_buffers(&rctx
->b
, blitter
->vb_slot
, 1, &vbuffer
);
233 util_draw_arrays_instanced(&rctx
->b
, R600_PRIM_RECTANGLE_LIST
, 0, 3,
235 pipe_resource_reference(&buf
, NULL
);
238 static void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
)
240 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
242 if (rctx
->chip_class
>= EVERGREEN
)
243 radeon_emit(cs
, 0xf0000000); /* NOP */
245 /* TODO: R600-R700 should use the FENCE packet.
246 * CS checker support is required. */
250 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
251 struct r600_resource
*dst
, struct r600_resource
*src
)
253 uint64_t vram
= ctx
->dma
.cs
->used_vram
;
254 uint64_t gtt
= ctx
->dma
.cs
->used_gart
;
257 vram
+= dst
->vram_usage
;
258 gtt
+= dst
->gart_usage
;
261 vram
+= src
->vram_usage
;
262 gtt
+= src
->gart_usage
;
265 /* Flush the GFX IB if DMA depends on it. */
266 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
268 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, dst
->buf
,
269 RADEON_USAGE_READWRITE
)) ||
271 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, src
->buf
,
272 RADEON_USAGE_WRITE
))))
273 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
275 /* Flush if there's not enough space, or if the memory usage per IB
278 * IBs using too little memory are limited by the IB submission overhead.
279 * IBs using too much memory are limited by the kernel/TTM overhead.
280 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
282 * This heuristic makes sure that DMA requests are executed
283 * very soon after the call is made and lowers memory usage.
284 * It improves texture upload performance by keeping the DMA
285 * engine busy while uploads are being submitted.
287 num_dw
++; /* for emit_wait_idle below */
288 if (!ctx
->ws
->cs_check_space(ctx
->dma
.cs
, num_dw
) ||
289 ctx
->dma
.cs
->used_vram
+ ctx
->dma
.cs
->used_gart
> 64 * 1024 * 1024 ||
290 !radeon_cs_memory_below_limit(ctx
->screen
, ctx
->dma
.cs
, vram
, gtt
)) {
291 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
292 assert((num_dw
+ ctx
->dma
.cs
->current
.cdw
) <= ctx
->dma
.cs
->current
.max_dw
);
295 /* Wait for idle if either buffer has been used in the IB before to
296 * prevent read-after-write hazards.
299 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, dst
->buf
,
300 RADEON_USAGE_READWRITE
)) ||
302 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, src
->buf
,
303 RADEON_USAGE_WRITE
)))
304 r600_dma_emit_wait_idle(ctx
);
306 /* If GPUVM is not supported, the CS checker needs 2 entries
307 * in the buffer list per packet, which has to be done manually.
309 if (ctx
->screen
->info
.has_virtual_memory
) {
311 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, dst
,
313 RADEON_PRIO_SDMA_BUFFER
);
315 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, src
,
317 RADEON_PRIO_SDMA_BUFFER
);
320 /* this function is called before all DMA calls, so increment this. */
321 ctx
->num_dma_calls
++;
324 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
326 /* suspend queries */
327 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
328 r600_suspend_queries(ctx
);
330 ctx
->streamout
.suspended
= false;
331 if (ctx
->streamout
.begin_emitted
) {
332 r600_emit_streamout_end(ctx
);
333 ctx
->streamout
.suspended
= true;
337 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
339 if (ctx
->streamout
.suspended
) {
340 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
341 r600_streamout_buffers_dirty(ctx
);
345 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
346 r600_resume_queries(ctx
);
349 static void r600_add_fence_dependency(struct r600_common_context
*rctx
,
350 struct pipe_fence_handle
*fence
)
352 struct radeon_winsys
*ws
= rctx
->ws
;
355 ws
->cs_add_fence_dependency(rctx
->dma
.cs
, fence
);
356 ws
->cs_add_fence_dependency(rctx
->gfx
.cs
, fence
);
359 static void r600_fence_server_sync(struct pipe_context
*ctx
,
360 struct pipe_fence_handle
*fence
)
362 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
363 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
365 /* Only amdgpu needs to handle fence dependencies (for fence imports).
366 * radeon synchronizes all rings by default and will not implement
369 if (rctx
->screen
->info
.drm_major
== 2)
372 /* Only imported fences need to be handled by fence_server_sync,
373 * because the winsys handles synchronizations automatically for BOs
374 * within the process.
376 * Simply skip unflushed fences here, and the winsys will drop no-op
377 * dependencies (i.e. dependencies within the same ring).
379 if (rfence
->gfx_unflushed
.ctx
)
382 /* All unflushed commands will not start execution before
383 * this fence dependency is signalled.
385 * Should we flush the context to allow more GPU parallelism?
388 r600_add_fence_dependency(rctx
, rfence
->sdma
);
390 r600_add_fence_dependency(rctx
, rfence
->gfx
);
393 static void r600_flush_from_st(struct pipe_context
*ctx
,
394 struct pipe_fence_handle
**fence
,
397 struct pipe_screen
*screen
= ctx
->screen
;
398 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
399 struct radeon_winsys
*ws
= rctx
->ws
;
400 struct pipe_fence_handle
*gfx_fence
= NULL
;
401 struct pipe_fence_handle
*sdma_fence
= NULL
;
402 bool deferred_fence
= false;
403 unsigned rflags
= RADEON_FLUSH_ASYNC
;
405 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
406 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
408 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
410 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
412 if (!radeon_emitted(rctx
->gfx
.cs
, rctx
->initial_gfx_cs_size
)) {
414 ws
->fence_reference(&gfx_fence
, rctx
->last_gfx_fence
);
415 if (!(flags
& PIPE_FLUSH_DEFERRED
))
416 ws
->cs_sync_flush(rctx
->gfx
.cs
);
418 /* Instead of flushing, create a deferred fence. Constraints:
419 * - The state tracker must allow a deferred flush.
420 * - The state tracker must request a fence.
421 * Thread safety in fence_finish must be ensured by the state tracker.
423 if (flags
& PIPE_FLUSH_DEFERRED
&& fence
) {
424 gfx_fence
= rctx
->ws
->cs_get_next_fence(rctx
->gfx
.cs
);
425 deferred_fence
= true;
427 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
431 /* Both engines can signal out of order, so we need to keep both fences. */
433 struct r600_multi_fence
*multi_fence
=
434 CALLOC_STRUCT(r600_multi_fence
);
436 ws
->fence_reference(&sdma_fence
, NULL
);
437 ws
->fence_reference(&gfx_fence
, NULL
);
441 multi_fence
->reference
.count
= 1;
442 /* If both fences are NULL, fence_finish will always return true. */
443 multi_fence
->gfx
= gfx_fence
;
444 multi_fence
->sdma
= sdma_fence
;
446 if (deferred_fence
) {
447 multi_fence
->gfx_unflushed
.ctx
= rctx
;
448 multi_fence
->gfx_unflushed
.ib_index
= rctx
->num_gfx_cs_flushes
;
451 screen
->fence_reference(screen
, fence
, NULL
);
452 *fence
= (struct pipe_fence_handle
*)multi_fence
;
455 if (!(flags
& PIPE_FLUSH_DEFERRED
)) {
457 ws
->cs_sync_flush(rctx
->dma
.cs
);
458 ws
->cs_sync_flush(rctx
->gfx
.cs
);
462 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
463 struct pipe_fence_handle
**fence
)
465 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
466 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
467 struct radeon_saved_cs saved
;
469 (rctx
->screen
->debug_flags
& DBG_CHECK_VM
) &&
470 rctx
->check_vm_faults
;
472 if (!radeon_emitted(cs
, 0)) {
474 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
479 radeon_save_cs(rctx
->ws
, cs
, &saved
, true);
481 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
483 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
486 /* Use conservative timeout 800ms, after which we won't wait any
487 * longer and assume the GPU is hung.
489 rctx
->ws
->fence_wait(rctx
->ws
, rctx
->last_sdma_fence
, 800*1000*1000);
491 rctx
->check_vm_faults(rctx
, &saved
, RING_DMA
);
492 radeon_clear_saved_cs(&saved
);
497 * Store a linearized copy of all chunks of \p cs together with the buffer
500 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
501 struct radeon_saved_cs
*saved
, bool get_buffer_list
)
506 /* Save the IB chunks. */
507 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
508 saved
->ib
= MALLOC(4 * saved
->num_dw
);
513 for (i
= 0; i
< cs
->num_prev
; ++i
) {
514 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
515 buf
+= cs
->prev
[i
].cdw
;
517 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
519 if (!get_buffer_list
)
522 /* Save the buffer list. */
523 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
524 saved
->bo_list
= CALLOC(saved
->bo_count
,
525 sizeof(saved
->bo_list
[0]));
526 if (!saved
->bo_list
) {
530 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
535 fprintf(stderr
, "%s: out of memory\n", __func__
);
536 memset(saved
, 0, sizeof(*saved
));
539 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
)
542 FREE(saved
->bo_list
);
544 memset(saved
, 0, sizeof(*saved
));
547 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
549 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
550 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
551 RADEON_GPU_RESET_COUNTER
);
553 if (rctx
->gpu_reset_counter
== latest
)
554 return PIPE_NO_RESET
;
556 rctx
->gpu_reset_counter
= latest
;
557 return PIPE_UNKNOWN_CONTEXT_RESET
;
560 static void r600_set_debug_callback(struct pipe_context
*ctx
,
561 const struct pipe_debug_callback
*cb
)
563 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
568 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
571 static void r600_set_device_reset_callback(struct pipe_context
*ctx
,
572 const struct pipe_device_reset_callback
*cb
)
574 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
577 rctx
->device_reset_callback
= *cb
;
579 memset(&rctx
->device_reset_callback
, 0,
580 sizeof(rctx
->device_reset_callback
));
583 bool r600_check_device_reset(struct r600_common_context
*rctx
)
585 enum pipe_reset_status status
;
587 if (!rctx
->device_reset_callback
.reset
)
590 if (!rctx
->b
.get_device_reset_status
)
593 status
= rctx
->b
.get_device_reset_status(&rctx
->b
);
594 if (status
== PIPE_NO_RESET
)
597 rctx
->device_reset_callback
.reset(rctx
->device_reset_callback
.data
, status
);
601 static void r600_dma_clear_buffer_fallback(struct pipe_context
*ctx
,
602 struct pipe_resource
*dst
,
603 uint64_t offset
, uint64_t size
,
606 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
608 rctx
->clear_buffer(ctx
, dst
, offset
, size
, value
, R600_COHERENCY_NONE
);
611 static bool r600_resource_commit(struct pipe_context
*pctx
,
612 struct pipe_resource
*resource
,
613 unsigned level
, struct pipe_box
*box
,
616 struct r600_common_context
*ctx
= (struct r600_common_context
*)pctx
;
617 struct r600_resource
*res
= r600_resource(resource
);
620 * Since buffer commitment changes cannot be pipelined, we need to
621 * (a) flush any pending commands that refer to the buffer we're about
623 * (b) wait for threaded submit to finish, including those that were
624 * triggered by some other, earlier operation.
626 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
627 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
,
628 res
->buf
, RADEON_USAGE_READWRITE
)) {
629 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
631 if (radeon_emitted(ctx
->dma
.cs
, 0) &&
632 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
,
633 res
->buf
, RADEON_USAGE_READWRITE
)) {
634 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
637 ctx
->ws
->cs_sync_flush(ctx
->dma
.cs
);
638 ctx
->ws
->cs_sync_flush(ctx
->gfx
.cs
);
640 assert(resource
->target
== PIPE_BUFFER
);
642 return ctx
->ws
->buffer_commit(res
->buf
, box
->x
, box
->width
, commit
);
645 bool r600_common_context_init(struct r600_common_context
*rctx
,
646 struct r600_common_screen
*rscreen
,
647 unsigned context_flags
)
649 slab_create_child(&rctx
->pool_transfers
, &rscreen
->pool_transfers
);
650 slab_create_child(&rctx
->pool_transfers_unsync
, &rscreen
->pool_transfers
);
652 rctx
->screen
= rscreen
;
653 rctx
->ws
= rscreen
->ws
;
654 rctx
->family
= rscreen
->family
;
655 rctx
->chip_class
= rscreen
->chip_class
;
657 rctx
->b
.invalidate_resource
= r600_invalidate_resource
;
658 rctx
->b
.resource_commit
= r600_resource_commit
;
659 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
660 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
661 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
662 rctx
->b
.texture_subdata
= u_default_texture_subdata
;
663 rctx
->b
.flush
= r600_flush_from_st
;
664 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
665 rctx
->b
.fence_server_sync
= r600_fence_server_sync
;
666 rctx
->dma_clear_buffer
= r600_dma_clear_buffer_fallback
;
668 /* evergreen_compute.c has a special codepath for global buffers.
669 * Everything else can use the direct path.
671 if ((rscreen
->chip_class
== EVERGREEN
|| rscreen
->chip_class
== CAYMAN
) &&
672 (context_flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
673 rctx
->b
.buffer_subdata
= u_default_buffer_subdata
;
675 rctx
->b
.buffer_subdata
= r600_buffer_subdata
;
677 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
678 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
679 rctx
->gpu_reset_counter
=
680 rctx
->ws
->query_value(rctx
->ws
,
681 RADEON_GPU_RESET_COUNTER
);
684 rctx
->b
.set_device_reset_callback
= r600_set_device_reset_callback
;
686 r600_init_context_texture_functions(rctx
);
687 r600_init_viewport_functions(rctx
);
688 r600_streamout_init(rctx
);
689 r600_query_init(rctx
);
690 cayman_init_msaa(&rctx
->b
);
692 rctx
->allocator_zeroed_memory
=
693 u_suballocator_create(&rctx
->b
, rscreen
->info
.gart_page_size
,
694 0, PIPE_USAGE_DEFAULT
, 0, true);
695 if (!rctx
->allocator_zeroed_memory
)
698 rctx
->b
.stream_uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
699 0, PIPE_USAGE_STREAM
);
700 if (!rctx
->b
.stream_uploader
)
703 rctx
->b
.const_uploader
= u_upload_create(&rctx
->b
, 128 * 1024,
704 0, PIPE_USAGE_DEFAULT
);
705 if (!rctx
->b
.const_uploader
)
708 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
712 if (rscreen
->info
.num_sdma_rings
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
713 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
716 rctx
->dma
.flush
= r600_flush_dma_ring
;
722 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
724 if (rctx
->query_result_shader
)
725 rctx
->b
.delete_compute_state(&rctx
->b
, rctx
->query_result_shader
);
728 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
730 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
732 rctx
->ws
->ctx_destroy(rctx
->ctx
);
734 if (rctx
->b
.stream_uploader
)
735 u_upload_destroy(rctx
->b
.stream_uploader
);
736 if (rctx
->b
.const_uploader
)
737 u_upload_destroy(rctx
->b
.const_uploader
);
739 slab_destroy_child(&rctx
->pool_transfers
);
740 slab_destroy_child(&rctx
->pool_transfers_unsync
);
742 if (rctx
->allocator_zeroed_memory
) {
743 u_suballocator_destroy(rctx
->allocator_zeroed_memory
);
745 rctx
->ws
->fence_reference(&rctx
->last_gfx_fence
, NULL
);
746 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
747 r600_resource_reference(&rctx
->eop_bug_scratch
, NULL
);
754 static const struct debug_named_value common_debug_options
[] = {
756 { "tex", DBG_TEX
, "Print texture info" },
757 { "nir", DBG_NIR
, "Enable experimental NIR shaders" },
758 { "compute", DBG_COMPUTE
, "Print compute info" },
759 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
760 { "info", DBG_INFO
, "Print driver information" },
763 { "fs", DBG_FS
, "Print fetch shaders" },
764 { "vs", DBG_VS
, "Print vertex shaders" },
765 { "gs", DBG_GS
, "Print geometry shaders" },
766 { "ps", DBG_PS
, "Print pixel shaders" },
767 { "cs", DBG_CS
, "Print compute shaders" },
768 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
769 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
770 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
771 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
772 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
773 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
774 { "checkir", DBG_CHECK_IR
, "Enable additional sanity checks on shader IR" },
775 { "nooptvariant", DBG_NO_OPT_VARIANT
, "Disable compiling optimized shader variants." },
777 { "testdma", DBG_TEST_DMA
, "Invoke SDMA tests and exit." },
778 { "testvmfaultcp", DBG_TEST_VMFAULT_CP
, "Invoke a CP VM fault test and exit." },
779 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA
, "Invoke a SDMA VM fault test and exit." },
780 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER
, "Invoke a shader VM fault test and exit." },
783 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
784 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
785 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
786 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
787 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
788 { "notiling", DBG_NO_TILING
, "Disable tiling" },
789 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
790 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
791 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
792 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
793 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
794 { "unsafemath", DBG_UNSAFE_MATH
, "Enable unsafe math shader optimizations" },
796 DEBUG_NAMED_VALUE_END
/* must be last */
799 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
804 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
809 static const char *r600_get_marketing_name(struct radeon_winsys
*ws
)
811 if (!ws
->get_chip_name
)
813 return ws
->get_chip_name(ws
);
816 static const char *r600_get_family_name(const struct r600_common_screen
*rscreen
)
818 switch (rscreen
->info
.family
) {
819 case CHIP_R600
: return "AMD R600";
820 case CHIP_RV610
: return "AMD RV610";
821 case CHIP_RV630
: return "AMD RV630";
822 case CHIP_RV670
: return "AMD RV670";
823 case CHIP_RV620
: return "AMD RV620";
824 case CHIP_RV635
: return "AMD RV635";
825 case CHIP_RS780
: return "AMD RS780";
826 case CHIP_RS880
: return "AMD RS880";
827 case CHIP_RV770
: return "AMD RV770";
828 case CHIP_RV730
: return "AMD RV730";
829 case CHIP_RV710
: return "AMD RV710";
830 case CHIP_RV740
: return "AMD RV740";
831 case CHIP_CEDAR
: return "AMD CEDAR";
832 case CHIP_REDWOOD
: return "AMD REDWOOD";
833 case CHIP_JUNIPER
: return "AMD JUNIPER";
834 case CHIP_CYPRESS
: return "AMD CYPRESS";
835 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
836 case CHIP_PALM
: return "AMD PALM";
837 case CHIP_SUMO
: return "AMD SUMO";
838 case CHIP_SUMO2
: return "AMD SUMO2";
839 case CHIP_BARTS
: return "AMD BARTS";
840 case CHIP_TURKS
: return "AMD TURKS";
841 case CHIP_CAICOS
: return "AMD CAICOS";
842 case CHIP_CAYMAN
: return "AMD CAYMAN";
843 case CHIP_ARUBA
: return "AMD ARUBA";
844 default: return "AMD unknown";
848 static void r600_disk_cache_create(struct r600_common_screen
*rscreen
)
850 /* Don't use the cache if shader dumping is enabled. */
851 if (rscreen
->debug_flags
& DBG_ALL_SHADERS
)
854 uint32_t mesa_timestamp
;
855 if (disk_cache_get_function_timestamp(r600_disk_cache_create
,
860 res
= asprintf(×tamp_str
, "%u",mesa_timestamp
);
862 /* These flags affect shader compilation. */
863 uint64_t shader_debug_flags
=
864 rscreen
->debug_flags
&
865 (DBG_FS_CORRECT_DERIVS_AFTER_KILL
|
868 rscreen
->disk_shader_cache
=
869 disk_cache_create(r600_get_family_name(rscreen
),
877 static struct disk_cache
*r600_get_disk_shader_cache(struct pipe_screen
*pscreen
)
879 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
880 return rscreen
->disk_shader_cache
;
883 static const char* r600_get_name(struct pipe_screen
* pscreen
)
885 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
887 return rscreen
->renderer_string
;
890 static float r600_get_paramf(struct pipe_screen
* pscreen
,
891 enum pipe_capf param
)
893 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
896 case PIPE_CAPF_MAX_LINE_WIDTH
:
897 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
898 case PIPE_CAPF_MAX_POINT_WIDTH
:
899 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
900 if (rscreen
->family
>= CHIP_CEDAR
)
904 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
906 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
908 case PIPE_CAPF_GUARD_BAND_LEFT
:
909 case PIPE_CAPF_GUARD_BAND_TOP
:
910 case PIPE_CAPF_GUARD_BAND_RIGHT
:
911 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
917 static int r600_get_video_param(struct pipe_screen
*screen
,
918 enum pipe_video_profile profile
,
919 enum pipe_video_entrypoint entrypoint
,
920 enum pipe_video_cap param
)
923 case PIPE_VIDEO_CAP_SUPPORTED
:
924 return vl_profile_supported(screen
, profile
, entrypoint
);
925 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
927 case PIPE_VIDEO_CAP_MAX_WIDTH
:
928 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
929 return vl_video_buffer_max_size(screen
);
930 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
931 return PIPE_FORMAT_NV12
;
932 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
934 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
936 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
938 case PIPE_VIDEO_CAP_MAX_LEVEL
:
939 return vl_level_supported(screen
, profile
);
945 const char *r600_get_llvm_processor_name(enum radeon_family family
)
993 static unsigned get_max_threads_per_block(struct r600_common_screen
*screen
,
994 enum pipe_shader_ir ir_type
)
999 static int r600_get_compute_param(struct pipe_screen
*screen
,
1000 enum pipe_shader_ir ir_type
,
1001 enum pipe_compute_cap param
,
1004 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1006 //TODO: select these params by asic
1008 case PIPE_COMPUTE_CAP_IR_TARGET
: {
1010 const char *triple
= "r600--";
1011 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
1013 sprintf(ret
, "%s-%s", gpu
, triple
);
1015 /* +2 for dash and terminating NIL byte */
1016 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
1018 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
1020 uint64_t *grid_dimension
= ret
;
1021 grid_dimension
[0] = 3;
1023 return 1 * sizeof(uint64_t);
1025 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
1027 uint64_t *grid_size
= ret
;
1028 grid_size
[0] = 65535;
1029 grid_size
[1] = 65535;
1030 grid_size
[2] = 65535;
1032 return 3 * sizeof(uint64_t) ;
1034 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
1036 uint64_t *block_size
= ret
;
1037 unsigned threads_per_block
= get_max_threads_per_block(rscreen
, ir_type
);
1038 block_size
[0] = threads_per_block
;
1039 block_size
[1] = threads_per_block
;
1040 block_size
[2] = threads_per_block
;
1042 return 3 * sizeof(uint64_t);
1044 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
1046 uint64_t *max_threads_per_block
= ret
;
1047 *max_threads_per_block
= get_max_threads_per_block(rscreen
, ir_type
);
1049 return sizeof(uint64_t);
1050 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
1052 uint32_t *address_bits
= ret
;
1053 address_bits
[0] = 32;
1055 return 1 * sizeof(uint32_t);
1057 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
1059 uint64_t *max_global_size
= ret
;
1060 uint64_t max_mem_alloc_size
;
1062 r600_get_compute_param(screen
, ir_type
,
1063 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
1064 &max_mem_alloc_size
);
1066 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1067 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1068 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1069 * make sure we never report more than
1070 * 4 * MAX_MEM_ALLOC_SIZE.
1072 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
1073 MAX2(rscreen
->info
.gart_size
,
1074 rscreen
->info
.vram_size
));
1076 return sizeof(uint64_t);
1078 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
1080 uint64_t *max_local_size
= ret
;
1081 /* Value reported by the closed source driver. */
1082 *max_local_size
= 32768;
1084 return sizeof(uint64_t);
1086 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
1088 uint64_t *max_input_size
= ret
;
1089 /* Value reported by the closed source driver. */
1090 *max_input_size
= 1024;
1092 return sizeof(uint64_t);
1094 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
1096 uint64_t *max_mem_alloc_size
= ret
;
1098 *max_mem_alloc_size
= rscreen
->info
.max_alloc_size
;
1100 return sizeof(uint64_t);
1102 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
1104 uint32_t *max_clock_frequency
= ret
;
1105 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
1107 return sizeof(uint32_t);
1109 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
1111 uint32_t *max_compute_units
= ret
;
1112 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
1114 return sizeof(uint32_t);
1116 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
1118 uint32_t *images_supported
= ret
;
1119 *images_supported
= 0;
1121 return sizeof(uint32_t);
1122 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
1124 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
1126 uint32_t *subgroup_size
= ret
;
1127 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
1129 return sizeof(uint32_t);
1130 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
1132 uint64_t *max_variable_threads_per_block
= ret
;
1133 *max_variable_threads_per_block
= 0;
1135 return sizeof(uint64_t);
1138 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
1142 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
1144 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1146 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
1147 rscreen
->info
.clock_crystal_freq
;
1150 static void r600_fence_reference(struct pipe_screen
*screen
,
1151 struct pipe_fence_handle
**dst
,
1152 struct pipe_fence_handle
*src
)
1154 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
1155 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
1156 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
1158 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
1159 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
1160 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
1166 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
1167 struct pipe_context
*ctx
,
1168 struct pipe_fence_handle
*fence
,
1171 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
1172 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
1173 struct r600_common_context
*rctx
;
1174 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
1176 ctx
= threaded_context_unwrap_sync(ctx
);
1177 rctx
= ctx
? (struct r600_common_context
*)ctx
: NULL
;
1180 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
1183 /* Recompute the timeout after waiting. */
1184 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1185 int64_t time
= os_time_get_nano();
1186 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1193 /* Flush the gfx IB if it hasn't been flushed yet. */
1195 rfence
->gfx_unflushed
.ctx
== rctx
&&
1196 rfence
->gfx_unflushed
.ib_index
== rctx
->num_gfx_cs_flushes
) {
1197 rctx
->gfx
.flush(rctx
, timeout
? 0 : RADEON_FLUSH_ASYNC
, NULL
);
1198 rfence
->gfx_unflushed
.ctx
= NULL
;
1203 /* Recompute the timeout after all that. */
1204 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1205 int64_t time
= os_time_get_nano();
1206 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1210 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
1213 static void r600_query_memory_info(struct pipe_screen
*screen
,
1214 struct pipe_memory_info
*info
)
1216 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1217 struct radeon_winsys
*ws
= rscreen
->ws
;
1218 unsigned vram_usage
, gtt_usage
;
1220 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
1221 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
1223 /* The real TTM memory usage is somewhat random, because:
1225 * 1) TTM delays freeing memory, because it can only free it after
1228 * 2) The memory usage can be really low if big VRAM evictions are
1229 * taking place, but the real usage is well above the size of VRAM.
1231 * Instead, return statistics of this process.
1233 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
1234 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
1236 info
->avail_device_memory
=
1237 vram_usage
<= info
->total_device_memory
?
1238 info
->total_device_memory
- vram_usage
: 0;
1239 info
->avail_staging_memory
=
1240 gtt_usage
<= info
->total_staging_memory
?
1241 info
->total_staging_memory
- gtt_usage
: 0;
1243 info
->device_memory_evicted
=
1244 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
1246 if (rscreen
->info
.drm_major
== 3 && rscreen
->info
.drm_minor
>= 4)
1247 info
->nr_device_memory_evictions
=
1248 ws
->query_value(ws
, RADEON_NUM_EVICTIONS
);
1250 /* Just return the number of evicted 64KB pages. */
1251 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
1254 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
1255 const struct pipe_resource
*templ
)
1257 if (templ
->target
== PIPE_BUFFER
) {
1258 return r600_buffer_create(screen
, templ
, 256);
1260 return r600_texture_create(screen
, templ
);
1264 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
1265 struct radeon_winsys
*ws
)
1267 char family_name
[32] = {}, llvm_string
[32] = {}, kernel_version
[128] = {};
1268 struct utsname uname_data
;
1269 const char *chip_name
;
1271 ws
->query_info(ws
, &rscreen
->info
);
1274 if ((chip_name
= r600_get_marketing_name(ws
)))
1275 snprintf(family_name
, sizeof(family_name
), "%s / ",
1276 r600_get_family_name(rscreen
) + 4);
1278 chip_name
= r600_get_family_name(rscreen
);
1280 if (uname(&uname_data
) == 0)
1281 snprintf(kernel_version
, sizeof(kernel_version
),
1282 " / %s", uname_data
.release
);
1284 if (HAVE_LLVM
> 0) {
1285 snprintf(llvm_string
, sizeof(llvm_string
),
1286 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
1287 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
1290 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
1291 "%s (%sDRM %i.%i.%i%s%s)",
1292 chip_name
, family_name
, rscreen
->info
.drm_major
,
1293 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
1294 kernel_version
, llvm_string
);
1296 rscreen
->b
.get_name
= r600_get_name
;
1297 rscreen
->b
.get_vendor
= r600_get_vendor
;
1298 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
1299 rscreen
->b
.get_disk_shader_cache
= r600_get_disk_shader_cache
;
1300 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
1301 rscreen
->b
.get_paramf
= r600_get_paramf
;
1302 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
1303 rscreen
->b
.fence_finish
= r600_fence_finish
;
1304 rscreen
->b
.fence_reference
= r600_fence_reference
;
1305 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
1306 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
1307 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
1309 if (rscreen
->info
.has_hw_decode
) {
1310 rscreen
->b
.get_video_param
= rvid_get_video_param
;
1311 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
1313 rscreen
->b
.get_video_param
= r600_get_video_param
;
1314 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1317 r600_init_screen_texture_functions(rscreen
);
1318 r600_init_screen_query_functions(rscreen
);
1320 rscreen
->family
= rscreen
->info
.family
;
1321 rscreen
->chip_class
= rscreen
->info
.chip_class
;
1322 rscreen
->debug_flags
|= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
1324 r600_disk_cache_create(rscreen
);
1326 slab_create_parent(&rscreen
->pool_transfers
, sizeof(struct r600_transfer
), 64);
1328 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1329 if (rscreen
->force_aniso
>= 0) {
1330 printf("radeon: Forcing anisotropy filter to %ix\n",
1331 /* round down to a power of two */
1332 1 << util_logbase2(rscreen
->force_aniso
));
1335 (void) mtx_init(&rscreen
->aux_context_lock
, mtx_plain
);
1336 (void) mtx_init(&rscreen
->gpu_load_mutex
, mtx_plain
);
1338 if (rscreen
->debug_flags
& DBG_INFO
) {
1339 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1340 rscreen
->info
.pci_domain
, rscreen
->info
.pci_bus
,
1341 rscreen
->info
.pci_dev
, rscreen
->info
.pci_func
);
1342 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
1343 printf("family = %i (%s)\n", rscreen
->info
.family
,
1344 r600_get_family_name(rscreen
));
1345 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
1346 printf("pte_fragment_size = %u\n", rscreen
->info
.pte_fragment_size
);
1347 printf("gart_page_size = %u\n", rscreen
->info
.gart_page_size
);
1348 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
1349 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
1350 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_vis_size
, 1024*1024));
1351 printf("max_alloc_size = %i MB\n",
1352 (int)DIV_ROUND_UP(rscreen
->info
.max_alloc_size
, 1024*1024));
1353 printf("min_alloc_size = %u\n", rscreen
->info
.min_alloc_size
);
1354 printf("has_dedicated_vram = %u\n", rscreen
->info
.has_dedicated_vram
);
1355 printf("has_virtual_memory = %i\n", rscreen
->info
.has_virtual_memory
);
1356 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
1357 printf("has_hw_decode = %u\n", rscreen
->info
.has_hw_decode
);
1358 printf("num_sdma_rings = %i\n", rscreen
->info
.num_sdma_rings
);
1359 printf("num_compute_rings = %u\n", rscreen
->info
.num_compute_rings
);
1360 printf("uvd_fw_version = %u\n", rscreen
->info
.uvd_fw_version
);
1361 printf("vce_fw_version = %u\n", rscreen
->info
.vce_fw_version
);
1362 printf("me_fw_version = %i\n", rscreen
->info
.me_fw_version
);
1363 printf("pfp_fw_version = %i\n", rscreen
->info
.pfp_fw_version
);
1364 printf("ce_fw_version = %i\n", rscreen
->info
.ce_fw_version
);
1365 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
1366 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
1367 printf("tcc_cache_line_size = %u\n", rscreen
->info
.tcc_cache_line_size
);
1368 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
1369 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
1370 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
1371 printf("has_syncobj = %u\n", rscreen
->info
.has_syncobj
);
1373 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
1374 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
1375 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
1376 printf("max_se = %i\n", rscreen
->info
.max_se
);
1377 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
1379 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
1380 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
1381 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
1382 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
1383 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
1384 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
1385 printf("enabled_rb_mask = 0x%x\n", rscreen
->info
.enabled_rb_mask
);
1386 printf("max_alignment = %u\n", (unsigned)rscreen
->info
.max_alignment
);
1391 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
1393 r600_perfcounters_destroy(rscreen
);
1394 r600_gpu_load_kill_thread(rscreen
);
1396 mtx_destroy(&rscreen
->gpu_load_mutex
);
1397 mtx_destroy(&rscreen
->aux_context_lock
);
1398 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
1400 slab_destroy_parent(&rscreen
->pool_transfers
);
1402 disk_cache_destroy(rscreen
->disk_shader_cache
);
1403 rscreen
->ws
->destroy(rscreen
->ws
);
1407 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
1410 return rscreen
->debug_flags
& (1 << processor
);
1413 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
, unsigned processor
)
1415 return (rscreen
->debug_flags
& DBG_CHECK_IR
) ||
1416 r600_can_dump_shader(rscreen
, processor
);
1419 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1420 uint64_t offset
, uint64_t size
, unsigned value
)
1422 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1424 mtx_lock(&rscreen
->aux_context_lock
);
1425 rctx
->dma_clear_buffer(&rctx
->b
, dst
, offset
, size
, value
);
1426 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1427 mtx_unlock(&rscreen
->aux_context_lock
);