2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "compiler/nir/nir.h"
31 #include "util/list.h"
32 #include "util/u_draw_quad.h"
33 #include "util/u_memory.h"
34 #include "util/format/u_format_s3tc.h"
35 #include "util/u_upload_mgr.h"
36 #include "util/os_time.h"
37 #include "vl/vl_decoder.h"
38 #include "vl/vl_video_buffer.h"
39 #include "radeon_video.h"
41 #include <sys/utsname.h>
45 #include <llvm-c/TargetMachine.h>
48 struct r600_multi_fence
{
49 struct pipe_reference reference
;
50 struct pipe_fence_handle
*gfx
;
51 struct pipe_fence_handle
*sdma
;
53 /* If the context wasn't flushed at fence creation, this is non-NULL. */
55 struct r600_common_context
*ctx
;
67 * \param event EVENT_TYPE_*
68 * \param event_flags Optional cache flush flags (TC)
69 * \param data_sel 1 = fence, 3 = timestamp
71 * \param va GPU address
72 * \param old_value Previous fence value (for a bug workaround)
73 * \param new_value Fence value to write for this event.
75 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
76 unsigned event
, unsigned event_flags
,
78 struct r600_resource
*buf
, uint64_t va
,
79 uint32_t new_fence
, unsigned query_type
)
81 struct radeon_cmdbuf
*cs
= ctx
->gfx
.cs
;
82 unsigned op
= EVENT_TYPE(event
) |
85 unsigned sel
= EOP_DATA_SEL(data_sel
);
87 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE_EOP
, 4, 0));
90 radeon_emit(cs
, ((va
>> 32) & 0xffff) | sel
);
91 radeon_emit(cs
, new_fence
); /* immediate data */
92 radeon_emit(cs
, 0); /* unused */
95 r600_emit_reloc(ctx
, &ctx
->gfx
, buf
, RADEON_USAGE_WRITE
,
99 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
)
103 if (!screen
->info
.r600_has_virtual_memory
)
109 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
110 struct r600_resource
*buf
,
111 uint64_t va
, uint32_t ref
, uint32_t mask
)
113 struct radeon_cmdbuf
*cs
= ctx
->gfx
.cs
;
115 radeon_emit(cs
, PKT3(PKT3_WAIT_REG_MEM
, 5, 0));
116 radeon_emit(cs
, WAIT_REG_MEM_EQUAL
| WAIT_REG_MEM_MEM_SPACE(1));
118 radeon_emit(cs
, va
>> 32);
119 radeon_emit(cs
, ref
); /* reference value */
120 radeon_emit(cs
, mask
); /* mask */
121 radeon_emit(cs
, 4); /* poll interval */
124 r600_emit_reloc(ctx
, &ctx
->gfx
, buf
, RADEON_USAGE_READ
,
128 void r600_draw_rectangle(struct blitter_context
*blitter
,
129 void *vertex_elements_cso
,
130 blitter_get_vs_func get_vs
,
131 int x1
, int y1
, int x2
, int y2
,
132 float depth
, unsigned num_instances
,
133 enum blitter_attrib_type type
,
134 const union blitter_attrib
*attrib
)
136 struct r600_common_context
*rctx
=
137 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
138 struct pipe_viewport_state viewport
;
139 struct pipe_resource
*buf
= NULL
;
143 rctx
->b
.bind_vertex_elements_state(&rctx
->b
, vertex_elements_cso
);
144 rctx
->b
.bind_vs_state(&rctx
->b
, get_vs(blitter
));
146 /* Some operations (like color resolve on r6xx) don't work
147 * with the conventional primitive types.
148 * One that works is PT_RECTLIST, which we use here. */
151 viewport
.scale
[0] = 1.0f
;
152 viewport
.scale
[1] = 1.0f
;
153 viewport
.scale
[2] = 1.0f
;
154 viewport
.translate
[0] = 0.0f
;
155 viewport
.translate
[1] = 0.0f
;
156 viewport
.translate
[2] = 0.0f
;
157 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
159 /* Upload vertices. The hw rectangle has only 3 vertices,
160 * The 4th one is derived from the first 3.
161 * The vertex specification should match u_blitter's vertex element state. */
162 u_upload_alloc(rctx
->b
.stream_uploader
, 0, sizeof(float) * 24,
163 rctx
->screen
->info
.tcc_cache_line_size
,
164 &offset
, &buf
, (void**)&vb
);
184 case UTIL_BLITTER_ATTRIB_COLOR
:
185 memcpy(vb
+4, attrib
->color
, sizeof(float)*4);
186 memcpy(vb
+12, attrib
->color
, sizeof(float)*4);
187 memcpy(vb
+20, attrib
->color
, sizeof(float)*4);
189 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
190 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
191 vb
[6] = vb
[14] = vb
[22] = attrib
->texcoord
.z
;
192 vb
[7] = vb
[15] = vb
[23] = attrib
->texcoord
.w
;
194 vb
[4] = attrib
->texcoord
.x1
;
195 vb
[5] = attrib
->texcoord
.y1
;
196 vb
[12] = attrib
->texcoord
.x1
;
197 vb
[13] = attrib
->texcoord
.y2
;
198 vb
[20] = attrib
->texcoord
.x2
;
199 vb
[21] = attrib
->texcoord
.y1
;
201 default:; /* Nothing to do. */
205 struct pipe_vertex_buffer vbuffer
= {};
206 vbuffer
.buffer
.resource
= buf
;
207 vbuffer
.stride
= 2 * 4 * sizeof(float); /* vertex size */
208 vbuffer
.buffer_offset
= offset
;
210 rctx
->b
.set_vertex_buffers(&rctx
->b
, blitter
->vb_slot
, 1, &vbuffer
);
211 util_draw_arrays_instanced(&rctx
->b
, R600_PRIM_RECTANGLE_LIST
, 0, 3,
213 pipe_resource_reference(&buf
, NULL
);
216 static void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
)
218 struct radeon_cmdbuf
*cs
= rctx
->dma
.cs
;
220 if (rctx
->chip_class
>= EVERGREEN
)
221 radeon_emit(cs
, 0xf0000000); /* NOP */
223 /* TODO: R600-R700 should use the FENCE packet.
224 * CS checker support is required. */
228 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
229 struct r600_resource
*dst
, struct r600_resource
*src
)
231 uint64_t vram
= ctx
->dma
.cs
->used_vram
;
232 uint64_t gtt
= ctx
->dma
.cs
->used_gart
;
235 vram
+= dst
->vram_usage
;
236 gtt
+= dst
->gart_usage
;
239 vram
+= src
->vram_usage
;
240 gtt
+= src
->gart_usage
;
243 /* Flush the GFX IB if DMA depends on it. */
244 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
246 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, dst
->buf
,
247 RADEON_USAGE_READWRITE
)) ||
249 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, src
->buf
,
250 RADEON_USAGE_WRITE
))))
251 ctx
->gfx
.flush(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
253 /* Flush if there's not enough space, or if the memory usage per IB
256 * IBs using too little memory are limited by the IB submission overhead.
257 * IBs using too much memory are limited by the kernel/TTM overhead.
258 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
260 * This heuristic makes sure that DMA requests are executed
261 * very soon after the call is made and lowers memory usage.
262 * It improves texture upload performance by keeping the DMA
263 * engine busy while uploads are being submitted.
265 num_dw
++; /* for emit_wait_idle below */
266 if (!ctx
->ws
->cs_check_space(ctx
->dma
.cs
, num_dw
, false) ||
267 ctx
->dma
.cs
->used_vram
+ ctx
->dma
.cs
->used_gart
> 64 * 1024 * 1024 ||
268 !radeon_cs_memory_below_limit(ctx
->screen
, ctx
->dma
.cs
, vram
, gtt
)) {
269 ctx
->dma
.flush(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
270 assert((num_dw
+ ctx
->dma
.cs
->current
.cdw
) <= ctx
->dma
.cs
->current
.max_dw
);
273 /* Wait for idle if either buffer has been used in the IB before to
274 * prevent read-after-write hazards.
277 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, dst
->buf
,
278 RADEON_USAGE_READWRITE
)) ||
280 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
, src
->buf
,
281 RADEON_USAGE_WRITE
)))
282 r600_dma_emit_wait_idle(ctx
);
284 /* If GPUVM is not supported, the CS checker needs 2 entries
285 * in the buffer list per packet, which has to be done manually.
287 if (ctx
->screen
->info
.r600_has_virtual_memory
) {
289 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, dst
,
290 RADEON_USAGE_WRITE
, 0);
292 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, src
,
293 RADEON_USAGE_READ
, 0);
296 /* this function is called before all DMA calls, so increment this. */
297 ctx
->num_dma_calls
++;
300 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
302 /* suspend queries */
303 if (!list_is_empty(&ctx
->active_queries
))
304 r600_suspend_queries(ctx
);
306 ctx
->streamout
.suspended
= false;
307 if (ctx
->streamout
.begin_emitted
) {
308 r600_emit_streamout_end(ctx
);
309 ctx
->streamout
.suspended
= true;
313 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
315 if (ctx
->streamout
.suspended
) {
316 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
317 r600_streamout_buffers_dirty(ctx
);
321 if (!list_is_empty(&ctx
->active_queries
))
322 r600_resume_queries(ctx
);
325 static void r600_fence_server_sync(struct pipe_context
*ctx
,
326 struct pipe_fence_handle
*fence
)
328 /* radeon synchronizes all rings by default and will not implement
333 static void r600_flush_from_st(struct pipe_context
*ctx
,
334 struct pipe_fence_handle
**fence
,
337 struct pipe_screen
*screen
= ctx
->screen
;
338 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
339 struct radeon_winsys
*ws
= rctx
->ws
;
340 struct pipe_fence_handle
*gfx_fence
= NULL
;
341 struct pipe_fence_handle
*sdma_fence
= NULL
;
342 bool deferred_fence
= false;
343 unsigned rflags
= PIPE_FLUSH_ASYNC
;
345 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
346 rflags
|= PIPE_FLUSH_END_OF_FRAME
;
348 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
350 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
352 if (!radeon_emitted(rctx
->gfx
.cs
, rctx
->initial_gfx_cs_size
)) {
354 ws
->fence_reference(&gfx_fence
, rctx
->last_gfx_fence
);
355 if (!(flags
& PIPE_FLUSH_DEFERRED
))
356 ws
->cs_sync_flush(rctx
->gfx
.cs
);
358 /* Instead of flushing, create a deferred fence. Constraints:
359 * - the gallium frontend must allow a deferred flush.
360 * - the gallium frontend must request a fence.
361 * Thread safety in fence_finish must be ensured by the gallium frontend.
363 if (flags
& PIPE_FLUSH_DEFERRED
&& fence
) {
364 gfx_fence
= rctx
->ws
->cs_get_next_fence(rctx
->gfx
.cs
);
365 deferred_fence
= true;
367 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
371 /* Both engines can signal out of order, so we need to keep both fences. */
373 struct r600_multi_fence
*multi_fence
=
374 CALLOC_STRUCT(r600_multi_fence
);
376 ws
->fence_reference(&sdma_fence
, NULL
);
377 ws
->fence_reference(&gfx_fence
, NULL
);
381 multi_fence
->reference
.count
= 1;
382 /* If both fences are NULL, fence_finish will always return true. */
383 multi_fence
->gfx
= gfx_fence
;
384 multi_fence
->sdma
= sdma_fence
;
386 if (deferred_fence
) {
387 multi_fence
->gfx_unflushed
.ctx
= rctx
;
388 multi_fence
->gfx_unflushed
.ib_index
= rctx
->num_gfx_cs_flushes
;
391 screen
->fence_reference(screen
, fence
, NULL
);
392 *fence
= (struct pipe_fence_handle
*)multi_fence
;
395 if (!(flags
& PIPE_FLUSH_DEFERRED
)) {
397 ws
->cs_sync_flush(rctx
->dma
.cs
);
398 ws
->cs_sync_flush(rctx
->gfx
.cs
);
402 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
403 struct pipe_fence_handle
**fence
)
405 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
406 struct radeon_cmdbuf
*cs
= rctx
->dma
.cs
;
407 struct radeon_saved_cs saved
;
409 (rctx
->screen
->debug_flags
& DBG_CHECK_VM
) &&
410 rctx
->check_vm_faults
;
412 if (!radeon_emitted(cs
, 0)) {
414 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
419 radeon_save_cs(rctx
->ws
, cs
, &saved
, true);
421 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
423 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
426 /* Use conservative timeout 800ms, after which we won't wait any
427 * longer and assume the GPU is hung.
429 rctx
->ws
->fence_wait(rctx
->ws
, rctx
->last_sdma_fence
, 800*1000*1000);
431 rctx
->check_vm_faults(rctx
, &saved
, RING_DMA
);
432 radeon_clear_saved_cs(&saved
);
437 * Store a linearized copy of all chunks of \p cs together with the buffer
440 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
441 struct radeon_saved_cs
*saved
, bool get_buffer_list
)
446 /* Save the IB chunks. */
447 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
448 saved
->ib
= MALLOC(4 * saved
->num_dw
);
453 for (i
= 0; i
< cs
->num_prev
; ++i
) {
454 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
455 buf
+= cs
->prev
[i
].cdw
;
457 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
459 if (!get_buffer_list
)
462 /* Save the buffer list. */
463 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
464 saved
->bo_list
= CALLOC(saved
->bo_count
,
465 sizeof(saved
->bo_list
[0]));
466 if (!saved
->bo_list
) {
470 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
475 fprintf(stderr
, "%s: out of memory\n", __func__
);
476 memset(saved
, 0, sizeof(*saved
));
479 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
)
482 FREE(saved
->bo_list
);
484 memset(saved
, 0, sizeof(*saved
));
487 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
489 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
491 return rctx
->ws
->ctx_query_reset_status(rctx
->ctx
);
494 static void r600_set_debug_callback(struct pipe_context
*ctx
,
495 const struct pipe_debug_callback
*cb
)
497 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
502 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
505 static void r600_set_device_reset_callback(struct pipe_context
*ctx
,
506 const struct pipe_device_reset_callback
*cb
)
508 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
511 rctx
->device_reset_callback
= *cb
;
513 memset(&rctx
->device_reset_callback
, 0,
514 sizeof(rctx
->device_reset_callback
));
517 bool r600_check_device_reset(struct r600_common_context
*rctx
)
519 enum pipe_reset_status status
;
521 if (!rctx
->device_reset_callback
.reset
)
524 if (!rctx
->b
.get_device_reset_status
)
527 status
= rctx
->b
.get_device_reset_status(&rctx
->b
);
528 if (status
== PIPE_NO_RESET
)
531 rctx
->device_reset_callback
.reset(rctx
->device_reset_callback
.data
, status
);
535 static void r600_dma_clear_buffer_fallback(struct pipe_context
*ctx
,
536 struct pipe_resource
*dst
,
537 uint64_t offset
, uint64_t size
,
540 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
542 rctx
->clear_buffer(ctx
, dst
, offset
, size
, value
, R600_COHERENCY_NONE
);
545 static bool r600_resource_commit(struct pipe_context
*pctx
,
546 struct pipe_resource
*resource
,
547 unsigned level
, struct pipe_box
*box
,
550 struct r600_common_context
*ctx
= (struct r600_common_context
*)pctx
;
551 struct r600_resource
*res
= r600_resource(resource
);
554 * Since buffer commitment changes cannot be pipelined, we need to
555 * (a) flush any pending commands that refer to the buffer we're about
557 * (b) wait for threaded submit to finish, including those that were
558 * triggered by some other, earlier operation.
560 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
561 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
,
562 res
->buf
, RADEON_USAGE_READWRITE
)) {
563 ctx
->gfx
.flush(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
565 if (radeon_emitted(ctx
->dma
.cs
, 0) &&
566 ctx
->ws
->cs_is_buffer_referenced(ctx
->dma
.cs
,
567 res
->buf
, RADEON_USAGE_READWRITE
)) {
568 ctx
->dma
.flush(ctx
, PIPE_FLUSH_ASYNC
, NULL
);
571 ctx
->ws
->cs_sync_flush(ctx
->dma
.cs
);
572 ctx
->ws
->cs_sync_flush(ctx
->gfx
.cs
);
574 assert(resource
->target
== PIPE_BUFFER
);
576 return ctx
->ws
->buffer_commit(res
->buf
, box
->x
, box
->width
, commit
);
579 bool r600_common_context_init(struct r600_common_context
*rctx
,
580 struct r600_common_screen
*rscreen
,
581 unsigned context_flags
)
583 slab_create_child(&rctx
->pool_transfers
, &rscreen
->pool_transfers
);
584 slab_create_child(&rctx
->pool_transfers_unsync
, &rscreen
->pool_transfers
);
586 rctx
->screen
= rscreen
;
587 rctx
->ws
= rscreen
->ws
;
588 rctx
->family
= rscreen
->family
;
589 rctx
->chip_class
= rscreen
->chip_class
;
591 rctx
->b
.invalidate_resource
= r600_invalidate_resource
;
592 rctx
->b
.resource_commit
= r600_resource_commit
;
593 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
594 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
595 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
596 rctx
->b
.texture_subdata
= u_default_texture_subdata
;
597 rctx
->b
.flush
= r600_flush_from_st
;
598 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
599 rctx
->b
.fence_server_sync
= r600_fence_server_sync
;
600 rctx
->dma_clear_buffer
= r600_dma_clear_buffer_fallback
;
602 /* evergreen_compute.c has a special codepath for global buffers.
603 * Everything else can use the direct path.
605 if ((rscreen
->chip_class
== EVERGREEN
|| rscreen
->chip_class
== CAYMAN
) &&
606 (context_flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
607 rctx
->b
.buffer_subdata
= u_default_buffer_subdata
;
609 rctx
->b
.buffer_subdata
= r600_buffer_subdata
;
611 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
612 rctx
->b
.set_device_reset_callback
= r600_set_device_reset_callback
;
614 r600_init_context_texture_functions(rctx
);
615 r600_init_viewport_functions(rctx
);
616 r600_streamout_init(rctx
);
617 r600_query_init(rctx
);
618 cayman_init_msaa(&rctx
->b
);
620 rctx
->allocator_zeroed_memory
=
621 u_suballocator_create(&rctx
->b
, rscreen
->info
.gart_page_size
,
622 0, PIPE_USAGE_DEFAULT
, 0, true);
623 if (!rctx
->allocator_zeroed_memory
)
626 rctx
->b
.stream_uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
627 0, PIPE_USAGE_STREAM
, 0);
628 if (!rctx
->b
.stream_uploader
)
631 rctx
->b
.const_uploader
= u_upload_create(&rctx
->b
, 128 * 1024,
632 0, PIPE_USAGE_DEFAULT
, 0);
633 if (!rctx
->b
.const_uploader
)
636 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
640 if (rscreen
->info
.num_rings
[RING_DMA
] && !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
641 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
644 rctx
->dma
.flush
= r600_flush_dma_ring
;
650 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
652 if (rctx
->query_result_shader
)
653 rctx
->b
.delete_compute_state(&rctx
->b
, rctx
->query_result_shader
);
656 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
658 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
660 rctx
->ws
->ctx_destroy(rctx
->ctx
);
662 if (rctx
->b
.stream_uploader
)
663 u_upload_destroy(rctx
->b
.stream_uploader
);
664 if (rctx
->b
.const_uploader
)
665 u_upload_destroy(rctx
->b
.const_uploader
);
667 slab_destroy_child(&rctx
->pool_transfers
);
668 slab_destroy_child(&rctx
->pool_transfers_unsync
);
670 if (rctx
->allocator_zeroed_memory
) {
671 u_suballocator_destroy(rctx
->allocator_zeroed_memory
);
673 rctx
->ws
->fence_reference(&rctx
->last_gfx_fence
, NULL
);
674 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
675 r600_resource_reference(&rctx
->eop_bug_scratch
, NULL
);
682 static const struct debug_named_value common_debug_options
[] = {
684 { "tex", DBG_TEX
, "Print texture info" },
685 { "nir", DBG_NIR
, "Enable experimental NIR shaders" },
686 { "compute", DBG_COMPUTE
, "Print compute info" },
687 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
688 { "info", DBG_INFO
, "Print driver information" },
691 { "fs", DBG_FS
, "Print fetch shaders" },
692 { "vs", DBG_VS
, "Print vertex shaders" },
693 { "gs", DBG_GS
, "Print geometry shaders" },
694 { "ps", DBG_PS
, "Print pixel shaders" },
695 { "cs", DBG_CS
, "Print compute shaders" },
696 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
697 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
698 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
699 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
700 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
701 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
702 { "checkir", DBG_CHECK_IR
, "Enable additional sanity checks on shader IR" },
703 { "nooptvariant", DBG_NO_OPT_VARIANT
, "Disable compiling optimized shader variants." },
705 { "testdma", DBG_TEST_DMA
, "Invoke SDMA tests and exit." },
706 { "testvmfaultcp", DBG_TEST_VMFAULT_CP
, "Invoke a CP VM fault test and exit." },
707 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA
, "Invoke a SDMA VM fault test and exit." },
708 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER
, "Invoke a shader VM fault test and exit." },
711 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
712 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
713 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
714 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
715 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
716 { "notiling", DBG_NO_TILING
, "Disable tiling" },
717 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
718 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
719 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
720 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
721 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
722 { "unsafemath", DBG_UNSAFE_MATH
, "Enable unsafe math shader optimizations" },
724 DEBUG_NAMED_VALUE_END
/* must be last */
727 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
732 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
737 static const char *r600_get_family_name(const struct r600_common_screen
*rscreen
)
739 switch (rscreen
->info
.family
) {
740 case CHIP_R600
: return "AMD R600";
741 case CHIP_RV610
: return "AMD RV610";
742 case CHIP_RV630
: return "AMD RV630";
743 case CHIP_RV670
: return "AMD RV670";
744 case CHIP_RV620
: return "AMD RV620";
745 case CHIP_RV635
: return "AMD RV635";
746 case CHIP_RS780
: return "AMD RS780";
747 case CHIP_RS880
: return "AMD RS880";
748 case CHIP_RV770
: return "AMD RV770";
749 case CHIP_RV730
: return "AMD RV730";
750 case CHIP_RV710
: return "AMD RV710";
751 case CHIP_RV740
: return "AMD RV740";
752 case CHIP_CEDAR
: return "AMD CEDAR";
753 case CHIP_REDWOOD
: return "AMD REDWOOD";
754 case CHIP_JUNIPER
: return "AMD JUNIPER";
755 case CHIP_CYPRESS
: return "AMD CYPRESS";
756 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
757 case CHIP_PALM
: return "AMD PALM";
758 case CHIP_SUMO
: return "AMD SUMO";
759 case CHIP_SUMO2
: return "AMD SUMO2";
760 case CHIP_BARTS
: return "AMD BARTS";
761 case CHIP_TURKS
: return "AMD TURKS";
762 case CHIP_CAICOS
: return "AMD CAICOS";
763 case CHIP_CAYMAN
: return "AMD CAYMAN";
764 case CHIP_ARUBA
: return "AMD ARUBA";
765 default: return "AMD unknown";
769 static void r600_disk_cache_create(struct r600_common_screen
*rscreen
)
771 /* Don't use the cache if shader dumping is enabled. */
772 if (rscreen
->debug_flags
& DBG_ALL_SHADERS
)
775 struct mesa_sha1 ctx
;
776 unsigned char sha1
[20];
777 char cache_id
[20 * 2 + 1];
779 _mesa_sha1_init(&ctx
);
780 if (!disk_cache_get_function_identifier(r600_disk_cache_create
,
784 _mesa_sha1_final(&ctx
, sha1
);
785 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
787 /* These flags affect shader compilation. */
788 uint64_t shader_debug_flags
=
789 rscreen
->debug_flags
&
790 (DBG_FS_CORRECT_DERIVS_AFTER_KILL
|
793 rscreen
->disk_shader_cache
=
794 disk_cache_create(r600_get_family_name(rscreen
),
799 static struct disk_cache
*r600_get_disk_shader_cache(struct pipe_screen
*pscreen
)
801 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
802 return rscreen
->disk_shader_cache
;
805 static const char* r600_get_name(struct pipe_screen
* pscreen
)
807 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
809 return rscreen
->renderer_string
;
812 static float r600_get_paramf(struct pipe_screen
* pscreen
,
813 enum pipe_capf param
)
816 case PIPE_CAPF_MAX_LINE_WIDTH
:
817 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
818 case PIPE_CAPF_MAX_POINT_WIDTH
:
819 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
821 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
823 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
825 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
826 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
827 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
833 static int r600_get_video_param(struct pipe_screen
*screen
,
834 enum pipe_video_profile profile
,
835 enum pipe_video_entrypoint entrypoint
,
836 enum pipe_video_cap param
)
839 case PIPE_VIDEO_CAP_SUPPORTED
:
840 return vl_profile_supported(screen
, profile
, entrypoint
);
841 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
843 case PIPE_VIDEO_CAP_MAX_WIDTH
:
844 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
845 return vl_video_buffer_max_size(screen
);
846 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
847 return PIPE_FORMAT_NV12
;
848 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
850 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
852 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
854 case PIPE_VIDEO_CAP_MAX_LEVEL
:
855 return vl_level_supported(screen
, profile
);
861 const char *r600_get_llvm_processor_name(enum radeon_family family
)
909 static unsigned get_max_threads_per_block(struct r600_common_screen
*screen
,
910 enum pipe_shader_ir ir_type
)
912 if (ir_type
!= PIPE_SHADER_IR_TGSI
&&
913 ir_type
!= PIPE_SHADER_IR_NIR
)
915 if (screen
->chip_class
>= EVERGREEN
)
920 static int r600_get_compute_param(struct pipe_screen
*screen
,
921 enum pipe_shader_ir ir_type
,
922 enum pipe_compute_cap param
,
925 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
927 //TODO: select these params by asic
929 case PIPE_COMPUTE_CAP_IR_TARGET
: {
931 const char *triple
= "r600--";
932 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
934 sprintf(ret
, "%s-%s", gpu
, triple
);
936 /* +2 for dash and terminating NIL byte */
937 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
939 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
941 uint64_t *grid_dimension
= ret
;
942 grid_dimension
[0] = 3;
944 return 1 * sizeof(uint64_t);
946 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
948 uint64_t *grid_size
= ret
;
949 grid_size
[0] = 65535;
950 grid_size
[1] = 65535;
951 grid_size
[2] = 65535;
953 return 3 * sizeof(uint64_t) ;
955 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
957 uint64_t *block_size
= ret
;
958 unsigned threads_per_block
= get_max_threads_per_block(rscreen
, ir_type
);
959 block_size
[0] = threads_per_block
;
960 block_size
[1] = threads_per_block
;
961 block_size
[2] = threads_per_block
;
963 return 3 * sizeof(uint64_t);
965 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
967 uint64_t *max_threads_per_block
= ret
;
968 *max_threads_per_block
= get_max_threads_per_block(rscreen
, ir_type
);
970 return sizeof(uint64_t);
971 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
973 uint32_t *address_bits
= ret
;
974 address_bits
[0] = 32;
976 return 1 * sizeof(uint32_t);
978 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
980 uint64_t *max_global_size
= ret
;
981 uint64_t max_mem_alloc_size
;
983 r600_get_compute_param(screen
, ir_type
,
984 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
985 &max_mem_alloc_size
);
987 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
988 * 1/4 of the MAX_GLOBAL_SIZE. Since the
989 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
990 * make sure we never report more than
991 * 4 * MAX_MEM_ALLOC_SIZE.
993 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
994 MAX2(rscreen
->info
.gart_size
,
995 rscreen
->info
.vram_size
));
997 return sizeof(uint64_t);
999 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
1001 uint64_t *max_local_size
= ret
;
1002 /* Value reported by the closed source driver. */
1003 *max_local_size
= 32768;
1005 return sizeof(uint64_t);
1007 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
1009 uint64_t *max_input_size
= ret
;
1010 /* Value reported by the closed source driver. */
1011 *max_input_size
= 1024;
1013 return sizeof(uint64_t);
1015 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
1017 uint64_t *max_mem_alloc_size
= ret
;
1019 *max_mem_alloc_size
= rscreen
->info
.max_alloc_size
;
1021 return sizeof(uint64_t);
1023 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
1025 uint32_t *max_clock_frequency
= ret
;
1026 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
1028 return sizeof(uint32_t);
1030 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
1032 uint32_t *max_compute_units
= ret
;
1033 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
1035 return sizeof(uint32_t);
1037 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
1039 uint32_t *images_supported
= ret
;
1040 *images_supported
= 0;
1042 return sizeof(uint32_t);
1043 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
1045 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
1047 uint32_t *subgroup_size
= ret
;
1048 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
1050 return sizeof(uint32_t);
1051 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
1053 uint64_t *max_variable_threads_per_block
= ret
;
1054 *max_variable_threads_per_block
= 0;
1056 return sizeof(uint64_t);
1059 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
1063 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
1065 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1067 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
1068 rscreen
->info
.clock_crystal_freq
;
1071 static void r600_fence_reference(struct pipe_screen
*screen
,
1072 struct pipe_fence_handle
**dst
,
1073 struct pipe_fence_handle
*src
)
1075 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
1076 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
1077 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
1079 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
1080 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
1081 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
1087 static bool r600_fence_finish(struct pipe_screen
*screen
,
1088 struct pipe_context
*ctx
,
1089 struct pipe_fence_handle
*fence
,
1092 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
1093 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
1094 struct r600_common_context
*rctx
;
1095 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
1097 ctx
= threaded_context_unwrap_sync(ctx
);
1098 rctx
= ctx
? (struct r600_common_context
*)ctx
: NULL
;
1101 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
1104 /* Recompute the timeout after waiting. */
1105 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1106 int64_t time
= os_time_get_nano();
1107 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1114 /* Flush the gfx IB if it hasn't been flushed yet. */
1116 rfence
->gfx_unflushed
.ctx
== rctx
&&
1117 rfence
->gfx_unflushed
.ib_index
== rctx
->num_gfx_cs_flushes
) {
1118 rctx
->gfx
.flush(rctx
, timeout
? 0 : PIPE_FLUSH_ASYNC
, NULL
);
1119 rfence
->gfx_unflushed
.ctx
= NULL
;
1124 /* Recompute the timeout after all that. */
1125 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1126 int64_t time
= os_time_get_nano();
1127 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1131 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
1134 static void r600_query_memory_info(struct pipe_screen
*screen
,
1135 struct pipe_memory_info
*info
)
1137 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1138 struct radeon_winsys
*ws
= rscreen
->ws
;
1139 unsigned vram_usage
, gtt_usage
;
1141 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
1142 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
1144 /* The real TTM memory usage is somewhat random, because:
1146 * 1) TTM delays freeing memory, because it can only free it after
1149 * 2) The memory usage can be really low if big VRAM evictions are
1150 * taking place, but the real usage is well above the size of VRAM.
1152 * Instead, return statistics of this process.
1154 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
1155 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
1157 info
->avail_device_memory
=
1158 vram_usage
<= info
->total_device_memory
?
1159 info
->total_device_memory
- vram_usage
: 0;
1160 info
->avail_staging_memory
=
1161 gtt_usage
<= info
->total_staging_memory
?
1162 info
->total_staging_memory
- gtt_usage
: 0;
1164 info
->device_memory_evicted
=
1165 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
1167 /* Just return the number of evicted 64KB pages. */
1168 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
1171 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
1172 const struct pipe_resource
*templ
)
1174 if (templ
->target
== PIPE_BUFFER
) {
1175 return r600_buffer_create(screen
, templ
, 256);
1177 return r600_texture_create(screen
, templ
);
1181 const struct nir_shader_compiler_options r600_nir_fs_options
= {
1184 .lower_flrp32
= true,
1185 .lower_flrp64
= true,
1190 .lower_doubles_options
= nir_lower_fp64_full_software
,
1191 .lower_int64_options
= 0,
1192 .lower_extract_byte
= true,
1193 .lower_extract_word
= true,
1194 .max_unroll_iterations
= 32,
1195 .lower_all_io_to_temps
= true,
1196 .vectorize_io
= true,
1201 const struct nir_shader_compiler_options r600_nir_options
= {
1204 .lower_flrp32
= true,
1205 .lower_flrp64
= true,
1210 .lower_doubles_options
= nir_lower_fp64_full_software
,
1211 .lower_int64_options
= 0,
1212 .lower_extract_byte
= true,
1213 .lower_extract_word
= true,
1214 .max_unroll_iterations
= 32,
1215 .vectorize_io
= true,
1222 r600_get_compiler_options(struct pipe_screen
*screen
,
1223 enum pipe_shader_ir ir
,
1224 enum pipe_shader_type shader
)
1226 assert(ir
== PIPE_SHADER_IR_NIR
);
1227 if (shader
== PIPE_SHADER_FRAGMENT
)
1228 return &r600_nir_fs_options
;
1230 return &r600_nir_options
;
1233 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
1234 struct radeon_winsys
*ws
)
1236 char family_name
[32] = {}, kernel_version
[128] = {};
1237 struct utsname uname_data
;
1238 const char *chip_name
;
1240 ws
->query_info(ws
, &rscreen
->info
);
1243 chip_name
= r600_get_family_name(rscreen
);
1245 if (uname(&uname_data
) == 0)
1246 snprintf(kernel_version
, sizeof(kernel_version
),
1247 " / %s", uname_data
.release
);
1249 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
1250 "%s (%sDRM %i.%i.%i%s"
1251 #ifdef LLVM_AVAILABLE
1252 ", LLVM " MESA_LLVM_VERSION_STRING
1255 chip_name
, family_name
, rscreen
->info
.drm_major
,
1256 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
1259 rscreen
->b
.get_name
= r600_get_name
;
1260 rscreen
->b
.get_vendor
= r600_get_vendor
;
1261 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
1262 rscreen
->b
.get_disk_shader_cache
= r600_get_disk_shader_cache
;
1263 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
1264 rscreen
->b
.get_paramf
= r600_get_paramf
;
1265 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
1266 rscreen
->b
.get_compiler_options
= r600_get_compiler_options
;
1267 rscreen
->b
.fence_finish
= r600_fence_finish
;
1268 rscreen
->b
.fence_reference
= r600_fence_reference
;
1269 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
1270 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
1271 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
1273 if (rscreen
->info
.has_hw_decode
) {
1274 rscreen
->b
.get_video_param
= rvid_get_video_param
;
1275 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
1277 rscreen
->b
.get_video_param
= r600_get_video_param
;
1278 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1281 r600_init_screen_texture_functions(rscreen
);
1282 r600_init_screen_query_functions(rscreen
);
1284 rscreen
->family
= rscreen
->info
.family
;
1285 rscreen
->chip_class
= rscreen
->info
.chip_class
;
1286 rscreen
->debug_flags
|= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
1287 int has_draw_use_llvm
= debug_get_bool_option("DRAW_USE_LLVM", FALSE
);
1288 if (!has_draw_use_llvm
)
1289 setenv("DRAW_USE_LLVM", "no", 0);
1292 r600_disk_cache_create(rscreen
);
1294 slab_create_parent(&rscreen
->pool_transfers
, sizeof(struct r600_transfer
), 64);
1296 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1297 if (rscreen
->force_aniso
>= 0) {
1298 printf("radeon: Forcing anisotropy filter to %ix\n",
1299 /* round down to a power of two */
1300 1 << util_logbase2(rscreen
->force_aniso
));
1303 (void) mtx_init(&rscreen
->aux_context_lock
, mtx_plain
);
1304 (void) mtx_init(&rscreen
->gpu_load_mutex
, mtx_plain
);
1306 if (rscreen
->debug_flags
& DBG_INFO
) {
1307 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1308 rscreen
->info
.pci_domain
, rscreen
->info
.pci_bus
,
1309 rscreen
->info
.pci_dev
, rscreen
->info
.pci_func
);
1310 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
1311 printf("family = %i (%s)\n", rscreen
->info
.family
,
1312 r600_get_family_name(rscreen
));
1313 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
1314 printf("pte_fragment_size = %u\n", rscreen
->info
.pte_fragment_size
);
1315 printf("gart_page_size = %u\n", rscreen
->info
.gart_page_size
);
1316 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
1317 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
1318 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_vis_size
, 1024*1024));
1319 printf("max_alloc_size = %i MB\n",
1320 (int)DIV_ROUND_UP(rscreen
->info
.max_alloc_size
, 1024*1024));
1321 printf("min_alloc_size = %u\n", rscreen
->info
.min_alloc_size
);
1322 printf("has_dedicated_vram = %u\n", rscreen
->info
.has_dedicated_vram
);
1323 printf("r600_has_virtual_memory = %i\n", rscreen
->info
.r600_has_virtual_memory
);
1324 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
1325 printf("has_hw_decode = %u\n", rscreen
->info
.has_hw_decode
);
1326 printf("num_rings[RING_DMA] = %i\n", rscreen
->info
.num_rings
[RING_DMA
]);
1327 printf("num_rings[RING_COMPUTE] = %u\n", rscreen
->info
.num_rings
[RING_COMPUTE
]);
1328 printf("uvd_fw_version = %u\n", rscreen
->info
.uvd_fw_version
);
1329 printf("vce_fw_version = %u\n", rscreen
->info
.vce_fw_version
);
1330 printf("me_fw_version = %i\n", rscreen
->info
.me_fw_version
);
1331 printf("pfp_fw_version = %i\n", rscreen
->info
.pfp_fw_version
);
1332 printf("ce_fw_version = %i\n", rscreen
->info
.ce_fw_version
);
1333 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
1334 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
1335 printf("tcc_cache_line_size = %u\n", rscreen
->info
.tcc_cache_line_size
);
1336 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
1337 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
1338 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
1339 printf("has_syncobj = %u\n", rscreen
->info
.has_syncobj
);
1341 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
1342 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
1343 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
1344 printf("max_se = %i\n", rscreen
->info
.max_se
);
1345 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
1347 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
1348 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
1349 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
1350 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
1351 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
1352 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
1353 printf("enabled_rb_mask = 0x%x\n", rscreen
->info
.enabled_rb_mask
);
1354 printf("max_alignment = %u\n", (unsigned)rscreen
->info
.max_alignment
);
1359 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
1361 r600_perfcounters_destroy(rscreen
);
1362 r600_gpu_load_kill_thread(rscreen
);
1364 mtx_destroy(&rscreen
->gpu_load_mutex
);
1365 mtx_destroy(&rscreen
->aux_context_lock
);
1366 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
1368 slab_destroy_parent(&rscreen
->pool_transfers
);
1370 disk_cache_destroy(rscreen
->disk_shader_cache
);
1371 rscreen
->ws
->destroy(rscreen
->ws
);
1375 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
1378 return rscreen
->debug_flags
& (1 << processor
);
1381 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
, unsigned processor
)
1383 return (rscreen
->debug_flags
& DBG_CHECK_IR
) ||
1384 r600_can_dump_shader(rscreen
, processor
);
1387 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1388 uint64_t offset
, uint64_t size
, unsigned value
)
1390 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1392 mtx_lock(&rscreen
->aux_context_lock
);
1393 rctx
->dma_clear_buffer(&rctx
->b
, dst
, offset
, size
, value
);
1394 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1395 mtx_unlock(&rscreen
->aux_context_lock
);