2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "radeon/radeon_winsys.h"
39 #include "util/disk_cache.h"
40 #include "util/u_blitter.h"
41 #include "util/list.h"
42 #include "util/u_range.h"
43 #include "util/slab.h"
44 #include "util/u_suballoc.h"
45 #include "util/u_transfer.h"
46 #include "util/u_threaded_context.h"
49 #define ATI_VENDOR_ID 0x1002
51 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
52 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
53 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
54 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
56 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
57 /* Pipeline & streamout query controls. */
58 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
59 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
60 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
61 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
63 /* special primitive types */
64 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
66 #define R600_NOT_QUERY 0xffffffff
69 #define DBG_VS (1 << PIPE_SHADER_VERTEX)
70 #define DBG_PS (1 << PIPE_SHADER_FRAGMENT)
71 #define DBG_GS (1 << PIPE_SHADER_GEOMETRY)
72 #define DBG_TCS (1 << PIPE_SHADER_TESS_CTRL)
73 #define DBG_TES (1 << PIPE_SHADER_TESS_EVAL)
74 #define DBG_CS (1 << PIPE_SHADER_COMPUTE)
75 #define DBG_ALL_SHADERS (DBG_FS - 1)
76 #define DBG_FS (1 << 6) /* fetch shader */
77 #define DBG_TEX (1 << 7)
78 #define DBG_NIR (1 << 8)
79 #define DBG_COMPUTE (1 << 9)
81 #define DBG_VM (1 << 11)
82 #define DBG_NO_IR (1 << 12)
83 #define DBG_NO_TGSI (1 << 13)
84 #define DBG_NO_ASM (1 << 14)
85 #define DBG_PREOPT_IR (1 << 15)
86 #define DBG_CHECK_IR (1 << 16)
87 #define DBG_NO_OPT_VARIANT (1 << 17)
88 #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
90 #define DBG_TEST_DMA (1 << 20)
91 /* Bits 21-31 are reserved for the r600g driver. */
93 #define DBG_NO_ASYNC_DMA (1ull << 32)
94 #define DBG_NO_HYPERZ (1ull << 33)
95 #define DBG_NO_DISCARD_RANGE (1ull << 34)
96 #define DBG_NO_2D_TILING (1ull << 35)
97 #define DBG_NO_TILING (1ull << 36)
98 #define DBG_SWITCH_ON_EOP (1ull << 37)
99 #define DBG_FORCE_DMA (1ull << 38)
100 #define DBG_PRECOMPILE (1ull << 39)
101 #define DBG_INFO (1ull << 40)
102 #define DBG_NO_WC (1ull << 41)
103 #define DBG_CHECK_VM (1ull << 42)
105 #define DBG_UNSAFE_MATH (1ull << 49)
106 #define DBG_TEST_VMFAULT_CP (1ull << 51)
107 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
108 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
110 #define R600_MAP_BUFFER_ALIGNMENT 64
111 #define R600_MAX_VIEWPORTS 16
113 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
115 enum r600_coherency
{
116 R600_COHERENCY_NONE
, /* no cache flushes needed */
117 R600_COHERENCY_SHADER
,
118 R600_COHERENCY_CB_META
,
121 #ifdef PIPE_ARCH_BIG_ENDIAN
122 #define R600_BIG_ENDIAN 1
124 #define R600_BIG_ENDIAN 0
127 struct r600_common_context
;
128 struct r600_perfcounters
;
129 struct tgsi_shader_info
;
130 struct r600_qbo_state
;
132 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
135 struct r600_resource
{
136 struct threaded_resource b
;
138 /* Winsys objects. */
139 struct pb_buffer
*buf
;
140 uint64_t gpu_address
;
141 /* Memory usage if the buffer placement is optimal. */
145 /* Resource properties. */
147 unsigned bo_alignment
;
148 enum radeon_bo_domain domains
;
149 enum radeon_bo_flag flags
;
150 unsigned bind_history
;
152 /* The buffer range which is initialized (with a write transfer,
153 * streamout, DMA, or as a random access target). The rest of
154 * the buffer is considered invalid and can be mapped unsynchronized.
156 * This allows unsychronized mapping of a buffer range which hasn't
157 * been used yet. It's for applications which forget to use
158 * the unsynchronized map flag and expect the driver to figure it out.
160 struct util_range valid_buffer_range
;
162 /* Whether the resource has been exported via resource_get_handle. */
163 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
165 /* Whether this resource is referenced by bindless handles. */
166 bool texture_handle_allocated
;
167 bool image_handle_allocated
;
170 * EG/Cayman only - for RAT operations hw need an immediate buffer
171 * to store results in.
173 struct r600_resource
*immed_buffer
;
176 struct r600_transfer
{
177 struct threaded_transfer b
;
178 struct r600_resource
*staging
;
182 struct r600_fmask_info
{
186 unsigned pitch_in_pixels
;
187 unsigned bank_height
;
188 unsigned slice_tile_max
;
189 unsigned tile_mode_index
;
190 unsigned tile_swizzle
;
193 struct r600_cmask_info
{
197 unsigned slice_tile_max
;
198 uint64_t base_address_reg
;
201 struct r600_texture
{
202 struct r600_resource resource
;
205 unsigned num_level0_transfers
;
206 enum pipe_format db_render_format
;
211 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
212 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
213 struct r600_texture
*flushed_depth_texture
;
214 struct radeon_surf surface
;
216 /* Colorbuffer compression and fast clear. */
217 struct r600_fmask_info fmask
;
218 struct r600_cmask_info cmask
;
219 struct r600_resource
*cmask_buffer
;
220 unsigned cb_color_info
; /* fast clear enable bit */
221 unsigned color_clear_value
[2];
222 unsigned last_msaa_resolve_target_micro_mode
;
224 /* Depth buffer compression and fast clear. */
225 uint64_t htile_offset
;
226 bool depth_cleared
; /* if it was cleared at least once */
227 float depth_clear_value
;
228 bool stencil_cleared
; /* if it was cleared at least once */
229 uint8_t stencil_clear_value
;
231 bool non_disp_tiling
; /* R600-Cayman only */
233 /* Counter that should be non-zero if the texture is bound to a
234 * framebuffer. Implemented in radeonsi only.
236 uint32_t framebuffers_bound
;
239 struct r600_surface
{
240 struct pipe_surface base
;
242 /* These can vary with block-compressed textures. */
246 bool color_initialized
;
247 bool depth_initialized
;
249 /* Misc. color flags. */
250 bool alphatest_bypass
;
255 /* Color registers. */
256 unsigned cb_color_info
;
257 unsigned cb_color_base
;
258 unsigned cb_color_view
;
259 unsigned cb_color_size
; /* R600 only */
260 unsigned cb_color_dim
; /* EG only */
261 unsigned cb_color_pitch
; /* EG and later */
262 unsigned cb_color_slice
; /* EG and later */
263 unsigned cb_color_attrib
; /* EG and later */
264 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
265 unsigned cb_color_fmask_slice
; /* EG and later */
266 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
267 unsigned cb_color_mask
; /* R600 only */
268 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
269 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
272 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
273 uint64_t db_stencil_base
; /* EG and later */
274 uint64_t db_htile_data_base
;
275 unsigned db_depth_info
; /* R600 only, then SI and later */
276 unsigned db_z_info
; /* EG and later */
277 unsigned db_depth_view
;
278 unsigned db_depth_size
;
279 unsigned db_depth_slice
; /* EG and later */
280 unsigned db_stencil_info
; /* EG and later */
281 unsigned db_prefetch_limit
; /* R600 only */
282 unsigned db_htile_surface
;
283 unsigned db_preload_control
; /* EG and later */
286 struct r600_mmio_counter
{
291 union r600_mmio_counters
{
293 /* For global GPU load including SDMA. */
294 struct r600_mmio_counter gpu
;
297 struct r600_mmio_counter spi
;
298 struct r600_mmio_counter gui
;
299 struct r600_mmio_counter ta
;
300 struct r600_mmio_counter gds
;
301 struct r600_mmio_counter vgt
;
302 struct r600_mmio_counter ia
;
303 struct r600_mmio_counter sx
;
304 struct r600_mmio_counter wd
;
305 struct r600_mmio_counter bci
;
306 struct r600_mmio_counter sc
;
307 struct r600_mmio_counter pa
;
308 struct r600_mmio_counter db
;
309 struct r600_mmio_counter cp
;
310 struct r600_mmio_counter cb
;
313 struct r600_mmio_counter sdma
;
316 struct r600_mmio_counter pfp
;
317 struct r600_mmio_counter meq
;
318 struct r600_mmio_counter me
;
319 struct r600_mmio_counter surf_sync
;
320 struct r600_mmio_counter cp_dma
;
321 struct r600_mmio_counter scratch_ram
;
326 struct r600_memory_object
{
327 struct pipe_memory_object b
;
328 struct pb_buffer
*buf
;
333 struct r600_common_screen
{
334 struct pipe_screen b
;
335 struct radeon_winsys
*ws
;
336 enum radeon_family family
;
337 enum chip_class chip_class
;
338 struct radeon_info info
;
339 uint64_t debug_flags
;
343 struct disk_cache
*disk_shader_cache
;
345 struct slab_parent_pool pool_transfers
;
347 /* Texture filter settings. */
348 int force_aniso
; /* -1 = disabled */
350 /* Auxiliary context. Mainly used to initialize resources.
351 * It must be locked prior to using and flushed before unlocking. */
352 struct pipe_context
*aux_context
;
353 mtx_t aux_context_lock
;
355 /* This must be in the screen, because UE4 uses one context for
356 * compilation and another one for rendering.
358 unsigned num_compilations
;
359 /* Along with ST_DEBUG=precompile, this should show if applications
360 * are loading shaders on demand. This is a monotonic counter.
362 unsigned num_shaders_created
;
363 unsigned num_shader_cache_hits
;
365 /* GPU load thread. */
366 mtx_t gpu_load_mutex
;
367 thrd_t gpu_load_thread
;
368 union r600_mmio_counters mmio_counters
;
369 volatile unsigned gpu_load_stop_thread
; /* bool */
371 char renderer_string
[100];
373 /* Performance counters. */
374 struct r600_perfcounters
*perfcounters
;
376 /* If pipe_screen wants to recompute and re-emit the framebuffer,
377 * sampler, and image states of all contexts, it should atomically
380 * Each context will compare this with its own last known value of
381 * the counter before drawing and re-emit the states accordingly.
383 unsigned dirty_tex_counter
;
385 /* Atomically increment this counter when an existing texture's
386 * metadata is enabled or disabled in a way that requires changing
387 * contexts' compressed texture binding masks.
389 unsigned compressed_colortex_counter
;
392 /* Context flags to set so that all writes from earlier jobs
393 * in the CP are seen by L2 clients.
397 /* Context flags to set so that all writes from earlier jobs
398 * that end in L2 are seen by CP.
402 /* Context flags to set so that all writes from earlier
403 * compute jobs are seen by L2 clients.
405 unsigned compute_to_L2
;
408 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
409 struct r600_texture
*rtex
,
410 struct radeon_bo_metadata
*md
);
412 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
413 struct r600_texture
*rtex
,
414 struct radeon_bo_metadata
*md
);
417 /* This encapsulates a state or an operation which can emitted into the GPU
420 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
425 struct r600_so_target
{
426 struct pipe_stream_output_target b
;
428 /* The buffer where BUFFER_FILLED_SIZE is stored. */
429 struct r600_resource
*buf_filled_size
;
430 unsigned buf_filled_size_offset
;
431 bool buf_filled_size_valid
;
433 unsigned stride_in_dw
;
436 struct r600_streamout
{
437 struct r600_atom begin_atom
;
439 unsigned num_dw_for_end
;
441 unsigned enabled_mask
;
442 unsigned num_targets
;
443 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
445 unsigned append_bitmask
;
448 /* External state which comes from the vertex shader,
449 * it must be set explicitly when binding a shader. */
450 uint16_t *stride_in_dw
;
451 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
453 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
454 unsigned hw_enabled_mask
;
456 /* The state of VGT_STRMOUT_(CONFIG|EN). */
457 struct r600_atom enable_atom
;
458 bool streamout_enabled
;
459 bool prims_gen_query_enabled
;
460 int num_prims_gen_queries
;
463 struct r600_signed_scissor
{
470 struct r600_scissors
{
471 struct r600_atom atom
;
473 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
476 struct r600_viewports
{
477 struct r600_atom atom
;
479 unsigned depth_range_dirty_mask
;
480 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
481 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
485 struct radeon_cmdbuf
*cs
;
486 void (*flush
)(void *ctx
, unsigned flags
,
487 struct pipe_fence_handle
**fence
);
490 /* Saved CS data for debugging features. */
491 struct radeon_saved_cs
{
495 struct radeon_bo_list_item
*bo_list
;
499 struct r600_common_context
{
500 struct pipe_context b
; /* base class */
502 struct r600_common_screen
*screen
;
503 struct radeon_winsys
*ws
;
504 struct radeon_winsys_ctx
*ctx
;
505 enum radeon_family family
;
506 enum chip_class chip_class
;
507 struct r600_ring gfx
;
508 struct r600_ring dma
;
509 struct pipe_fence_handle
*last_gfx_fence
;
510 struct pipe_fence_handle
*last_sdma_fence
;
511 struct r600_resource
*eop_bug_scratch
;
512 unsigned num_gfx_cs_flushes
;
513 unsigned initial_gfx_cs_size
;
514 unsigned last_dirty_tex_counter
;
515 unsigned last_compressed_colortex_counter
;
516 unsigned last_num_draw_calls
;
518 struct threaded_context
*tc
;
519 struct u_suballocator
*allocator_zeroed_memory
;
520 struct slab_child_pool pool_transfers
;
521 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
523 /* Current unaccounted memory usage. */
528 struct r600_streamout streamout
;
529 struct r600_scissors scissors
;
530 struct r600_viewports viewports
;
531 bool scissor_enabled
;
533 bool vs_writes_viewport_index
;
534 bool vs_disables_clipping_viewport
;
536 /* Additional context states. */
537 unsigned flags
; /* flush flags */
540 /* Maintain the list of active queries for pausing between IBs. */
541 int num_occlusion_queries
;
542 int num_perfect_occlusion_queries
;
543 struct list_head active_queries
;
544 unsigned num_cs_dw_queries_suspend
;
546 unsigned num_draw_calls
;
547 unsigned num_decompress_calls
;
548 unsigned num_mrt_draw_calls
;
549 unsigned num_prim_restart_calls
;
550 unsigned num_spill_draw_calls
;
551 unsigned num_compute_calls
;
552 unsigned num_spill_compute_calls
;
553 unsigned num_dma_calls
;
554 unsigned num_cp_dma_calls
;
555 unsigned num_vs_flushes
;
556 unsigned num_ps_flushes
;
557 unsigned num_cs_flushes
;
558 unsigned num_cb_cache_flushes
;
559 unsigned num_db_cache_flushes
;
560 unsigned num_resident_handles
;
561 uint64_t num_alloc_tex_transfer_bytes
;
563 /* Render condition. */
564 struct r600_atom render_cond_atom
;
565 struct pipe_query
*render_cond
;
566 unsigned render_cond_mode
;
567 bool render_cond_invert
;
568 bool render_cond_force_off
; /* for u_blitter */
570 /* MSAA sample locations.
571 * The first index is the sample index.
572 * The second index is the coordinate: X, Y. */
573 float sample_locations_1x
[1][2];
574 float sample_locations_2x
[2][2];
575 float sample_locations_4x
[4][2];
576 float sample_locations_8x
[8][2];
577 float sample_locations_16x
[16][2];
579 struct pipe_debug_callback debug
;
580 struct pipe_device_reset_callback device_reset_callback
;
581 struct u_log_context
*log
;
583 void *query_result_shader
;
585 /* Copy one resource to another using async DMA. */
586 void (*dma_copy
)(struct pipe_context
*ctx
,
587 struct pipe_resource
*dst
,
589 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
590 struct pipe_resource
*src
,
592 const struct pipe_box
*src_box
);
594 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
595 uint64_t offset
, uint64_t size
, unsigned value
);
597 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
598 uint64_t offset
, uint64_t size
, unsigned value
,
599 enum r600_coherency coher
);
601 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
602 struct r600_texture
*texture
,
603 struct r600_texture
*staging
,
604 unsigned first_level
, unsigned last_level
,
605 unsigned first_layer
, unsigned last_layer
,
606 unsigned first_sample
, unsigned last_sample
);
608 /* Reallocate the buffer and update all resource bindings where
609 * the buffer is bound, including all resource descriptors. */
610 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
612 /* Update all resource bindings where the buffer is bound, including
613 * all resource descriptors. This is invalidate_buffer without
614 * the invalidation. */
615 void (*rebind_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
616 uint64_t old_gpu_address
);
618 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
620 /* This ensures there is enough space in the command stream. */
621 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
622 bool include_draw_vbo
);
624 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
625 struct r600_atom
*atom
, bool dirty
);
627 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
628 struct radeon_saved_cs
*saved
,
629 enum ring_type ring
);
632 /* r600_buffer_common.c */
633 bool r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
634 struct pb_buffer
*buf
,
635 enum radeon_bo_usage usage
);
636 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
637 struct r600_resource
*resource
,
639 void r600_buffer_subdata(struct pipe_context
*ctx
,
640 struct pipe_resource
*buffer
,
641 unsigned usage
, unsigned offset
,
642 unsigned size
, const void *data
);
643 void r600_init_resource_fields(struct r600_common_screen
*rscreen
,
644 struct r600_resource
*res
,
645 uint64_t size
, unsigned alignment
);
646 bool r600_alloc_resource(struct r600_common_screen
*rscreen
,
647 struct r600_resource
*res
);
648 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
649 const struct pipe_resource
*templ
,
651 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
656 struct pipe_resource
*
657 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
658 const struct pipe_resource
*templ
,
661 r600_invalidate_resource(struct pipe_context
*ctx
,
662 struct pipe_resource
*resource
);
663 void r600_replace_buffer_storage(struct pipe_context
*ctx
,
664 struct pipe_resource
*dst
,
665 struct pipe_resource
*src
);
667 /* r600_common_pipe.c */
668 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
669 unsigned event
, unsigned event_flags
,
671 struct r600_resource
*buf
, uint64_t va
,
672 uint32_t new_fence
, unsigned query_type
);
673 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
674 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
675 struct r600_resource
*buf
,
676 uint64_t va
, uint32_t ref
, uint32_t mask
);
677 void r600_draw_rectangle(struct blitter_context
*blitter
,
678 void *vertex_elements_cso
,
679 blitter_get_vs_func get_vs
,
680 int x1
, int y1
, int x2
, int y2
,
681 float depth
, unsigned num_instances
,
682 enum blitter_attrib_type type
,
683 const union blitter_attrib
*attrib
);
684 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
685 struct radeon_winsys
*ws
);
686 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
687 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
688 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
689 bool r600_common_context_init(struct r600_common_context
*rctx
,
690 struct r600_common_screen
*rscreen
,
691 unsigned context_flags
);
692 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
693 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
695 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
,
697 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
698 uint64_t offset
, uint64_t size
, unsigned value
);
699 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
700 const struct pipe_resource
*templ
);
701 const char *r600_get_llvm_processor_name(enum radeon_family family
);
702 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
703 struct r600_resource
*dst
, struct r600_resource
*src
);
704 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_cmdbuf
*cs
,
705 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
706 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
);
707 bool r600_check_device_reset(struct r600_common_context
*rctx
);
709 /* r600_gpu_load.c */
710 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
711 uint64_t r600_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
712 unsigned r600_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
715 /* r600_perfcounters.c */
716 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
719 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
720 void r600_query_init(struct r600_common_context
*rctx
);
721 void r600_suspend_queries(struct r600_common_context
*ctx
);
722 void r600_resume_queries(struct r600_common_context
*ctx
);
723 void r600_query_fix_enabled_rb_mask(struct r600_common_screen
*rscreen
);
725 /* r600_streamout.c */
726 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
727 void r600_set_streamout_targets(struct pipe_context
*ctx
,
728 unsigned num_targets
,
729 struct pipe_stream_output_target
**targets
,
730 const unsigned *offset
);
731 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
732 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
733 unsigned type
, int diff
);
734 void r600_streamout_init(struct r600_common_context
*rctx
);
736 /* r600_test_dma.c */
737 void r600_test_dma(struct r600_common_screen
*rscreen
);
740 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
741 struct r600_texture
*rdst
,
742 unsigned dst_level
, unsigned dstx
,
743 unsigned dsty
, unsigned dstz
,
744 struct r600_texture
*rsrc
,
746 const struct pipe_box
*src_box
);
747 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
748 struct r600_texture
*rtex
,
750 struct r600_fmask_info
*out
);
751 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
752 struct r600_texture
*rtex
,
753 struct r600_cmask_info
*out
);
754 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
755 struct pipe_resource
*texture
,
756 struct r600_texture
**staging
);
757 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
758 struct r600_texture
*rtex
, struct u_log_context
*log
);
759 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
760 const struct pipe_resource
*templ
);
761 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
762 struct pipe_resource
*texture
,
763 const struct pipe_surface
*templ
,
764 unsigned width0
, unsigned height0
,
765 unsigned width
, unsigned height
);
766 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
767 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
768 struct pipe_framebuffer_state
*fb
,
769 struct r600_atom
*fb_state
,
770 unsigned *buffers
, ubyte
*dirty_cbufs
,
771 const union pipe_color_union
*color
);
772 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
773 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
774 void eg_resource_alloc_immed(struct r600_common_screen
*rscreen
,
775 struct r600_resource
*res
,
776 unsigned immed_size
);
778 /* r600_viewport.c */
779 void evergreen_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
780 struct pipe_scissor_state
*scissor
);
781 void r600_viewport_set_rast_deps(struct r600_common_context
*rctx
,
782 bool scissor_enable
, bool clip_halfz
);
783 void r600_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
784 struct tgsi_shader_info
*info
);
785 void r600_init_viewport_functions(struct r600_common_context
*rctx
);
788 extern const uint32_t eg_sample_locs_2x
[4];
789 extern const unsigned eg_max_dist_2x
;
790 extern const uint32_t eg_sample_locs_4x
[4];
791 extern const unsigned eg_max_dist_4x
;
792 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
793 unsigned sample_index
, float *out_value
);
794 void cayman_init_msaa(struct pipe_context
*ctx
);
795 void cayman_emit_msaa_state(struct radeon_cmdbuf
*cs
, int nr_samples
,
796 int ps_iter_samples
, int overrast_samples
);
799 /* Inline helpers. */
801 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
803 return (struct r600_resource
*)r
;
807 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
809 pipe_resource_reference((struct pipe_resource
**)ptr
,
810 (struct pipe_resource
*)res
);
814 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
816 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
820 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
822 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
823 struct r600_resource
*res
= (struct r600_resource
*)r
;
826 /* Add memory usage for need_gfx_cs_space */
827 rctx
->vram
+= res
->vram_usage
;
828 rctx
->gtt
+= res
->gart_usage
;
832 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
834 return rctx
->streamout
.streamout_enabled
||
835 rctx
->streamout
.prims_gen_query_enabled
;
838 #define SQ_TEX_XY_FILTER_POINT 0x00
839 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
840 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
841 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
843 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
845 if (filter
== PIPE_TEX_FILTER_LINEAR
)
846 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
847 : SQ_TEX_XY_FILTER_BILINEAR
;
849 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
850 : SQ_TEX_XY_FILTER_POINT
;
853 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
866 static inline unsigned r600_wavefront_size(enum radeon_family family
)
886 static inline enum radeon_bo_priority
887 r600_get_sampler_view_priority(struct r600_resource
*res
)
889 if (res
->b
.b
.target
== PIPE_BUFFER
)
890 return RADEON_PRIO_SAMPLER_BUFFER
;
892 if (res
->b
.b
.nr_samples
> 1)
893 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
895 return RADEON_PRIO_SAMPLER_TEXTURE
;
899 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
901 return (stencil_sampler
&& tex
->can_sample_s
) ||
902 (!stencil_sampler
&& tex
->can_sample_z
);
906 r600_htile_enabled(struct r600_texture
*tex
, unsigned level
)
908 return tex
->htile_offset
&& level
== 0;
911 #define COMPUTE_DBG(rscreen, fmt, args...) \
913 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
916 #define R600_ERR(fmt, args...) \
917 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
919 /* For MSAA sample positions. */
920 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
921 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
922 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
923 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
924 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
926 static inline int S_FIXED(float value
, unsigned frac_bits
)
928 return value
* (1 << frac_bits
);