2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
37 #include "amd/common/ac_binary.h"
39 #include "radeon/radeon_winsys.h"
41 #include "util/disk_cache.h"
42 #include "util/u_blitter.h"
43 #include "util/list.h"
44 #include "util/u_range.h"
45 #include "util/slab.h"
46 #include "util/u_suballoc.h"
47 #include "util/u_transfer.h"
48 #include "util/u_threaded_context.h"
52 #define ATI_VENDOR_ID 0x1002
54 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
55 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
56 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
57 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
59 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
60 /* Pipeline & streamout query controls. */
61 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
62 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
63 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
64 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
66 /* special primitive types */
67 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
69 #define R600_NOT_QUERY 0xffffffff
72 #define DBG_VS (1 << PIPE_SHADER_VERTEX)
73 #define DBG_PS (1 << PIPE_SHADER_FRAGMENT)
74 #define DBG_GS (1 << PIPE_SHADER_GEOMETRY)
75 #define DBG_TCS (1 << PIPE_SHADER_TESS_CTRL)
76 #define DBG_TES (1 << PIPE_SHADER_TESS_EVAL)
77 #define DBG_CS (1 << PIPE_SHADER_COMPUTE)
78 #define DBG_ALL_SHADERS (DBG_FS - 1)
79 #define DBG_FS (1 << 6) /* fetch shader */
80 #define DBG_TEX (1 << 7)
81 #define DBG_NIR (1 << 8)
82 #define DBG_COMPUTE (1 << 9)
84 #define DBG_VM (1 << 11)
85 #define DBG_NO_IR (1 << 12)
86 #define DBG_NO_TGSI (1 << 13)
87 #define DBG_NO_ASM (1 << 14)
88 #define DBG_PREOPT_IR (1 << 15)
89 #define DBG_CHECK_IR (1 << 16)
90 #define DBG_NO_OPT_VARIANT (1 << 17)
91 #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
93 #define DBG_TEST_DMA (1 << 20)
94 /* Bits 21-31 are reserved for the r600g driver. */
96 #define DBG_NO_ASYNC_DMA (1ull << 32)
97 #define DBG_NO_HYPERZ (1ull << 33)
98 #define DBG_NO_DISCARD_RANGE (1ull << 34)
99 #define DBG_NO_2D_TILING (1ull << 35)
100 #define DBG_NO_TILING (1ull << 36)
101 #define DBG_SWITCH_ON_EOP (1ull << 37)
102 #define DBG_FORCE_DMA (1ull << 38)
103 #define DBG_PRECOMPILE (1ull << 39)
104 #define DBG_INFO (1ull << 40)
105 #define DBG_NO_WC (1ull << 41)
106 #define DBG_CHECK_VM (1ull << 42)
108 #define DBG_UNSAFE_MATH (1ull << 49)
109 #define DBG_TEST_VMFAULT_CP (1ull << 51)
110 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
111 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
113 #define R600_MAP_BUFFER_ALIGNMENT 64
114 #define R600_MAX_VIEWPORTS 16
116 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
118 enum r600_coherency
{
119 R600_COHERENCY_NONE
, /* no cache flushes needed */
120 R600_COHERENCY_SHADER
,
121 R600_COHERENCY_CB_META
,
124 #ifdef PIPE_ARCH_BIG_ENDIAN
125 #define R600_BIG_ENDIAN 1
127 #define R600_BIG_ENDIAN 0
130 struct r600_common_context
;
131 struct r600_perfcounters
;
132 struct tgsi_shader_info
;
133 struct r600_qbo_state
;
135 void radeon_shader_binary_init(struct ac_shader_binary
*b
);
136 void radeon_shader_binary_clean(struct ac_shader_binary
*b
);
138 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
141 struct r600_resource
{
142 struct threaded_resource b
;
144 /* Winsys objects. */
145 struct pb_buffer
*buf
;
146 uint64_t gpu_address
;
147 /* Memory usage if the buffer placement is optimal. */
151 /* Resource properties. */
153 unsigned bo_alignment
;
154 enum radeon_bo_domain domains
;
155 enum radeon_bo_flag flags
;
156 unsigned bind_history
;
158 /* The buffer range which is initialized (with a write transfer,
159 * streamout, DMA, or as a random access target). The rest of
160 * the buffer is considered invalid and can be mapped unsynchronized.
162 * This allows unsychronized mapping of a buffer range which hasn't
163 * been used yet. It's for applications which forget to use
164 * the unsynchronized map flag and expect the driver to figure it out.
166 struct util_range valid_buffer_range
;
168 /* For buffers only. This indicates that a write operation has been
169 * performed by TC L2, but the cache hasn't been flushed.
170 * Any hw block which doesn't use or bypasses TC L2 should check this
171 * flag and flush the cache before using the buffer.
173 * For example, TC L2 must be flushed if a buffer which has been
174 * modified by a shader store instruction is about to be used as
175 * an index buffer. The reason is that VGT DMA index fetching doesn't
180 /* Whether the resource has been exported via resource_get_handle. */
181 unsigned external_usage
; /* PIPE_HANDLE_USAGE_* */
183 /* Whether this resource is referenced by bindless handles. */
184 bool texture_handle_allocated
;
185 bool image_handle_allocated
;
188 struct r600_transfer
{
189 struct threaded_transfer b
;
190 struct r600_resource
*staging
;
194 struct r600_fmask_info
{
198 unsigned pitch_in_pixels
;
199 unsigned bank_height
;
200 unsigned slice_tile_max
;
201 unsigned tile_mode_index
;
202 unsigned tile_swizzle
;
205 struct r600_cmask_info
{
209 unsigned slice_tile_max
;
210 uint64_t base_address_reg
;
213 struct r600_texture
{
214 struct r600_resource resource
;
217 unsigned num_level0_transfers
;
218 enum pipe_format db_render_format
;
223 unsigned dirty_level_mask
; /* each bit says if that mipmap is compressed */
224 unsigned stencil_dirty_level_mask
; /* each bit says if that mipmap is compressed */
225 struct r600_texture
*flushed_depth_texture
;
226 struct radeon_surf surface
;
228 /* Colorbuffer compression and fast clear. */
229 struct r600_fmask_info fmask
;
230 struct r600_cmask_info cmask
;
231 struct r600_resource
*cmask_buffer
;
232 unsigned cb_color_info
; /* fast clear enable bit */
233 unsigned color_clear_value
[2];
234 unsigned last_msaa_resolve_target_micro_mode
;
236 /* Depth buffer compression and fast clear. */
237 uint64_t htile_offset
;
238 bool depth_cleared
; /* if it was cleared at least once */
239 float depth_clear_value
;
240 bool stencil_cleared
; /* if it was cleared at least once */
241 uint8_t stencil_clear_value
;
243 bool non_disp_tiling
; /* R600-Cayman only */
245 /* Counter that should be non-zero if the texture is bound to a
246 * framebuffer. Implemented in radeonsi only.
248 uint32_t framebuffers_bound
;
251 struct r600_surface
{
252 struct pipe_surface base
;
254 /* These can vary with block-compressed textures. */
258 bool color_initialized
;
259 bool depth_initialized
;
261 /* Misc. color flags. */
262 bool alphatest_bypass
;
267 /* Color registers. */
268 unsigned cb_color_info
;
269 unsigned cb_color_base
;
270 unsigned cb_color_view
;
271 unsigned cb_color_size
; /* R600 only */
272 unsigned cb_color_dim
; /* EG only */
273 unsigned cb_color_pitch
; /* EG and later */
274 unsigned cb_color_slice
; /* EG and later */
275 unsigned cb_color_attrib
; /* EG and later */
276 unsigned cb_color_fmask
; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
277 unsigned cb_color_fmask_slice
; /* EG and later */
278 unsigned cb_color_cmask
; /* CB_COLORn_TILE (r600 only) */
279 unsigned cb_color_mask
; /* R600 only */
280 struct r600_resource
*cb_buffer_fmask
; /* Used for FMASK relocations. R600 only */
281 struct r600_resource
*cb_buffer_cmask
; /* Used for CMASK relocations. R600 only */
284 uint64_t db_depth_base
; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
285 uint64_t db_stencil_base
; /* EG and later */
286 uint64_t db_htile_data_base
;
287 unsigned db_depth_info
; /* R600 only, then SI and later */
288 unsigned db_z_info
; /* EG and later */
289 unsigned db_depth_view
;
290 unsigned db_depth_size
;
291 unsigned db_depth_slice
; /* EG and later */
292 unsigned db_stencil_info
; /* EG and later */
293 unsigned db_prefetch_limit
; /* R600 only */
294 unsigned db_htile_surface
;
295 unsigned db_preload_control
; /* EG and later */
298 struct r600_mmio_counter
{
303 union r600_mmio_counters
{
305 /* For global GPU load including SDMA. */
306 struct r600_mmio_counter gpu
;
309 struct r600_mmio_counter spi
;
310 struct r600_mmio_counter gui
;
311 struct r600_mmio_counter ta
;
312 struct r600_mmio_counter gds
;
313 struct r600_mmio_counter vgt
;
314 struct r600_mmio_counter ia
;
315 struct r600_mmio_counter sx
;
316 struct r600_mmio_counter wd
;
317 struct r600_mmio_counter bci
;
318 struct r600_mmio_counter sc
;
319 struct r600_mmio_counter pa
;
320 struct r600_mmio_counter db
;
321 struct r600_mmio_counter cp
;
322 struct r600_mmio_counter cb
;
325 struct r600_mmio_counter sdma
;
328 struct r600_mmio_counter pfp
;
329 struct r600_mmio_counter meq
;
330 struct r600_mmio_counter me
;
331 struct r600_mmio_counter surf_sync
;
332 struct r600_mmio_counter cp_dma
;
333 struct r600_mmio_counter scratch_ram
;
338 struct r600_memory_object
{
339 struct pipe_memory_object b
;
340 struct pb_buffer
*buf
;
345 struct r600_common_screen
{
346 struct pipe_screen b
;
347 struct radeon_winsys
*ws
;
348 enum radeon_family family
;
349 enum chip_class chip_class
;
350 struct radeon_info info
;
351 uint64_t debug_flags
;
355 struct disk_cache
*disk_shader_cache
;
357 struct slab_parent_pool pool_transfers
;
359 /* Texture filter settings. */
360 int force_aniso
; /* -1 = disabled */
362 /* Auxiliary context. Mainly used to initialize resources.
363 * It must be locked prior to using and flushed before unlocking. */
364 struct pipe_context
*aux_context
;
365 mtx_t aux_context_lock
;
367 /* This must be in the screen, because UE4 uses one context for
368 * compilation and another one for rendering.
370 unsigned num_compilations
;
371 /* Along with ST_DEBUG=precompile, this should show if applications
372 * are loading shaders on demand. This is a monotonic counter.
374 unsigned num_shaders_created
;
375 unsigned num_shader_cache_hits
;
377 /* GPU load thread. */
378 mtx_t gpu_load_mutex
;
379 thrd_t gpu_load_thread
;
380 union r600_mmio_counters mmio_counters
;
381 volatile unsigned gpu_load_stop_thread
; /* bool */
383 char renderer_string
[100];
385 /* Performance counters. */
386 struct r600_perfcounters
*perfcounters
;
388 /* If pipe_screen wants to recompute and re-emit the framebuffer,
389 * sampler, and image states of all contexts, it should atomically
392 * Each context will compare this with its own last known value of
393 * the counter before drawing and re-emit the states accordingly.
395 unsigned dirty_tex_counter
;
397 /* Atomically increment this counter when an existing texture's
398 * metadata is enabled or disabled in a way that requires changing
399 * contexts' compressed texture binding masks.
401 unsigned compressed_colortex_counter
;
404 /* Context flags to set so that all writes from earlier jobs
405 * in the CP are seen by L2 clients.
409 /* Context flags to set so that all writes from earlier jobs
410 * that end in L2 are seen by CP.
414 /* Context flags to set so that all writes from earlier
415 * compute jobs are seen by L2 clients.
417 unsigned compute_to_L2
;
420 void (*query_opaque_metadata
)(struct r600_common_screen
*rscreen
,
421 struct r600_texture
*rtex
,
422 struct radeon_bo_metadata
*md
);
424 void (*apply_opaque_metadata
)(struct r600_common_screen
*rscreen
,
425 struct r600_texture
*rtex
,
426 struct radeon_bo_metadata
*md
);
429 /* This encapsulates a state or an operation which can emitted into the GPU
432 void (*emit
)(struct r600_common_context
*ctx
, struct r600_atom
*state
);
437 struct r600_so_target
{
438 struct pipe_stream_output_target b
;
440 /* The buffer where BUFFER_FILLED_SIZE is stored. */
441 struct r600_resource
*buf_filled_size
;
442 unsigned buf_filled_size_offset
;
443 bool buf_filled_size_valid
;
445 unsigned stride_in_dw
;
448 struct r600_streamout
{
449 struct r600_atom begin_atom
;
451 unsigned num_dw_for_end
;
453 unsigned enabled_mask
;
454 unsigned num_targets
;
455 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
457 unsigned append_bitmask
;
460 /* External state which comes from the vertex shader,
461 * it must be set explicitly when binding a shader. */
462 uint16_t *stride_in_dw
;
463 unsigned enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
465 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
466 unsigned hw_enabled_mask
;
468 /* The state of VGT_STRMOUT_(CONFIG|EN). */
469 struct r600_atom enable_atom
;
470 bool streamout_enabled
;
471 bool prims_gen_query_enabled
;
472 int num_prims_gen_queries
;
475 struct r600_signed_scissor
{
482 struct r600_scissors
{
483 struct r600_atom atom
;
485 struct pipe_scissor_state states
[R600_MAX_VIEWPORTS
];
488 struct r600_viewports
{
489 struct r600_atom atom
;
491 unsigned depth_range_dirty_mask
;
492 struct pipe_viewport_state states
[R600_MAX_VIEWPORTS
];
493 struct r600_signed_scissor as_scissor
[R600_MAX_VIEWPORTS
];
497 struct radeon_winsys_cs
*cs
;
498 void (*flush
)(void *ctx
, unsigned flags
,
499 struct pipe_fence_handle
**fence
);
502 /* Saved CS data for debugging features. */
503 struct radeon_saved_cs
{
507 struct radeon_bo_list_item
*bo_list
;
511 struct r600_common_context
{
512 struct pipe_context b
; /* base class */
514 struct r600_common_screen
*screen
;
515 struct radeon_winsys
*ws
;
516 struct radeon_winsys_ctx
*ctx
;
517 enum radeon_family family
;
518 enum chip_class chip_class
;
519 struct r600_ring gfx
;
520 struct r600_ring dma
;
521 struct pipe_fence_handle
*last_gfx_fence
;
522 struct pipe_fence_handle
*last_sdma_fence
;
523 struct r600_resource
*eop_bug_scratch
;
524 unsigned num_gfx_cs_flushes
;
525 unsigned initial_gfx_cs_size
;
526 unsigned gpu_reset_counter
;
527 unsigned last_dirty_tex_counter
;
528 unsigned last_compressed_colortex_counter
;
529 unsigned last_num_draw_calls
;
531 struct threaded_context
*tc
;
532 struct u_suballocator
*allocator_zeroed_memory
;
533 struct slab_child_pool pool_transfers
;
534 struct slab_child_pool pool_transfers_unsync
; /* for threaded_context */
536 /* Current unaccounted memory usage. */
541 struct r600_streamout streamout
;
542 struct r600_scissors scissors
;
543 struct r600_viewports viewports
;
544 bool scissor_enabled
;
546 bool vs_writes_viewport_index
;
547 bool vs_disables_clipping_viewport
;
549 /* Additional context states. */
550 unsigned flags
; /* flush flags */
553 /* Maintain the list of active queries for pausing between IBs. */
554 int num_occlusion_queries
;
555 int num_perfect_occlusion_queries
;
556 struct list_head active_queries
;
557 unsigned num_cs_dw_queries_suspend
;
559 unsigned num_draw_calls
;
560 unsigned num_decompress_calls
;
561 unsigned num_mrt_draw_calls
;
562 unsigned num_prim_restart_calls
;
563 unsigned num_spill_draw_calls
;
564 unsigned num_compute_calls
;
565 unsigned num_spill_compute_calls
;
566 unsigned num_dma_calls
;
567 unsigned num_cp_dma_calls
;
568 unsigned num_vs_flushes
;
569 unsigned num_ps_flushes
;
570 unsigned num_cs_flushes
;
571 unsigned num_cb_cache_flushes
;
572 unsigned num_db_cache_flushes
;
573 unsigned num_L2_invalidates
;
574 unsigned num_L2_writebacks
;
575 unsigned num_resident_handles
;
576 uint64_t num_alloc_tex_transfer_bytes
;
578 /* Render condition. */
579 struct r600_atom render_cond_atom
;
580 struct pipe_query
*render_cond
;
581 unsigned render_cond_mode
;
582 bool render_cond_invert
;
583 bool render_cond_force_off
; /* for u_blitter */
585 /* MSAA sample locations.
586 * The first index is the sample index.
587 * The second index is the coordinate: X, Y. */
588 float sample_locations_1x
[1][2];
589 float sample_locations_2x
[2][2];
590 float sample_locations_4x
[4][2];
591 float sample_locations_8x
[8][2];
592 float sample_locations_16x
[16][2];
594 struct pipe_debug_callback debug
;
595 struct pipe_device_reset_callback device_reset_callback
;
596 struct u_log_context
*log
;
598 void *query_result_shader
;
600 /* Copy one resource to another using async DMA. */
601 void (*dma_copy
)(struct pipe_context
*ctx
,
602 struct pipe_resource
*dst
,
604 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
605 struct pipe_resource
*src
,
607 const struct pipe_box
*src_box
);
609 void (*dma_clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
610 uint64_t offset
, uint64_t size
, unsigned value
);
612 void (*clear_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*dst
,
613 uint64_t offset
, uint64_t size
, unsigned value
,
614 enum r600_coherency coher
);
616 void (*blit_decompress_depth
)(struct pipe_context
*ctx
,
617 struct r600_texture
*texture
,
618 struct r600_texture
*staging
,
619 unsigned first_level
, unsigned last_level
,
620 unsigned first_layer
, unsigned last_layer
,
621 unsigned first_sample
, unsigned last_sample
);
623 /* Reallocate the buffer and update all resource bindings where
624 * the buffer is bound, including all resource descriptors. */
625 void (*invalidate_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
);
627 /* Update all resource bindings where the buffer is bound, including
628 * all resource descriptors. This is invalidate_buffer without
629 * the invalidation. */
630 void (*rebind_buffer
)(struct pipe_context
*ctx
, struct pipe_resource
*buf
,
631 uint64_t old_gpu_address
);
633 void (*save_qbo_state
)(struct pipe_context
*ctx
, struct r600_qbo_state
*st
);
635 /* This ensures there is enough space in the command stream. */
636 void (*need_gfx_cs_space
)(struct pipe_context
*ctx
, unsigned num_dw
,
637 bool include_draw_vbo
);
639 void (*set_atom_dirty
)(struct r600_common_context
*ctx
,
640 struct r600_atom
*atom
, bool dirty
);
642 void (*check_vm_faults
)(struct r600_common_context
*ctx
,
643 struct radeon_saved_cs
*saved
,
644 enum ring_type ring
);
647 /* r600_buffer_common.c */
648 bool r600_rings_is_buffer_referenced(struct r600_common_context
*ctx
,
649 struct pb_buffer
*buf
,
650 enum radeon_bo_usage usage
);
651 void *r600_buffer_map_sync_with_rings(struct r600_common_context
*ctx
,
652 struct r600_resource
*resource
,
654 void r600_buffer_subdata(struct pipe_context
*ctx
,
655 struct pipe_resource
*buffer
,
656 unsigned usage
, unsigned offset
,
657 unsigned size
, const void *data
);
658 void r600_init_resource_fields(struct r600_common_screen
*rscreen
,
659 struct r600_resource
*res
,
660 uint64_t size
, unsigned alignment
);
661 bool r600_alloc_resource(struct r600_common_screen
*rscreen
,
662 struct r600_resource
*res
);
663 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
664 const struct pipe_resource
*templ
,
666 struct pipe_resource
* r600_aligned_buffer_create(struct pipe_screen
*screen
,
671 struct pipe_resource
*
672 r600_buffer_from_user_memory(struct pipe_screen
*screen
,
673 const struct pipe_resource
*templ
,
676 r600_invalidate_resource(struct pipe_context
*ctx
,
677 struct pipe_resource
*resource
);
678 void r600_replace_buffer_storage(struct pipe_context
*ctx
,
679 struct pipe_resource
*dst
,
680 struct pipe_resource
*src
);
682 /* r600_common_pipe.c */
683 void r600_gfx_write_event_eop(struct r600_common_context
*ctx
,
684 unsigned event
, unsigned event_flags
,
686 struct r600_resource
*buf
, uint64_t va
,
687 uint32_t new_fence
, unsigned query_type
);
688 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen
*screen
);
689 void r600_gfx_wait_fence(struct r600_common_context
*ctx
,
690 uint64_t va
, uint32_t ref
, uint32_t mask
);
691 void r600_draw_rectangle(struct blitter_context
*blitter
,
692 void *vertex_elements_cso
,
693 blitter_get_vs_func get_vs
,
694 int x1
, int y1
, int x2
, int y2
,
695 float depth
, unsigned num_instances
,
696 enum blitter_attrib_type type
,
697 const union blitter_attrib
*attrib
);
698 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
699 struct radeon_winsys
*ws
);
700 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
);
701 void r600_preflush_suspend_features(struct r600_common_context
*ctx
);
702 void r600_postflush_resume_features(struct r600_common_context
*ctx
);
703 bool r600_common_context_init(struct r600_common_context
*rctx
,
704 struct r600_common_screen
*rscreen
,
705 unsigned context_flags
);
706 void r600_common_context_cleanup(struct r600_common_context
*rctx
);
707 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
709 bool r600_extra_shader_checks(struct r600_common_screen
*rscreen
,
711 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
712 uint64_t offset
, uint64_t size
, unsigned value
);
713 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
714 const struct pipe_resource
*templ
);
715 const char *r600_get_llvm_processor_name(enum radeon_family family
);
716 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
717 struct r600_resource
*dst
, struct r600_resource
*src
);
718 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
719 struct radeon_saved_cs
*saved
, bool get_buffer_list
);
720 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
);
721 bool r600_check_device_reset(struct r600_common_context
*rctx
);
723 /* r600_gpu_load.c */
724 void r600_gpu_load_kill_thread(struct r600_common_screen
*rscreen
);
725 uint64_t r600_begin_counter(struct r600_common_screen
*rscreen
, unsigned type
);
726 unsigned r600_end_counter(struct r600_common_screen
*rscreen
, unsigned type
,
729 /* r600_perfcounters.c */
730 void r600_perfcounters_destroy(struct r600_common_screen
*rscreen
);
733 void r600_init_screen_query_functions(struct r600_common_screen
*rscreen
);
734 void r600_query_init(struct r600_common_context
*rctx
);
735 void r600_suspend_queries(struct r600_common_context
*ctx
);
736 void r600_resume_queries(struct r600_common_context
*ctx
);
737 void r600_query_fix_enabled_rb_mask(struct r600_common_screen
*rscreen
);
739 /* r600_streamout.c */
740 void r600_streamout_buffers_dirty(struct r600_common_context
*rctx
);
741 void r600_set_streamout_targets(struct pipe_context
*ctx
,
742 unsigned num_targets
,
743 struct pipe_stream_output_target
**targets
,
744 const unsigned *offset
);
745 void r600_emit_streamout_end(struct r600_common_context
*rctx
);
746 void r600_update_prims_generated_query_state(struct r600_common_context
*rctx
,
747 unsigned type
, int diff
);
748 void r600_streamout_init(struct r600_common_context
*rctx
);
750 /* r600_test_dma.c */
751 void r600_test_dma(struct r600_common_screen
*rscreen
);
754 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
755 struct r600_texture
*rdst
,
756 unsigned dst_level
, unsigned dstx
,
757 unsigned dsty
, unsigned dstz
,
758 struct r600_texture
*rsrc
,
760 const struct pipe_box
*src_box
);
761 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
762 struct r600_texture
*rtex
,
764 struct r600_fmask_info
*out
);
765 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
766 struct r600_texture
*rtex
,
767 struct r600_cmask_info
*out
);
768 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
769 struct pipe_resource
*texture
,
770 struct r600_texture
**staging
);
771 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
772 struct r600_texture
*rtex
, struct u_log_context
*log
);
773 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
774 const struct pipe_resource
*templ
);
775 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
776 struct pipe_resource
*texture
,
777 const struct pipe_surface
*templ
,
778 unsigned width0
, unsigned height0
,
779 unsigned width
, unsigned height
);
780 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
);
781 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
782 struct pipe_framebuffer_state
*fb
,
783 struct r600_atom
*fb_state
,
784 unsigned *buffers
, ubyte
*dirty_cbufs
,
785 const union pipe_color_union
*color
);
786 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
);
787 void r600_init_context_texture_functions(struct r600_common_context
*rctx
);
789 /* r600_viewport.c */
790 void evergreen_apply_scissor_bug_workaround(struct r600_common_context
*rctx
,
791 struct pipe_scissor_state
*scissor
);
792 void r600_viewport_set_rast_deps(struct r600_common_context
*rctx
,
793 bool scissor_enable
, bool clip_halfz
);
794 void r600_update_vs_writes_viewport_index(struct r600_common_context
*rctx
,
795 struct tgsi_shader_info
*info
);
796 void r600_init_viewport_functions(struct r600_common_context
*rctx
);
799 extern const uint32_t eg_sample_locs_2x
[4];
800 extern const unsigned eg_max_dist_2x
;
801 extern const uint32_t eg_sample_locs_4x
[4];
802 extern const unsigned eg_max_dist_4x
;
803 void cayman_get_sample_position(struct pipe_context
*ctx
, unsigned sample_count
,
804 unsigned sample_index
, float *out_value
);
805 void cayman_init_msaa(struct pipe_context
*ctx
);
806 void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs
*cs
, int nr_samples
);
807 void cayman_emit_msaa_config(struct radeon_winsys_cs
*cs
, int nr_samples
,
808 int ps_iter_samples
, int overrast_samples
,
809 unsigned sc_mode_cntl_1
);
812 /* Inline helpers. */
814 static inline struct r600_resource
*r600_resource(struct pipe_resource
*r
)
816 return (struct r600_resource
*)r
;
820 r600_resource_reference(struct r600_resource
**ptr
, struct r600_resource
*res
)
822 pipe_resource_reference((struct pipe_resource
**)ptr
,
823 (struct pipe_resource
*)res
);
827 r600_texture_reference(struct r600_texture
**ptr
, struct r600_texture
*res
)
829 pipe_resource_reference((struct pipe_resource
**)ptr
, &res
->resource
.b
.b
);
833 r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
835 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
836 struct r600_resource
*res
= (struct r600_resource
*)r
;
839 /* Add memory usage for need_gfx_cs_space */
840 rctx
->vram
+= res
->vram_usage
;
841 rctx
->gtt
+= res
->gart_usage
;
845 static inline bool r600_get_strmout_en(struct r600_common_context
*rctx
)
847 return rctx
->streamout
.streamout_enabled
||
848 rctx
->streamout
.prims_gen_query_enabled
;
851 #define SQ_TEX_XY_FILTER_POINT 0x00
852 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
853 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
854 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
856 static inline unsigned eg_tex_filter(unsigned filter
, unsigned max_aniso
)
858 if (filter
== PIPE_TEX_FILTER_LINEAR
)
859 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
860 : SQ_TEX_XY_FILTER_BILINEAR
;
862 return max_aniso
> 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
863 : SQ_TEX_XY_FILTER_POINT
;
866 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
879 static inline unsigned r600_wavefront_size(enum radeon_family family
)
899 static inline enum radeon_bo_priority
900 r600_get_sampler_view_priority(struct r600_resource
*res
)
902 if (res
->b
.b
.target
== PIPE_BUFFER
)
903 return RADEON_PRIO_SAMPLER_BUFFER
;
905 if (res
->b
.b
.nr_samples
> 1)
906 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA
;
908 return RADEON_PRIO_SAMPLER_TEXTURE
;
912 r600_can_sample_zs(struct r600_texture
*tex
, bool stencil_sampler
)
914 return (stencil_sampler
&& tex
->can_sample_s
) ||
915 (!stencil_sampler
&& tex
->can_sample_z
);
919 r600_htile_enabled(struct r600_texture
*tex
, unsigned level
)
921 return tex
->htile_offset
&& level
== 0;
924 #define COMPUTE_DBG(rscreen, fmt, args...) \
926 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
929 #define R600_ERR(fmt, args...) \
930 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
932 /* For MSAA sample positions. */
933 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
934 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
935 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
936 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
937 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
939 static inline int S_FIXED(float value
, unsigned frac_bits
)
941 return value
* (1 << frac_bits
);