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r600: cleanup set_occlusion_query_state
[mesa.git] / src / gallium / drivers / r600 / r600_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "r600_query.h"
26 #include "r600_pipe.h"
27 #include "r600_cs.h"
28 #include "util/u_memory.h"
29 #include "util/u_upload_mgr.h"
30 #include "os/os_time.h"
31 #include "tgsi/tgsi_text.h"
32
33 #define R600_MAX_STREAMS 4
34
35 struct r600_hw_query_params {
36 unsigned start_offset;
37 unsigned end_offset;
38 unsigned fence_offset;
39 unsigned pair_stride;
40 unsigned pair_count;
41 };
42
43 /* Queries without buffer handling or suspend/resume. */
44 struct r600_query_sw {
45 struct r600_query b;
46
47 uint64_t begin_result;
48 uint64_t end_result;
49
50 uint64_t begin_time;
51 uint64_t end_time;
52
53 /* Fence for GPU_FINISHED. */
54 struct pipe_fence_handle *fence;
55 };
56
57 static void r600_query_sw_destroy(struct r600_common_screen *rscreen,
58 struct r600_query *rquery)
59 {
60 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
61
62 rscreen->b.fence_reference(&rscreen->b, &query->fence, NULL);
63 FREE(query);
64 }
65
66 static enum radeon_value_id winsys_id_from_type(unsigned type)
67 {
68 switch (type) {
69 case R600_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
70 case R600_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
71 case R600_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
72 case R600_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
73 case R600_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
74 case R600_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
75 case R600_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
76 case R600_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
77 case R600_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
78 case R600_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
79 case R600_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
80 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
81 case R600_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
82 case R600_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
83 case R600_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
84 case R600_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
85 case R600_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
86 case R600_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
87 case R600_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
88 default: unreachable("query type does not correspond to winsys id");
89 }
90 }
91
92 static bool r600_query_sw_begin(struct r600_common_context *rctx,
93 struct r600_query *rquery)
94 {
95 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
96 enum radeon_value_id ws_id;
97
98 switch(query->b.type) {
99 case PIPE_QUERY_TIMESTAMP_DISJOINT:
100 case PIPE_QUERY_GPU_FINISHED:
101 break;
102 case R600_QUERY_DRAW_CALLS:
103 query->begin_result = rctx->num_draw_calls;
104 break;
105 case R600_QUERY_DECOMPRESS_CALLS:
106 query->begin_result = rctx->num_decompress_calls;
107 break;
108 case R600_QUERY_MRT_DRAW_CALLS:
109 query->begin_result = rctx->num_mrt_draw_calls;
110 break;
111 case R600_QUERY_PRIM_RESTART_CALLS:
112 query->begin_result = rctx->num_prim_restart_calls;
113 break;
114 case R600_QUERY_SPILL_DRAW_CALLS:
115 query->begin_result = rctx->num_spill_draw_calls;
116 break;
117 case R600_QUERY_COMPUTE_CALLS:
118 query->begin_result = rctx->num_compute_calls;
119 break;
120 case R600_QUERY_SPILL_COMPUTE_CALLS:
121 query->begin_result = rctx->num_spill_compute_calls;
122 break;
123 case R600_QUERY_DMA_CALLS:
124 query->begin_result = rctx->num_dma_calls;
125 break;
126 case R600_QUERY_CP_DMA_CALLS:
127 query->begin_result = rctx->num_cp_dma_calls;
128 break;
129 case R600_QUERY_NUM_VS_FLUSHES:
130 query->begin_result = rctx->num_vs_flushes;
131 break;
132 case R600_QUERY_NUM_PS_FLUSHES:
133 query->begin_result = rctx->num_ps_flushes;
134 break;
135 case R600_QUERY_NUM_CS_FLUSHES:
136 query->begin_result = rctx->num_cs_flushes;
137 break;
138 case R600_QUERY_NUM_CB_CACHE_FLUSHES:
139 query->begin_result = rctx->num_cb_cache_flushes;
140 break;
141 case R600_QUERY_NUM_DB_CACHE_FLUSHES:
142 query->begin_result = rctx->num_db_cache_flushes;
143 break;
144 case R600_QUERY_NUM_L2_INVALIDATES:
145 query->begin_result = rctx->num_L2_invalidates;
146 break;
147 case R600_QUERY_NUM_L2_WRITEBACKS:
148 query->begin_result = rctx->num_L2_writebacks;
149 break;
150 case R600_QUERY_NUM_RESIDENT_HANDLES:
151 query->begin_result = rctx->num_resident_handles;
152 break;
153 case R600_QUERY_TC_OFFLOADED_SLOTS:
154 query->begin_result = rctx->tc ? rctx->tc->num_offloaded_slots : 0;
155 break;
156 case R600_QUERY_TC_DIRECT_SLOTS:
157 query->begin_result = rctx->tc ? rctx->tc->num_direct_slots : 0;
158 break;
159 case R600_QUERY_TC_NUM_SYNCS:
160 query->begin_result = rctx->tc ? rctx->tc->num_syncs : 0;
161 break;
162 case R600_QUERY_REQUESTED_VRAM:
163 case R600_QUERY_REQUESTED_GTT:
164 case R600_QUERY_MAPPED_VRAM:
165 case R600_QUERY_MAPPED_GTT:
166 case R600_QUERY_VRAM_USAGE:
167 case R600_QUERY_VRAM_VIS_USAGE:
168 case R600_QUERY_GTT_USAGE:
169 case R600_QUERY_GPU_TEMPERATURE:
170 case R600_QUERY_CURRENT_GPU_SCLK:
171 case R600_QUERY_CURRENT_GPU_MCLK:
172 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
173 case R600_QUERY_NUM_MAPPED_BUFFERS:
174 query->begin_result = 0;
175 break;
176 case R600_QUERY_BUFFER_WAIT_TIME:
177 case R600_QUERY_NUM_GFX_IBS:
178 case R600_QUERY_NUM_SDMA_IBS:
179 case R600_QUERY_NUM_BYTES_MOVED:
180 case R600_QUERY_NUM_EVICTIONS:
181 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
182 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
183 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
184 break;
185 }
186 case R600_QUERY_GFX_BO_LIST_SIZE:
187 ws_id = winsys_id_from_type(query->b.type);
188 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
189 query->begin_time = rctx->ws->query_value(rctx->ws,
190 RADEON_NUM_GFX_IBS);
191 break;
192 case R600_QUERY_CS_THREAD_BUSY:
193 ws_id = winsys_id_from_type(query->b.type);
194 query->begin_result = rctx->ws->query_value(rctx->ws, ws_id);
195 query->begin_time = os_time_get_nano();
196 break;
197 case R600_QUERY_GALLIUM_THREAD_BUSY:
198 query->begin_result =
199 rctx->tc ? util_queue_get_thread_time_nano(&rctx->tc->queue, 0) : 0;
200 query->begin_time = os_time_get_nano();
201 break;
202 case R600_QUERY_GPU_LOAD:
203 case R600_QUERY_GPU_SHADERS_BUSY:
204 case R600_QUERY_GPU_TA_BUSY:
205 case R600_QUERY_GPU_GDS_BUSY:
206 case R600_QUERY_GPU_VGT_BUSY:
207 case R600_QUERY_GPU_IA_BUSY:
208 case R600_QUERY_GPU_SX_BUSY:
209 case R600_QUERY_GPU_WD_BUSY:
210 case R600_QUERY_GPU_BCI_BUSY:
211 case R600_QUERY_GPU_SC_BUSY:
212 case R600_QUERY_GPU_PA_BUSY:
213 case R600_QUERY_GPU_DB_BUSY:
214 case R600_QUERY_GPU_CP_BUSY:
215 case R600_QUERY_GPU_CB_BUSY:
216 case R600_QUERY_GPU_SDMA_BUSY:
217 case R600_QUERY_GPU_PFP_BUSY:
218 case R600_QUERY_GPU_MEQ_BUSY:
219 case R600_QUERY_GPU_ME_BUSY:
220 case R600_QUERY_GPU_SURF_SYNC_BUSY:
221 case R600_QUERY_GPU_CP_DMA_BUSY:
222 case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
223 query->begin_result = r600_begin_counter(rctx->screen,
224 query->b.type);
225 break;
226 case R600_QUERY_NUM_COMPILATIONS:
227 query->begin_result = p_atomic_read(&rctx->screen->num_compilations);
228 break;
229 case R600_QUERY_NUM_SHADERS_CREATED:
230 query->begin_result = p_atomic_read(&rctx->screen->num_shaders_created);
231 break;
232 case R600_QUERY_NUM_SHADER_CACHE_HITS:
233 query->begin_result =
234 p_atomic_read(&rctx->screen->num_shader_cache_hits);
235 break;
236 case R600_QUERY_GPIN_ASIC_ID:
237 case R600_QUERY_GPIN_NUM_SIMD:
238 case R600_QUERY_GPIN_NUM_RB:
239 case R600_QUERY_GPIN_NUM_SPI:
240 case R600_QUERY_GPIN_NUM_SE:
241 break;
242 default:
243 unreachable("r600_query_sw_begin: bad query type");
244 }
245
246 return true;
247 }
248
249 static bool r600_query_sw_end(struct r600_common_context *rctx,
250 struct r600_query *rquery)
251 {
252 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
253 enum radeon_value_id ws_id;
254
255 switch(query->b.type) {
256 case PIPE_QUERY_TIMESTAMP_DISJOINT:
257 break;
258 case PIPE_QUERY_GPU_FINISHED:
259 rctx->b.flush(&rctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
260 break;
261 case R600_QUERY_DRAW_CALLS:
262 query->end_result = rctx->num_draw_calls;
263 break;
264 case R600_QUERY_DECOMPRESS_CALLS:
265 query->end_result = rctx->num_decompress_calls;
266 break;
267 case R600_QUERY_MRT_DRAW_CALLS:
268 query->end_result = rctx->num_mrt_draw_calls;
269 break;
270 case R600_QUERY_PRIM_RESTART_CALLS:
271 query->end_result = rctx->num_prim_restart_calls;
272 break;
273 case R600_QUERY_SPILL_DRAW_CALLS:
274 query->end_result = rctx->num_spill_draw_calls;
275 break;
276 case R600_QUERY_COMPUTE_CALLS:
277 query->end_result = rctx->num_compute_calls;
278 break;
279 case R600_QUERY_SPILL_COMPUTE_CALLS:
280 query->end_result = rctx->num_spill_compute_calls;
281 break;
282 case R600_QUERY_DMA_CALLS:
283 query->end_result = rctx->num_dma_calls;
284 break;
285 case R600_QUERY_CP_DMA_CALLS:
286 query->end_result = rctx->num_cp_dma_calls;
287 break;
288 case R600_QUERY_NUM_VS_FLUSHES:
289 query->end_result = rctx->num_vs_flushes;
290 break;
291 case R600_QUERY_NUM_PS_FLUSHES:
292 query->end_result = rctx->num_ps_flushes;
293 break;
294 case R600_QUERY_NUM_CS_FLUSHES:
295 query->end_result = rctx->num_cs_flushes;
296 break;
297 case R600_QUERY_NUM_CB_CACHE_FLUSHES:
298 query->end_result = rctx->num_cb_cache_flushes;
299 break;
300 case R600_QUERY_NUM_DB_CACHE_FLUSHES:
301 query->end_result = rctx->num_db_cache_flushes;
302 break;
303 case R600_QUERY_NUM_L2_INVALIDATES:
304 query->end_result = rctx->num_L2_invalidates;
305 break;
306 case R600_QUERY_NUM_L2_WRITEBACKS:
307 query->end_result = rctx->num_L2_writebacks;
308 break;
309 case R600_QUERY_NUM_RESIDENT_HANDLES:
310 query->end_result = rctx->num_resident_handles;
311 break;
312 case R600_QUERY_TC_OFFLOADED_SLOTS:
313 query->end_result = rctx->tc ? rctx->tc->num_offloaded_slots : 0;
314 break;
315 case R600_QUERY_TC_DIRECT_SLOTS:
316 query->end_result = rctx->tc ? rctx->tc->num_direct_slots : 0;
317 break;
318 case R600_QUERY_TC_NUM_SYNCS:
319 query->end_result = rctx->tc ? rctx->tc->num_syncs : 0;
320 break;
321 case R600_QUERY_REQUESTED_VRAM:
322 case R600_QUERY_REQUESTED_GTT:
323 case R600_QUERY_MAPPED_VRAM:
324 case R600_QUERY_MAPPED_GTT:
325 case R600_QUERY_VRAM_USAGE:
326 case R600_QUERY_VRAM_VIS_USAGE:
327 case R600_QUERY_GTT_USAGE:
328 case R600_QUERY_GPU_TEMPERATURE:
329 case R600_QUERY_CURRENT_GPU_SCLK:
330 case R600_QUERY_CURRENT_GPU_MCLK:
331 case R600_QUERY_BUFFER_WAIT_TIME:
332 case R600_QUERY_NUM_MAPPED_BUFFERS:
333 case R600_QUERY_NUM_GFX_IBS:
334 case R600_QUERY_NUM_SDMA_IBS:
335 case R600_QUERY_NUM_BYTES_MOVED:
336 case R600_QUERY_NUM_EVICTIONS:
337 case R600_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
338 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
339 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
340 break;
341 }
342 case R600_QUERY_GFX_BO_LIST_SIZE:
343 ws_id = winsys_id_from_type(query->b.type);
344 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
345 query->end_time = rctx->ws->query_value(rctx->ws,
346 RADEON_NUM_GFX_IBS);
347 break;
348 case R600_QUERY_CS_THREAD_BUSY:
349 ws_id = winsys_id_from_type(query->b.type);
350 query->end_result = rctx->ws->query_value(rctx->ws, ws_id);
351 query->end_time = os_time_get_nano();
352 break;
353 case R600_QUERY_GALLIUM_THREAD_BUSY:
354 query->end_result =
355 rctx->tc ? util_queue_get_thread_time_nano(&rctx->tc->queue, 0) : 0;
356 query->end_time = os_time_get_nano();
357 break;
358 case R600_QUERY_GPU_LOAD:
359 case R600_QUERY_GPU_SHADERS_BUSY:
360 case R600_QUERY_GPU_TA_BUSY:
361 case R600_QUERY_GPU_GDS_BUSY:
362 case R600_QUERY_GPU_VGT_BUSY:
363 case R600_QUERY_GPU_IA_BUSY:
364 case R600_QUERY_GPU_SX_BUSY:
365 case R600_QUERY_GPU_WD_BUSY:
366 case R600_QUERY_GPU_BCI_BUSY:
367 case R600_QUERY_GPU_SC_BUSY:
368 case R600_QUERY_GPU_PA_BUSY:
369 case R600_QUERY_GPU_DB_BUSY:
370 case R600_QUERY_GPU_CP_BUSY:
371 case R600_QUERY_GPU_CB_BUSY:
372 case R600_QUERY_GPU_SDMA_BUSY:
373 case R600_QUERY_GPU_PFP_BUSY:
374 case R600_QUERY_GPU_MEQ_BUSY:
375 case R600_QUERY_GPU_ME_BUSY:
376 case R600_QUERY_GPU_SURF_SYNC_BUSY:
377 case R600_QUERY_GPU_CP_DMA_BUSY:
378 case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
379 query->end_result = r600_end_counter(rctx->screen,
380 query->b.type,
381 query->begin_result);
382 query->begin_result = 0;
383 break;
384 case R600_QUERY_NUM_COMPILATIONS:
385 query->end_result = p_atomic_read(&rctx->screen->num_compilations);
386 break;
387 case R600_QUERY_NUM_SHADERS_CREATED:
388 query->end_result = p_atomic_read(&rctx->screen->num_shaders_created);
389 break;
390 case R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
391 query->end_result = rctx->last_tex_ps_draw_ratio;
392 break;
393 case R600_QUERY_NUM_SHADER_CACHE_HITS:
394 query->end_result =
395 p_atomic_read(&rctx->screen->num_shader_cache_hits);
396 break;
397 case R600_QUERY_GPIN_ASIC_ID:
398 case R600_QUERY_GPIN_NUM_SIMD:
399 case R600_QUERY_GPIN_NUM_RB:
400 case R600_QUERY_GPIN_NUM_SPI:
401 case R600_QUERY_GPIN_NUM_SE:
402 break;
403 default:
404 unreachable("r600_query_sw_end: bad query type");
405 }
406
407 return true;
408 }
409
410 static bool r600_query_sw_get_result(struct r600_common_context *rctx,
411 struct r600_query *rquery,
412 bool wait,
413 union pipe_query_result *result)
414 {
415 struct r600_query_sw *query = (struct r600_query_sw *)rquery;
416
417 switch (query->b.type) {
418 case PIPE_QUERY_TIMESTAMP_DISJOINT:
419 /* Convert from cycles per millisecond to cycles per second (Hz). */
420 result->timestamp_disjoint.frequency =
421 (uint64_t)rctx->screen->info.clock_crystal_freq * 1000;
422 result->timestamp_disjoint.disjoint = false;
423 return true;
424 case PIPE_QUERY_GPU_FINISHED: {
425 struct pipe_screen *screen = rctx->b.screen;
426 struct pipe_context *ctx = rquery->b.flushed ? NULL : &rctx->b;
427
428 result->b = screen->fence_finish(screen, ctx, query->fence,
429 wait ? PIPE_TIMEOUT_INFINITE : 0);
430 return result->b;
431 }
432
433 case R600_QUERY_GFX_BO_LIST_SIZE:
434 result->u64 = (query->end_result - query->begin_result) /
435 (query->end_time - query->begin_time);
436 return true;
437 case R600_QUERY_CS_THREAD_BUSY:
438 case R600_QUERY_GALLIUM_THREAD_BUSY:
439 result->u64 = (query->end_result - query->begin_result) * 100 /
440 (query->end_time - query->begin_time);
441 return true;
442 case R600_QUERY_GPIN_ASIC_ID:
443 result->u32 = 0;
444 return true;
445 case R600_QUERY_GPIN_NUM_SIMD:
446 result->u32 = rctx->screen->info.num_good_compute_units;
447 return true;
448 case R600_QUERY_GPIN_NUM_RB:
449 result->u32 = rctx->screen->info.num_render_backends;
450 return true;
451 case R600_QUERY_GPIN_NUM_SPI:
452 result->u32 = 1; /* all supported chips have one SPI per SE */
453 return true;
454 case R600_QUERY_GPIN_NUM_SE:
455 result->u32 = rctx->screen->info.max_se;
456 return true;
457 }
458
459 result->u64 = query->end_result - query->begin_result;
460
461 switch (query->b.type) {
462 case R600_QUERY_BUFFER_WAIT_TIME:
463 case R600_QUERY_GPU_TEMPERATURE:
464 result->u64 /= 1000;
465 break;
466 case R600_QUERY_CURRENT_GPU_SCLK:
467 case R600_QUERY_CURRENT_GPU_MCLK:
468 result->u64 *= 1000000;
469 break;
470 }
471
472 return true;
473 }
474
475
476 static struct r600_query_ops sw_query_ops = {
477 .destroy = r600_query_sw_destroy,
478 .begin = r600_query_sw_begin,
479 .end = r600_query_sw_end,
480 .get_result = r600_query_sw_get_result,
481 .get_result_resource = NULL
482 };
483
484 static struct pipe_query *r600_query_sw_create(unsigned query_type)
485 {
486 struct r600_query_sw *query;
487
488 query = CALLOC_STRUCT(r600_query_sw);
489 if (!query)
490 return NULL;
491
492 query->b.type = query_type;
493 query->b.ops = &sw_query_ops;
494
495 return (struct pipe_query *)query;
496 }
497
498 void r600_query_hw_destroy(struct r600_common_screen *rscreen,
499 struct r600_query *rquery)
500 {
501 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
502 struct r600_query_buffer *prev = query->buffer.previous;
503
504 /* Release all query buffers. */
505 while (prev) {
506 struct r600_query_buffer *qbuf = prev;
507 prev = prev->previous;
508 r600_resource_reference(&qbuf->buf, NULL);
509 FREE(qbuf);
510 }
511
512 r600_resource_reference(&query->buffer.buf, NULL);
513 r600_resource_reference(&query->workaround_buf, NULL);
514 FREE(rquery);
515 }
516
517 static struct r600_resource *r600_new_query_buffer(struct r600_common_screen *rscreen,
518 struct r600_query_hw *query)
519 {
520 unsigned buf_size = MAX2(query->result_size,
521 rscreen->info.min_alloc_size);
522
523 /* Queries are normally read by the CPU after
524 * being written by the gpu, hence staging is probably a good
525 * usage pattern.
526 */
527 struct r600_resource *buf = (struct r600_resource*)
528 pipe_buffer_create(&rscreen->b, 0,
529 PIPE_USAGE_STAGING, buf_size);
530 if (!buf)
531 return NULL;
532
533 if (!query->ops->prepare_buffer(rscreen, query, buf)) {
534 r600_resource_reference(&buf, NULL);
535 return NULL;
536 }
537
538 return buf;
539 }
540
541 static bool r600_query_hw_prepare_buffer(struct r600_common_screen *rscreen,
542 struct r600_query_hw *query,
543 struct r600_resource *buffer)
544 {
545 /* Callers ensure that the buffer is currently unused by the GPU. */
546 uint32_t *results = rscreen->ws->buffer_map(buffer->buf, NULL,
547 PIPE_TRANSFER_WRITE |
548 PIPE_TRANSFER_UNSYNCHRONIZED);
549 if (!results)
550 return false;
551
552 memset(results, 0, buffer->b.b.width0);
553
554 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
555 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE) {
556 unsigned max_rbs = rscreen->info.num_render_backends;
557 unsigned enabled_rb_mask = rscreen->info.enabled_rb_mask;
558 unsigned num_results;
559 unsigned i, j;
560
561 /* Set top bits for unused backends. */
562 num_results = buffer->b.b.width0 / query->result_size;
563 for (j = 0; j < num_results; j++) {
564 for (i = 0; i < max_rbs; i++) {
565 if (!(enabled_rb_mask & (1<<i))) {
566 results[(i * 4)+1] = 0x80000000;
567 results[(i * 4)+3] = 0x80000000;
568 }
569 }
570 results += 4 * max_rbs;
571 }
572 }
573
574 return true;
575 }
576
577 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
578 struct r600_query *rquery,
579 bool wait,
580 enum pipe_query_value_type result_type,
581 int index,
582 struct pipe_resource *resource,
583 unsigned offset);
584
585 static struct r600_query_ops query_hw_ops = {
586 .destroy = r600_query_hw_destroy,
587 .begin = r600_query_hw_begin,
588 .end = r600_query_hw_end,
589 .get_result = r600_query_hw_get_result,
590 .get_result_resource = r600_query_hw_get_result_resource,
591 };
592
593 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
594 struct r600_query_hw *query,
595 struct r600_resource *buffer,
596 uint64_t va);
597 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
598 struct r600_query_hw *query,
599 struct r600_resource *buffer,
600 uint64_t va);
601 static void r600_query_hw_add_result(struct r600_common_screen *rscreen,
602 struct r600_query_hw *, void *buffer,
603 union pipe_query_result *result);
604 static void r600_query_hw_clear_result(struct r600_query_hw *,
605 union pipe_query_result *);
606
607 static struct r600_query_hw_ops query_hw_default_hw_ops = {
608 .prepare_buffer = r600_query_hw_prepare_buffer,
609 .emit_start = r600_query_hw_do_emit_start,
610 .emit_stop = r600_query_hw_do_emit_stop,
611 .clear_result = r600_query_hw_clear_result,
612 .add_result = r600_query_hw_add_result,
613 };
614
615 bool r600_query_hw_init(struct r600_common_screen *rscreen,
616 struct r600_query_hw *query)
617 {
618 query->buffer.buf = r600_new_query_buffer(rscreen, query);
619 if (!query->buffer.buf)
620 return false;
621
622 return true;
623 }
624
625 static struct pipe_query *r600_query_hw_create(struct r600_common_screen *rscreen,
626 unsigned query_type,
627 unsigned index)
628 {
629 struct r600_query_hw *query = CALLOC_STRUCT(r600_query_hw);
630 if (!query)
631 return NULL;
632
633 query->b.type = query_type;
634 query->b.ops = &query_hw_ops;
635 query->ops = &query_hw_default_hw_ops;
636
637 switch (query_type) {
638 case PIPE_QUERY_OCCLUSION_COUNTER:
639 case PIPE_QUERY_OCCLUSION_PREDICATE:
640 query->result_size = 16 * rscreen->info.num_render_backends;
641 query->result_size += 16; /* for the fence + alignment */
642 query->num_cs_dw_begin = 6;
643 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rscreen);
644 break;
645 case PIPE_QUERY_TIME_ELAPSED:
646 query->result_size = 24;
647 query->num_cs_dw_begin = 8;
648 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rscreen);
649 break;
650 case PIPE_QUERY_TIMESTAMP:
651 query->result_size = 16;
652 query->num_cs_dw_end = 8 + r600_gfx_write_fence_dwords(rscreen);
653 query->flags = R600_QUERY_HW_FLAG_NO_START;
654 break;
655 case PIPE_QUERY_PRIMITIVES_EMITTED:
656 case PIPE_QUERY_PRIMITIVES_GENERATED:
657 case PIPE_QUERY_SO_STATISTICS:
658 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
659 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
660 query->result_size = 32;
661 query->num_cs_dw_begin = 6;
662 query->num_cs_dw_end = 6;
663 query->stream = index;
664 break;
665 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
666 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
667 query->result_size = 32 * R600_MAX_STREAMS;
668 query->num_cs_dw_begin = 6 * R600_MAX_STREAMS;
669 query->num_cs_dw_end = 6 * R600_MAX_STREAMS;
670 break;
671 case PIPE_QUERY_PIPELINE_STATISTICS:
672 /* 11 values on EG, 8 on R600. */
673 query->result_size = (rscreen->chip_class >= EVERGREEN ? 11 : 8) * 16;
674 query->result_size += 8; /* for the fence + alignment */
675 query->num_cs_dw_begin = 6;
676 query->num_cs_dw_end = 6 + r600_gfx_write_fence_dwords(rscreen);
677 break;
678 default:
679 assert(0);
680 FREE(query);
681 return NULL;
682 }
683
684 if (!r600_query_hw_init(rscreen, query)) {
685 FREE(query);
686 return NULL;
687 }
688
689 return (struct pipe_query *)query;
690 }
691
692 static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
693 unsigned type, int diff)
694 {
695 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
696 type == PIPE_QUERY_OCCLUSION_PREDICATE) {
697 bool old_enable = rctx->num_occlusion_queries != 0;
698 bool old_perfect_enable =
699 rctx->num_perfect_occlusion_queries != 0;
700 bool enable, perfect_enable;
701
702 rctx->num_occlusion_queries += diff;
703 assert(rctx->num_occlusion_queries >= 0);
704
705 if (type == PIPE_QUERY_OCCLUSION_COUNTER) {
706 rctx->num_perfect_occlusion_queries += diff;
707 assert(rctx->num_perfect_occlusion_queries >= 0);
708 }
709
710 enable = rctx->num_occlusion_queries != 0;
711 perfect_enable = rctx->num_perfect_occlusion_queries != 0;
712
713 if (enable != old_enable || perfect_enable != old_perfect_enable) {
714 struct r600_context *ctx = (struct r600_context*)rctx;
715 r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
716 }
717 }
718 }
719
720 static unsigned event_type_for_stream(unsigned stream)
721 {
722 switch (stream) {
723 default:
724 case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS;
725 case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1;
726 case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2;
727 case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3;
728 }
729 }
730
731 static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va,
732 unsigned stream)
733 {
734 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
735 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | EVENT_INDEX(3));
736 radeon_emit(cs, va);
737 radeon_emit(cs, va >> 32);
738 }
739
740 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
741 struct r600_query_hw *query,
742 struct r600_resource *buffer,
743 uint64_t va)
744 {
745 struct radeon_winsys_cs *cs = ctx->gfx.cs;
746
747 switch (query->b.type) {
748 case PIPE_QUERY_OCCLUSION_COUNTER:
749 case PIPE_QUERY_OCCLUSION_PREDICATE:
750 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
751 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
752 radeon_emit(cs, va);
753 radeon_emit(cs, va >> 32);
754 break;
755 case PIPE_QUERY_PRIMITIVES_EMITTED:
756 case PIPE_QUERY_PRIMITIVES_GENERATED:
757 case PIPE_QUERY_SO_STATISTICS:
758 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
759 emit_sample_streamout(cs, va, query->stream);
760 break;
761 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
762 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
763 emit_sample_streamout(cs, va + 32 * stream, stream);
764 break;
765 case PIPE_QUERY_TIME_ELAPSED:
766 if (ctx->chip_class >= SI) {
767 /* Write the timestamp from the CP not waiting for
768 * outstanding draws (top-of-pipe).
769 */
770 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
771 radeon_emit(cs, COPY_DATA_COUNT_SEL |
772 COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
773 COPY_DATA_DST_SEL(COPY_DATA_MEM_ASYNC));
774 radeon_emit(cs, 0);
775 radeon_emit(cs, 0);
776 radeon_emit(cs, va);
777 radeon_emit(cs, va >> 32);
778 } else {
779 /* Write the timestamp after the last draw is done.
780 * (bottom-of-pipe)
781 */
782 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
783 0, EOP_DATA_SEL_TIMESTAMP,
784 NULL, va, 0, query->b.type);
785 }
786 break;
787 case PIPE_QUERY_PIPELINE_STATISTICS:
788 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
789 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
790 radeon_emit(cs, va);
791 radeon_emit(cs, va >> 32);
792 break;
793 default:
794 assert(0);
795 }
796 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
797 RADEON_PRIO_QUERY);
798 }
799
800 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
801 struct r600_query_hw *query)
802 {
803 uint64_t va;
804
805 if (!query->buffer.buf)
806 return; // previous buffer allocation failure
807
808 r600_update_occlusion_query_state(ctx, query->b.type, 1);
809 r600_update_prims_generated_query_state(ctx, query->b.type, 1);
810
811 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
812 true);
813
814 /* Get a new query buffer if needed. */
815 if (query->buffer.results_end + query->result_size > query->buffer.buf->b.b.width0) {
816 struct r600_query_buffer *qbuf = MALLOC_STRUCT(r600_query_buffer);
817 *qbuf = query->buffer;
818 query->buffer.results_end = 0;
819 query->buffer.previous = qbuf;
820 query->buffer.buf = r600_new_query_buffer(ctx->screen, query);
821 if (!query->buffer.buf)
822 return;
823 }
824
825 /* emit begin query */
826 va = query->buffer.buf->gpu_address + query->buffer.results_end;
827
828 query->ops->emit_start(ctx, query, query->buffer.buf, va);
829
830 ctx->num_cs_dw_queries_suspend += query->num_cs_dw_end;
831 }
832
833 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
834 struct r600_query_hw *query,
835 struct r600_resource *buffer,
836 uint64_t va)
837 {
838 struct radeon_winsys_cs *cs = ctx->gfx.cs;
839 uint64_t fence_va = 0;
840
841 switch (query->b.type) {
842 case PIPE_QUERY_OCCLUSION_COUNTER:
843 case PIPE_QUERY_OCCLUSION_PREDICATE:
844 va += 8;
845 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
846 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
847 radeon_emit(cs, va);
848 radeon_emit(cs, va >> 32);
849
850 fence_va = va + ctx->screen->info.num_render_backends * 16 - 8;
851 break;
852 case PIPE_QUERY_PRIMITIVES_EMITTED:
853 case PIPE_QUERY_PRIMITIVES_GENERATED:
854 case PIPE_QUERY_SO_STATISTICS:
855 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
856 va += 16;
857 emit_sample_streamout(cs, va, query->stream);
858 break;
859 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
860 va += 16;
861 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream)
862 emit_sample_streamout(cs, va + 32 * stream, stream);
863 break;
864 case PIPE_QUERY_TIME_ELAPSED:
865 va += 8;
866 /* fall through */
867 case PIPE_QUERY_TIMESTAMP:
868 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
869 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
870 0, query->b.type);
871 fence_va = va + 8;
872 break;
873 case PIPE_QUERY_PIPELINE_STATISTICS: {
874 unsigned sample_size = (query->result_size - 8) / 2;
875
876 va += sample_size;
877 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
878 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
879 radeon_emit(cs, va);
880 radeon_emit(cs, va >> 32);
881
882 fence_va = va + sample_size;
883 break;
884 }
885 default:
886 assert(0);
887 }
888 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE,
889 RADEON_PRIO_QUERY);
890
891 if (fence_va)
892 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
893 EOP_DATA_SEL_VALUE_32BIT,
894 query->buffer.buf, fence_va, 0x80000000,
895 query->b.type);
896 }
897
898 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
899 struct r600_query_hw *query)
900 {
901 uint64_t va;
902
903 if (!query->buffer.buf)
904 return; // previous buffer allocation failure
905
906 /* The queries which need begin already called this in begin_query. */
907 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
908 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_end, false);
909 }
910
911 /* emit end query */
912 va = query->buffer.buf->gpu_address + query->buffer.results_end;
913
914 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
915
916 query->buffer.results_end += query->result_size;
917
918 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
919 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
920
921 r600_update_occlusion_query_state(ctx, query->b.type, -1);
922 r600_update_prims_generated_query_state(ctx, query->b.type, -1);
923 }
924
925 static void emit_set_predicate(struct r600_common_context *ctx,
926 struct r600_resource *buf, uint64_t va,
927 uint32_t op)
928 {
929 struct radeon_winsys_cs *cs = ctx->gfx.cs;
930
931 if (ctx->chip_class >= GFX9) {
932 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
933 radeon_emit(cs, op);
934 radeon_emit(cs, va);
935 radeon_emit(cs, va >> 32);
936 } else {
937 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
938 radeon_emit(cs, va);
939 radeon_emit(cs, op | ((va >> 32) & 0xFF));
940 }
941 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ,
942 RADEON_PRIO_QUERY);
943 }
944
945 static void r600_emit_query_predication(struct r600_common_context *ctx,
946 struct r600_atom *atom)
947 {
948 struct r600_query_hw *query = (struct r600_query_hw *)ctx->render_cond;
949 struct r600_query_buffer *qbuf;
950 uint32_t op;
951 bool flag_wait, invert;
952
953 if (!query)
954 return;
955
956 invert = ctx->render_cond_invert;
957 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
958 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
959
960 if (query->workaround_buf) {
961 op = PRED_OP(PREDICATION_OP_BOOL64);
962 } else {
963 switch (query->b.type) {
964 case PIPE_QUERY_OCCLUSION_COUNTER:
965 case PIPE_QUERY_OCCLUSION_PREDICATE:
966 op = PRED_OP(PREDICATION_OP_ZPASS);
967 break;
968 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
969 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
970 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
971 invert = !invert;
972 break;
973 default:
974 assert(0);
975 return;
976 }
977 }
978
979 /* if true then invert, see GL_ARB_conditional_render_inverted */
980 if (invert)
981 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visible or overflow */
982 else
983 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visible or no overflow */
984
985 /* Use the value written by compute shader as a workaround. Note that
986 * the wait flag does not apply in this predication mode.
987 *
988 * The shader outputs the result value to L2. Workarounds only affect VI
989 * and later, where the CP reads data from L2, so we don't need an
990 * additional flush.
991 */
992 if (query->workaround_buf) {
993 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset;
994 emit_set_predicate(ctx, query->workaround_buf, va, op);
995 return;
996 }
997
998 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
999
1000 /* emit predicate packets for all data blocks */
1001 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1002 unsigned results_base = 0;
1003 uint64_t va_base = qbuf->buf->gpu_address;
1004
1005 while (results_base < qbuf->results_end) {
1006 uint64_t va = va_base + results_base;
1007
1008 if (query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE) {
1009 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream) {
1010 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
1011
1012 /* set CONTINUE bit for all packets except the first */
1013 op |= PREDICATION_CONTINUE;
1014 }
1015 } else {
1016 emit_set_predicate(ctx, qbuf->buf, va, op);
1017 op |= PREDICATION_CONTINUE;
1018 }
1019
1020 results_base += query->result_size;
1021 }
1022 }
1023 }
1024
1025 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
1026 {
1027 struct r600_common_screen *rscreen =
1028 (struct r600_common_screen *)ctx->screen;
1029
1030 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
1031 query_type == PIPE_QUERY_GPU_FINISHED ||
1032 query_type >= PIPE_QUERY_DRIVER_SPECIFIC)
1033 return r600_query_sw_create(query_type);
1034
1035 return r600_query_hw_create(rscreen, query_type, index);
1036 }
1037
1038 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1039 {
1040 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1041 struct r600_query *rquery = (struct r600_query *)query;
1042
1043 rquery->ops->destroy(rctx->screen, rquery);
1044 }
1045
1046 static boolean r600_begin_query(struct pipe_context *ctx,
1047 struct pipe_query *query)
1048 {
1049 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1050 struct r600_query *rquery = (struct r600_query *)query;
1051
1052 return rquery->ops->begin(rctx, rquery);
1053 }
1054
1055 void r600_query_hw_reset_buffers(struct r600_common_context *rctx,
1056 struct r600_query_hw *query)
1057 {
1058 struct r600_query_buffer *prev = query->buffer.previous;
1059
1060 /* Discard the old query buffers. */
1061 while (prev) {
1062 struct r600_query_buffer *qbuf = prev;
1063 prev = prev->previous;
1064 r600_resource_reference(&qbuf->buf, NULL);
1065 FREE(qbuf);
1066 }
1067
1068 query->buffer.results_end = 0;
1069 query->buffer.previous = NULL;
1070
1071 /* Obtain a new buffer if the current one can't be mapped without a stall. */
1072 if (r600_rings_is_buffer_referenced(rctx, query->buffer.buf->buf, RADEON_USAGE_READWRITE) ||
1073 !rctx->ws->buffer_wait(query->buffer.buf->buf, 0, RADEON_USAGE_READWRITE)) {
1074 r600_resource_reference(&query->buffer.buf, NULL);
1075 query->buffer.buf = r600_new_query_buffer(rctx->screen, query);
1076 } else {
1077 if (!query->ops->prepare_buffer(rctx->screen, query, query->buffer.buf))
1078 r600_resource_reference(&query->buffer.buf, NULL);
1079 }
1080 }
1081
1082 bool r600_query_hw_begin(struct r600_common_context *rctx,
1083 struct r600_query *rquery)
1084 {
1085 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1086
1087 if (query->flags & R600_QUERY_HW_FLAG_NO_START) {
1088 assert(0);
1089 return false;
1090 }
1091
1092 if (!(query->flags & R600_QUERY_HW_FLAG_BEGIN_RESUMES))
1093 r600_query_hw_reset_buffers(rctx, query);
1094
1095 r600_resource_reference(&query->workaround_buf, NULL);
1096
1097 r600_query_hw_emit_start(rctx, query);
1098 if (!query->buffer.buf)
1099 return false;
1100
1101 LIST_ADDTAIL(&query->list, &rctx->active_queries);
1102 return true;
1103 }
1104
1105 static bool r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
1106 {
1107 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1108 struct r600_query *rquery = (struct r600_query *)query;
1109
1110 return rquery->ops->end(rctx, rquery);
1111 }
1112
1113 bool r600_query_hw_end(struct r600_common_context *rctx,
1114 struct r600_query *rquery)
1115 {
1116 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1117
1118 if (query->flags & R600_QUERY_HW_FLAG_NO_START)
1119 r600_query_hw_reset_buffers(rctx, query);
1120
1121 r600_query_hw_emit_stop(rctx, query);
1122
1123 if (!(query->flags & R600_QUERY_HW_FLAG_NO_START))
1124 LIST_DELINIT(&query->list);
1125
1126 if (!query->buffer.buf)
1127 return false;
1128
1129 return true;
1130 }
1131
1132 static void r600_get_hw_query_params(struct r600_common_context *rctx,
1133 struct r600_query_hw *rquery, int index,
1134 struct r600_hw_query_params *params)
1135 {
1136 unsigned max_rbs = rctx->screen->info.num_render_backends;
1137
1138 params->pair_stride = 0;
1139 params->pair_count = 1;
1140
1141 switch (rquery->b.type) {
1142 case PIPE_QUERY_OCCLUSION_COUNTER:
1143 case PIPE_QUERY_OCCLUSION_PREDICATE:
1144 params->start_offset = 0;
1145 params->end_offset = 8;
1146 params->fence_offset = max_rbs * 16;
1147 params->pair_stride = 16;
1148 params->pair_count = max_rbs;
1149 break;
1150 case PIPE_QUERY_TIME_ELAPSED:
1151 params->start_offset = 0;
1152 params->end_offset = 8;
1153 params->fence_offset = 16;
1154 break;
1155 case PIPE_QUERY_TIMESTAMP:
1156 params->start_offset = 0;
1157 params->end_offset = 0;
1158 params->fence_offset = 8;
1159 break;
1160 case PIPE_QUERY_PRIMITIVES_EMITTED:
1161 params->start_offset = 8;
1162 params->end_offset = 24;
1163 params->fence_offset = params->end_offset + 4;
1164 break;
1165 case PIPE_QUERY_PRIMITIVES_GENERATED:
1166 params->start_offset = 0;
1167 params->end_offset = 16;
1168 params->fence_offset = params->end_offset + 4;
1169 break;
1170 case PIPE_QUERY_SO_STATISTICS:
1171 params->start_offset = 8 - index * 8;
1172 params->end_offset = 24 - index * 8;
1173 params->fence_offset = params->end_offset + 4;
1174 break;
1175 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1176 params->pair_count = R600_MAX_STREAMS;
1177 params->pair_stride = 32;
1178 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1179 params->start_offset = 0;
1180 params->end_offset = 16;
1181
1182 /* We can re-use the high dword of the last 64-bit value as a
1183 * fence: it is initialized as 0, and the high bit is set by
1184 * the write of the streamout stats event.
1185 */
1186 params->fence_offset = rquery->result_size - 4;
1187 break;
1188 case PIPE_QUERY_PIPELINE_STATISTICS:
1189 {
1190 /* Offsets apply to EG+ */
1191 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1192 params->start_offset = offsets[index];
1193 params->end_offset = 88 + offsets[index];
1194 params->fence_offset = 2 * 88;
1195 break;
1196 }
1197 default:
1198 unreachable("r600_get_hw_query_params unsupported");
1199 }
1200 }
1201
1202 static unsigned r600_query_read_result(void *map, unsigned start_index, unsigned end_index,
1203 bool test_status_bit)
1204 {
1205 uint32_t *current_result = (uint32_t*)map;
1206 uint64_t start, end;
1207
1208 start = (uint64_t)current_result[start_index] |
1209 (uint64_t)current_result[start_index+1] << 32;
1210 end = (uint64_t)current_result[end_index] |
1211 (uint64_t)current_result[end_index+1] << 32;
1212
1213 if (!test_status_bit ||
1214 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1215 return end - start;
1216 }
1217 return 0;
1218 }
1219
1220 static void r600_query_hw_add_result(struct r600_common_screen *rscreen,
1221 struct r600_query_hw *query,
1222 void *buffer,
1223 union pipe_query_result *result)
1224 {
1225 unsigned max_rbs = rscreen->info.num_render_backends;
1226
1227 switch (query->b.type) {
1228 case PIPE_QUERY_OCCLUSION_COUNTER: {
1229 for (unsigned i = 0; i < max_rbs; ++i) {
1230 unsigned results_base = i * 16;
1231 result->u64 +=
1232 r600_query_read_result(buffer + results_base, 0, 2, true);
1233 }
1234 break;
1235 }
1236 case PIPE_QUERY_OCCLUSION_PREDICATE: {
1237 for (unsigned i = 0; i < max_rbs; ++i) {
1238 unsigned results_base = i * 16;
1239 result->b = result->b ||
1240 r600_query_read_result(buffer + results_base, 0, 2, true) != 0;
1241 }
1242 break;
1243 }
1244 case PIPE_QUERY_TIME_ELAPSED:
1245 result->u64 += r600_query_read_result(buffer, 0, 2, false);
1246 break;
1247 case PIPE_QUERY_TIMESTAMP:
1248 result->u64 = *(uint64_t*)buffer;
1249 break;
1250 case PIPE_QUERY_PRIMITIVES_EMITTED:
1251 /* SAMPLE_STREAMOUTSTATS stores this structure:
1252 * {
1253 * u64 NumPrimitivesWritten;
1254 * u64 PrimitiveStorageNeeded;
1255 * }
1256 * We only need NumPrimitivesWritten here. */
1257 result->u64 += r600_query_read_result(buffer, 2, 6, true);
1258 break;
1259 case PIPE_QUERY_PRIMITIVES_GENERATED:
1260 /* Here we read PrimitiveStorageNeeded. */
1261 result->u64 += r600_query_read_result(buffer, 0, 4, true);
1262 break;
1263 case PIPE_QUERY_SO_STATISTICS:
1264 result->so_statistics.num_primitives_written +=
1265 r600_query_read_result(buffer, 2, 6, true);
1266 result->so_statistics.primitives_storage_needed +=
1267 r600_query_read_result(buffer, 0, 4, true);
1268 break;
1269 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1270 result->b = result->b ||
1271 r600_query_read_result(buffer, 2, 6, true) !=
1272 r600_query_read_result(buffer, 0, 4, true);
1273 break;
1274 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1275 for (unsigned stream = 0; stream < R600_MAX_STREAMS; ++stream) {
1276 result->b = result->b ||
1277 r600_query_read_result(buffer, 2, 6, true) !=
1278 r600_query_read_result(buffer, 0, 4, true);
1279 buffer = (char *)buffer + 32;
1280 }
1281 break;
1282 case PIPE_QUERY_PIPELINE_STATISTICS:
1283 if (rscreen->chip_class >= EVERGREEN) {
1284 result->pipeline_statistics.ps_invocations +=
1285 r600_query_read_result(buffer, 0, 22, false);
1286 result->pipeline_statistics.c_primitives +=
1287 r600_query_read_result(buffer, 2, 24, false);
1288 result->pipeline_statistics.c_invocations +=
1289 r600_query_read_result(buffer, 4, 26, false);
1290 result->pipeline_statistics.vs_invocations +=
1291 r600_query_read_result(buffer, 6, 28, false);
1292 result->pipeline_statistics.gs_invocations +=
1293 r600_query_read_result(buffer, 8, 30, false);
1294 result->pipeline_statistics.gs_primitives +=
1295 r600_query_read_result(buffer, 10, 32, false);
1296 result->pipeline_statistics.ia_primitives +=
1297 r600_query_read_result(buffer, 12, 34, false);
1298 result->pipeline_statistics.ia_vertices +=
1299 r600_query_read_result(buffer, 14, 36, false);
1300 result->pipeline_statistics.hs_invocations +=
1301 r600_query_read_result(buffer, 16, 38, false);
1302 result->pipeline_statistics.ds_invocations +=
1303 r600_query_read_result(buffer, 18, 40, false);
1304 result->pipeline_statistics.cs_invocations +=
1305 r600_query_read_result(buffer, 20, 42, false);
1306 } else {
1307 result->pipeline_statistics.ps_invocations +=
1308 r600_query_read_result(buffer, 0, 16, false);
1309 result->pipeline_statistics.c_primitives +=
1310 r600_query_read_result(buffer, 2, 18, false);
1311 result->pipeline_statistics.c_invocations +=
1312 r600_query_read_result(buffer, 4, 20, false);
1313 result->pipeline_statistics.vs_invocations +=
1314 r600_query_read_result(buffer, 6, 22, false);
1315 result->pipeline_statistics.gs_invocations +=
1316 r600_query_read_result(buffer, 8, 24, false);
1317 result->pipeline_statistics.gs_primitives +=
1318 r600_query_read_result(buffer, 10, 26, false);
1319 result->pipeline_statistics.ia_primitives +=
1320 r600_query_read_result(buffer, 12, 28, false);
1321 result->pipeline_statistics.ia_vertices +=
1322 r600_query_read_result(buffer, 14, 30, false);
1323 }
1324 #if 0 /* for testing */
1325 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1326 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1327 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1328 result->pipeline_statistics.ia_vertices,
1329 result->pipeline_statistics.ia_primitives,
1330 result->pipeline_statistics.vs_invocations,
1331 result->pipeline_statistics.hs_invocations,
1332 result->pipeline_statistics.ds_invocations,
1333 result->pipeline_statistics.gs_invocations,
1334 result->pipeline_statistics.gs_primitives,
1335 result->pipeline_statistics.c_invocations,
1336 result->pipeline_statistics.c_primitives,
1337 result->pipeline_statistics.ps_invocations,
1338 result->pipeline_statistics.cs_invocations);
1339 #endif
1340 break;
1341 default:
1342 assert(0);
1343 }
1344 }
1345
1346 static boolean r600_get_query_result(struct pipe_context *ctx,
1347 struct pipe_query *query, boolean wait,
1348 union pipe_query_result *result)
1349 {
1350 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1351 struct r600_query *rquery = (struct r600_query *)query;
1352
1353 return rquery->ops->get_result(rctx, rquery, wait, result);
1354 }
1355
1356 static void r600_get_query_result_resource(struct pipe_context *ctx,
1357 struct pipe_query *query,
1358 boolean wait,
1359 enum pipe_query_value_type result_type,
1360 int index,
1361 struct pipe_resource *resource,
1362 unsigned offset)
1363 {
1364 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1365 struct r600_query *rquery = (struct r600_query *)query;
1366
1367 rquery->ops->get_result_resource(rctx, rquery, wait, result_type, index,
1368 resource, offset);
1369 }
1370
1371 static void r600_query_hw_clear_result(struct r600_query_hw *query,
1372 union pipe_query_result *result)
1373 {
1374 util_query_clear_result(result, query->b.type);
1375 }
1376
1377 bool r600_query_hw_get_result(struct r600_common_context *rctx,
1378 struct r600_query *rquery,
1379 bool wait, union pipe_query_result *result)
1380 {
1381 struct r600_common_screen *rscreen = rctx->screen;
1382 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1383 struct r600_query_buffer *qbuf;
1384
1385 query->ops->clear_result(query, result);
1386
1387 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1388 unsigned usage = PIPE_TRANSFER_READ |
1389 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
1390 unsigned results_base = 0;
1391 void *map;
1392
1393 if (rquery->b.flushed)
1394 map = rctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
1395 else
1396 map = r600_buffer_map_sync_with_rings(rctx, qbuf->buf, usage);
1397
1398 if (!map)
1399 return false;
1400
1401 while (results_base != qbuf->results_end) {
1402 query->ops->add_result(rscreen, query, map + results_base,
1403 result);
1404 results_base += query->result_size;
1405 }
1406 }
1407
1408 /* Convert the time to expected units. */
1409 if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
1410 rquery->type == PIPE_QUERY_TIMESTAMP) {
1411 result->u64 = (1000000 * result->u64) / rscreen->info.clock_crystal_freq;
1412 }
1413 return true;
1414 }
1415
1416 /* Create the compute shader that is used to collect the results.
1417 *
1418 * One compute grid with a single thread is launched for every query result
1419 * buffer. The thread (optionally) reads a previous summary buffer, then
1420 * accumulates data from the query result buffer, and writes the result either
1421 * to a summary buffer to be consumed by the next grid invocation or to the
1422 * user-supplied buffer.
1423 *
1424 * Data layout:
1425 *
1426 * CONST
1427 * 0.x = end_offset
1428 * 0.y = result_stride
1429 * 0.z = result_count
1430 * 0.w = bit field:
1431 * 1: read previously accumulated values
1432 * 2: write accumulated values for chaining
1433 * 4: write result available
1434 * 8: convert result to boolean (0/1)
1435 * 16: only read one dword and use that as result
1436 * 32: apply timestamp conversion
1437 * 64: store full 64 bits result
1438 * 128: store signed 32 bits result
1439 * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
1440 * 1.x = fence_offset
1441 * 1.y = pair_stride
1442 * 1.z = pair_count
1443 *
1444 * BUFFER[0] = query result buffer
1445 * BUFFER[1] = previous summary buffer
1446 * BUFFER[2] = next summary buffer or user-supplied buffer
1447 */
1448 static void r600_create_query_result_shader(struct r600_common_context *rctx)
1449 {
1450 /* TEMP[0].xy = accumulated result so far
1451 * TEMP[0].z = result not available
1452 *
1453 * TEMP[1].x = current result index
1454 * TEMP[1].y = current pair index
1455 */
1456 static const char text_tmpl[] =
1457 "COMP\n"
1458 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
1459 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
1460 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
1461 "DCL BUFFER[0]\n"
1462 "DCL BUFFER[1]\n"
1463 "DCL BUFFER[2]\n"
1464 "DCL CONST[0][0..1]\n"
1465 "DCL TEMP[0..5]\n"
1466 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
1467 "IMM[1] UINT32 {1, 2, 4, 8}\n"
1468 "IMM[2] UINT32 {16, 32, 64, 128}\n"
1469 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
1470 "IMM[4] UINT32 {256, 0, 0, 0}\n"
1471
1472 "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
1473 "UIF TEMP[5]\n"
1474 /* Check result availability. */
1475 "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
1476 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
1477 "MOV TEMP[1], TEMP[0].zzzz\n"
1478 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1479
1480 /* Load result if available. */
1481 "UIF TEMP[1]\n"
1482 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
1483 "ENDIF\n"
1484 "ELSE\n"
1485 /* Load previously accumulated result if requested. */
1486 "MOV TEMP[0], IMM[0].xxxx\n"
1487 "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
1488 "UIF TEMP[4]\n"
1489 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
1490 "ENDIF\n"
1491
1492 "MOV TEMP[1].x, IMM[0].xxxx\n"
1493 "BGNLOOP\n"
1494 /* Break if accumulated result so far is not available. */
1495 "UIF TEMP[0].zzzz\n"
1496 "BRK\n"
1497 "ENDIF\n"
1498
1499 /* Break if result_index >= result_count. */
1500 "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
1501 "UIF TEMP[5]\n"
1502 "BRK\n"
1503 "ENDIF\n"
1504
1505 /* Load fence and check result availability */
1506 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
1507 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
1508 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
1509 "NOT TEMP[0].z, TEMP[0].zzzz\n"
1510 "UIF TEMP[0].zzzz\n"
1511 "BRK\n"
1512 "ENDIF\n"
1513
1514 "MOV TEMP[1].y, IMM[0].xxxx\n"
1515 "BGNLOOP\n"
1516 /* Load start and end. */
1517 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
1518 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
1519 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1520
1521 "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
1522 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1523
1524 "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
1525
1526 "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
1527 "UIF TEMP[5].zzzz\n"
1528 /* Load second start/end half-pair and
1529 * take the difference
1530 */
1531 "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
1532 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
1533 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
1534
1535 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
1536 "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
1537 "ENDIF\n"
1538
1539 "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
1540
1541 /* Increment pair index */
1542 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
1543 "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
1544 "UIF TEMP[5]\n"
1545 "BRK\n"
1546 "ENDIF\n"
1547 "ENDLOOP\n"
1548
1549 /* Increment result index */
1550 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
1551 "ENDLOOP\n"
1552 "ENDIF\n"
1553
1554 "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
1555 "UIF TEMP[4]\n"
1556 /* Store accumulated data for chaining. */
1557 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
1558 "ELSE\n"
1559 "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
1560 "UIF TEMP[4]\n"
1561 /* Store result availability. */
1562 "NOT TEMP[0].z, TEMP[0]\n"
1563 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
1564 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
1565
1566 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1567 "UIF TEMP[4]\n"
1568 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
1569 "ENDIF\n"
1570 "ELSE\n"
1571 /* Store result if it is available. */
1572 "NOT TEMP[4], TEMP[0].zzzz\n"
1573 "UIF TEMP[4]\n"
1574 /* Apply timestamp conversion */
1575 "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
1576 "UIF TEMP[4]\n"
1577 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
1578 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
1579 "ENDIF\n"
1580
1581 /* Convert to boolean */
1582 "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
1583 "UIF TEMP[4]\n"
1584 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
1585 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
1586 "MOV TEMP[0].y, IMM[0].xxxx\n"
1587 "ENDIF\n"
1588
1589 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
1590 "UIF TEMP[4]\n"
1591 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
1592 "ELSE\n"
1593 /* Clamping */
1594 "UIF TEMP[0].yyyy\n"
1595 "MOV TEMP[0].x, IMM[0].wwww\n"
1596 "ENDIF\n"
1597
1598 "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
1599 "UIF TEMP[4]\n"
1600 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
1601 "ENDIF\n"
1602
1603 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
1604 "ENDIF\n"
1605 "ENDIF\n"
1606 "ENDIF\n"
1607 "ENDIF\n"
1608
1609 "END\n";
1610
1611 char text[sizeof(text_tmpl) + 32];
1612 struct tgsi_token tokens[1024];
1613 struct pipe_compute_state state = {};
1614
1615 /* Hard code the frequency into the shader so that the backend can
1616 * use the full range of optimizations for divide-by-constant.
1617 */
1618 snprintf(text, sizeof(text), text_tmpl,
1619 rctx->screen->info.clock_crystal_freq);
1620
1621 if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
1622 assert(false);
1623 return;
1624 }
1625
1626 state.ir_type = PIPE_SHADER_IR_TGSI;
1627 state.prog = tokens;
1628
1629 rctx->query_result_shader = rctx->b.create_compute_state(&rctx->b, &state);
1630 }
1631
1632 static void r600_restore_qbo_state(struct r600_common_context *rctx,
1633 struct r600_qbo_state *st)
1634 {
1635 rctx->b.bind_compute_state(&rctx->b, st->saved_compute);
1636
1637 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1638 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1639
1640 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1641 for (unsigned i = 0; i < 3; ++i)
1642 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1643 }
1644
1645 static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
1646 struct r600_query *rquery,
1647 bool wait,
1648 enum pipe_query_value_type result_type,
1649 int index,
1650 struct pipe_resource *resource,
1651 unsigned offset)
1652 {
1653 struct r600_query_hw *query = (struct r600_query_hw *)rquery;
1654 struct r600_query_buffer *qbuf;
1655 struct r600_query_buffer *qbuf_prev;
1656 struct pipe_resource *tmp_buffer = NULL;
1657 unsigned tmp_buffer_offset = 0;
1658 struct r600_qbo_state saved_state = {};
1659 struct pipe_grid_info grid = {};
1660 struct pipe_constant_buffer constant_buffer = {};
1661 struct pipe_shader_buffer ssbo[3];
1662 struct r600_hw_query_params params;
1663 struct {
1664 uint32_t end_offset;
1665 uint32_t result_stride;
1666 uint32_t result_count;
1667 uint32_t config;
1668 uint32_t fence_offset;
1669 uint32_t pair_stride;
1670 uint32_t pair_count;
1671 } consts;
1672
1673 if (!rctx->query_result_shader) {
1674 r600_create_query_result_shader(rctx);
1675 if (!rctx->query_result_shader)
1676 return;
1677 }
1678
1679 if (query->buffer.previous) {
1680 u_suballocator_alloc(rctx->allocator_zeroed_memory, 16, 16,
1681 &tmp_buffer_offset, &tmp_buffer);
1682 if (!tmp_buffer)
1683 return;
1684 }
1685
1686 rctx->save_qbo_state(&rctx->b, &saved_state);
1687
1688 r600_get_hw_query_params(rctx, query, index >= 0 ? index : 0, &params);
1689 consts.end_offset = params.end_offset - params.start_offset;
1690 consts.fence_offset = params.fence_offset - params.start_offset;
1691 consts.result_stride = query->result_size;
1692 consts.pair_stride = params.pair_stride;
1693 consts.pair_count = params.pair_count;
1694
1695 constant_buffer.buffer_size = sizeof(consts);
1696 constant_buffer.user_buffer = &consts;
1697
1698 ssbo[1].buffer = tmp_buffer;
1699 ssbo[1].buffer_offset = tmp_buffer_offset;
1700 ssbo[1].buffer_size = 16;
1701
1702 ssbo[2] = ssbo[1];
1703
1704 rctx->b.bind_compute_state(&rctx->b, rctx->query_result_shader);
1705
1706 grid.block[0] = 1;
1707 grid.block[1] = 1;
1708 grid.block[2] = 1;
1709 grid.grid[0] = 1;
1710 grid.grid[1] = 1;
1711 grid.grid[2] = 1;
1712
1713 consts.config = 0;
1714 if (index < 0)
1715 consts.config |= 4;
1716 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE)
1717 consts.config |= 8;
1718 else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
1719 query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1720 consts.config |= 8 | 256;
1721 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1722 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1723 consts.config |= 32;
1724
1725 switch (result_type) {
1726 case PIPE_QUERY_TYPE_U64:
1727 case PIPE_QUERY_TYPE_I64:
1728 consts.config |= 64;
1729 break;
1730 case PIPE_QUERY_TYPE_I32:
1731 consts.config |= 128;
1732 break;
1733 case PIPE_QUERY_TYPE_U32:
1734 break;
1735 }
1736
1737 rctx->flags |= rctx->screen->barrier_flags.cp_to_L2;
1738
1739 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1740 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1741 qbuf_prev = qbuf->previous;
1742 consts.result_count = qbuf->results_end / query->result_size;
1743 consts.config &= ~3;
1744 if (qbuf != &query->buffer)
1745 consts.config |= 1;
1746 if (qbuf->previous)
1747 consts.config |= 2;
1748 } else {
1749 /* Only read the last timestamp. */
1750 qbuf_prev = NULL;
1751 consts.result_count = 0;
1752 consts.config |= 16;
1753 params.start_offset += qbuf->results_end - query->result_size;
1754 }
1755
1756 rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1757
1758 ssbo[0].buffer = &qbuf->buf->b.b;
1759 ssbo[0].buffer_offset = params.start_offset;
1760 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1761
1762 if (!qbuf->previous) {
1763 ssbo[2].buffer = resource;
1764 ssbo[2].buffer_offset = offset;
1765 ssbo[2].buffer_size = 8;
1766
1767 ((struct r600_resource *)resource)->TC_L2_dirty = true;
1768 }
1769
1770 rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
1771
1772 if (wait && qbuf == &query->buffer) {
1773 uint64_t va;
1774
1775 /* Wait for result availability. Wait only for readiness
1776 * of the last entry, since the fence writes should be
1777 * serialized in the CP.
1778 */
1779 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1780 va += params.fence_offset;
1781
1782 r600_gfx_wait_fence(rctx, va, 0x80000000, 0x80000000);
1783 }
1784
1785 rctx->b.launch_grid(&rctx->b, &grid);
1786 rctx->flags |= rctx->screen->barrier_flags.compute_to_L2;
1787 }
1788
1789 r600_restore_qbo_state(rctx, &saved_state);
1790 pipe_resource_reference(&tmp_buffer, NULL);
1791 }
1792
1793 static void r600_render_condition(struct pipe_context *ctx,
1794 struct pipe_query *query,
1795 boolean condition,
1796 enum pipe_render_cond_flag mode)
1797 {
1798 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1799 struct r600_query_hw *rquery = (struct r600_query_hw *)query;
1800 struct r600_query_buffer *qbuf;
1801 struct r600_atom *atom = &rctx->render_cond_atom;
1802
1803 /* Compute the size of SET_PREDICATION packets. */
1804 atom->num_dw = 0;
1805 if (query) {
1806 bool needs_workaround = false;
1807
1808 /* There is a firmware regression in VI which causes successive
1809 * SET_PREDICATION packets to give the wrong answer for
1810 * non-inverted stream overflow predication.
1811 */
1812 if (rctx->chip_class >= VI && !condition &&
1813 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
1814 (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
1815 (rquery->buffer.previous ||
1816 rquery->buffer.results_end > rquery->result_size)))) {
1817 needs_workaround = true;
1818 }
1819
1820 if (needs_workaround && !rquery->workaround_buf) {
1821 bool old_force_off = rctx->render_cond_force_off;
1822 rctx->render_cond_force_off = true;
1823
1824 u_suballocator_alloc(
1825 rctx->allocator_zeroed_memory, 8, 8,
1826 &rquery->workaround_offset,
1827 (struct pipe_resource **)&rquery->workaround_buf);
1828
1829 /* Reset to NULL to avoid a redundant SET_PREDICATION
1830 * from launching the compute grid.
1831 */
1832 rctx->render_cond = NULL;
1833
1834 ctx->get_query_result_resource(
1835 ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
1836 &rquery->workaround_buf->b.b, rquery->workaround_offset);
1837
1838 /* Settings this in the render cond atom is too late,
1839 * so set it here. */
1840 rctx->flags |= rctx->screen->barrier_flags.L2_to_cp |
1841 R600_CONTEXT_FLUSH_FOR_RENDER_COND;
1842
1843 rctx->render_cond_force_off = old_force_off;
1844 }
1845
1846 if (needs_workaround) {
1847 atom->num_dw = 5;
1848 } else {
1849 for (qbuf = &rquery->buffer; qbuf; qbuf = qbuf->previous)
1850 atom->num_dw += (qbuf->results_end / rquery->result_size) * 5;
1851
1852 if (rquery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1853 atom->num_dw *= R600_MAX_STREAMS;
1854 }
1855 }
1856
1857 rctx->render_cond = query;
1858 rctx->render_cond_invert = condition;
1859 rctx->render_cond_mode = mode;
1860
1861 rctx->set_atom_dirty(rctx, atom, query != NULL);
1862 }
1863
1864 void r600_suspend_queries(struct r600_common_context *ctx)
1865 {
1866 struct r600_query_hw *query;
1867
1868 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1869 r600_query_hw_emit_stop(ctx, query);
1870 }
1871 assert(ctx->num_cs_dw_queries_suspend == 0);
1872 }
1873
1874 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
1875 struct list_head *query_list)
1876 {
1877 struct r600_query_hw *query;
1878 unsigned num_dw = 0;
1879
1880 LIST_FOR_EACH_ENTRY(query, query_list, list) {
1881 /* begin + end */
1882 num_dw += query->num_cs_dw_begin + query->num_cs_dw_end;
1883
1884 /* Workaround for the fact that
1885 * num_cs_dw_nontimer_queries_suspend is incremented for every
1886 * resumed query, which raises the bar in need_cs_space for
1887 * queries about to be resumed.
1888 */
1889 num_dw += query->num_cs_dw_end;
1890 }
1891 /* primitives generated query */
1892 num_dw += ctx->streamout.enable_atom.num_dw;
1893 /* guess for ZPASS enable or PERFECT_ZPASS_COUNT enable updates */
1894 num_dw += 13;
1895
1896 return num_dw;
1897 }
1898
1899 void r600_resume_queries(struct r600_common_context *ctx)
1900 {
1901 struct r600_query_hw *query;
1902 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, &ctx->active_queries);
1903
1904 assert(ctx->num_cs_dw_queries_suspend == 0);
1905
1906 /* Check CS space here. Resuming must not be interrupted by flushes. */
1907 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, true);
1908
1909 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1910 r600_query_hw_emit_start(ctx, query);
1911 }
1912 }
1913
1914 /* Fix radeon_info::enabled_rb_mask for R600, R700, EVERGREEN, NI. */
1915 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen)
1916 {
1917 struct r600_common_context *ctx =
1918 (struct r600_common_context*)rscreen->aux_context;
1919 struct radeon_winsys_cs *cs = ctx->gfx.cs;
1920 struct r600_resource *buffer;
1921 uint32_t *results;
1922 unsigned i, mask = 0;
1923 unsigned max_rbs = ctx->screen->info.num_render_backends;
1924
1925 assert(rscreen->chip_class <= CAYMAN);
1926
1927 /* if backend_map query is supported by the kernel */
1928 if (rscreen->info.r600_gb_backend_map_valid) {
1929 unsigned num_tile_pipes = rscreen->info.num_tile_pipes;
1930 unsigned backend_map = rscreen->info.r600_gb_backend_map;
1931 unsigned item_width, item_mask;
1932
1933 if (ctx->chip_class >= EVERGREEN) {
1934 item_width = 4;
1935 item_mask = 0x7;
1936 } else {
1937 item_width = 2;
1938 item_mask = 0x3;
1939 }
1940
1941 while (num_tile_pipes--) {
1942 i = backend_map & item_mask;
1943 mask |= (1<<i);
1944 backend_map >>= item_width;
1945 }
1946 if (mask != 0) {
1947 rscreen->info.enabled_rb_mask = mask;
1948 return;
1949 }
1950 }
1951
1952 /* otherwise backup path for older kernels */
1953
1954 /* create buffer for event data */
1955 buffer = (struct r600_resource*)
1956 pipe_buffer_create(ctx->b.screen, 0,
1957 PIPE_USAGE_STAGING, max_rbs * 16);
1958 if (!buffer)
1959 return;
1960
1961 /* initialize buffer with zeroes */
1962 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
1963 if (results) {
1964 memset(results, 0, max_rbs * 4 * 4);
1965
1966 /* emit EVENT_WRITE for ZPASS_DONE */
1967 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
1968 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
1969 radeon_emit(cs, buffer->gpu_address);
1970 radeon_emit(cs, buffer->gpu_address >> 32);
1971
1972 r600_emit_reloc(ctx, &ctx->gfx, buffer,
1973 RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
1974
1975 /* analyze results */
1976 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
1977 if (results) {
1978 for(i = 0; i < max_rbs; i++) {
1979 /* at least highest bit will be set if backend is used */
1980 if (results[i*4 + 1])
1981 mask |= (1<<i);
1982 }
1983 }
1984 }
1985
1986 r600_resource_reference(&buffer, NULL);
1987
1988 if (mask)
1989 rscreen->info.enabled_rb_mask = mask;
1990 }
1991
1992 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1993 { \
1994 .name = name_, \
1995 .query_type = R600_QUERY_##query_type_, \
1996 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1997 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1998 .group_id = group_id_ \
1999 }
2000
2001 #define X(name_, query_type_, type_, result_type_) \
2002 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
2003
2004 #define XG(group_, name_, query_type_, type_, result_type_) \
2005 XFULL(name_, query_type_, type_, result_type_, R600_QUERY_GROUP_##group_)
2006
2007 static struct pipe_driver_query_info r600_driver_query_list[] = {
2008 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
2009 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
2010 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
2011 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
2012 X("decompress-calls", DECOMPRESS_CALLS, UINT64, AVERAGE),
2013 X("MRT-draw-calls", MRT_DRAW_CALLS, UINT64, AVERAGE),
2014 X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, AVERAGE),
2015 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
2016 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
2017 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
2018 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
2019 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
2020 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
2021 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
2022 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
2023 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES, UINT64, AVERAGE),
2024 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES, UINT64, AVERAGE),
2025 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
2026 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
2027 X("num-resident-handles", NUM_RESIDENT_HANDLES, UINT64, AVERAGE),
2028 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS, UINT64, AVERAGE),
2029 X("tc-direct-slots", TC_DIRECT_SLOTS, UINT64, AVERAGE),
2030 X("tc-num-syncs", TC_NUM_SYNCS, UINT64, AVERAGE),
2031 X("CS-thread-busy", CS_THREAD_BUSY, UINT64, AVERAGE),
2032 X("gallium-thread-busy", GALLIUM_THREAD_BUSY, UINT64, AVERAGE),
2033 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
2034 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
2035 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
2036 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
2037 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
2038 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
2039 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
2040 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
2041 X("GFX-BO-list-size", GFX_BO_LIST_SIZE, UINT64, AVERAGE),
2042 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
2043 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
2044 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS, UINT64, CUMULATIVE),
2045 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
2046 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
2047 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
2048 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
2049
2050 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
2051 * which use it as a fallback path to detect the GPU type.
2052 *
2053 * Note: The names of these queries are significant for GPUPerfStudio
2054 * (and possibly their order as well). */
2055 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
2056 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
2057 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
2058 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
2059 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
2060
2061 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
2062 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
2063 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
2064
2065 /* The following queries must be at the end of the list because their
2066 * availability is adjusted dynamically based on the DRM version. */
2067 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
2068 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
2069 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
2070 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
2071 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
2072 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
2073 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
2074 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
2075 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
2076 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
2077 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
2078 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
2079 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
2080 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
2081 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
2082 X("GPU-pfp-busy", GPU_PFP_BUSY, UINT64, AVERAGE),
2083 X("GPU-meq-busy", GPU_MEQ_BUSY, UINT64, AVERAGE),
2084 X("GPU-me-busy", GPU_ME_BUSY, UINT64, AVERAGE),
2085 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
2086 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
2087 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
2088 };
2089
2090 #undef X
2091 #undef XG
2092 #undef XFULL
2093
2094 static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
2095 {
2096 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
2097 return ARRAY_SIZE(r600_driver_query_list);
2098 else if (rscreen->info.drm_major == 3) {
2099 if (rscreen->chip_class >= VI)
2100 return ARRAY_SIZE(r600_driver_query_list);
2101 else
2102 return ARRAY_SIZE(r600_driver_query_list) - 7;
2103 }
2104 else
2105 return ARRAY_SIZE(r600_driver_query_list) - 25;
2106 }
2107
2108 static int r600_get_driver_query_info(struct pipe_screen *screen,
2109 unsigned index,
2110 struct pipe_driver_query_info *info)
2111 {
2112 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
2113 unsigned num_queries = r600_get_num_queries(rscreen);
2114
2115 if (!info) {
2116 unsigned num_perfcounters =
2117 r600_get_perfcounter_info(rscreen, 0, NULL);
2118
2119 return num_queries + num_perfcounters;
2120 }
2121
2122 if (index >= num_queries)
2123 return r600_get_perfcounter_info(rscreen, index - num_queries, info);
2124
2125 *info = r600_driver_query_list[index];
2126
2127 switch (info->query_type) {
2128 case R600_QUERY_REQUESTED_VRAM:
2129 case R600_QUERY_VRAM_USAGE:
2130 case R600_QUERY_MAPPED_VRAM:
2131 info->max_value.u64 = rscreen->info.vram_size;
2132 break;
2133 case R600_QUERY_REQUESTED_GTT:
2134 case R600_QUERY_GTT_USAGE:
2135 case R600_QUERY_MAPPED_GTT:
2136 info->max_value.u64 = rscreen->info.gart_size;
2137 break;
2138 case R600_QUERY_GPU_TEMPERATURE:
2139 info->max_value.u64 = 125;
2140 break;
2141 case R600_QUERY_VRAM_VIS_USAGE:
2142 info->max_value.u64 = rscreen->info.vram_vis_size;
2143 break;
2144 }
2145
2146 if (info->group_id != ~(unsigned)0 && rscreen->perfcounters)
2147 info->group_id += rscreen->perfcounters->num_groups;
2148
2149 return 1;
2150 }
2151
2152 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
2153 * performance counter groups, so be careful when changing this and related
2154 * functions.
2155 */
2156 static int r600_get_driver_query_group_info(struct pipe_screen *screen,
2157 unsigned index,
2158 struct pipe_driver_query_group_info *info)
2159 {
2160 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
2161 unsigned num_pc_groups = 0;
2162
2163 if (rscreen->perfcounters)
2164 num_pc_groups = rscreen->perfcounters->num_groups;
2165
2166 if (!info)
2167 return num_pc_groups + R600_NUM_SW_QUERY_GROUPS;
2168
2169 if (index < num_pc_groups)
2170 return r600_get_perfcounter_group_info(rscreen, index, info);
2171
2172 index -= num_pc_groups;
2173 if (index >= R600_NUM_SW_QUERY_GROUPS)
2174 return 0;
2175
2176 info->name = "GPIN";
2177 info->max_active_queries = 5;
2178 info->num_queries = 5;
2179 return 1;
2180 }
2181
2182 void r600_query_init(struct r600_common_context *rctx)
2183 {
2184 rctx->b.create_query = r600_create_query;
2185 rctx->b.create_batch_query = r600_create_batch_query;
2186 rctx->b.destroy_query = r600_destroy_query;
2187 rctx->b.begin_query = r600_begin_query;
2188 rctx->b.end_query = r600_end_query;
2189 rctx->b.get_query_result = r600_get_query_result;
2190 rctx->b.get_query_result_resource = r600_get_query_result_resource;
2191 rctx->render_cond_atom.emit = r600_emit_query_predication;
2192
2193 if (((struct r600_common_screen*)rctx->b.screen)->info.num_render_backends > 0)
2194 rctx->b.render_condition = r600_render_condition;
2195
2196 LIST_INITHEAD(&rctx->active_queries);
2197 }
2198
2199 void r600_init_screen_query_functions(struct r600_common_screen *rscreen)
2200 {
2201 rscreen->b.get_driver_query_info = r600_get_driver_query_info;
2202 rscreen->b.get_driver_query_group_info = r600_get_driver_query_group_info;
2203 }