src/gallium/drivers/r600/r600_resource.h

   1 /*
   2  * Copyright 2010 Marek Olšák <maraeo@gmail.com
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef R600_RESOURCE_H
  24 #define R600_RESOURCE_H
  25
  26 #include "r600.h"
  27
  28 /* flag to indicate a resource is to be used as a transfer so should not be tiled */
  29 #define R600_RESOURCE_FLAG_TRANSFER             PIPE_RESOURCE_FLAG_DRV_PRIV
  30 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
  31 #define R600_RESOURCE_FLAG_FORCE_TILING         (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
  32
  33 struct r600_transfer {
  34         struct pipe_transfer            transfer;
  35         struct r600_resource            *staging;
  36         unsigned                        offset;
  37 };
  38
  39 struct compute_memory_item;
  40
  41 struct r600_resource_global {
  42         struct r600_resource base;
  43         struct compute_memory_item *chunk;
  44 };
  45
  46 struct r600_texture {
  47         struct r600_resource            resource;
  48
  49         unsigned                        array_mode[PIPE_MAX_TEXTURE_LEVELS];
  50         unsigned                        pitch_override;
  51         unsigned                        size;
  52         bool                            non_disp_tiling;
  53         bool                            is_depth;
  54         bool                            is_rat;
  55         unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
  56         struct r600_texture             *flushed_depth_texture;
  57         boolean                         is_flushing_texture;
  58         struct radeon_surface           surface;
  59
  60         /* FMASK and CMASK can only be used with MSAA textures for now.
  61          * MSAA textures cannot have mipmaps. */
  62         unsigned                        fmask_offset, fmask_size, fmask_bank_height;
  63         unsigned                        cmask_offset, cmask_size, cmask_slice_tile_max;
  64
  65         struct r600_resource            *htile;
  66         /* use htile only for first level */
  67         float                           depth_clear;
  68 };
  69
  70 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
  71
  72 struct r600_fmask_info {
  73         unsigned size;
  74         unsigned alignment;
  75         unsigned bank_height;
  76 };
  77
  78 struct r600_cmask_info {
  79         unsigned size;
  80         unsigned alignment;
  81         unsigned slice_tile_max;
  82 };
  83
  84 struct r600_surface {
  85         struct pipe_surface             base;
  86
  87         bool color_initialized;
  88         bool depth_initialized;
  89
  90         /* Misc. color flags. */
  91         bool alphatest_bypass;
  92         bool export_16bpc;
  93
  94         /* Color registers. */
  95         unsigned cb_color_info;
  96         unsigned cb_color_base;
  97         unsigned cb_color_view;
  98         unsigned cb_color_size;         /* R600 only */
  99         unsigned cb_color_dim;          /* EG only */
 100         unsigned cb_color_pitch;        /* EG only */
 101         unsigned cb_color_slice;        /* EG only */
 102         unsigned cb_color_attrib;       /* EG only */
 103         unsigned cb_color_fmask;        /* CB_COLORn_FMASK (EG) or CB_COLORn_FRAG (r600) */
 104         unsigned cb_color_fmask_slice;  /* EG only */
 105         unsigned cb_color_cmask;        /* CB_COLORn_CMASK (EG) or CB_COLORn_TILE (r600) */
 106         unsigned cb_color_cmask_slice;  /* EG only */
 107         unsigned cb_color_mask;         /* R600 only */
 108         struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
 109         struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
 110
 111         /* DB registers. */
 112         unsigned db_depth_info;         /* DB_Z_INFO (EG) or DB_DEPTH_INFO (r600) */
 113         unsigned db_depth_base;         /* DB_Z_READ/WRITE_BASE (EG) or DB_DEPTH_BASE (r600) */
 114         unsigned db_depth_view;
 115         unsigned db_depth_size;
 116         unsigned db_depth_slice;        /* EG only */
 117         unsigned db_stencil_base;       /* EG only */
 118         unsigned db_stencil_info;       /* EG only */
 119         unsigned db_prefetch_limit;     /* R600 only */
 120         unsigned pa_su_poly_offset_db_fmt_cntl;
 121
 122         unsigned                        htile_enabled;
 123         unsigned                        db_htile_surface;
 124         unsigned                        db_htile_data_base;
 125         unsigned                        db_preload_control;
 126 };
 127
 128 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
 129 static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
 130 {
 131         return rtex->resource.b.b.nr_samples <= 1 &&
 132                (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
 133                 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
 134 }
 135
 136 void r600_resource_destroy(struct pipe_screen *screen, struct pipe_resource *res);
 137 void r600_init_screen_resource_functions(struct pipe_screen *screen);
 138
 139 /* r600_texture */
 140 void r600_texture_get_fmask_info(struct r600_screen *rscreen,
 141                                  struct r600_texture *rtex,
 142                                  unsigned nr_samples,
 143                                  struct r600_fmask_info *out);
 144 void r600_texture_get_cmask_info(struct r600_screen *rscreen,
 145                                  struct r600_texture *rtex,
 146                                  struct r600_cmask_info *out);
 147 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 148                                         const struct pipe_resource *templ);
 149 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 150                                                 const struct pipe_resource *base,
 151                                                 struct winsys_handle *whandle);
 152
 153 static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
 154 {
 155         return (struct r600_resource*)r;
 156 }
 157
 158 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
 159                                      struct pipe_resource *texture,
 160                                      struct r600_texture **staging);
 161
 162 #endif