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052b4971f316f74c9a36cc477b45013da935160c
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
31 #include "r600_asm.h"
32 #include "r600_sq.h"
33 #include "r600d.h"
34 #include <stdio.h>
35 #include <errno.h>
36
37
38 struct r600_shader_tgsi_instruction;
39
40 struct r600_shader_ctx {
41 struct tgsi_shader_info info;
42 struct tgsi_parse_context parse;
43 const struct tgsi_token *tokens;
44 unsigned type;
45 unsigned file_offset[TGSI_FILE_COUNT];
46 unsigned temp_reg;
47 struct r600_shader_tgsi_instruction *inst_info;
48 struct r600_bc *bc;
49 struct r600_shader *shader;
50 u32 value[4];
51 };
52
53 struct r600_shader_tgsi_instruction {
54 unsigned tgsi_opcode;
55 unsigned is_op3;
56 unsigned r600_opcode;
57 int (*process)(struct r600_shader_ctx *ctx);
58 };
59
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[];
61 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
62
63 static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
64 {
65 struct r600_context *rctx = r600_context(ctx);
66 const struct util_format_description *desc;
67 enum pipe_format resource_format[160];
68 unsigned i, nresources = 0;
69 struct r600_bc *bc = &shader->bc;
70 struct r600_bc_cf *cf;
71 struct r600_bc_vtx *vtx;
72
73 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
74 return 0;
75 for (i = 0; i < rctx->vertex_elements->count; i++) {
76 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
77 }
78 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
79 switch (cf->inst) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
82 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
83 desc = util_format_description(resource_format[vtx->buffer_id]);
84 if (desc == NULL) {
85 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
86 return -EINVAL;
87 }
88 vtx->dst_sel_x = desc->swizzle[0];
89 vtx->dst_sel_y = desc->swizzle[1];
90 vtx->dst_sel_z = desc->swizzle[2];
91 vtx->dst_sel_w = desc->swizzle[3];
92 }
93 break;
94 default:
95 break;
96 }
97 }
98 return r600_bc_build(&shader->bc);
99 }
100
101 int r600_pipe_shader_create(struct pipe_context *ctx,
102 struct r600_context_state *rpshader,
103 const struct tgsi_token *tokens)
104 {
105 struct r600_screen *rscreen = r600_screen(ctx->screen);
106 int r;
107
108 //fprintf(stderr, "--------------------------------------------------------------\n");
109 //tgsi_dump(tokens, 0);
110 if (rpshader == NULL)
111 return -ENOMEM;
112 rpshader->shader.family = radeon_get_family(rscreen->rw);
113 r = r600_shader_from_tgsi(tokens, &rpshader->shader);
114 if (r) {
115 R600_ERR("translation from TGSI failed !\n");
116 return r;
117 }
118 r = r600_bc_build(&rpshader->shader.bc);
119 if (r) {
120 R600_ERR("building bytecode failed !\n");
121 return r;
122 }
123 //fprintf(stderr, "______________________________________________________________\n");
124 return 0;
125 }
126
127 static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
128 {
129 struct r600_screen *rscreen = r600_screen(ctx->screen);
130 struct r600_shader *rshader = &rpshader->shader;
131 struct radeon_state *state;
132 unsigned i, tmp;
133
134 rpshader->rstate = radeon_state_decref(rpshader->rstate);
135 state = radeon_state(rscreen->rw, R600_VS_SHADER);
136 if (state == NULL)
137 return -ENOMEM;
138 for (i = 0; i < 10; i++) {
139 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
140 }
141 /* so far never got proper semantic id from tgsi */
142 for (i = 0; i < 32; i++) {
143 tmp = i << ((i & 3) * 8);
144 state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
145 }
146 state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
147 state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
148 S_028868_STACK_SIZE(rshader->bc.nstack);
149 rpshader->rstate = state;
150 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
151 rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
152 rpshader->rstate->nbo = 2;
153 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
154 rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
155 state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
156 state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
157 return radeon_state_pm4(state);
158 }
159
160 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
161 {
162 const struct pipe_rasterizer_state *rasterizer;
163 struct r600_screen *rscreen = r600_screen(ctx->screen);
164 struct r600_shader *rshader = &rpshader->shader;
165 struct r600_context *rctx = r600_context(ctx);
166 struct radeon_state *state;
167 unsigned i, tmp, exports_ps, num_cout;
168
169 rasterizer = &rctx->rasterizer->state.rasterizer;
170 rpshader->rstate = radeon_state_decref(rpshader->rstate);
171 state = radeon_state(rscreen->rw, R600_PS_SHADER);
172 if (state == NULL)
173 return -ENOMEM;
174 for (i = 0; i < rshader->ninput; i++) {
175 tmp = S_028644_SEMANTIC(i);
176 tmp |= S_028644_SEL_CENTROID(1);
177 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
178 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
179 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
180 }
181 if (rasterizer->sprite_coord_enable & (1 << i)) {
182 tmp |= S_028644_PT_SPRITE_TEX(1);
183 }
184 state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
185 }
186
187 exports_ps = 0;
188 num_cout = 0;
189 for (i = 0; i < rshader->noutput; i++) {
190 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
191 exports_ps |= 1;
192 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
193 exports_ps |= (1 << (num_cout+1));
194 num_cout++;
195 }
196 }
197 if (!exports_ps) {
198 /* always at least export 1 component per pixel */
199 exports_ps = 2;
200 }
201 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
202 S_0286CC_PERSP_GRADIENT_ENA(1);
203 state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
204 state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
205 S_028868_STACK_SIZE(rshader->bc.nstack);
206 state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
207 rpshader->rstate = state;
208 rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
209 rpshader->rstate->nbo = 1;
210 rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
211 state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
212 return radeon_state_pm4(state);
213 }
214
215 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
216 {
217 struct r600_screen *rscreen = r600_screen(ctx->screen);
218 struct r600_context *rctx = r600_context(ctx);
219 struct r600_shader *rshader = &rpshader->shader;
220 int r;
221
222 /* copy new shader */
223 radeon_bo_decref(rscreen->rw, rpshader->bo);
224 rpshader->bo = NULL;
225 rpshader->bo = radeon_bo(rscreen->rw, 0, rshader->bc.ndw * 4,
226 4096, NULL);
227 if (rpshader->bo == NULL) {
228 return -ENOMEM;
229 }
230 radeon_bo_map(rscreen->rw, rpshader->bo);
231 memcpy(rpshader->bo->data, rshader->bc.bytecode, rshader->bc.ndw * 4);
232 radeon_bo_unmap(rscreen->rw, rpshader->bo);
233 /* build state */
234 rshader->flat_shade = rctx->flat_shade;
235 switch (rshader->processor_type) {
236 case TGSI_PROCESSOR_VERTEX:
237 r = r600_pipe_shader_vs(ctx, rpshader);
238 break;
239 case TGSI_PROCESSOR_FRAGMENT:
240 r = r600_pipe_shader_ps(ctx, rpshader);
241 break;
242 default:
243 r = -EINVAL;
244 break;
245 }
246 return r;
247 }
248
249 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
250 {
251 struct r600_context *rctx = r600_context(ctx);
252 int r;
253
254 if (rpshader == NULL)
255 return -EINVAL;
256 /* there should be enough input */
257 if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
258 R600_ERR("%d resources provided, expecting %d\n",
259 rctx->vertex_elements->count, rpshader->shader.bc.nresource);
260 return -EINVAL;
261 }
262 r = r600_shader_update(ctx, &rpshader->shader);
263 if (r)
264 return r;
265 return r600_pipe_shader(ctx, rpshader);
266 }
267
268 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
269 {
270 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
271 int j;
272
273 if (i->Instruction.NumDstRegs > 1) {
274 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
275 return -EINVAL;
276 }
277 if (i->Instruction.Predicate) {
278 R600_ERR("predicate unsupported\n");
279 return -EINVAL;
280 }
281 #if 0
282 if (i->Instruction.Label) {
283 R600_ERR("label unsupported\n");
284 return -EINVAL;
285 }
286 #endif
287 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
288 if (i->Src[j].Register.Indirect ||
289 i->Src[j].Register.Dimension ||
290 i->Src[j].Register.Absolute) {
291 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
292 return -EINVAL;
293 }
294 }
295 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
296 if (i->Dst[j].Register.Indirect || i->Dst[j].Register.Dimension) {
297 R600_ERR("unsupported dst (indirect|dimension)\n");
298 return -EINVAL;
299 }
300 }
301 return 0;
302 }
303
304 static int tgsi_declaration(struct r600_shader_ctx *ctx)
305 {
306 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
307 struct r600_bc_vtx vtx;
308 unsigned i;
309 int r;
310
311 switch (d->Declaration.File) {
312 case TGSI_FILE_INPUT:
313 i = ctx->shader->ninput++;
314 ctx->shader->input[i].name = d->Semantic.Name;
315 ctx->shader->input[i].sid = d->Semantic.Index;
316 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
317 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
318 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
319 /* turn input into fetch */
320 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
321 vtx.inst = 0;
322 vtx.fetch_type = 0;
323 vtx.buffer_id = i;
324 /* register containing the index into the buffer */
325 vtx.src_gpr = 0;
326 vtx.src_sel_x = 0;
327 vtx.mega_fetch_count = 0x1F;
328 vtx.dst_gpr = ctx->shader->input[i].gpr;
329 vtx.dst_sel_x = 0;
330 vtx.dst_sel_y = 1;
331 vtx.dst_sel_z = 2;
332 vtx.dst_sel_w = 3;
333 r = r600_bc_add_vtx(ctx->bc, &vtx);
334 if (r)
335 return r;
336 }
337 break;
338 case TGSI_FILE_OUTPUT:
339 i = ctx->shader->noutput++;
340 ctx->shader->output[i].name = d->Semantic.Name;
341 ctx->shader->output[i].sid = d->Semantic.Index;
342 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
343 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
344 break;
345 case TGSI_FILE_CONSTANT:
346 case TGSI_FILE_TEMPORARY:
347 case TGSI_FILE_SAMPLER:
348 break;
349 default:
350 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
351 return -EINVAL;
352 }
353 return 0;
354 }
355
356 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
357 {
358 struct tgsi_full_immediate *immediate;
359 struct r600_shader_ctx ctx;
360 struct r600_bc_output output[32];
361 unsigned output_done, noutput;
362 unsigned opcode;
363 int i, r = 0, pos0;
364
365 ctx.bc = &shader->bc;
366 ctx.shader = shader;
367 r = r600_bc_init(ctx.bc, shader->family);
368 if (r)
369 return r;
370 ctx.tokens = tokens;
371 tgsi_scan_shader(tokens, &ctx.info);
372 tgsi_parse_init(&ctx.parse, tokens);
373 ctx.type = ctx.parse.FullHeader.Processor.Processor;
374 shader->processor_type = ctx.type;
375
376 /* register allocations */
377 /* Values [0,127] correspond to GPR[0..127].
378 * Values [128,159] correspond to constant buffer bank 0
379 * Values [160,191] correspond to constant buffer bank 1
380 * Values [256,511] correspond to cfile constants c[0..255].
381 * Other special values are shown in the list below.
382 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
383 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
384 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
385 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
386 * 248 SQ_ALU_SRC_0: special constant 0.0.
387 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
388 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
389 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
390 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
391 * 253 SQ_ALU_SRC_LITERAL: literal constant.
392 * 254 SQ_ALU_SRC_PV: previous vector result.
393 * 255 SQ_ALU_SRC_PS: previous scalar result.
394 */
395 for (i = 0; i < TGSI_FILE_COUNT; i++) {
396 ctx.file_offset[i] = 0;
397 }
398 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
399 ctx.file_offset[TGSI_FILE_INPUT] = 1;
400 }
401 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
402 ctx.info.file_count[TGSI_FILE_INPUT];
403 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
404 ctx.info.file_count[TGSI_FILE_OUTPUT];
405 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
406 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
407 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
408 ctx.info.file_count[TGSI_FILE_TEMPORARY];
409
410 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
411 tgsi_parse_token(&ctx.parse);
412 switch (ctx.parse.FullToken.Token.Type) {
413 case TGSI_TOKEN_TYPE_IMMEDIATE:
414 immediate = &ctx.parse.FullToken.FullImmediate;
415 ctx.value[0] = immediate->u[0].Uint;
416 ctx.value[1] = immediate->u[1].Uint;
417 ctx.value[2] = immediate->u[2].Uint;
418 ctx.value[3] = immediate->u[3].Uint;
419 break;
420 case TGSI_TOKEN_TYPE_DECLARATION:
421 r = tgsi_declaration(&ctx);
422 if (r)
423 goto out_err;
424 break;
425 case TGSI_TOKEN_TYPE_INSTRUCTION:
426 r = tgsi_is_supported(&ctx);
427 if (r)
428 goto out_err;
429 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
430 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
431 r = ctx.inst_info->process(&ctx);
432 if (r)
433 goto out_err;
434 r = r600_bc_add_literal(ctx.bc, ctx.value);
435 if (r)
436 goto out_err;
437 break;
438 default:
439 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
440 r = -EINVAL;
441 goto out_err;
442 }
443 }
444 /* export output */
445 noutput = shader->noutput;
446 for (i = 0, pos0 = 0; i < noutput; i++) {
447 memset(&output[i], 0, sizeof(struct r600_bc_output));
448 output[i].gpr = shader->output[i].gpr;
449 output[i].elem_size = 3;
450 output[i].swizzle_x = 0;
451 output[i].swizzle_y = 1;
452 output[i].swizzle_z = 2;
453 output[i].swizzle_w = 3;
454 output[i].barrier = 1;
455 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
456 output[i].array_base = i - pos0;
457 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
458 switch (ctx.type) {
459 case TGSI_PROCESSOR_VERTEX:
460 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
461 output[i].array_base = 60;
462 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
463 /* position doesn't count in array_base */
464 pos0++;
465 }
466 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
467 output[i].array_base = 61;
468 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
469 /* position doesn't count in array_base */
470 pos0++;
471 }
472 break;
473 case TGSI_PROCESSOR_FRAGMENT:
474 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
475 output[i].array_base = shader->output[i].sid;
476 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
477 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
478 output[i].array_base = 61;
479 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
480 } else {
481 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
482 r = -EINVAL;
483 goto out_err;
484 }
485 break;
486 default:
487 R600_ERR("unsupported processor type %d\n", ctx.type);
488 r = -EINVAL;
489 goto out_err;
490 }
491 }
492 /* add fake param output for vertex shader if no param is exported */
493 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
494 for (i = 0, pos0 = 0; i < noutput; i++) {
495 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
496 pos0 = 1;
497 break;
498 }
499 }
500 if (!pos0) {
501 memset(&output[i], 0, sizeof(struct r600_bc_output));
502 output[i].gpr = 0;
503 output[i].elem_size = 3;
504 output[i].swizzle_x = 0;
505 output[i].swizzle_y = 1;
506 output[i].swizzle_z = 2;
507 output[i].swizzle_w = 3;
508 output[i].barrier = 1;
509 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
510 output[i].array_base = 0;
511 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
512 noutput++;
513 }
514 }
515 /* add fake pixel export */
516 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
517 memset(&output[0], 0, sizeof(struct r600_bc_output));
518 output[0].gpr = 0;
519 output[0].elem_size = 3;
520 output[0].swizzle_x = 7;
521 output[0].swizzle_y = 7;
522 output[0].swizzle_z = 7;
523 output[0].swizzle_w = 7;
524 output[0].barrier = 1;
525 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
526 output[0].array_base = 0;
527 output[0].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
528 noutput++;
529 }
530 /* set export done on last export of each type */
531 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
532 if (i == (noutput - 1)) {
533 output[i].end_of_program = 1;
534 }
535 if (!(output_done & (1 << output[i].type))) {
536 output_done |= (1 << output[i].type);
537 output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
538 }
539 }
540 /* add output to bytecode */
541 for (i = 0; i < noutput; i++) {
542 r = r600_bc_add_output(ctx.bc, &output[i]);
543 if (r)
544 goto out_err;
545 }
546 tgsi_parse_free(&ctx.parse);
547 return 0;
548 out_err:
549 tgsi_parse_free(&ctx.parse);
550 return r;
551 }
552
553 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
554 {
555 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
556 return -EINVAL;
557 }
558
559 static int tgsi_end(struct r600_shader_ctx *ctx)
560 {
561 return 0;
562 }
563
564 static int tgsi_src(struct r600_shader_ctx *ctx,
565 const struct tgsi_full_src_register *tgsi_src,
566 struct r600_bc_alu_src *r600_src)
567 {
568 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
569 r600_src->sel = tgsi_src->Register.Index;
570 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
571 r600_src->sel = 0;
572 }
573 r600_src->neg = tgsi_src->Register.Negate;
574 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
575 return 0;
576 }
577
578 static int tgsi_dst(struct r600_shader_ctx *ctx,
579 const struct tgsi_full_dst_register *tgsi_dst,
580 unsigned swizzle,
581 struct r600_bc_alu_dst *r600_dst)
582 {
583 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
584
585 r600_dst->sel = tgsi_dst->Register.Index;
586 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
587 r600_dst->chan = swizzle;
588 r600_dst->write = 1;
589 if (inst->Instruction.Saturate) {
590 r600_dst->clamp = 1;
591 }
592 return 0;
593 }
594
595 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
596 {
597 switch (swizzle) {
598 case 0:
599 return tgsi_src->Register.SwizzleX;
600 case 1:
601 return tgsi_src->Register.SwizzleY;
602 case 2:
603 return tgsi_src->Register.SwizzleZ;
604 case 3:
605 return tgsi_src->Register.SwizzleW;
606 default:
607 return 0;
608 }
609 }
610
611 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
612 {
613 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
614 struct r600_bc_alu alu;
615 int i, j, k, nconst, r;
616
617 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
618 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
619 nconst++;
620 }
621 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
622 if (r) {
623 return r;
624 }
625 }
626 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
627 if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
628 for (k = 0; k < 4; k++) {
629 memset(&alu, 0, sizeof(struct r600_bc_alu));
630 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
631 alu.src[0].sel = r600_src[0].sel;
632 alu.src[0].chan = k;
633 alu.dst.sel = ctx->temp_reg + j;
634 alu.dst.chan = k;
635 alu.dst.write = 1;
636 if (k == 3)
637 alu.last = 1;
638 r = r600_bc_add_alu(ctx->bc, &alu);
639 if (r)
640 return r;
641 }
642 r600_src[0].sel = ctx->temp_reg + j;
643 j--;
644 }
645 }
646 return 0;
647 }
648
649 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
650 {
651 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
652 struct r600_bc_alu_src r600_src[3];
653 struct r600_bc_alu alu;
654 int i, j, r;
655 int lasti = 0;
656
657 for (i = 0; i < 4; i++) {
658 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
659 lasti = i;
660 }
661 }
662
663 r = tgsi_split_constant(ctx, r600_src);
664 if (r)
665 return r;
666 for (i = 0; i < lasti + 1; i++) {
667 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
668 continue;
669
670 memset(&alu, 0, sizeof(struct r600_bc_alu));
671 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
672 if (r)
673 return r;
674
675 alu.inst = ctx->inst_info->r600_opcode;
676 if (!swap) {
677 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
678 alu.src[j] = r600_src[j];
679 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
680 }
681 } else {
682 alu.src[0] = r600_src[1];
683 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
684
685 alu.src[1] = r600_src[0];
686 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
687 }
688 /* handle some special cases */
689 switch (ctx->inst_info->tgsi_opcode) {
690 case TGSI_OPCODE_SUB:
691 alu.src[1].neg = 1;
692 break;
693 case TGSI_OPCODE_ABS:
694 alu.src[0].abs = 1;
695 break;
696 default:
697 break;
698 }
699 if (i == lasti) {
700 alu.last = 1;
701 }
702 r = r600_bc_add_alu(ctx->bc, &alu);
703 if (r)
704 return r;
705 }
706 return 0;
707 }
708
709 static int tgsi_op2(struct r600_shader_ctx *ctx)
710 {
711 return tgsi_op2_s(ctx, 0);
712 }
713
714 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
715 {
716 return tgsi_op2_s(ctx, 1);
717 }
718
719 /*
720 * r600 - trunc to -PI..PI range
721 * r700 - normalize by dividing by 2PI
722 * see fdo bug 27901
723 */
724 static int tgsi_trig(struct r600_shader_ctx *ctx)
725 {
726 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
727 struct r600_bc_alu_src r600_src[3];
728 struct r600_bc_alu alu;
729 int i, r;
730 uint32_t lit_vals[4];
731
732 memset(lit_vals, 0, 4*4);
733 r = tgsi_split_constant(ctx, r600_src);
734 if (r)
735 return r;
736 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
737 lit_vals[1] = fui(0.5f);
738
739 memset(&alu, 0, sizeof(struct r600_bc_alu));
740 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
741 alu.is_op3 = 1;
742
743 alu.dst.chan = 0;
744 alu.dst.sel = ctx->temp_reg;
745 alu.dst.write = 1;
746
747 alu.src[0] = r600_src[0];
748 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
749
750 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
751 alu.src[1].chan = 0;
752 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
753 alu.src[2].chan = 1;
754 alu.last = 1;
755 r = r600_bc_add_alu(ctx->bc, &alu);
756 if (r)
757 return r;
758 r = r600_bc_add_literal(ctx->bc, lit_vals);
759 if (r)
760 return r;
761
762 memset(&alu, 0, sizeof(struct r600_bc_alu));
763 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
764
765 alu.dst.chan = 0;
766 alu.dst.sel = ctx->temp_reg;
767 alu.dst.write = 1;
768
769 alu.src[0].sel = ctx->temp_reg;
770 alu.src[0].chan = 0;
771 alu.last = 1;
772 r = r600_bc_add_alu(ctx->bc, &alu);
773 if (r)
774 return r;
775
776 if (ctx->bc->chiprev == 0) {
777 lit_vals[0] = fui(3.1415926535897f * 2.0f);
778 lit_vals[1] = fui(-3.1415926535897f);
779 } else {
780 lit_vals[0] = fui(1.0f);
781 lit_vals[1] = fui(-0.5f);
782 }
783
784 memset(&alu, 0, sizeof(struct r600_bc_alu));
785 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
786 alu.is_op3 = 1;
787
788 alu.dst.chan = 0;
789 alu.dst.sel = ctx->temp_reg;
790 alu.dst.write = 1;
791
792 alu.src[0].sel = ctx->temp_reg;
793 alu.src[0].chan = 0;
794
795 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
796 alu.src[1].chan = 0;
797 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
798 alu.src[2].chan = 1;
799 alu.last = 1;
800 r = r600_bc_add_alu(ctx->bc, &alu);
801 if (r)
802 return r;
803 r = r600_bc_add_literal(ctx->bc, lit_vals);
804 if (r)
805 return r;
806
807 memset(&alu, 0, sizeof(struct r600_bc_alu));
808 alu.inst = ctx->inst_info->r600_opcode;
809 alu.dst.chan = 0;
810 alu.dst.sel = ctx->temp_reg;
811 alu.dst.write = 1;
812
813 alu.src[0].sel = ctx->temp_reg;
814 alu.src[0].chan = 0;
815 alu.last = 1;
816 r = r600_bc_add_alu(ctx->bc, &alu);
817 if (r)
818 return r;
819
820 /* replicate result */
821 for (i = 0; i < 4; i++) {
822 memset(&alu, 0, sizeof(struct r600_bc_alu));
823 alu.src[0].sel = ctx->temp_reg;
824 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
825 alu.dst.chan = i;
826 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
827 if (r)
828 return r;
829 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
830 if (i == 3)
831 alu.last = 1;
832 r = r600_bc_add_alu(ctx->bc, &alu);
833 if (r)
834 return r;
835 }
836 return 0;
837 }
838
839 static int tgsi_kill(struct r600_shader_ctx *ctx)
840 {
841 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
842 struct r600_bc_alu alu;
843 int i, r;
844
845 for (i = 0; i < 4; i++) {
846 memset(&alu, 0, sizeof(struct r600_bc_alu));
847 alu.inst = ctx->inst_info->r600_opcode;
848 alu.dst.chan = i;
849 alu.src[0].sel = V_SQ_ALU_SRC_0;
850 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
851 if (r)
852 return r;
853 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
854 if (i == 3) {
855 alu.last = 1;
856 }
857 r = r600_bc_add_alu(ctx->bc, &alu);
858 if (r)
859 return r;
860 }
861 return 0;
862 }
863
864 static int tgsi_lit(struct r600_shader_ctx *ctx)
865 {
866 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
867 struct r600_bc_alu alu;
868 int r;
869
870 /* dst.x, <- 1.0 */
871 memset(&alu, 0, sizeof(struct r600_bc_alu));
872 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
873 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
874 alu.src[0].chan = 0;
875 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
876 if (r)
877 return r;
878 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
879 r = r600_bc_add_alu(ctx->bc, &alu);
880 if (r)
881 return r;
882
883 /* dst.y = max(src.x, 0.0) */
884 memset(&alu, 0, sizeof(struct r600_bc_alu));
885 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
886 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
887 if (r)
888 return r;
889 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
890 alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
891 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
892 if (r)
893 return r;
894 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
895 r = r600_bc_add_alu(ctx->bc, &alu);
896 if (r)
897 return r;
898
899 /* dst.z = NOP - fill Z slot */
900 memset(&alu, 0, sizeof(struct r600_bc_alu));
901 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
902 alu.dst.chan = 2;
903 r = r600_bc_add_alu(ctx->bc, &alu);
904 if (r)
905 return r;
906
907 /* dst.w, <- 1.0 */
908 memset(&alu, 0, sizeof(struct r600_bc_alu));
909 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
910 alu.src[0].sel = V_SQ_ALU_SRC_1;
911 alu.src[0].chan = 0;
912 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
913 if (r)
914 return r;
915 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
916 alu.last = 1;
917 r = r600_bc_add_alu(ctx->bc, &alu);
918 if (r)
919 return r;
920
921 if (inst->Dst[0].Register.WriteMask & (1 << 2))
922 {
923 int chan;
924 int sel;
925
926 /* dst.z = log(src.y) */
927 memset(&alu, 0, sizeof(struct r600_bc_alu));
928 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED;
929 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
930 if (r)
931 return r;
932 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
933 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
934 if (r)
935 return r;
936 alu.last = 1;
937 r = r600_bc_add_alu(ctx->bc, &alu);
938 if (r)
939 return r;
940
941 chan = alu.dst.chan;
942 sel = alu.dst.sel;
943
944 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
945 memset(&alu, 0, sizeof(struct r600_bc_alu));
946 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
947 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
948 if (r)
949 return r;
950 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
951 alu.src[1].sel = sel;
952 alu.src[1].chan = chan;
953 r = tgsi_src(ctx, &inst->Src[0], &alu.src[2]);
954 if (r)
955 return r;
956 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
957 alu.dst.sel = ctx->temp_reg;
958 alu.dst.chan = 0;
959 alu.dst.write = 1;
960 alu.is_op3 = 1;
961 alu.last = 1;
962 r = r600_bc_add_alu(ctx->bc, &alu);
963 if (r)
964 return r;
965
966 /* dst.z = exp(tmp.x) */
967 memset(&alu, 0, sizeof(struct r600_bc_alu));
968 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
969 alu.src[0].sel = ctx->temp_reg;
970 alu.src[0].chan = 0;
971 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
972 if (r)
973 return r;
974 alu.last = 1;
975 r = r600_bc_add_alu(ctx->bc, &alu);
976 if (r)
977 return r;
978 }
979 return 0;
980 }
981
982 static int tgsi_trans(struct r600_shader_ctx *ctx)
983 {
984 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
985 struct r600_bc_alu alu;
986 int i, j, r;
987
988 for (i = 0; i < 4; i++) {
989 memset(&alu, 0, sizeof(struct r600_bc_alu));
990 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
991 alu.inst = ctx->inst_info->r600_opcode;
992 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
993 r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
994 if (r)
995 return r;
996 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
997 }
998 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
999 if (r)
1000 return r;
1001 alu.last = 1;
1002 r = r600_bc_add_alu(ctx->bc, &alu);
1003 if (r)
1004 return r;
1005 }
1006 }
1007 return 0;
1008 }
1009
1010 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1011 {
1012 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1013 struct r600_bc_alu alu;
1014 int i, r;
1015
1016 for (i = 0; i < 4; i++) {
1017 memset(&alu, 0, sizeof(struct r600_bc_alu));
1018 alu.src[0].sel = ctx->temp_reg;
1019 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1020 alu.dst.chan = i;
1021 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1022 if (r)
1023 return r;
1024 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1025 if (i == 3)
1026 alu.last = 1;
1027 r = r600_bc_add_alu(ctx->bc, &alu);
1028 if (r)
1029 return r;
1030 }
1031 return 0;
1032 }
1033
1034 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1035 {
1036 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1037 struct r600_bc_alu alu;
1038 int i, r;
1039
1040 memset(&alu, 0, sizeof(struct r600_bc_alu));
1041 alu.inst = ctx->inst_info->r600_opcode;
1042 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1043 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1044 if (r)
1045 return r;
1046 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1047 }
1048 alu.dst.sel = ctx->temp_reg;
1049 alu.dst.write = 1;
1050 alu.last = 1;
1051 r = r600_bc_add_alu(ctx->bc, &alu);
1052 if (r)
1053 return r;
1054 /* replicate result */
1055 return tgsi_helper_tempx_replicate(ctx);
1056 }
1057
1058 static int tgsi_pow(struct r600_shader_ctx *ctx)
1059 {
1060 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1061 struct r600_bc_alu alu;
1062 int r;
1063
1064 /* LOG2(a) */
1065 memset(&alu, 0, sizeof(struct r600_bc_alu));
1066 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE;
1067 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1068 if (r)
1069 return r;
1070 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1071 alu.dst.sel = ctx->temp_reg;
1072 alu.dst.write = 1;
1073 alu.last = 1;
1074 r = r600_bc_add_alu(ctx->bc, &alu);
1075 if (r)
1076 return r;
1077 /* b * LOG2(a) */
1078 memset(&alu, 0, sizeof(struct r600_bc_alu));
1079 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE;
1080 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1081 if (r)
1082 return r;
1083 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1084 alu.src[1].sel = ctx->temp_reg;
1085 alu.dst.sel = ctx->temp_reg;
1086 alu.dst.write = 1;
1087 alu.last = 1;
1088 r = r600_bc_add_alu(ctx->bc, &alu);
1089 if (r)
1090 return r;
1091 /* POW(a,b) = EXP2(b * LOG2(a))*/
1092 memset(&alu, 0, sizeof(struct r600_bc_alu));
1093 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1094 alu.src[0].sel = ctx->temp_reg;
1095 alu.dst.sel = ctx->temp_reg;
1096 alu.dst.write = 1;
1097 alu.last = 1;
1098 r = r600_bc_add_alu(ctx->bc, &alu);
1099 if (r)
1100 return r;
1101 return tgsi_helper_tempx_replicate(ctx);
1102 }
1103
1104 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1105 {
1106 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1107 struct r600_bc_alu alu;
1108 struct r600_bc_alu_src r600_src[3];
1109 int i, r;
1110
1111 r = tgsi_split_constant(ctx, r600_src);
1112 if (r)
1113 return r;
1114
1115 /* tmp = (src > 0 ? 1 : src) */
1116 for (i = 0; i < 4; i++) {
1117 memset(&alu, 0, sizeof(struct r600_bc_alu));
1118 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
1119 alu.is_op3 = 1;
1120 alu.dst.sel = ctx->temp_reg;
1121 alu.dst.write = 1;
1122
1123 alu.src[0] = r600_src[0];
1124 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1125
1126 alu.src[1].sel = V_SQ_ALU_SRC_1;
1127
1128 alu.src[2] = r600_src[0];
1129 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1130 if (i == 3)
1131 alu.last = 1;
1132 r = r600_bc_add_alu(ctx->bc, &alu);
1133 if (r)
1134 return r;
1135 }
1136
1137 /* dst = (-tmp > 0 ? -1 : tmp) */
1138 for (i = 0; i < 4; i++) {
1139 memset(&alu, 0, sizeof(struct r600_bc_alu));
1140 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
1141 alu.is_op3 = 1;
1142 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1143 if (r)
1144 return r;
1145
1146 alu.src[0].sel = ctx->temp_reg;
1147 alu.src[0].neg = 1;
1148
1149 alu.src[1].sel = V_SQ_ALU_SRC_1;
1150 alu.src[1].neg = 1;
1151
1152 alu.src[2].sel = ctx->temp_reg;
1153
1154 alu.dst.write = 1;
1155 if (i == 3)
1156 alu.last = 1;
1157 r = r600_bc_add_alu(ctx->bc, &alu);
1158 if (r)
1159 return r;
1160 }
1161 return 0;
1162 }
1163
1164 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1165 {
1166 struct r600_bc_alu alu;
1167 int i, r;
1168
1169 r = r600_bc_add_literal(ctx->bc, ctx->value);
1170 if (r)
1171 return r;
1172 for (i = 0; i < 4; i++) {
1173 memset(&alu, 0, sizeof(struct r600_bc_alu));
1174 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1175 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
1176 alu.dst.chan = i;
1177 } else {
1178 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1179 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1180 if (r)
1181 return r;
1182 alu.src[0].sel = ctx->temp_reg;
1183 alu.src[0].chan = i;
1184 }
1185 if (i == 3) {
1186 alu.last = 1;
1187 }
1188 r = r600_bc_add_alu(ctx->bc, &alu);
1189 if (r)
1190 return r;
1191 }
1192 return 0;
1193 }
1194
1195 static int tgsi_op3(struct r600_shader_ctx *ctx)
1196 {
1197 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1198 struct r600_bc_alu_src r600_src[3];
1199 struct r600_bc_alu alu;
1200 int i, j, r;
1201
1202 r = tgsi_split_constant(ctx, r600_src);
1203 if (r)
1204 return r;
1205 /* do it in 2 step as op3 doesn't support writemask */
1206 for (i = 0; i < 4; i++) {
1207 memset(&alu, 0, sizeof(struct r600_bc_alu));
1208 alu.inst = ctx->inst_info->r600_opcode;
1209 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1210 alu.src[j] = r600_src[j];
1211 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1212 }
1213 alu.dst.sel = ctx->temp_reg;
1214 alu.dst.chan = i;
1215 alu.dst.write = 1;
1216 alu.is_op3 = 1;
1217 if (i == 3) {
1218 alu.last = 1;
1219 }
1220 r = r600_bc_add_alu(ctx->bc, &alu);
1221 if (r)
1222 return r;
1223 }
1224 return tgsi_helper_copy(ctx, inst);
1225 }
1226
1227 static int tgsi_dp(struct r600_shader_ctx *ctx)
1228 {
1229 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1230 struct r600_bc_alu_src r600_src[3];
1231 struct r600_bc_alu alu;
1232 int i, j, r;
1233
1234 r = tgsi_split_constant(ctx, r600_src);
1235 if (r)
1236 return r;
1237 for (i = 0; i < 4; i++) {
1238 memset(&alu, 0, sizeof(struct r600_bc_alu));
1239 alu.inst = ctx->inst_info->r600_opcode;
1240 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1241 alu.src[j] = r600_src[j];
1242 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1243 }
1244 alu.dst.sel = ctx->temp_reg;
1245 alu.dst.chan = i;
1246 alu.dst.write = 1;
1247 /* handle some special cases */
1248 switch (ctx->inst_info->tgsi_opcode) {
1249 case TGSI_OPCODE_DP2:
1250 if (i > 1) {
1251 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1252 alu.src[0].chan = alu.src[1].chan = 0;
1253 }
1254 break;
1255 case TGSI_OPCODE_DP3:
1256 if (i > 2) {
1257 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1258 alu.src[0].chan = alu.src[1].chan = 0;
1259 }
1260 break;
1261 case TGSI_OPCODE_DPH:
1262 if (i == 3) {
1263 alu.src[0].sel = V_SQ_ALU_SRC_1;
1264 alu.src[0].chan = 0;
1265 alu.src[0].neg = 0;
1266 }
1267 break;
1268 default:
1269 break;
1270 }
1271 if (i == 3) {
1272 alu.last = 1;
1273 }
1274 r = r600_bc_add_alu(ctx->bc, &alu);
1275 if (r)
1276 return r;
1277 }
1278 return tgsi_helper_copy(ctx, inst);
1279 }
1280
1281 static int tgsi_tex(struct r600_shader_ctx *ctx)
1282 {
1283 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1284 struct r600_bc_tex tex;
1285 struct r600_bc_alu alu;
1286 unsigned src_gpr;
1287 int r, i;
1288
1289 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1290
1291 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1292 /* Add perspective divide */
1293 memset(&alu, 0, sizeof(struct r600_bc_alu));
1294 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
1295 alu.src[0].sel = src_gpr;
1296 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1297 alu.dst.sel = ctx->temp_reg;
1298 alu.dst.chan = 3;
1299 alu.last = 1;
1300 alu.dst.write = 1;
1301 r = r600_bc_add_alu(ctx->bc, &alu);
1302 if (r)
1303 return r;
1304
1305 for (i = 0; i < 3; i++) {
1306 memset(&alu, 0, sizeof(struct r600_bc_alu));
1307 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1308 alu.src[0].sel = ctx->temp_reg;
1309 alu.src[0].chan = 3;
1310 alu.src[1].sel = src_gpr;
1311 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1312 alu.dst.sel = ctx->temp_reg;
1313 alu.dst.chan = i;
1314 alu.dst.write = 1;
1315 r = r600_bc_add_alu(ctx->bc, &alu);
1316 if (r)
1317 return r;
1318 }
1319 memset(&alu, 0, sizeof(struct r600_bc_alu));
1320 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1321 alu.src[0].sel = V_SQ_ALU_SRC_1;
1322 alu.src[0].chan = 0;
1323 alu.dst.sel = ctx->temp_reg;
1324 alu.dst.chan = 3;
1325 alu.last = 1;
1326 alu.dst.write = 1;
1327 r = r600_bc_add_alu(ctx->bc, &alu);
1328 if (r)
1329 return r;
1330 src_gpr = ctx->temp_reg;
1331 } else if (inst->Src[0].Register.File != TGSI_FILE_TEMPORARY) {
1332 for (i = 0; i < 4; i++) {
1333 memset(&alu, 0, sizeof(struct r600_bc_alu));
1334 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1335 alu.src[0].sel = src_gpr;
1336 alu.src[0].chan = i;
1337 alu.dst.sel = ctx->temp_reg;
1338 alu.dst.chan = i;
1339 if (i == 3)
1340 alu.last = 1;
1341 alu.dst.write = 1;
1342 r = r600_bc_add_alu(ctx->bc, &alu);
1343 if (r)
1344 return r;
1345 }
1346 src_gpr = ctx->temp_reg;
1347 }
1348
1349 memset(&tex, 0, sizeof(struct r600_bc_tex));
1350 tex.inst = ctx->inst_info->r600_opcode;
1351 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1352 tex.sampler_id = tex.resource_id;
1353 tex.src_gpr = src_gpr;
1354 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1355 tex.dst_sel_x = 0;
1356 tex.dst_sel_y = 1;
1357 tex.dst_sel_z = 2;
1358 tex.dst_sel_w = 3;
1359 tex.src_sel_x = 0;
1360 tex.src_sel_y = 1;
1361 tex.src_sel_z = 2;
1362 tex.src_sel_w = 3;
1363
1364 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1365 tex.coord_type_x = 1;
1366 tex.coord_type_y = 1;
1367 tex.coord_type_z = 1;
1368 tex.coord_type_w = 1;
1369 }
1370 return r600_bc_add_tex(ctx->bc, &tex);
1371 }
1372
1373 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1374 {
1375 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1376 struct r600_bc_alu_src r600_src[3];
1377 struct r600_bc_alu alu;
1378 unsigned i;
1379 int r;
1380
1381 r = tgsi_split_constant(ctx, r600_src);
1382 if (r)
1383 return r;
1384 /* 1 - src0 */
1385 for (i = 0; i < 4; i++) {
1386 memset(&alu, 0, sizeof(struct r600_bc_alu));
1387 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD;
1388 alu.src[0].sel = V_SQ_ALU_SRC_1;
1389 alu.src[0].chan = 0;
1390 alu.src[1] = r600_src[0];
1391 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1392 alu.src[1].neg = 1;
1393 alu.dst.sel = ctx->temp_reg;
1394 alu.dst.chan = i;
1395 if (i == 3) {
1396 alu.last = 1;
1397 }
1398 alu.dst.write = 1;
1399 r = r600_bc_add_alu(ctx->bc, &alu);
1400 if (r)
1401 return r;
1402 }
1403 r = r600_bc_add_literal(ctx->bc, ctx->value);
1404 if (r)
1405 return r;
1406
1407 /* (1 - src0) * src2 */
1408 for (i = 0; i < 4; i++) {
1409 memset(&alu, 0, sizeof(struct r600_bc_alu));
1410 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1411 alu.src[0].sel = ctx->temp_reg;
1412 alu.src[0].chan = i;
1413 alu.src[1] = r600_src[2];
1414 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1415 alu.dst.sel = ctx->temp_reg;
1416 alu.dst.chan = i;
1417 if (i == 3) {
1418 alu.last = 1;
1419 }
1420 alu.dst.write = 1;
1421 r = r600_bc_add_alu(ctx->bc, &alu);
1422 if (r)
1423 return r;
1424 }
1425 r = r600_bc_add_literal(ctx->bc, ctx->value);
1426 if (r)
1427 return r;
1428
1429 /* src0 * src1 + (1 - src0) * src2 */
1430 for (i = 0; i < 4; i++) {
1431 memset(&alu, 0, sizeof(struct r600_bc_alu));
1432 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
1433 alu.is_op3 = 1;
1434 alu.src[0] = r600_src[0];
1435 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1436 alu.src[1] = r600_src[1];
1437 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1438 alu.src[2].sel = ctx->temp_reg;
1439 alu.src[2].chan = i;
1440 alu.dst.sel = ctx->temp_reg;
1441 alu.dst.chan = i;
1442 if (i == 3) {
1443 alu.last = 1;
1444 }
1445 r = r600_bc_add_alu(ctx->bc, &alu);
1446 if (r)
1447 return r;
1448 }
1449 return tgsi_helper_copy(ctx, inst);
1450 }
1451
1452 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1453 {
1454 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1455 struct r600_bc_alu_src r600_src[3];
1456 struct r600_bc_alu alu;
1457 int use_temp = 0;
1458 int i, r;
1459
1460 r = tgsi_split_constant(ctx, r600_src);
1461 if (r)
1462 return r;
1463
1464 if (inst->Dst[0].Register.WriteMask != 0xf)
1465 use_temp = 1;
1466
1467 for (i = 0; i < 4; i++) {
1468 memset(&alu, 0, sizeof(struct r600_bc_alu));
1469 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE;
1470 alu.src[0] = r600_src[0];
1471 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1472
1473 alu.src[1] = r600_src[2];
1474 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1475
1476 alu.src[2] = r600_src[1];
1477 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
1478
1479 if (use_temp)
1480 alu.dst.sel = ctx->temp_reg;
1481 else {
1482 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1483 if (r)
1484 return r;
1485 }
1486 alu.dst.chan = i;
1487 alu.dst.write = 1;
1488 alu.is_op3 = 1;
1489 if (i == 3)
1490 alu.last = 1;
1491 r = r600_bc_add_alu(ctx->bc, &alu);
1492 if (r)
1493 return r;
1494 }
1495 if (use_temp)
1496 return tgsi_helper_copy(ctx, inst);
1497 return 0;
1498 }
1499
1500 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1501 {
1502 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1503 struct r600_bc_alu_src r600_src[3];
1504 struct r600_bc_alu alu;
1505 uint32_t use_temp = 0;
1506 int i, r;
1507
1508 if (inst->Dst[0].Register.WriteMask != 0xf)
1509 use_temp = 1;
1510
1511 r = tgsi_split_constant(ctx, r600_src);
1512 if (r)
1513 return r;
1514
1515 for (i = 0; i < 4; i++) {
1516 memset(&alu, 0, sizeof(struct r600_bc_alu));
1517 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
1518
1519 alu.src[0] = r600_src[0];
1520 switch (i) {
1521 case 0:
1522 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1523 break;
1524 case 1:
1525 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1526 break;
1527 case 2:
1528 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1529 break;
1530 case 3:
1531 alu.src[0].sel = V_SQ_ALU_SRC_0;
1532 alu.src[0].chan = i;
1533 }
1534
1535 alu.src[1] = r600_src[1];
1536 switch (i) {
1537 case 0:
1538 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1539 break;
1540 case 1:
1541 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1542 break;
1543 case 2:
1544 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1545 break;
1546 case 3:
1547 alu.src[1].sel = V_SQ_ALU_SRC_0;
1548 alu.src[1].chan = i;
1549 }
1550
1551 alu.dst.sel = ctx->temp_reg;
1552 alu.dst.chan = i;
1553 alu.dst.write = 1;
1554
1555 if (i == 3)
1556 alu.last = 1;
1557 r = r600_bc_add_alu(ctx->bc, &alu);
1558 if (r)
1559 return r;
1560 }
1561
1562 for (i = 0; i < 4; i++) {
1563 memset(&alu, 0, sizeof(struct r600_bc_alu));
1564 alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
1565
1566 alu.src[0] = r600_src[0];
1567 switch (i) {
1568 case 0:
1569 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1570 break;
1571 case 1:
1572 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
1573 break;
1574 case 2:
1575 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1576 break;
1577 case 3:
1578 alu.src[0].sel = V_SQ_ALU_SRC_0;
1579 alu.src[0].chan = i;
1580 }
1581
1582 alu.src[1] = r600_src[1];
1583 switch (i) {
1584 case 0:
1585 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
1586 break;
1587 case 1:
1588 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
1589 break;
1590 case 2:
1591 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
1592 break;
1593 case 3:
1594 alu.src[1].sel = V_SQ_ALU_SRC_0;
1595 alu.src[1].chan = i;
1596 }
1597
1598 alu.src[2].sel = ctx->temp_reg;
1599 alu.src[2].neg = 1;
1600 alu.src[2].chan = i;
1601
1602 if (use_temp)
1603 alu.dst.sel = ctx->temp_reg;
1604 else {
1605 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1606 if (r)
1607 return r;
1608 }
1609 alu.dst.chan = i;
1610 alu.dst.write = 1;
1611 alu.is_op3 = 1;
1612 if (i == 3)
1613 alu.last = 1;
1614 r = r600_bc_add_alu(ctx->bc, &alu);
1615 if (r)
1616 return r;
1617 }
1618 if (use_temp)
1619 return tgsi_helper_copy(ctx, inst);
1620 return 0;
1621 }
1622
1623 static int tgsi_exp(struct r600_shader_ctx *ctx)
1624 {
1625 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1626 struct r600_bc_alu_src r600_src[3];
1627 struct r600_bc_alu alu;
1628 uint32_t use_temp = 0;
1629 int i, r;
1630
1631 /* result.x = 2^floor(src); */
1632 if (inst->Dst[0].Register.WriteMask & 1) {
1633 memset(&alu, 0, sizeof(struct r600_bc_alu));
1634
1635 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
1636 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1637 if (r)
1638 return r;
1639
1640 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1641
1642 alu.dst.sel = ctx->temp_reg;
1643 alu.dst.chan = 0;
1644 alu.dst.write = 1;
1645 alu.last = 1;
1646 r = r600_bc_add_alu(ctx->bc, &alu);
1647 if (r)
1648 return r;
1649
1650 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1651 alu.src[0].sel = ctx->temp_reg;
1652 alu.src[0].chan = 0;
1653
1654 alu.dst.sel = ctx->temp_reg;
1655 alu.dst.chan = 0;
1656 alu.dst.write = 1;
1657 alu.last = 1;
1658 r = r600_bc_add_alu(ctx->bc, &alu);
1659 if (r)
1660 return r;
1661 }
1662
1663 /* result.y = tmp - floor(tmp); */
1664 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
1665 memset(&alu, 0, sizeof(struct r600_bc_alu));
1666
1667 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
1668 alu.src[0] = r600_src[0];
1669 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1670 if (r)
1671 return r;
1672 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1673
1674 alu.dst.sel = ctx->temp_reg;
1675 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1676 // if (r)
1677 // return r;
1678 alu.dst.write = 1;
1679 alu.dst.chan = 1;
1680
1681 alu.last = 1;
1682
1683 r = r600_bc_add_alu(ctx->bc, &alu);
1684 if (r)
1685 return r;
1686 }
1687
1688 /* result.z = RoughApprox2ToX(tmp);*/
1689 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
1690 memset(&alu, 0, sizeof(struct r600_bc_alu));
1691 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
1692 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1693 if (r)
1694 return r;
1695 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1696
1697 alu.dst.sel = ctx->temp_reg;
1698 alu.dst.write = 1;
1699 alu.dst.chan = 2;
1700
1701 alu.last = 1;
1702
1703 r = r600_bc_add_alu(ctx->bc, &alu);
1704 if (r)
1705 return r;
1706
1707 }
1708
1709 /* result.w = 1.0;*/
1710 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
1711 memset(&alu, 0, sizeof(struct r600_bc_alu));
1712
1713 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
1714 alu.src[0].sel = V_SQ_ALU_SRC_1;
1715 alu.src[0].chan = 0;
1716
1717 alu.dst.sel = ctx->temp_reg;
1718 alu.dst.chan = 3;
1719 alu.dst.write = 1;
1720 alu.last = 1;
1721 r = r600_bc_add_alu(ctx->bc, &alu);
1722 if (r)
1723 return r;
1724 }
1725 return tgsi_helper_copy(ctx, inst);
1726 }
1727
1728 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
1729 {
1730 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1731 struct r600_bc_alu alu, *lalu;
1732 struct r600_bc_cf *last;
1733 int r;
1734
1735 memset(&alu, 0, sizeof(struct r600_bc_alu));
1736 alu.inst = opcode;
1737 alu.predicate = 1;
1738
1739 alu.dst.sel = ctx->temp_reg;
1740 alu.dst.write = 1;
1741 alu.dst.chan = 0;
1742
1743 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1744 if (r)
1745 return r;
1746 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1747 alu.src[1].sel = V_SQ_ALU_SRC_0;
1748 alu.src[1].chan = 0;
1749
1750 alu.last = 1;
1751
1752 r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE);
1753 if (r)
1754 return r;
1755
1756 return 0;
1757 }
1758
1759 static int pops(struct r600_shader_ctx *ctx, int pops)
1760 {
1761 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_POP);
1762 ctx->bc->cf_last->pop_count = pops;
1763 return 0;
1764 }
1765
1766 static int tgsi_if(struct r600_shader_ctx *ctx)
1767 {
1768 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1769
1770 emit_logic_pred(ctx, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE);
1771
1772 ctx->bc->fc_sp++;
1773 ctx->bc->fc_stack[ctx->bc->fc_sp].type = FC_IF;
1774 ctx->bc->fc_stack[ctx->bc->fc_sp].mid = NULL;
1775 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
1776
1777 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
1778 return 0;
1779 }
1780
1781 static int tgsi_else(struct r600_shader_ctx *ctx)
1782 {
1783 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1784 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_ELSE);
1785 ctx->bc->cf_last->pop_count = 1;
1786
1787 /* fixup mid */
1788 ctx->bc->fc_stack[ctx->bc->fc_sp].mid = ctx->bc->cf_last;
1789 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
1790 return 0;
1791 }
1792
1793 static int tgsi_endif(struct r600_shader_ctx *ctx)
1794 {
1795 pops(ctx, 1);
1796 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
1797 R600_ERR("if/endif unbalanced in shader\n");
1798 return -1;
1799 }
1800
1801 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
1802 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
1803 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
1804 } else {
1805 ctx->bc->fc_stack[ctx->bc->fc_sp].mid->cf_addr = ctx->bc->cf_last->id + 2;
1806 }
1807 ctx->bc->fc_sp--;
1808
1809 return 0;
1810 }
1811
1812 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
1813 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1814 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1815 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
1816 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
1817 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
1818 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
1819 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1820 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
1821 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1822 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1823 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1824 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1825 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
1826 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
1827 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
1828 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
1829 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
1830 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
1831 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
1832 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1833 /* gap */
1834 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1835 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1836 /* gap */
1837 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1838 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1839 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
1840 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1841 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
1842 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1843 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
1844 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
1845 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
1846 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
1847 /* gap */
1848 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1849 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
1850 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1851 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1852 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
1853 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
1854 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
1855 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* predicated kill */
1856 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1857 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1858 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1859 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1860 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1861 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
1862 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1863 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
1864 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
1865 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
1866 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
1867 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1868 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
1869 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1870 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
1871 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1872 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1873 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1874 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1875 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1876 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1877 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1878 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1879 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1880 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1881 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
1882 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
1883 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1884 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
1885 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1886 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1887 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
1888 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1889 {TGSI_OPCODE_BRK, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1890 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
1891 /* gap */
1892 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1893 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1894 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
1895 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
1896 /* gap */
1897 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1898 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1899 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1900 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1901 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1902 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1903 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1904 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
1905 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1906 /* gap */
1907 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1908 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1909 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1910 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1911 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1912 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1913 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1914 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1915 {TGSI_OPCODE_CONT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1916 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1917 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1918 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1919 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1920 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1921 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1922 /* gap */
1923 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1924 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1925 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1926 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1927 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1928 /* gap */
1929 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1930 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1931 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1932 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1933 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1934 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1935 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1936 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1937 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
1938 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
1939 /* gap */
1940 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1941 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1942 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1943 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1944 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1945 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1946 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1947 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1948 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1949 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1950 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1951 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1952 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1953 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1954 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1955 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1956 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1957 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1958 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1959 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1960 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1961 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1962 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1963 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1964 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1965 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1966 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1967 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
1968 };