2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
29 #include "sb/sb_public.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
43 Why CAYMAN got loops for lots of instructions is explained here.
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
63 /* Contents of r0 on entry to various shaders
69 GS - r0.xyw, r1.xyz = per-vertex offsets
75 .w = tess factor base.
77 TES - .x = TessCoord.x
79 - .z = RelPatchID (??)
82 PS - face_gpr.z = SampleMask
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
87 struct r600_pipe_shader
*pipeshader
,
88 union r600_shader_key key
);
90 static void r600_add_gpr_array(struct r600_shader
*ps
, int start_gpr
,
91 int size
, unsigned comp_mask
) {
96 if (ps
->num_arrays
== ps
->max_arrays
) {
98 ps
->arrays
= realloc(ps
->arrays
, ps
->max_arrays
*
99 sizeof(struct r600_shader_array
));
102 int n
= ps
->num_arrays
;
105 ps
->arrays
[n
].comp_mask
= comp_mask
;
106 ps
->arrays
[n
].gpr_start
= start_gpr
;
107 ps
->arrays
[n
].gpr_count
= size
;
110 static void r600_dump_streamout(struct pipe_stream_output_info
*so
)
114 fprintf(stderr
, "STREAMOUT\n");
115 for (i
= 0; i
< so
->num_outputs
; i
++) {
116 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
117 so
->output
[i
].start_component
;
118 fprintf(stderr
, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
120 so
->output
[i
].stream
,
121 so
->output
[i
].output_buffer
,
122 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
123 so
->output
[i
].register_index
,
128 so
->output
[i
].dst_offset
< so
->output
[i
].start_component
? " (will lower)" : "");
132 static int store_shader(struct pipe_context
*ctx
,
133 struct r600_pipe_shader
*shader
)
135 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
138 if (shader
->bo
== NULL
) {
139 shader
->bo
= (struct r600_resource
*)
140 pipe_buffer_create(ctx
->screen
, 0, PIPE_USAGE_IMMUTABLE
, shader
->shader
.bc
.ndw
* 4);
141 if (shader
->bo
== NULL
) {
144 ptr
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->bo
, PIPE_TRANSFER_WRITE
);
145 if (R600_BIG_ENDIAN
) {
146 for (i
= 0; i
< shader
->shader
.bc
.ndw
; ++i
) {
147 ptr
[i
] = util_cpu_to_le32(shader
->shader
.bc
.bytecode
[i
]);
150 memcpy(ptr
, shader
->shader
.bc
.bytecode
, shader
->shader
.bc
.ndw
* sizeof(*ptr
));
152 rctx
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
158 int r600_pipe_shader_create(struct pipe_context
*ctx
,
159 struct r600_pipe_shader
*shader
,
160 union r600_shader_key key
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
165 bool dump
= r600_can_dump_shader(&rctx
->screen
->b
,
166 tgsi_get_processor_type(sel
->tokens
));
167 unsigned use_sb
= !(rctx
->screen
->b
.debug_flags
& DBG_NO_SB
);
168 unsigned sb_disasm
= use_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
169 unsigned export_shader
;
171 shader
->shader
.bc
.isa
= rctx
->isa
;
174 fprintf(stderr
, "--------------------------------------------------------------\n");
175 tgsi_dump(sel
->tokens
, 0);
177 if (sel
->so
.num_outputs
) {
178 r600_dump_streamout(&sel
->so
);
181 r
= r600_shader_from_tgsi(rctx
, shader
, key
);
183 R600_ERR("translation from TGSI failed !\n");
186 if (shader
->shader
.processor_type
== PIPE_SHADER_VERTEX
) {
187 /* only disable for vertex shaders in tess paths */
191 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_CTRL
);
192 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_EVAL
);
194 /* disable SB for shaders using doubles */
195 use_sb
&= !shader
->shader
.uses_doubles
;
197 use_sb
&= !shader
->shader
.uses_atomics
;
199 /* Check if the bytecode has already been built. */
200 if (!shader
->shader
.bc
.bytecode
) {
201 r
= r600_bytecode_build(&shader
->shader
.bc
);
203 R600_ERR("building bytecode failed !\n");
208 if (dump
&& !sb_disasm
) {
209 fprintf(stderr
, "--------------------------------------------------------------\n");
210 r600_bytecode_disasm(&shader
->shader
.bc
);
211 fprintf(stderr
, "______________________________________________________________\n");
212 } else if ((dump
&& sb_disasm
) || use_sb
) {
213 r
= r600_sb_bytecode_process(rctx
, &shader
->shader
.bc
, &shader
->shader
,
216 R600_ERR("r600_sb_bytecode_process failed !\n");
221 if (shader
->gs_copy_shader
) {
224 r
= r600_sb_bytecode_process(rctx
, &shader
->gs_copy_shader
->shader
.bc
,
225 &shader
->gs_copy_shader
->shader
, dump
, 0);
230 if ((r
= store_shader(ctx
, shader
->gs_copy_shader
)))
234 /* Store the shader in a buffer. */
235 if ((r
= store_shader(ctx
, shader
)))
239 switch (shader
->shader
.processor_type
) {
240 case PIPE_SHADER_TESS_CTRL
:
241 evergreen_update_hs_state(ctx
, shader
);
243 case PIPE_SHADER_TESS_EVAL
:
245 evergreen_update_es_state(ctx
, shader
);
247 evergreen_update_vs_state(ctx
, shader
);
249 case PIPE_SHADER_GEOMETRY
:
250 if (rctx
->b
.chip_class
>= EVERGREEN
) {
251 evergreen_update_gs_state(ctx
, shader
);
252 evergreen_update_vs_state(ctx
, shader
->gs_copy_shader
);
254 r600_update_gs_state(ctx
, shader
);
255 r600_update_vs_state(ctx
, shader
->gs_copy_shader
);
258 case PIPE_SHADER_VERTEX
:
259 export_shader
= key
.vs
.as_es
;
260 if (rctx
->b
.chip_class
>= EVERGREEN
) {
262 evergreen_update_ls_state(ctx
, shader
);
263 else if (key
.vs
.as_es
)
264 evergreen_update_es_state(ctx
, shader
);
266 evergreen_update_vs_state(ctx
, shader
);
269 r600_update_es_state(ctx
, shader
);
271 r600_update_vs_state(ctx
, shader
);
274 case PIPE_SHADER_FRAGMENT
:
275 if (rctx
->b
.chip_class
>= EVERGREEN
) {
276 evergreen_update_ps_state(ctx
, shader
);
278 r600_update_ps_state(ctx
, shader
);
288 r600_pipe_shader_destroy(ctx
, shader
);
292 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
294 r600_resource_reference(&shader
->bo
, NULL
);
295 r600_bytecode_clear(&shader
->shader
.bc
);
296 r600_release_command_buffer(&shader
->command_buffer
);
300 * tgsi -> r600 shader
302 struct r600_shader_tgsi_instruction
;
304 struct r600_shader_src
{
311 boolean kc_rel
; /* true if cache bank is indexed */
320 struct r600_shader_ctx
{
321 struct tgsi_shader_info info
;
322 struct tgsi_parse_context parse
;
323 const struct tgsi_token
*tokens
;
325 unsigned file_offset
[TGSI_FILE_COUNT
];
327 const struct r600_shader_tgsi_instruction
*inst_info
;
328 struct r600_bytecode
*bc
;
329 struct r600_shader
*shader
;
330 struct r600_shader_src src
[4];
333 uint32_t max_driver_temp_used
;
334 /* needed for evergreen interpolation */
335 struct eg_interp eg_interpolators
[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
336 /* evergreen/cayman also store sample mask in face register */
338 /* sample id is .w component stored in fixed point position register */
339 int fixed_pt_position_gpr
;
341 boolean clip_vertex_write
;
343 unsigned edgeflag_output
;
346 int next_ring_offset
;
347 int gs_out_ring_offset
;
349 struct r600_shader
*gs_for_vs
;
350 int gs_export_gpr_tregs
[4];
351 int gs_rotated_input
[2];
352 const struct pipe_stream_output_info
*gs_stream_output_info
;
353 unsigned enabled_stream_buffers_mask
;
354 unsigned tess_input_info
; /* temp with tess input offsets */
355 unsigned tess_output_info
; /* temp with tess input offsets */
358 struct r600_shader_tgsi_instruction
{
360 int (*process
)(struct r600_shader_ctx
*ctx
);
363 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
);
364 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
365 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
366 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
);
367 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
368 static int tgsi_else(struct r600_shader_ctx
*ctx
);
369 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
370 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
371 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
372 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
373 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
374 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
375 unsigned int dst_reg
);
376 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
377 const struct r600_shader_src
*shader_src
,
379 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
382 static int tgsi_last_instruction(unsigned writemask
)
386 for (i
= 0; i
< 4; i
++) {
387 if (writemask
& (1 << i
)) {
394 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
396 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
399 if (i
->Instruction
.NumDstRegs
> 1 && i
->Instruction
.Opcode
!= TGSI_OPCODE_DFRACEXP
) {
400 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
404 if (i
->Instruction
.Label
) {
405 R600_ERR("label unsupported\n");
409 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
410 if (i
->Src
[j
].Register
.Dimension
) {
411 switch (i
->Src
[j
].Register
.File
) {
412 case TGSI_FILE_CONSTANT
:
413 case TGSI_FILE_HW_ATOMIC
:
415 case TGSI_FILE_INPUT
:
416 if (ctx
->type
== PIPE_SHADER_GEOMETRY
||
417 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
418 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
420 case TGSI_FILE_OUTPUT
:
421 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
424 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j
,
425 i
->Src
[j
].Register
.File
,
426 i
->Src
[j
].Register
.Dimension
);
431 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
432 if (i
->Dst
[j
].Register
.Dimension
) {
433 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
435 R600_ERR("unsupported dst (dimension)\n");
442 int eg_get_interpolator_index(unsigned interpolate
, unsigned location
)
444 if (interpolate
== TGSI_INTERPOLATE_COLOR
||
445 interpolate
== TGSI_INTERPOLATE_LINEAR
||
446 interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
448 int is_linear
= interpolate
== TGSI_INTERPOLATE_LINEAR
;
452 case TGSI_INTERPOLATE_LOC_CENTER
:
455 case TGSI_INTERPOLATE_LOC_CENTROID
:
458 case TGSI_INTERPOLATE_LOC_SAMPLE
:
463 return is_linear
* 3 + loc
;
469 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx
*ctx
,
472 int i
= eg_get_interpolator_index(
473 ctx
->shader
->input
[input
].interpolate
,
474 ctx
->shader
->input
[input
].interpolate_location
);
476 ctx
->shader
->input
[input
].ij_index
= ctx
->eg_interpolators
[i
].ij_index
;
479 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
482 struct r600_bytecode_alu alu
;
483 int gpr
= 0, base_chan
= 0;
484 int ij_index
= ctx
->shader
->input
[input
].ij_index
;
486 /* work out gpr and base_chan from index */
488 base_chan
= (2 * (ij_index
% 2)) + 1;
490 for (i
= 0; i
< 8; i
++) {
491 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
494 alu
.op
= ALU_OP2_INTERP_ZW
;
496 alu
.op
= ALU_OP2_INTERP_XY
;
498 if ((i
> 1) && (i
< 6)) {
499 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
503 alu
.dst
.chan
= i
% 4;
505 alu
.src
[0].sel
= gpr
;
506 alu
.src
[0].chan
= (base_chan
- (i
% 2));
508 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
510 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
513 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
520 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
523 struct r600_bytecode_alu alu
;
525 for (i
= 0; i
< 4; i
++) {
526 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
528 alu
.op
= ALU_OP1_INTERP_LOAD_P0
;
530 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
535 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
540 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
548 * Special export handling in shaders
550 * shader export ARRAY_BASE for EXPORT_POS:
553 * 62, 63 are clip distance vectors
555 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
556 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
557 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
558 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
559 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
560 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
561 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
562 * exclusive from render target index)
563 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
566 * shader export ARRAY_BASE for EXPORT_PIXEL:
568 * 61 computed Z vector
570 * The use of the values exported in the computed Z vector are controlled
571 * by DB_SHADER_CONTROL:
572 * Z_EXPORT_ENABLE - Z as a float in RED
573 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
574 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
575 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
576 * DB_SOURCE_FORMAT - export control restrictions
581 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
582 static int r600_spi_sid(struct r600_shader_io
* io
)
584 int index
, name
= io
->name
;
586 /* These params are handled differently, they don't need
587 * semantic indices, so we'll use 0 for them.
589 if (name
== TGSI_SEMANTIC_POSITION
||
590 name
== TGSI_SEMANTIC_PSIZE
||
591 name
== TGSI_SEMANTIC_EDGEFLAG
||
592 name
== TGSI_SEMANTIC_FACE
||
593 name
== TGSI_SEMANTIC_SAMPLEMASK
)
596 if (name
== TGSI_SEMANTIC_GENERIC
) {
597 /* For generic params simply use sid from tgsi */
600 /* For non-generic params - pack name and sid into 8 bits */
601 index
= 0x80 | (name
<<3) | (io
->sid
);
604 /* Make sure that all really used indices have nonzero value, so
605 * we can just compare it to 0 later instead of comparing the name
606 * with different values to detect special cases. */
613 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
614 int r600_get_lds_unique_index(unsigned semantic_name
, unsigned index
)
616 switch (semantic_name
) {
617 case TGSI_SEMANTIC_POSITION
:
619 case TGSI_SEMANTIC_PSIZE
:
621 case TGSI_SEMANTIC_CLIPDIST
:
624 case TGSI_SEMANTIC_GENERIC
:
626 return 4 + index
- 9;
628 /* same explanation as in the default statement,
629 * the only user hitting this is st/nine.
633 /* patch indices are completely separate and thus start from 0 */
634 case TGSI_SEMANTIC_TESSOUTER
:
636 case TGSI_SEMANTIC_TESSINNER
:
638 case TGSI_SEMANTIC_PATCH
:
642 /* Don't fail here. The result of this function is only used
643 * for LS, TCS, TES, and GS, where legacy GL semantics can't
644 * occur, but this function is called for all vertex shaders
645 * before it's known whether LS will be compiled or not.
651 /* turn input into interpolate on EG */
652 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
656 if (ctx
->shader
->input
[index
].spi_sid
) {
657 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
658 if (ctx
->shader
->input
[index
].interpolate
> 0) {
659 evergreen_interp_assign_ij_index(ctx
, index
);
660 r
= evergreen_interp_alu(ctx
, index
);
662 r
= evergreen_interp_flat(ctx
, index
);
668 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
670 struct r600_bytecode_alu alu
;
672 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
673 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
675 for (i
= 0; i
< 4; i
++) {
676 memset(&alu
, 0, sizeof(alu
));
677 alu
.op
= ALU_OP3_CNDGT
;
680 alu
.dst
.sel
= gpr_front
;
681 alu
.src
[0].sel
= ctx
->face_gpr
;
682 alu
.src
[1].sel
= gpr_front
;
683 alu
.src
[2].sel
= gpr_back
;
690 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
697 /* execute a single slot ALU calculation */
698 static int single_alu_op2(struct r600_shader_ctx
*ctx
, int op
,
699 int dst_sel
, int dst_chan
,
700 int src0_sel
, unsigned src0_chan_val
,
701 int src1_sel
, unsigned src1_chan_val
)
703 struct r600_bytecode_alu alu
;
706 if (ctx
->bc
->chip_class
== CAYMAN
&& op
== ALU_OP2_MULLO_INT
) {
707 for (i
= 0; i
< 4; i
++) {
708 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
710 alu
.src
[0].sel
= src0_sel
;
711 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
712 alu
.src
[0].value
= src0_chan_val
;
714 alu
.src
[0].chan
= src0_chan_val
;
715 alu
.src
[1].sel
= src1_sel
;
716 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
717 alu
.src
[1].value
= src1_chan_val
;
719 alu
.src
[1].chan
= src1_chan_val
;
720 alu
.dst
.sel
= dst_sel
;
722 alu
.dst
.write
= i
== dst_chan
;
724 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
731 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
733 alu
.src
[0].sel
= src0_sel
;
734 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
735 alu
.src
[0].value
= src0_chan_val
;
737 alu
.src
[0].chan
= src0_chan_val
;
738 alu
.src
[1].sel
= src1_sel
;
739 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
740 alu
.src
[1].value
= src1_chan_val
;
742 alu
.src
[1].chan
= src1_chan_val
;
743 alu
.dst
.sel
= dst_sel
;
744 alu
.dst
.chan
= dst_chan
;
747 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
753 /* execute a single slot ALU calculation */
754 static int single_alu_op3(struct r600_shader_ctx
*ctx
, int op
,
755 int dst_sel
, int dst_chan
,
756 int src0_sel
, unsigned src0_chan_val
,
757 int src1_sel
, unsigned src1_chan_val
,
758 int src2_sel
, unsigned src2_chan_val
)
760 struct r600_bytecode_alu alu
;
763 /* validate this for other ops */
764 assert(op
== ALU_OP3_MULADD_UINT24
|| op
== ALU_OP3_CNDE_INT
);
765 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
767 alu
.src
[0].sel
= src0_sel
;
768 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
769 alu
.src
[0].value
= src0_chan_val
;
771 alu
.src
[0].chan
= src0_chan_val
;
772 alu
.src
[1].sel
= src1_sel
;
773 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
774 alu
.src
[1].value
= src1_chan_val
;
776 alu
.src
[1].chan
= src1_chan_val
;
777 alu
.src
[2].sel
= src2_sel
;
778 if (src2_sel
== V_SQ_ALU_SRC_LITERAL
)
779 alu
.src
[2].value
= src2_chan_val
;
781 alu
.src
[2].chan
= src2_chan_val
;
782 alu
.dst
.sel
= dst_sel
;
783 alu
.dst
.chan
= dst_chan
;
786 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
792 /* put it in temp_reg.x */
793 static int get_lds_offset0(struct r600_shader_ctx
*ctx
,
795 int temp_reg
, bool is_patch_var
)
799 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
801 Dimension - patch0_offset (input_vals.z),
802 Non-dim - patch0_data_offset (input_vals.w)
804 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
806 ctx
->tess_output_info
, 0,
808 ctx
->tess_output_info
, is_patch_var
? 3 : 2);
814 static inline int get_address_file_reg(struct r600_shader_ctx
*ctx
, int index
)
816 return index
> 0 ? ctx
->bc
->index_reg
[index
- 1] : ctx
->bc
->ar_reg
;
819 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
821 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
824 static int vs_add_primid_output(struct r600_shader_ctx
*ctx
, int prim_id_sid
)
827 i
= ctx
->shader
->noutput
++;
828 ctx
->shader
->output
[i
].name
= TGSI_SEMANTIC_PRIMID
;
829 ctx
->shader
->output
[i
].sid
= 0;
830 ctx
->shader
->output
[i
].gpr
= 0;
831 ctx
->shader
->output
[i
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
832 ctx
->shader
->output
[i
].write_mask
= 0x4;
833 ctx
->shader
->output
[i
].spi_sid
= prim_id_sid
;
838 static int tgsi_barrier(struct r600_shader_ctx
*ctx
)
840 struct r600_bytecode_alu alu
;
843 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
844 alu
.op
= ctx
->inst_info
->op
;
847 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
853 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
855 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
856 int r
, i
, j
, count
= d
->Range
.Last
- d
->Range
.First
+ 1;
858 switch (d
->Declaration
.File
) {
859 case TGSI_FILE_INPUT
:
860 for (j
= 0; j
< count
; j
++) {
861 i
= ctx
->shader
->ninput
+ j
;
862 assert(i
< ARRAY_SIZE(ctx
->shader
->input
));
863 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
864 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
+ j
;
865 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
866 ctx
->shader
->input
[i
].interpolate_location
= d
->Interp
.Location
;
867 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
+ j
;
868 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
869 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
870 switch (ctx
->shader
->input
[i
].name
) {
871 case TGSI_SEMANTIC_FACE
:
872 if (ctx
->face_gpr
!= -1)
873 ctx
->shader
->input
[i
].gpr
= ctx
->face_gpr
; /* already allocated by allocate_system_value_inputs */
875 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
877 case TGSI_SEMANTIC_COLOR
:
880 case TGSI_SEMANTIC_POSITION
:
881 ctx
->fragcoord_input
= i
;
883 case TGSI_SEMANTIC_PRIMID
:
884 /* set this for now */
885 ctx
->shader
->gs_prim_id_input
= true;
886 ctx
->shader
->ps_prim_id_input
= i
;
889 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
890 if ((r
= evergreen_interp_input(ctx
, i
)))
893 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
894 /* FIXME probably skip inputs if they aren't passed in the ring */
895 ctx
->shader
->input
[i
].ring_offset
= ctx
->next_ring_offset
;
896 ctx
->next_ring_offset
+= 16;
897 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_PRIMID
)
898 ctx
->shader
->gs_prim_id_input
= true;
901 ctx
->shader
->ninput
+= count
;
903 case TGSI_FILE_OUTPUT
:
904 for (j
= 0; j
< count
; j
++) {
905 i
= ctx
->shader
->noutput
+ j
;
906 assert(i
< ARRAY_SIZE(ctx
->shader
->output
));
907 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
908 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
+ j
;
909 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
+ j
;
910 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
911 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
912 if (ctx
->type
== PIPE_SHADER_VERTEX
||
913 ctx
->type
== PIPE_SHADER_GEOMETRY
||
914 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
915 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
916 switch (d
->Semantic
.Name
) {
917 case TGSI_SEMANTIC_CLIPDIST
:
918 ctx
->shader
->clip_dist_write
|= d
->Declaration
.UsageMask
<<
919 ((d
->Semantic
.Index
+ j
) << 2);
921 case TGSI_SEMANTIC_PSIZE
:
922 ctx
->shader
->vs_out_misc_write
= 1;
923 ctx
->shader
->vs_out_point_size
= 1;
925 case TGSI_SEMANTIC_EDGEFLAG
:
926 ctx
->shader
->vs_out_misc_write
= 1;
927 ctx
->shader
->vs_out_edgeflag
= 1;
928 ctx
->edgeflag_output
= i
;
930 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
931 ctx
->shader
->vs_out_misc_write
= 1;
932 ctx
->shader
->vs_out_viewport
= 1;
934 case TGSI_SEMANTIC_LAYER
:
935 ctx
->shader
->vs_out_misc_write
= 1;
936 ctx
->shader
->vs_out_layer
= 1;
938 case TGSI_SEMANTIC_CLIPVERTEX
:
939 ctx
->clip_vertex_write
= TRUE
;
943 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
944 ctx
->gs_out_ring_offset
+= 16;
946 } else if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
947 switch (d
->Semantic
.Name
) {
948 case TGSI_SEMANTIC_COLOR
:
949 ctx
->shader
->nr_ps_max_color_exports
++;
954 ctx
->shader
->noutput
+= count
;
956 case TGSI_FILE_TEMPORARY
:
957 if (ctx
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) {
958 if (d
->Array
.ArrayID
) {
959 r600_add_gpr_array(ctx
->shader
,
960 ctx
->file_offset
[TGSI_FILE_TEMPORARY
] +
962 d
->Range
.Last
- d
->Range
.First
+ 1, 0x0F);
967 case TGSI_FILE_CONSTANT
:
968 case TGSI_FILE_SAMPLER
:
969 case TGSI_FILE_SAMPLER_VIEW
:
970 case TGSI_FILE_ADDRESS
:
973 case TGSI_FILE_HW_ATOMIC
:
974 i
= ctx
->shader
->nhwatomic_ranges
;
975 ctx
->shader
->atomics
[i
].start
= d
->Range
.First
;
976 ctx
->shader
->atomics
[i
].end
= d
->Range
.Last
;
977 ctx
->shader
->atomics
[i
].hw_idx
= ctx
->shader
->atomic_base
+ ctx
->shader
->nhwatomic
;
978 ctx
->shader
->atomics
[i
].array_id
= d
->Array
.ArrayID
;
979 ctx
->shader
->atomics
[i
].buffer_id
= d
->Dim
.Index2D
;
980 ctx
->shader
->nhwatomic_ranges
++;
981 ctx
->shader
->nhwatomic
+= count
;
984 case TGSI_FILE_SYSTEM_VALUE
:
985 if (d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEMASK
||
986 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEID
||
987 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEPOS
) {
988 break; /* Already handled from allocate_system_value_inputs */
989 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
990 if (!ctx
->native_integers
) {
991 struct r600_bytecode_alu alu
;
992 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
994 alu
.op
= ALU_OP1_INT_TO_FLT
;
1003 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1007 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
1009 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INVOCATIONID
)
1011 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
||
1012 d
->Semantic
.Name
== TGSI_SEMANTIC_TESSOUTER
) {
1013 int param
= r600_get_lds_unique_index(d
->Semantic
.Name
, 0);
1014 int dreg
= d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
? 3 : 2;
1015 unsigned temp_reg
= r600_get_temp(ctx
);
1017 r
= get_lds_offset0(ctx
, 2, temp_reg
, true);
1021 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1024 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1028 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
1030 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSCOORD
) {
1034 for (i
= 0; i
< 2; i
++) {
1035 struct r600_bytecode_alu alu
;
1036 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1037 alu
.op
= ALU_OP1_MOV
;
1039 alu
.src
[0].chan
= 0 + i
;
1041 alu
.dst
.chan
= 0 + i
;
1043 alu
.last
= (i
== 1) ? 1 : 0;
1044 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1047 /* ADD r1.z, 1.0f, -r0.x */
1048 struct r600_bytecode_alu alu
;
1049 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1050 alu
.op
= ALU_OP2_ADD
;
1051 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1053 alu
.src
[1].chan
= 0;
1059 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1062 /* ADD r1.z, r1.z, -r1.y */
1063 alu
.op
= ALU_OP2_ADD
;
1065 alu
.src
[0].chan
= 2;
1067 alu
.src
[1].chan
= 1;
1073 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1079 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
1085 static int allocate_system_value_inputs(struct r600_shader_ctx
*ctx
, int gpr_offset
)
1087 struct tgsi_parse_context parse
;
1091 unsigned name
, alternate_name
;
1093 { false, &ctx
->face_gpr
, TGSI_SEMANTIC_SAMPLEMASK
, ~0u }, /* lives in Front Face GPR.z */
1095 { false, &ctx
->fixed_pt_position_gpr
, TGSI_SEMANTIC_SAMPLEID
, TGSI_SEMANTIC_SAMPLEPOS
} /* SAMPLEID is in Fixed Point Position GPR.w */
1097 int i
, k
, num_regs
= 0;
1099 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1103 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1104 while (!tgsi_parse_end_of_tokens(&parse
)) {
1105 tgsi_parse_token(&parse
);
1107 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1108 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1109 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1110 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1111 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1113 int interpolate
, location
, k
;
1115 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1116 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1117 inputs
[1].enabled
= true; /* needs SAMPLEID */
1118 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1119 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1120 /* Needs sample positions, currently those are always available */
1122 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1125 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1126 k
= eg_get_interpolator_index(interpolate
, location
);
1128 ctx
->eg_interpolators
[k
].enabled
= true;
1130 } else if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
1131 struct tgsi_full_declaration
*d
= &parse
.FullToken
.FullDeclaration
;
1132 if (d
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1133 for (k
= 0; k
< ARRAY_SIZE(inputs
); k
++) {
1134 if (d
->Semantic
.Name
== inputs
[k
].name
||
1135 d
->Semantic
.Name
== inputs
[k
].alternate_name
) {
1136 inputs
[k
].enabled
= true;
1143 tgsi_parse_free(&parse
);
1145 for (i
= 0; i
< ARRAY_SIZE(inputs
); i
++) {
1146 boolean enabled
= inputs
[i
].enabled
;
1147 int *reg
= inputs
[i
].reg
;
1148 unsigned name
= inputs
[i
].name
;
1151 int gpr
= gpr_offset
+ num_regs
++;
1152 ctx
->shader
->nsys_inputs
++;
1154 // add to inputs, allocate a gpr
1155 k
= ctx
->shader
->ninput
++;
1156 ctx
->shader
->input
[k
].name
= name
;
1157 ctx
->shader
->input
[k
].sid
= 0;
1158 ctx
->shader
->input
[k
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1159 ctx
->shader
->input
[k
].interpolate_location
= TGSI_INTERPOLATE_LOC_CENTER
;
1160 *reg
= ctx
->shader
->input
[k
].gpr
= gpr
;
1164 return gpr_offset
+ num_regs
;
1168 * for evergreen we need to scan the shader to find the number of GPRs we need to
1169 * reserve for interpolation and system values
1171 * we need to know if we are going to emit
1172 * any sample or centroid inputs
1173 * if perspective and linear are required
1175 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
1179 struct tgsi_parse_context parse
;
1181 memset(&ctx
->eg_interpolators
, 0, sizeof(ctx
->eg_interpolators
));
1183 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
1185 /* skip position/face/mask/sampleid */
1186 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
1187 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
||
1188 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEMASK
||
1189 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEID
)
1192 k
= eg_get_interpolator_index(
1193 ctx
->info
.input_interpolate
[i
],
1194 ctx
->info
.input_interpolate_loc
[i
]);
1196 ctx
->eg_interpolators
[k
].enabled
= TRUE
;
1199 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1203 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1204 while (!tgsi_parse_end_of_tokens(&parse
)) {
1205 tgsi_parse_token(&parse
);
1207 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1208 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1209 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1210 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1211 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1213 int interpolate
, location
, k
;
1215 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1216 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1217 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1218 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1220 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1223 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1224 k
= eg_get_interpolator_index(interpolate
, location
);
1226 ctx
->eg_interpolators
[k
].enabled
= true;
1231 tgsi_parse_free(&parse
);
1233 /* assign gpr to each interpolator according to priority */
1235 for (i
= 0; i
< ARRAY_SIZE(ctx
->eg_interpolators
); i
++) {
1236 if (ctx
->eg_interpolators
[i
].enabled
) {
1237 ctx
->eg_interpolators
[i
].ij_index
= num_baryc
;
1242 /* XXX PULL MODEL and LINE STIPPLE */
1244 num_baryc
= (num_baryc
+ 1) >> 1;
1245 return allocate_system_value_inputs(ctx
, num_baryc
);
1248 /* sample_id_sel == NULL means fetch for current sample */
1249 static int load_sample_position(struct r600_shader_ctx
*ctx
, struct r600_shader_src
*sample_id
, int chan_sel
)
1251 struct r600_bytecode_vtx vtx
;
1254 assert(ctx
->fixed_pt_position_gpr
!= -1);
1256 t1
= r600_get_temp(ctx
);
1258 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
1259 vtx
.op
= FETCH_OP_VFETCH
;
1260 vtx
.buffer_id
= R600_BUFFER_INFO_CONST_BUFFER
;
1261 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1262 if (sample_id
== NULL
) {
1263 vtx
.src_gpr
= ctx
->fixed_pt_position_gpr
; // SAMPLEID is in .w;
1267 struct r600_bytecode_alu alu
;
1269 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1270 alu
.op
= ALU_OP1_MOV
;
1271 r600_bytecode_src(&alu
.src
[0], sample_id
, chan_sel
);
1275 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1282 vtx
.mega_fetch_count
= 16;
1288 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1289 vtx
.num_format_all
= 2;
1290 vtx
.format_comp_all
= 1;
1291 vtx
.use_const_fields
= 0;
1292 vtx
.offset
= 1; // first element is size of buffer
1293 vtx
.endian
= r600_endian_swap(32);
1294 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1296 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
1303 static void tgsi_src(struct r600_shader_ctx
*ctx
,
1304 const struct tgsi_full_src_register
*tgsi_src
,
1305 struct r600_shader_src
*r600_src
)
1307 memset(r600_src
, 0, sizeof(*r600_src
));
1308 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
1309 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
1310 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
1311 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
1312 r600_src
->neg
= tgsi_src
->Register
.Negate
;
1313 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
1315 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
1317 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
1318 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
1319 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
1321 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
1322 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
, r600_src
->abs
);
1323 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
1326 index
= tgsi_src
->Register
.Index
;
1327 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
1328 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
1329 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1330 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEMASK
) {
1331 r600_src
->swizzle
[0] = 2; // Z value
1332 r600_src
->swizzle
[1] = 2;
1333 r600_src
->swizzle
[2] = 2;
1334 r600_src
->swizzle
[3] = 2;
1335 r600_src
->sel
= ctx
->face_gpr
;
1336 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEID
) {
1337 r600_src
->swizzle
[0] = 3; // W value
1338 r600_src
->swizzle
[1] = 3;
1339 r600_src
->swizzle
[2] = 3;
1340 r600_src
->swizzle
[3] = 3;
1341 r600_src
->sel
= ctx
->fixed_pt_position_gpr
;
1342 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEPOS
) {
1343 r600_src
->swizzle
[0] = 0;
1344 r600_src
->swizzle
[1] = 1;
1345 r600_src
->swizzle
[2] = 4;
1346 r600_src
->swizzle
[3] = 4;
1347 r600_src
->sel
= load_sample_position(ctx
, NULL
, -1);
1348 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
1349 r600_src
->swizzle
[0] = 3;
1350 r600_src
->swizzle
[1] = 3;
1351 r600_src
->swizzle
[2] = 3;
1352 r600_src
->swizzle
[3] = 3;
1354 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
1355 r600_src
->swizzle
[0] = 0;
1356 r600_src
->swizzle
[1] = 0;
1357 r600_src
->swizzle
[2] = 0;
1358 r600_src
->swizzle
[3] = 0;
1360 } else if (ctx
->type
!= PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1361 r600_src
->swizzle
[0] = 3;
1362 r600_src
->swizzle
[1] = 3;
1363 r600_src
->swizzle
[2] = 3;
1364 r600_src
->swizzle
[3] = 3;
1366 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1367 r600_src
->swizzle
[0] = 2;
1368 r600_src
->swizzle
[1] = 2;
1369 r600_src
->swizzle
[2] = 2;
1370 r600_src
->swizzle
[3] = 2;
1372 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSCOORD
) {
1374 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSINNER
) {
1376 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSOUTER
) {
1378 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTICESIN
) {
1379 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
1380 r600_src
->sel
= ctx
->tess_input_info
;
1381 r600_src
->swizzle
[0] = 2;
1382 r600_src
->swizzle
[1] = 2;
1383 r600_src
->swizzle
[2] = 2;
1384 r600_src
->swizzle
[3] = 2;
1386 r600_src
->sel
= ctx
->tess_input_info
;
1387 r600_src
->swizzle
[0] = 3;
1388 r600_src
->swizzle
[1] = 3;
1389 r600_src
->swizzle
[2] = 3;
1390 r600_src
->swizzle
[3] = 3;
1392 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1394 r600_src
->swizzle
[0] = 0;
1395 r600_src
->swizzle
[1] = 0;
1396 r600_src
->swizzle
[2] = 0;
1397 r600_src
->swizzle
[3] = 0;
1398 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1400 r600_src
->swizzle
[0] = 3;
1401 r600_src
->swizzle
[1] = 3;
1402 r600_src
->swizzle
[2] = 3;
1403 r600_src
->swizzle
[3] = 3;
1406 if (tgsi_src
->Register
.Indirect
)
1407 r600_src
->rel
= V_SQ_REL_RELATIVE
;
1408 r600_src
->sel
= tgsi_src
->Register
.Index
;
1409 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
1411 if (tgsi_src
->Register
.File
== TGSI_FILE_CONSTANT
) {
1412 if (tgsi_src
->Register
.Dimension
) {
1413 r600_src
->kc_bank
= tgsi_src
->Dimension
.Index
;
1414 if (tgsi_src
->Dimension
.Indirect
) {
1415 r600_src
->kc_rel
= 1;
1421 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
1422 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
1423 unsigned int dst_reg
)
1425 struct r600_bytecode_vtx vtx
;
1426 unsigned int ar_reg
;
1430 struct r600_bytecode_alu alu
;
1432 memset(&alu
, 0, sizeof(alu
));
1434 alu
.op
= ALU_OP2_ADD_INT
;
1435 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
1436 alu
.src
[0].chan
= ar_chan
;
1438 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1439 alu
.src
[1].value
= offset
;
1441 alu
.dst
.sel
= dst_reg
;
1442 alu
.dst
.chan
= ar_chan
;
1446 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1451 ar_reg
= ctx
->bc
->ar_reg
;
1454 memset(&vtx
, 0, sizeof(vtx
));
1455 vtx
.buffer_id
= cb_idx
;
1456 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1457 vtx
.src_gpr
= ar_reg
;
1458 vtx
.src_sel_x
= ar_chan
;
1459 vtx
.mega_fetch_count
= 16;
1460 vtx
.dst_gpr
= dst_reg
;
1461 vtx
.dst_sel_x
= 0; /* SEL_X */
1462 vtx
.dst_sel_y
= 1; /* SEL_Y */
1463 vtx
.dst_sel_z
= 2; /* SEL_Z */
1464 vtx
.dst_sel_w
= 3; /* SEL_W */
1465 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1466 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1467 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1468 vtx
.endian
= r600_endian_swap(32);
1469 vtx
.buffer_index_mode
= cb_rel
; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1471 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1477 static int fetch_gs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1479 struct r600_bytecode_vtx vtx
;
1481 unsigned index
= src
->Register
.Index
;
1482 unsigned vtx_id
= src
->Dimension
.Index
;
1483 int offset_reg
= ctx
->gs_rotated_input
[vtx_id
/ 3];
1484 int offset_chan
= vtx_id
% 3;
1487 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1488 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1490 if (offset_reg
== ctx
->gs_rotated_input
[0] && offset_chan
== 2)
1493 if (src
->Dimension
.Indirect
|| src
->Register
.Indirect
)
1494 t2
= r600_get_temp(ctx
);
1496 if (src
->Dimension
.Indirect
) {
1498 struct r600_bytecode_alu alu
;
1501 addr_reg
= get_address_file_reg(ctx
, src
->DimIndirect
.Index
);
1502 if (src
->DimIndirect
.Index
> 0) {
1503 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
1511 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1512 at least this is what fglrx seems to do. */
1513 for (i
= 0; i
< 3; i
++) {
1514 treg
[i
] = r600_get_temp(ctx
);
1516 r600_add_gpr_array(ctx
->shader
, treg
[0], 3, 0x0F);
1518 for (i
= 0; i
< 3; i
++) {
1519 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1520 alu
.op
= ALU_OP1_MOV
;
1521 alu
.src
[0].sel
= ctx
->gs_rotated_input
[0];
1522 alu
.src
[0].chan
= i
== 2 ? 3 : i
;
1523 alu
.dst
.sel
= treg
[i
];
1527 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1531 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1532 alu
.op
= ALU_OP1_MOV
;
1533 alu
.src
[0].sel
= treg
[0];
1538 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1545 if (src
->Register
.Indirect
) {
1547 unsigned first
= ctx
->info
.input_array_first
[src
->Indirect
.ArrayID
];
1549 addr_reg
= get_address_file_reg(ctx
, src
->Indirect
.Index
);
1551 /* pull the value from index_reg */
1552 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1555 V_SQ_ALU_SRC_LITERAL
, first
);
1558 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1561 V_SQ_ALU_SRC_LITERAL
, 4,
1562 offset_reg
, offset_chan
);
1567 index
= src
->Register
.Index
- first
;
1570 memset(&vtx
, 0, sizeof(vtx
));
1571 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1572 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1573 vtx
.src_gpr
= offset_reg
;
1574 vtx
.src_sel_x
= offset_chan
;
1575 vtx
.offset
= index
* 16; /*bytes*/
1576 vtx
.mega_fetch_count
= 16;
1577 vtx
.dst_gpr
= dst_reg
;
1578 vtx
.dst_sel_x
= 0; /* SEL_X */
1579 vtx
.dst_sel_y
= 1; /* SEL_Y */
1580 vtx
.dst_sel_z
= 2; /* SEL_Z */
1581 vtx
.dst_sel_w
= 3; /* SEL_W */
1582 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1583 vtx
.use_const_fields
= 1;
1585 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1588 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1594 static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx
)
1596 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1599 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1600 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1602 if (src
->Register
.File
== TGSI_FILE_INPUT
) {
1603 if (ctx
->shader
->input
[src
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
1604 /* primitive id is in R0.z */
1605 ctx
->src
[i
].sel
= 0;
1606 ctx
->src
[i
].swizzle
[0] = 2;
1609 if (src
->Register
.File
== TGSI_FILE_INPUT
&& src
->Register
.Dimension
) {
1610 int treg
= r600_get_temp(ctx
);
1612 fetch_gs_input(ctx
, src
, treg
);
1613 ctx
->src
[i
].sel
= treg
;
1614 ctx
->src
[i
].rel
= 0;
1621 /* Tessellation shaders pass outputs to the next shader using LDS.
1623 * LS outputs = TCS(HS) inputs
1624 * TCS(HS) outputs = TES(DS) inputs
1626 * The LDS layout is:
1627 * - TCS inputs for patch 0
1628 * - TCS inputs for patch 1
1629 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1631 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1632 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1633 * - TCS outputs for patch 1
1634 * - Per-patch TCS outputs for patch 1
1635 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1636 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1639 * All three shaders VS(LS), TCS, TES share the same LDS space.
1641 /* this will return with the dw address in temp_reg.x */
1642 static int r600_get_byte_address(struct r600_shader_ctx
*ctx
, int temp_reg
,
1643 const struct tgsi_full_dst_register
*dst
,
1644 const struct tgsi_full_src_register
*src
,
1645 int stride_bytes_reg
, int stride_bytes_chan
)
1647 struct tgsi_full_dst_register reg
;
1648 ubyte
*name
, *index
, *array_first
;
1651 struct tgsi_shader_info
*info
= &ctx
->info
;
1652 /* Set the register description. The address computation is the same
1653 * for sources and destinations. */
1655 reg
.Register
.File
= src
->Register
.File
;
1656 reg
.Register
.Index
= src
->Register
.Index
;
1657 reg
.Register
.Indirect
= src
->Register
.Indirect
;
1658 reg
.Register
.Dimension
= src
->Register
.Dimension
;
1659 reg
.Indirect
= src
->Indirect
;
1660 reg
.Dimension
= src
->Dimension
;
1661 reg
.DimIndirect
= src
->DimIndirect
;
1665 /* If the register is 2-dimensional (e.g. an array of vertices
1666 * in a primitive), calculate the base address of the vertex. */
1667 if (reg
.Register
.Dimension
) {
1669 if (reg
.Dimension
.Indirect
) {
1671 assert (reg
.DimIndirect
.File
== TGSI_FILE_ADDRESS
);
1673 addr_reg
= get_address_file_reg(ctx
, reg
.DimIndirect
.Index
);
1674 /* pull the value from index_reg */
1678 sel
= V_SQ_ALU_SRC_LITERAL
;
1679 chan
= reg
.Dimension
.Index
;
1682 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1684 stride_bytes_reg
, stride_bytes_chan
,
1691 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1692 name
= info
->input_semantic_name
;
1693 index
= info
->input_semantic_index
;
1694 array_first
= info
->input_array_first
;
1695 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1696 name
= info
->output_semantic_name
;
1697 index
= info
->output_semantic_index
;
1698 array_first
= info
->output_array_first
;
1703 if (reg
.Register
.Indirect
) {
1706 /* Add the relative address of the element. */
1707 if (reg
.Indirect
.ArrayID
)
1708 first
= array_first
[reg
.Indirect
.ArrayID
];
1710 first
= reg
.Register
.Index
;
1712 addr_reg
= get_address_file_reg(ctx
, reg
.Indirect
.Index
);
1714 /* pull the value from index_reg */
1715 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1717 V_SQ_ALU_SRC_LITERAL
, 16,
1723 param
= r600_get_lds_unique_index(name
[first
],
1727 param
= r600_get_lds_unique_index(name
[reg
.Register
.Index
],
1728 index
[reg
.Register
.Index
]);
1731 /* add to base_addr - passed in temp_reg.x */
1733 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1736 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1744 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
1747 struct r600_bytecode_alu alu
;
1750 if ((ctx
->bc
->cf_last
->ndw
>>1) >= 0x60)
1751 ctx
->bc
->force_add_cf
= 1;
1752 for (i
= 1; i
< 4; i
++) {
1753 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1756 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
1760 for (i
= 0; i
< 4; i
++) {
1761 /* emit an LDS_READ_RET */
1762 memset(&alu
, 0, sizeof(alu
));
1763 alu
.op
= LDS_OP1_LDS_READ_RET
;
1764 alu
.src
[0].sel
= temp_reg
;
1765 alu
.src
[0].chan
= i
;
1766 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1767 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
1769 alu
.is_lds_idx_op
= true;
1771 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1775 for (i
= 0; i
< 4; i
++) {
1776 /* then read from LDS_OQ_A_POP */
1777 memset(&alu
, 0, sizeof(alu
));
1779 alu
.op
= ALU_OP1_MOV
;
1780 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
;
1781 alu
.src
[0].chan
= 0;
1782 alu
.dst
.sel
= dst_reg
;
1786 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1793 static int fetch_tes_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1796 unsigned temp_reg
= r600_get_temp(ctx
);
1798 r
= get_lds_offset0(ctx
, 2, temp_reg
,
1799 src
->Register
.Dimension
? false : true);
1803 /* the base address is now in temp.x */
1804 r
= r600_get_byte_address(ctx
, temp_reg
,
1805 NULL
, src
, ctx
->tess_output_info
, 1);
1809 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1815 static int fetch_tcs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1818 unsigned temp_reg
= r600_get_temp(ctx
);
1820 /* t.x = ips * r0.y */
1821 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
1823 ctx
->tess_input_info
, 0,
1829 /* the base address is now in temp.x */
1830 r
= r600_get_byte_address(ctx
, temp_reg
,
1831 NULL
, src
, ctx
->tess_input_info
, 1);
1835 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1841 static int fetch_tcs_output(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1844 unsigned temp_reg
= r600_get_temp(ctx
);
1846 r
= get_lds_offset0(ctx
, 1, temp_reg
,
1847 src
->Register
.Dimension
? false : true);
1850 /* the base address is now in temp.x */
1851 r
= r600_get_byte_address(ctx
, temp_reg
,
1853 ctx
->tess_output_info
, 1);
1857 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
);
1863 static int tgsi_split_lds_inputs(struct r600_shader_ctx
*ctx
)
1865 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1868 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1869 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1871 if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1872 int treg
= r600_get_temp(ctx
);
1873 fetch_tes_input(ctx
, src
, treg
);
1874 ctx
->src
[i
].sel
= treg
;
1875 ctx
->src
[i
].rel
= 0;
1877 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1878 int treg
= r600_get_temp(ctx
);
1879 fetch_tcs_input(ctx
, src
, treg
);
1880 ctx
->src
[i
].sel
= treg
;
1881 ctx
->src
[i
].rel
= 0;
1883 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_OUTPUT
) {
1884 int treg
= r600_get_temp(ctx
);
1885 fetch_tcs_output(ctx
, src
, treg
);
1886 ctx
->src
[i
].sel
= treg
;
1887 ctx
->src
[i
].rel
= 0;
1893 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1895 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1896 struct r600_bytecode_alu alu
;
1897 int i
, j
, k
, nconst
, r
;
1899 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1900 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1903 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1905 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1906 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1910 if (ctx
->src
[i
].rel
) {
1911 int chan
= inst
->Src
[i
].Indirect
.Swizzle
;
1912 int treg
= r600_get_temp(ctx
);
1913 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].kc_bank
, ctx
->src
[i
].kc_rel
, ctx
->src
[i
].sel
- 512, chan
, treg
)))
1916 ctx
->src
[i
].kc_bank
= 0;
1917 ctx
->src
[i
].kc_rel
= 0;
1918 ctx
->src
[i
].sel
= treg
;
1919 ctx
->src
[i
].rel
= 0;
1922 int treg
= r600_get_temp(ctx
);
1923 for (k
= 0; k
< 4; k
++) {
1924 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1925 alu
.op
= ALU_OP1_MOV
;
1926 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1927 alu
.src
[0].chan
= k
;
1928 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
1929 alu
.src
[0].kc_bank
= ctx
->src
[i
].kc_bank
;
1930 alu
.src
[0].kc_rel
= ctx
->src
[i
].kc_rel
;
1936 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1940 ctx
->src
[i
].sel
= treg
;
1948 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1949 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1951 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1952 struct r600_bytecode_alu alu
;
1953 int i
, j
, k
, nliteral
, r
;
1955 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1956 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1960 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1961 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1962 int treg
= r600_get_temp(ctx
);
1963 for (k
= 0; k
< 4; k
++) {
1964 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1965 alu
.op
= ALU_OP1_MOV
;
1966 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1967 alu
.src
[0].chan
= k
;
1968 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1974 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1978 ctx
->src
[i
].sel
= treg
;
1985 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
1987 int i
, r
, count
= ctx
->shader
->ninput
;
1989 for (i
= 0; i
< count
; i
++) {
1990 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
1991 r
= select_twoside_color(ctx
, i
, ctx
->shader
->input
[i
].back_color_input
);
1999 static int emit_streamout(struct r600_shader_ctx
*ctx
, struct pipe_stream_output_info
*so
,
2000 int stream
, unsigned *stream_item_size
)
2002 unsigned so_gpr
[PIPE_MAX_SHADER_OUTPUTS
];
2003 unsigned start_comp
[PIPE_MAX_SHADER_OUTPUTS
];
2006 /* Sanity checking. */
2007 if (so
->num_outputs
> PIPE_MAX_SO_OUTPUTS
) {
2008 R600_ERR("Too many stream outputs: %d\n", so
->num_outputs
);
2012 for (i
= 0; i
< so
->num_outputs
; i
++) {
2013 if (so
->output
[i
].output_buffer
>= 4) {
2014 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2015 so
->output
[i
].output_buffer
);
2021 /* Initialize locations where the outputs are stored. */
2022 for (i
= 0; i
< so
->num_outputs
; i
++) {
2024 so_gpr
[i
] = ctx
->shader
->output
[so
->output
[i
].register_index
].gpr
;
2025 start_comp
[i
] = so
->output
[i
].start_component
;
2026 /* Lower outputs with dst_offset < start_component.
2028 * We can only output 4D vectors with a write mask, e.g. we can
2029 * only output the W component at offset 3, etc. If we want
2030 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2031 * to move it to X and output X. */
2032 if (so
->output
[i
].dst_offset
< so
->output
[i
].start_component
) {
2033 unsigned tmp
= r600_get_temp(ctx
);
2035 for (j
= 0; j
< so
->output
[i
].num_components
; j
++) {
2036 struct r600_bytecode_alu alu
;
2037 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2038 alu
.op
= ALU_OP1_MOV
;
2039 alu
.src
[0].sel
= so_gpr
[i
];
2040 alu
.src
[0].chan
= so
->output
[i
].start_component
+ j
;
2045 if (j
== so
->output
[i
].num_components
- 1)
2047 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2056 /* Write outputs to buffers. */
2057 for (i
= 0; i
< so
->num_outputs
; i
++) {
2058 struct r600_bytecode_output output
;
2060 if (stream
!= -1 && stream
!= so
->output
[i
].output_buffer
)
2063 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2064 output
.gpr
= so_gpr
[i
];
2065 output
.elem_size
= so
->output
[i
].num_components
- 1;
2066 if (output
.elem_size
== 2)
2067 output
.elem_size
= 3; // 3 not supported, write 4 with junk at end
2068 output
.array_base
= so
->output
[i
].dst_offset
- start_comp
[i
];
2069 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2070 output
.burst_count
= 1;
2071 /* array_size is an upper limit for the burst_count
2072 * with MEM_STREAM instructions */
2073 output
.array_size
= 0xFFF;
2074 output
.comp_mask
= ((1 << so
->output
[i
].num_components
) - 1) << start_comp
[i
];
2076 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
2077 switch (so
->output
[i
].output_buffer
) {
2079 output
.op
= CF_OP_MEM_STREAM0_BUF0
;
2082 output
.op
= CF_OP_MEM_STREAM0_BUF1
;
2085 output
.op
= CF_OP_MEM_STREAM0_BUF2
;
2088 output
.op
= CF_OP_MEM_STREAM0_BUF3
;
2091 output
.op
+= so
->output
[i
].stream
* 4;
2092 assert(output
.op
>= CF_OP_MEM_STREAM0_BUF0
&& output
.op
<= CF_OP_MEM_STREAM3_BUF3
);
2093 ctx
->enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << so
->output
[i
].stream
* 4;
2095 switch (so
->output
[i
].output_buffer
) {
2097 output
.op
= CF_OP_MEM_STREAM0
;
2100 output
.op
= CF_OP_MEM_STREAM1
;
2103 output
.op
= CF_OP_MEM_STREAM2
;
2106 output
.op
= CF_OP_MEM_STREAM3
;
2109 ctx
->enabled_stream_buffers_mask
|= 1 << so
->output
[i
].output_buffer
;
2111 r
= r600_bytecode_add_output(ctx
->bc
, &output
);
2120 static void convert_edgeflag_to_int(struct r600_shader_ctx
*ctx
)
2122 struct r600_bytecode_alu alu
;
2125 if (!ctx
->shader
->vs_out_edgeflag
)
2128 reg
= ctx
->shader
->output
[ctx
->edgeflag_output
].gpr
;
2130 /* clamp(x, 0, 1) */
2131 memset(&alu
, 0, sizeof(alu
));
2132 alu
.op
= ALU_OP1_MOV
;
2133 alu
.src
[0].sel
= reg
;
2138 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2140 memset(&alu
, 0, sizeof(alu
));
2141 alu
.op
= ALU_OP1_FLT_TO_INT
;
2142 alu
.src
[0].sel
= reg
;
2146 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2149 static int generate_gs_copy_shader(struct r600_context
*rctx
,
2150 struct r600_pipe_shader
*gs
,
2151 struct pipe_stream_output_info
*so
)
2153 struct r600_shader_ctx ctx
= {};
2154 struct r600_shader
*gs_shader
= &gs
->shader
;
2155 struct r600_pipe_shader
*cshader
;
2156 int ocnt
= gs_shader
->noutput
;
2157 struct r600_bytecode_alu alu
;
2158 struct r600_bytecode_vtx vtx
;
2159 struct r600_bytecode_output output
;
2160 struct r600_bytecode_cf
*cf_jump
, *cf_pop
,
2161 *last_exp_pos
= NULL
, *last_exp_param
= NULL
;
2162 int i
, j
, next_clip_pos
= 61, next_param
= 0;
2164 bool only_ring_0
= true;
2165 cshader
= calloc(1, sizeof(struct r600_pipe_shader
));
2169 memcpy(cshader
->shader
.output
, gs_shader
->output
, ocnt
*
2170 sizeof(struct r600_shader_io
));
2172 cshader
->shader
.noutput
= ocnt
;
2174 ctx
.shader
= &cshader
->shader
;
2175 ctx
.bc
= &ctx
.shader
->bc
;
2176 ctx
.type
= ctx
.bc
->type
= PIPE_SHADER_VERTEX
;
2178 r600_bytecode_init(ctx
.bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2179 rctx
->screen
->has_compressed_msaa_texturing
);
2181 ctx
.bc
->isa
= rctx
->isa
;
2184 memset(cshader
->shader
.ring_item_sizes
, 0, sizeof(cshader
->shader
.ring_item_sizes
));
2186 /* R0.x = R0.x & 0x3fffffff */
2187 memset(&alu
, 0, sizeof(alu
));
2188 alu
.op
= ALU_OP2_AND_INT
;
2189 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2190 alu
.src
[1].value
= 0x3fffffff;
2192 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2194 /* R0.y = R0.x >> 30 */
2195 memset(&alu
, 0, sizeof(alu
));
2196 alu
.op
= ALU_OP2_LSHR_INT
;
2197 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2198 alu
.src
[1].value
= 0x1e;
2202 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2204 /* fetch vertex data from GSVS ring */
2205 for (i
= 0; i
< ocnt
; ++i
) {
2206 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2209 out
->ring_offset
= i
* 16;
2211 memset(&vtx
, 0, sizeof(vtx
));
2212 vtx
.op
= FETCH_OP_VFETCH
;
2213 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
2214 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2215 vtx
.mega_fetch_count
= 16;
2216 vtx
.offset
= out
->ring_offset
;
2217 vtx
.dst_gpr
= out
->gpr
;
2223 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2224 vtx
.use_const_fields
= 1;
2226 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
2229 r600_bytecode_add_vtx(ctx
.bc
, &vtx
);
2231 ctx
.temp_reg
= i
+ 1;
2232 for (ring
= 3; ring
>= 0; --ring
) {
2233 bool enabled
= false;
2234 for (i
= 0; i
< so
->num_outputs
; i
++) {
2235 if (so
->output
[i
].stream
== ring
) {
2238 only_ring_0
= false;
2242 if (ring
!= 0 && !enabled
) {
2243 cshader
->shader
.ring_item_sizes
[ring
] = 0;
2248 // Patch up jump label
2249 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2250 cf_pop
= ctx
.bc
->cf_last
;
2252 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2253 cf_jump
->pop_count
= 1;
2254 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2255 cf_pop
->pop_count
= 1;
2258 /* PRED_SETE_INT __, R0.y, ring */
2259 memset(&alu
, 0, sizeof(alu
));
2260 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2261 alu
.src
[0].chan
= 1;
2262 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2263 alu
.src
[1].value
= ring
;
2264 alu
.execute_mask
= 1;
2265 alu
.update_pred
= 1;
2267 r600_bytecode_add_alu_type(ctx
.bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2269 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_JUMP
);
2270 cf_jump
= ctx
.bc
->cf_last
;
2273 emit_streamout(&ctx
, so
, only_ring_0
? -1 : ring
, &cshader
->shader
.ring_item_sizes
[ring
]);
2274 cshader
->shader
.ring_item_sizes
[ring
] = ocnt
* 16;
2277 /* bc adds nops - copy it */
2278 if (ctx
.bc
->chip_class
== R600
) {
2279 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2280 alu
.op
= ALU_OP0_NOP
;
2282 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2284 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2287 /* export vertex data */
2288 /* XXX factor out common code with r600_shader_from_tgsi ? */
2289 for (i
= 0; i
< ocnt
; ++i
) {
2290 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2291 bool instream0
= true;
2292 if (out
->name
== TGSI_SEMANTIC_CLIPVERTEX
)
2295 for (j
= 0; j
< so
->num_outputs
; j
++) {
2296 if (so
->output
[j
].register_index
== i
) {
2297 if (so
->output
[j
].stream
== 0)
2299 if (so
->output
[j
].stream
> 0)
2305 memset(&output
, 0, sizeof(output
));
2306 output
.gpr
= out
->gpr
;
2307 output
.elem_size
= 3;
2308 output
.swizzle_x
= 0;
2309 output
.swizzle_y
= 1;
2310 output
.swizzle_z
= 2;
2311 output
.swizzle_w
= 3;
2312 output
.burst_count
= 1;
2313 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2314 output
.op
= CF_OP_EXPORT
;
2315 switch (out
->name
) {
2316 case TGSI_SEMANTIC_POSITION
:
2317 output
.array_base
= 60;
2318 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2321 case TGSI_SEMANTIC_PSIZE
:
2322 output
.array_base
= 61;
2323 if (next_clip_pos
== 61)
2325 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2326 output
.swizzle_y
= 7;
2327 output
.swizzle_z
= 7;
2328 output
.swizzle_w
= 7;
2329 ctx
.shader
->vs_out_misc_write
= 1;
2330 ctx
.shader
->vs_out_point_size
= 1;
2332 case TGSI_SEMANTIC_LAYER
:
2334 /* duplicate it as PARAM to pass to the pixel shader */
2335 output
.array_base
= next_param
++;
2336 r600_bytecode_add_output(ctx
.bc
, &output
);
2337 last_exp_param
= ctx
.bc
->cf_last
;
2339 output
.array_base
= 61;
2340 if (next_clip_pos
== 61)
2342 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2343 output
.swizzle_x
= 7;
2344 output
.swizzle_y
= 7;
2345 output
.swizzle_z
= 0;
2346 output
.swizzle_w
= 7;
2347 ctx
.shader
->vs_out_misc_write
= 1;
2348 ctx
.shader
->vs_out_layer
= 1;
2350 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2352 /* duplicate it as PARAM to pass to the pixel shader */
2353 output
.array_base
= next_param
++;
2354 r600_bytecode_add_output(ctx
.bc
, &output
);
2355 last_exp_param
= ctx
.bc
->cf_last
;
2357 output
.array_base
= 61;
2358 if (next_clip_pos
== 61)
2360 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2361 ctx
.shader
->vs_out_misc_write
= 1;
2362 ctx
.shader
->vs_out_viewport
= 1;
2363 output
.swizzle_x
= 7;
2364 output
.swizzle_y
= 7;
2365 output
.swizzle_z
= 7;
2366 output
.swizzle_w
= 0;
2368 case TGSI_SEMANTIC_CLIPDIST
:
2369 /* spi_sid is 0 for clipdistance outputs that were generated
2370 * for clipvertex - we don't need to pass them to PS */
2371 ctx
.shader
->clip_dist_write
= gs
->shader
.clip_dist_write
;
2373 /* duplicate it as PARAM to pass to the pixel shader */
2374 output
.array_base
= next_param
++;
2375 r600_bytecode_add_output(ctx
.bc
, &output
);
2376 last_exp_param
= ctx
.bc
->cf_last
;
2378 output
.array_base
= next_clip_pos
++;
2379 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2381 case TGSI_SEMANTIC_FOG
:
2382 output
.swizzle_y
= 4; /* 0 */
2383 output
.swizzle_z
= 4; /* 0 */
2384 output
.swizzle_w
= 5; /* 1 */
2387 output
.array_base
= next_param
++;
2390 r600_bytecode_add_output(ctx
.bc
, &output
);
2391 if (output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
)
2392 last_exp_param
= ctx
.bc
->cf_last
;
2394 last_exp_pos
= ctx
.bc
->cf_last
;
2397 if (!last_exp_pos
) {
2398 memset(&output
, 0, sizeof(output
));
2400 output
.elem_size
= 3;
2401 output
.swizzle_x
= 7;
2402 output
.swizzle_y
= 7;
2403 output
.swizzle_z
= 7;
2404 output
.swizzle_w
= 7;
2405 output
.burst_count
= 1;
2407 output
.op
= CF_OP_EXPORT
;
2408 output
.array_base
= 60;
2409 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2410 r600_bytecode_add_output(ctx
.bc
, &output
);
2411 last_exp_pos
= ctx
.bc
->cf_last
;
2414 if (!last_exp_param
) {
2415 memset(&output
, 0, sizeof(output
));
2417 output
.elem_size
= 3;
2418 output
.swizzle_x
= 7;
2419 output
.swizzle_y
= 7;
2420 output
.swizzle_z
= 7;
2421 output
.swizzle_w
= 7;
2422 output
.burst_count
= 1;
2424 output
.op
= CF_OP_EXPORT
;
2425 output
.array_base
= next_param
++;
2426 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2427 r600_bytecode_add_output(ctx
.bc
, &output
);
2428 last_exp_param
= ctx
.bc
->cf_last
;
2431 last_exp_pos
->op
= CF_OP_EXPORT_DONE
;
2432 last_exp_param
->op
= CF_OP_EXPORT_DONE
;
2434 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2435 cf_pop
= ctx
.bc
->cf_last
;
2437 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2438 cf_jump
->pop_count
= 1;
2439 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2440 cf_pop
->pop_count
= 1;
2442 if (ctx
.bc
->chip_class
== CAYMAN
)
2443 cm_bytecode_add_cf_end(ctx
.bc
);
2445 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2446 ctx
.bc
->cf_last
->end_of_program
= 1;
2449 gs
->gs_copy_shader
= cshader
;
2450 cshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
2454 return r600_bytecode_build(ctx
.bc
);
2457 static int emit_inc_ring_offset(struct r600_shader_ctx
*ctx
, int idx
, bool ind
)
2460 struct r600_bytecode_alu alu
;
2463 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2464 alu
.op
= ALU_OP2_ADD_INT
;
2465 alu
.src
[0].sel
= ctx
->gs_export_gpr_tregs
[idx
];
2466 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2467 alu
.src
[1].value
= ctx
->gs_out_ring_offset
>> 4;
2468 alu
.dst
.sel
= ctx
->gs_export_gpr_tregs
[idx
];
2471 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2478 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
)
2480 struct r600_bytecode_output output
;
2481 int i
, k
, ring_offset
;
2482 int effective_stream
= stream
== -1 ? 0 : stream
;
2485 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2486 if (ctx
->gs_for_vs
) {
2487 /* for ES we need to lookup corresponding ring offset expected by GS
2488 * (map this output to GS input by name and sid) */
2489 /* FIXME precompute offsets */
2491 for(k
= 0; k
< ctx
->gs_for_vs
->ninput
; ++k
) {
2492 struct r600_shader_io
*in
= &ctx
->gs_for_vs
->input
[k
];
2493 struct r600_shader_io
*out
= &ctx
->shader
->output
[i
];
2494 if (in
->name
== out
->name
&& in
->sid
== out
->sid
)
2495 ring_offset
= in
->ring_offset
;
2498 if (ring_offset
== -1)
2501 ring_offset
= idx
* 16;
2505 if (stream
> 0 && ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2507 /* next_ring_offset after parsing input decls contains total size of
2508 * single vertex data, gs_next_vertex - current vertex index */
2510 ring_offset
+= ctx
->gs_out_ring_offset
* ctx
->gs_next_vertex
;
2512 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2513 output
.gpr
= ctx
->shader
->output
[i
].gpr
;
2514 output
.elem_size
= 3;
2515 output
.comp_mask
= 0xF;
2516 output
.burst_count
= 1;
2519 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
2521 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2526 output
.op
= CF_OP_MEM_RING
; break;
2528 output
.op
= CF_OP_MEM_RING1
; break;
2530 output
.op
= CF_OP_MEM_RING2
; break;
2532 output
.op
= CF_OP_MEM_RING3
; break;
2536 output
.array_base
= ring_offset
>> 2; /* in dwords */
2537 output
.array_size
= 0xfff;
2538 output
.index_gpr
= ctx
->gs_export_gpr_tregs
[effective_stream
];
2540 output
.array_base
= ring_offset
>> 2; /* in dwords */
2541 r600_bytecode_add_output(ctx
->bc
, &output
);
2544 ++ctx
->gs_next_vertex
;
2549 static int r600_fetch_tess_io_info(struct r600_shader_ctx
*ctx
)
2552 struct r600_bytecode_vtx vtx
;
2553 int temp_val
= ctx
->temp_reg
;
2554 /* need to store the TCS output somewhere */
2555 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2557 V_SQ_ALU_SRC_LITERAL
, 0,
2562 /* used by VS/TCS */
2563 if (ctx
->tess_input_info
) {
2564 /* fetch tcs input values into resv space */
2565 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2566 vtx
.op
= FETCH_OP_VFETCH
;
2567 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2568 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2569 vtx
.mega_fetch_count
= 16;
2570 vtx
.data_format
= FMT_32_32_32_32
;
2571 vtx
.num_format_all
= 2;
2572 vtx
.format_comp_all
= 1;
2573 vtx
.use_const_fields
= 0;
2574 vtx
.endian
= r600_endian_swap(32);
2575 vtx
.srf_mode_all
= 1;
2577 vtx
.dst_gpr
= ctx
->tess_input_info
;
2582 vtx
.src_gpr
= temp_val
;
2585 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2590 /* used by TCS/TES */
2591 if (ctx
->tess_output_info
) {
2592 /* fetch tcs output values into resv space */
2593 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2594 vtx
.op
= FETCH_OP_VFETCH
;
2595 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2596 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2597 vtx
.mega_fetch_count
= 16;
2598 vtx
.data_format
= FMT_32_32_32_32
;
2599 vtx
.num_format_all
= 2;
2600 vtx
.format_comp_all
= 1;
2601 vtx
.use_const_fields
= 0;
2602 vtx
.endian
= r600_endian_swap(32);
2603 vtx
.srf_mode_all
= 1;
2605 vtx
.dst_gpr
= ctx
->tess_output_info
;
2610 vtx
.src_gpr
= temp_val
;
2613 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2620 static int emit_lds_vs_writes(struct r600_shader_ctx
*ctx
)
2625 /* fetch tcs input values into input_vals */
2626 ctx
->tess_input_info
= r600_get_temp(ctx
);
2627 ctx
->tess_output_info
= 0;
2628 r
= r600_fetch_tess_io_info(ctx
);
2632 temp_reg
= r600_get_temp(ctx
);
2633 /* dst reg contains LDS address stride * idx */
2634 /* MUL vertexID, vertex_dw_stride */
2635 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
2637 ctx
->tess_input_info
, 1,
2638 0, 1); /* rel id in r0.y? */
2642 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2643 struct r600_bytecode_alu alu
;
2644 int param
= r600_get_lds_unique_index(ctx
->shader
->output
[i
].name
, ctx
->shader
->output
[i
].sid
);
2647 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2650 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2655 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2657 temp_reg
, param
? 1 : 0,
2658 V_SQ_ALU_SRC_LITERAL
, 8);
2663 for (j
= 0; j
< 2; j
++) {
2664 int chan
= (j
== 1) ? 2 : (param
? 1 : 0);
2665 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2666 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2667 alu
.src
[0].sel
= temp_reg
;
2668 alu
.src
[0].chan
= chan
;
2669 alu
.src
[1].sel
= ctx
->shader
->output
[i
].gpr
;
2670 alu
.src
[1].chan
= j
* 2;
2671 alu
.src
[2].sel
= ctx
->shader
->output
[i
].gpr
;
2672 alu
.src
[2].chan
= (j
* 2) + 1;
2676 alu
.is_lds_idx_op
= true;
2677 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2685 static int r600_store_tcs_output(struct r600_shader_ctx
*ctx
)
2687 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2688 const struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
2690 int temp_reg
= r600_get_temp(ctx
);
2691 struct r600_bytecode_alu alu
;
2692 unsigned write_mask
= dst
->Register
.WriteMask
;
2694 if (inst
->Dst
[0].Register
.File
!= TGSI_FILE_OUTPUT
)
2697 r
= get_lds_offset0(ctx
, 1, temp_reg
, dst
->Register
.Dimension
? false : true);
2701 /* the base address is now in temp.x */
2702 r
= r600_get_byte_address(ctx
, temp_reg
,
2703 &inst
->Dst
[0], NULL
, ctx
->tess_output_info
, 1);
2708 lasti
= tgsi_last_instruction(write_mask
);
2709 for (i
= 1; i
<= lasti
; i
++) {
2711 if (!(write_mask
& (1 << i
)))
2713 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2716 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2721 for (i
= 0; i
<= lasti
; i
++) {
2722 if (!(write_mask
& (1 << i
)))
2725 if ((i
== 0 && ((write_mask
& 3) == 3)) ||
2726 (i
== 2 && ((write_mask
& 0xc) == 0xc))) {
2727 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2728 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2729 alu
.src
[0].sel
= temp_reg
;
2730 alu
.src
[0].chan
= i
;
2732 alu
.src
[1].sel
= dst
->Register
.Index
;
2733 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2734 alu
.src
[1].chan
= i
;
2736 alu
.src
[2].sel
= dst
->Register
.Index
;
2737 alu
.src
[2].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2738 alu
.src
[2].chan
= i
+ 1;
2742 alu
.is_lds_idx_op
= true;
2743 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2749 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2750 alu
.op
= LDS_OP2_LDS_WRITE
;
2751 alu
.src
[0].sel
= temp_reg
;
2752 alu
.src
[0].chan
= i
;
2754 alu
.src
[1].sel
= dst
->Register
.Index
;
2755 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2756 alu
.src
[1].chan
= i
;
2758 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
2761 alu
.is_lds_idx_op
= true;
2762 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2769 static int r600_tess_factor_read(struct r600_shader_ctx
*ctx
,
2773 unsigned temp_reg
= r600_get_temp(ctx
);
2774 unsigned name
= ctx
->shader
->output
[output_idx
].name
;
2775 int dreg
= ctx
->shader
->output
[output_idx
].gpr
;
2778 param
= r600_get_lds_unique_index(name
, 0);
2779 r
= get_lds_offset0(ctx
, 1, temp_reg
, true);
2783 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2786 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2790 do_lds_fetch_values(ctx
, temp_reg
, dreg
);
2794 static int r600_emit_tess_factor(struct r600_shader_ctx
*ctx
)
2797 int stride
, outer_comps
, inner_comps
;
2798 int tessinner_idx
= -1, tessouter_idx
= -1;
2800 int temp_reg
= r600_get_temp(ctx
);
2801 int treg
[3] = {-1, -1, -1};
2802 struct r600_bytecode_alu alu
;
2803 struct r600_bytecode_cf
*cf_jump
, *cf_pop
;
2805 /* only execute factor emission for invocation 0 */
2806 /* PRED_SETE_INT __, R0.x, 0 */
2807 memset(&alu
, 0, sizeof(alu
));
2808 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2809 alu
.src
[0].chan
= 2;
2810 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2811 alu
.execute_mask
= 1;
2812 alu
.update_pred
= 1;
2814 r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2816 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
2817 cf_jump
= ctx
->bc
->cf_last
;
2819 treg
[0] = r600_get_temp(ctx
);
2820 switch (ctx
->shader
->tcs_prim_mode
) {
2821 case PIPE_PRIM_LINES
:
2822 stride
= 8; /* 2 dwords, 1 vec2 store */
2826 case PIPE_PRIM_TRIANGLES
:
2827 stride
= 16; /* 4 dwords, 1 vec4 store */
2830 treg
[1] = r600_get_temp(ctx
);
2832 case PIPE_PRIM_QUADS
:
2833 stride
= 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2836 treg
[1] = r600_get_temp(ctx
);
2837 treg
[2] = r600_get_temp(ctx
);
2844 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2845 /* TF_WRITE takes index in R.x, value in R.y */
2846 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2847 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSINNER
)
2849 if (ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_TESSOUTER
)
2853 if (tessouter_idx
== -1)
2856 if (tessinner_idx
== -1 && inner_comps
)
2859 if (tessouter_idx
!= -1) {
2860 r
= r600_tess_factor_read(ctx
, tessouter_idx
);
2865 if (tessinner_idx
!= -1) {
2866 r
= r600_tess_factor_read(ctx
, tessinner_idx
);
2871 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2872 /* r.x = relpatchid(r0.y) * tf_stride */
2874 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2875 /* add incoming r0.w to it: t.x = t.x + r0.w */
2876 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
2879 V_SQ_ALU_SRC_LITERAL
, stride
,
2884 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2885 int out_idx
= i
>= outer_comps
? tessinner_idx
: tessouter_idx
;
2886 int out_comp
= i
>= outer_comps
? i
- outer_comps
: i
;
2888 if (ctx
->shader
->tcs_prim_mode
== PIPE_PRIM_LINES
) {
2891 else if (out_comp
== 0)
2895 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2896 treg
[i
/ 2], (2 * (i
% 2)),
2898 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2901 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2902 treg
[i
/ 2], 1 + (2 * (i
%2)),
2903 ctx
->shader
->output
[out_idx
].gpr
, out_comp
,
2908 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2909 struct r600_bytecode_gds gds
;
2911 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
2912 gds
.src_gpr
= treg
[i
/ 2];
2913 gds
.src_sel_x
= 2 * (i
% 2);
2914 gds
.src_sel_y
= 1 + (2 * (i
% 2));
2920 gds
.op
= FETCH_OP_TF_WRITE
;
2921 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
2926 // Patch up jump label
2927 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
2928 cf_pop
= ctx
->bc
->cf_last
;
2930 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2931 cf_jump
->pop_count
= 1;
2932 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2933 cf_pop
->pop_count
= 1;
2938 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
2939 struct r600_pipe_shader
*pipeshader
,
2940 union r600_shader_key key
)
2942 struct r600_screen
*rscreen
= rctx
->screen
;
2943 struct r600_shader
*shader
= &pipeshader
->shader
;
2944 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
2945 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
2946 struct tgsi_full_immediate
*immediate
;
2947 struct r600_shader_ctx ctx
;
2948 struct r600_bytecode_output output
[ARRAY_SIZE(shader
->output
)];
2949 unsigned output_done
, noutput
;
2952 int next_param_base
= 0, next_clip_base
;
2953 int max_color_exports
= MAX2(key
.ps
.nr_cbufs
, 1);
2955 bool ring_outputs
= false;
2956 bool lds_outputs
= false;
2957 bool lds_inputs
= false;
2958 bool pos_emitted
= false;
2960 ctx
.bc
= &shader
->bc
;
2961 ctx
.shader
= shader
;
2962 ctx
.native_integers
= true;
2964 r600_bytecode_init(ctx
.bc
, rscreen
->b
.chip_class
, rscreen
->b
.family
,
2965 rscreen
->has_compressed_msaa_texturing
);
2966 ctx
.tokens
= tokens
;
2967 tgsi_scan_shader(tokens
, &ctx
.info
);
2968 shader
->indirect_files
= ctx
.info
.indirect_files
;
2970 shader
->uses_doubles
= ctx
.info
.uses_doubles
;
2971 shader
->uses_atomics
= ctx
.info
.file_mask
[TGSI_FILE_HW_ATOMIC
];
2972 shader
->nsys_inputs
= 0;
2974 indirect_gprs
= ctx
.info
.indirect_files
& ~((1 << TGSI_FILE_CONSTANT
) | (1 << TGSI_FILE_SAMPLER
));
2975 tgsi_parse_init(&ctx
.parse
, tokens
);
2976 ctx
.type
= ctx
.info
.processor
;
2977 shader
->processor_type
= ctx
.type
;
2978 ctx
.bc
->type
= shader
->processor_type
;
2981 case PIPE_SHADER_VERTEX
:
2982 shader
->vs_as_gs_a
= key
.vs
.as_gs_a
;
2983 shader
->vs_as_es
= key
.vs
.as_es
;
2984 shader
->vs_as_ls
= key
.vs
.as_ls
;
2985 shader
->atomic_base
= key
.vs
.first_atomic_counter
;
2986 if (shader
->vs_as_es
)
2987 ring_outputs
= true;
2988 if (shader
->vs_as_ls
)
2991 case PIPE_SHADER_GEOMETRY
:
2992 ring_outputs
= true;
2993 shader
->atomic_base
= key
.gs
.first_atomic_counter
;
2994 shader
->gs_tri_strip_adj_fix
= key
.gs
.tri_strip_adj_fix
;
2996 case PIPE_SHADER_TESS_CTRL
:
2997 shader
->tcs_prim_mode
= key
.tcs
.prim_mode
;
2998 shader
->atomic_base
= key
.tcs
.first_atomic_counter
;
3002 case PIPE_SHADER_TESS_EVAL
:
3003 shader
->tes_as_es
= key
.tes
.as_es
;
3004 shader
->atomic_base
= key
.tes
.first_atomic_counter
;
3006 if (shader
->tes_as_es
)
3007 ring_outputs
= true;
3009 case PIPE_SHADER_FRAGMENT
:
3010 shader
->two_side
= key
.ps
.color_two_side
;
3011 shader
->atomic_base
= key
.ps
.first_atomic_counter
;
3017 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3018 ctx
.gs_for_vs
= &rctx
->gs_shader
->current
->shader
;
3020 ctx
.gs_for_vs
= NULL
;
3023 ctx
.next_ring_offset
= 0;
3024 ctx
.gs_out_ring_offset
= 0;
3025 ctx
.gs_next_vertex
= 0;
3026 ctx
.gs_stream_output_info
= &so
;
3029 ctx
.fixed_pt_position_gpr
= -1;
3030 ctx
.fragcoord_input
= -1;
3031 ctx
.colors_used
= 0;
3032 ctx
.clip_vertex_write
= 0;
3034 shader
->nr_ps_color_exports
= 0;
3035 shader
->nr_ps_max_color_exports
= 0;
3038 /* register allocations */
3039 /* Values [0,127] correspond to GPR[0..127].
3040 * Values [128,159] correspond to constant buffer bank 0
3041 * Values [160,191] correspond to constant buffer bank 1
3042 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3043 * Values [256,287] correspond to constant buffer bank 2 (EG)
3044 * Values [288,319] correspond to constant buffer bank 3 (EG)
3045 * Other special values are shown in the list below.
3046 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3047 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3048 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3049 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3050 * 248 SQ_ALU_SRC_0: special constant 0.0.
3051 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3052 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3053 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3054 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3055 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3056 * 254 SQ_ALU_SRC_PV: previous vector result.
3057 * 255 SQ_ALU_SRC_PS: previous scalar result.
3059 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
3060 ctx
.file_offset
[i
] = 0;
3063 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3065 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3066 if (ctx
.info
.num_inputs
)
3067 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CALL_FS
);
3069 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
3070 if (ctx
.bc
->chip_class
>= EVERGREEN
)
3071 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
3073 ctx
.file_offset
[TGSI_FILE_INPUT
] = allocate_system_value_inputs(&ctx
, ctx
.file_offset
[TGSI_FILE_INPUT
]);
3075 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3076 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3077 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
3079 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3080 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3081 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3082 bool add_tesscoord
= false, add_tess_inout
= false;
3083 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3084 for (i
= 0; i
< PIPE_MAX_SHADER_INPUTS
; i
++) {
3085 /* if we have tesscoord save one reg */
3086 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSCOORD
)
3087 add_tesscoord
= true;
3088 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSINNER
||
3089 ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSOUTER
)
3090 add_tess_inout
= true;
3092 if (add_tesscoord
|| add_tess_inout
)
3093 ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3095 ctx
.file_offset
[TGSI_FILE_INPUT
]+=2;
3098 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3099 ctx
.file_offset
[TGSI_FILE_INPUT
] +
3100 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3101 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
3102 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3104 /* Outside the GPR range. This will be translated to one of the
3105 * kcache banks later. */
3106 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
3108 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
3109 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
3110 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3111 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 1;
3112 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 2;
3114 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3115 ctx
.tess_input_info
= ctx
.bc
->ar_reg
+ 3;
3116 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 4;
3117 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 5;
3118 } else if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3119 ctx
.tess_input_info
= 0;
3120 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 3;
3121 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 4;
3122 } else if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3123 ctx
.gs_export_gpr_tregs
[0] = ctx
.bc
->ar_reg
+ 3;
3124 ctx
.gs_export_gpr_tregs
[1] = ctx
.bc
->ar_reg
+ 4;
3125 ctx
.gs_export_gpr_tregs
[2] = ctx
.bc
->ar_reg
+ 5;
3126 ctx
.gs_export_gpr_tregs
[3] = ctx
.bc
->ar_reg
+ 6;
3127 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 7;
3128 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3129 ctx
.gs_rotated_input
[0] = ctx
.bc
->ar_reg
+ 7;
3130 ctx
.gs_rotated_input
[1] = ctx
.bc
->ar_reg
+ 8;
3133 ctx
.gs_rotated_input
[0] = 0;
3134 ctx
.gs_rotated_input
[1] = 1;
3137 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 3;
3140 shader
->max_arrays
= 0;
3141 shader
->num_arrays
= 0;
3142 if (indirect_gprs
) {
3144 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_INPUT
)) {
3145 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_INPUT
],
3146 ctx
.file_offset
[TGSI_FILE_OUTPUT
] -
3147 ctx
.file_offset
[TGSI_FILE_INPUT
],
3150 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_OUTPUT
)) {
3151 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3152 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] -
3153 ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3159 ctx
.literals
= NULL
;
3161 shader
->fs_write_all
= ctx
.info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
3162 ctx
.info
.colors_written
== 1;
3163 shader
->vs_position_window_space
= ctx
.info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
3164 shader
->ps_conservative_z
= (uint8_t)ctx
.info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
];
3166 if (shader
->vs_as_gs_a
)
3167 vs_add_primid_output(&ctx
, key
.vs
.prim_id_out
);
3169 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3170 r600_fetch_tess_io_info(&ctx
);
3172 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3173 tgsi_parse_token(&ctx
.parse
);
3174 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3175 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3176 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
3177 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
3178 if(ctx
.literals
== NULL
) {
3182 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
3183 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
3184 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
3185 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
3188 case TGSI_TOKEN_TYPE_DECLARATION
:
3189 r
= tgsi_declaration(&ctx
);
3193 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3194 case TGSI_TOKEN_TYPE_PROPERTY
:
3197 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
3203 shader
->ring_item_sizes
[0] = ctx
.next_ring_offset
;
3204 shader
->ring_item_sizes
[1] = 0;
3205 shader
->ring_item_sizes
[2] = 0;
3206 shader
->ring_item_sizes
[3] = 0;
3208 /* Process two side if needed */
3209 if (shader
->two_side
&& ctx
.colors_used
) {
3210 int i
, count
= ctx
.shader
->ninput
;
3211 unsigned next_lds_loc
= ctx
.shader
->nlds
;
3213 /* additional inputs will be allocated right after the existing inputs,
3214 * we won't need them after the color selection, so we don't need to
3215 * reserve these gprs for the rest of the shader code and to adjust
3216 * output offsets etc. */
3217 int gpr
= ctx
.file_offset
[TGSI_FILE_INPUT
] +
3218 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3220 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3221 if (ctx
.face_gpr
== -1) {
3222 i
= ctx
.shader
->ninput
++;
3223 ctx
.shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
3224 ctx
.shader
->input
[i
].spi_sid
= 0;
3225 ctx
.shader
->input
[i
].gpr
= gpr
++;
3226 ctx
.face_gpr
= ctx
.shader
->input
[i
].gpr
;
3229 for (i
= 0; i
< count
; i
++) {
3230 if (ctx
.shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3231 int ni
= ctx
.shader
->ninput
++;
3232 memcpy(&ctx
.shader
->input
[ni
],&ctx
.shader
->input
[i
], sizeof(struct r600_shader_io
));
3233 ctx
.shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
3234 ctx
.shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
.shader
->input
[ni
]);
3235 ctx
.shader
->input
[ni
].gpr
= gpr
++;
3236 // TGSI to LLVM needs to know the lds position of inputs.
3237 // Non LLVM path computes it later (in process_twoside_color)
3238 ctx
.shader
->input
[ni
].lds_pos
= next_lds_loc
++;
3239 ctx
.shader
->input
[i
].back_color_input
= ni
;
3240 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
3241 if ((r
= evergreen_interp_input(&ctx
, ni
)))
3248 if (shader
->fs_write_all
&& rscreen
->b
.chip_class
>= EVERGREEN
)
3249 shader
->nr_ps_max_color_exports
= 8;
3251 if (ctx
.fragcoord_input
>= 0) {
3252 if (ctx
.bc
->chip_class
== CAYMAN
) {
3253 for (j
= 0 ; j
< 4; j
++) {
3254 struct r600_bytecode_alu alu
;
3255 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3256 alu
.op
= ALU_OP1_RECIP_IEEE
;
3257 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3258 alu
.src
[0].chan
= 3;
3260 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3262 alu
.dst
.write
= (j
== 3);
3264 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3268 struct r600_bytecode_alu alu
;
3269 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3270 alu
.op
= ALU_OP1_RECIP_IEEE
;
3271 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3272 alu
.src
[0].chan
= 3;
3274 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3278 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3283 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3284 struct r600_bytecode_alu alu
;
3287 /* GS thread with no output workaround - emit a cut at start of GS */
3288 if (ctx
.bc
->chip_class
== R600
)
3289 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CUT_VERTEX
);
3291 for (j
= 0; j
< 4; j
++) {
3292 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3293 alu
.op
= ALU_OP1_MOV
;
3294 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3295 alu
.src
[0].value
= 0;
3296 alu
.dst
.sel
= ctx
.gs_export_gpr_tregs
[j
];
3299 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3304 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3305 r
= single_alu_op2(&ctx
, ALU_OP2_AND_INT
,
3306 ctx
.gs_rotated_input
[0], 2,
3308 V_SQ_ALU_SRC_LITERAL
, 1);
3312 for (i
= 0; i
< 6; i
++) {
3313 int rotated
= (i
+ 4) % 6;
3314 int offset_reg
= i
/ 3;
3315 int offset_chan
= i
% 3;
3316 int rotated_offset_reg
= rotated
/ 3;
3317 int rotated_offset_chan
= rotated
% 3;
3319 if (offset_reg
== 0 && offset_chan
== 2)
3321 if (rotated_offset_reg
== 0 && rotated_offset_chan
== 2)
3322 rotated_offset_chan
= 3;
3324 r
= single_alu_op3(&ctx
, ALU_OP3_CNDE_INT
,
3325 ctx
.gs_rotated_input
[offset_reg
], offset_chan
,
3326 ctx
.gs_rotated_input
[0], 2,
3327 offset_reg
, offset_chan
,
3328 rotated_offset_reg
, rotated_offset_chan
);
3335 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3336 r600_fetch_tess_io_info(&ctx
);
3338 if (shader
->two_side
&& ctx
.colors_used
) {
3339 if ((r
= process_twoside_color_inputs(&ctx
)))
3343 tgsi_parse_init(&ctx
.parse
, tokens
);
3344 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3345 tgsi_parse_token(&ctx
.parse
);
3346 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3347 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3348 r
= tgsi_is_supported(&ctx
);
3351 ctx
.max_driver_temp_used
= 0;
3352 /* reserve first tmp for everyone */
3353 r600_get_temp(&ctx
);
3355 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3356 if ((r
= tgsi_split_constant(&ctx
)))
3358 if ((r
= tgsi_split_literal_constant(&ctx
)))
3360 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3361 if ((r
= tgsi_split_gs_inputs(&ctx
)))
3363 } else if (lds_inputs
) {
3364 if ((r
= tgsi_split_lds_inputs(&ctx
)))
3367 if (ctx
.bc
->chip_class
== CAYMAN
)
3368 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
3369 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
3370 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
3372 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
3373 r
= ctx
.inst_info
->process(&ctx
);
3377 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3378 r
= r600_store_tcs_output(&ctx
);
3388 /* Reset the temporary register counter. */
3389 ctx
.max_driver_temp_used
= 0;
3391 noutput
= shader
->noutput
;
3393 if (!ring_outputs
&& ctx
.clip_vertex_write
) {
3394 unsigned clipdist_temp
[2];
3396 clipdist_temp
[0] = r600_get_temp(&ctx
);
3397 clipdist_temp
[1] = r600_get_temp(&ctx
);
3399 /* need to convert a clipvertex write into clipdistance writes and not export
3400 the clip vertex anymore */
3402 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
3403 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3404 shader
->output
[noutput
].gpr
= clipdist_temp
[0];
3406 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3407 shader
->output
[noutput
].gpr
= clipdist_temp
[1];
3410 /* reset spi_sid for clipvertex output to avoid confusing spi */
3411 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
3413 shader
->clip_dist_write
= 0xFF;
3415 for (i
= 0; i
< 8; i
++) {
3419 for (j
= 0; j
< 4; j
++) {
3420 struct r600_bytecode_alu alu
;
3421 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3422 alu
.op
= ALU_OP2_DOT4
;
3423 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
3424 alu
.src
[0].chan
= j
;
3426 alu
.src
[1].sel
= 512 + i
;
3427 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
3428 alu
.src
[1].chan
= j
;
3430 alu
.dst
.sel
= clipdist_temp
[oreg
];
3432 alu
.dst
.write
= (j
== ochan
);
3435 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3442 /* Add stream outputs. */
3443 if (so
.num_outputs
) {
3445 if (!lds_outputs
&& !ring_outputs
&& ctx
.type
== PIPE_SHADER_VERTEX
)
3447 if (!ring_outputs
&& ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3450 emit_streamout(&ctx
, &so
, -1, NULL
);
3452 pipeshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
3453 convert_edgeflag_to_int(&ctx
);
3455 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3456 r600_emit_tess_factor(&ctx
);
3459 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3460 if (ctx
.shader
->noutput
)
3461 emit_lds_vs_writes(&ctx
);
3463 } else if (ring_outputs
) {
3464 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3465 ctx
.gs_export_gpr_tregs
[0] = r600_get_temp(&ctx
);
3466 ctx
.gs_export_gpr_tregs
[1] = -1;
3467 ctx
.gs_export_gpr_tregs
[2] = -1;
3468 ctx
.gs_export_gpr_tregs
[3] = -1;
3470 emit_gs_ring_writes(&ctx
, &so
, -1, FALSE
);
3474 next_clip_base
= shader
->vs_out_misc_write
? 62 : 61;
3476 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
3477 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3478 output
[j
].gpr
= shader
->output
[i
].gpr
;
3479 output
[j
].elem_size
= 3;
3480 output
[j
].swizzle_x
= 0;
3481 output
[j
].swizzle_y
= 1;
3482 output
[j
].swizzle_z
= 2;
3483 output
[j
].swizzle_w
= 3;
3484 output
[j
].burst_count
= 1;
3485 output
[j
].type
= -1;
3486 output
[j
].op
= CF_OP_EXPORT
;
3488 case PIPE_SHADER_VERTEX
:
3489 case PIPE_SHADER_TESS_EVAL
:
3490 switch (shader
->output
[i
].name
) {
3491 case TGSI_SEMANTIC_POSITION
:
3492 output
[j
].array_base
= 60;
3493 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3497 case TGSI_SEMANTIC_PSIZE
:
3498 output
[j
].array_base
= 61;
3499 output
[j
].swizzle_y
= 7;
3500 output
[j
].swizzle_z
= 7;
3501 output
[j
].swizzle_w
= 7;
3502 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3505 case TGSI_SEMANTIC_EDGEFLAG
:
3506 output
[j
].array_base
= 61;
3507 output
[j
].swizzle_x
= 7;
3508 output
[j
].swizzle_y
= 0;
3509 output
[j
].swizzle_z
= 7;
3510 output
[j
].swizzle_w
= 7;
3511 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3514 case TGSI_SEMANTIC_LAYER
:
3515 /* spi_sid is 0 for outputs that are
3516 * not consumed by PS */
3517 if (shader
->output
[i
].spi_sid
) {
3518 output
[j
].array_base
= next_param_base
++;
3519 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3521 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3523 output
[j
].array_base
= 61;
3524 output
[j
].swizzle_x
= 7;
3525 output
[j
].swizzle_y
= 7;
3526 output
[j
].swizzle_z
= 0;
3527 output
[j
].swizzle_w
= 7;
3528 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3531 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
3532 /* spi_sid is 0 for outputs that are
3533 * not consumed by PS */
3534 if (shader
->output
[i
].spi_sid
) {
3535 output
[j
].array_base
= next_param_base
++;
3536 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3538 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3540 output
[j
].array_base
= 61;
3541 output
[j
].swizzle_x
= 7;
3542 output
[j
].swizzle_y
= 7;
3543 output
[j
].swizzle_z
= 7;
3544 output
[j
].swizzle_w
= 0;
3545 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3548 case TGSI_SEMANTIC_CLIPVERTEX
:
3551 case TGSI_SEMANTIC_CLIPDIST
:
3552 output
[j
].array_base
= next_clip_base
++;
3553 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3555 /* spi_sid is 0 for clipdistance outputs that were generated
3556 * for clipvertex - we don't need to pass them to PS */
3557 if (shader
->output
[i
].spi_sid
) {
3559 /* duplicate it as PARAM to pass to the pixel shader */
3560 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3561 output
[j
].array_base
= next_param_base
++;
3562 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3565 case TGSI_SEMANTIC_FOG
:
3566 output
[j
].swizzle_y
= 4; /* 0 */
3567 output
[j
].swizzle_z
= 4; /* 0 */
3568 output
[j
].swizzle_w
= 5; /* 1 */
3570 case TGSI_SEMANTIC_PRIMID
:
3571 output
[j
].swizzle_x
= 2;
3572 output
[j
].swizzle_y
= 4; /* 0 */
3573 output
[j
].swizzle_z
= 4; /* 0 */
3574 output
[j
].swizzle_w
= 4; /* 0 */
3579 case PIPE_SHADER_FRAGMENT
:
3580 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3581 /* never export more colors than the number of CBs */
3582 if (shader
->output
[i
].sid
>= max_color_exports
) {
3587 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3588 output
[j
].array_base
= shader
->output
[i
].sid
;
3589 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3590 shader
->nr_ps_color_exports
++;
3591 if (shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
)) {
3592 for (k
= 1; k
< max_color_exports
; k
++) {
3594 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3595 output
[j
].gpr
= shader
->output
[i
].gpr
;
3596 output
[j
].elem_size
= 3;
3597 output
[j
].swizzle_x
= 0;
3598 output
[j
].swizzle_y
= 1;
3599 output
[j
].swizzle_z
= 2;
3600 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3601 output
[j
].burst_count
= 1;
3602 output
[j
].array_base
= k
;
3603 output
[j
].op
= CF_OP_EXPORT
;
3604 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3605 shader
->nr_ps_color_exports
++;
3608 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
3609 output
[j
].array_base
= 61;
3610 output
[j
].swizzle_x
= 2;
3611 output
[j
].swizzle_y
= 7;
3612 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3613 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3614 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
3615 output
[j
].array_base
= 61;
3616 output
[j
].swizzle_x
= 7;
3617 output
[j
].swizzle_y
= 1;
3618 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3619 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3620 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3621 output
[j
].array_base
= 61;
3622 output
[j
].swizzle_x
= 7;
3623 output
[j
].swizzle_y
= 7;
3624 output
[j
].swizzle_z
= 0;
3625 output
[j
].swizzle_w
= 7;
3626 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3628 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
3633 case PIPE_SHADER_TESS_CTRL
:
3636 R600_ERR("unsupported processor type %d\n", ctx
.type
);
3641 if (output
[j
].type
==-1) {
3642 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3643 output
[j
].array_base
= next_param_base
++;
3647 /* add fake position export */
3648 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && pos_emitted
== false) {
3649 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3651 output
[j
].elem_size
= 3;
3652 output
[j
].swizzle_x
= 7;
3653 output
[j
].swizzle_y
= 7;
3654 output
[j
].swizzle_z
= 7;
3655 output
[j
].swizzle_w
= 7;
3656 output
[j
].burst_count
= 1;
3657 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3658 output
[j
].array_base
= 60;
3659 output
[j
].op
= CF_OP_EXPORT
;
3663 /* add fake param output for vertex shader if no param is exported */
3664 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && next_param_base
== 0) {
3665 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3667 output
[j
].elem_size
= 3;
3668 output
[j
].swizzle_x
= 7;
3669 output
[j
].swizzle_y
= 7;
3670 output
[j
].swizzle_z
= 7;
3671 output
[j
].swizzle_w
= 7;
3672 output
[j
].burst_count
= 1;
3673 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3674 output
[j
].array_base
= 0;
3675 output
[j
].op
= CF_OP_EXPORT
;
3679 /* add fake pixel export */
3680 if (ctx
.type
== PIPE_SHADER_FRAGMENT
&& shader
->nr_ps_color_exports
== 0) {
3681 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3683 output
[j
].elem_size
= 3;
3684 output
[j
].swizzle_x
= 7;
3685 output
[j
].swizzle_y
= 7;
3686 output
[j
].swizzle_z
= 7;
3687 output
[j
].swizzle_w
= 7;
3688 output
[j
].burst_count
= 1;
3689 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3690 output
[j
].array_base
= 0;
3691 output
[j
].op
= CF_OP_EXPORT
;
3693 shader
->nr_ps_color_exports
++;
3698 /* set export done on last export of each type */
3699 for (i
= noutput
- 1, output_done
= 0; i
>= 0; i
--) {
3700 if (!(output_done
& (1 << output
[i
].type
))) {
3701 output_done
|= (1 << output
[i
].type
);
3702 output
[i
].op
= CF_OP_EXPORT_DONE
;
3705 /* add output to bytecode */
3706 for (i
= 0; i
< noutput
; i
++) {
3707 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
3713 /* add program end */
3714 if (ctx
.bc
->chip_class
== CAYMAN
)
3715 cm_bytecode_add_cf_end(ctx
.bc
);
3717 const struct cf_op_info
*last
= NULL
;
3719 if (ctx
.bc
->cf_last
)
3720 last
= r600_isa_cf(ctx
.bc
->cf_last
->op
);
3722 /* alu clause instructions don't have EOP bit, so add NOP */
3723 if (!last
|| last
->flags
& CF_ALU
|| ctx
.bc
->cf_last
->op
== CF_OP_LOOP_END
|| ctx
.bc
->cf_last
->op
== CF_OP_CALL_FS
|| ctx
.bc
->cf_last
->op
== CF_OP_POP
|| ctx
.bc
->cf_last
->op
== CF_OP_GDS
)
3724 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
3726 ctx
.bc
->cf_last
->end_of_program
= 1;
3729 /* check GPR limit - we have 124 = 128 - 4
3730 * (4 are reserved as alu clause temporary registers) */
3731 if (ctx
.bc
->ngpr
> 124) {
3732 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
3737 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3738 if ((r
= generate_gs_copy_shader(rctx
, pipeshader
, &so
)))
3743 tgsi_parse_free(&ctx
.parse
);
3747 tgsi_parse_free(&ctx
.parse
);
3751 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
3753 const unsigned tgsi_opcode
=
3754 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3755 R600_ERR("%s tgsi opcode unsupported\n",
3756 tgsi_get_opcode_name(tgsi_opcode
));
3760 static int tgsi_end(struct r600_shader_ctx
*ctx
)
3765 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
3766 const struct r600_shader_src
*shader_src
,
3769 bc_src
->sel
= shader_src
->sel
;
3770 bc_src
->chan
= shader_src
->swizzle
[chan
];
3771 bc_src
->neg
= shader_src
->neg
;
3772 bc_src
->abs
= shader_src
->abs
;
3773 bc_src
->rel
= shader_src
->rel
;
3774 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
3775 bc_src
->kc_bank
= shader_src
->kc_bank
;
3776 bc_src
->kc_rel
= shader_src
->kc_rel
;
3779 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
3785 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
3787 bc_src
->neg
= !bc_src
->neg
;
3790 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
3791 const struct tgsi_full_dst_register
*tgsi_dst
,
3793 struct r600_bytecode_alu_dst
*r600_dst
)
3795 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3797 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
3798 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
3799 r600_dst
->chan
= swizzle
;
3800 r600_dst
->write
= 1;
3801 if (inst
->Instruction
.Saturate
) {
3802 r600_dst
->clamp
= 1;
3804 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
3805 if (tgsi_dst
->Register
.File
== TGSI_FILE_OUTPUT
) {
3809 if (tgsi_dst
->Register
.Indirect
)
3810 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
3814 static int tgsi_op2_64_params(struct r600_shader_ctx
*ctx
, bool singledest
, bool swap
)
3816 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3817 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3818 struct r600_bytecode_alu alu
;
3819 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3823 switch (write_mask
) {
3841 lasti
= tgsi_last_instruction(write_mask
);
3842 for (i
= 0; i
<= lasti
; i
++) {
3844 if (!(write_mask
& (1 << i
)))
3847 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3850 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3852 alu
.dst
.sel
= ctx
->temp_reg
;
3856 if (i
== 1 || i
== 3)
3859 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3861 alu
.op
= ctx
->inst_info
->op
;
3862 if (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DABS
) {
3863 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
3865 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3866 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
3869 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], fp64_switch(i
));
3870 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], fp64_switch(i
));
3873 /* handle some special cases */
3874 if (i
== 1 || i
== 3) {
3875 switch (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
) {
3876 case TGSI_OPCODE_DABS
:
3877 r600_bytecode_src_set_abs(&alu
.src
[0]);
3886 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3892 write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3894 /* move result from temp to dst */
3895 for (i
= 0; i
<= lasti
; i
++) {
3896 if (!(write_mask
& (1 << i
)))
3899 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3900 alu
.op
= ALU_OP1_MOV
;
3901 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3902 alu
.src
[0].sel
= ctx
->temp_reg
;
3903 alu
.src
[0].chan
= use_tmp
- 1;
3904 alu
.last
= (i
== lasti
);
3906 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3914 static int tgsi_op2_64(struct r600_shader_ctx
*ctx
)
3916 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3917 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3918 /* confirm writemasking */
3919 if ((write_mask
& 0x3) != 0x3 &&
3920 (write_mask
& 0xc) != 0xc) {
3921 fprintf(stderr
, "illegal writemask for 64-bit: 0x%x\n", write_mask
);
3924 return tgsi_op2_64_params(ctx
, false, false);
3927 static int tgsi_op2_64_single_dest(struct r600_shader_ctx
*ctx
)
3929 return tgsi_op2_64_params(ctx
, true, false);
3932 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx
*ctx
)
3934 return tgsi_op2_64_params(ctx
, true, true);
3937 static int tgsi_op3_64(struct r600_shader_ctx
*ctx
)
3939 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3940 struct r600_bytecode_alu alu
;
3943 int tmp
= r600_get_temp(ctx
);
3945 for (i
= 0; i
< lasti
+ 1; i
++) {
3947 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3948 alu
.op
= ctx
->inst_info
->op
;
3949 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3950 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
== 3 ? 0 : 1);
3953 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
3954 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3963 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3970 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
3972 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3973 struct r600_bytecode_alu alu
;
3974 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3975 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3976 /* use temp register if trans_only and more than one dst component */
3977 int use_tmp
= trans_only
&& (write_mask
^ (1 << lasti
));
3978 unsigned op
= ctx
->inst_info
->op
;
3980 if (op
== ALU_OP2_MUL_IEEE
&&
3981 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
3984 for (i
= 0; i
<= lasti
; i
++) {
3985 if (!(write_mask
& (1 << i
)))
3988 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3990 alu
.dst
.sel
= ctx
->temp_reg
;
3994 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3998 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
3999 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4002 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4003 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4005 if (i
== lasti
|| trans_only
) {
4008 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4014 /* move result from temp to dst */
4015 for (i
= 0; i
<= lasti
; i
++) {
4016 if (!(write_mask
& (1 << i
)))
4019 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4020 alu
.op
= ALU_OP1_MOV
;
4021 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4022 alu
.src
[0].sel
= ctx
->temp_reg
;
4023 alu
.src
[0].chan
= i
;
4024 alu
.last
= (i
== lasti
);
4026 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4034 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
4036 return tgsi_op2_s(ctx
, 0, 0);
4039 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
4041 return tgsi_op2_s(ctx
, 1, 0);
4044 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
4046 return tgsi_op2_s(ctx
, 0, 1);
4049 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
4051 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4052 struct r600_bytecode_alu alu
;
4054 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4056 for (i
= 0; i
< lasti
+ 1; i
++) {
4058 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4060 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4061 alu
.op
= ctx
->inst_info
->op
;
4063 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4065 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4067 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4072 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4080 static int tgsi_dneg(struct r600_shader_ctx
*ctx
)
4082 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4083 struct r600_bytecode_alu alu
;
4085 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4087 for (i
= 0; i
< lasti
+ 1; i
++) {
4089 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4091 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4092 alu
.op
= ALU_OP1_MOV
;
4094 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4096 if (i
== 1 || i
== 3)
4097 r600_bytecode_src_toggle_neg(&alu
.src
[0]);
4098 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4103 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4111 static int tgsi_dfracexp(struct r600_shader_ctx
*ctx
)
4113 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4114 struct r600_bytecode_alu alu
;
4115 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4118 for (i
= 0; i
<= 3; i
++) {
4119 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4120 alu
.op
= ctx
->inst_info
->op
;
4122 alu
.dst
.sel
= ctx
->temp_reg
;
4125 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4126 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4132 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4137 /* Replicate significand result across channels. */
4138 for (i
= 0; i
<= 3; i
++) {
4139 if (!(write_mask
& (1 << i
)))
4142 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4143 alu
.op
= ALU_OP1_MOV
;
4144 alu
.src
[0].chan
= (i
& 1) + 2;
4145 alu
.src
[0].sel
= ctx
->temp_reg
;
4147 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4150 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4155 for (i
= 0; i
<= 3; i
++) {
4156 if (inst
->Dst
[1].Register
.WriteMask
& (1 << i
)) {
4157 /* MOV third channels to writemask dst1 */
4158 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4159 alu
.op
= ALU_OP1_MOV
;
4160 alu
.src
[0].chan
= 1;
4161 alu
.src
[0].sel
= ctx
->temp_reg
;
4163 tgsi_dst(ctx
, &inst
->Dst
[1], i
, &alu
.dst
);
4165 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4175 static int egcm_int_to_double(struct r600_shader_ctx
*ctx
)
4177 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4178 struct r600_bytecode_alu alu
;
4180 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4182 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_I2D
||
4183 inst
->Instruction
.Opcode
== TGSI_OPCODE_U2D
);
4185 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4186 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4187 alu
.op
= ctx
->inst_info
->op
;
4189 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4190 alu
.dst
.sel
= ctx
->temp_reg
;
4195 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4200 for (i
= 0; i
<= lasti
; i
++) {
4201 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4202 alu
.op
= ALU_OP1_FLT32_TO_FLT64
;
4204 alu
.src
[0].chan
= i
/2;
4206 alu
.src
[0].sel
= ctx
->temp_reg
;
4208 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
4209 alu
.src
[0].value
= 0x0;
4211 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4212 alu
.last
= i
== lasti
;
4214 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4222 static int egcm_double_to_int(struct r600_shader_ctx
*ctx
)
4224 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4225 struct r600_bytecode_alu alu
;
4227 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4229 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_D2I
||
4230 inst
->Instruction
.Opcode
== TGSI_OPCODE_D2U
);
4232 for (i
= 0; i
<= lasti
; i
++) {
4233 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4234 alu
.op
= ALU_OP1_FLT64_TO_FLT32
;
4236 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], fp64_switch(i
));
4238 alu
.dst
.sel
= ctx
->temp_reg
;
4239 alu
.dst
.write
= i
%2 == 0;
4240 alu
.last
= i
== lasti
;
4242 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4247 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4248 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4249 alu
.op
= ctx
->inst_info
->op
;
4251 alu
.src
[0].chan
= i
*2;
4252 alu
.src
[0].sel
= ctx
->temp_reg
;
4253 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4256 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4264 static int cayman_emit_unary_double_raw(struct r600_bytecode
*bc
,
4267 struct r600_shader_src
*src
,
4270 struct r600_bytecode_alu alu
;
4271 const int last_slot
= 3;
4274 /* these have to write the result to X/Y by the looks of it */
4275 for (int i
= 0 ; i
< last_slot
; i
++) {
4276 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4279 r600_bytecode_src(&alu
.src
[0], src
, 1);
4280 r600_bytecode_src(&alu
.src
[1], src
, 0);
4283 r600_bytecode_src_set_abs(&alu
.src
[1]);
4285 alu
.dst
.sel
= dst_reg
;
4287 alu
.dst
.write
= (i
== 0 || i
== 1);
4289 if (bc
->chip_class
!= CAYMAN
|| i
== last_slot
- 1)
4291 r
= r600_bytecode_add_alu(bc
, &alu
);
4299 static int cayman_emit_double_instr(struct r600_shader_ctx
*ctx
)
4301 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4303 struct r600_bytecode_alu alu
;
4304 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4305 int t1
= ctx
->temp_reg
;
4307 /* should only be one src regs */
4308 assert(inst
->Instruction
.NumSrcRegs
== 1);
4310 /* only support one double at a time */
4311 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4312 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4314 r
= cayman_emit_unary_double_raw(
4315 ctx
->bc
, ctx
->inst_info
->op
, t1
,
4317 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DRSQ
||
4318 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DSQRT
);
4322 for (i
= 0 ; i
<= lasti
; i
++) {
4323 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4325 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4326 alu
.op
= ALU_OP1_MOV
;
4327 alu
.src
[0].sel
= t1
;
4328 alu
.src
[0].chan
= (i
== 0 || i
== 2) ? 0 : 1;
4329 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4333 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4340 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
4342 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4344 struct r600_bytecode_alu alu
;
4345 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4347 for (i
= 0 ; i
< last_slot
; i
++) {
4348 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4349 alu
.op
= ctx
->inst_info
->op
;
4350 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4351 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
4353 /* RSQ should take the absolute value of src */
4354 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RSQ
) {
4355 r600_bytecode_src_set_abs(&alu
.src
[j
]);
4358 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4359 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4361 if (i
== last_slot
- 1)
4363 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4370 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
4372 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4374 struct r600_bytecode_alu alu
;
4375 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4376 int t1
= ctx
->temp_reg
;
4378 for (k
= 0; k
<= lasti
; k
++) {
4379 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
4382 for (i
= 0 ; i
< 4; i
++) {
4383 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4384 alu
.op
= ctx
->inst_info
->op
;
4385 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4386 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
4390 alu
.dst
.write
= (i
== k
);
4393 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4399 for (i
= 0 ; i
<= lasti
; i
++) {
4400 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4402 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4403 alu
.op
= ALU_OP1_MOV
;
4404 alu
.src
[0].sel
= t1
;
4405 alu
.src
[0].chan
= i
;
4406 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4410 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4419 static int cayman_mul_double_instr(struct r600_shader_ctx
*ctx
)
4421 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4423 struct r600_bytecode_alu alu
;
4424 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4425 int t1
= ctx
->temp_reg
;
4427 /* t1 would get overwritten below if we actually tried to
4428 * multiply two pairs of doubles at a time. */
4429 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4430 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4432 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4434 for (i
= 0; i
< 4; i
++) {
4435 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4436 alu
.op
= ctx
->inst_info
->op
;
4437 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4438 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
* 2 + ((i
== 3) ? 0 : 1));
4445 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4450 for (i
= 0; i
<= lasti
; i
++) {
4451 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4453 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4454 alu
.op
= ALU_OP1_MOV
;
4455 alu
.src
[0].sel
= t1
;
4456 alu
.src
[0].chan
= i
;
4457 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4461 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4470 * Emit RECIP_64 + MUL_64 to implement division.
4472 static int cayman_ddiv_instr(struct r600_shader_ctx
*ctx
)
4474 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4476 struct r600_bytecode_alu alu
;
4477 int t1
= ctx
->temp_reg
;
4480 /* Only support one double at a time. This is the same constraint as
4481 * in DMUL lowering. */
4482 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4483 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4485 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4487 r
= cayman_emit_unary_double_raw(ctx
->bc
, ALU_OP2_RECIP_64
, t1
, &ctx
->src
[1], false);
4491 for (int i
= 0; i
< 4; i
++) {
4492 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4493 alu
.op
= ALU_OP2_MUL_64
;
4495 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], k
* 2 + ((i
== 3) ? 0 : 1));
4497 alu
.src
[1].sel
= t1
;
4498 alu
.src
[1].chan
= (i
== 3) ? 0 : 1;
4505 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4510 for (int i
= 0; i
< 2; i
++) {
4511 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4512 alu
.op
= ALU_OP1_MOV
;
4513 alu
.src
[0].sel
= t1
;
4514 alu
.src
[0].chan
= i
;
4515 tgsi_dst(ctx
, &inst
->Dst
[0], k
* 2 + i
, &alu
.dst
);
4519 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4527 * r600 - trunc to -PI..PI range
4528 * r700 - normalize by dividing by 2PI
4531 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
4534 struct r600_bytecode_alu alu
;
4536 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4537 alu
.op
= ALU_OP3_MULADD
;
4541 alu
.dst
.sel
= ctx
->temp_reg
;
4544 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4546 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4547 alu
.src
[1].chan
= 0;
4548 alu
.src
[1].value
= u_bitcast_f2u(0.5f
* M_1_PI
);
4549 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4550 alu
.src
[2].chan
= 0;
4552 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4556 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4557 alu
.op
= ALU_OP1_FRACT
;
4560 alu
.dst
.sel
= ctx
->temp_reg
;
4563 alu
.src
[0].sel
= ctx
->temp_reg
;
4564 alu
.src
[0].chan
= 0;
4566 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4570 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4571 alu
.op
= ALU_OP3_MULADD
;
4575 alu
.dst
.sel
= ctx
->temp_reg
;
4578 alu
.src
[0].sel
= ctx
->temp_reg
;
4579 alu
.src
[0].chan
= 0;
4581 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4582 alu
.src
[1].chan
= 0;
4583 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
4584 alu
.src
[2].chan
= 0;
4586 if (ctx
->bc
->chip_class
== R600
) {
4587 alu
.src
[1].value
= u_bitcast_f2u(2.0f
* M_PI
);
4588 alu
.src
[2].value
= u_bitcast_f2u(-M_PI
);
4590 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4591 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4596 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4602 static int cayman_trig(struct r600_shader_ctx
*ctx
)
4604 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4605 struct r600_bytecode_alu alu
;
4606 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4609 r
= tgsi_setup_trig(ctx
);
4614 for (i
= 0; i
< last_slot
; i
++) {
4615 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4616 alu
.op
= ctx
->inst_info
->op
;
4619 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4620 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4622 alu
.src
[0].sel
= ctx
->temp_reg
;
4623 alu
.src
[0].chan
= 0;
4624 if (i
== last_slot
- 1)
4626 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4633 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
4635 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4636 struct r600_bytecode_alu alu
;
4638 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4640 r
= tgsi_setup_trig(ctx
);
4644 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4645 alu
.op
= ctx
->inst_info
->op
;
4647 alu
.dst
.sel
= ctx
->temp_reg
;
4650 alu
.src
[0].sel
= ctx
->temp_reg
;
4651 alu
.src
[0].chan
= 0;
4653 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4657 /* replicate result */
4658 for (i
= 0; i
< lasti
+ 1; i
++) {
4659 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4662 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4663 alu
.op
= ALU_OP1_MOV
;
4665 alu
.src
[0].sel
= ctx
->temp_reg
;
4666 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4669 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4676 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
4678 const struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4679 struct r600_bytecode_alu alu
;
4682 for (i
= 0; i
< 4; i
++) {
4683 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4684 alu
.op
= ctx
->inst_info
->op
;
4688 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4690 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_KILL
) {
4691 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4694 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4699 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4704 /* kill must be last in ALU */
4705 ctx
->bc
->force_add_cf
= 1;
4706 ctx
->shader
->uses_kill
= TRUE
;
4710 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
4712 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4713 struct r600_bytecode_alu alu
;
4716 /* tmp.x = max(src.y, 0.0) */
4717 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4718 alu
.op
= ALU_OP2_MAX
;
4719 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
4720 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4721 alu
.src
[1].chan
= 1;
4723 alu
.dst
.sel
= ctx
->temp_reg
;
4728 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4732 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
4738 if (ctx
->bc
->chip_class
== CAYMAN
) {
4739 for (i
= 0; i
< 3; i
++) {
4740 /* tmp.z = log(tmp.x) */
4741 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4742 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4743 alu
.src
[0].sel
= ctx
->temp_reg
;
4744 alu
.src
[0].chan
= 0;
4745 alu
.dst
.sel
= ctx
->temp_reg
;
4753 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4758 /* tmp.z = log(tmp.x) */
4759 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4760 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4761 alu
.src
[0].sel
= ctx
->temp_reg
;
4762 alu
.src
[0].chan
= 0;
4763 alu
.dst
.sel
= ctx
->temp_reg
;
4767 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4772 chan
= alu
.dst
.chan
;
4775 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4776 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4777 alu
.op
= ALU_OP3_MUL_LIT
;
4778 alu
.src
[0].sel
= sel
;
4779 alu
.src
[0].chan
= chan
;
4780 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
4781 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
4782 alu
.dst
.sel
= ctx
->temp_reg
;
4787 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4791 if (ctx
->bc
->chip_class
== CAYMAN
) {
4792 for (i
= 0; i
< 3; i
++) {
4793 /* dst.z = exp(tmp.x) */
4794 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4795 alu
.op
= ALU_OP1_EXP_IEEE
;
4796 alu
.src
[0].sel
= ctx
->temp_reg
;
4797 alu
.src
[0].chan
= 0;
4798 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4804 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4809 /* dst.z = exp(tmp.x) */
4810 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4811 alu
.op
= ALU_OP1_EXP_IEEE
;
4812 alu
.src
[0].sel
= ctx
->temp_reg
;
4813 alu
.src
[0].chan
= 0;
4814 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
4816 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4823 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4824 alu
.op
= ALU_OP1_MOV
;
4825 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
4826 alu
.src
[0].chan
= 0;
4827 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4828 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
4829 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4833 /* dst.y = max(src.x, 0.0) */
4834 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4835 alu
.op
= ALU_OP2_MAX
;
4836 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4837 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4838 alu
.src
[1].chan
= 0;
4839 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
4840 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
4841 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4846 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4847 alu
.op
= ALU_OP1_MOV
;
4848 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4849 alu
.src
[0].chan
= 0;
4850 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
4851 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
4853 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4860 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
4862 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4863 struct r600_bytecode_alu alu
;
4866 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4869 * For state trackers other than OpenGL, we'll want to use
4870 * _RECIPSQRT_IEEE instead.
4872 alu
.op
= ALU_OP1_RECIPSQRT_CLAMPED
;
4874 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4875 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4876 r600_bytecode_src_set_abs(&alu
.src
[i
]);
4878 alu
.dst
.sel
= ctx
->temp_reg
;
4881 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4884 /* replicate result */
4885 return tgsi_helper_tempx_replicate(ctx
);
4888 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
4890 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4891 struct r600_bytecode_alu alu
;
4894 for (i
= 0; i
< 4; i
++) {
4895 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4896 alu
.src
[0].sel
= ctx
->temp_reg
;
4897 alu
.op
= ALU_OP1_MOV
;
4899 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4900 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4903 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4910 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
4912 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4913 struct r600_bytecode_alu alu
;
4916 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4917 alu
.op
= ctx
->inst_info
->op
;
4918 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
4919 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
4921 alu
.dst
.sel
= ctx
->temp_reg
;
4924 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4927 /* replicate result */
4928 return tgsi_helper_tempx_replicate(ctx
);
4931 static int cayman_pow(struct r600_shader_ctx
*ctx
)
4933 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4935 struct r600_bytecode_alu alu
;
4936 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4938 for (i
= 0; i
< 3; i
++) {
4939 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4940 alu
.op
= ALU_OP1_LOG_IEEE
;
4941 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4942 alu
.dst
.sel
= ctx
->temp_reg
;
4947 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4953 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4954 alu
.op
= ALU_OP2_MUL
;
4955 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
4956 alu
.src
[1].sel
= ctx
->temp_reg
;
4957 alu
.dst
.sel
= ctx
->temp_reg
;
4960 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4964 for (i
= 0; i
< last_slot
; i
++) {
4965 /* POW(a,b) = EXP2(b * LOG2(a))*/
4966 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4967 alu
.op
= ALU_OP1_EXP_IEEE
;
4968 alu
.src
[0].sel
= ctx
->temp_reg
;
4970 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4971 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4972 if (i
== last_slot
- 1)
4974 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4981 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
4983 struct r600_bytecode_alu alu
;
4987 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4988 alu
.op
= ALU_OP1_LOG_IEEE
;
4989 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4990 alu
.dst
.sel
= ctx
->temp_reg
;
4993 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4997 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4998 alu
.op
= ALU_OP2_MUL
;
4999 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5000 alu
.src
[1].sel
= ctx
->temp_reg
;
5001 alu
.dst
.sel
= ctx
->temp_reg
;
5004 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5007 /* POW(a,b) = EXP2(b * LOG2(a))*/
5008 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5009 alu
.op
= ALU_OP1_EXP_IEEE
;
5010 alu
.src
[0].sel
= ctx
->temp_reg
;
5011 alu
.dst
.sel
= ctx
->temp_reg
;
5014 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5017 return tgsi_helper_tempx_replicate(ctx
);
5020 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
5022 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5023 struct r600_bytecode_alu alu
;
5025 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5026 int tmp0
= ctx
->temp_reg
;
5027 int tmp1
= r600_get_temp(ctx
);
5028 int tmp2
= r600_get_temp(ctx
);
5029 int tmp3
= r600_get_temp(ctx
);
5032 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5034 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5035 * 2. tmp0.z = lo (tmp0.x * src2)
5036 * 3. tmp0.w = -tmp0.z
5037 * 4. tmp0.y = hi (tmp0.x * src2)
5038 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5039 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5040 * 7. tmp1.x = tmp0.x - tmp0.w
5041 * 8. tmp1.y = tmp0.x + tmp0.w
5042 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5043 * 10. tmp0.z = hi(tmp0.x * src1) = q
5044 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5046 * 12. tmp0.w = src1 - tmp0.y = r
5047 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5048 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5052 * 15. tmp1.z = tmp0.z + 1 = q + 1
5053 * 16. tmp1.w = tmp0.z - 1 = q - 1
5057 * 15. tmp1.z = tmp0.w - src2 = r - src2
5058 * 16. tmp1.w = tmp0.w + src2 = r + src2
5062 * 17. tmp1.x = tmp1.x & tmp1.y
5064 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5065 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5067 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5068 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5072 * Same as unsigned, using abs values of the operands,
5073 * and fixing the sign of the result in the end.
5076 for (i
= 0; i
< 4; i
++) {
5077 if (!(write_mask
& (1<<i
)))
5082 /* tmp2.x = -src0 */
5083 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5084 alu
.op
= ALU_OP2_SUB_INT
;
5090 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5092 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5095 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5098 /* tmp2.y = -src1 */
5099 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5100 alu
.op
= ALU_OP2_SUB_INT
;
5106 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5108 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5111 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5114 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5115 /* it will be a sign of the quotient */
5118 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5119 alu
.op
= ALU_OP2_XOR_INT
;
5125 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5126 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5129 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5133 /* tmp2.x = |src0| */
5134 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5135 alu
.op
= ALU_OP3_CNDGE_INT
;
5142 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5143 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5144 alu
.src
[2].sel
= tmp2
;
5145 alu
.src
[2].chan
= 0;
5148 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5151 /* tmp2.y = |src1| */
5152 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5153 alu
.op
= ALU_OP3_CNDGE_INT
;
5160 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5161 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5162 alu
.src
[2].sel
= tmp2
;
5163 alu
.src
[2].chan
= 1;
5166 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5171 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5172 if (ctx
->bc
->chip_class
== CAYMAN
) {
5173 /* tmp3.x = u2f(src2) */
5174 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5175 alu
.op
= ALU_OP1_UINT_TO_FLT
;
5182 alu
.src
[0].sel
= tmp2
;
5183 alu
.src
[0].chan
= 1;
5185 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5189 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5192 /* tmp0.x = recip(tmp3.x) */
5193 for (j
= 0 ; j
< 3; j
++) {
5194 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5195 alu
.op
= ALU_OP1_RECIP_IEEE
;
5199 alu
.dst
.write
= (j
== 0);
5201 alu
.src
[0].sel
= tmp3
;
5202 alu
.src
[0].chan
= 0;
5206 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5210 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5211 alu
.op
= ALU_OP2_MUL
;
5213 alu
.src
[0].sel
= tmp0
;
5214 alu
.src
[0].chan
= 0;
5216 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5217 alu
.src
[1].value
= 0x4f800000;
5222 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5226 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5227 alu
.op
= ALU_OP1_FLT_TO_UINT
;
5233 alu
.src
[0].sel
= tmp3
;
5234 alu
.src
[0].chan
= 0;
5237 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5241 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5242 alu
.op
= ALU_OP1_RECIP_UINT
;
5249 alu
.src
[0].sel
= tmp2
;
5250 alu
.src
[0].chan
= 1;
5252 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5256 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5260 /* 2. tmp0.z = lo (tmp0.x * src2) */
5261 if (ctx
->bc
->chip_class
== CAYMAN
) {
5262 for (j
= 0 ; j
< 4; j
++) {
5263 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5264 alu
.op
= ALU_OP2_MULLO_UINT
;
5268 alu
.dst
.write
= (j
== 2);
5270 alu
.src
[0].sel
= tmp0
;
5271 alu
.src
[0].chan
= 0;
5273 alu
.src
[1].sel
= tmp2
;
5274 alu
.src
[1].chan
= 1;
5276 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5279 alu
.last
= (j
== 3);
5280 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5284 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5285 alu
.op
= ALU_OP2_MULLO_UINT
;
5291 alu
.src
[0].sel
= tmp0
;
5292 alu
.src
[0].chan
= 0;
5294 alu
.src
[1].sel
= tmp2
;
5295 alu
.src
[1].chan
= 1;
5297 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5301 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5305 /* 3. tmp0.w = -tmp0.z */
5306 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5307 alu
.op
= ALU_OP2_SUB_INT
;
5313 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5314 alu
.src
[1].sel
= tmp0
;
5315 alu
.src
[1].chan
= 2;
5318 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5321 /* 4. tmp0.y = hi (tmp0.x * src2) */
5322 if (ctx
->bc
->chip_class
== CAYMAN
) {
5323 for (j
= 0 ; j
< 4; j
++) {
5324 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5325 alu
.op
= ALU_OP2_MULHI_UINT
;
5329 alu
.dst
.write
= (j
== 1);
5331 alu
.src
[0].sel
= tmp0
;
5332 alu
.src
[0].chan
= 0;
5335 alu
.src
[1].sel
= tmp2
;
5336 alu
.src
[1].chan
= 1;
5338 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5340 alu
.last
= (j
== 3);
5341 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5345 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5346 alu
.op
= ALU_OP2_MULHI_UINT
;
5352 alu
.src
[0].sel
= tmp0
;
5353 alu
.src
[0].chan
= 0;
5356 alu
.src
[1].sel
= tmp2
;
5357 alu
.src
[1].chan
= 1;
5359 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5363 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5367 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5368 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5369 alu
.op
= ALU_OP3_CNDE_INT
;
5376 alu
.src
[0].sel
= tmp0
;
5377 alu
.src
[0].chan
= 1;
5378 alu
.src
[1].sel
= tmp0
;
5379 alu
.src
[1].chan
= 3;
5380 alu
.src
[2].sel
= tmp0
;
5381 alu
.src
[2].chan
= 2;
5384 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5387 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5388 if (ctx
->bc
->chip_class
== CAYMAN
) {
5389 for (j
= 0 ; j
< 4; j
++) {
5390 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5391 alu
.op
= ALU_OP2_MULHI_UINT
;
5395 alu
.dst
.write
= (j
== 3);
5397 alu
.src
[0].sel
= tmp0
;
5398 alu
.src
[0].chan
= 2;
5400 alu
.src
[1].sel
= tmp0
;
5401 alu
.src
[1].chan
= 0;
5403 alu
.last
= (j
== 3);
5404 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5408 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5409 alu
.op
= ALU_OP2_MULHI_UINT
;
5415 alu
.src
[0].sel
= tmp0
;
5416 alu
.src
[0].chan
= 2;
5418 alu
.src
[1].sel
= tmp0
;
5419 alu
.src
[1].chan
= 0;
5422 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5426 /* 7. tmp1.x = tmp0.x - tmp0.w */
5427 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5428 alu
.op
= ALU_OP2_SUB_INT
;
5434 alu
.src
[0].sel
= tmp0
;
5435 alu
.src
[0].chan
= 0;
5436 alu
.src
[1].sel
= tmp0
;
5437 alu
.src
[1].chan
= 3;
5440 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5443 /* 8. tmp1.y = tmp0.x + tmp0.w */
5444 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5445 alu
.op
= ALU_OP2_ADD_INT
;
5451 alu
.src
[0].sel
= tmp0
;
5452 alu
.src
[0].chan
= 0;
5453 alu
.src
[1].sel
= tmp0
;
5454 alu
.src
[1].chan
= 3;
5457 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5460 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5461 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5462 alu
.op
= ALU_OP3_CNDE_INT
;
5469 alu
.src
[0].sel
= tmp0
;
5470 alu
.src
[0].chan
= 1;
5471 alu
.src
[1].sel
= tmp1
;
5472 alu
.src
[1].chan
= 1;
5473 alu
.src
[2].sel
= tmp1
;
5474 alu
.src
[2].chan
= 0;
5477 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5480 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5481 if (ctx
->bc
->chip_class
== CAYMAN
) {
5482 for (j
= 0 ; j
< 4; j
++) {
5483 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5484 alu
.op
= ALU_OP2_MULHI_UINT
;
5488 alu
.dst
.write
= (j
== 2);
5490 alu
.src
[0].sel
= tmp0
;
5491 alu
.src
[0].chan
= 0;
5494 alu
.src
[1].sel
= tmp2
;
5495 alu
.src
[1].chan
= 0;
5497 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5500 alu
.last
= (j
== 3);
5501 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5505 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5506 alu
.op
= ALU_OP2_MULHI_UINT
;
5512 alu
.src
[0].sel
= tmp0
;
5513 alu
.src
[0].chan
= 0;
5516 alu
.src
[1].sel
= tmp2
;
5517 alu
.src
[1].chan
= 0;
5519 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5523 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5527 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5528 if (ctx
->bc
->chip_class
== CAYMAN
) {
5529 for (j
= 0 ; j
< 4; j
++) {
5530 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5531 alu
.op
= ALU_OP2_MULLO_UINT
;
5535 alu
.dst
.write
= (j
== 1);
5538 alu
.src
[0].sel
= tmp2
;
5539 alu
.src
[0].chan
= 1;
5541 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5544 alu
.src
[1].sel
= tmp0
;
5545 alu
.src
[1].chan
= 2;
5547 alu
.last
= (j
== 3);
5548 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5552 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5553 alu
.op
= ALU_OP2_MULLO_UINT
;
5560 alu
.src
[0].sel
= tmp2
;
5561 alu
.src
[0].chan
= 1;
5563 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5566 alu
.src
[1].sel
= tmp0
;
5567 alu
.src
[1].chan
= 2;
5570 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5574 /* 12. tmp0.w = src1 - tmp0.y = r */
5575 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5576 alu
.op
= ALU_OP2_SUB_INT
;
5583 alu
.src
[0].sel
= tmp2
;
5584 alu
.src
[0].chan
= 0;
5586 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5589 alu
.src
[1].sel
= tmp0
;
5590 alu
.src
[1].chan
= 1;
5593 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5596 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5597 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5598 alu
.op
= ALU_OP2_SETGE_UINT
;
5604 alu
.src
[0].sel
= tmp0
;
5605 alu
.src
[0].chan
= 3;
5607 alu
.src
[1].sel
= tmp2
;
5608 alu
.src
[1].chan
= 1;
5610 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5614 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5617 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5618 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5619 alu
.op
= ALU_OP2_SETGE_UINT
;
5626 alu
.src
[0].sel
= tmp2
;
5627 alu
.src
[0].chan
= 0;
5629 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5632 alu
.src
[1].sel
= tmp0
;
5633 alu
.src
[1].chan
= 1;
5636 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5639 if (mod
) { /* UMOD */
5641 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5642 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5643 alu
.op
= ALU_OP2_SUB_INT
;
5649 alu
.src
[0].sel
= tmp0
;
5650 alu
.src
[0].chan
= 3;
5653 alu
.src
[1].sel
= tmp2
;
5654 alu
.src
[1].chan
= 1;
5656 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5660 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5663 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5664 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5665 alu
.op
= ALU_OP2_ADD_INT
;
5671 alu
.src
[0].sel
= tmp0
;
5672 alu
.src
[0].chan
= 3;
5674 alu
.src
[1].sel
= tmp2
;
5675 alu
.src
[1].chan
= 1;
5677 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5681 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5686 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5687 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5688 alu
.op
= ALU_OP2_ADD_INT
;
5694 alu
.src
[0].sel
= tmp0
;
5695 alu
.src
[0].chan
= 2;
5696 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
5699 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5702 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5703 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5704 alu
.op
= ALU_OP2_ADD_INT
;
5710 alu
.src
[0].sel
= tmp0
;
5711 alu
.src
[0].chan
= 2;
5712 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
5715 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5720 /* 17. tmp1.x = tmp1.x & tmp1.y */
5721 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5722 alu
.op
= ALU_OP2_AND_INT
;
5728 alu
.src
[0].sel
= tmp1
;
5729 alu
.src
[0].chan
= 0;
5730 alu
.src
[1].sel
= tmp1
;
5731 alu
.src
[1].chan
= 1;
5734 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5737 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5738 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5739 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5740 alu
.op
= ALU_OP3_CNDE_INT
;
5747 alu
.src
[0].sel
= tmp1
;
5748 alu
.src
[0].chan
= 0;
5749 alu
.src
[1].sel
= tmp0
;
5750 alu
.src
[1].chan
= mod
? 3 : 2;
5751 alu
.src
[2].sel
= tmp1
;
5752 alu
.src
[2].chan
= 2;
5755 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5758 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5759 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5760 alu
.op
= ALU_OP3_CNDE_INT
;
5768 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5771 alu
.src
[0].sel
= tmp1
;
5772 alu
.src
[0].chan
= 1;
5773 alu
.src
[1].sel
= tmp1
;
5774 alu
.src
[1].chan
= 3;
5775 alu
.src
[2].sel
= tmp0
;
5776 alu
.src
[2].chan
= 2;
5779 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5784 /* fix the sign of the result */
5788 /* tmp0.x = -tmp0.z */
5789 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5790 alu
.op
= ALU_OP2_SUB_INT
;
5796 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5797 alu
.src
[1].sel
= tmp0
;
5798 alu
.src
[1].chan
= 2;
5801 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5804 /* sign of the remainder is the same as the sign of src0 */
5805 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5806 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5807 alu
.op
= ALU_OP3_CNDGE_INT
;
5810 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5812 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5813 alu
.src
[1].sel
= tmp0
;
5814 alu
.src
[1].chan
= 2;
5815 alu
.src
[2].sel
= tmp0
;
5816 alu
.src
[2].chan
= 0;
5819 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5824 /* tmp0.x = -tmp0.z */
5825 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5826 alu
.op
= ALU_OP2_SUB_INT
;
5832 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5833 alu
.src
[1].sel
= tmp0
;
5834 alu
.src
[1].chan
= 2;
5837 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5840 /* fix the quotient sign (same as the sign of src0*src1) */
5841 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5842 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5843 alu
.op
= ALU_OP3_CNDGE_INT
;
5846 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5848 alu
.src
[0].sel
= tmp2
;
5849 alu
.src
[0].chan
= 2;
5850 alu
.src
[1].sel
= tmp0
;
5851 alu
.src
[1].chan
= 2;
5852 alu
.src
[2].sel
= tmp0
;
5853 alu
.src
[2].chan
= 0;
5856 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5864 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
5866 return tgsi_divmod(ctx
, 0, 0);
5869 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
5871 return tgsi_divmod(ctx
, 1, 0);
5874 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
5876 return tgsi_divmod(ctx
, 0, 1);
5879 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
5881 return tgsi_divmod(ctx
, 1, 1);
5885 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
5887 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5888 struct r600_bytecode_alu alu
;
5890 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5891 int last_inst
= tgsi_last_instruction(write_mask
);
5893 for (i
= 0; i
< 4; i
++) {
5894 if (!(write_mask
& (1<<i
)))
5897 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5898 alu
.op
= ALU_OP1_TRUNC
;
5900 alu
.dst
.sel
= ctx
->temp_reg
;
5904 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5907 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5912 for (i
= 0; i
< 4; i
++) {
5913 if (!(write_mask
& (1<<i
)))
5916 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5917 alu
.op
= ctx
->inst_info
->op
;
5919 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5921 alu
.src
[0].sel
= ctx
->temp_reg
;
5922 alu
.src
[0].chan
= i
;
5924 if (i
== last_inst
|| alu
.op
== ALU_OP1_FLT_TO_UINT
)
5926 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5934 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
5936 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5937 struct r600_bytecode_alu alu
;
5939 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5940 int last_inst
= tgsi_last_instruction(write_mask
);
5943 for (i
= 0; i
< 4; i
++) {
5944 if (!(write_mask
& (1<<i
)))
5947 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5948 alu
.op
= ALU_OP2_SUB_INT
;
5950 alu
.dst
.sel
= ctx
->temp_reg
;
5954 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5955 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5959 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5964 /* dst = (src >= 0 ? src : tmp) */
5965 for (i
= 0; i
< 4; i
++) {
5966 if (!(write_mask
& (1<<i
)))
5969 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5970 alu
.op
= ALU_OP3_CNDGE_INT
;
5974 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5976 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5977 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5978 alu
.src
[2].sel
= ctx
->temp_reg
;
5979 alu
.src
[2].chan
= i
;
5983 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5990 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
5992 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5993 struct r600_bytecode_alu alu
;
5995 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5996 int last_inst
= tgsi_last_instruction(write_mask
);
5998 /* tmp = (src >= 0 ? src : -1) */
5999 for (i
= 0; i
< 4; i
++) {
6000 if (!(write_mask
& (1<<i
)))
6003 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6004 alu
.op
= ALU_OP3_CNDGE_INT
;
6007 alu
.dst
.sel
= ctx
->temp_reg
;
6011 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6012 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6013 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
6017 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6022 /* dst = (tmp > 0 ? 1 : tmp) */
6023 for (i
= 0; i
< 4; i
++) {
6024 if (!(write_mask
& (1<<i
)))
6027 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6028 alu
.op
= ALU_OP3_CNDGT_INT
;
6032 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6034 alu
.src
[0].sel
= ctx
->temp_reg
;
6035 alu
.src
[0].chan
= i
;
6037 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
6039 alu
.src
[2].sel
= ctx
->temp_reg
;
6040 alu
.src
[2].chan
= i
;
6044 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6053 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
6055 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6056 struct r600_bytecode_alu alu
;
6059 /* tmp = (src > 0 ? 1 : src) */
6060 for (i
= 0; i
< 4; i
++) {
6061 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6062 alu
.op
= ALU_OP3_CNDGT
;
6065 alu
.dst
.sel
= ctx
->temp_reg
;
6068 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6069 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6070 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6074 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6079 /* dst = (-tmp > 0 ? -1 : tmp) */
6080 for (i
= 0; i
< 4; i
++) {
6081 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6082 alu
.op
= ALU_OP3_CNDGT
;
6084 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6086 alu
.src
[0].sel
= ctx
->temp_reg
;
6087 alu
.src
[0].chan
= i
;
6090 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6093 alu
.src
[2].sel
= ctx
->temp_reg
;
6094 alu
.src
[2].chan
= i
;
6098 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6105 static int tgsi_bfi(struct r600_shader_ctx
*ctx
)
6107 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6108 struct r600_bytecode_alu alu
;
6111 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6112 int last_inst
= tgsi_last_instruction(write_mask
);
6114 t1
= r600_get_temp(ctx
);
6116 for (i
= 0; i
< 4; i
++) {
6117 if (!(write_mask
& (1<<i
)))
6120 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6121 alu
.op
= ALU_OP2_SETGE_INT
;
6122 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6123 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
6124 alu
.src
[1].value
= 32;
6125 alu
.dst
.sel
= ctx
->temp_reg
;
6128 alu
.last
= i
== last_inst
;
6129 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6134 for (i
= 0; i
< 4; i
++) {
6135 if (!(write_mask
& (1<<i
)))
6138 /* create mask tmp */
6139 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6140 alu
.op
= ALU_OP2_BFM_INT
;
6144 alu
.last
= i
== last_inst
;
6146 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6147 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6149 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6154 t2
= r600_get_temp(ctx
);
6156 for (i
= 0; i
< 4; i
++) {
6157 if (!(write_mask
& (1<<i
)))
6160 /* shift insert left */
6161 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6162 alu
.op
= ALU_OP2_LSHL_INT
;
6166 alu
.last
= i
== last_inst
;
6168 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
6169 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6171 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6176 for (i
= 0; i
< 4; i
++) {
6177 if (!(write_mask
& (1<<i
)))
6180 /* actual bitfield insert */
6181 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6182 alu
.op
= ALU_OP3_BFI_INT
;
6184 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6187 alu
.last
= i
== last_inst
;
6189 alu
.src
[0].sel
= t1
;
6190 alu
.src
[0].chan
= i
;
6191 alu
.src
[1].sel
= t2
;
6192 alu
.src
[1].chan
= i
;
6193 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6195 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6200 for (i
= 0; i
< 4; i
++) {
6201 if (!(write_mask
& (1<<i
)))
6203 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6204 alu
.op
= ALU_OP3_CNDE_INT
;
6206 alu
.src
[0].sel
= ctx
->temp_reg
;
6207 alu
.src
[0].chan
= i
;
6208 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
6210 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6212 alu
.src
[1].sel
= alu
.dst
.sel
;
6213 alu
.src
[1].chan
= i
;
6215 alu
.last
= i
== last_inst
;
6216 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6223 static int tgsi_msb(struct r600_shader_ctx
*ctx
)
6225 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6226 struct r600_bytecode_alu alu
;
6229 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6230 int last_inst
= tgsi_last_instruction(write_mask
);
6232 assert(ctx
->inst_info
->op
== ALU_OP1_FFBH_INT
||
6233 ctx
->inst_info
->op
== ALU_OP1_FFBH_UINT
);
6237 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6238 for (i
= 0; i
< 4; i
++) {
6239 if (!(write_mask
& (1<<i
)))
6242 /* t1 = FFBH_INT / FFBH_UINT */
6243 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6244 alu
.op
= ctx
->inst_info
->op
;
6248 alu
.last
= i
== last_inst
;
6250 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6252 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6257 t2
= r600_get_temp(ctx
);
6259 for (i
= 0; i
< 4; i
++) {
6260 if (!(write_mask
& (1<<i
)))
6264 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6265 alu
.op
= ALU_OP2_SUB_INT
;
6269 alu
.last
= i
== last_inst
;
6271 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
6272 alu
.src
[0].value
= 31;
6273 alu
.src
[1].sel
= t1
;
6274 alu
.src
[1].chan
= i
;
6276 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6281 for (i
= 0; i
< 4; i
++) {
6282 if (!(write_mask
& (1<<i
)))
6285 /* result = t1 >= 0 ? t2 : t1 */
6286 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6287 alu
.op
= ALU_OP3_CNDGE_INT
;
6289 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6292 alu
.last
= i
== last_inst
;
6294 alu
.src
[0].sel
= t1
;
6295 alu
.src
[0].chan
= i
;
6296 alu
.src
[1].sel
= t2
;
6297 alu
.src
[1].chan
= i
;
6298 alu
.src
[2].sel
= t1
;
6299 alu
.src
[2].chan
= i
;
6301 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6309 static int tgsi_interp_egcm(struct r600_shader_ctx
*ctx
)
6311 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6312 struct r600_bytecode_alu alu
;
6313 int r
, i
= 0, k
, interp_gpr
, interp_base_chan
, tmp
, lasti
;
6315 const int input
= inst
->Src
[0].Register
.Index
+ ctx
->shader
->nsys_inputs
;
6317 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
6319 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6320 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6321 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6322 location
= TGSI_INTERPOLATE_LOC_CENTER
; /* sample offset will be added explicitly */
6325 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
6328 k
= eg_get_interpolator_index(ctx
->shader
->input
[input
].interpolate
, location
);
6331 interp_gpr
= ctx
->eg_interpolators
[k
].ij_index
/ 2;
6332 interp_base_chan
= 2 * (ctx
->eg_interpolators
[k
].ij_index
% 2);
6334 /* NOTE: currently offset is not perspective correct */
6335 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6336 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6337 int sample_gpr
= -1;
6338 int gradientsH
, gradientsV
;
6339 struct r600_bytecode_tex tex
;
6341 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6342 sample_gpr
= load_sample_position(ctx
, &ctx
->src
[1], ctx
->src
[1].swizzle
[0]);
6345 gradientsH
= r600_get_temp(ctx
);
6346 gradientsV
= r600_get_temp(ctx
);
6347 for (i
= 0; i
< 2; i
++) {
6348 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
6349 tex
.op
= i
== 0 ? FETCH_OP_GET_GRADIENTS_H
: FETCH_OP_GET_GRADIENTS_V
;
6350 tex
.src_gpr
= interp_gpr
;
6351 tex
.src_sel_x
= interp_base_chan
+ 0;
6352 tex
.src_sel_y
= interp_base_chan
+ 1;
6355 tex
.dst_gpr
= i
== 0 ? gradientsH
: gradientsV
;
6360 tex
.inst_mod
= 1; // Use per pixel gradient calculation
6362 tex
.resource_id
= tex
.sampler_id
;
6363 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
6368 for (i
= 0; i
< 2; i
++) {
6369 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6370 alu
.op
= ALU_OP3_MULADD
;
6372 alu
.src
[0].sel
= gradientsH
;
6373 alu
.src
[0].chan
= i
;
6374 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6375 alu
.src
[1].sel
= sample_gpr
;
6376 alu
.src
[1].chan
= 2;
6379 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 0);
6381 alu
.src
[2].sel
= interp_gpr
;
6382 alu
.src
[2].chan
= interp_base_chan
+ i
;
6383 alu
.dst
.sel
= ctx
->temp_reg
;
6387 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6392 for (i
= 0; i
< 2; i
++) {
6393 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6394 alu
.op
= ALU_OP3_MULADD
;
6396 alu
.src
[0].sel
= gradientsV
;
6397 alu
.src
[0].chan
= i
;
6398 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6399 alu
.src
[1].sel
= sample_gpr
;
6400 alu
.src
[1].chan
= 3;
6403 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 1);
6405 alu
.src
[2].sel
= ctx
->temp_reg
;
6406 alu
.src
[2].chan
= i
;
6407 alu
.dst
.sel
= ctx
->temp_reg
;
6411 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6417 tmp
= r600_get_temp(ctx
);
6418 for (i
= 0; i
< 8; i
++) {
6419 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6420 alu
.op
= i
< 4 ? ALU_OP2_INTERP_ZW
: ALU_OP2_INTERP_XY
;
6423 if ((i
> 1 && i
< 6)) {
6429 alu
.dst
.chan
= i
% 4;
6431 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6432 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6433 alu
.src
[0].sel
= ctx
->temp_reg
;
6434 alu
.src
[0].chan
= 1 - (i
% 2);
6436 alu
.src
[0].sel
= interp_gpr
;
6437 alu
.src
[0].chan
= interp_base_chan
+ 1 - (i
% 2);
6439 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
6440 alu
.src
[1].chan
= 0;
6442 alu
.last
= i
% 4 == 3;
6443 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
6445 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6450 // INTERP can't swizzle dst
6451 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6452 for (i
= 0; i
<= lasti
; i
++) {
6453 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6456 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6457 alu
.op
= ALU_OP1_MOV
;
6458 alu
.src
[0].sel
= tmp
;
6459 alu
.src
[0].chan
= ctx
->src
[0].swizzle
[i
];
6460 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6462 alu
.last
= i
== lasti
;
6463 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6472 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
6474 struct r600_bytecode_alu alu
;
6477 for (i
= 0; i
< 4; i
++) {
6478 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6479 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
6480 alu
.op
= ALU_OP0_NOP
;
6483 alu
.op
= ALU_OP1_MOV
;
6484 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6485 alu
.src
[0].sel
= ctx
->temp_reg
;
6486 alu
.src
[0].chan
= i
;
6491 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6498 static int tgsi_make_src_for_op3(struct r600_shader_ctx
*ctx
,
6499 unsigned temp
, int chan
,
6500 struct r600_bytecode_alu_src
*bc_src
,
6501 const struct r600_shader_src
*shader_src
)
6503 struct r600_bytecode_alu alu
;
6506 r600_bytecode_src(bc_src
, shader_src
, chan
);
6508 /* op3 operands don't support abs modifier */
6510 assert(temp
!=0); /* we actually need the extra register, make sure it is allocated. */
6511 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6512 alu
.op
= ALU_OP1_MOV
;
6514 alu
.dst
.chan
= chan
;
6517 alu
.src
[0] = *bc_src
;
6518 alu
.last
= true; // sufficient?
6519 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6523 memset(bc_src
, 0, sizeof(*bc_src
));
6525 bc_src
->chan
= chan
;
6530 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
6532 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6533 struct r600_bytecode_alu alu
;
6535 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6537 unsigned op
= ctx
->inst_info
->op
;
6539 if (op
== ALU_OP3_MULADD_IEEE
&&
6540 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6541 op
= ALU_OP3_MULADD
;
6543 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6545 if (ctx
->src
[j
].abs
)
6546 temp_regs
[j
] = r600_get_temp(ctx
);
6548 for (i
= 0; i
< lasti
+ 1; i
++) {
6549 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6552 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6554 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6555 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[j
], i
, &alu
.src
[j
], &ctx
->src
[j
]);
6560 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6567 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6574 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
6576 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6577 struct r600_bytecode_alu alu
;
6579 unsigned op
= ctx
->inst_info
->op
;
6580 if (op
== ALU_OP2_DOT4_IEEE
&&
6581 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6584 for (i
= 0; i
< 4; i
++) {
6585 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6587 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6588 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
6591 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6593 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
6594 /* handle some special cases */
6595 switch (inst
->Instruction
.Opcode
) {
6596 case TGSI_OPCODE_DP2
:
6598 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6599 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6602 case TGSI_OPCODE_DP3
:
6604 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6605 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6614 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6621 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
6624 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6625 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
6626 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
6627 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
6628 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
||
6629 (inst
->Src
[index
].Register
.File
== TGSI_FILE_INPUT
&& ctx
->type
== PIPE_SHADER_GEOMETRY
);
6632 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
6635 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6636 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
6639 static int do_vtx_fetch_inst(struct r600_shader_ctx
*ctx
, boolean src_requires_loading
)
6641 struct r600_bytecode_vtx vtx
;
6642 struct r600_bytecode_alu alu
;
6643 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6645 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6647 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6648 if (src_requires_loading
) {
6649 for (i
= 0; i
< 4; i
++) {
6650 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6651 alu
.op
= ALU_OP1_MOV
;
6652 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6653 alu
.dst
.sel
= ctx
->temp_reg
;
6658 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6662 src_gpr
= ctx
->temp_reg
;
6665 memset(&vtx
, 0, sizeof(vtx
));
6666 vtx
.op
= FETCH_OP_VFETCH
;
6667 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
6668 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
6669 vtx
.src_gpr
= src_gpr
;
6670 vtx
.mega_fetch_count
= 16;
6671 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
6672 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
6673 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
6674 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
6675 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
6676 vtx
.use_const_fields
= 1;
6678 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
6681 if (ctx
->bc
->chip_class
>= EVERGREEN
)
6684 for (i
= 0; i
< 4; i
++) {
6685 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6686 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6689 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6690 alu
.op
= ALU_OP2_AND_INT
;
6693 alu
.dst
.sel
= vtx
.dst_gpr
;
6696 alu
.src
[0].sel
= vtx
.dst_gpr
;
6697 alu
.src
[0].chan
= i
;
6699 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6700 alu
.src
[1].sel
+= (id
* 2);
6701 alu
.src
[1].chan
= i
% 4;
6702 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6706 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6711 if (inst
->Dst
[0].Register
.WriteMask
& 3) {
6712 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6713 alu
.op
= ALU_OP2_OR_INT
;
6716 alu
.dst
.sel
= vtx
.dst_gpr
;
6719 alu
.src
[0].sel
= vtx
.dst_gpr
;
6720 alu
.src
[0].chan
= 3;
6722 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
+ (id
* 2) + 1;
6723 alu
.src
[1].chan
= 0;
6724 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6727 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6734 static int r600_do_buffer_txq(struct r600_shader_ctx
*ctx
)
6736 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6737 struct r600_bytecode_alu alu
;
6739 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6741 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6742 alu
.op
= ALU_OP1_MOV
;
6743 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6744 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
6745 /* channel 0 or 2 of each word */
6746 alu
.src
[0].sel
+= (id
/ 2);
6747 alu
.src
[0].chan
= (id
% 2) * 2;
6749 /* r600 we have them at channel 2 of the second dword */
6750 alu
.src
[0].sel
+= (id
* 2) + 1;
6751 alu
.src
[0].chan
= 1;
6753 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6754 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
6756 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6762 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
6764 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6765 struct r600_bytecode_tex tex
;
6766 struct r600_bytecode_alu alu
;
6770 bool read_compressed_msaa
= ctx
->bc
->has_compressed_msaa_texturing
&&
6771 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6772 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
6773 inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
6775 bool txf_add_offsets
= inst
->Texture
.NumOffsets
&&
6776 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6777 inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
;
6779 /* Texture fetch instructions can only use gprs as source.
6780 * Also they cannot negate the source or take the absolute value */
6781 const boolean src_requires_loading
= (inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQS
&&
6782 tgsi_tex_src_requires_loading(ctx
, 0)) ||
6783 read_compressed_msaa
|| txf_add_offsets
;
6785 boolean src_loaded
= FALSE
;
6786 unsigned sampler_src_reg
= 1;
6787 int8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
6788 boolean has_txq_cube_array_z
= false;
6789 unsigned sampler_index_mode
;
6791 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
6792 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6793 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)))
6794 if (inst
->Dst
[0].Register
.WriteMask
& 4) {
6795 ctx
->shader
->has_txq_cube_array_z_comp
= true;
6796 has_txq_cube_array_z
= true;
6799 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
6800 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
6801 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
||
6802 inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
)
6803 sampler_src_reg
= 2;
6805 /* TGSI moves the sampler to src reg 3 for TXD */
6806 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
)
6807 sampler_src_reg
= 3;
6809 sampler_index_mode
= inst
->Src
[sampler_src_reg
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6811 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6813 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
6814 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
6815 ctx
->shader
->uses_tex_buffers
= true;
6816 return r600_do_buffer_txq(ctx
);
6818 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
6819 if (ctx
->bc
->chip_class
< EVERGREEN
)
6820 ctx
->shader
->uses_tex_buffers
= true;
6821 return do_vtx_fetch_inst(ctx
, src_requires_loading
);
6825 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
6827 /* Add perspective divide */
6828 if (ctx
->bc
->chip_class
== CAYMAN
) {
6830 for (i
= 0; i
< 3; i
++) {
6831 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6832 alu
.op
= ALU_OP1_RECIP_IEEE
;
6833 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6835 alu
.dst
.sel
= ctx
->temp_reg
;
6841 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6848 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6849 alu
.op
= ALU_OP1_RECIP_IEEE
;
6850 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6852 alu
.dst
.sel
= ctx
->temp_reg
;
6853 alu
.dst
.chan
= out_chan
;
6856 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6861 for (i
= 0; i
< 3; i
++) {
6862 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6863 alu
.op
= ALU_OP2_MUL
;
6864 alu
.src
[0].sel
= ctx
->temp_reg
;
6865 alu
.src
[0].chan
= out_chan
;
6866 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6867 alu
.dst
.sel
= ctx
->temp_reg
;
6870 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6874 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6875 alu
.op
= ALU_OP1_MOV
;
6876 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
6877 alu
.src
[0].chan
= 0;
6878 alu
.dst
.sel
= ctx
->temp_reg
;
6882 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6886 src_gpr
= ctx
->temp_reg
;
6890 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
6891 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6892 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
6893 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
6894 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
) {
6896 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
6897 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
6899 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6900 for (i
= 0; i
< 4; i
++) {
6901 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6902 alu
.op
= ALU_OP2_CUBE
;
6903 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
6904 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
6905 alu
.dst
.sel
= ctx
->temp_reg
;
6910 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6915 /* tmp1.z = RCP_e(|tmp1.z|) */
6916 if (ctx
->bc
->chip_class
== CAYMAN
) {
6917 for (i
= 0; i
< 3; i
++) {
6918 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6919 alu
.op
= ALU_OP1_RECIP_IEEE
;
6920 alu
.src
[0].sel
= ctx
->temp_reg
;
6921 alu
.src
[0].chan
= 2;
6923 alu
.dst
.sel
= ctx
->temp_reg
;
6929 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6934 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6935 alu
.op
= ALU_OP1_RECIP_IEEE
;
6936 alu
.src
[0].sel
= ctx
->temp_reg
;
6937 alu
.src
[0].chan
= 2;
6939 alu
.dst
.sel
= ctx
->temp_reg
;
6943 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6948 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6949 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6950 * muladd has no writemask, have to use another temp
6952 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6953 alu
.op
= ALU_OP3_MULADD
;
6956 alu
.src
[0].sel
= ctx
->temp_reg
;
6957 alu
.src
[0].chan
= 0;
6958 alu
.src
[1].sel
= ctx
->temp_reg
;
6959 alu
.src
[1].chan
= 2;
6961 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
6962 alu
.src
[2].chan
= 0;
6963 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
6965 alu
.dst
.sel
= ctx
->temp_reg
;
6969 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6973 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6974 alu
.op
= ALU_OP3_MULADD
;
6977 alu
.src
[0].sel
= ctx
->temp_reg
;
6978 alu
.src
[0].chan
= 1;
6979 alu
.src
[1].sel
= ctx
->temp_reg
;
6980 alu
.src
[1].chan
= 2;
6982 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
6983 alu
.src
[2].chan
= 0;
6984 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
6986 alu
.dst
.sel
= ctx
->temp_reg
;
6991 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6994 /* write initial compare value into Z component
6995 - W src 0 for shadow cube
6996 - X src 1 for shadow cube array */
6997 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
6998 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
6999 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7000 alu
.op
= ALU_OP1_MOV
;
7001 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
7002 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7004 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7005 alu
.dst
.sel
= ctx
->temp_reg
;
7009 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7014 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7015 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7016 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7017 int mytmp
= r600_get_temp(ctx
);
7018 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7019 alu
.op
= ALU_OP1_MOV
;
7020 alu
.src
[0].sel
= ctx
->temp_reg
;
7021 alu
.src
[0].chan
= 3;
7022 alu
.dst
.sel
= mytmp
;
7026 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7030 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7031 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7032 alu
.op
= ALU_OP3_MULADD
;
7034 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7035 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7036 alu
.src
[1].chan
= 0;
7037 alu
.src
[1].value
= u_bitcast_f2u(8.0f
);
7038 alu
.src
[2].sel
= mytmp
;
7039 alu
.src
[2].chan
= 0;
7040 alu
.dst
.sel
= ctx
->temp_reg
;
7044 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7047 } else if (ctx
->bc
->chip_class
< EVERGREEN
) {
7048 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7049 tex
.op
= FETCH_OP_SET_CUBEMAP_INDEX
;
7050 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7051 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7052 tex
.src_gpr
= r600_get_temp(ctx
);
7057 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7058 tex
.coord_type_x
= 1;
7059 tex
.coord_type_y
= 1;
7060 tex
.coord_type_z
= 1;
7061 tex
.coord_type_w
= 1;
7062 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7063 alu
.op
= ALU_OP1_MOV
;
7064 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7065 alu
.dst
.sel
= tex
.src_gpr
;
7069 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7073 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7080 /* for cube forms of lod and bias we need to route things */
7081 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
7082 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
7083 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7084 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
7085 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7086 alu
.op
= ALU_OP1_MOV
;
7087 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7088 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
)
7089 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7091 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7092 alu
.dst
.sel
= ctx
->temp_reg
;
7096 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7102 src_gpr
= ctx
->temp_reg
;
7105 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
7106 int temp_h
= 0, temp_v
= 0;
7109 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7110 if (src_loaded
== TRUE
)
7114 for (i
= start_val
; i
< 3; i
++) {
7115 int treg
= r600_get_temp(ctx
);
7124 for (j
= 0; j
< 4; j
++) {
7125 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7126 alu
.op
= ALU_OP1_MOV
;
7127 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
7133 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7138 for (i
= 1; i
< 3; i
++) {
7139 /* set gradients h/v */
7140 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7141 tex
.op
= (i
== 1) ? FETCH_OP_SET_GRADIENTS_H
:
7142 FETCH_OP_SET_GRADIENTS_V
;
7143 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7144 tex
.sampler_index_mode
= sampler_index_mode
;
7145 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7146 tex
.resource_index_mode
= sampler_index_mode
;
7148 tex
.src_gpr
= (i
== 1) ? temp_h
: temp_v
;
7154 tex
.dst_gpr
= r600_get_temp(ctx
); /* just to avoid confusing the asm scheduler */
7155 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7156 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
7157 tex
.coord_type_x
= 1;
7158 tex
.coord_type_y
= 1;
7159 tex
.coord_type_z
= 1;
7160 tex
.coord_type_w
= 1;
7162 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7168 if (src_requires_loading
&& !src_loaded
) {
7169 for (i
= 0; i
< 4; i
++) {
7170 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7171 alu
.op
= ALU_OP1_MOV
;
7172 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7173 alu
.dst
.sel
= ctx
->temp_reg
;
7178 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7183 src_gpr
= ctx
->temp_reg
;
7186 /* get offset values */
7187 if (inst
->Texture
.NumOffsets
) {
7188 assert(inst
->Texture
.NumOffsets
== 1);
7190 /* The texture offset feature doesn't work with the TXF instruction
7191 * and must be emulated by adding the offset to the texture coordinates. */
7192 if (txf_add_offsets
) {
7193 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
7195 switch (inst
->Texture
.Texture
) {
7196 case TGSI_TEXTURE_3D
:
7197 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7198 alu
.op
= ALU_OP2_ADD_INT
;
7199 alu
.src
[0].sel
= src_gpr
;
7200 alu
.src
[0].chan
= 2;
7201 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7202 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleZ
];
7203 alu
.dst
.sel
= src_gpr
;
7207 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7212 case TGSI_TEXTURE_2D
:
7213 case TGSI_TEXTURE_SHADOW2D
:
7214 case TGSI_TEXTURE_RECT
:
7215 case TGSI_TEXTURE_SHADOWRECT
:
7216 case TGSI_TEXTURE_2D_ARRAY
:
7217 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7218 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7219 alu
.op
= ALU_OP2_ADD_INT
;
7220 alu
.src
[0].sel
= src_gpr
;
7221 alu
.src
[0].chan
= 1;
7222 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7223 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleY
];
7224 alu
.dst
.sel
= src_gpr
;
7228 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7233 case TGSI_TEXTURE_1D
:
7234 case TGSI_TEXTURE_SHADOW1D
:
7235 case TGSI_TEXTURE_1D_ARRAY
:
7236 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7237 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7238 alu
.op
= ALU_OP2_ADD_INT
;
7239 alu
.src
[0].sel
= src_gpr
;
7240 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7241 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleX
];
7242 alu
.dst
.sel
= src_gpr
;
7245 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7249 /* texture offsets do not apply to other texture targets */
7252 switch (inst
->Texture
.Texture
) {
7253 case TGSI_TEXTURE_3D
:
7254 offset_z
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
7256 case TGSI_TEXTURE_2D
:
7257 case TGSI_TEXTURE_SHADOW2D
:
7258 case TGSI_TEXTURE_RECT
:
7259 case TGSI_TEXTURE_SHADOWRECT
:
7260 case TGSI_TEXTURE_2D_ARRAY
:
7261 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7262 offset_y
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
7264 case TGSI_TEXTURE_1D
:
7265 case TGSI_TEXTURE_SHADOW1D
:
7266 case TGSI_TEXTURE_1D_ARRAY
:
7267 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7268 offset_x
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
7273 /* Obtain the sample index for reading a compressed MSAA color texture.
7274 * To read the FMASK, we use the ldfptr instruction, which tells us
7275 * where the samples are stored.
7276 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7277 * which is the identity mapping. Each nibble says which physical sample
7278 * should be fetched to get that sample.
7280 * Assume src.z contains the sample index. It should be modified like this:
7281 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7282 * Then fetch the texel with src.
7284 if (read_compressed_msaa
) {
7285 unsigned sample_chan
= 3;
7286 unsigned temp
= r600_get_temp(ctx
);
7289 /* temp.w = ldfptr() */
7290 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7291 tex
.op
= FETCH_OP_LD
;
7292 tex
.inst_mod
= 1; /* to indicate this is ldfptr */
7293 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7294 tex
.sampler_index_mode
= sampler_index_mode
;
7295 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7296 tex
.resource_index_mode
= sampler_index_mode
;
7297 tex
.src_gpr
= src_gpr
;
7299 tex
.dst_sel_x
= 7; /* mask out these components */
7302 tex
.dst_sel_w
= 0; /* store X */
7307 tex
.offset_x
= offset_x
;
7308 tex
.offset_y
= offset_y
;
7309 tex
.offset_z
= offset_z
;
7310 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7314 /* temp.x = sample_index*4 */
7315 if (ctx
->bc
->chip_class
== CAYMAN
) {
7316 for (i
= 0 ; i
< 4; i
++) {
7317 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7318 alu
.op
= ALU_OP2_MULLO_INT
;
7319 alu
.src
[0].sel
= src_gpr
;
7320 alu
.src
[0].chan
= sample_chan
;
7321 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7322 alu
.src
[1].value
= 4;
7325 alu
.dst
.write
= i
== 0;
7328 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7333 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7334 alu
.op
= ALU_OP2_MULLO_INT
;
7335 alu
.src
[0].sel
= src_gpr
;
7336 alu
.src
[0].chan
= sample_chan
;
7337 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7338 alu
.src
[1].value
= 4;
7343 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7348 /* sample_index = temp.w >> temp.x */
7349 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7350 alu
.op
= ALU_OP2_LSHR_INT
;
7351 alu
.src
[0].sel
= temp
;
7352 alu
.src
[0].chan
= 3;
7353 alu
.src
[1].sel
= temp
;
7354 alu
.src
[1].chan
= 0;
7355 alu
.dst
.sel
= src_gpr
;
7356 alu
.dst
.chan
= sample_chan
;
7359 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7363 /* sample_index & 0xF */
7364 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7365 alu
.op
= ALU_OP2_AND_INT
;
7366 alu
.src
[0].sel
= src_gpr
;
7367 alu
.src
[0].chan
= sample_chan
;
7368 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7369 alu
.src
[1].value
= 0xF;
7370 alu
.dst
.sel
= src_gpr
;
7371 alu
.dst
.chan
= sample_chan
;
7374 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7378 /* visualize the FMASK */
7379 for (i
= 0; i
< 4; i
++) {
7380 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7381 alu
.op
= ALU_OP1_INT_TO_FLT
;
7382 alu
.src
[0].sel
= src_gpr
;
7383 alu
.src
[0].chan
= sample_chan
;
7384 alu
.dst
.sel
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7388 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7396 /* does this shader want a num layers from TXQ for a cube array? */
7397 if (has_txq_cube_array_z
) {
7398 int id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7400 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7401 alu
.op
= ALU_OP1_MOV
;
7403 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
7404 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7405 /* channel 1 or 3 of each word */
7406 alu
.src
[0].sel
+= (id
/ 2);
7407 alu
.src
[0].chan
= ((id
% 2) * 2) + 1;
7409 /* r600 we have them at channel 2 of the second dword */
7410 alu
.src
[0].sel
+= (id
* 2) + 1;
7411 alu
.src
[0].chan
= 2;
7413 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
7414 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
7416 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7419 /* disable writemask from texture instruction */
7420 inst
->Dst
[0].Register
.WriteMask
&= ~4;
7423 opcode
= ctx
->inst_info
->op
;
7424 if (opcode
== FETCH_OP_GATHER4
&&
7425 inst
->TexOffsets
[0].File
!= TGSI_FILE_NULL
&&
7426 inst
->TexOffsets
[0].File
!= TGSI_FILE_IMMEDIATE
) {
7427 opcode
= FETCH_OP_GATHER4_O
;
7429 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7430 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7431 encoded in the instruction are ignored. */
7432 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7433 tex
.op
= FETCH_OP_SET_TEXTURE_OFFSETS
;
7434 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7435 tex
.sampler_index_mode
= sampler_index_mode
;
7436 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7437 tex
.resource_index_mode
= sampler_index_mode
;
7439 tex
.src_gpr
= ctx
->file_offset
[inst
->TexOffsets
[0].File
] + inst
->TexOffsets
[0].Index
;
7440 tex
.src_sel_x
= inst
->TexOffsets
[0].SwizzleX
;
7441 tex
.src_sel_y
= inst
->TexOffsets
[0].SwizzleY
;
7442 tex
.src_sel_z
= inst
->TexOffsets
[0].SwizzleZ
;
7450 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7455 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7456 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7457 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7458 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7459 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
7460 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7461 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7463 case FETCH_OP_SAMPLE
:
7464 opcode
= FETCH_OP_SAMPLE_C
;
7466 case FETCH_OP_SAMPLE_L
:
7467 opcode
= FETCH_OP_SAMPLE_C_L
;
7469 case FETCH_OP_SAMPLE_LB
:
7470 opcode
= FETCH_OP_SAMPLE_C_LB
;
7472 case FETCH_OP_SAMPLE_G
:
7473 opcode
= FETCH_OP_SAMPLE_C_G
;
7475 /* Texture gather variants */
7476 case FETCH_OP_GATHER4
:
7477 opcode
= FETCH_OP_GATHER4_C
;
7479 case FETCH_OP_GATHER4_O
:
7480 opcode
= FETCH_OP_GATHER4_C_O
;
7485 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7488 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7489 tex
.sampler_index_mode
= sampler_index_mode
;
7490 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7491 tex
.resource_index_mode
= sampler_index_mode
;
7492 tex
.src_gpr
= src_gpr
;
7493 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7495 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DDX_FINE
||
7496 inst
->Instruction
.Opcode
== TGSI_OPCODE_DDY_FINE
) {
7497 tex
.inst_mod
= 1; /* per pixel gradient calculation instead of per 2x2 quad */
7500 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
) {
7501 int8_t texture_component_select
= ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
];
7502 tex
.inst_mod
= texture_component_select
;
7504 if (ctx
->bc
->chip_class
== CAYMAN
) {
7505 /* GATHER4 result order is different from TGSI TG4 */
7506 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 0 : 7;
7507 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 1 : 7;
7508 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 2 : 7;
7509 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7511 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7512 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7513 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7514 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7517 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LODQ
) {
7518 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7519 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7523 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7530 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7531 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7532 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7533 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7537 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7542 } else if (src_loaded
) {
7548 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
7549 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
7550 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
7551 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
7552 tex
.src_rel
= ctx
->src
[0].rel
;
7555 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7556 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7557 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7558 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7562 tex
.src_sel_w
= 2; /* route Z compare or Lod value into W */
7565 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
7566 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
7567 tex
.coord_type_x
= 1;
7568 tex
.coord_type_y
= 1;
7570 tex
.coord_type_z
= 1;
7571 tex
.coord_type_w
= 1;
7573 tex
.offset_x
= offset_x
;
7574 tex
.offset_y
= offset_y
;
7575 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
&&
7576 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7577 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)) {
7581 tex
.offset_z
= offset_z
;
7584 /* Put the depth for comparison in W.
7585 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7586 * Some instructions expect the depth in Z. */
7587 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7588 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7589 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7590 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
7591 opcode
!= FETCH_OP_SAMPLE_C_L
&&
7592 opcode
!= FETCH_OP_SAMPLE_C_LB
) {
7593 tex
.src_sel_w
= tex
.src_sel_z
;
7596 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
7597 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
7598 if (opcode
== FETCH_OP_SAMPLE_C_L
||
7599 opcode
== FETCH_OP_SAMPLE_C_LB
) {
7600 /* the array index is read from Y */
7601 tex
.coord_type_y
= 0;
7603 /* the array index is read from Z */
7604 tex
.coord_type_z
= 0;
7605 tex
.src_sel_z
= tex
.src_sel_y
;
7607 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7608 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7609 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7610 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7611 (ctx
->bc
->chip_class
>= EVERGREEN
)))
7612 /* the array index is read from Z */
7613 tex
.coord_type_z
= 0;
7615 /* mask unused source components */
7616 if (opcode
== FETCH_OP_SAMPLE
|| opcode
== FETCH_OP_GATHER4
) {
7617 switch (inst
->Texture
.Texture
) {
7618 case TGSI_TEXTURE_2D
:
7619 case TGSI_TEXTURE_RECT
:
7623 case TGSI_TEXTURE_1D_ARRAY
:
7627 case TGSI_TEXTURE_1D
:
7635 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7639 /* add shadow ambient support - gallium doesn't do it yet */
7643 static int find_hw_atomic_counter(struct r600_shader_ctx
*ctx
,
7644 struct tgsi_full_src_register
*src
)
7648 if (src
->Register
.Indirect
) {
7649 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7650 if (src
->Indirect
.ArrayID
== ctx
->shader
->atomics
[i
].array_id
)
7651 return ctx
->shader
->atomics
[i
].hw_idx
;
7654 uint32_t index
= src
->Register
.Index
;
7655 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7656 if (ctx
->shader
->atomics
[i
].buffer_id
!= src
->Dimension
.Index
)
7658 if (index
> ctx
->shader
->atomics
[i
].end
)
7660 if (index
< ctx
->shader
->atomics
[i
].start
)
7662 uint32_t offset
= (index
- ctx
->shader
->atomics
[i
].start
);
7663 return ctx
->shader
->atomics
[i
].hw_idx
+ offset
;
7671 static int tgsi_load_gds(struct r600_shader_ctx
*ctx
)
7673 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7675 struct r600_bytecode_gds gds
;
7677 int uav_index_mode
= 0;
7679 uav_id
= find_hw_atomic_counter(ctx
, &inst
->Src
[0]);
7681 if (inst
->Src
[0].Register
.Indirect
)
7684 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
7685 gds
.op
= FETCH_OP_GDS_READ_RET
;
7686 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7687 gds
.uav_id
= uav_id
;
7688 gds
.uav_index_mode
= uav_index_mode
;
7689 gds
.src_gpr
= ctx
->temp_reg
;
7697 gds
.src_gpr2
= ctx
->temp_reg
;
7698 gds
.alloc_consume
= 1;
7699 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
7703 ctx
->bc
->cf_last
->vpm
= 1;
7707 static int tgsi_load(struct r600_shader_ctx
*ctx
)
7709 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7710 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
7711 return tgsi_load_gds(ctx
);
7715 static int get_gds_op(int opcode
)
7718 case TGSI_OPCODE_ATOMUADD
:
7719 return FETCH_OP_GDS_ADD_RET
;
7720 case TGSI_OPCODE_ATOMAND
:
7721 return FETCH_OP_GDS_AND_RET
;
7722 case TGSI_OPCODE_ATOMOR
:
7723 return FETCH_OP_GDS_OR_RET
;
7724 case TGSI_OPCODE_ATOMXOR
:
7725 return FETCH_OP_GDS_XOR_RET
;
7726 case TGSI_OPCODE_ATOMUMIN
:
7727 return FETCH_OP_GDS_MIN_UINT_RET
;
7728 case TGSI_OPCODE_ATOMUMAX
:
7729 return FETCH_OP_GDS_MAX_UINT_RET
;
7730 case TGSI_OPCODE_ATOMXCHG
:
7731 return FETCH_OP_GDS_XCHG_RET
;
7732 case TGSI_OPCODE_ATOMCAS
:
7733 return FETCH_OP_GDS_CMP_XCHG_RET
;
7739 static int tgsi_atomic_op_gds(struct r600_shader_ctx
*ctx
)
7741 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7742 struct r600_bytecode_gds gds
;
7743 struct r600_bytecode_alu alu
;
7744 int gds_op
= get_gds_op(inst
->Instruction
.Opcode
);
7747 int uav_index_mode
= 0;
7750 fprintf(stderr
, "unknown GDS op for opcode %d\n", inst
->Instruction
.Opcode
);
7754 uav_id
= find_hw_atomic_counter(ctx
, &inst
->Src
[0]);
7756 if (inst
->Src
[0].Register
.Indirect
)
7759 if (inst
->Src
[2].Register
.File
== TGSI_FILE_IMMEDIATE
) {
7760 int value
= (ctx
->literals
[4 * inst
->Src
[2].Register
.Index
+ inst
->Src
[2].Register
.SwizzleX
]);
7761 int abs_value
= abs(value
);
7762 if (abs_value
!= value
&& gds_op
== FETCH_OP_GDS_ADD_RET
)
7763 gds_op
= FETCH_OP_GDS_SUB_RET
;
7764 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7765 alu
.op
= ALU_OP1_MOV
;
7766 alu
.dst
.sel
= ctx
->temp_reg
;
7768 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
7769 alu
.src
[0].value
= abs_value
;
7772 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7776 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7777 alu
.op
= ALU_OP1_MOV
;
7778 alu
.dst
.sel
= ctx
->temp_reg
;
7780 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
7783 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7788 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
7790 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7791 gds
.uav_id
= uav_id
;
7792 gds
.uav_index_mode
= uav_index_mode
;
7793 gds
.src_gpr
= ctx
->temp_reg
;
7794 gds
.src_gpr2
= ctx
->temp_reg
;
7802 gds
.alloc_consume
= 1;
7803 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
7806 ctx
->bc
->cf_last
->vpm
= 1;
7810 static int tgsi_atomic_op(struct r600_shader_ctx
*ctx
)
7812 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7813 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
7814 return tgsi_atomic_op_gds(ctx
);
7818 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
7820 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7821 struct r600_bytecode_alu alu
;
7822 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7823 unsigned i
, temp_regs
[2];
7826 /* optimize if it's just an equal balance */
7827 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
7828 for (i
= 0; i
< lasti
+ 1; i
++) {
7829 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7832 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7833 alu
.op
= ALU_OP2_ADD
;
7834 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
7835 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7837 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7842 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7850 for (i
= 0; i
< lasti
+ 1; i
++) {
7851 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7854 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7855 alu
.op
= ALU_OP2_ADD
;
7856 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
7857 alu
.src
[0].chan
= 0;
7858 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
7859 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
7860 alu
.dst
.sel
= ctx
->temp_reg
;
7866 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7871 /* (1 - src0) * src2 */
7872 for (i
= 0; i
< lasti
+ 1; i
++) {
7873 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7876 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7877 alu
.op
= ALU_OP2_MUL
;
7878 alu
.src
[0].sel
= ctx
->temp_reg
;
7879 alu
.src
[0].chan
= i
;
7880 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7881 alu
.dst
.sel
= ctx
->temp_reg
;
7887 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7892 /* src0 * src1 + (1 - src0) * src2 */
7893 if (ctx
->src
[0].abs
)
7894 temp_regs
[0] = r600_get_temp(ctx
);
7897 if (ctx
->src
[1].abs
)
7898 temp_regs
[1] = r600_get_temp(ctx
);
7902 for (i
= 0; i
< lasti
+ 1; i
++) {
7903 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7906 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7907 alu
.op
= ALU_OP3_MULADD
;
7909 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
7912 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[1], &ctx
->src
[1]);
7915 alu
.src
[2].sel
= ctx
->temp_reg
;
7916 alu
.src
[2].chan
= i
;
7918 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7923 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7930 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
7932 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7933 struct r600_bytecode_alu alu
;
7935 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7939 if (ctx
->src
[0].abs
&& ctx
->src
[0].neg
) {
7941 ctx
->src
[0].abs
= 0;
7942 ctx
->src
[0].neg
= 0;
7947 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
7949 if (ctx
->src
[j
].abs
)
7950 temp_regs
[j
] = r600_get_temp(ctx
);
7953 for (i
= 0; i
< lasti
+ 1; i
++) {
7954 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7957 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7959 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
7962 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[2], i
, &alu
.src
[1], &ctx
->src
[2]);
7965 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[2], &ctx
->src
[1]);
7968 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
7974 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7981 static int tgsi_ucmp(struct r600_shader_ctx
*ctx
)
7983 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7984 struct r600_bytecode_alu alu
;
7986 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
7988 for (i
= 0; i
< lasti
+ 1; i
++) {
7989 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
7992 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7993 alu
.op
= ALU_OP3_CNDE_INT
;
7994 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7995 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
7996 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
7997 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8003 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8010 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
8012 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8013 struct r600_bytecode_alu alu
;
8017 /* result.x = 2^floor(src); */
8018 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8019 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8021 alu
.op
= ALU_OP1_FLOOR
;
8022 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8024 alu
.dst
.sel
= ctx
->temp_reg
;
8028 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8032 if (ctx
->bc
->chip_class
== CAYMAN
) {
8033 for (i
= 0; i
< 3; i
++) {
8034 alu
.op
= ALU_OP1_EXP_IEEE
;
8035 alu
.src
[0].sel
= ctx
->temp_reg
;
8036 alu
.src
[0].chan
= 0;
8038 alu
.dst
.sel
= ctx
->temp_reg
;
8040 alu
.dst
.write
= i
== 0;
8042 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8047 alu
.op
= ALU_OP1_EXP_IEEE
;
8048 alu
.src
[0].sel
= ctx
->temp_reg
;
8049 alu
.src
[0].chan
= 0;
8051 alu
.dst
.sel
= ctx
->temp_reg
;
8055 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8061 /* result.y = tmp - floor(tmp); */
8062 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8063 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8065 alu
.op
= ALU_OP1_FRACT
;
8066 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8068 alu
.dst
.sel
= ctx
->temp_reg
;
8070 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8079 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8084 /* result.z = RoughApprox2ToX(tmp);*/
8085 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
8086 if (ctx
->bc
->chip_class
== CAYMAN
) {
8087 for (i
= 0; i
< 3; i
++) {
8088 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8089 alu
.op
= ALU_OP1_EXP_IEEE
;
8090 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8092 alu
.dst
.sel
= ctx
->temp_reg
;
8099 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8104 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8105 alu
.op
= ALU_OP1_EXP_IEEE
;
8106 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8108 alu
.dst
.sel
= ctx
->temp_reg
;
8114 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8120 /* result.w = 1.0;*/
8121 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
8122 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8124 alu
.op
= ALU_OP1_MOV
;
8125 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8126 alu
.src
[0].chan
= 0;
8128 alu
.dst
.sel
= ctx
->temp_reg
;
8132 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8136 return tgsi_helper_copy(ctx
, inst
);
8139 static int tgsi_log(struct r600_shader_ctx
*ctx
)
8141 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8142 struct r600_bytecode_alu alu
;
8146 /* result.x = floor(log2(|src|)); */
8147 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8148 if (ctx
->bc
->chip_class
== CAYMAN
) {
8149 for (i
= 0; i
< 3; i
++) {
8150 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8152 alu
.op
= ALU_OP1_LOG_IEEE
;
8153 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8154 r600_bytecode_src_set_abs(&alu
.src
[0]);
8156 alu
.dst
.sel
= ctx
->temp_reg
;
8162 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8168 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8170 alu
.op
= ALU_OP1_LOG_IEEE
;
8171 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8172 r600_bytecode_src_set_abs(&alu
.src
[0]);
8174 alu
.dst
.sel
= ctx
->temp_reg
;
8178 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8183 alu
.op
= ALU_OP1_FLOOR
;
8184 alu
.src
[0].sel
= ctx
->temp_reg
;
8185 alu
.src
[0].chan
= 0;
8187 alu
.dst
.sel
= ctx
->temp_reg
;
8192 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8197 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8198 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8200 if (ctx
->bc
->chip_class
== CAYMAN
) {
8201 for (i
= 0; i
< 3; i
++) {
8202 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8204 alu
.op
= ALU_OP1_LOG_IEEE
;
8205 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8206 r600_bytecode_src_set_abs(&alu
.src
[0]);
8208 alu
.dst
.sel
= ctx
->temp_reg
;
8215 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8220 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8222 alu
.op
= ALU_OP1_LOG_IEEE
;
8223 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8224 r600_bytecode_src_set_abs(&alu
.src
[0]);
8226 alu
.dst
.sel
= ctx
->temp_reg
;
8231 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8236 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8238 alu
.op
= ALU_OP1_FLOOR
;
8239 alu
.src
[0].sel
= ctx
->temp_reg
;
8240 alu
.src
[0].chan
= 1;
8242 alu
.dst
.sel
= ctx
->temp_reg
;
8247 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8251 if (ctx
->bc
->chip_class
== CAYMAN
) {
8252 for (i
= 0; i
< 3; i
++) {
8253 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8254 alu
.op
= ALU_OP1_EXP_IEEE
;
8255 alu
.src
[0].sel
= ctx
->temp_reg
;
8256 alu
.src
[0].chan
= 1;
8258 alu
.dst
.sel
= ctx
->temp_reg
;
8265 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8270 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8271 alu
.op
= ALU_OP1_EXP_IEEE
;
8272 alu
.src
[0].sel
= ctx
->temp_reg
;
8273 alu
.src
[0].chan
= 1;
8275 alu
.dst
.sel
= ctx
->temp_reg
;
8280 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8285 if (ctx
->bc
->chip_class
== CAYMAN
) {
8286 for (i
= 0; i
< 3; i
++) {
8287 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8288 alu
.op
= ALU_OP1_RECIP_IEEE
;
8289 alu
.src
[0].sel
= ctx
->temp_reg
;
8290 alu
.src
[0].chan
= 1;
8292 alu
.dst
.sel
= ctx
->temp_reg
;
8299 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8304 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8305 alu
.op
= ALU_OP1_RECIP_IEEE
;
8306 alu
.src
[0].sel
= ctx
->temp_reg
;
8307 alu
.src
[0].chan
= 1;
8309 alu
.dst
.sel
= ctx
->temp_reg
;
8314 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8319 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8321 alu
.op
= ALU_OP2_MUL
;
8323 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8324 r600_bytecode_src_set_abs(&alu
.src
[0]);
8326 alu
.src
[1].sel
= ctx
->temp_reg
;
8327 alu
.src
[1].chan
= 1;
8329 alu
.dst
.sel
= ctx
->temp_reg
;
8334 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8339 /* result.z = log2(|src|);*/
8340 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
8341 if (ctx
->bc
->chip_class
== CAYMAN
) {
8342 for (i
= 0; i
< 3; i
++) {
8343 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8345 alu
.op
= ALU_OP1_LOG_IEEE
;
8346 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8347 r600_bytecode_src_set_abs(&alu
.src
[0]);
8349 alu
.dst
.sel
= ctx
->temp_reg
;
8356 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8361 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8363 alu
.op
= ALU_OP1_LOG_IEEE
;
8364 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8365 r600_bytecode_src_set_abs(&alu
.src
[0]);
8367 alu
.dst
.sel
= ctx
->temp_reg
;
8372 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8378 /* result.w = 1.0; */
8379 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
8380 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8382 alu
.op
= ALU_OP1_MOV
;
8383 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8384 alu
.src
[0].chan
= 0;
8386 alu
.dst
.sel
= ctx
->temp_reg
;
8391 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8396 return tgsi_helper_copy(ctx
, inst
);
8399 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
8401 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8402 struct r600_bytecode_alu alu
;
8404 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8405 unsigned reg
= get_address_file_reg(ctx
, inst
->Dst
[0].Register
.Index
);
8407 assert(inst
->Dst
[0].Register
.Index
< 3);
8408 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8410 switch (inst
->Instruction
.Opcode
) {
8411 case TGSI_OPCODE_ARL
:
8412 alu
.op
= ALU_OP1_FLT_TO_INT_FLOOR
;
8414 case TGSI_OPCODE_ARR
:
8415 alu
.op
= ALU_OP1_FLT_TO_INT
;
8417 case TGSI_OPCODE_UARL
:
8418 alu
.op
= ALU_OP1_MOV
;
8425 for (i
= 0; i
<= lasti
; ++i
) {
8426 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8428 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8429 alu
.last
= i
== lasti
;
8433 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8438 if (inst
->Dst
[0].Register
.Index
> 0)
8439 ctx
->bc
->index_loaded
[inst
->Dst
[0].Register
.Index
- 1] = 0;
8441 ctx
->bc
->ar_loaded
= 0;
8445 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
8447 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8448 struct r600_bytecode_alu alu
;
8450 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8452 switch (inst
->Instruction
.Opcode
) {
8453 case TGSI_OPCODE_ARL
:
8454 memset(&alu
, 0, sizeof(alu
));
8455 alu
.op
= ALU_OP1_FLOOR
;
8456 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8458 for (i
= 0; i
<= lasti
; ++i
) {
8459 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8461 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8462 alu
.last
= i
== lasti
;
8463 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8468 memset(&alu
, 0, sizeof(alu
));
8469 alu
.op
= ALU_OP1_FLT_TO_INT
;
8470 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
8471 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8473 /* FLT_TO_INT is trans-only on r600/r700 */
8475 for (i
= 0; i
<= lasti
; ++i
) {
8477 alu
.src
[0].chan
= i
;
8478 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8482 case TGSI_OPCODE_ARR
:
8483 memset(&alu
, 0, sizeof(alu
));
8484 alu
.op
= ALU_OP1_FLT_TO_INT
;
8485 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8487 /* FLT_TO_INT is trans-only on r600/r700 */
8489 for (i
= 0; i
<= lasti
; ++i
) {
8490 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8492 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8493 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8498 case TGSI_OPCODE_UARL
:
8499 memset(&alu
, 0, sizeof(alu
));
8500 alu
.op
= ALU_OP1_MOV
;
8501 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
8503 for (i
= 0; i
<= lasti
; ++i
) {
8504 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
8506 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8507 alu
.last
= i
== lasti
;
8508 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
8518 ctx
->bc
->ar_loaded
= 0;
8522 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
8524 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8525 struct r600_bytecode_alu alu
;
8528 for (i
= 0; i
< 4; i
++) {
8529 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8531 alu
.op
= ALU_OP2_MUL
;
8532 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8534 if (i
== 0 || i
== 3) {
8535 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8537 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8540 if (i
== 0 || i
== 2) {
8541 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
8543 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
8547 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8554 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
, int alu_type
)
8556 struct r600_bytecode_alu alu
;
8559 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8561 alu
.execute_mask
= 1;
8562 alu
.update_pred
= 1;
8564 alu
.dst
.sel
= ctx
->temp_reg
;
8568 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8569 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
8570 alu
.src
[1].chan
= 0;
8574 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, alu_type
);
8580 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
8582 unsigned force_pop
= ctx
->bc
->force_add_cf
;
8586 if (ctx
->bc
->cf_last
) {
8587 if (ctx
->bc
->cf_last
->op
== CF_OP_ALU
)
8589 else if (ctx
->bc
->cf_last
->op
== CF_OP_ALU_POP_AFTER
)
8594 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP_AFTER
;
8595 ctx
->bc
->force_add_cf
= 1;
8596 } else if (alu_pop
== 2) {
8597 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP2_AFTER
;
8598 ctx
->bc
->force_add_cf
= 1;
8605 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
8606 ctx
->bc
->cf_last
->pop_count
= pops
;
8607 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8613 static inline void callstack_update_max_depth(struct r600_shader_ctx
*ctx
,
8616 struct r600_stack_info
*stack
= &ctx
->bc
->stack
;
8617 unsigned elements
, entries
;
8619 unsigned entry_size
= stack
->entry_size
;
8621 elements
= (stack
->loop
+ stack
->push_wqm
) * entry_size
;
8622 elements
+= stack
->push
;
8624 switch (ctx
->bc
->chip_class
) {
8627 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8628 * the stack must be reserved to hold the current active/continue
8630 if (reason
== FC_PUSH_VPM
) {
8636 /* r9xx: any stack operation on empty stack consumes 2 additional
8641 /* FIXME: do the two elements added above cover the cases for the
8645 /* r8xx+: 2 extra elements are not always required, but one extra
8646 * element must be added for each of the following cases:
8647 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8649 * (Currently we don't use ALU_ELSE_AFTER.)
8650 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8651 * PUSH instruction executed.
8653 * NOTE: it seems we also need to reserve additional element in some
8654 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8655 * then STACK_SIZE should be 2 instead of 1 */
8656 if (reason
== FC_PUSH_VPM
) {
8666 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8667 * for all chips, so we use 4 in the final formula, not the real entry_size
8671 entries
= (elements
+ (entry_size
- 1)) / entry_size
;
8673 if (entries
> stack
->max_entries
)
8674 stack
->max_entries
= entries
;
8677 static inline void callstack_pop(struct r600_shader_ctx
*ctx
, unsigned reason
)
8681 --ctx
->bc
->stack
.push
;
8682 assert(ctx
->bc
->stack
.push
>= 0);
8685 --ctx
->bc
->stack
.push_wqm
;
8686 assert(ctx
->bc
->stack
.push_wqm
>= 0);
8689 --ctx
->bc
->stack
.loop
;
8690 assert(ctx
->bc
->stack
.loop
>= 0);
8698 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
)
8702 ++ctx
->bc
->stack
.push
;
8705 ++ctx
->bc
->stack
.push_wqm
;
8707 ++ctx
->bc
->stack
.loop
;
8713 callstack_update_max_depth(ctx
, reason
);
8716 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
8718 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
8720 sp
->mid
= realloc((void *)sp
->mid
,
8721 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
8722 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
8726 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
8728 assert(ctx
->bc
->fc_sp
< ARRAY_SIZE(ctx
->bc
->fc_stack
));
8729 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
8730 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
8734 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
8736 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1];
8746 static int emit_return(struct r600_shader_ctx
*ctx
)
8748 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_RETURN
));
8752 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
8755 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
));
8756 ctx
->bc
->cf_last
->pop_count
= pops
;
8757 /* XXX work out offset */
8761 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
8766 static void emit_testflag(struct r600_shader_ctx
*ctx
)
8771 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
8774 emit_jump_to_offset(ctx
, 1, 4);
8775 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
8776 pops(ctx
, ifidx
+ 1);
8780 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
8784 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8785 ctx
->bc
->cf_last
->pop_count
= 1;
8787 fc_set_mid(ctx
, fc_sp
);
8793 static int emit_if(struct r600_shader_ctx
*ctx
, int opcode
)
8795 int alu_type
= CF_OP_ALU_PUSH_BEFORE
;
8797 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8798 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8799 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8800 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8801 if (ctx
->bc
->chip_class
== CAYMAN
&& ctx
->bc
->stack
.loop
> 1) {
8802 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_PUSH
);
8803 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8804 alu_type
= CF_OP_ALU
;
8807 emit_logic_pred(ctx
, opcode
, alu_type
);
8809 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
8811 fc_pushlevel(ctx
, FC_IF
);
8813 callstack_push(ctx
, FC_PUSH_VPM
);
8817 static int tgsi_if(struct r600_shader_ctx
*ctx
)
8819 return emit_if(ctx
, ALU_OP2_PRED_SETNE
);
8822 static int tgsi_uif(struct r600_shader_ctx
*ctx
)
8824 return emit_if(ctx
, ALU_OP2_PRED_SETNE_INT
);
8827 static int tgsi_else(struct r600_shader_ctx
*ctx
)
8829 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_ELSE
);
8830 ctx
->bc
->cf_last
->pop_count
= 1;
8832 fc_set_mid(ctx
, ctx
->bc
->fc_sp
- 1);
8833 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
8837 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
8840 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_IF
) {
8841 R600_ERR("if/endif unbalanced in shader\n");
8845 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
== NULL
) {
8846 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8847 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->pop_count
= 1;
8849 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8853 callstack_pop(ctx
, FC_PUSH_VPM
);
8857 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
8859 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8860 * limited to 4096 iterations, like the other LOOP_* instructions. */
8861 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_START_DX10
);
8863 fc_pushlevel(ctx
, FC_LOOP
);
8865 /* check stack depth */
8866 callstack_push(ctx
, FC_LOOP
);
8870 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
8874 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_END
);
8876 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_LOOP
) {
8877 R600_ERR("loop/endloop in shader code are not paired.\n");
8881 /* fixup loop pointers - from r600isa
8882 LOOP END points to CF after LOOP START,
8883 LOOP START point to CF after LOOP END
8884 BRK/CONT point to LOOP END CF
8886 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->id
+ 2;
8888 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
8890 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].num_mid
; i
++) {
8891 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
8893 /* XXX add LOOPRET support */
8895 callstack_pop(ctx
, FC_LOOP
);
8899 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
8903 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
8905 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
- 1].type
)
8910 R600_ERR("Break not inside loop/endloop pair\n");
8914 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8916 fc_set_mid(ctx
, fscp
- 1);
8921 static int tgsi_gs_emit(struct r600_shader_ctx
*ctx
)
8923 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8924 int stream
= ctx
->literals
[inst
->Src
[0].Register
.Index
* 4 + inst
->Src
[0].Register
.SwizzleX
];
8927 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
8928 emit_gs_ring_writes(ctx
, ctx
->gs_stream_output_info
, stream
, TRUE
);
8930 r
= r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
8932 ctx
->bc
->cf_last
->count
= stream
; // Count field for CUT/EMIT_VERTEX indicates which stream
8933 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
8934 return emit_inc_ring_offset(ctx
, stream
, TRUE
);
8939 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
8941 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8942 struct r600_bytecode_alu alu
;
8944 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8947 for (i
= 0; i
< lasti
+ 1; i
++) {
8948 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8951 if (ctx
->bc
->chip_class
== CAYMAN
) {
8952 for (j
= 0 ; j
< 4; j
++) {
8953 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8955 alu
.op
= ALU_OP2_MULLO_UINT
;
8956 for (k
= 0; k
< inst
->Instruction
.NumSrcRegs
; k
++) {
8957 r600_bytecode_src(&alu
.src
[k
], &ctx
->src
[k
], i
);
8960 alu
.dst
.sel
= ctx
->temp_reg
;
8961 alu
.dst
.write
= (j
== i
);
8964 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8969 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8972 alu
.dst
.sel
= ctx
->temp_reg
;
8975 alu
.op
= ALU_OP2_MULLO_UINT
;
8976 for (j
= 0; j
< 2; j
++) {
8977 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
8981 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8988 for (i
= 0; i
< lasti
+ 1; i
++) {
8989 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8992 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8993 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8995 alu
.op
= ALU_OP2_ADD_INT
;
8997 alu
.src
[0].sel
= ctx
->temp_reg
;
8998 alu
.src
[0].chan
= i
;
9000 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
9004 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9011 static int tgsi_pk2h(struct r600_shader_ctx
*ctx
)
9013 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9014 struct r600_bytecode_alu alu
;
9016 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9018 /* temp.xy = f32_to_f16(src) */
9019 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9020 alu
.op
= ALU_OP1_FLT32_TO_FLT16
;
9022 alu
.dst
.sel
= ctx
->temp_reg
;
9024 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9025 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9029 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
9031 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9035 /* dst.x = temp.y * 0x10000 + temp.x */
9036 for (i
= 0; i
< lasti
+ 1; i
++) {
9037 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9040 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9041 alu
.op
= ALU_OP3_MULADD_UINT24
;
9043 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9044 alu
.last
= i
== lasti
;
9045 alu
.src
[0].sel
= ctx
->temp_reg
;
9046 alu
.src
[0].chan
= 1;
9047 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9048 alu
.src
[1].value
= 0x10000;
9049 alu
.src
[2].sel
= ctx
->temp_reg
;
9050 alu
.src
[2].chan
= 0;
9051 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9059 static int tgsi_up2h(struct r600_shader_ctx
*ctx
)
9061 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9062 struct r600_bytecode_alu alu
;
9064 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9066 /* temp.x = src.x */
9067 /* note: no need to mask out the high bits */
9068 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9069 alu
.op
= ALU_OP1_MOV
;
9071 alu
.dst
.sel
= ctx
->temp_reg
;
9073 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9074 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9078 /* temp.y = src.x >> 16 */
9079 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9080 alu
.op
= ALU_OP2_LSHR_INT
;
9082 alu
.dst
.sel
= ctx
->temp_reg
;
9084 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9085 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9086 alu
.src
[1].value
= 16;
9088 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9092 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9093 for (i
= 0; i
< lasti
+ 1; i
++) {
9094 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9096 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9097 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9098 alu
.op
= ALU_OP1_FLT16_TO_FLT32
;
9099 alu
.src
[0].sel
= ctx
->temp_reg
;
9100 alu
.src
[0].chan
= i
% 2;
9101 alu
.last
= i
== lasti
;
9102 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9110 static int tgsi_bfe(struct r600_shader_ctx
*ctx
)
9112 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9113 struct r600_bytecode_alu alu
;
9114 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9121 for (i
= 0; i
< lasti
+ 1; i
++) {
9122 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9123 alu
.op
= ALU_OP2_SETGE_INT
;
9124 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], i
);
9125 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9126 alu
.src
[1].value
= 32;
9127 alu
.dst
.sel
= ctx
->temp_reg
;
9132 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9137 for (i
= 0; i
< lasti
+ 1; i
++) {
9138 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9139 alu
.op
= ALU_OP3_CNDE_INT
;
9141 alu
.src
[0].sel
= ctx
->temp_reg
;
9142 alu
.src
[1].chan
= i
;
9144 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9145 alu
.src
[1].sel
= alu
.dst
.sel
;
9146 alu
.src
[1].chan
= i
;
9147 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
9151 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9159 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
9160 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9161 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9162 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9165 * For state trackers other than OpenGL, we'll want to use
9166 * _RECIP_IEEE instead.
9168 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
9170 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
9171 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9172 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9173 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9174 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9175 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9176 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9177 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9178 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9179 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9180 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9181 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9182 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9183 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9184 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9185 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9186 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
9187 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9188 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9189 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9190 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9191 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9192 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9193 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9194 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9195 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9196 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
9197 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9198 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9199 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9200 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
9201 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9202 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9203 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9204 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9205 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9206 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9207 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9208 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9209 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9210 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9211 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9212 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9213 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9214 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9215 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9216 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9217 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9218 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9219 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9220 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9221 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9222 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9223 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9224 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9225 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9226 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9227 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9228 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9229 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9230 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9231 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9232 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
9233 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9234 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9235 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9236 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9237 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9238 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9239 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9240 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9241 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9242 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9243 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9244 [TGSI_OPCODE_DDX_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9245 [TGSI_OPCODE_DDY_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9246 [81] = { ALU_OP0_NOP
, tgsi_unsupported
},
9247 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
9248 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9249 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9250 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9251 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9252 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2_trans
},
9253 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9254 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9255 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9256 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9257 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9258 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
9259 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9260 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9261 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9262 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9263 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9264 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9265 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9266 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9267 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9268 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9269 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9270 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9271 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9272 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9273 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9274 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9275 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9276 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9277 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9278 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
9279 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9280 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
9281 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9282 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9283 [TGSI_OPCODE_DFMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9284 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2_trans
},
9285 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9286 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9287 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9288 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9289 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9290 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2_trans
},
9291 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9292 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2_trans
},
9293 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9294 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9295 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9296 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9297 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9298 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9299 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9300 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9301 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9302 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9303 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2_trans
},
9304 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9305 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2_swap
},
9306 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9307 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9308 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9309 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9310 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9311 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9312 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9313 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9314 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9315 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9316 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9317 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9318 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9319 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9320 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9321 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9322 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_r600_arl
},
9323 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9324 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9325 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9326 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9327 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9328 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
9329 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
9330 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
9331 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9332 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9333 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9334 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9335 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9336 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9337 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9338 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9339 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9340 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9341 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9342 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9343 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9344 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9345 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9346 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9347 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_unsupported
},
9348 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_unsupported
},
9349 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_unsupported
},
9350 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_unsupported
},
9351 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9352 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_unsupported
},
9353 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_unsupported
},
9354 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_unsupported
},
9355 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_unsupported
},
9356 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_unsupported
},
9357 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9358 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9359 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9360 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9363 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
9364 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9365 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9366 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9367 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
9368 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, tgsi_rsq
},
9369 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9370 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9371 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9372 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9373 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9374 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9375 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9376 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9377 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9378 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9379 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9380 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9381 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9382 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
9383 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9384 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
9385 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9386 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9387 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9388 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9389 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9390 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9391 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9392 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9393 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9394 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
9395 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9396 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9397 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9398 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
9399 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9400 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9401 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9402 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9403 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
9404 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9405 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9406 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9407 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9408 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9409 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9410 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9411 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9412 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9413 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9414 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9415 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9416 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9417 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9418 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
9419 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9420 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9421 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9422 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9423 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9424 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9425 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9426 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9427 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9428 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9429 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9430 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
9431 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9432 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9433 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9434 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9435 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9436 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9437 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9438 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9439 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9440 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9441 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9442 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9443 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9444 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
9445 [83] = { ALU_OP0_NOP
, tgsi_unsupported
},
9446 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9447 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
9448 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9449 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9450 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
9451 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9452 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9453 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9454 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9455 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9456 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
9457 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9458 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9459 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9460 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9461 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9462 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9463 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9464 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9465 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9466 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9467 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9468 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9469 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9470 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9471 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9472 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9473 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9474 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9475 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9476 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
9477 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9478 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
9479 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9480 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9481 /* Refer below for TGSI_OPCODE_DFMA */
9482 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_f2i
},
9483 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9484 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9485 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9486 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9487 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9488 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
9489 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9490 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_f2i
},
9491 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
9492 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9493 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9494 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9495 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9496 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9497 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9498 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
9499 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9500 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9501 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
9502 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9503 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
9504 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9505 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9506 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9507 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9508 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9509 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9510 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9511 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9512 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9513 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9514 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9515 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9516 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9517 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9518 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9519 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9520 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
9521 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9522 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9523 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9524 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
9525 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9526 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
9527 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
9528 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
9529 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9530 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
9531 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
9532 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
9533 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
9534 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
9535 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
9536 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
9537 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
9538 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
9539 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
9540 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9541 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9542 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9543 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
9544 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
9545 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
9546 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
9547 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
9548 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
9549 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
9550 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
9551 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
9552 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
9553 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
9554 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
9555 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9556 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9557 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9558 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
9559 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
9560 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
9561 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
9562 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
9563 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
9564 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
9565 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
9566 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
9567 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
9568 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
9569 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
9570 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
9571 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
9572 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
9573 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9574 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9575 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
9576 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
9577 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
9578 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
9579 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
9580 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
9581 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
9582 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
9583 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9586 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
9587 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9588 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9589 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9590 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, cayman_emit_float_instr
},
9591 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
9592 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9593 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9594 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9595 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9596 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9597 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9598 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9599 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN
, tgsi_op2
},
9600 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX
, tgsi_op2
},
9601 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9602 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9603 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9604 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9605 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
9606 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, cayman_emit_float_instr
},
9607 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
9608 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9609 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9610 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9611 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9612 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9613 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9614 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, cayman_emit_float_instr
},
9615 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, cayman_emit_float_instr
},
9616 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, cayman_pow
},
9617 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
9618 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9619 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9620 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9621 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
9622 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, cayman_trig
},
9623 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9624 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9625 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9626 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
9627 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9628 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9629 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9630 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9631 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9632 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9633 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9634 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, cayman_trig
},
9635 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9636 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9637 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9638 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9639 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9640 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9641 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
9642 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9643 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9644 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9645 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9646 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9647 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
9648 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9649 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9650 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9651 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
9652 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
9653 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
9654 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9655 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
9656 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9657 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9658 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9659 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
9660 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
9661 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
9662 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
9663 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
9664 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
9665 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9666 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9667 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
9668 [83] = { ALU_OP0_NOP
, tgsi_unsupported
},
9669 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
9670 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2
},
9671 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
9672 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
9673 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
9674 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
9675 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
9676 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
9677 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
9678 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
9679 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
9680 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
9681 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9682 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
9683 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
9684 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
9685 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
9686 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9687 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
9688 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9689 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
9690 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
9691 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9692 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
9693 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9694 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
9695 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
9696 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
9697 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
9698 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9699 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
9700 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
9701 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
9702 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
9703 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
9704 /* Refer below for TGSI_OPCODE_DFMA */
9705 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2
},
9706 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
9707 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
9708 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
9709 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
9710 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
9711 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
9712 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
9713 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2
},
9714 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2
},
9715 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
9716 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
9717 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
9718 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
9719 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
9720 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
9721 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_INT
, cayman_mul_int_instr
},
9722 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
9723 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
9724 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
9725 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
9726 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
9727 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9728 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9729 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9730 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9731 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
9732 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
9733 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
9734 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
9735 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
9736 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
9737 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
9738 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
9739 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
9740 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
9741 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
9742 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
9743 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
9744 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
9745 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
9746 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
9747 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
9748 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9749 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
9750 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
9751 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
9752 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
9753 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
9754 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
9755 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
9756 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
9757 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
9758 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
9759 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
9760 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
9761 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
9762 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
9763 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9764 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
9765 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
9766 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, cayman_mul_int_instr
},
9767 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, cayman_mul_int_instr
},
9768 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
9769 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
9770 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
9771 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
9772 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
9773 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
9774 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
9775 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
9776 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
9777 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
9778 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9779 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9780 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
9781 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
9782 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
9783 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
9784 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
9785 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
9786 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
9787 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
9788 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
9789 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
9790 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
9791 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
9792 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
9793 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
9794 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
9795 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
9796 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9797 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
9798 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
9799 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
9800 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
9801 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
9802 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
9803 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
9804 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
9805 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
9806 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},