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r600: fix isoline tess factor component swapping.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198
199 /* Check if the bytecode has already been built. */
200 if (!shader->shader.bc.bytecode) {
201 r = r600_bytecode_build(&shader->shader.bc);
202 if (r) {
203 R600_ERR("building bytecode failed !\n");
204 goto error;
205 }
206 }
207
208 if (dump && !sb_disasm) {
209 fprintf(stderr, "--------------------------------------------------------------\n");
210 r600_bytecode_disasm(&shader->shader.bc);
211 fprintf(stderr, "______________________________________________________________\n");
212 } else if ((dump && sb_disasm) || use_sb) {
213 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
214 dump, use_sb);
215 if (r) {
216 R600_ERR("r600_sb_bytecode_process failed !\n");
217 goto error;
218 }
219 }
220
221 if (shader->gs_copy_shader) {
222 if (dump) {
223 // dump copy shader
224 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
225 &shader->gs_copy_shader->shader, dump, 0);
226 if (r)
227 goto error;
228 }
229
230 if ((r = store_shader(ctx, shader->gs_copy_shader)))
231 goto error;
232 }
233
234 /* Store the shader in a buffer. */
235 if ((r = store_shader(ctx, shader)))
236 goto error;
237
238 /* Build state. */
239 switch (shader->shader.processor_type) {
240 case PIPE_SHADER_TESS_CTRL:
241 evergreen_update_hs_state(ctx, shader);
242 break;
243 case PIPE_SHADER_TESS_EVAL:
244 if (key.tes.as_es)
245 evergreen_update_es_state(ctx, shader);
246 else
247 evergreen_update_vs_state(ctx, shader);
248 break;
249 case PIPE_SHADER_GEOMETRY:
250 if (rctx->b.chip_class >= EVERGREEN) {
251 evergreen_update_gs_state(ctx, shader);
252 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
253 } else {
254 r600_update_gs_state(ctx, shader);
255 r600_update_vs_state(ctx, shader->gs_copy_shader);
256 }
257 break;
258 case PIPE_SHADER_VERTEX:
259 export_shader = key.vs.as_es;
260 if (rctx->b.chip_class >= EVERGREEN) {
261 if (key.vs.as_ls)
262 evergreen_update_ls_state(ctx, shader);
263 else if (key.vs.as_es)
264 evergreen_update_es_state(ctx, shader);
265 else
266 evergreen_update_vs_state(ctx, shader);
267 } else {
268 if (export_shader)
269 r600_update_es_state(ctx, shader);
270 else
271 r600_update_vs_state(ctx, shader);
272 }
273 break;
274 case PIPE_SHADER_FRAGMENT:
275 if (rctx->b.chip_class >= EVERGREEN) {
276 evergreen_update_ps_state(ctx, shader);
277 } else {
278 r600_update_ps_state(ctx, shader);
279 }
280 break;
281 default:
282 r = -EINVAL;
283 goto error;
284 }
285 return 0;
286
287 error:
288 r600_pipe_shader_destroy(ctx, shader);
289 return r;
290 }
291
292 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
293 {
294 r600_resource_reference(&shader->bo, NULL);
295 r600_bytecode_clear(&shader->shader.bc);
296 r600_release_command_buffer(&shader->command_buffer);
297 }
298
299 /*
300 * tgsi -> r600 shader
301 */
302 struct r600_shader_tgsi_instruction;
303
304 struct r600_shader_src {
305 unsigned sel;
306 unsigned swizzle[4];
307 unsigned neg;
308 unsigned abs;
309 unsigned rel;
310 unsigned kc_bank;
311 boolean kc_rel; /* true if cache bank is indexed */
312 uint32_t value[4];
313 };
314
315 struct eg_interp {
316 boolean enabled;
317 unsigned ij_index;
318 };
319
320 struct r600_shader_ctx {
321 struct tgsi_shader_info info;
322 struct tgsi_parse_context parse;
323 const struct tgsi_token *tokens;
324 unsigned type;
325 unsigned file_offset[TGSI_FILE_COUNT];
326 unsigned temp_reg;
327 const struct r600_shader_tgsi_instruction *inst_info;
328 struct r600_bytecode *bc;
329 struct r600_shader *shader;
330 struct r600_shader_src src[4];
331 uint32_t *literals;
332 uint32_t nliterals;
333 uint32_t max_driver_temp_used;
334 /* needed for evergreen interpolation */
335 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
336 /* evergreen/cayman also store sample mask in face register */
337 int face_gpr;
338 /* sample id is .w component stored in fixed point position register */
339 int fixed_pt_position_gpr;
340 int colors_used;
341 boolean clip_vertex_write;
342 unsigned cv_output;
343 unsigned edgeflag_output;
344 int fragcoord_input;
345 int native_integers;
346 int next_ring_offset;
347 int gs_out_ring_offset;
348 int gs_next_vertex;
349 struct r600_shader *gs_for_vs;
350 int gs_export_gpr_tregs[4];
351 const struct pipe_stream_output_info *gs_stream_output_info;
352 unsigned enabled_stream_buffers_mask;
353 unsigned tess_input_info; /* temp with tess input offsets */
354 unsigned tess_output_info; /* temp with tess input offsets */
355 };
356
357 struct r600_shader_tgsi_instruction {
358 unsigned op;
359 int (*process)(struct r600_shader_ctx *ctx);
360 };
361
362 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
363 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
364 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
365 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
366 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
367 static int tgsi_else(struct r600_shader_ctx *ctx);
368 static int tgsi_endif(struct r600_shader_ctx *ctx);
369 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
370 static int tgsi_endloop(struct r600_shader_ctx *ctx);
371 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
372 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
373 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
374 unsigned int dst_reg);
375 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
376 const struct r600_shader_src *shader_src,
377 unsigned chan);
378 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
379 unsigned dst_reg);
380
381 static int tgsi_last_instruction(unsigned writemask)
382 {
383 int i, lasti = 0;
384
385 for (i = 0; i < 4; i++) {
386 if (writemask & (1 << i)) {
387 lasti = i;
388 }
389 }
390 return lasti;
391 }
392
393 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
394 {
395 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
396 unsigned j;
397
398 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
399 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
400 return -EINVAL;
401 }
402 #if 0
403 if (i->Instruction.Label) {
404 R600_ERR("label unsupported\n");
405 return -EINVAL;
406 }
407 #endif
408 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
409 if (i->Src[j].Register.Dimension) {
410 switch (i->Src[j].Register.File) {
411 case TGSI_FILE_CONSTANT:
412 case TGSI_FILE_HW_ATOMIC:
413 break;
414 case TGSI_FILE_INPUT:
415 if (ctx->type == PIPE_SHADER_GEOMETRY ||
416 ctx->type == PIPE_SHADER_TESS_CTRL ||
417 ctx->type == PIPE_SHADER_TESS_EVAL)
418 break;
419 case TGSI_FILE_OUTPUT:
420 if (ctx->type == PIPE_SHADER_TESS_CTRL)
421 break;
422 default:
423 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
424 i->Src[j].Register.File,
425 i->Src[j].Register.Dimension);
426 return -EINVAL;
427 }
428 }
429 }
430 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
431 if (i->Dst[j].Register.Dimension) {
432 if (ctx->type == PIPE_SHADER_TESS_CTRL)
433 continue;
434 R600_ERR("unsupported dst (dimension)\n");
435 return -EINVAL;
436 }
437 }
438 return 0;
439 }
440
441 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
442 {
443 if (interpolate == TGSI_INTERPOLATE_COLOR ||
444 interpolate == TGSI_INTERPOLATE_LINEAR ||
445 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
446 {
447 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
448 int loc;
449
450 switch(location) {
451 case TGSI_INTERPOLATE_LOC_CENTER:
452 loc = 1;
453 break;
454 case TGSI_INTERPOLATE_LOC_CENTROID:
455 loc = 2;
456 break;
457 case TGSI_INTERPOLATE_LOC_SAMPLE:
458 default:
459 loc = 0; break;
460 }
461
462 return is_linear * 3 + loc;
463 }
464
465 return -1;
466 }
467
468 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
469 int input)
470 {
471 int i = eg_get_interpolator_index(
472 ctx->shader->input[input].interpolate,
473 ctx->shader->input[input].interpolate_location);
474 assert(i >= 0);
475 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
476 }
477
478 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
479 {
480 int i, r;
481 struct r600_bytecode_alu alu;
482 int gpr = 0, base_chan = 0;
483 int ij_index = ctx->shader->input[input].ij_index;
484
485 /* work out gpr and base_chan from index */
486 gpr = ij_index / 2;
487 base_chan = (2 * (ij_index % 2)) + 1;
488
489 for (i = 0; i < 8; i++) {
490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
491
492 if (i < 4)
493 alu.op = ALU_OP2_INTERP_ZW;
494 else
495 alu.op = ALU_OP2_INTERP_XY;
496
497 if ((i > 1) && (i < 6)) {
498 alu.dst.sel = ctx->shader->input[input].gpr;
499 alu.dst.write = 1;
500 }
501
502 alu.dst.chan = i % 4;
503
504 alu.src[0].sel = gpr;
505 alu.src[0].chan = (base_chan - (i % 2));
506
507 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
508
509 alu.bank_swizzle_force = SQ_ALU_VEC_210;
510 if ((i % 4) == 3)
511 alu.last = 1;
512 r = r600_bytecode_add_alu(ctx->bc, &alu);
513 if (r)
514 return r;
515 }
516 return 0;
517 }
518
519 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
520 {
521 int i, r;
522 struct r600_bytecode_alu alu;
523
524 for (i = 0; i < 4; i++) {
525 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
526
527 alu.op = ALU_OP1_INTERP_LOAD_P0;
528
529 alu.dst.sel = ctx->shader->input[input].gpr;
530 alu.dst.write = 1;
531
532 alu.dst.chan = i;
533
534 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
535 alu.src[0].chan = i;
536
537 if (i == 3)
538 alu.last = 1;
539 r = r600_bytecode_add_alu(ctx->bc, &alu);
540 if (r)
541 return r;
542 }
543 return 0;
544 }
545
546 /*
547 * Special export handling in shaders
548 *
549 * shader export ARRAY_BASE for EXPORT_POS:
550 * 60 is position
551 * 61 is misc vector
552 * 62, 63 are clip distance vectors
553 *
554 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
555 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
556 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
557 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
558 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
559 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
560 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
561 * exclusive from render target index)
562 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
563 *
564 *
565 * shader export ARRAY_BASE for EXPORT_PIXEL:
566 * 0-7 CB targets
567 * 61 computed Z vector
568 *
569 * The use of the values exported in the computed Z vector are controlled
570 * by DB_SHADER_CONTROL:
571 * Z_EXPORT_ENABLE - Z as a float in RED
572 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
573 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
574 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
575 * DB_SOURCE_FORMAT - export control restrictions
576 *
577 */
578
579
580 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
581 static int r600_spi_sid(struct r600_shader_io * io)
582 {
583 int index, name = io->name;
584
585 /* These params are handled differently, they don't need
586 * semantic indices, so we'll use 0 for them.
587 */
588 if (name == TGSI_SEMANTIC_POSITION ||
589 name == TGSI_SEMANTIC_PSIZE ||
590 name == TGSI_SEMANTIC_EDGEFLAG ||
591 name == TGSI_SEMANTIC_FACE ||
592 name == TGSI_SEMANTIC_SAMPLEMASK)
593 index = 0;
594 else {
595 if (name == TGSI_SEMANTIC_GENERIC) {
596 /* For generic params simply use sid from tgsi */
597 index = io->sid;
598 } else {
599 /* For non-generic params - pack name and sid into 8 bits */
600 index = 0x80 | (name<<3) | (io->sid);
601 }
602
603 /* Make sure that all really used indices have nonzero value, so
604 * we can just compare it to 0 later instead of comparing the name
605 * with different values to detect special cases. */
606 index++;
607 }
608
609 return index;
610 };
611
612 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
613 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
614 {
615 switch (semantic_name) {
616 case TGSI_SEMANTIC_POSITION:
617 return 0;
618 case TGSI_SEMANTIC_PSIZE:
619 return 1;
620 case TGSI_SEMANTIC_CLIPDIST:
621 assert(index <= 1);
622 return 2 + index;
623 case TGSI_SEMANTIC_GENERIC:
624 if (index <= 63-4)
625 return 4 + index - 9;
626 else
627 /* same explanation as in the default statement,
628 * the only user hitting this is st/nine.
629 */
630 return 0;
631
632 /* patch indices are completely separate and thus start from 0 */
633 case TGSI_SEMANTIC_TESSOUTER:
634 return 0;
635 case TGSI_SEMANTIC_TESSINNER:
636 return 1;
637 case TGSI_SEMANTIC_PATCH:
638 return 2 + index;
639
640 default:
641 /* Don't fail here. The result of this function is only used
642 * for LS, TCS, TES, and GS, where legacy GL semantics can't
643 * occur, but this function is called for all vertex shaders
644 * before it's known whether LS will be compiled or not.
645 */
646 return 0;
647 }
648 }
649
650 /* turn input into interpolate on EG */
651 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
652 {
653 int r = 0;
654
655 if (ctx->shader->input[index].spi_sid) {
656 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
657 if (ctx->shader->input[index].interpolate > 0) {
658 evergreen_interp_assign_ij_index(ctx, index);
659 r = evergreen_interp_alu(ctx, index);
660 } else {
661 r = evergreen_interp_flat(ctx, index);
662 }
663 }
664 return r;
665 }
666
667 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
668 {
669 struct r600_bytecode_alu alu;
670 int i, r;
671 int gpr_front = ctx->shader->input[front].gpr;
672 int gpr_back = ctx->shader->input[back].gpr;
673
674 for (i = 0; i < 4; i++) {
675 memset(&alu, 0, sizeof(alu));
676 alu.op = ALU_OP3_CNDGT;
677 alu.is_op3 = 1;
678 alu.dst.write = 1;
679 alu.dst.sel = gpr_front;
680 alu.src[0].sel = ctx->face_gpr;
681 alu.src[1].sel = gpr_front;
682 alu.src[2].sel = gpr_back;
683
684 alu.dst.chan = i;
685 alu.src[1].chan = i;
686 alu.src[2].chan = i;
687 alu.last = (i==3);
688
689 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
690 return r;
691 }
692
693 return 0;
694 }
695
696 /* execute a single slot ALU calculation */
697 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
698 int dst_sel, int dst_chan,
699 int src0_sel, unsigned src0_chan_val,
700 int src1_sel, unsigned src1_chan_val)
701 {
702 struct r600_bytecode_alu alu;
703 int r, i;
704
705 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
706 for (i = 0; i < 4; i++) {
707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
708 alu.op = op;
709 alu.src[0].sel = src0_sel;
710 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
711 alu.src[0].value = src0_chan_val;
712 else
713 alu.src[0].chan = src0_chan_val;
714 alu.src[1].sel = src1_sel;
715 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
716 alu.src[1].value = src1_chan_val;
717 else
718 alu.src[1].chan = src1_chan_val;
719 alu.dst.sel = dst_sel;
720 alu.dst.chan = i;
721 alu.dst.write = i == dst_chan;
722 alu.last = (i == 3);
723 r = r600_bytecode_add_alu(ctx->bc, &alu);
724 if (r)
725 return r;
726 }
727 return 0;
728 }
729
730 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
731 alu.op = op;
732 alu.src[0].sel = src0_sel;
733 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
734 alu.src[0].value = src0_chan_val;
735 else
736 alu.src[0].chan = src0_chan_val;
737 alu.src[1].sel = src1_sel;
738 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
739 alu.src[1].value = src1_chan_val;
740 else
741 alu.src[1].chan = src1_chan_val;
742 alu.dst.sel = dst_sel;
743 alu.dst.chan = dst_chan;
744 alu.dst.write = 1;
745 alu.last = 1;
746 r = r600_bytecode_add_alu(ctx->bc, &alu);
747 if (r)
748 return r;
749 return 0;
750 }
751
752 /* execute a single slot ALU calculation */
753 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
754 int dst_sel, int dst_chan,
755 int src0_sel, unsigned src0_chan_val,
756 int src1_sel, unsigned src1_chan_val,
757 int src2_sel, unsigned src2_chan_val)
758 {
759 struct r600_bytecode_alu alu;
760 int r;
761
762 /* validate this for other ops */
763 assert(op == ALU_OP3_MULADD_UINT24);
764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
765 alu.op = op;
766 alu.src[0].sel = src0_sel;
767 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
768 alu.src[0].value = src0_chan_val;
769 else
770 alu.src[0].chan = src0_chan_val;
771 alu.src[1].sel = src1_sel;
772 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
773 alu.src[1].value = src1_chan_val;
774 else
775 alu.src[1].chan = src1_chan_val;
776 alu.src[2].sel = src2_sel;
777 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
778 alu.src[2].value = src2_chan_val;
779 else
780 alu.src[2].chan = src2_chan_val;
781 alu.dst.sel = dst_sel;
782 alu.dst.chan = dst_chan;
783 alu.is_op3 = 1;
784 alu.last = 1;
785 r = r600_bytecode_add_alu(ctx->bc, &alu);
786 if (r)
787 return r;
788 return 0;
789 }
790
791 /* put it in temp_reg.x */
792 static int get_lds_offset0(struct r600_shader_ctx *ctx,
793 int rel_patch_chan,
794 int temp_reg, bool is_patch_var)
795 {
796 int r;
797
798 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
799 /* ADD
800 Dimension - patch0_offset (input_vals.z),
801 Non-dim - patch0_data_offset (input_vals.w)
802 */
803 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
804 temp_reg, 0,
805 ctx->tess_output_info, 0,
806 0, rel_patch_chan,
807 ctx->tess_output_info, is_patch_var ? 3 : 2);
808 if (r)
809 return r;
810 return 0;
811 }
812
813 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
814 {
815 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
816 }
817
818 static int r600_get_temp(struct r600_shader_ctx *ctx)
819 {
820 return ctx->temp_reg + ctx->max_driver_temp_used++;
821 }
822
823 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
824 {
825 int i;
826 i = ctx->shader->noutput++;
827 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
828 ctx->shader->output[i].sid = 0;
829 ctx->shader->output[i].gpr = 0;
830 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
831 ctx->shader->output[i].write_mask = 0x4;
832 ctx->shader->output[i].spi_sid = prim_id_sid;
833
834 return 0;
835 }
836
837 static int tgsi_barrier(struct r600_shader_ctx *ctx)
838 {
839 struct r600_bytecode_alu alu;
840 int r;
841
842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
843 alu.op = ctx->inst_info->op;
844 alu.last = 1;
845
846 r = r600_bytecode_add_alu(ctx->bc, &alu);
847 if (r)
848 return r;
849 return 0;
850 }
851
852 static int tgsi_declaration(struct r600_shader_ctx *ctx)
853 {
854 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
855 int r, i, j, count = d->Range.Last - d->Range.First + 1;
856
857 switch (d->Declaration.File) {
858 case TGSI_FILE_INPUT:
859 for (j = 0; j < count; j++) {
860 i = ctx->shader->ninput + j;
861 assert(i < ARRAY_SIZE(ctx->shader->input));
862 ctx->shader->input[i].name = d->Semantic.Name;
863 ctx->shader->input[i].sid = d->Semantic.Index + j;
864 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
865 ctx->shader->input[i].interpolate_location = d->Interp.Location;
866 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
867 if (ctx->type == PIPE_SHADER_FRAGMENT) {
868 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
869 switch (ctx->shader->input[i].name) {
870 case TGSI_SEMANTIC_FACE:
871 if (ctx->face_gpr != -1)
872 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
873 else
874 ctx->face_gpr = ctx->shader->input[i].gpr;
875 break;
876 case TGSI_SEMANTIC_COLOR:
877 ctx->colors_used++;
878 break;
879 case TGSI_SEMANTIC_POSITION:
880 ctx->fragcoord_input = i;
881 break;
882 case TGSI_SEMANTIC_PRIMID:
883 /* set this for now */
884 ctx->shader->gs_prim_id_input = true;
885 ctx->shader->ps_prim_id_input = i;
886 break;
887 }
888 if (ctx->bc->chip_class >= EVERGREEN) {
889 if ((r = evergreen_interp_input(ctx, i)))
890 return r;
891 }
892 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
893 /* FIXME probably skip inputs if they aren't passed in the ring */
894 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
895 ctx->next_ring_offset += 16;
896 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
897 ctx->shader->gs_prim_id_input = true;
898 }
899 }
900 ctx->shader->ninput += count;
901 break;
902 case TGSI_FILE_OUTPUT:
903 for (j = 0; j < count; j++) {
904 i = ctx->shader->noutput + j;
905 assert(i < ARRAY_SIZE(ctx->shader->output));
906 ctx->shader->output[i].name = d->Semantic.Name;
907 ctx->shader->output[i].sid = d->Semantic.Index + j;
908 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
909 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
910 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
911 if (ctx->type == PIPE_SHADER_VERTEX ||
912 ctx->type == PIPE_SHADER_GEOMETRY ||
913 ctx->type == PIPE_SHADER_TESS_EVAL) {
914 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
915 switch (d->Semantic.Name) {
916 case TGSI_SEMANTIC_CLIPDIST:
917 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
918 ((d->Semantic.Index + j) << 2);
919 break;
920 case TGSI_SEMANTIC_PSIZE:
921 ctx->shader->vs_out_misc_write = 1;
922 ctx->shader->vs_out_point_size = 1;
923 break;
924 case TGSI_SEMANTIC_EDGEFLAG:
925 ctx->shader->vs_out_misc_write = 1;
926 ctx->shader->vs_out_edgeflag = 1;
927 ctx->edgeflag_output = i;
928 break;
929 case TGSI_SEMANTIC_VIEWPORT_INDEX:
930 ctx->shader->vs_out_misc_write = 1;
931 ctx->shader->vs_out_viewport = 1;
932 break;
933 case TGSI_SEMANTIC_LAYER:
934 ctx->shader->vs_out_misc_write = 1;
935 ctx->shader->vs_out_layer = 1;
936 break;
937 case TGSI_SEMANTIC_CLIPVERTEX:
938 ctx->clip_vertex_write = TRUE;
939 ctx->cv_output = i;
940 break;
941 }
942 if (ctx->type == PIPE_SHADER_GEOMETRY) {
943 ctx->gs_out_ring_offset += 16;
944 }
945 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
946 switch (d->Semantic.Name) {
947 case TGSI_SEMANTIC_COLOR:
948 ctx->shader->nr_ps_max_color_exports++;
949 break;
950 }
951 }
952 }
953 ctx->shader->noutput += count;
954 break;
955 case TGSI_FILE_TEMPORARY:
956 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
957 if (d->Array.ArrayID) {
958 r600_add_gpr_array(ctx->shader,
959 ctx->file_offset[TGSI_FILE_TEMPORARY] +
960 d->Range.First,
961 d->Range.Last - d->Range.First + 1, 0x0F);
962 }
963 }
964 break;
965
966 case TGSI_FILE_CONSTANT:
967 case TGSI_FILE_SAMPLER:
968 case TGSI_FILE_SAMPLER_VIEW:
969 case TGSI_FILE_ADDRESS:
970 break;
971
972 case TGSI_FILE_HW_ATOMIC:
973 i = ctx->shader->nhwatomic_ranges;
974 ctx->shader->atomics[i].start = d->Range.First;
975 ctx->shader->atomics[i].end = d->Range.Last;
976 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
977 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
978 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
979 ctx->shader->nhwatomic_ranges++;
980 ctx->shader->nhwatomic += count;
981 break;
982
983 case TGSI_FILE_SYSTEM_VALUE:
984 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
985 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
986 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
987 break; /* Already handled from allocate_system_value_inputs */
988 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
989 if (!ctx->native_integers) {
990 struct r600_bytecode_alu alu;
991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
992
993 alu.op = ALU_OP1_INT_TO_FLT;
994 alu.src[0].sel = 0;
995 alu.src[0].chan = 3;
996
997 alu.dst.sel = 0;
998 alu.dst.chan = 3;
999 alu.dst.write = 1;
1000 alu.last = 1;
1001
1002 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1003 return r;
1004 }
1005 break;
1006 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1007 break;
1008 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1009 break;
1010 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1011 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1012 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1013 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1014 unsigned temp_reg = r600_get_temp(ctx);
1015
1016 r = get_lds_offset0(ctx, 2, temp_reg, true);
1017 if (r)
1018 return r;
1019
1020 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1021 temp_reg, 0,
1022 temp_reg, 0,
1023 V_SQ_ALU_SRC_LITERAL, param * 16);
1024 if (r)
1025 return r;
1026
1027 do_lds_fetch_values(ctx, temp_reg, dreg);
1028 }
1029 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1030 /* MOV r1.x, r0.x;
1031 MOV r1.y, r0.y;
1032 */
1033 for (i = 0; i < 2; i++) {
1034 struct r600_bytecode_alu alu;
1035 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1036 alu.op = ALU_OP1_MOV;
1037 alu.src[0].sel = 0;
1038 alu.src[0].chan = 0 + i;
1039 alu.dst.sel = 1;
1040 alu.dst.chan = 0 + i;
1041 alu.dst.write = 1;
1042 alu.last = (i == 1) ? 1 : 0;
1043 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1044 return r;
1045 }
1046 /* ADD r1.z, 1.0f, -r0.x */
1047 struct r600_bytecode_alu alu;
1048 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1049 alu.op = ALU_OP2_ADD;
1050 alu.src[0].sel = V_SQ_ALU_SRC_1;
1051 alu.src[1].sel = 1;
1052 alu.src[1].chan = 0;
1053 alu.src[1].neg = 1;
1054 alu.dst.sel = 1;
1055 alu.dst.chan = 2;
1056 alu.dst.write = 1;
1057 alu.last = 1;
1058 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1059 return r;
1060
1061 /* ADD r1.z, r1.z, -r1.y */
1062 alu.op = ALU_OP2_ADD;
1063 alu.src[0].sel = 1;
1064 alu.src[0].chan = 2;
1065 alu.src[1].sel = 1;
1066 alu.src[1].chan = 1;
1067 alu.src[1].neg = 1;
1068 alu.dst.sel = 1;
1069 alu.dst.chan = 2;
1070 alu.dst.write = 1;
1071 alu.last = 1;
1072 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1073 return r;
1074 break;
1075 }
1076 break;
1077 default:
1078 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1079 return -EINVAL;
1080 }
1081 return 0;
1082 }
1083
1084 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1085 {
1086 struct tgsi_parse_context parse;
1087 struct {
1088 boolean enabled;
1089 int *reg;
1090 unsigned name, alternate_name;
1091 } inputs[2] = {
1092 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1093
1094 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1095 };
1096 int i, k, num_regs = 0;
1097
1098 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1099 return 0;
1100 }
1101
1102 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1103 while (!tgsi_parse_end_of_tokens(&parse)) {
1104 tgsi_parse_token(&parse);
1105
1106 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1107 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1108 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1109 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1110 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1111 {
1112 int interpolate, location, k;
1113
1114 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1115 location = TGSI_INTERPOLATE_LOC_CENTER;
1116 inputs[1].enabled = true; /* needs SAMPLEID */
1117 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1118 location = TGSI_INTERPOLATE_LOC_CENTER;
1119 /* Needs sample positions, currently those are always available */
1120 } else {
1121 location = TGSI_INTERPOLATE_LOC_CENTROID;
1122 }
1123
1124 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1125 k = eg_get_interpolator_index(interpolate, location);
1126 if (k >= 0)
1127 ctx->eg_interpolators[k].enabled = true;
1128 }
1129 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1130 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1131 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1132 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1133 if (d->Semantic.Name == inputs[k].name ||
1134 d->Semantic.Name == inputs[k].alternate_name) {
1135 inputs[k].enabled = true;
1136 }
1137 }
1138 }
1139 }
1140 }
1141
1142 tgsi_parse_free(&parse);
1143
1144 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1145 boolean enabled = inputs[i].enabled;
1146 int *reg = inputs[i].reg;
1147 unsigned name = inputs[i].name;
1148
1149 if (enabled) {
1150 int gpr = gpr_offset + num_regs++;
1151 ctx->shader->nsys_inputs++;
1152
1153 // add to inputs, allocate a gpr
1154 k = ctx->shader->ninput++;
1155 ctx->shader->input[k].name = name;
1156 ctx->shader->input[k].sid = 0;
1157 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1158 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1159 *reg = ctx->shader->input[k].gpr = gpr;
1160 }
1161 }
1162
1163 return gpr_offset + num_regs;
1164 }
1165
1166 /*
1167 * for evergreen we need to scan the shader to find the number of GPRs we need to
1168 * reserve for interpolation and system values
1169 *
1170 * we need to know if we are going to emit
1171 * any sample or centroid inputs
1172 * if perspective and linear are required
1173 */
1174 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1175 {
1176 unsigned i;
1177 int num_baryc;
1178 struct tgsi_parse_context parse;
1179
1180 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1181
1182 for (i = 0; i < ctx->info.num_inputs; i++) {
1183 int k;
1184 /* skip position/face/mask/sampleid */
1185 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1186 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1187 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1188 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1189 continue;
1190
1191 k = eg_get_interpolator_index(
1192 ctx->info.input_interpolate[i],
1193 ctx->info.input_interpolate_loc[i]);
1194 if (k >= 0)
1195 ctx->eg_interpolators[k].enabled = TRUE;
1196 }
1197
1198 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1199 return 0;
1200 }
1201
1202 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1203 while (!tgsi_parse_end_of_tokens(&parse)) {
1204 tgsi_parse_token(&parse);
1205
1206 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1207 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1208 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1209 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1210 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1211 {
1212 int interpolate, location, k;
1213
1214 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1215 location = TGSI_INTERPOLATE_LOC_CENTER;
1216 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1217 location = TGSI_INTERPOLATE_LOC_CENTER;
1218 } else {
1219 location = TGSI_INTERPOLATE_LOC_CENTROID;
1220 }
1221
1222 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1223 k = eg_get_interpolator_index(interpolate, location);
1224 if (k >= 0)
1225 ctx->eg_interpolators[k].enabled = true;
1226 }
1227 }
1228 }
1229
1230 tgsi_parse_free(&parse);
1231
1232 /* assign gpr to each interpolator according to priority */
1233 num_baryc = 0;
1234 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1235 if (ctx->eg_interpolators[i].enabled) {
1236 ctx->eg_interpolators[i].ij_index = num_baryc;
1237 num_baryc ++;
1238 }
1239 }
1240
1241 /* XXX PULL MODEL and LINE STIPPLE */
1242
1243 num_baryc = (num_baryc + 1) >> 1;
1244 return allocate_system_value_inputs(ctx, num_baryc);
1245 }
1246
1247 /* sample_id_sel == NULL means fetch for current sample */
1248 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1249 {
1250 struct r600_bytecode_vtx vtx;
1251 int r, t1;
1252
1253 assert(ctx->fixed_pt_position_gpr != -1);
1254
1255 t1 = r600_get_temp(ctx);
1256
1257 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1258 vtx.op = FETCH_OP_VFETCH;
1259 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1260 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1261 if (sample_id == NULL) {
1262 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1263 vtx.src_sel_x = 3;
1264 }
1265 else {
1266 struct r600_bytecode_alu alu;
1267
1268 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1269 alu.op = ALU_OP1_MOV;
1270 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1271 alu.dst.sel = t1;
1272 alu.dst.write = 1;
1273 alu.last = 1;
1274 r = r600_bytecode_add_alu(ctx->bc, &alu);
1275 if (r)
1276 return r;
1277
1278 vtx.src_gpr = t1;
1279 vtx.src_sel_x = 0;
1280 }
1281 vtx.mega_fetch_count = 16;
1282 vtx.dst_gpr = t1;
1283 vtx.dst_sel_x = 0;
1284 vtx.dst_sel_y = 1;
1285 vtx.dst_sel_z = 2;
1286 vtx.dst_sel_w = 3;
1287 vtx.data_format = FMT_32_32_32_32_FLOAT;
1288 vtx.num_format_all = 2;
1289 vtx.format_comp_all = 1;
1290 vtx.use_const_fields = 0;
1291 vtx.offset = 1; // first element is size of buffer
1292 vtx.endian = r600_endian_swap(32);
1293 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1294
1295 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1296 if (r)
1297 return r;
1298
1299 return t1;
1300 }
1301
1302 static void tgsi_src(struct r600_shader_ctx *ctx,
1303 const struct tgsi_full_src_register *tgsi_src,
1304 struct r600_shader_src *r600_src)
1305 {
1306 memset(r600_src, 0, sizeof(*r600_src));
1307 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1308 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1309 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1310 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1311 r600_src->neg = tgsi_src->Register.Negate;
1312 r600_src->abs = tgsi_src->Register.Absolute;
1313
1314 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1315 int index;
1316 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1317 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1318 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1319
1320 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1321 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1322 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1323 return;
1324 }
1325 index = tgsi_src->Register.Index;
1326 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1327 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1328 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1329 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1330 r600_src->swizzle[0] = 2; // Z value
1331 r600_src->swizzle[1] = 2;
1332 r600_src->swizzle[2] = 2;
1333 r600_src->swizzle[3] = 2;
1334 r600_src->sel = ctx->face_gpr;
1335 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1336 r600_src->swizzle[0] = 3; // W value
1337 r600_src->swizzle[1] = 3;
1338 r600_src->swizzle[2] = 3;
1339 r600_src->swizzle[3] = 3;
1340 r600_src->sel = ctx->fixed_pt_position_gpr;
1341 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1342 r600_src->swizzle[0] = 0;
1343 r600_src->swizzle[1] = 1;
1344 r600_src->swizzle[2] = 4;
1345 r600_src->swizzle[3] = 4;
1346 r600_src->sel = load_sample_position(ctx, NULL, -1);
1347 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1348 r600_src->swizzle[0] = 3;
1349 r600_src->swizzle[1] = 3;
1350 r600_src->swizzle[2] = 3;
1351 r600_src->swizzle[3] = 3;
1352 r600_src->sel = 0;
1353 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1354 r600_src->swizzle[0] = 0;
1355 r600_src->swizzle[1] = 0;
1356 r600_src->swizzle[2] = 0;
1357 r600_src->swizzle[3] = 0;
1358 r600_src->sel = 0;
1359 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1360 r600_src->swizzle[0] = 3;
1361 r600_src->swizzle[1] = 3;
1362 r600_src->swizzle[2] = 3;
1363 r600_src->swizzle[3] = 3;
1364 r600_src->sel = 1;
1365 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1366 r600_src->swizzle[0] = 2;
1367 r600_src->swizzle[1] = 2;
1368 r600_src->swizzle[2] = 2;
1369 r600_src->swizzle[3] = 2;
1370 r600_src->sel = 0;
1371 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1372 r600_src->sel = 1;
1373 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1374 r600_src->sel = 3;
1375 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1376 r600_src->sel = 2;
1377 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1378 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1379 r600_src->sel = ctx->tess_input_info;
1380 r600_src->swizzle[0] = 2;
1381 r600_src->swizzle[1] = 2;
1382 r600_src->swizzle[2] = 2;
1383 r600_src->swizzle[3] = 2;
1384 } else {
1385 r600_src->sel = ctx->tess_input_info;
1386 r600_src->swizzle[0] = 3;
1387 r600_src->swizzle[1] = 3;
1388 r600_src->swizzle[2] = 3;
1389 r600_src->swizzle[3] = 3;
1390 }
1391 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1392 r600_src->sel = 0;
1393 r600_src->swizzle[0] = 0;
1394 r600_src->swizzle[1] = 0;
1395 r600_src->swizzle[2] = 0;
1396 r600_src->swizzle[3] = 0;
1397 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1398 r600_src->sel = 0;
1399 r600_src->swizzle[0] = 3;
1400 r600_src->swizzle[1] = 3;
1401 r600_src->swizzle[2] = 3;
1402 r600_src->swizzle[3] = 3;
1403 }
1404 } else {
1405 if (tgsi_src->Register.Indirect)
1406 r600_src->rel = V_SQ_REL_RELATIVE;
1407 r600_src->sel = tgsi_src->Register.Index;
1408 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1409 }
1410 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1411 if (tgsi_src->Register.Dimension) {
1412 r600_src->kc_bank = tgsi_src->Dimension.Index;
1413 if (tgsi_src->Dimension.Indirect) {
1414 r600_src->kc_rel = 1;
1415 }
1416 }
1417 }
1418 }
1419
1420 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1421 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1422 unsigned int dst_reg)
1423 {
1424 struct r600_bytecode_vtx vtx;
1425 unsigned int ar_reg;
1426 int r;
1427
1428 if (offset) {
1429 struct r600_bytecode_alu alu;
1430
1431 memset(&alu, 0, sizeof(alu));
1432
1433 alu.op = ALU_OP2_ADD_INT;
1434 alu.src[0].sel = ctx->bc->ar_reg;
1435 alu.src[0].chan = ar_chan;
1436
1437 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1438 alu.src[1].value = offset;
1439
1440 alu.dst.sel = dst_reg;
1441 alu.dst.chan = ar_chan;
1442 alu.dst.write = 1;
1443 alu.last = 1;
1444
1445 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1446 return r;
1447
1448 ar_reg = dst_reg;
1449 } else {
1450 ar_reg = ctx->bc->ar_reg;
1451 }
1452
1453 memset(&vtx, 0, sizeof(vtx));
1454 vtx.buffer_id = cb_idx;
1455 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1456 vtx.src_gpr = ar_reg;
1457 vtx.src_sel_x = ar_chan;
1458 vtx.mega_fetch_count = 16;
1459 vtx.dst_gpr = dst_reg;
1460 vtx.dst_sel_x = 0; /* SEL_X */
1461 vtx.dst_sel_y = 1; /* SEL_Y */
1462 vtx.dst_sel_z = 2; /* SEL_Z */
1463 vtx.dst_sel_w = 3; /* SEL_W */
1464 vtx.data_format = FMT_32_32_32_32_FLOAT;
1465 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1466 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1467 vtx.endian = r600_endian_swap(32);
1468 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1469
1470 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1471 return r;
1472
1473 return 0;
1474 }
1475
1476 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1477 {
1478 struct r600_bytecode_vtx vtx;
1479 int r;
1480 unsigned index = src->Register.Index;
1481 unsigned vtx_id = src->Dimension.Index;
1482 int offset_reg = vtx_id / 3;
1483 int offset_chan = vtx_id % 3;
1484 int t2 = 0;
1485
1486 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1487 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1488
1489 if (offset_reg == 0 && offset_chan == 2)
1490 offset_chan = 3;
1491
1492 if (src->Dimension.Indirect || src->Register.Indirect)
1493 t2 = r600_get_temp(ctx);
1494
1495 if (src->Dimension.Indirect) {
1496 int treg[3];
1497 struct r600_bytecode_alu alu;
1498 int r, i;
1499 unsigned addr_reg;
1500 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1501 if (src->DimIndirect.Index > 0) {
1502 r = single_alu_op2(ctx, ALU_OP1_MOV,
1503 ctx->bc->ar_reg, 0,
1504 addr_reg, 0,
1505 0, 0);
1506 if (r)
1507 return r;
1508 }
1509 /*
1510 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1511 at least this is what fglrx seems to do. */
1512 for (i = 0; i < 3; i++) {
1513 treg[i] = r600_get_temp(ctx);
1514 }
1515 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1516
1517 for (i = 0; i < 3; i++) {
1518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1519 alu.op = ALU_OP1_MOV;
1520 alu.src[0].sel = 0;
1521 alu.src[0].chan = i == 2 ? 3 : i;
1522 alu.dst.sel = treg[i];
1523 alu.dst.chan = 0;
1524 alu.dst.write = 1;
1525 alu.last = 1;
1526 r = r600_bytecode_add_alu(ctx->bc, &alu);
1527 if (r)
1528 return r;
1529 }
1530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1531 alu.op = ALU_OP1_MOV;
1532 alu.src[0].sel = treg[0];
1533 alu.src[0].rel = 1;
1534 alu.dst.sel = t2;
1535 alu.dst.write = 1;
1536 alu.last = 1;
1537 r = r600_bytecode_add_alu(ctx->bc, &alu);
1538 if (r)
1539 return r;
1540 offset_reg = t2;
1541 offset_chan = 0;
1542 }
1543
1544 if (src->Register.Indirect) {
1545 int addr_reg;
1546 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1547
1548 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1549
1550 /* pull the value from index_reg */
1551 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1552 t2, 1,
1553 addr_reg, 0,
1554 V_SQ_ALU_SRC_LITERAL, first);
1555 if (r)
1556 return r;
1557 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1558 t2, 0,
1559 t2, 1,
1560 V_SQ_ALU_SRC_LITERAL, 4,
1561 offset_reg, offset_chan);
1562 if (r)
1563 return r;
1564 offset_reg = t2;
1565 offset_chan = 0;
1566 index = src->Register.Index - first;
1567 }
1568
1569 memset(&vtx, 0, sizeof(vtx));
1570 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1571 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1572 vtx.src_gpr = offset_reg;
1573 vtx.src_sel_x = offset_chan;
1574 vtx.offset = index * 16; /*bytes*/
1575 vtx.mega_fetch_count = 16;
1576 vtx.dst_gpr = dst_reg;
1577 vtx.dst_sel_x = 0; /* SEL_X */
1578 vtx.dst_sel_y = 1; /* SEL_Y */
1579 vtx.dst_sel_z = 2; /* SEL_Z */
1580 vtx.dst_sel_w = 3; /* SEL_W */
1581 if (ctx->bc->chip_class >= EVERGREEN) {
1582 vtx.use_const_fields = 1;
1583 } else {
1584 vtx.data_format = FMT_32_32_32_32_FLOAT;
1585 }
1586
1587 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1588 return r;
1589
1590 return 0;
1591 }
1592
1593 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1594 {
1595 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1596 unsigned i;
1597
1598 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1599 struct tgsi_full_src_register *src = &inst->Src[i];
1600
1601 if (src->Register.File == TGSI_FILE_INPUT) {
1602 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1603 /* primitive id is in R0.z */
1604 ctx->src[i].sel = 0;
1605 ctx->src[i].swizzle[0] = 2;
1606 }
1607 }
1608 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1609 int treg = r600_get_temp(ctx);
1610
1611 fetch_gs_input(ctx, src, treg);
1612 ctx->src[i].sel = treg;
1613 ctx->src[i].rel = 0;
1614 }
1615 }
1616 return 0;
1617 }
1618
1619
1620 /* Tessellation shaders pass outputs to the next shader using LDS.
1621 *
1622 * LS outputs = TCS(HS) inputs
1623 * TCS(HS) outputs = TES(DS) inputs
1624 *
1625 * The LDS layout is:
1626 * - TCS inputs for patch 0
1627 * - TCS inputs for patch 1
1628 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1629 * - ...
1630 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1631 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1632 * - TCS outputs for patch 1
1633 * - Per-patch TCS outputs for patch 1
1634 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1635 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1636 * - ...
1637 *
1638 * All three shaders VS(LS), TCS, TES share the same LDS space.
1639 */
1640 /* this will return with the dw address in temp_reg.x */
1641 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1642 const struct tgsi_full_dst_register *dst,
1643 const struct tgsi_full_src_register *src,
1644 int stride_bytes_reg, int stride_bytes_chan)
1645 {
1646 struct tgsi_full_dst_register reg;
1647 ubyte *name, *index, *array_first;
1648 int r;
1649 int param;
1650 struct tgsi_shader_info *info = &ctx->info;
1651 /* Set the register description. The address computation is the same
1652 * for sources and destinations. */
1653 if (src) {
1654 reg.Register.File = src->Register.File;
1655 reg.Register.Index = src->Register.Index;
1656 reg.Register.Indirect = src->Register.Indirect;
1657 reg.Register.Dimension = src->Register.Dimension;
1658 reg.Indirect = src->Indirect;
1659 reg.Dimension = src->Dimension;
1660 reg.DimIndirect = src->DimIndirect;
1661 } else
1662 reg = *dst;
1663
1664 /* If the register is 2-dimensional (e.g. an array of vertices
1665 * in a primitive), calculate the base address of the vertex. */
1666 if (reg.Register.Dimension) {
1667 int sel, chan;
1668 if (reg.Dimension.Indirect) {
1669 unsigned addr_reg;
1670 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1671
1672 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1673 /* pull the value from index_reg */
1674 sel = addr_reg;
1675 chan = 0;
1676 } else {
1677 sel = V_SQ_ALU_SRC_LITERAL;
1678 chan = reg.Dimension.Index;
1679 }
1680
1681 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1682 temp_reg, 0,
1683 stride_bytes_reg, stride_bytes_chan,
1684 sel, chan,
1685 temp_reg, 0);
1686 if (r)
1687 return r;
1688 }
1689
1690 if (reg.Register.File == TGSI_FILE_INPUT) {
1691 name = info->input_semantic_name;
1692 index = info->input_semantic_index;
1693 array_first = info->input_array_first;
1694 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1695 name = info->output_semantic_name;
1696 index = info->output_semantic_index;
1697 array_first = info->output_array_first;
1698 } else {
1699 assert(0);
1700 return -1;
1701 }
1702 if (reg.Register.Indirect) {
1703 int addr_reg;
1704 int first;
1705 /* Add the relative address of the element. */
1706 if (reg.Indirect.ArrayID)
1707 first = array_first[reg.Indirect.ArrayID];
1708 else
1709 first = reg.Register.Index;
1710
1711 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1712
1713 /* pull the value from index_reg */
1714 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1715 temp_reg, 0,
1716 V_SQ_ALU_SRC_LITERAL, 16,
1717 addr_reg, 0,
1718 temp_reg, 0);
1719 if (r)
1720 return r;
1721
1722 param = r600_get_lds_unique_index(name[first],
1723 index[first]);
1724
1725 } else {
1726 param = r600_get_lds_unique_index(name[reg.Register.Index],
1727 index[reg.Register.Index]);
1728 }
1729
1730 /* add to base_addr - passed in temp_reg.x */
1731 if (param) {
1732 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1733 temp_reg, 0,
1734 temp_reg, 0,
1735 V_SQ_ALU_SRC_LITERAL, param * 16);
1736 if (r)
1737 return r;
1738
1739 }
1740 return 0;
1741 }
1742
1743 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1744 unsigned dst_reg)
1745 {
1746 struct r600_bytecode_alu alu;
1747 int r, i;
1748
1749 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1750 ctx->bc->force_add_cf = 1;
1751 for (i = 1; i < 4; i++) {
1752 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1753 temp_reg, i,
1754 temp_reg, 0,
1755 V_SQ_ALU_SRC_LITERAL, 4 * i);
1756 if (r)
1757 return r;
1758 }
1759 for (i = 0; i < 4; i++) {
1760 /* emit an LDS_READ_RET */
1761 memset(&alu, 0, sizeof(alu));
1762 alu.op = LDS_OP1_LDS_READ_RET;
1763 alu.src[0].sel = temp_reg;
1764 alu.src[0].chan = i;
1765 alu.src[1].sel = V_SQ_ALU_SRC_0;
1766 alu.src[2].sel = V_SQ_ALU_SRC_0;
1767 alu.dst.chan = 0;
1768 alu.is_lds_idx_op = true;
1769 alu.last = 1;
1770 r = r600_bytecode_add_alu(ctx->bc, &alu);
1771 if (r)
1772 return r;
1773 }
1774 for (i = 0; i < 4; i++) {
1775 /* then read from LDS_OQ_A_POP */
1776 memset(&alu, 0, sizeof(alu));
1777
1778 alu.op = ALU_OP1_MOV;
1779 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1780 alu.src[0].chan = 0;
1781 alu.dst.sel = dst_reg;
1782 alu.dst.chan = i;
1783 alu.dst.write = 1;
1784 alu.last = 1;
1785 r = r600_bytecode_add_alu(ctx->bc, &alu);
1786 if (r)
1787 return r;
1788 }
1789 return 0;
1790 }
1791
1792 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1793 {
1794 int r;
1795 unsigned temp_reg = r600_get_temp(ctx);
1796
1797 r = get_lds_offset0(ctx, 2, temp_reg,
1798 src->Register.Dimension ? false : true);
1799 if (r)
1800 return r;
1801
1802 /* the base address is now in temp.x */
1803 r = r600_get_byte_address(ctx, temp_reg,
1804 NULL, src, ctx->tess_output_info, 1);
1805 if (r)
1806 return r;
1807
1808 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1809 if (r)
1810 return r;
1811 return 0;
1812 }
1813
1814 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1815 {
1816 int r;
1817 unsigned temp_reg = r600_get_temp(ctx);
1818
1819 /* t.x = ips * r0.y */
1820 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1821 temp_reg, 0,
1822 ctx->tess_input_info, 0,
1823 0, 1);
1824
1825 if (r)
1826 return r;
1827
1828 /* the base address is now in temp.x */
1829 r = r600_get_byte_address(ctx, temp_reg,
1830 NULL, src, ctx->tess_input_info, 1);
1831 if (r)
1832 return r;
1833
1834 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1835 if (r)
1836 return r;
1837 return 0;
1838 }
1839
1840 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1841 {
1842 int r;
1843 unsigned temp_reg = r600_get_temp(ctx);
1844
1845 r = get_lds_offset0(ctx, 1, temp_reg,
1846 src->Register.Dimension ? false : true);
1847 if (r)
1848 return r;
1849 /* the base address is now in temp.x */
1850 r = r600_get_byte_address(ctx, temp_reg,
1851 NULL, src,
1852 ctx->tess_output_info, 1);
1853 if (r)
1854 return r;
1855
1856 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1857 if (r)
1858 return r;
1859 return 0;
1860 }
1861
1862 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1863 {
1864 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1865 unsigned i;
1866
1867 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1868 struct tgsi_full_src_register *src = &inst->Src[i];
1869
1870 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1871 int treg = r600_get_temp(ctx);
1872 fetch_tes_input(ctx, src, treg);
1873 ctx->src[i].sel = treg;
1874 ctx->src[i].rel = 0;
1875 }
1876 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1877 int treg = r600_get_temp(ctx);
1878 fetch_tcs_input(ctx, src, treg);
1879 ctx->src[i].sel = treg;
1880 ctx->src[i].rel = 0;
1881 }
1882 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1883 int treg = r600_get_temp(ctx);
1884 fetch_tcs_output(ctx, src, treg);
1885 ctx->src[i].sel = treg;
1886 ctx->src[i].rel = 0;
1887 }
1888 }
1889 return 0;
1890 }
1891
1892 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1893 {
1894 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1895 struct r600_bytecode_alu alu;
1896 int i, j, k, nconst, r;
1897
1898 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1899 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1900 nconst++;
1901 }
1902 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1903 }
1904 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1905 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1906 continue;
1907 }
1908
1909 if (ctx->src[i].rel) {
1910 int chan = inst->Src[i].Indirect.Swizzle;
1911 int treg = r600_get_temp(ctx);
1912 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1913 return r;
1914
1915 ctx->src[i].kc_bank = 0;
1916 ctx->src[i].kc_rel = 0;
1917 ctx->src[i].sel = treg;
1918 ctx->src[i].rel = 0;
1919 j--;
1920 } else if (j > 0) {
1921 int treg = r600_get_temp(ctx);
1922 for (k = 0; k < 4; k++) {
1923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1924 alu.op = ALU_OP1_MOV;
1925 alu.src[0].sel = ctx->src[i].sel;
1926 alu.src[0].chan = k;
1927 alu.src[0].rel = ctx->src[i].rel;
1928 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1929 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1930 alu.dst.sel = treg;
1931 alu.dst.chan = k;
1932 alu.dst.write = 1;
1933 if (k == 3)
1934 alu.last = 1;
1935 r = r600_bytecode_add_alu(ctx->bc, &alu);
1936 if (r)
1937 return r;
1938 }
1939 ctx->src[i].sel = treg;
1940 ctx->src[i].rel =0;
1941 j--;
1942 }
1943 }
1944 return 0;
1945 }
1946
1947 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1948 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1949 {
1950 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1951 struct r600_bytecode_alu alu;
1952 int i, j, k, nliteral, r;
1953
1954 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1955 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1956 nliteral++;
1957 }
1958 }
1959 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1960 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1961 int treg = r600_get_temp(ctx);
1962 for (k = 0; k < 4; k++) {
1963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1964 alu.op = ALU_OP1_MOV;
1965 alu.src[0].sel = ctx->src[i].sel;
1966 alu.src[0].chan = k;
1967 alu.src[0].value = ctx->src[i].value[k];
1968 alu.dst.sel = treg;
1969 alu.dst.chan = k;
1970 alu.dst.write = 1;
1971 if (k == 3)
1972 alu.last = 1;
1973 r = r600_bytecode_add_alu(ctx->bc, &alu);
1974 if (r)
1975 return r;
1976 }
1977 ctx->src[i].sel = treg;
1978 j--;
1979 }
1980 }
1981 return 0;
1982 }
1983
1984 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1985 {
1986 int i, r, count = ctx->shader->ninput;
1987
1988 for (i = 0; i < count; i++) {
1989 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1990 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1991 if (r)
1992 return r;
1993 }
1994 }
1995 return 0;
1996 }
1997
1998 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1999 int stream, unsigned *stream_item_size)
2000 {
2001 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2002 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2003 int i, j, r;
2004
2005 /* Sanity checking. */
2006 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2007 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2008 r = -EINVAL;
2009 goto out_err;
2010 }
2011 for (i = 0; i < so->num_outputs; i++) {
2012 if (so->output[i].output_buffer >= 4) {
2013 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2014 so->output[i].output_buffer);
2015 r = -EINVAL;
2016 goto out_err;
2017 }
2018 }
2019
2020 /* Initialize locations where the outputs are stored. */
2021 for (i = 0; i < so->num_outputs; i++) {
2022
2023 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2024 start_comp[i] = so->output[i].start_component;
2025 /* Lower outputs with dst_offset < start_component.
2026 *
2027 * We can only output 4D vectors with a write mask, e.g. we can
2028 * only output the W component at offset 3, etc. If we want
2029 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2030 * to move it to X and output X. */
2031 if (so->output[i].dst_offset < so->output[i].start_component) {
2032 unsigned tmp = r600_get_temp(ctx);
2033
2034 for (j = 0; j < so->output[i].num_components; j++) {
2035 struct r600_bytecode_alu alu;
2036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2037 alu.op = ALU_OP1_MOV;
2038 alu.src[0].sel = so_gpr[i];
2039 alu.src[0].chan = so->output[i].start_component + j;
2040
2041 alu.dst.sel = tmp;
2042 alu.dst.chan = j;
2043 alu.dst.write = 1;
2044 if (j == so->output[i].num_components - 1)
2045 alu.last = 1;
2046 r = r600_bytecode_add_alu(ctx->bc, &alu);
2047 if (r)
2048 return r;
2049 }
2050 start_comp[i] = 0;
2051 so_gpr[i] = tmp;
2052 }
2053 }
2054
2055 /* Write outputs to buffers. */
2056 for (i = 0; i < so->num_outputs; i++) {
2057 struct r600_bytecode_output output;
2058
2059 if (stream != -1 && stream != so->output[i].output_buffer)
2060 continue;
2061
2062 memset(&output, 0, sizeof(struct r600_bytecode_output));
2063 output.gpr = so_gpr[i];
2064 output.elem_size = so->output[i].num_components - 1;
2065 if (output.elem_size == 2)
2066 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2067 output.array_base = so->output[i].dst_offset - start_comp[i];
2068 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2069 output.burst_count = 1;
2070 /* array_size is an upper limit for the burst_count
2071 * with MEM_STREAM instructions */
2072 output.array_size = 0xFFF;
2073 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2074
2075 if (ctx->bc->chip_class >= EVERGREEN) {
2076 switch (so->output[i].output_buffer) {
2077 case 0:
2078 output.op = CF_OP_MEM_STREAM0_BUF0;
2079 break;
2080 case 1:
2081 output.op = CF_OP_MEM_STREAM0_BUF1;
2082 break;
2083 case 2:
2084 output.op = CF_OP_MEM_STREAM0_BUF2;
2085 break;
2086 case 3:
2087 output.op = CF_OP_MEM_STREAM0_BUF3;
2088 break;
2089 }
2090 output.op += so->output[i].stream * 4;
2091 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2092 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2093 } else {
2094 switch (so->output[i].output_buffer) {
2095 case 0:
2096 output.op = CF_OP_MEM_STREAM0;
2097 break;
2098 case 1:
2099 output.op = CF_OP_MEM_STREAM1;
2100 break;
2101 case 2:
2102 output.op = CF_OP_MEM_STREAM2;
2103 break;
2104 case 3:
2105 output.op = CF_OP_MEM_STREAM3;
2106 break;
2107 }
2108 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2109 }
2110 r = r600_bytecode_add_output(ctx->bc, &output);
2111 if (r)
2112 goto out_err;
2113 }
2114 return 0;
2115 out_err:
2116 return r;
2117 }
2118
2119 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2120 {
2121 struct r600_bytecode_alu alu;
2122 unsigned reg;
2123
2124 if (!ctx->shader->vs_out_edgeflag)
2125 return;
2126
2127 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2128
2129 /* clamp(x, 0, 1) */
2130 memset(&alu, 0, sizeof(alu));
2131 alu.op = ALU_OP1_MOV;
2132 alu.src[0].sel = reg;
2133 alu.dst.sel = reg;
2134 alu.dst.write = 1;
2135 alu.dst.clamp = 1;
2136 alu.last = 1;
2137 r600_bytecode_add_alu(ctx->bc, &alu);
2138
2139 memset(&alu, 0, sizeof(alu));
2140 alu.op = ALU_OP1_FLT_TO_INT;
2141 alu.src[0].sel = reg;
2142 alu.dst.sel = reg;
2143 alu.dst.write = 1;
2144 alu.last = 1;
2145 r600_bytecode_add_alu(ctx->bc, &alu);
2146 }
2147
2148 static int generate_gs_copy_shader(struct r600_context *rctx,
2149 struct r600_pipe_shader *gs,
2150 struct pipe_stream_output_info *so)
2151 {
2152 struct r600_shader_ctx ctx = {};
2153 struct r600_shader *gs_shader = &gs->shader;
2154 struct r600_pipe_shader *cshader;
2155 int ocnt = gs_shader->noutput;
2156 struct r600_bytecode_alu alu;
2157 struct r600_bytecode_vtx vtx;
2158 struct r600_bytecode_output output;
2159 struct r600_bytecode_cf *cf_jump, *cf_pop,
2160 *last_exp_pos = NULL, *last_exp_param = NULL;
2161 int i, j, next_clip_pos = 61, next_param = 0;
2162 int ring;
2163 bool only_ring_0 = true;
2164 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2165 if (!cshader)
2166 return 0;
2167
2168 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2169 sizeof(struct r600_shader_io));
2170
2171 cshader->shader.noutput = ocnt;
2172
2173 ctx.shader = &cshader->shader;
2174 ctx.bc = &ctx.shader->bc;
2175 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2176
2177 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2178 rctx->screen->has_compressed_msaa_texturing);
2179
2180 ctx.bc->isa = rctx->isa;
2181
2182 cf_jump = NULL;
2183 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2184
2185 /* R0.x = R0.x & 0x3fffffff */
2186 memset(&alu, 0, sizeof(alu));
2187 alu.op = ALU_OP2_AND_INT;
2188 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2189 alu.src[1].value = 0x3fffffff;
2190 alu.dst.write = 1;
2191 r600_bytecode_add_alu(ctx.bc, &alu);
2192
2193 /* R0.y = R0.x >> 30 */
2194 memset(&alu, 0, sizeof(alu));
2195 alu.op = ALU_OP2_LSHR_INT;
2196 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2197 alu.src[1].value = 0x1e;
2198 alu.dst.chan = 1;
2199 alu.dst.write = 1;
2200 alu.last = 1;
2201 r600_bytecode_add_alu(ctx.bc, &alu);
2202
2203 /* fetch vertex data from GSVS ring */
2204 for (i = 0; i < ocnt; ++i) {
2205 struct r600_shader_io *out = &ctx.shader->output[i];
2206
2207 out->gpr = i + 1;
2208 out->ring_offset = i * 16;
2209
2210 memset(&vtx, 0, sizeof(vtx));
2211 vtx.op = FETCH_OP_VFETCH;
2212 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2213 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2214 vtx.mega_fetch_count = 16;
2215 vtx.offset = out->ring_offset;
2216 vtx.dst_gpr = out->gpr;
2217 vtx.src_gpr = 0;
2218 vtx.dst_sel_x = 0;
2219 vtx.dst_sel_y = 1;
2220 vtx.dst_sel_z = 2;
2221 vtx.dst_sel_w = 3;
2222 if (rctx->b.chip_class >= EVERGREEN) {
2223 vtx.use_const_fields = 1;
2224 } else {
2225 vtx.data_format = FMT_32_32_32_32_FLOAT;
2226 }
2227
2228 r600_bytecode_add_vtx(ctx.bc, &vtx);
2229 }
2230 ctx.temp_reg = i + 1;
2231 for (ring = 3; ring >= 0; --ring) {
2232 bool enabled = false;
2233 for (i = 0; i < so->num_outputs; i++) {
2234 if (so->output[i].stream == ring) {
2235 enabled = true;
2236 if (ring > 0)
2237 only_ring_0 = false;
2238 break;
2239 }
2240 }
2241 if (ring != 0 && !enabled) {
2242 cshader->shader.ring_item_sizes[ring] = 0;
2243 continue;
2244 }
2245
2246 if (cf_jump) {
2247 // Patch up jump label
2248 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2249 cf_pop = ctx.bc->cf_last;
2250
2251 cf_jump->cf_addr = cf_pop->id + 2;
2252 cf_jump->pop_count = 1;
2253 cf_pop->cf_addr = cf_pop->id + 2;
2254 cf_pop->pop_count = 1;
2255 }
2256
2257 /* PRED_SETE_INT __, R0.y, ring */
2258 memset(&alu, 0, sizeof(alu));
2259 alu.op = ALU_OP2_PRED_SETE_INT;
2260 alu.src[0].chan = 1;
2261 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2262 alu.src[1].value = ring;
2263 alu.execute_mask = 1;
2264 alu.update_pred = 1;
2265 alu.last = 1;
2266 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2267
2268 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2269 cf_jump = ctx.bc->cf_last;
2270
2271 if (enabled)
2272 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2273 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2274 }
2275
2276 /* bc adds nops - copy it */
2277 if (ctx.bc->chip_class == R600) {
2278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2279 alu.op = ALU_OP0_NOP;
2280 alu.last = 1;
2281 r600_bytecode_add_alu(ctx.bc, &alu);
2282
2283 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2284 }
2285
2286 /* export vertex data */
2287 /* XXX factor out common code with r600_shader_from_tgsi ? */
2288 for (i = 0; i < ocnt; ++i) {
2289 struct r600_shader_io *out = &ctx.shader->output[i];
2290 bool instream0 = true;
2291 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2292 continue;
2293
2294 for (j = 0; j < so->num_outputs; j++) {
2295 if (so->output[j].register_index == i) {
2296 if (so->output[j].stream == 0)
2297 break;
2298 if (so->output[j].stream > 0)
2299 instream0 = false;
2300 }
2301 }
2302 if (!instream0)
2303 continue;
2304 memset(&output, 0, sizeof(output));
2305 output.gpr = out->gpr;
2306 output.elem_size = 3;
2307 output.swizzle_x = 0;
2308 output.swizzle_y = 1;
2309 output.swizzle_z = 2;
2310 output.swizzle_w = 3;
2311 output.burst_count = 1;
2312 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2313 output.op = CF_OP_EXPORT;
2314 switch (out->name) {
2315 case TGSI_SEMANTIC_POSITION:
2316 output.array_base = 60;
2317 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2318 break;
2319
2320 case TGSI_SEMANTIC_PSIZE:
2321 output.array_base = 61;
2322 if (next_clip_pos == 61)
2323 next_clip_pos = 62;
2324 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2325 output.swizzle_y = 7;
2326 output.swizzle_z = 7;
2327 output.swizzle_w = 7;
2328 ctx.shader->vs_out_misc_write = 1;
2329 ctx.shader->vs_out_point_size = 1;
2330 break;
2331 case TGSI_SEMANTIC_LAYER:
2332 if (out->spi_sid) {
2333 /* duplicate it as PARAM to pass to the pixel shader */
2334 output.array_base = next_param++;
2335 r600_bytecode_add_output(ctx.bc, &output);
2336 last_exp_param = ctx.bc->cf_last;
2337 }
2338 output.array_base = 61;
2339 if (next_clip_pos == 61)
2340 next_clip_pos = 62;
2341 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2342 output.swizzle_x = 7;
2343 output.swizzle_y = 7;
2344 output.swizzle_z = 0;
2345 output.swizzle_w = 7;
2346 ctx.shader->vs_out_misc_write = 1;
2347 ctx.shader->vs_out_layer = 1;
2348 break;
2349 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2350 if (out->spi_sid) {
2351 /* duplicate it as PARAM to pass to the pixel shader */
2352 output.array_base = next_param++;
2353 r600_bytecode_add_output(ctx.bc, &output);
2354 last_exp_param = ctx.bc->cf_last;
2355 }
2356 output.array_base = 61;
2357 if (next_clip_pos == 61)
2358 next_clip_pos = 62;
2359 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2360 ctx.shader->vs_out_misc_write = 1;
2361 ctx.shader->vs_out_viewport = 1;
2362 output.swizzle_x = 7;
2363 output.swizzle_y = 7;
2364 output.swizzle_z = 7;
2365 output.swizzle_w = 0;
2366 break;
2367 case TGSI_SEMANTIC_CLIPDIST:
2368 /* spi_sid is 0 for clipdistance outputs that were generated
2369 * for clipvertex - we don't need to pass them to PS */
2370 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2371 if (out->spi_sid) {
2372 /* duplicate it as PARAM to pass to the pixel shader */
2373 output.array_base = next_param++;
2374 r600_bytecode_add_output(ctx.bc, &output);
2375 last_exp_param = ctx.bc->cf_last;
2376 }
2377 output.array_base = next_clip_pos++;
2378 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2379 break;
2380 case TGSI_SEMANTIC_FOG:
2381 output.swizzle_y = 4; /* 0 */
2382 output.swizzle_z = 4; /* 0 */
2383 output.swizzle_w = 5; /* 1 */
2384 break;
2385 default:
2386 output.array_base = next_param++;
2387 break;
2388 }
2389 r600_bytecode_add_output(ctx.bc, &output);
2390 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2391 last_exp_param = ctx.bc->cf_last;
2392 else
2393 last_exp_pos = ctx.bc->cf_last;
2394 }
2395
2396 if (!last_exp_pos) {
2397 memset(&output, 0, sizeof(output));
2398 output.gpr = 0;
2399 output.elem_size = 3;
2400 output.swizzle_x = 7;
2401 output.swizzle_y = 7;
2402 output.swizzle_z = 7;
2403 output.swizzle_w = 7;
2404 output.burst_count = 1;
2405 output.type = 2;
2406 output.op = CF_OP_EXPORT;
2407 output.array_base = 60;
2408 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2409 r600_bytecode_add_output(ctx.bc, &output);
2410 last_exp_pos = ctx.bc->cf_last;
2411 }
2412
2413 if (!last_exp_param) {
2414 memset(&output, 0, sizeof(output));
2415 output.gpr = 0;
2416 output.elem_size = 3;
2417 output.swizzle_x = 7;
2418 output.swizzle_y = 7;
2419 output.swizzle_z = 7;
2420 output.swizzle_w = 7;
2421 output.burst_count = 1;
2422 output.type = 2;
2423 output.op = CF_OP_EXPORT;
2424 output.array_base = next_param++;
2425 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2426 r600_bytecode_add_output(ctx.bc, &output);
2427 last_exp_param = ctx.bc->cf_last;
2428 }
2429
2430 last_exp_pos->op = CF_OP_EXPORT_DONE;
2431 last_exp_param->op = CF_OP_EXPORT_DONE;
2432
2433 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2434 cf_pop = ctx.bc->cf_last;
2435
2436 cf_jump->cf_addr = cf_pop->id + 2;
2437 cf_jump->pop_count = 1;
2438 cf_pop->cf_addr = cf_pop->id + 2;
2439 cf_pop->pop_count = 1;
2440
2441 if (ctx.bc->chip_class == CAYMAN)
2442 cm_bytecode_add_cf_end(ctx.bc);
2443 else {
2444 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2445 ctx.bc->cf_last->end_of_program = 1;
2446 }
2447
2448 gs->gs_copy_shader = cshader;
2449 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2450
2451 ctx.bc->nstack = 1;
2452
2453 return r600_bytecode_build(ctx.bc);
2454 }
2455
2456 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2457 {
2458 if (ind) {
2459 struct r600_bytecode_alu alu;
2460 int r;
2461
2462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2463 alu.op = ALU_OP2_ADD_INT;
2464 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2465 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2466 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2467 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2468 alu.dst.write = 1;
2469 alu.last = 1;
2470 r = r600_bytecode_add_alu(ctx->bc, &alu);
2471 if (r)
2472 return r;
2473 }
2474 return 0;
2475 }
2476
2477 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2478 {
2479 struct r600_bytecode_output output;
2480 int i, k, ring_offset;
2481 int effective_stream = stream == -1 ? 0 : stream;
2482 int idx = 0;
2483
2484 for (i = 0; i < ctx->shader->noutput; i++) {
2485 if (ctx->gs_for_vs) {
2486 /* for ES we need to lookup corresponding ring offset expected by GS
2487 * (map this output to GS input by name and sid) */
2488 /* FIXME precompute offsets */
2489 ring_offset = -1;
2490 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2491 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2492 struct r600_shader_io *out = &ctx->shader->output[i];
2493 if (in->name == out->name && in->sid == out->sid)
2494 ring_offset = in->ring_offset;
2495 }
2496
2497 if (ring_offset == -1)
2498 continue;
2499 } else {
2500 ring_offset = idx * 16;
2501 idx++;
2502 }
2503
2504 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2505 continue;
2506 /* next_ring_offset after parsing input decls contains total size of
2507 * single vertex data, gs_next_vertex - current vertex index */
2508 if (!ind)
2509 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2510
2511 memset(&output, 0, sizeof(struct r600_bytecode_output));
2512 output.gpr = ctx->shader->output[i].gpr;
2513 output.elem_size = 3;
2514 output.comp_mask = 0xF;
2515 output.burst_count = 1;
2516
2517 if (ind)
2518 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2519 else
2520 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2521
2522 switch (stream) {
2523 default:
2524 case 0:
2525 output.op = CF_OP_MEM_RING; break;
2526 case 1:
2527 output.op = CF_OP_MEM_RING1; break;
2528 case 2:
2529 output.op = CF_OP_MEM_RING2; break;
2530 case 3:
2531 output.op = CF_OP_MEM_RING3; break;
2532 }
2533
2534 if (ind) {
2535 output.array_base = ring_offset >> 2; /* in dwords */
2536 output.array_size = 0xfff;
2537 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2538 } else
2539 output.array_base = ring_offset >> 2; /* in dwords */
2540 r600_bytecode_add_output(ctx->bc, &output);
2541 }
2542
2543 ++ctx->gs_next_vertex;
2544 return 0;
2545 }
2546
2547
2548 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2549 {
2550 int r;
2551 struct r600_bytecode_vtx vtx;
2552 int temp_val = ctx->temp_reg;
2553 /* need to store the TCS output somewhere */
2554 r = single_alu_op2(ctx, ALU_OP1_MOV,
2555 temp_val, 0,
2556 V_SQ_ALU_SRC_LITERAL, 0,
2557 0, 0);
2558 if (r)
2559 return r;
2560
2561 /* used by VS/TCS */
2562 if (ctx->tess_input_info) {
2563 /* fetch tcs input values into resv space */
2564 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2565 vtx.op = FETCH_OP_VFETCH;
2566 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2567 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2568 vtx.mega_fetch_count = 16;
2569 vtx.data_format = FMT_32_32_32_32;
2570 vtx.num_format_all = 2;
2571 vtx.format_comp_all = 1;
2572 vtx.use_const_fields = 0;
2573 vtx.endian = r600_endian_swap(32);
2574 vtx.srf_mode_all = 1;
2575 vtx.offset = 0;
2576 vtx.dst_gpr = ctx->tess_input_info;
2577 vtx.dst_sel_x = 0;
2578 vtx.dst_sel_y = 1;
2579 vtx.dst_sel_z = 2;
2580 vtx.dst_sel_w = 3;
2581 vtx.src_gpr = temp_val;
2582 vtx.src_sel_x = 0;
2583
2584 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2585 if (r)
2586 return r;
2587 }
2588
2589 /* used by TCS/TES */
2590 if (ctx->tess_output_info) {
2591 /* fetch tcs output values into resv space */
2592 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2593 vtx.op = FETCH_OP_VFETCH;
2594 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2595 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2596 vtx.mega_fetch_count = 16;
2597 vtx.data_format = FMT_32_32_32_32;
2598 vtx.num_format_all = 2;
2599 vtx.format_comp_all = 1;
2600 vtx.use_const_fields = 0;
2601 vtx.endian = r600_endian_swap(32);
2602 vtx.srf_mode_all = 1;
2603 vtx.offset = 16;
2604 vtx.dst_gpr = ctx->tess_output_info;
2605 vtx.dst_sel_x = 0;
2606 vtx.dst_sel_y = 1;
2607 vtx.dst_sel_z = 2;
2608 vtx.dst_sel_w = 3;
2609 vtx.src_gpr = temp_val;
2610 vtx.src_sel_x = 0;
2611
2612 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2613 if (r)
2614 return r;
2615 }
2616 return 0;
2617 }
2618
2619 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2620 {
2621 int i, j, r;
2622 int temp_reg;
2623
2624 /* fetch tcs input values into input_vals */
2625 ctx->tess_input_info = r600_get_temp(ctx);
2626 ctx->tess_output_info = 0;
2627 r = r600_fetch_tess_io_info(ctx);
2628 if (r)
2629 return r;
2630
2631 temp_reg = r600_get_temp(ctx);
2632 /* dst reg contains LDS address stride * idx */
2633 /* MUL vertexID, vertex_dw_stride */
2634 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2635 temp_reg, 0,
2636 ctx->tess_input_info, 1,
2637 0, 1); /* rel id in r0.y? */
2638 if (r)
2639 return r;
2640
2641 for (i = 0; i < ctx->shader->noutput; i++) {
2642 struct r600_bytecode_alu alu;
2643 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2644
2645 if (param) {
2646 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2647 temp_reg, 1,
2648 temp_reg, 0,
2649 V_SQ_ALU_SRC_LITERAL, param * 16);
2650 if (r)
2651 return r;
2652 }
2653
2654 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2655 temp_reg, 2,
2656 temp_reg, param ? 1 : 0,
2657 V_SQ_ALU_SRC_LITERAL, 8);
2658 if (r)
2659 return r;
2660
2661
2662 for (j = 0; j < 2; j++) {
2663 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2665 alu.op = LDS_OP3_LDS_WRITE_REL;
2666 alu.src[0].sel = temp_reg;
2667 alu.src[0].chan = chan;
2668 alu.src[1].sel = ctx->shader->output[i].gpr;
2669 alu.src[1].chan = j * 2;
2670 alu.src[2].sel = ctx->shader->output[i].gpr;
2671 alu.src[2].chan = (j * 2) + 1;
2672 alu.last = 1;
2673 alu.dst.chan = 0;
2674 alu.lds_idx = 1;
2675 alu.is_lds_idx_op = true;
2676 r = r600_bytecode_add_alu(ctx->bc, &alu);
2677 if (r)
2678 return r;
2679 }
2680 }
2681 return 0;
2682 }
2683
2684 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2685 {
2686 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2687 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2688 int i, r, lasti;
2689 int temp_reg = r600_get_temp(ctx);
2690 struct r600_bytecode_alu alu;
2691 unsigned write_mask = dst->Register.WriteMask;
2692
2693 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2694 return 0;
2695
2696 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2697 if (r)
2698 return r;
2699
2700 /* the base address is now in temp.x */
2701 r = r600_get_byte_address(ctx, temp_reg,
2702 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2703 if (r)
2704 return r;
2705
2706 /* LDS write */
2707 lasti = tgsi_last_instruction(write_mask);
2708 for (i = 1; i <= lasti; i++) {
2709
2710 if (!(write_mask & (1 << i)))
2711 continue;
2712 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2713 temp_reg, i,
2714 temp_reg, 0,
2715 V_SQ_ALU_SRC_LITERAL, 4 * i);
2716 if (r)
2717 return r;
2718 }
2719
2720 for (i = 0; i <= lasti; i++) {
2721 if (!(write_mask & (1 << i)))
2722 continue;
2723
2724 if ((i == 0 && ((write_mask & 3) == 3)) ||
2725 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2727 alu.op = LDS_OP3_LDS_WRITE_REL;
2728 alu.src[0].sel = temp_reg;
2729 alu.src[0].chan = i;
2730
2731 alu.src[1].sel = dst->Register.Index;
2732 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2733 alu.src[1].chan = i;
2734
2735 alu.src[2].sel = dst->Register.Index;
2736 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2737 alu.src[2].chan = i + 1;
2738 alu.lds_idx = 1;
2739 alu.dst.chan = 0;
2740 alu.last = 1;
2741 alu.is_lds_idx_op = true;
2742 r = r600_bytecode_add_alu(ctx->bc, &alu);
2743 if (r)
2744 return r;
2745 i += 1;
2746 continue;
2747 }
2748 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2749 alu.op = LDS_OP2_LDS_WRITE;
2750 alu.src[0].sel = temp_reg;
2751 alu.src[0].chan = i;
2752
2753 alu.src[1].sel = dst->Register.Index;
2754 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2755 alu.src[1].chan = i;
2756
2757 alu.src[2].sel = V_SQ_ALU_SRC_0;
2758 alu.dst.chan = 0;
2759 alu.last = 1;
2760 alu.is_lds_idx_op = true;
2761 r = r600_bytecode_add_alu(ctx->bc, &alu);
2762 if (r)
2763 return r;
2764 }
2765 return 0;
2766 }
2767
2768 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2769 int output_idx)
2770 {
2771 int param;
2772 unsigned temp_reg = r600_get_temp(ctx);
2773 unsigned name = ctx->shader->output[output_idx].name;
2774 int dreg = ctx->shader->output[output_idx].gpr;
2775 int r;
2776
2777 param = r600_get_lds_unique_index(name, 0);
2778 r = get_lds_offset0(ctx, 1, temp_reg, true);
2779 if (r)
2780 return r;
2781
2782 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2783 temp_reg, 0,
2784 temp_reg, 0,
2785 V_SQ_ALU_SRC_LITERAL, param * 16);
2786 if (r)
2787 return r;
2788
2789 do_lds_fetch_values(ctx, temp_reg, dreg);
2790 return 0;
2791 }
2792
2793 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2794 {
2795 unsigned i;
2796 int stride, outer_comps, inner_comps;
2797 int tessinner_idx = -1, tessouter_idx = -1;
2798 int r;
2799 int temp_reg = r600_get_temp(ctx);
2800 int treg[3] = {-1, -1, -1};
2801 struct r600_bytecode_alu alu;
2802 struct r600_bytecode_cf *cf_jump, *cf_pop;
2803
2804 /* only execute factor emission for invocation 0 */
2805 /* PRED_SETE_INT __, R0.x, 0 */
2806 memset(&alu, 0, sizeof(alu));
2807 alu.op = ALU_OP2_PRED_SETE_INT;
2808 alu.src[0].chan = 2;
2809 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2810 alu.execute_mask = 1;
2811 alu.update_pred = 1;
2812 alu.last = 1;
2813 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2814
2815 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2816 cf_jump = ctx->bc->cf_last;
2817
2818 treg[0] = r600_get_temp(ctx);
2819 switch (ctx->shader->tcs_prim_mode) {
2820 case PIPE_PRIM_LINES:
2821 stride = 8; /* 2 dwords, 1 vec2 store */
2822 outer_comps = 2;
2823 inner_comps = 0;
2824 break;
2825 case PIPE_PRIM_TRIANGLES:
2826 stride = 16; /* 4 dwords, 1 vec4 store */
2827 outer_comps = 3;
2828 inner_comps = 1;
2829 treg[1] = r600_get_temp(ctx);
2830 break;
2831 case PIPE_PRIM_QUADS:
2832 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2833 outer_comps = 4;
2834 inner_comps = 2;
2835 treg[1] = r600_get_temp(ctx);
2836 treg[2] = r600_get_temp(ctx);
2837 break;
2838 default:
2839 assert(0);
2840 return -1;
2841 }
2842
2843 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2844 /* TF_WRITE takes index in R.x, value in R.y */
2845 for (i = 0; i < ctx->shader->noutput; i++) {
2846 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2847 tessinner_idx = i;
2848 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2849 tessouter_idx = i;
2850 }
2851
2852 if (tessouter_idx == -1)
2853 return -1;
2854
2855 if (tessinner_idx == -1 && inner_comps)
2856 return -1;
2857
2858 if (tessouter_idx != -1) {
2859 r = r600_tess_factor_read(ctx, tessouter_idx);
2860 if (r)
2861 return r;
2862 }
2863
2864 if (tessinner_idx != -1) {
2865 r = r600_tess_factor_read(ctx, tessinner_idx);
2866 if (r)
2867 return r;
2868 }
2869
2870 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2871 /* r.x = relpatchid(r0.y) * tf_stride */
2872
2873 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2874 /* add incoming r0.w to it: t.x = t.x + r0.w */
2875 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2876 temp_reg, 0,
2877 0, 1,
2878 V_SQ_ALU_SRC_LITERAL, stride,
2879 0, 3);
2880 if (r)
2881 return r;
2882
2883 for (i = 0; i < outer_comps + inner_comps; i++) {
2884 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2885 int out_comp = i >= outer_comps ? i - outer_comps : i;
2886
2887 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2888 if (out_comp == 1)
2889 out_comp = 0;
2890 else if (out_comp == 0)
2891 out_comp = 1;
2892 }
2893
2894 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2895 treg[i / 2], (2 * (i % 2)),
2896 temp_reg, 0,
2897 V_SQ_ALU_SRC_LITERAL, 4 * i);
2898 if (r)
2899 return r;
2900 r = single_alu_op2(ctx, ALU_OP1_MOV,
2901 treg[i / 2], 1 + (2 * (i%2)),
2902 ctx->shader->output[out_idx].gpr, out_comp,
2903 0, 0);
2904 if (r)
2905 return r;
2906 }
2907 for (i = 0; i < outer_comps + inner_comps; i++) {
2908 struct r600_bytecode_gds gds;
2909
2910 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2911 gds.src_gpr = treg[i / 2];
2912 gds.src_sel_x = 2 * (i % 2);
2913 gds.src_sel_y = 1 + (2 * (i % 2));
2914 gds.src_sel_z = 4;
2915 gds.dst_sel_x = 7;
2916 gds.dst_sel_y = 7;
2917 gds.dst_sel_z = 7;
2918 gds.dst_sel_w = 7;
2919 gds.op = FETCH_OP_TF_WRITE;
2920 r = r600_bytecode_add_gds(ctx->bc, &gds);
2921 if (r)
2922 return r;
2923 }
2924
2925 // Patch up jump label
2926 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2927 cf_pop = ctx->bc->cf_last;
2928
2929 cf_jump->cf_addr = cf_pop->id + 2;
2930 cf_jump->pop_count = 1;
2931 cf_pop->cf_addr = cf_pop->id + 2;
2932 cf_pop->pop_count = 1;
2933
2934 return 0;
2935 }
2936
2937 static int r600_shader_from_tgsi(struct r600_context *rctx,
2938 struct r600_pipe_shader *pipeshader,
2939 union r600_shader_key key)
2940 {
2941 struct r600_screen *rscreen = rctx->screen;
2942 struct r600_shader *shader = &pipeshader->shader;
2943 struct tgsi_token *tokens = pipeshader->selector->tokens;
2944 struct pipe_stream_output_info so = pipeshader->selector->so;
2945 struct tgsi_full_immediate *immediate;
2946 struct r600_shader_ctx ctx;
2947 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
2948 unsigned output_done, noutput;
2949 unsigned opcode;
2950 int i, j, k, r = 0;
2951 int next_param_base = 0, next_clip_base;
2952 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
2953 bool indirect_gprs;
2954 bool ring_outputs = false;
2955 bool lds_outputs = false;
2956 bool lds_inputs = false;
2957 bool pos_emitted = false;
2958
2959 ctx.bc = &shader->bc;
2960 ctx.shader = shader;
2961 ctx.native_integers = true;
2962
2963 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
2964 rscreen->has_compressed_msaa_texturing);
2965 ctx.tokens = tokens;
2966 tgsi_scan_shader(tokens, &ctx.info);
2967 shader->indirect_files = ctx.info.indirect_files;
2968
2969 shader->uses_doubles = ctx.info.uses_doubles;
2970 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
2971 shader->nsys_inputs = 0;
2972
2973 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
2974 tgsi_parse_init(&ctx.parse, tokens);
2975 ctx.type = ctx.info.processor;
2976 shader->processor_type = ctx.type;
2977 ctx.bc->type = shader->processor_type;
2978
2979 switch (ctx.type) {
2980 case PIPE_SHADER_VERTEX:
2981 shader->vs_as_gs_a = key.vs.as_gs_a;
2982 shader->vs_as_es = key.vs.as_es;
2983 shader->vs_as_ls = key.vs.as_ls;
2984 shader->atomic_base = key.vs.first_atomic_counter;
2985 if (shader->vs_as_es)
2986 ring_outputs = true;
2987 if (shader->vs_as_ls)
2988 lds_outputs = true;
2989 break;
2990 case PIPE_SHADER_GEOMETRY:
2991 ring_outputs = true;
2992 shader->atomic_base = key.gs.first_atomic_counter;
2993 break;
2994 case PIPE_SHADER_TESS_CTRL:
2995 shader->tcs_prim_mode = key.tcs.prim_mode;
2996 shader->atomic_base = key.tcs.first_atomic_counter;
2997 lds_outputs = true;
2998 lds_inputs = true;
2999 break;
3000 case PIPE_SHADER_TESS_EVAL:
3001 shader->tes_as_es = key.tes.as_es;
3002 shader->atomic_base = key.tes.first_atomic_counter;
3003 lds_inputs = true;
3004 if (shader->tes_as_es)
3005 ring_outputs = true;
3006 break;
3007 case PIPE_SHADER_FRAGMENT:
3008 shader->two_side = key.ps.color_two_side;
3009 shader->atomic_base = key.ps.first_atomic_counter;
3010 break;
3011 default:
3012 break;
3013 }
3014
3015 if (shader->vs_as_es || shader->tes_as_es) {
3016 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3017 } else {
3018 ctx.gs_for_vs = NULL;
3019 }
3020
3021 ctx.next_ring_offset = 0;
3022 ctx.gs_out_ring_offset = 0;
3023 ctx.gs_next_vertex = 0;
3024 ctx.gs_stream_output_info = &so;
3025
3026 ctx.face_gpr = -1;
3027 ctx.fixed_pt_position_gpr = -1;
3028 ctx.fragcoord_input = -1;
3029 ctx.colors_used = 0;
3030 ctx.clip_vertex_write = 0;
3031
3032 shader->nr_ps_color_exports = 0;
3033 shader->nr_ps_max_color_exports = 0;
3034
3035
3036 /* register allocations */
3037 /* Values [0,127] correspond to GPR[0..127].
3038 * Values [128,159] correspond to constant buffer bank 0
3039 * Values [160,191] correspond to constant buffer bank 1
3040 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3041 * Values [256,287] correspond to constant buffer bank 2 (EG)
3042 * Values [288,319] correspond to constant buffer bank 3 (EG)
3043 * Other special values are shown in the list below.
3044 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3045 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3046 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3047 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3048 * 248 SQ_ALU_SRC_0: special constant 0.0.
3049 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3050 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3051 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3052 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3053 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3054 * 254 SQ_ALU_SRC_PV: previous vector result.
3055 * 255 SQ_ALU_SRC_PS: previous scalar result.
3056 */
3057 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3058 ctx.file_offset[i] = 0;
3059 }
3060
3061 if (ctx.type == PIPE_SHADER_VERTEX) {
3062
3063 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3064 if (ctx.info.num_inputs)
3065 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3066 }
3067 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3068 if (ctx.bc->chip_class >= EVERGREEN)
3069 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3070 else
3071 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3072 }
3073 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3074 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3075 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3076 }
3077 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3078 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3079 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3080 bool add_tesscoord = false, add_tess_inout = false;
3081 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3082 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3083 /* if we have tesscoord save one reg */
3084 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3085 add_tesscoord = true;
3086 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3087 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3088 add_tess_inout = true;
3089 }
3090 if (add_tesscoord || add_tess_inout)
3091 ctx.file_offset[TGSI_FILE_INPUT]++;
3092 if (add_tess_inout)
3093 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3094 }
3095
3096 ctx.file_offset[TGSI_FILE_OUTPUT] =
3097 ctx.file_offset[TGSI_FILE_INPUT] +
3098 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3099 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3100 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3101
3102 /* Outside the GPR range. This will be translated to one of the
3103 * kcache banks later. */
3104 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3105
3106 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3107 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3108 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3109 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3110 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3111
3112 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3113 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3114 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3115 ctx.temp_reg = ctx.bc->ar_reg + 5;
3116 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3117 ctx.tess_input_info = 0;
3118 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3119 ctx.temp_reg = ctx.bc->ar_reg + 4;
3120 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3121 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3122 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3123 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3124 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3125 ctx.temp_reg = ctx.bc->ar_reg + 7;
3126 } else {
3127 ctx.temp_reg = ctx.bc->ar_reg + 3;
3128 }
3129
3130 shader->max_arrays = 0;
3131 shader->num_arrays = 0;
3132 if (indirect_gprs) {
3133
3134 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3135 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3136 ctx.file_offset[TGSI_FILE_OUTPUT] -
3137 ctx.file_offset[TGSI_FILE_INPUT],
3138 0x0F);
3139 }
3140 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3141 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3142 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3143 ctx.file_offset[TGSI_FILE_OUTPUT],
3144 0x0F);
3145 }
3146 }
3147
3148 ctx.nliterals = 0;
3149 ctx.literals = NULL;
3150
3151 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3152 ctx.info.colors_written == 1;
3153 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3154 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3155
3156 if (shader->vs_as_gs_a)
3157 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3158
3159 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3160 r600_fetch_tess_io_info(&ctx);
3161
3162 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3163 tgsi_parse_token(&ctx.parse);
3164 switch (ctx.parse.FullToken.Token.Type) {
3165 case TGSI_TOKEN_TYPE_IMMEDIATE:
3166 immediate = &ctx.parse.FullToken.FullImmediate;
3167 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3168 if(ctx.literals == NULL) {
3169 r = -ENOMEM;
3170 goto out_err;
3171 }
3172 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3173 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3174 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3175 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3176 ctx.nliterals++;
3177 break;
3178 case TGSI_TOKEN_TYPE_DECLARATION:
3179 r = tgsi_declaration(&ctx);
3180 if (r)
3181 goto out_err;
3182 break;
3183 case TGSI_TOKEN_TYPE_INSTRUCTION:
3184 case TGSI_TOKEN_TYPE_PROPERTY:
3185 break;
3186 default:
3187 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3188 r = -EINVAL;
3189 goto out_err;
3190 }
3191 }
3192
3193 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3194 shader->ring_item_sizes[1] = 0;
3195 shader->ring_item_sizes[2] = 0;
3196 shader->ring_item_sizes[3] = 0;
3197
3198 /* Process two side if needed */
3199 if (shader->two_side && ctx.colors_used) {
3200 int i, count = ctx.shader->ninput;
3201 unsigned next_lds_loc = ctx.shader->nlds;
3202
3203 /* additional inputs will be allocated right after the existing inputs,
3204 * we won't need them after the color selection, so we don't need to
3205 * reserve these gprs for the rest of the shader code and to adjust
3206 * output offsets etc. */
3207 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3208 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3209
3210 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3211 if (ctx.face_gpr == -1) {
3212 i = ctx.shader->ninput++;
3213 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3214 ctx.shader->input[i].spi_sid = 0;
3215 ctx.shader->input[i].gpr = gpr++;
3216 ctx.face_gpr = ctx.shader->input[i].gpr;
3217 }
3218
3219 for (i = 0; i < count; i++) {
3220 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3221 int ni = ctx.shader->ninput++;
3222 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3223 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3224 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3225 ctx.shader->input[ni].gpr = gpr++;
3226 // TGSI to LLVM needs to know the lds position of inputs.
3227 // Non LLVM path computes it later (in process_twoside_color)
3228 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3229 ctx.shader->input[i].back_color_input = ni;
3230 if (ctx.bc->chip_class >= EVERGREEN) {
3231 if ((r = evergreen_interp_input(&ctx, ni)))
3232 return r;
3233 }
3234 }
3235 }
3236 }
3237
3238 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3239 shader->nr_ps_max_color_exports = 8;
3240
3241 if (ctx.fragcoord_input >= 0) {
3242 if (ctx.bc->chip_class == CAYMAN) {
3243 for (j = 0 ; j < 4; j++) {
3244 struct r600_bytecode_alu alu;
3245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3246 alu.op = ALU_OP1_RECIP_IEEE;
3247 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3248 alu.src[0].chan = 3;
3249
3250 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3251 alu.dst.chan = j;
3252 alu.dst.write = (j == 3);
3253 alu.last = 1;
3254 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3255 return r;
3256 }
3257 } else {
3258 struct r600_bytecode_alu alu;
3259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3260 alu.op = ALU_OP1_RECIP_IEEE;
3261 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3262 alu.src[0].chan = 3;
3263
3264 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3265 alu.dst.chan = 3;
3266 alu.dst.write = 1;
3267 alu.last = 1;
3268 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3269 return r;
3270 }
3271 }
3272
3273 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3274 struct r600_bytecode_alu alu;
3275 int r;
3276
3277 /* GS thread with no output workaround - emit a cut at start of GS */
3278 if (ctx.bc->chip_class == R600)
3279 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3280
3281 for (j = 0; j < 4; j++) {
3282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3283 alu.op = ALU_OP1_MOV;
3284 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3285 alu.src[0].value = 0;
3286 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3287 alu.dst.write = 1;
3288 alu.last = 1;
3289 r = r600_bytecode_add_alu(ctx.bc, &alu);
3290 if (r)
3291 return r;
3292 }
3293 }
3294
3295 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3296 r600_fetch_tess_io_info(&ctx);
3297
3298 if (shader->two_side && ctx.colors_used) {
3299 if ((r = process_twoside_color_inputs(&ctx)))
3300 return r;
3301 }
3302
3303 tgsi_parse_init(&ctx.parse, tokens);
3304 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3305 tgsi_parse_token(&ctx.parse);
3306 switch (ctx.parse.FullToken.Token.Type) {
3307 case TGSI_TOKEN_TYPE_INSTRUCTION:
3308 r = tgsi_is_supported(&ctx);
3309 if (r)
3310 goto out_err;
3311 ctx.max_driver_temp_used = 0;
3312 /* reserve first tmp for everyone */
3313 r600_get_temp(&ctx);
3314
3315 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3316 if ((r = tgsi_split_constant(&ctx)))
3317 goto out_err;
3318 if ((r = tgsi_split_literal_constant(&ctx)))
3319 goto out_err;
3320 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3321 if ((r = tgsi_split_gs_inputs(&ctx)))
3322 goto out_err;
3323 } else if (lds_inputs) {
3324 if ((r = tgsi_split_lds_inputs(&ctx)))
3325 goto out_err;
3326 }
3327 if (ctx.bc->chip_class == CAYMAN)
3328 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3329 else if (ctx.bc->chip_class >= EVERGREEN)
3330 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3331 else
3332 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3333 r = ctx.inst_info->process(&ctx);
3334 if (r)
3335 goto out_err;
3336
3337 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3338 r = r600_store_tcs_output(&ctx);
3339 if (r)
3340 goto out_err;
3341 }
3342 break;
3343 default:
3344 break;
3345 }
3346 }
3347
3348 /* Reset the temporary register counter. */
3349 ctx.max_driver_temp_used = 0;
3350
3351 noutput = shader->noutput;
3352
3353 if (!ring_outputs && ctx.clip_vertex_write) {
3354 unsigned clipdist_temp[2];
3355
3356 clipdist_temp[0] = r600_get_temp(&ctx);
3357 clipdist_temp[1] = r600_get_temp(&ctx);
3358
3359 /* need to convert a clipvertex write into clipdistance writes and not export
3360 the clip vertex anymore */
3361
3362 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3363 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3364 shader->output[noutput].gpr = clipdist_temp[0];
3365 noutput++;
3366 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3367 shader->output[noutput].gpr = clipdist_temp[1];
3368 noutput++;
3369
3370 /* reset spi_sid for clipvertex output to avoid confusing spi */
3371 shader->output[ctx.cv_output].spi_sid = 0;
3372
3373 shader->clip_dist_write = 0xFF;
3374
3375 for (i = 0; i < 8; i++) {
3376 int oreg = i >> 2;
3377 int ochan = i & 3;
3378
3379 for (j = 0; j < 4; j++) {
3380 struct r600_bytecode_alu alu;
3381 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3382 alu.op = ALU_OP2_DOT4;
3383 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3384 alu.src[0].chan = j;
3385
3386 alu.src[1].sel = 512 + i;
3387 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3388 alu.src[1].chan = j;
3389
3390 alu.dst.sel = clipdist_temp[oreg];
3391 alu.dst.chan = j;
3392 alu.dst.write = (j == ochan);
3393 if (j == 3)
3394 alu.last = 1;
3395 r = r600_bytecode_add_alu(ctx.bc, &alu);
3396 if (r)
3397 return r;
3398 }
3399 }
3400 }
3401
3402 /* Add stream outputs. */
3403 if (so.num_outputs) {
3404 bool emit = false;
3405 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3406 emit = true;
3407 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3408 emit = true;
3409 if (emit)
3410 emit_streamout(&ctx, &so, -1, NULL);
3411 }
3412 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3413 convert_edgeflag_to_int(&ctx);
3414
3415 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3416 r600_emit_tess_factor(&ctx);
3417
3418 if (lds_outputs) {
3419 if (ctx.type == PIPE_SHADER_VERTEX) {
3420 if (ctx.shader->noutput)
3421 emit_lds_vs_writes(&ctx);
3422 }
3423 } else if (ring_outputs) {
3424 if (shader->vs_as_es || shader->tes_as_es) {
3425 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3426 ctx.gs_export_gpr_tregs[1] = -1;
3427 ctx.gs_export_gpr_tregs[2] = -1;
3428 ctx.gs_export_gpr_tregs[3] = -1;
3429
3430 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3431 }
3432 } else {
3433 /* Export output */
3434 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3435
3436 for (i = 0, j = 0; i < noutput; i++, j++) {
3437 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3438 output[j].gpr = shader->output[i].gpr;
3439 output[j].elem_size = 3;
3440 output[j].swizzle_x = 0;
3441 output[j].swizzle_y = 1;
3442 output[j].swizzle_z = 2;
3443 output[j].swizzle_w = 3;
3444 output[j].burst_count = 1;
3445 output[j].type = -1;
3446 output[j].op = CF_OP_EXPORT;
3447 switch (ctx.type) {
3448 case PIPE_SHADER_VERTEX:
3449 case PIPE_SHADER_TESS_EVAL:
3450 switch (shader->output[i].name) {
3451 case TGSI_SEMANTIC_POSITION:
3452 output[j].array_base = 60;
3453 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3454 pos_emitted = true;
3455 break;
3456
3457 case TGSI_SEMANTIC_PSIZE:
3458 output[j].array_base = 61;
3459 output[j].swizzle_y = 7;
3460 output[j].swizzle_z = 7;
3461 output[j].swizzle_w = 7;
3462 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3463 pos_emitted = true;
3464 break;
3465 case TGSI_SEMANTIC_EDGEFLAG:
3466 output[j].array_base = 61;
3467 output[j].swizzle_x = 7;
3468 output[j].swizzle_y = 0;
3469 output[j].swizzle_z = 7;
3470 output[j].swizzle_w = 7;
3471 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3472 pos_emitted = true;
3473 break;
3474 case TGSI_SEMANTIC_LAYER:
3475 /* spi_sid is 0 for outputs that are
3476 * not consumed by PS */
3477 if (shader->output[i].spi_sid) {
3478 output[j].array_base = next_param_base++;
3479 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3480 j++;
3481 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3482 }
3483 output[j].array_base = 61;
3484 output[j].swizzle_x = 7;
3485 output[j].swizzle_y = 7;
3486 output[j].swizzle_z = 0;
3487 output[j].swizzle_w = 7;
3488 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3489 pos_emitted = true;
3490 break;
3491 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3492 /* spi_sid is 0 for outputs that are
3493 * not consumed by PS */
3494 if (shader->output[i].spi_sid) {
3495 output[j].array_base = next_param_base++;
3496 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3497 j++;
3498 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3499 }
3500 output[j].array_base = 61;
3501 output[j].swizzle_x = 7;
3502 output[j].swizzle_y = 7;
3503 output[j].swizzle_z = 7;
3504 output[j].swizzle_w = 0;
3505 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3506 pos_emitted = true;
3507 break;
3508 case TGSI_SEMANTIC_CLIPVERTEX:
3509 j--;
3510 break;
3511 case TGSI_SEMANTIC_CLIPDIST:
3512 output[j].array_base = next_clip_base++;
3513 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3514 pos_emitted = true;
3515 /* spi_sid is 0 for clipdistance outputs that were generated
3516 * for clipvertex - we don't need to pass them to PS */
3517 if (shader->output[i].spi_sid) {
3518 j++;
3519 /* duplicate it as PARAM to pass to the pixel shader */
3520 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3521 output[j].array_base = next_param_base++;
3522 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3523 }
3524 break;
3525 case TGSI_SEMANTIC_FOG:
3526 output[j].swizzle_y = 4; /* 0 */
3527 output[j].swizzle_z = 4; /* 0 */
3528 output[j].swizzle_w = 5; /* 1 */
3529 break;
3530 case TGSI_SEMANTIC_PRIMID:
3531 output[j].swizzle_x = 2;
3532 output[j].swizzle_y = 4; /* 0 */
3533 output[j].swizzle_z = 4; /* 0 */
3534 output[j].swizzle_w = 4; /* 0 */
3535 break;
3536 }
3537
3538 break;
3539 case PIPE_SHADER_FRAGMENT:
3540 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3541 /* never export more colors than the number of CBs */
3542 if (shader->output[i].sid >= max_color_exports) {
3543 /* skip export */
3544 j--;
3545 continue;
3546 }
3547 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3548 output[j].array_base = shader->output[i].sid;
3549 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3550 shader->nr_ps_color_exports++;
3551 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3552 for (k = 1; k < max_color_exports; k++) {
3553 j++;
3554 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3555 output[j].gpr = shader->output[i].gpr;
3556 output[j].elem_size = 3;
3557 output[j].swizzle_x = 0;
3558 output[j].swizzle_y = 1;
3559 output[j].swizzle_z = 2;
3560 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3561 output[j].burst_count = 1;
3562 output[j].array_base = k;
3563 output[j].op = CF_OP_EXPORT;
3564 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3565 shader->nr_ps_color_exports++;
3566 }
3567 }
3568 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3569 output[j].array_base = 61;
3570 output[j].swizzle_x = 2;
3571 output[j].swizzle_y = 7;
3572 output[j].swizzle_z = output[j].swizzle_w = 7;
3573 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3574 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3575 output[j].array_base = 61;
3576 output[j].swizzle_x = 7;
3577 output[j].swizzle_y = 1;
3578 output[j].swizzle_z = output[j].swizzle_w = 7;
3579 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3580 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3581 output[j].array_base = 61;
3582 output[j].swizzle_x = 7;
3583 output[j].swizzle_y = 7;
3584 output[j].swizzle_z = 0;
3585 output[j].swizzle_w = 7;
3586 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3587 } else {
3588 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3589 r = -EINVAL;
3590 goto out_err;
3591 }
3592 break;
3593 case PIPE_SHADER_TESS_CTRL:
3594 break;
3595 default:
3596 R600_ERR("unsupported processor type %d\n", ctx.type);
3597 r = -EINVAL;
3598 goto out_err;
3599 }
3600
3601 if (output[j].type==-1) {
3602 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3603 output[j].array_base = next_param_base++;
3604 }
3605 }
3606
3607 /* add fake position export */
3608 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3609 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3610 output[j].gpr = 0;
3611 output[j].elem_size = 3;
3612 output[j].swizzle_x = 7;
3613 output[j].swizzle_y = 7;
3614 output[j].swizzle_z = 7;
3615 output[j].swizzle_w = 7;
3616 output[j].burst_count = 1;
3617 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3618 output[j].array_base = 60;
3619 output[j].op = CF_OP_EXPORT;
3620 j++;
3621 }
3622
3623 /* add fake param output for vertex shader if no param is exported */
3624 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3625 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3626 output[j].gpr = 0;
3627 output[j].elem_size = 3;
3628 output[j].swizzle_x = 7;
3629 output[j].swizzle_y = 7;
3630 output[j].swizzle_z = 7;
3631 output[j].swizzle_w = 7;
3632 output[j].burst_count = 1;
3633 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3634 output[j].array_base = 0;
3635 output[j].op = CF_OP_EXPORT;
3636 j++;
3637 }
3638
3639 /* add fake pixel export */
3640 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3641 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3642 output[j].gpr = 0;
3643 output[j].elem_size = 3;
3644 output[j].swizzle_x = 7;
3645 output[j].swizzle_y = 7;
3646 output[j].swizzle_z = 7;
3647 output[j].swizzle_w = 7;
3648 output[j].burst_count = 1;
3649 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3650 output[j].array_base = 0;
3651 output[j].op = CF_OP_EXPORT;
3652 j++;
3653 shader->nr_ps_color_exports++;
3654 }
3655
3656 noutput = j;
3657
3658 /* set export done on last export of each type */
3659 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3660 if (!(output_done & (1 << output[i].type))) {
3661 output_done |= (1 << output[i].type);
3662 output[i].op = CF_OP_EXPORT_DONE;
3663 }
3664 }
3665 /* add output to bytecode */
3666 for (i = 0; i < noutput; i++) {
3667 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3668 if (r)
3669 goto out_err;
3670 }
3671 }
3672
3673 /* add program end */
3674 if (ctx.bc->chip_class == CAYMAN)
3675 cm_bytecode_add_cf_end(ctx.bc);
3676 else {
3677 const struct cf_op_info *last = NULL;
3678
3679 if (ctx.bc->cf_last)
3680 last = r600_isa_cf(ctx.bc->cf_last->op);
3681
3682 /* alu clause instructions don't have EOP bit, so add NOP */
3683 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3684 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3685
3686 ctx.bc->cf_last->end_of_program = 1;
3687 }
3688
3689 /* check GPR limit - we have 124 = 128 - 4
3690 * (4 are reserved as alu clause temporary registers) */
3691 if (ctx.bc->ngpr > 124) {
3692 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3693 r = -ENOMEM;
3694 goto out_err;
3695 }
3696
3697 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3698 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3699 return r;
3700 }
3701
3702 free(ctx.literals);
3703 tgsi_parse_free(&ctx.parse);
3704 return 0;
3705 out_err:
3706 free(ctx.literals);
3707 tgsi_parse_free(&ctx.parse);
3708 return r;
3709 }
3710
3711 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3712 {
3713 const unsigned tgsi_opcode =
3714 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3715 R600_ERR("%s tgsi opcode unsupported\n",
3716 tgsi_get_opcode_name(tgsi_opcode));
3717 return -EINVAL;
3718 }
3719
3720 static int tgsi_end(struct r600_shader_ctx *ctx)
3721 {
3722 return 0;
3723 }
3724
3725 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3726 const struct r600_shader_src *shader_src,
3727 unsigned chan)
3728 {
3729 bc_src->sel = shader_src->sel;
3730 bc_src->chan = shader_src->swizzle[chan];
3731 bc_src->neg = shader_src->neg;
3732 bc_src->abs = shader_src->abs;
3733 bc_src->rel = shader_src->rel;
3734 bc_src->value = shader_src->value[bc_src->chan];
3735 bc_src->kc_bank = shader_src->kc_bank;
3736 bc_src->kc_rel = shader_src->kc_rel;
3737 }
3738
3739 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3740 {
3741 bc_src->abs = 1;
3742 bc_src->neg = 0;
3743 }
3744
3745 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3746 {
3747 bc_src->neg = !bc_src->neg;
3748 }
3749
3750 static void tgsi_dst(struct r600_shader_ctx *ctx,
3751 const struct tgsi_full_dst_register *tgsi_dst,
3752 unsigned swizzle,
3753 struct r600_bytecode_alu_dst *r600_dst)
3754 {
3755 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3756
3757 r600_dst->sel = tgsi_dst->Register.Index;
3758 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3759 r600_dst->chan = swizzle;
3760 r600_dst->write = 1;
3761 if (inst->Instruction.Saturate) {
3762 r600_dst->clamp = 1;
3763 }
3764 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3765 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3766 return;
3767 }
3768 }
3769 if (tgsi_dst->Register.Indirect)
3770 r600_dst->rel = V_SQ_REL_RELATIVE;
3771
3772 }
3773
3774 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3775 {
3776 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3777 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3778 struct r600_bytecode_alu alu;
3779 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3780 int use_tmp = 0;
3781
3782 if (singledest) {
3783 switch (write_mask) {
3784 case 0x1:
3785 write_mask = 0x3;
3786 break;
3787 case 0x2:
3788 use_tmp = 1;
3789 write_mask = 0x3;
3790 break;
3791 case 0x4:
3792 write_mask = 0xc;
3793 break;
3794 case 0x8:
3795 write_mask = 0xc;
3796 use_tmp = 3;
3797 break;
3798 }
3799 }
3800
3801 lasti = tgsi_last_instruction(write_mask);
3802 for (i = 0; i <= lasti; i++) {
3803
3804 if (!(write_mask & (1 << i)))
3805 continue;
3806
3807 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3808
3809 if (singledest) {
3810 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3811 if (use_tmp) {
3812 alu.dst.sel = ctx->temp_reg;
3813 alu.dst.chan = i;
3814 alu.dst.write = 1;
3815 }
3816 if (i == 1 || i == 3)
3817 alu.dst.write = 0;
3818 } else
3819 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3820
3821 alu.op = ctx->inst_info->op;
3822 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3823 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3824 } else if (!swap) {
3825 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3826 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3827 }
3828 } else {
3829 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3830 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3831 }
3832
3833 /* handle some special cases */
3834 if (i == 1 || i == 3) {
3835 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3836 case TGSI_OPCODE_DABS:
3837 r600_bytecode_src_set_abs(&alu.src[0]);
3838 break;
3839 default:
3840 break;
3841 }
3842 }
3843 if (i == lasti) {
3844 alu.last = 1;
3845 }
3846 r = r600_bytecode_add_alu(ctx->bc, &alu);
3847 if (r)
3848 return r;
3849 }
3850
3851 if (use_tmp) {
3852 write_mask = inst->Dst[0].Register.WriteMask;
3853
3854 /* move result from temp to dst */
3855 for (i = 0; i <= lasti; i++) {
3856 if (!(write_mask & (1 << i)))
3857 continue;
3858
3859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3860 alu.op = ALU_OP1_MOV;
3861 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3862 alu.src[0].sel = ctx->temp_reg;
3863 alu.src[0].chan = use_tmp - 1;
3864 alu.last = (i == lasti);
3865
3866 r = r600_bytecode_add_alu(ctx->bc, &alu);
3867 if (r)
3868 return r;
3869 }
3870 }
3871 return 0;
3872 }
3873
3874 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3875 {
3876 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3877 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3878 /* confirm writemasking */
3879 if ((write_mask & 0x3) != 0x3 &&
3880 (write_mask & 0xc) != 0xc) {
3881 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
3882 return -1;
3883 }
3884 return tgsi_op2_64_params(ctx, false, false);
3885 }
3886
3887 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
3888 {
3889 return tgsi_op2_64_params(ctx, true, false);
3890 }
3891
3892 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
3893 {
3894 return tgsi_op2_64_params(ctx, true, true);
3895 }
3896
3897 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
3898 {
3899 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3900 struct r600_bytecode_alu alu;
3901 int i, j, r;
3902 int lasti = 3;
3903 int tmp = r600_get_temp(ctx);
3904
3905 for (i = 0; i < lasti + 1; i++) {
3906
3907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3908 alu.op = ctx->inst_info->op;
3909 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3910 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
3911 }
3912
3913 if (inst->Dst[0].Register.WriteMask & (1 << i))
3914 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3915 else
3916 alu.dst.sel = tmp;
3917
3918 alu.dst.chan = i;
3919 alu.is_op3 = 1;
3920 if (i == lasti) {
3921 alu.last = 1;
3922 }
3923 r = r600_bytecode_add_alu(ctx->bc, &alu);
3924 if (r)
3925 return r;
3926 }
3927 return 0;
3928 }
3929
3930 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
3931 {
3932 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3933 struct r600_bytecode_alu alu;
3934 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3935 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3936 /* use temp register if trans_only and more than one dst component */
3937 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
3938 unsigned op = ctx->inst_info->op;
3939
3940 if (op == ALU_OP2_MUL_IEEE &&
3941 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
3942 op = ALU_OP2_MUL;
3943
3944 for (i = 0; i <= lasti; i++) {
3945 if (!(write_mask & (1 << i)))
3946 continue;
3947
3948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3949 if (use_tmp) {
3950 alu.dst.sel = ctx->temp_reg;
3951 alu.dst.chan = i;
3952 alu.dst.write = 1;
3953 } else
3954 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3955
3956 alu.op = op;
3957 if (!swap) {
3958 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3959 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3960 }
3961 } else {
3962 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3963 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3964 }
3965 if (i == lasti || trans_only) {
3966 alu.last = 1;
3967 }
3968 r = r600_bytecode_add_alu(ctx->bc, &alu);
3969 if (r)
3970 return r;
3971 }
3972
3973 if (use_tmp) {
3974 /* move result from temp to dst */
3975 for (i = 0; i <= lasti; i++) {
3976 if (!(write_mask & (1 << i)))
3977 continue;
3978
3979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3980 alu.op = ALU_OP1_MOV;
3981 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3982 alu.src[0].sel = ctx->temp_reg;
3983 alu.src[0].chan = i;
3984 alu.last = (i == lasti);
3985
3986 r = r600_bytecode_add_alu(ctx->bc, &alu);
3987 if (r)
3988 return r;
3989 }
3990 }
3991 return 0;
3992 }
3993
3994 static int tgsi_op2(struct r600_shader_ctx *ctx)
3995 {
3996 return tgsi_op2_s(ctx, 0, 0);
3997 }
3998
3999 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4000 {
4001 return tgsi_op2_s(ctx, 1, 0);
4002 }
4003
4004 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4005 {
4006 return tgsi_op2_s(ctx, 0, 1);
4007 }
4008
4009 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4010 {
4011 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4012 struct r600_bytecode_alu alu;
4013 int i, r;
4014 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4015
4016 for (i = 0; i < lasti + 1; i++) {
4017
4018 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4019 continue;
4020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4021 alu.op = ctx->inst_info->op;
4022
4023 alu.src[0].sel = V_SQ_ALU_SRC_0;
4024
4025 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4026
4027 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4028
4029 if (i == lasti) {
4030 alu.last = 1;
4031 }
4032 r = r600_bytecode_add_alu(ctx->bc, &alu);
4033 if (r)
4034 return r;
4035 }
4036 return 0;
4037
4038 }
4039
4040 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4041 {
4042 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4043 struct r600_bytecode_alu alu;
4044 int i, r;
4045 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4046
4047 for (i = 0; i < lasti + 1; i++) {
4048
4049 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4050 continue;
4051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4052 alu.op = ALU_OP1_MOV;
4053
4054 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4055
4056 if (i == 1 || i == 3)
4057 r600_bytecode_src_toggle_neg(&alu.src[0]);
4058 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4059
4060 if (i == lasti) {
4061 alu.last = 1;
4062 }
4063 r = r600_bytecode_add_alu(ctx->bc, &alu);
4064 if (r)
4065 return r;
4066 }
4067 return 0;
4068
4069 }
4070
4071 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4072 {
4073 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4074 struct r600_bytecode_alu alu;
4075 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4076 int i, j, r;
4077
4078 for (i = 0; i <= 3; i++) {
4079 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4080 alu.op = ctx->inst_info->op;
4081
4082 alu.dst.sel = ctx->temp_reg;
4083 alu.dst.chan = i;
4084 alu.dst.write = 1;
4085 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4086 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4087 }
4088
4089 if (i == 3)
4090 alu.last = 1;
4091
4092 r = r600_bytecode_add_alu(ctx->bc, &alu);
4093 if (r)
4094 return r;
4095 }
4096
4097 /* Replicate significand result across channels. */
4098 for (i = 0; i <= 3; i++) {
4099 if (!(write_mask & (1 << i)))
4100 continue;
4101
4102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4103 alu.op = ALU_OP1_MOV;
4104 alu.src[0].chan = (i & 1) + 2;
4105 alu.src[0].sel = ctx->temp_reg;
4106
4107 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4108 alu.dst.write = 1;
4109 alu.last = 1;
4110 r = r600_bytecode_add_alu(ctx->bc, &alu);
4111 if (r)
4112 return r;
4113 }
4114
4115 for (i = 0; i <= 3; i++) {
4116 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4117 /* MOV third channels to writemask dst1 */
4118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4119 alu.op = ALU_OP1_MOV;
4120 alu.src[0].chan = 1;
4121 alu.src[0].sel = ctx->temp_reg;
4122
4123 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4124 alu.last = 1;
4125 r = r600_bytecode_add_alu(ctx->bc, &alu);
4126 if (r)
4127 return r;
4128 break;
4129 }
4130 }
4131 return 0;
4132 }
4133
4134
4135 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4136 {
4137 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4138 struct r600_bytecode_alu alu;
4139 int i, r;
4140 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4141
4142 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4143 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4144
4145 for (i = 0; i <= (lasti+1)/2; i++) {
4146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4147 alu.op = ctx->inst_info->op;
4148
4149 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4150 alu.dst.sel = ctx->temp_reg;
4151 alu.dst.chan = i;
4152 alu.dst.write = 1;
4153 alu.last = 1;
4154
4155 r = r600_bytecode_add_alu(ctx->bc, &alu);
4156 if (r)
4157 return r;
4158 }
4159
4160 for (i = 0; i <= lasti; i++) {
4161 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4162 alu.op = ALU_OP1_FLT32_TO_FLT64;
4163
4164 alu.src[0].chan = i/2;
4165 if (i%2 == 0)
4166 alu.src[0].sel = ctx->temp_reg;
4167 else {
4168 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4169 alu.src[0].value = 0x0;
4170 }
4171 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4172 alu.last = i == lasti;
4173
4174 r = r600_bytecode_add_alu(ctx->bc, &alu);
4175 if (r)
4176 return r;
4177 }
4178
4179 return 0;
4180 }
4181
4182 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4183 {
4184 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4185 struct r600_bytecode_alu alu;
4186 int i, r;
4187 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4188
4189 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4190 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4191
4192 for (i = 0; i <= lasti; i++) {
4193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4194 alu.op = ALU_OP1_FLT64_TO_FLT32;
4195
4196 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4197 alu.dst.chan = i;
4198 alu.dst.sel = ctx->temp_reg;
4199 alu.dst.write = i%2 == 0;
4200 alu.last = i == lasti;
4201
4202 r = r600_bytecode_add_alu(ctx->bc, &alu);
4203 if (r)
4204 return r;
4205 }
4206
4207 for (i = 0; i <= (lasti+1)/2; i++) {
4208 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4209 alu.op = ctx->inst_info->op;
4210
4211 alu.src[0].chan = i*2;
4212 alu.src[0].sel = ctx->temp_reg;
4213 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4214 alu.last = 1;
4215
4216 r = r600_bytecode_add_alu(ctx->bc, &alu);
4217 if (r)
4218 return r;
4219 }
4220
4221 return 0;
4222 }
4223
4224 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4225 unsigned op,
4226 int dst_reg,
4227 struct r600_shader_src *src,
4228 bool abs)
4229 {
4230 struct r600_bytecode_alu alu;
4231 const int last_slot = 3;
4232 int r;
4233
4234 /* these have to write the result to X/Y by the looks of it */
4235 for (int i = 0 ; i < last_slot; i++) {
4236 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4237 alu.op = op;
4238
4239 r600_bytecode_src(&alu.src[0], src, 1);
4240 r600_bytecode_src(&alu.src[1], src, 0);
4241
4242 if (abs)
4243 r600_bytecode_src_set_abs(&alu.src[1]);
4244
4245 alu.dst.sel = dst_reg;
4246 alu.dst.chan = i;
4247 alu.dst.write = (i == 0 || i == 1);
4248
4249 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4250 alu.last = 1;
4251 r = r600_bytecode_add_alu(bc, &alu);
4252 if (r)
4253 return r;
4254 }
4255
4256 return 0;
4257 }
4258
4259 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4260 {
4261 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4262 int i, r;
4263 struct r600_bytecode_alu alu;
4264 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4265 int t1 = ctx->temp_reg;
4266
4267 /* should only be one src regs */
4268 assert(inst->Instruction.NumSrcRegs == 1);
4269
4270 /* only support one double at a time */
4271 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4272 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4273
4274 r = cayman_emit_unary_double_raw(
4275 ctx->bc, ctx->inst_info->op, t1,
4276 &ctx->src[0],
4277 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4278 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4279 if (r)
4280 return r;
4281
4282 for (i = 0 ; i <= lasti; i++) {
4283 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4284 continue;
4285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4286 alu.op = ALU_OP1_MOV;
4287 alu.src[0].sel = t1;
4288 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4289 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4290 alu.dst.write = 1;
4291 if (i == lasti)
4292 alu.last = 1;
4293 r = r600_bytecode_add_alu(ctx->bc, &alu);
4294 if (r)
4295 return r;
4296 }
4297 return 0;
4298 }
4299
4300 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4301 {
4302 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4303 int i, j, r;
4304 struct r600_bytecode_alu alu;
4305 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4306
4307 for (i = 0 ; i < last_slot; i++) {
4308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4309 alu.op = ctx->inst_info->op;
4310 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4311 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4312
4313 /* RSQ should take the absolute value of src */
4314 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4315 r600_bytecode_src_set_abs(&alu.src[j]);
4316 }
4317 }
4318 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4319 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4320
4321 if (i == last_slot - 1)
4322 alu.last = 1;
4323 r = r600_bytecode_add_alu(ctx->bc, &alu);
4324 if (r)
4325 return r;
4326 }
4327 return 0;
4328 }
4329
4330 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4331 {
4332 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4333 int i, j, k, r;
4334 struct r600_bytecode_alu alu;
4335 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4336 int t1 = ctx->temp_reg;
4337
4338 for (k = 0; k <= lasti; k++) {
4339 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4340 continue;
4341
4342 for (i = 0 ; i < 4; i++) {
4343 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4344 alu.op = ctx->inst_info->op;
4345 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4346 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4347 }
4348 alu.dst.sel = t1;
4349 alu.dst.chan = i;
4350 alu.dst.write = (i == k);
4351 if (i == 3)
4352 alu.last = 1;
4353 r = r600_bytecode_add_alu(ctx->bc, &alu);
4354 if (r)
4355 return r;
4356 }
4357 }
4358
4359 for (i = 0 ; i <= lasti; i++) {
4360 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4361 continue;
4362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4363 alu.op = ALU_OP1_MOV;
4364 alu.src[0].sel = t1;
4365 alu.src[0].chan = i;
4366 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4367 alu.dst.write = 1;
4368 if (i == lasti)
4369 alu.last = 1;
4370 r = r600_bytecode_add_alu(ctx->bc, &alu);
4371 if (r)
4372 return r;
4373 }
4374
4375 return 0;
4376 }
4377
4378
4379 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4380 {
4381 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4382 int i, j, k, r;
4383 struct r600_bytecode_alu alu;
4384 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4385 int t1 = ctx->temp_reg;
4386
4387 /* t1 would get overwritten below if we actually tried to
4388 * multiply two pairs of doubles at a time. */
4389 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4390 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4391
4392 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4393
4394 for (i = 0; i < 4; i++) {
4395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4396 alu.op = ctx->inst_info->op;
4397 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4398 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4399 }
4400 alu.dst.sel = t1;
4401 alu.dst.chan = i;
4402 alu.dst.write = 1;
4403 if (i == 3)
4404 alu.last = 1;
4405 r = r600_bytecode_add_alu(ctx->bc, &alu);
4406 if (r)
4407 return r;
4408 }
4409
4410 for (i = 0; i <= lasti; i++) {
4411 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4412 continue;
4413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4414 alu.op = ALU_OP1_MOV;
4415 alu.src[0].sel = t1;
4416 alu.src[0].chan = i;
4417 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4418 alu.dst.write = 1;
4419 if (i == lasti)
4420 alu.last = 1;
4421 r = r600_bytecode_add_alu(ctx->bc, &alu);
4422 if (r)
4423 return r;
4424 }
4425
4426 return 0;
4427 }
4428
4429 /*
4430 * Emit RECIP_64 + MUL_64 to implement division.
4431 */
4432 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4433 {
4434 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4435 int r;
4436 struct r600_bytecode_alu alu;
4437 int t1 = ctx->temp_reg;
4438 int k;
4439
4440 /* Only support one double at a time. This is the same constraint as
4441 * in DMUL lowering. */
4442 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4443 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4444
4445 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4446
4447 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4448 if (r)
4449 return r;
4450
4451 for (int i = 0; i < 4; i++) {
4452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4453 alu.op = ALU_OP2_MUL_64;
4454
4455 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4456
4457 alu.src[1].sel = t1;
4458 alu.src[1].chan = (i == 3) ? 0 : 1;
4459
4460 alu.dst.sel = t1;
4461 alu.dst.chan = i;
4462 alu.dst.write = 1;
4463 if (i == 3)
4464 alu.last = 1;
4465 r = r600_bytecode_add_alu(ctx->bc, &alu);
4466 if (r)
4467 return r;
4468 }
4469
4470 for (int i = 0; i < 2; i++) {
4471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4472 alu.op = ALU_OP1_MOV;
4473 alu.src[0].sel = t1;
4474 alu.src[0].chan = i;
4475 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4476 alu.dst.write = 1;
4477 if (i == 1)
4478 alu.last = 1;
4479 r = r600_bytecode_add_alu(ctx->bc, &alu);
4480 if (r)
4481 return r;
4482 }
4483 return 0;
4484 }
4485
4486 /*
4487 * r600 - trunc to -PI..PI range
4488 * r700 - normalize by dividing by 2PI
4489 * see fdo bug 27901
4490 */
4491 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4492 {
4493 int r;
4494 struct r600_bytecode_alu alu;
4495
4496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4497 alu.op = ALU_OP3_MULADD;
4498 alu.is_op3 = 1;
4499
4500 alu.dst.chan = 0;
4501 alu.dst.sel = ctx->temp_reg;
4502 alu.dst.write = 1;
4503
4504 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4505
4506 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4507 alu.src[1].chan = 0;
4508 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4509 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4510 alu.src[2].chan = 0;
4511 alu.last = 1;
4512 r = r600_bytecode_add_alu(ctx->bc, &alu);
4513 if (r)
4514 return r;
4515
4516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4517 alu.op = ALU_OP1_FRACT;
4518
4519 alu.dst.chan = 0;
4520 alu.dst.sel = ctx->temp_reg;
4521 alu.dst.write = 1;
4522
4523 alu.src[0].sel = ctx->temp_reg;
4524 alu.src[0].chan = 0;
4525 alu.last = 1;
4526 r = r600_bytecode_add_alu(ctx->bc, &alu);
4527 if (r)
4528 return r;
4529
4530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4531 alu.op = ALU_OP3_MULADD;
4532 alu.is_op3 = 1;
4533
4534 alu.dst.chan = 0;
4535 alu.dst.sel = ctx->temp_reg;
4536 alu.dst.write = 1;
4537
4538 alu.src[0].sel = ctx->temp_reg;
4539 alu.src[0].chan = 0;
4540
4541 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4542 alu.src[1].chan = 0;
4543 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4544 alu.src[2].chan = 0;
4545
4546 if (ctx->bc->chip_class == R600) {
4547 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4548 alu.src[2].value = u_bitcast_f2u(-M_PI);
4549 } else {
4550 alu.src[1].sel = V_SQ_ALU_SRC_1;
4551 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4552 alu.src[2].neg = 1;
4553 }
4554
4555 alu.last = 1;
4556 r = r600_bytecode_add_alu(ctx->bc, &alu);
4557 if (r)
4558 return r;
4559 return 0;
4560 }
4561
4562 static int cayman_trig(struct r600_shader_ctx *ctx)
4563 {
4564 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4565 struct r600_bytecode_alu alu;
4566 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4567 int i, r;
4568
4569 r = tgsi_setup_trig(ctx);
4570 if (r)
4571 return r;
4572
4573
4574 for (i = 0; i < last_slot; i++) {
4575 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4576 alu.op = ctx->inst_info->op;
4577 alu.dst.chan = i;
4578
4579 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4580 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4581
4582 alu.src[0].sel = ctx->temp_reg;
4583 alu.src[0].chan = 0;
4584 if (i == last_slot - 1)
4585 alu.last = 1;
4586 r = r600_bytecode_add_alu(ctx->bc, &alu);
4587 if (r)
4588 return r;
4589 }
4590 return 0;
4591 }
4592
4593 static int tgsi_trig(struct r600_shader_ctx *ctx)
4594 {
4595 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4596 struct r600_bytecode_alu alu;
4597 int i, r;
4598 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4599
4600 r = tgsi_setup_trig(ctx);
4601 if (r)
4602 return r;
4603
4604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4605 alu.op = ctx->inst_info->op;
4606 alu.dst.chan = 0;
4607 alu.dst.sel = ctx->temp_reg;
4608 alu.dst.write = 1;
4609
4610 alu.src[0].sel = ctx->temp_reg;
4611 alu.src[0].chan = 0;
4612 alu.last = 1;
4613 r = r600_bytecode_add_alu(ctx->bc, &alu);
4614 if (r)
4615 return r;
4616
4617 /* replicate result */
4618 for (i = 0; i < lasti + 1; i++) {
4619 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4620 continue;
4621
4622 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4623 alu.op = ALU_OP1_MOV;
4624
4625 alu.src[0].sel = ctx->temp_reg;
4626 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4627 if (i == lasti)
4628 alu.last = 1;
4629 r = r600_bytecode_add_alu(ctx->bc, &alu);
4630 if (r)
4631 return r;
4632 }
4633 return 0;
4634 }
4635
4636 static int tgsi_kill(struct r600_shader_ctx *ctx)
4637 {
4638 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4639 struct r600_bytecode_alu alu;
4640 int i, r;
4641
4642 for (i = 0; i < 4; i++) {
4643 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4644 alu.op = ctx->inst_info->op;
4645
4646 alu.dst.chan = i;
4647
4648 alu.src[0].sel = V_SQ_ALU_SRC_0;
4649
4650 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4651 alu.src[1].sel = V_SQ_ALU_SRC_1;
4652 alu.src[1].neg = 1;
4653 } else {
4654 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4655 }
4656 if (i == 3) {
4657 alu.last = 1;
4658 }
4659 r = r600_bytecode_add_alu(ctx->bc, &alu);
4660 if (r)
4661 return r;
4662 }
4663
4664 /* kill must be last in ALU */
4665 ctx->bc->force_add_cf = 1;
4666 ctx->shader->uses_kill = TRUE;
4667 return 0;
4668 }
4669
4670 static int tgsi_lit(struct r600_shader_ctx *ctx)
4671 {
4672 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4673 struct r600_bytecode_alu alu;
4674 int r;
4675
4676 /* tmp.x = max(src.y, 0.0) */
4677 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4678 alu.op = ALU_OP2_MAX;
4679 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4680 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4681 alu.src[1].chan = 1;
4682
4683 alu.dst.sel = ctx->temp_reg;
4684 alu.dst.chan = 0;
4685 alu.dst.write = 1;
4686
4687 alu.last = 1;
4688 r = r600_bytecode_add_alu(ctx->bc, &alu);
4689 if (r)
4690 return r;
4691
4692 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4693 {
4694 int chan;
4695 int sel;
4696 unsigned i;
4697
4698 if (ctx->bc->chip_class == CAYMAN) {
4699 for (i = 0; i < 3; i++) {
4700 /* tmp.z = log(tmp.x) */
4701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4702 alu.op = ALU_OP1_LOG_CLAMPED;
4703 alu.src[0].sel = ctx->temp_reg;
4704 alu.src[0].chan = 0;
4705 alu.dst.sel = ctx->temp_reg;
4706 alu.dst.chan = i;
4707 if (i == 2) {
4708 alu.dst.write = 1;
4709 alu.last = 1;
4710 } else
4711 alu.dst.write = 0;
4712
4713 r = r600_bytecode_add_alu(ctx->bc, &alu);
4714 if (r)
4715 return r;
4716 }
4717 } else {
4718 /* tmp.z = log(tmp.x) */
4719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4720 alu.op = ALU_OP1_LOG_CLAMPED;
4721 alu.src[0].sel = ctx->temp_reg;
4722 alu.src[0].chan = 0;
4723 alu.dst.sel = ctx->temp_reg;
4724 alu.dst.chan = 2;
4725 alu.dst.write = 1;
4726 alu.last = 1;
4727 r = r600_bytecode_add_alu(ctx->bc, &alu);
4728 if (r)
4729 return r;
4730 }
4731
4732 chan = alu.dst.chan;
4733 sel = alu.dst.sel;
4734
4735 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4736 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4737 alu.op = ALU_OP3_MUL_LIT;
4738 alu.src[0].sel = sel;
4739 alu.src[0].chan = chan;
4740 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4741 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4742 alu.dst.sel = ctx->temp_reg;
4743 alu.dst.chan = 0;
4744 alu.dst.write = 1;
4745 alu.is_op3 = 1;
4746 alu.last = 1;
4747 r = r600_bytecode_add_alu(ctx->bc, &alu);
4748 if (r)
4749 return r;
4750
4751 if (ctx->bc->chip_class == CAYMAN) {
4752 for (i = 0; i < 3; i++) {
4753 /* dst.z = exp(tmp.x) */
4754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4755 alu.op = ALU_OP1_EXP_IEEE;
4756 alu.src[0].sel = ctx->temp_reg;
4757 alu.src[0].chan = 0;
4758 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4759 if (i == 2) {
4760 alu.dst.write = 1;
4761 alu.last = 1;
4762 } else
4763 alu.dst.write = 0;
4764 r = r600_bytecode_add_alu(ctx->bc, &alu);
4765 if (r)
4766 return r;
4767 }
4768 } else {
4769 /* dst.z = exp(tmp.x) */
4770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4771 alu.op = ALU_OP1_EXP_IEEE;
4772 alu.src[0].sel = ctx->temp_reg;
4773 alu.src[0].chan = 0;
4774 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4775 alu.last = 1;
4776 r = r600_bytecode_add_alu(ctx->bc, &alu);
4777 if (r)
4778 return r;
4779 }
4780 }
4781
4782 /* dst.x, <- 1.0 */
4783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4784 alu.op = ALU_OP1_MOV;
4785 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4786 alu.src[0].chan = 0;
4787 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4788 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4789 r = r600_bytecode_add_alu(ctx->bc, &alu);
4790 if (r)
4791 return r;
4792
4793 /* dst.y = max(src.x, 0.0) */
4794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4795 alu.op = ALU_OP2_MAX;
4796 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4797 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4798 alu.src[1].chan = 0;
4799 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4800 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4801 r = r600_bytecode_add_alu(ctx->bc, &alu);
4802 if (r)
4803 return r;
4804
4805 /* dst.w, <- 1.0 */
4806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4807 alu.op = ALU_OP1_MOV;
4808 alu.src[0].sel = V_SQ_ALU_SRC_1;
4809 alu.src[0].chan = 0;
4810 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4811 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4812 alu.last = 1;
4813 r = r600_bytecode_add_alu(ctx->bc, &alu);
4814 if (r)
4815 return r;
4816
4817 return 0;
4818 }
4819
4820 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4821 {
4822 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4823 struct r600_bytecode_alu alu;
4824 int i, r;
4825
4826 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4827
4828 /* XXX:
4829 * For state trackers other than OpenGL, we'll want to use
4830 * _RECIPSQRT_IEEE instead.
4831 */
4832 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
4833
4834 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4835 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4836 r600_bytecode_src_set_abs(&alu.src[i]);
4837 }
4838 alu.dst.sel = ctx->temp_reg;
4839 alu.dst.write = 1;
4840 alu.last = 1;
4841 r = r600_bytecode_add_alu(ctx->bc, &alu);
4842 if (r)
4843 return r;
4844 /* replicate result */
4845 return tgsi_helper_tempx_replicate(ctx);
4846 }
4847
4848 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4849 {
4850 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4851 struct r600_bytecode_alu alu;
4852 int i, r;
4853
4854 for (i = 0; i < 4; i++) {
4855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4856 alu.src[0].sel = ctx->temp_reg;
4857 alu.op = ALU_OP1_MOV;
4858 alu.dst.chan = i;
4859 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4860 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4861 if (i == 3)
4862 alu.last = 1;
4863 r = r600_bytecode_add_alu(ctx->bc, &alu);
4864 if (r)
4865 return r;
4866 }
4867 return 0;
4868 }
4869
4870 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4871 {
4872 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4873 struct r600_bytecode_alu alu;
4874 int i, r;
4875
4876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4877 alu.op = ctx->inst_info->op;
4878 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4879 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4880 }
4881 alu.dst.sel = ctx->temp_reg;
4882 alu.dst.write = 1;
4883 alu.last = 1;
4884 r = r600_bytecode_add_alu(ctx->bc, &alu);
4885 if (r)
4886 return r;
4887 /* replicate result */
4888 return tgsi_helper_tempx_replicate(ctx);
4889 }
4890
4891 static int cayman_pow(struct r600_shader_ctx *ctx)
4892 {
4893 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4894 int i, r;
4895 struct r600_bytecode_alu alu;
4896 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4897
4898 for (i = 0; i < 3; i++) {
4899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4900 alu.op = ALU_OP1_LOG_IEEE;
4901 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4902 alu.dst.sel = ctx->temp_reg;
4903 alu.dst.chan = i;
4904 alu.dst.write = 1;
4905 if (i == 2)
4906 alu.last = 1;
4907 r = r600_bytecode_add_alu(ctx->bc, &alu);
4908 if (r)
4909 return r;
4910 }
4911
4912 /* b * LOG2(a) */
4913 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4914 alu.op = ALU_OP2_MUL;
4915 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4916 alu.src[1].sel = ctx->temp_reg;
4917 alu.dst.sel = ctx->temp_reg;
4918 alu.dst.write = 1;
4919 alu.last = 1;
4920 r = r600_bytecode_add_alu(ctx->bc, &alu);
4921 if (r)
4922 return r;
4923
4924 for (i = 0; i < last_slot; i++) {
4925 /* POW(a,b) = EXP2(b * LOG2(a))*/
4926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4927 alu.op = ALU_OP1_EXP_IEEE;
4928 alu.src[0].sel = ctx->temp_reg;
4929
4930 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4931 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4932 if (i == last_slot - 1)
4933 alu.last = 1;
4934 r = r600_bytecode_add_alu(ctx->bc, &alu);
4935 if (r)
4936 return r;
4937 }
4938 return 0;
4939 }
4940
4941 static int tgsi_pow(struct r600_shader_ctx *ctx)
4942 {
4943 struct r600_bytecode_alu alu;
4944 int r;
4945
4946 /* LOG2(a) */
4947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4948 alu.op = ALU_OP1_LOG_IEEE;
4949 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4950 alu.dst.sel = ctx->temp_reg;
4951 alu.dst.write = 1;
4952 alu.last = 1;
4953 r = r600_bytecode_add_alu(ctx->bc, &alu);
4954 if (r)
4955 return r;
4956 /* b * LOG2(a) */
4957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4958 alu.op = ALU_OP2_MUL;
4959 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4960 alu.src[1].sel = ctx->temp_reg;
4961 alu.dst.sel = ctx->temp_reg;
4962 alu.dst.write = 1;
4963 alu.last = 1;
4964 r = r600_bytecode_add_alu(ctx->bc, &alu);
4965 if (r)
4966 return r;
4967 /* POW(a,b) = EXP2(b * LOG2(a))*/
4968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4969 alu.op = ALU_OP1_EXP_IEEE;
4970 alu.src[0].sel = ctx->temp_reg;
4971 alu.dst.sel = ctx->temp_reg;
4972 alu.dst.write = 1;
4973 alu.last = 1;
4974 r = r600_bytecode_add_alu(ctx->bc, &alu);
4975 if (r)
4976 return r;
4977 return tgsi_helper_tempx_replicate(ctx);
4978 }
4979
4980 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
4981 {
4982 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4983 struct r600_bytecode_alu alu;
4984 int i, r, j;
4985 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4986 int tmp0 = ctx->temp_reg;
4987 int tmp1 = r600_get_temp(ctx);
4988 int tmp2 = r600_get_temp(ctx);
4989 int tmp3 = r600_get_temp(ctx);
4990 /* Unsigned path:
4991 *
4992 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
4993 *
4994 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
4995 * 2. tmp0.z = lo (tmp0.x * src2)
4996 * 3. tmp0.w = -tmp0.z
4997 * 4. tmp0.y = hi (tmp0.x * src2)
4998 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
4999 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5000 * 7. tmp1.x = tmp0.x - tmp0.w
5001 * 8. tmp1.y = tmp0.x + tmp0.w
5002 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5003 * 10. tmp0.z = hi(tmp0.x * src1) = q
5004 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5005 *
5006 * 12. tmp0.w = src1 - tmp0.y = r
5007 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5008 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5009 *
5010 * if DIV
5011 *
5012 * 15. tmp1.z = tmp0.z + 1 = q + 1
5013 * 16. tmp1.w = tmp0.z - 1 = q - 1
5014 *
5015 * else MOD
5016 *
5017 * 15. tmp1.z = tmp0.w - src2 = r - src2
5018 * 16. tmp1.w = tmp0.w + src2 = r + src2
5019 *
5020 * endif
5021 *
5022 * 17. tmp1.x = tmp1.x & tmp1.y
5023 *
5024 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5025 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5026 *
5027 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5028 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5029 *
5030 * Signed path:
5031 *
5032 * Same as unsigned, using abs values of the operands,
5033 * and fixing the sign of the result in the end.
5034 */
5035
5036 for (i = 0; i < 4; i++) {
5037 if (!(write_mask & (1<<i)))
5038 continue;
5039
5040 if (signed_op) {
5041
5042 /* tmp2.x = -src0 */
5043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5044 alu.op = ALU_OP2_SUB_INT;
5045
5046 alu.dst.sel = tmp2;
5047 alu.dst.chan = 0;
5048 alu.dst.write = 1;
5049
5050 alu.src[0].sel = V_SQ_ALU_SRC_0;
5051
5052 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5053
5054 alu.last = 1;
5055 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5056 return r;
5057
5058 /* tmp2.y = -src1 */
5059 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5060 alu.op = ALU_OP2_SUB_INT;
5061
5062 alu.dst.sel = tmp2;
5063 alu.dst.chan = 1;
5064 alu.dst.write = 1;
5065
5066 alu.src[0].sel = V_SQ_ALU_SRC_0;
5067
5068 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5069
5070 alu.last = 1;
5071 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5072 return r;
5073
5074 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5075 /* it will be a sign of the quotient */
5076 if (!mod) {
5077
5078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5079 alu.op = ALU_OP2_XOR_INT;
5080
5081 alu.dst.sel = tmp2;
5082 alu.dst.chan = 2;
5083 alu.dst.write = 1;
5084
5085 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5086 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5087
5088 alu.last = 1;
5089 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5090 return r;
5091 }
5092
5093 /* tmp2.x = |src0| */
5094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5095 alu.op = ALU_OP3_CNDGE_INT;
5096 alu.is_op3 = 1;
5097
5098 alu.dst.sel = tmp2;
5099 alu.dst.chan = 0;
5100 alu.dst.write = 1;
5101
5102 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5103 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5104 alu.src[2].sel = tmp2;
5105 alu.src[2].chan = 0;
5106
5107 alu.last = 1;
5108 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5109 return r;
5110
5111 /* tmp2.y = |src1| */
5112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5113 alu.op = ALU_OP3_CNDGE_INT;
5114 alu.is_op3 = 1;
5115
5116 alu.dst.sel = tmp2;
5117 alu.dst.chan = 1;
5118 alu.dst.write = 1;
5119
5120 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5121 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5122 alu.src[2].sel = tmp2;
5123 alu.src[2].chan = 1;
5124
5125 alu.last = 1;
5126 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5127 return r;
5128
5129 }
5130
5131 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5132 if (ctx->bc->chip_class == CAYMAN) {
5133 /* tmp3.x = u2f(src2) */
5134 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5135 alu.op = ALU_OP1_UINT_TO_FLT;
5136
5137 alu.dst.sel = tmp3;
5138 alu.dst.chan = 0;
5139 alu.dst.write = 1;
5140
5141 if (signed_op) {
5142 alu.src[0].sel = tmp2;
5143 alu.src[0].chan = 1;
5144 } else {
5145 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5146 }
5147
5148 alu.last = 1;
5149 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5150 return r;
5151
5152 /* tmp0.x = recip(tmp3.x) */
5153 for (j = 0 ; j < 3; j++) {
5154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5155 alu.op = ALU_OP1_RECIP_IEEE;
5156
5157 alu.dst.sel = tmp0;
5158 alu.dst.chan = j;
5159 alu.dst.write = (j == 0);
5160
5161 alu.src[0].sel = tmp3;
5162 alu.src[0].chan = 0;
5163
5164 if (j == 2)
5165 alu.last = 1;
5166 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5167 return r;
5168 }
5169
5170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5171 alu.op = ALU_OP2_MUL;
5172
5173 alu.src[0].sel = tmp0;
5174 alu.src[0].chan = 0;
5175
5176 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5177 alu.src[1].value = 0x4f800000;
5178
5179 alu.dst.sel = tmp3;
5180 alu.dst.write = 1;
5181 alu.last = 1;
5182 r = r600_bytecode_add_alu(ctx->bc, &alu);
5183 if (r)
5184 return r;
5185
5186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5187 alu.op = ALU_OP1_FLT_TO_UINT;
5188
5189 alu.dst.sel = tmp0;
5190 alu.dst.chan = 0;
5191 alu.dst.write = 1;
5192
5193 alu.src[0].sel = tmp3;
5194 alu.src[0].chan = 0;
5195
5196 alu.last = 1;
5197 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5198 return r;
5199
5200 } else {
5201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5202 alu.op = ALU_OP1_RECIP_UINT;
5203
5204 alu.dst.sel = tmp0;
5205 alu.dst.chan = 0;
5206 alu.dst.write = 1;
5207
5208 if (signed_op) {
5209 alu.src[0].sel = tmp2;
5210 alu.src[0].chan = 1;
5211 } else {
5212 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5213 }
5214
5215 alu.last = 1;
5216 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5217 return r;
5218 }
5219
5220 /* 2. tmp0.z = lo (tmp0.x * src2) */
5221 if (ctx->bc->chip_class == CAYMAN) {
5222 for (j = 0 ; j < 4; j++) {
5223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5224 alu.op = ALU_OP2_MULLO_UINT;
5225
5226 alu.dst.sel = tmp0;
5227 alu.dst.chan = j;
5228 alu.dst.write = (j == 2);
5229
5230 alu.src[0].sel = tmp0;
5231 alu.src[0].chan = 0;
5232 if (signed_op) {
5233 alu.src[1].sel = tmp2;
5234 alu.src[1].chan = 1;
5235 } else {
5236 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5237 }
5238
5239 alu.last = (j == 3);
5240 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5241 return r;
5242 }
5243 } else {
5244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5245 alu.op = ALU_OP2_MULLO_UINT;
5246
5247 alu.dst.sel = tmp0;
5248 alu.dst.chan = 2;
5249 alu.dst.write = 1;
5250
5251 alu.src[0].sel = tmp0;
5252 alu.src[0].chan = 0;
5253 if (signed_op) {
5254 alu.src[1].sel = tmp2;
5255 alu.src[1].chan = 1;
5256 } else {
5257 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5258 }
5259
5260 alu.last = 1;
5261 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5262 return r;
5263 }
5264
5265 /* 3. tmp0.w = -tmp0.z */
5266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5267 alu.op = ALU_OP2_SUB_INT;
5268
5269 alu.dst.sel = tmp0;
5270 alu.dst.chan = 3;
5271 alu.dst.write = 1;
5272
5273 alu.src[0].sel = V_SQ_ALU_SRC_0;
5274 alu.src[1].sel = tmp0;
5275 alu.src[1].chan = 2;
5276
5277 alu.last = 1;
5278 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5279 return r;
5280
5281 /* 4. tmp0.y = hi (tmp0.x * src2) */
5282 if (ctx->bc->chip_class == CAYMAN) {
5283 for (j = 0 ; j < 4; j++) {
5284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5285 alu.op = ALU_OP2_MULHI_UINT;
5286
5287 alu.dst.sel = tmp0;
5288 alu.dst.chan = j;
5289 alu.dst.write = (j == 1);
5290
5291 alu.src[0].sel = tmp0;
5292 alu.src[0].chan = 0;
5293
5294 if (signed_op) {
5295 alu.src[1].sel = tmp2;
5296 alu.src[1].chan = 1;
5297 } else {
5298 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5299 }
5300 alu.last = (j == 3);
5301 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5302 return r;
5303 }
5304 } else {
5305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5306 alu.op = ALU_OP2_MULHI_UINT;
5307
5308 alu.dst.sel = tmp0;
5309 alu.dst.chan = 1;
5310 alu.dst.write = 1;
5311
5312 alu.src[0].sel = tmp0;
5313 alu.src[0].chan = 0;
5314
5315 if (signed_op) {
5316 alu.src[1].sel = tmp2;
5317 alu.src[1].chan = 1;
5318 } else {
5319 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5320 }
5321
5322 alu.last = 1;
5323 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5324 return r;
5325 }
5326
5327 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5329 alu.op = ALU_OP3_CNDE_INT;
5330 alu.is_op3 = 1;
5331
5332 alu.dst.sel = tmp0;
5333 alu.dst.chan = 2;
5334 alu.dst.write = 1;
5335
5336 alu.src[0].sel = tmp0;
5337 alu.src[0].chan = 1;
5338 alu.src[1].sel = tmp0;
5339 alu.src[1].chan = 3;
5340 alu.src[2].sel = tmp0;
5341 alu.src[2].chan = 2;
5342
5343 alu.last = 1;
5344 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5345 return r;
5346
5347 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5348 if (ctx->bc->chip_class == CAYMAN) {
5349 for (j = 0 ; j < 4; j++) {
5350 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5351 alu.op = ALU_OP2_MULHI_UINT;
5352
5353 alu.dst.sel = tmp0;
5354 alu.dst.chan = j;
5355 alu.dst.write = (j == 3);
5356
5357 alu.src[0].sel = tmp0;
5358 alu.src[0].chan = 2;
5359
5360 alu.src[1].sel = tmp0;
5361 alu.src[1].chan = 0;
5362
5363 alu.last = (j == 3);
5364 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5365 return r;
5366 }
5367 } else {
5368 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5369 alu.op = ALU_OP2_MULHI_UINT;
5370
5371 alu.dst.sel = tmp0;
5372 alu.dst.chan = 3;
5373 alu.dst.write = 1;
5374
5375 alu.src[0].sel = tmp0;
5376 alu.src[0].chan = 2;
5377
5378 alu.src[1].sel = tmp0;
5379 alu.src[1].chan = 0;
5380
5381 alu.last = 1;
5382 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5383 return r;
5384 }
5385
5386 /* 7. tmp1.x = tmp0.x - tmp0.w */
5387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5388 alu.op = ALU_OP2_SUB_INT;
5389
5390 alu.dst.sel = tmp1;
5391 alu.dst.chan = 0;
5392 alu.dst.write = 1;
5393
5394 alu.src[0].sel = tmp0;
5395 alu.src[0].chan = 0;
5396 alu.src[1].sel = tmp0;
5397 alu.src[1].chan = 3;
5398
5399 alu.last = 1;
5400 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5401 return r;
5402
5403 /* 8. tmp1.y = tmp0.x + tmp0.w */
5404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5405 alu.op = ALU_OP2_ADD_INT;
5406
5407 alu.dst.sel = tmp1;
5408 alu.dst.chan = 1;
5409 alu.dst.write = 1;
5410
5411 alu.src[0].sel = tmp0;
5412 alu.src[0].chan = 0;
5413 alu.src[1].sel = tmp0;
5414 alu.src[1].chan = 3;
5415
5416 alu.last = 1;
5417 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5418 return r;
5419
5420 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5421 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5422 alu.op = ALU_OP3_CNDE_INT;
5423 alu.is_op3 = 1;
5424
5425 alu.dst.sel = tmp0;
5426 alu.dst.chan = 0;
5427 alu.dst.write = 1;
5428
5429 alu.src[0].sel = tmp0;
5430 alu.src[0].chan = 1;
5431 alu.src[1].sel = tmp1;
5432 alu.src[1].chan = 1;
5433 alu.src[2].sel = tmp1;
5434 alu.src[2].chan = 0;
5435
5436 alu.last = 1;
5437 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5438 return r;
5439
5440 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5441 if (ctx->bc->chip_class == CAYMAN) {
5442 for (j = 0 ; j < 4; j++) {
5443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5444 alu.op = ALU_OP2_MULHI_UINT;
5445
5446 alu.dst.sel = tmp0;
5447 alu.dst.chan = j;
5448 alu.dst.write = (j == 2);
5449
5450 alu.src[0].sel = tmp0;
5451 alu.src[0].chan = 0;
5452
5453 if (signed_op) {
5454 alu.src[1].sel = tmp2;
5455 alu.src[1].chan = 0;
5456 } else {
5457 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5458 }
5459
5460 alu.last = (j == 3);
5461 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5462 return r;
5463 }
5464 } else {
5465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5466 alu.op = ALU_OP2_MULHI_UINT;
5467
5468 alu.dst.sel = tmp0;
5469 alu.dst.chan = 2;
5470 alu.dst.write = 1;
5471
5472 alu.src[0].sel = tmp0;
5473 alu.src[0].chan = 0;
5474
5475 if (signed_op) {
5476 alu.src[1].sel = tmp2;
5477 alu.src[1].chan = 0;
5478 } else {
5479 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5480 }
5481
5482 alu.last = 1;
5483 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5484 return r;
5485 }
5486
5487 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5488 if (ctx->bc->chip_class == CAYMAN) {
5489 for (j = 0 ; j < 4; j++) {
5490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5491 alu.op = ALU_OP2_MULLO_UINT;
5492
5493 alu.dst.sel = tmp0;
5494 alu.dst.chan = j;
5495 alu.dst.write = (j == 1);
5496
5497 if (signed_op) {
5498 alu.src[0].sel = tmp2;
5499 alu.src[0].chan = 1;
5500 } else {
5501 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5502 }
5503
5504 alu.src[1].sel = tmp0;
5505 alu.src[1].chan = 2;
5506
5507 alu.last = (j == 3);
5508 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5509 return r;
5510 }
5511 } else {
5512 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5513 alu.op = ALU_OP2_MULLO_UINT;
5514
5515 alu.dst.sel = tmp0;
5516 alu.dst.chan = 1;
5517 alu.dst.write = 1;
5518
5519 if (signed_op) {
5520 alu.src[0].sel = tmp2;
5521 alu.src[0].chan = 1;
5522 } else {
5523 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5524 }
5525
5526 alu.src[1].sel = tmp0;
5527 alu.src[1].chan = 2;
5528
5529 alu.last = 1;
5530 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5531 return r;
5532 }
5533
5534 /* 12. tmp0.w = src1 - tmp0.y = r */
5535 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5536 alu.op = ALU_OP2_SUB_INT;
5537
5538 alu.dst.sel = tmp0;
5539 alu.dst.chan = 3;
5540 alu.dst.write = 1;
5541
5542 if (signed_op) {
5543 alu.src[0].sel = tmp2;
5544 alu.src[0].chan = 0;
5545 } else {
5546 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5547 }
5548
5549 alu.src[1].sel = tmp0;
5550 alu.src[1].chan = 1;
5551
5552 alu.last = 1;
5553 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5554 return r;
5555
5556 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5558 alu.op = ALU_OP2_SETGE_UINT;
5559
5560 alu.dst.sel = tmp1;
5561 alu.dst.chan = 0;
5562 alu.dst.write = 1;
5563
5564 alu.src[0].sel = tmp0;
5565 alu.src[0].chan = 3;
5566 if (signed_op) {
5567 alu.src[1].sel = tmp2;
5568 alu.src[1].chan = 1;
5569 } else {
5570 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5571 }
5572
5573 alu.last = 1;
5574 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5575 return r;
5576
5577 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5578 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5579 alu.op = ALU_OP2_SETGE_UINT;
5580
5581 alu.dst.sel = tmp1;
5582 alu.dst.chan = 1;
5583 alu.dst.write = 1;
5584
5585 if (signed_op) {
5586 alu.src[0].sel = tmp2;
5587 alu.src[0].chan = 0;
5588 } else {
5589 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5590 }
5591
5592 alu.src[1].sel = tmp0;
5593 alu.src[1].chan = 1;
5594
5595 alu.last = 1;
5596 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5597 return r;
5598
5599 if (mod) { /* UMOD */
5600
5601 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5602 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5603 alu.op = ALU_OP2_SUB_INT;
5604
5605 alu.dst.sel = tmp1;
5606 alu.dst.chan = 2;
5607 alu.dst.write = 1;
5608
5609 alu.src[0].sel = tmp0;
5610 alu.src[0].chan = 3;
5611
5612 if (signed_op) {
5613 alu.src[1].sel = tmp2;
5614 alu.src[1].chan = 1;
5615 } else {
5616 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5617 }
5618
5619 alu.last = 1;
5620 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5621 return r;
5622
5623 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5624 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5625 alu.op = ALU_OP2_ADD_INT;
5626
5627 alu.dst.sel = tmp1;
5628 alu.dst.chan = 3;
5629 alu.dst.write = 1;
5630
5631 alu.src[0].sel = tmp0;
5632 alu.src[0].chan = 3;
5633 if (signed_op) {
5634 alu.src[1].sel = tmp2;
5635 alu.src[1].chan = 1;
5636 } else {
5637 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5638 }
5639
5640 alu.last = 1;
5641 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5642 return r;
5643
5644 } else { /* UDIV */
5645
5646 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5648 alu.op = ALU_OP2_ADD_INT;
5649
5650 alu.dst.sel = tmp1;
5651 alu.dst.chan = 2;
5652 alu.dst.write = 1;
5653
5654 alu.src[0].sel = tmp0;
5655 alu.src[0].chan = 2;
5656 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5657
5658 alu.last = 1;
5659 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5660 return r;
5661
5662 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5664 alu.op = ALU_OP2_ADD_INT;
5665
5666 alu.dst.sel = tmp1;
5667 alu.dst.chan = 3;
5668 alu.dst.write = 1;
5669
5670 alu.src[0].sel = tmp0;
5671 alu.src[0].chan = 2;
5672 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5673
5674 alu.last = 1;
5675 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5676 return r;
5677
5678 }
5679
5680 /* 17. tmp1.x = tmp1.x & tmp1.y */
5681 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5682 alu.op = ALU_OP2_AND_INT;
5683
5684 alu.dst.sel = tmp1;
5685 alu.dst.chan = 0;
5686 alu.dst.write = 1;
5687
5688 alu.src[0].sel = tmp1;
5689 alu.src[0].chan = 0;
5690 alu.src[1].sel = tmp1;
5691 alu.src[1].chan = 1;
5692
5693 alu.last = 1;
5694 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5695 return r;
5696
5697 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5698 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5699 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5700 alu.op = ALU_OP3_CNDE_INT;
5701 alu.is_op3 = 1;
5702
5703 alu.dst.sel = tmp0;
5704 alu.dst.chan = 2;
5705 alu.dst.write = 1;
5706
5707 alu.src[0].sel = tmp1;
5708 alu.src[0].chan = 0;
5709 alu.src[1].sel = tmp0;
5710 alu.src[1].chan = mod ? 3 : 2;
5711 alu.src[2].sel = tmp1;
5712 alu.src[2].chan = 2;
5713
5714 alu.last = 1;
5715 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5716 return r;
5717
5718 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5720 alu.op = ALU_OP3_CNDE_INT;
5721 alu.is_op3 = 1;
5722
5723 if (signed_op) {
5724 alu.dst.sel = tmp0;
5725 alu.dst.chan = 2;
5726 alu.dst.write = 1;
5727 } else {
5728 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5729 }
5730
5731 alu.src[0].sel = tmp1;
5732 alu.src[0].chan = 1;
5733 alu.src[1].sel = tmp1;
5734 alu.src[1].chan = 3;
5735 alu.src[2].sel = tmp0;
5736 alu.src[2].chan = 2;
5737
5738 alu.last = 1;
5739 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5740 return r;
5741
5742 if (signed_op) {
5743
5744 /* fix the sign of the result */
5745
5746 if (mod) {
5747
5748 /* tmp0.x = -tmp0.z */
5749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5750 alu.op = ALU_OP2_SUB_INT;
5751
5752 alu.dst.sel = tmp0;
5753 alu.dst.chan = 0;
5754 alu.dst.write = 1;
5755
5756 alu.src[0].sel = V_SQ_ALU_SRC_0;
5757 alu.src[1].sel = tmp0;
5758 alu.src[1].chan = 2;
5759
5760 alu.last = 1;
5761 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5762 return r;
5763
5764 /* sign of the remainder is the same as the sign of src0 */
5765 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5767 alu.op = ALU_OP3_CNDGE_INT;
5768 alu.is_op3 = 1;
5769
5770 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5771
5772 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5773 alu.src[1].sel = tmp0;
5774 alu.src[1].chan = 2;
5775 alu.src[2].sel = tmp0;
5776 alu.src[2].chan = 0;
5777
5778 alu.last = 1;
5779 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5780 return r;
5781
5782 } else {
5783
5784 /* tmp0.x = -tmp0.z */
5785 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5786 alu.op = ALU_OP2_SUB_INT;
5787
5788 alu.dst.sel = tmp0;
5789 alu.dst.chan = 0;
5790 alu.dst.write = 1;
5791
5792 alu.src[0].sel = V_SQ_ALU_SRC_0;
5793 alu.src[1].sel = tmp0;
5794 alu.src[1].chan = 2;
5795
5796 alu.last = 1;
5797 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5798 return r;
5799
5800 /* fix the quotient sign (same as the sign of src0*src1) */
5801 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5802 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5803 alu.op = ALU_OP3_CNDGE_INT;
5804 alu.is_op3 = 1;
5805
5806 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5807
5808 alu.src[0].sel = tmp2;
5809 alu.src[0].chan = 2;
5810 alu.src[1].sel = tmp0;
5811 alu.src[1].chan = 2;
5812 alu.src[2].sel = tmp0;
5813 alu.src[2].chan = 0;
5814
5815 alu.last = 1;
5816 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5817 return r;
5818 }
5819 }
5820 }
5821 return 0;
5822 }
5823
5824 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5825 {
5826 return tgsi_divmod(ctx, 0, 0);
5827 }
5828
5829 static int tgsi_umod(struct r600_shader_ctx *ctx)
5830 {
5831 return tgsi_divmod(ctx, 1, 0);
5832 }
5833
5834 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5835 {
5836 return tgsi_divmod(ctx, 0, 1);
5837 }
5838
5839 static int tgsi_imod(struct r600_shader_ctx *ctx)
5840 {
5841 return tgsi_divmod(ctx, 1, 1);
5842 }
5843
5844
5845 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5846 {
5847 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5848 struct r600_bytecode_alu alu;
5849 int i, r;
5850 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5851 int last_inst = tgsi_last_instruction(write_mask);
5852
5853 for (i = 0; i < 4; i++) {
5854 if (!(write_mask & (1<<i)))
5855 continue;
5856
5857 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5858 alu.op = ALU_OP1_TRUNC;
5859
5860 alu.dst.sel = ctx->temp_reg;
5861 alu.dst.chan = i;
5862 alu.dst.write = 1;
5863
5864 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5865 if (i == last_inst)
5866 alu.last = 1;
5867 r = r600_bytecode_add_alu(ctx->bc, &alu);
5868 if (r)
5869 return r;
5870 }
5871
5872 for (i = 0; i < 4; i++) {
5873 if (!(write_mask & (1<<i)))
5874 continue;
5875
5876 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5877 alu.op = ctx->inst_info->op;
5878
5879 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5880
5881 alu.src[0].sel = ctx->temp_reg;
5882 alu.src[0].chan = i;
5883
5884 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
5885 alu.last = 1;
5886 r = r600_bytecode_add_alu(ctx->bc, &alu);
5887 if (r)
5888 return r;
5889 }
5890
5891 return 0;
5892 }
5893
5894 static int tgsi_iabs(struct r600_shader_ctx *ctx)
5895 {
5896 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5897 struct r600_bytecode_alu alu;
5898 int i, r;
5899 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5900 int last_inst = tgsi_last_instruction(write_mask);
5901
5902 /* tmp = -src */
5903 for (i = 0; i < 4; i++) {
5904 if (!(write_mask & (1<<i)))
5905 continue;
5906
5907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5908 alu.op = ALU_OP2_SUB_INT;
5909
5910 alu.dst.sel = ctx->temp_reg;
5911 alu.dst.chan = i;
5912 alu.dst.write = 1;
5913
5914 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5915 alu.src[0].sel = V_SQ_ALU_SRC_0;
5916
5917 if (i == last_inst)
5918 alu.last = 1;
5919 r = r600_bytecode_add_alu(ctx->bc, &alu);
5920 if (r)
5921 return r;
5922 }
5923
5924 /* dst = (src >= 0 ? src : tmp) */
5925 for (i = 0; i < 4; i++) {
5926 if (!(write_mask & (1<<i)))
5927 continue;
5928
5929 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5930 alu.op = ALU_OP3_CNDGE_INT;
5931 alu.is_op3 = 1;
5932 alu.dst.write = 1;
5933
5934 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5935
5936 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5937 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5938 alu.src[2].sel = ctx->temp_reg;
5939 alu.src[2].chan = i;
5940
5941 if (i == last_inst)
5942 alu.last = 1;
5943 r = r600_bytecode_add_alu(ctx->bc, &alu);
5944 if (r)
5945 return r;
5946 }
5947 return 0;
5948 }
5949
5950 static int tgsi_issg(struct r600_shader_ctx *ctx)
5951 {
5952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5953 struct r600_bytecode_alu alu;
5954 int i, r;
5955 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5956 int last_inst = tgsi_last_instruction(write_mask);
5957
5958 /* tmp = (src >= 0 ? src : -1) */
5959 for (i = 0; i < 4; i++) {
5960 if (!(write_mask & (1<<i)))
5961 continue;
5962
5963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5964 alu.op = ALU_OP3_CNDGE_INT;
5965 alu.is_op3 = 1;
5966
5967 alu.dst.sel = ctx->temp_reg;
5968 alu.dst.chan = i;
5969 alu.dst.write = 1;
5970
5971 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5972 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5973 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
5974
5975 if (i == last_inst)
5976 alu.last = 1;
5977 r = r600_bytecode_add_alu(ctx->bc, &alu);
5978 if (r)
5979 return r;
5980 }
5981
5982 /* dst = (tmp > 0 ? 1 : tmp) */
5983 for (i = 0; i < 4; i++) {
5984 if (!(write_mask & (1<<i)))
5985 continue;
5986
5987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5988 alu.op = ALU_OP3_CNDGT_INT;
5989 alu.is_op3 = 1;
5990 alu.dst.write = 1;
5991
5992 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5993
5994 alu.src[0].sel = ctx->temp_reg;
5995 alu.src[0].chan = i;
5996
5997 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5998
5999 alu.src[2].sel = ctx->temp_reg;
6000 alu.src[2].chan = i;
6001
6002 if (i == last_inst)
6003 alu.last = 1;
6004 r = r600_bytecode_add_alu(ctx->bc, &alu);
6005 if (r)
6006 return r;
6007 }
6008 return 0;
6009 }
6010
6011
6012
6013 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6014 {
6015 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6016 struct r600_bytecode_alu alu;
6017 int i, r;
6018
6019 /* tmp = (src > 0 ? 1 : src) */
6020 for (i = 0; i < 4; i++) {
6021 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6022 alu.op = ALU_OP3_CNDGT;
6023 alu.is_op3 = 1;
6024
6025 alu.dst.sel = ctx->temp_reg;
6026 alu.dst.chan = i;
6027
6028 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6029 alu.src[1].sel = V_SQ_ALU_SRC_1;
6030 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6031
6032 if (i == 3)
6033 alu.last = 1;
6034 r = r600_bytecode_add_alu(ctx->bc, &alu);
6035 if (r)
6036 return r;
6037 }
6038
6039 /* dst = (-tmp > 0 ? -1 : tmp) */
6040 for (i = 0; i < 4; i++) {
6041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6042 alu.op = ALU_OP3_CNDGT;
6043 alu.is_op3 = 1;
6044 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6045
6046 alu.src[0].sel = ctx->temp_reg;
6047 alu.src[0].chan = i;
6048 alu.src[0].neg = 1;
6049
6050 alu.src[1].sel = V_SQ_ALU_SRC_1;
6051 alu.src[1].neg = 1;
6052
6053 alu.src[2].sel = ctx->temp_reg;
6054 alu.src[2].chan = i;
6055
6056 if (i == 3)
6057 alu.last = 1;
6058 r = r600_bytecode_add_alu(ctx->bc, &alu);
6059 if (r)
6060 return r;
6061 }
6062 return 0;
6063 }
6064
6065 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6066 {
6067 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6068 struct r600_bytecode_alu alu;
6069 int i, r, t1, t2;
6070
6071 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6072 int last_inst = tgsi_last_instruction(write_mask);
6073
6074 t1 = ctx->temp_reg;
6075
6076 for (i = 0; i < 4; i++) {
6077 if (!(write_mask & (1<<i)))
6078 continue;
6079
6080 /* create mask tmp */
6081 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6082 alu.op = ALU_OP2_BFM_INT;
6083 alu.dst.sel = t1;
6084 alu.dst.chan = i;
6085 alu.dst.write = 1;
6086 alu.last = i == last_inst;
6087
6088 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6089 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6090
6091 r = r600_bytecode_add_alu(ctx->bc, &alu);
6092 if (r)
6093 return r;
6094 }
6095
6096 t2 = r600_get_temp(ctx);
6097
6098 for (i = 0; i < 4; i++) {
6099 if (!(write_mask & (1<<i)))
6100 continue;
6101
6102 /* shift insert left */
6103 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6104 alu.op = ALU_OP2_LSHL_INT;
6105 alu.dst.sel = t2;
6106 alu.dst.chan = i;
6107 alu.dst.write = 1;
6108 alu.last = i == last_inst;
6109
6110 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6111 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6112
6113 r = r600_bytecode_add_alu(ctx->bc, &alu);
6114 if (r)
6115 return r;
6116 }
6117
6118 for (i = 0; i < 4; i++) {
6119 if (!(write_mask & (1<<i)))
6120 continue;
6121
6122 /* actual bitfield insert */
6123 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6124 alu.op = ALU_OP3_BFI_INT;
6125 alu.is_op3 = 1;
6126 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6127 alu.dst.chan = i;
6128 alu.dst.write = 1;
6129 alu.last = i == last_inst;
6130
6131 alu.src[0].sel = t1;
6132 alu.src[0].chan = i;
6133 alu.src[1].sel = t2;
6134 alu.src[1].chan = i;
6135 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6136
6137 r = r600_bytecode_add_alu(ctx->bc, &alu);
6138 if (r)
6139 return r;
6140 }
6141
6142 return 0;
6143 }
6144
6145 static int tgsi_msb(struct r600_shader_ctx *ctx)
6146 {
6147 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6148 struct r600_bytecode_alu alu;
6149 int i, r, t1, t2;
6150
6151 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6152 int last_inst = tgsi_last_instruction(write_mask);
6153
6154 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6155 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6156
6157 t1 = ctx->temp_reg;
6158
6159 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6160 for (i = 0; i < 4; i++) {
6161 if (!(write_mask & (1<<i)))
6162 continue;
6163
6164 /* t1 = FFBH_INT / FFBH_UINT */
6165 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6166 alu.op = ctx->inst_info->op;
6167 alu.dst.sel = t1;
6168 alu.dst.chan = i;
6169 alu.dst.write = 1;
6170 alu.last = i == last_inst;
6171
6172 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6173
6174 r = r600_bytecode_add_alu(ctx->bc, &alu);
6175 if (r)
6176 return r;
6177 }
6178
6179 t2 = r600_get_temp(ctx);
6180
6181 for (i = 0; i < 4; i++) {
6182 if (!(write_mask & (1<<i)))
6183 continue;
6184
6185 /* t2 = 31 - t1 */
6186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6187 alu.op = ALU_OP2_SUB_INT;
6188 alu.dst.sel = t2;
6189 alu.dst.chan = i;
6190 alu.dst.write = 1;
6191 alu.last = i == last_inst;
6192
6193 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6194 alu.src[0].value = 31;
6195 alu.src[1].sel = t1;
6196 alu.src[1].chan = i;
6197
6198 r = r600_bytecode_add_alu(ctx->bc, &alu);
6199 if (r)
6200 return r;
6201 }
6202
6203 for (i = 0; i < 4; i++) {
6204 if (!(write_mask & (1<<i)))
6205 continue;
6206
6207 /* result = t1 >= 0 ? t2 : t1 */
6208 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6209 alu.op = ALU_OP3_CNDGE_INT;
6210 alu.is_op3 = 1;
6211 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6212 alu.dst.chan = i;
6213 alu.dst.write = 1;
6214 alu.last = i == last_inst;
6215
6216 alu.src[0].sel = t1;
6217 alu.src[0].chan = i;
6218 alu.src[1].sel = t2;
6219 alu.src[1].chan = i;
6220 alu.src[2].sel = t1;
6221 alu.src[2].chan = i;
6222
6223 r = r600_bytecode_add_alu(ctx->bc, &alu);
6224 if (r)
6225 return r;
6226 }
6227
6228 return 0;
6229 }
6230
6231 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6232 {
6233 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6234 struct r600_bytecode_alu alu;
6235 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6236 unsigned location;
6237 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6238
6239 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6240
6241 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6242 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6243 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6244 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6245 }
6246 else {
6247 location = TGSI_INTERPOLATE_LOC_CENTROID;
6248 }
6249
6250 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6251 if (k < 0)
6252 k = 0;
6253 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6254 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6255
6256 /* NOTE: currently offset is not perspective correct */
6257 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6258 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6259 int sample_gpr = -1;
6260 int gradientsH, gradientsV;
6261 struct r600_bytecode_tex tex;
6262
6263 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6264 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6265 }
6266
6267 gradientsH = r600_get_temp(ctx);
6268 gradientsV = r600_get_temp(ctx);
6269 for (i = 0; i < 2; i++) {
6270 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6271 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6272 tex.src_gpr = interp_gpr;
6273 tex.src_sel_x = interp_base_chan + 0;
6274 tex.src_sel_y = interp_base_chan + 1;
6275 tex.src_sel_z = 0;
6276 tex.src_sel_w = 0;
6277 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6278 tex.dst_sel_x = 0;
6279 tex.dst_sel_y = 1;
6280 tex.dst_sel_z = 7;
6281 tex.dst_sel_w = 7;
6282 tex.inst_mod = 1; // Use per pixel gradient calculation
6283 tex.sampler_id = 0;
6284 tex.resource_id = tex.sampler_id;
6285 r = r600_bytecode_add_tex(ctx->bc, &tex);
6286 if (r)
6287 return r;
6288 }
6289
6290 for (i = 0; i < 2; i++) {
6291 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6292 alu.op = ALU_OP3_MULADD;
6293 alu.is_op3 = 1;
6294 alu.src[0].sel = gradientsH;
6295 alu.src[0].chan = i;
6296 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6297 alu.src[1].sel = sample_gpr;
6298 alu.src[1].chan = 2;
6299 }
6300 else {
6301 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6302 }
6303 alu.src[2].sel = interp_gpr;
6304 alu.src[2].chan = interp_base_chan + i;
6305 alu.dst.sel = ctx->temp_reg;
6306 alu.dst.chan = i;
6307 alu.last = i == 1;
6308
6309 r = r600_bytecode_add_alu(ctx->bc, &alu);
6310 if (r)
6311 return r;
6312 }
6313
6314 for (i = 0; i < 2; i++) {
6315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6316 alu.op = ALU_OP3_MULADD;
6317 alu.is_op3 = 1;
6318 alu.src[0].sel = gradientsV;
6319 alu.src[0].chan = i;
6320 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6321 alu.src[1].sel = sample_gpr;
6322 alu.src[1].chan = 3;
6323 }
6324 else {
6325 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6326 }
6327 alu.src[2].sel = ctx->temp_reg;
6328 alu.src[2].chan = i;
6329 alu.dst.sel = ctx->temp_reg;
6330 alu.dst.chan = i;
6331 alu.last = i == 1;
6332
6333 r = r600_bytecode_add_alu(ctx->bc, &alu);
6334 if (r)
6335 return r;
6336 }
6337 }
6338
6339 tmp = r600_get_temp(ctx);
6340 for (i = 0; i < 8; i++) {
6341 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6342 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6343
6344 alu.dst.sel = tmp;
6345 if ((i > 1 && i < 6)) {
6346 alu.dst.write = 1;
6347 }
6348 else {
6349 alu.dst.write = 0;
6350 }
6351 alu.dst.chan = i % 4;
6352
6353 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6354 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6355 alu.src[0].sel = ctx->temp_reg;
6356 alu.src[0].chan = 1 - (i % 2);
6357 } else {
6358 alu.src[0].sel = interp_gpr;
6359 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6360 }
6361 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6362 alu.src[1].chan = 0;
6363
6364 alu.last = i % 4 == 3;
6365 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6366
6367 r = r600_bytecode_add_alu(ctx->bc, &alu);
6368 if (r)
6369 return r;
6370 }
6371
6372 // INTERP can't swizzle dst
6373 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6374 for (i = 0; i <= lasti; i++) {
6375 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6376 continue;
6377
6378 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6379 alu.op = ALU_OP1_MOV;
6380 alu.src[0].sel = tmp;
6381 alu.src[0].chan = ctx->src[0].swizzle[i];
6382 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6383 alu.dst.write = 1;
6384 alu.last = i == lasti;
6385 r = r600_bytecode_add_alu(ctx->bc, &alu);
6386 if (r)
6387 return r;
6388 }
6389
6390 return 0;
6391 }
6392
6393
6394 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6395 {
6396 struct r600_bytecode_alu alu;
6397 int i, r;
6398
6399 for (i = 0; i < 4; i++) {
6400 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6401 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6402 alu.op = ALU_OP0_NOP;
6403 alu.dst.chan = i;
6404 } else {
6405 alu.op = ALU_OP1_MOV;
6406 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6407 alu.src[0].sel = ctx->temp_reg;
6408 alu.src[0].chan = i;
6409 }
6410 if (i == 3) {
6411 alu.last = 1;
6412 }
6413 r = r600_bytecode_add_alu(ctx->bc, &alu);
6414 if (r)
6415 return r;
6416 }
6417 return 0;
6418 }
6419
6420 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6421 unsigned temp, int chan,
6422 struct r600_bytecode_alu_src *bc_src,
6423 const struct r600_shader_src *shader_src)
6424 {
6425 struct r600_bytecode_alu alu;
6426 int r;
6427
6428 r600_bytecode_src(bc_src, shader_src, chan);
6429
6430 /* op3 operands don't support abs modifier */
6431 if (bc_src->abs) {
6432 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6434 alu.op = ALU_OP1_MOV;
6435 alu.dst.sel = temp;
6436 alu.dst.chan = chan;
6437 alu.dst.write = 1;
6438
6439 alu.src[0] = *bc_src;
6440 alu.last = true; // sufficient?
6441 r = r600_bytecode_add_alu(ctx->bc, &alu);
6442 if (r)
6443 return r;
6444
6445 memset(bc_src, 0, sizeof(*bc_src));
6446 bc_src->sel = temp;
6447 bc_src->chan = chan;
6448 }
6449 return 0;
6450 }
6451
6452 static int tgsi_op3(struct r600_shader_ctx *ctx)
6453 {
6454 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6455 struct r600_bytecode_alu alu;
6456 int i, j, r;
6457 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6458 int temp_regs[4];
6459 unsigned op = ctx->inst_info->op;
6460
6461 if (op == ALU_OP3_MULADD_IEEE &&
6462 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6463 op = ALU_OP3_MULADD;
6464
6465 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6466 temp_regs[j] = 0;
6467 if (ctx->src[j].abs)
6468 temp_regs[j] = r600_get_temp(ctx);
6469 }
6470 for (i = 0; i < lasti + 1; i++) {
6471 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6472 continue;
6473
6474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6475 alu.op = op;
6476 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6477 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6478 if (r)
6479 return r;
6480 }
6481
6482 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6483 alu.dst.chan = i;
6484 alu.dst.write = 1;
6485 alu.is_op3 = 1;
6486 if (i == lasti) {
6487 alu.last = 1;
6488 }
6489 r = r600_bytecode_add_alu(ctx->bc, &alu);
6490 if (r)
6491 return r;
6492 }
6493 return 0;
6494 }
6495
6496 static int tgsi_dp(struct r600_shader_ctx *ctx)
6497 {
6498 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6499 struct r600_bytecode_alu alu;
6500 int i, j, r;
6501 unsigned op = ctx->inst_info->op;
6502 if (op == ALU_OP2_DOT4_IEEE &&
6503 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6504 op = ALU_OP2_DOT4;
6505
6506 for (i = 0; i < 4; i++) {
6507 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6508 alu.op = op;
6509 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6510 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6511 }
6512
6513 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6514 alu.dst.chan = i;
6515 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6516 /* handle some special cases */
6517 switch (inst->Instruction.Opcode) {
6518 case TGSI_OPCODE_DP2:
6519 if (i > 1) {
6520 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6521 alu.src[0].chan = alu.src[1].chan = 0;
6522 }
6523 break;
6524 case TGSI_OPCODE_DP3:
6525 if (i > 2) {
6526 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6527 alu.src[0].chan = alu.src[1].chan = 0;
6528 }
6529 break;
6530 default:
6531 break;
6532 }
6533 if (i == 3) {
6534 alu.last = 1;
6535 }
6536 r = r600_bytecode_add_alu(ctx->bc, &alu);
6537 if (r)
6538 return r;
6539 }
6540 return 0;
6541 }
6542
6543 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6544 unsigned index)
6545 {
6546 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6547 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6548 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6549 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6550 ctx->src[index].neg || ctx->src[index].abs ||
6551 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6552 }
6553
6554 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6555 unsigned index)
6556 {
6557 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6558 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6559 }
6560
6561 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6562 {
6563 struct r600_bytecode_vtx vtx;
6564 struct r600_bytecode_alu alu;
6565 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6566 int src_gpr, r, i;
6567 int id = tgsi_tex_get_src_gpr(ctx, 1);
6568
6569 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6570 if (src_requires_loading) {
6571 for (i = 0; i < 4; i++) {
6572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6573 alu.op = ALU_OP1_MOV;
6574 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6575 alu.dst.sel = ctx->temp_reg;
6576 alu.dst.chan = i;
6577 if (i == 3)
6578 alu.last = 1;
6579 alu.dst.write = 1;
6580 r = r600_bytecode_add_alu(ctx->bc, &alu);
6581 if (r)
6582 return r;
6583 }
6584 src_gpr = ctx->temp_reg;
6585 }
6586
6587 memset(&vtx, 0, sizeof(vtx));
6588 vtx.op = FETCH_OP_VFETCH;
6589 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6590 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6591 vtx.src_gpr = src_gpr;
6592 vtx.mega_fetch_count = 16;
6593 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6594 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6595 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6596 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6597 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6598 vtx.use_const_fields = 1;
6599
6600 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6601 return r;
6602
6603 if (ctx->bc->chip_class >= EVERGREEN)
6604 return 0;
6605
6606 for (i = 0; i < 4; i++) {
6607 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6608 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6609 continue;
6610
6611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6612 alu.op = ALU_OP2_AND_INT;
6613
6614 alu.dst.chan = i;
6615 alu.dst.sel = vtx.dst_gpr;
6616 alu.dst.write = 1;
6617
6618 alu.src[0].sel = vtx.dst_gpr;
6619 alu.src[0].chan = i;
6620
6621 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6622 alu.src[1].sel += (id * 2);
6623 alu.src[1].chan = i % 4;
6624 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6625
6626 if (i == lasti)
6627 alu.last = 1;
6628 r = r600_bytecode_add_alu(ctx->bc, &alu);
6629 if (r)
6630 return r;
6631 }
6632
6633 if (inst->Dst[0].Register.WriteMask & 3) {
6634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6635 alu.op = ALU_OP2_OR_INT;
6636
6637 alu.dst.chan = 3;
6638 alu.dst.sel = vtx.dst_gpr;
6639 alu.dst.write = 1;
6640
6641 alu.src[0].sel = vtx.dst_gpr;
6642 alu.src[0].chan = 3;
6643
6644 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6645 alu.src[1].chan = 0;
6646 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6647
6648 alu.last = 1;
6649 r = r600_bytecode_add_alu(ctx->bc, &alu);
6650 if (r)
6651 return r;
6652 }
6653 return 0;
6654 }
6655
6656 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
6657 {
6658 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6659 struct r600_bytecode_alu alu;
6660 int r;
6661 int id = tgsi_tex_get_src_gpr(ctx, 1);
6662
6663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6664 alu.op = ALU_OP1_MOV;
6665 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6666 if (ctx->bc->chip_class >= EVERGREEN) {
6667 /* channel 0 or 2 of each word */
6668 alu.src[0].sel += (id / 2);
6669 alu.src[0].chan = (id % 2) * 2;
6670 } else {
6671 /* r600 we have them at channel 2 of the second dword */
6672 alu.src[0].sel += (id * 2) + 1;
6673 alu.src[0].chan = 1;
6674 }
6675 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6676 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6677 alu.last = 1;
6678 r = r600_bytecode_add_alu(ctx->bc, &alu);
6679 if (r)
6680 return r;
6681 return 0;
6682 }
6683
6684 static int tgsi_tex(struct r600_shader_ctx *ctx)
6685 {
6686 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6687 struct r600_bytecode_tex tex;
6688 struct r600_bytecode_alu alu;
6689 unsigned src_gpr;
6690 int r, i, j;
6691 int opcode;
6692 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6693 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6694 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6695 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6696
6697 bool txf_add_offsets = inst->Texture.NumOffsets &&
6698 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6699 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6700
6701 /* Texture fetch instructions can only use gprs as source.
6702 * Also they cannot negate the source or take the absolute value */
6703 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6704 tgsi_tex_src_requires_loading(ctx, 0)) ||
6705 read_compressed_msaa || txf_add_offsets;
6706
6707 boolean src_loaded = FALSE;
6708 unsigned sampler_src_reg = 1;
6709 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6710 boolean has_txq_cube_array_z = false;
6711 unsigned sampler_index_mode;
6712
6713 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6714 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6715 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6716 if (inst->Dst[0].Register.WriteMask & 4) {
6717 ctx->shader->has_txq_cube_array_z_comp = true;
6718 has_txq_cube_array_z = true;
6719 }
6720
6721 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6722 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6723 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6724 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6725 sampler_src_reg = 2;
6726
6727 /* TGSI moves the sampler to src reg 3 for TXD */
6728 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6729 sampler_src_reg = 3;
6730
6731 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6732
6733 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6734
6735 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6736 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6737 ctx->shader->uses_tex_buffers = true;
6738 return r600_do_buffer_txq(ctx);
6739 }
6740 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6741 if (ctx->bc->chip_class < EVERGREEN)
6742 ctx->shader->uses_tex_buffers = true;
6743 return do_vtx_fetch_inst(ctx, src_requires_loading);
6744 }
6745 }
6746
6747 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6748 int out_chan;
6749 /* Add perspective divide */
6750 if (ctx->bc->chip_class == CAYMAN) {
6751 out_chan = 2;
6752 for (i = 0; i < 3; i++) {
6753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6754 alu.op = ALU_OP1_RECIP_IEEE;
6755 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6756
6757 alu.dst.sel = ctx->temp_reg;
6758 alu.dst.chan = i;
6759 if (i == 2)
6760 alu.last = 1;
6761 if (out_chan == i)
6762 alu.dst.write = 1;
6763 r = r600_bytecode_add_alu(ctx->bc, &alu);
6764 if (r)
6765 return r;
6766 }
6767
6768 } else {
6769 out_chan = 3;
6770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6771 alu.op = ALU_OP1_RECIP_IEEE;
6772 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6773
6774 alu.dst.sel = ctx->temp_reg;
6775 alu.dst.chan = out_chan;
6776 alu.last = 1;
6777 alu.dst.write = 1;
6778 r = r600_bytecode_add_alu(ctx->bc, &alu);
6779 if (r)
6780 return r;
6781 }
6782
6783 for (i = 0; i < 3; i++) {
6784 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6785 alu.op = ALU_OP2_MUL;
6786 alu.src[0].sel = ctx->temp_reg;
6787 alu.src[0].chan = out_chan;
6788 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6789 alu.dst.sel = ctx->temp_reg;
6790 alu.dst.chan = i;
6791 alu.dst.write = 1;
6792 r = r600_bytecode_add_alu(ctx->bc, &alu);
6793 if (r)
6794 return r;
6795 }
6796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6797 alu.op = ALU_OP1_MOV;
6798 alu.src[0].sel = V_SQ_ALU_SRC_1;
6799 alu.src[0].chan = 0;
6800 alu.dst.sel = ctx->temp_reg;
6801 alu.dst.chan = 3;
6802 alu.last = 1;
6803 alu.dst.write = 1;
6804 r = r600_bytecode_add_alu(ctx->bc, &alu);
6805 if (r)
6806 return r;
6807 src_loaded = TRUE;
6808 src_gpr = ctx->temp_reg;
6809 }
6810
6811
6812 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6813 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6814 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6815 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6816 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
6817
6818 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6819 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6820
6821 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6822 for (i = 0; i < 4; i++) {
6823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6824 alu.op = ALU_OP2_CUBE;
6825 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6826 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6827 alu.dst.sel = ctx->temp_reg;
6828 alu.dst.chan = i;
6829 if (i == 3)
6830 alu.last = 1;
6831 alu.dst.write = 1;
6832 r = r600_bytecode_add_alu(ctx->bc, &alu);
6833 if (r)
6834 return r;
6835 }
6836
6837 /* tmp1.z = RCP_e(|tmp1.z|) */
6838 if (ctx->bc->chip_class == CAYMAN) {
6839 for (i = 0; i < 3; i++) {
6840 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6841 alu.op = ALU_OP1_RECIP_IEEE;
6842 alu.src[0].sel = ctx->temp_reg;
6843 alu.src[0].chan = 2;
6844 alu.src[0].abs = 1;
6845 alu.dst.sel = ctx->temp_reg;
6846 alu.dst.chan = i;
6847 if (i == 2)
6848 alu.dst.write = 1;
6849 if (i == 2)
6850 alu.last = 1;
6851 r = r600_bytecode_add_alu(ctx->bc, &alu);
6852 if (r)
6853 return r;
6854 }
6855 } else {
6856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6857 alu.op = ALU_OP1_RECIP_IEEE;
6858 alu.src[0].sel = ctx->temp_reg;
6859 alu.src[0].chan = 2;
6860 alu.src[0].abs = 1;
6861 alu.dst.sel = ctx->temp_reg;
6862 alu.dst.chan = 2;
6863 alu.dst.write = 1;
6864 alu.last = 1;
6865 r = r600_bytecode_add_alu(ctx->bc, &alu);
6866 if (r)
6867 return r;
6868 }
6869
6870 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
6871 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
6872 * muladd has no writemask, have to use another temp
6873 */
6874 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6875 alu.op = ALU_OP3_MULADD;
6876 alu.is_op3 = 1;
6877
6878 alu.src[0].sel = ctx->temp_reg;
6879 alu.src[0].chan = 0;
6880 alu.src[1].sel = ctx->temp_reg;
6881 alu.src[1].chan = 2;
6882
6883 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6884 alu.src[2].chan = 0;
6885 alu.src[2].value = u_bitcast_f2u(1.5f);
6886
6887 alu.dst.sel = ctx->temp_reg;
6888 alu.dst.chan = 0;
6889 alu.dst.write = 1;
6890
6891 r = r600_bytecode_add_alu(ctx->bc, &alu);
6892 if (r)
6893 return r;
6894
6895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6896 alu.op = ALU_OP3_MULADD;
6897 alu.is_op3 = 1;
6898
6899 alu.src[0].sel = ctx->temp_reg;
6900 alu.src[0].chan = 1;
6901 alu.src[1].sel = ctx->temp_reg;
6902 alu.src[1].chan = 2;
6903
6904 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
6905 alu.src[2].chan = 0;
6906 alu.src[2].value = u_bitcast_f2u(1.5f);
6907
6908 alu.dst.sel = ctx->temp_reg;
6909 alu.dst.chan = 1;
6910 alu.dst.write = 1;
6911
6912 alu.last = 1;
6913 r = r600_bytecode_add_alu(ctx->bc, &alu);
6914 if (r)
6915 return r;
6916 /* write initial compare value into Z component
6917 - W src 0 for shadow cube
6918 - X src 1 for shadow cube array */
6919 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6920 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6922 alu.op = ALU_OP1_MOV;
6923 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
6924 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
6925 else
6926 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6927 alu.dst.sel = ctx->temp_reg;
6928 alu.dst.chan = 2;
6929 alu.dst.write = 1;
6930 alu.last = 1;
6931 r = r600_bytecode_add_alu(ctx->bc, &alu);
6932 if (r)
6933 return r;
6934 }
6935
6936 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6937 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6938 if (ctx->bc->chip_class >= EVERGREEN) {
6939 int mytmp = r600_get_temp(ctx);
6940 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6941 alu.op = ALU_OP1_MOV;
6942 alu.src[0].sel = ctx->temp_reg;
6943 alu.src[0].chan = 3;
6944 alu.dst.sel = mytmp;
6945 alu.dst.chan = 0;
6946 alu.dst.write = 1;
6947 alu.last = 1;
6948 r = r600_bytecode_add_alu(ctx->bc, &alu);
6949 if (r)
6950 return r;
6951
6952 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
6953 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6954 alu.op = ALU_OP3_MULADD;
6955 alu.is_op3 = 1;
6956 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6957 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6958 alu.src[1].chan = 0;
6959 alu.src[1].value = u_bitcast_f2u(8.0f);
6960 alu.src[2].sel = mytmp;
6961 alu.src[2].chan = 0;
6962 alu.dst.sel = ctx->temp_reg;
6963 alu.dst.chan = 3;
6964 alu.dst.write = 1;
6965 alu.last = 1;
6966 r = r600_bytecode_add_alu(ctx->bc, &alu);
6967 if (r)
6968 return r;
6969 } else if (ctx->bc->chip_class < EVERGREEN) {
6970 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6971 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
6972 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6973 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6974 tex.src_gpr = r600_get_temp(ctx);
6975 tex.src_sel_x = 0;
6976 tex.src_sel_y = 0;
6977 tex.src_sel_z = 0;
6978 tex.src_sel_w = 0;
6979 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6980 tex.coord_type_x = 1;
6981 tex.coord_type_y = 1;
6982 tex.coord_type_z = 1;
6983 tex.coord_type_w = 1;
6984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6985 alu.op = ALU_OP1_MOV;
6986 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6987 alu.dst.sel = tex.src_gpr;
6988 alu.dst.chan = 0;
6989 alu.last = 1;
6990 alu.dst.write = 1;
6991 r = r600_bytecode_add_alu(ctx->bc, &alu);
6992 if (r)
6993 return r;
6994
6995 r = r600_bytecode_add_tex(ctx->bc, &tex);
6996 if (r)
6997 return r;
6998 }
6999
7000 }
7001
7002 /* for cube forms of lod and bias we need to route things */
7003 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7004 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7005 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7006 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7008 alu.op = ALU_OP1_MOV;
7009 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7010 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7011 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7012 else
7013 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7014 alu.dst.sel = ctx->temp_reg;
7015 alu.dst.chan = 2;
7016 alu.last = 1;
7017 alu.dst.write = 1;
7018 r = r600_bytecode_add_alu(ctx->bc, &alu);
7019 if (r)
7020 return r;
7021 }
7022
7023 src_loaded = TRUE;
7024 src_gpr = ctx->temp_reg;
7025 }
7026
7027 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7028 int temp_h = 0, temp_v = 0;
7029 int start_val = 0;
7030
7031 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7032 if (src_loaded == TRUE)
7033 start_val = 1;
7034 else
7035 src_loaded = TRUE;
7036 for (i = start_val; i < 3; i++) {
7037 int treg = r600_get_temp(ctx);
7038
7039 if (i == 0)
7040 src_gpr = treg;
7041 else if (i == 1)
7042 temp_h = treg;
7043 else
7044 temp_v = treg;
7045
7046 for (j = 0; j < 4; j++) {
7047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7048 alu.op = ALU_OP1_MOV;
7049 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7050 alu.dst.sel = treg;
7051 alu.dst.chan = j;
7052 if (j == 3)
7053 alu.last = 1;
7054 alu.dst.write = 1;
7055 r = r600_bytecode_add_alu(ctx->bc, &alu);
7056 if (r)
7057 return r;
7058 }
7059 }
7060 for (i = 1; i < 3; i++) {
7061 /* set gradients h/v */
7062 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7063 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7064 FETCH_OP_SET_GRADIENTS_V;
7065 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7066 tex.sampler_index_mode = sampler_index_mode;
7067 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7068 tex.resource_index_mode = sampler_index_mode;
7069
7070 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7071 tex.src_sel_x = 0;
7072 tex.src_sel_y = 1;
7073 tex.src_sel_z = 2;
7074 tex.src_sel_w = 3;
7075
7076 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7077 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7078 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7079 tex.coord_type_x = 1;
7080 tex.coord_type_y = 1;
7081 tex.coord_type_z = 1;
7082 tex.coord_type_w = 1;
7083 }
7084 r = r600_bytecode_add_tex(ctx->bc, &tex);
7085 if (r)
7086 return r;
7087 }
7088 }
7089
7090 if (src_requires_loading && !src_loaded) {
7091 for (i = 0; i < 4; i++) {
7092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7093 alu.op = ALU_OP1_MOV;
7094 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7095 alu.dst.sel = ctx->temp_reg;
7096 alu.dst.chan = i;
7097 if (i == 3)
7098 alu.last = 1;
7099 alu.dst.write = 1;
7100 r = r600_bytecode_add_alu(ctx->bc, &alu);
7101 if (r)
7102 return r;
7103 }
7104 src_loaded = TRUE;
7105 src_gpr = ctx->temp_reg;
7106 }
7107
7108 /* get offset values */
7109 if (inst->Texture.NumOffsets) {
7110 assert(inst->Texture.NumOffsets == 1);
7111
7112 /* The texture offset feature doesn't work with the TXF instruction
7113 * and must be emulated by adding the offset to the texture coordinates. */
7114 if (txf_add_offsets) {
7115 const struct tgsi_texture_offset *off = inst->TexOffsets;
7116
7117 switch (inst->Texture.Texture) {
7118 case TGSI_TEXTURE_3D:
7119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7120 alu.op = ALU_OP2_ADD_INT;
7121 alu.src[0].sel = src_gpr;
7122 alu.src[0].chan = 2;
7123 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7124 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7125 alu.dst.sel = src_gpr;
7126 alu.dst.chan = 2;
7127 alu.dst.write = 1;
7128 alu.last = 1;
7129 r = r600_bytecode_add_alu(ctx->bc, &alu);
7130 if (r)
7131 return r;
7132 /* fall through */
7133
7134 case TGSI_TEXTURE_2D:
7135 case TGSI_TEXTURE_SHADOW2D:
7136 case TGSI_TEXTURE_RECT:
7137 case TGSI_TEXTURE_SHADOWRECT:
7138 case TGSI_TEXTURE_2D_ARRAY:
7139 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7141 alu.op = ALU_OP2_ADD_INT;
7142 alu.src[0].sel = src_gpr;
7143 alu.src[0].chan = 1;
7144 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7145 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7146 alu.dst.sel = src_gpr;
7147 alu.dst.chan = 1;
7148 alu.dst.write = 1;
7149 alu.last = 1;
7150 r = r600_bytecode_add_alu(ctx->bc, &alu);
7151 if (r)
7152 return r;
7153 /* fall through */
7154
7155 case TGSI_TEXTURE_1D:
7156 case TGSI_TEXTURE_SHADOW1D:
7157 case TGSI_TEXTURE_1D_ARRAY:
7158 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7160 alu.op = ALU_OP2_ADD_INT;
7161 alu.src[0].sel = src_gpr;
7162 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7163 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7164 alu.dst.sel = src_gpr;
7165 alu.dst.write = 1;
7166 alu.last = 1;
7167 r = r600_bytecode_add_alu(ctx->bc, &alu);
7168 if (r)
7169 return r;
7170 break;
7171 /* texture offsets do not apply to other texture targets */
7172 }
7173 } else {
7174 switch (inst->Texture.Texture) {
7175 case TGSI_TEXTURE_3D:
7176 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7177 /* fallthrough */
7178 case TGSI_TEXTURE_2D:
7179 case TGSI_TEXTURE_SHADOW2D:
7180 case TGSI_TEXTURE_RECT:
7181 case TGSI_TEXTURE_SHADOWRECT:
7182 case TGSI_TEXTURE_2D_ARRAY:
7183 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7184 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7185 /* fallthrough */
7186 case TGSI_TEXTURE_1D:
7187 case TGSI_TEXTURE_SHADOW1D:
7188 case TGSI_TEXTURE_1D_ARRAY:
7189 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7190 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7191 }
7192 }
7193 }
7194
7195 /* Obtain the sample index for reading a compressed MSAA color texture.
7196 * To read the FMASK, we use the ldfptr instruction, which tells us
7197 * where the samples are stored.
7198 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7199 * which is the identity mapping. Each nibble says which physical sample
7200 * should be fetched to get that sample.
7201 *
7202 * Assume src.z contains the sample index. It should be modified like this:
7203 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7204 * Then fetch the texel with src.
7205 */
7206 if (read_compressed_msaa) {
7207 unsigned sample_chan = 3;
7208 unsigned temp = r600_get_temp(ctx);
7209 assert(src_loaded);
7210
7211 /* temp.w = ldfptr() */
7212 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7213 tex.op = FETCH_OP_LD;
7214 tex.inst_mod = 1; /* to indicate this is ldfptr */
7215 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7216 tex.sampler_index_mode = sampler_index_mode;
7217 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7218 tex.resource_index_mode = sampler_index_mode;
7219 tex.src_gpr = src_gpr;
7220 tex.dst_gpr = temp;
7221 tex.dst_sel_x = 7; /* mask out these components */
7222 tex.dst_sel_y = 7;
7223 tex.dst_sel_z = 7;
7224 tex.dst_sel_w = 0; /* store X */
7225 tex.src_sel_x = 0;
7226 tex.src_sel_y = 1;
7227 tex.src_sel_z = 2;
7228 tex.src_sel_w = 3;
7229 tex.offset_x = offset_x;
7230 tex.offset_y = offset_y;
7231 tex.offset_z = offset_z;
7232 r = r600_bytecode_add_tex(ctx->bc, &tex);
7233 if (r)
7234 return r;
7235
7236 /* temp.x = sample_index*4 */
7237 if (ctx->bc->chip_class == CAYMAN) {
7238 for (i = 0 ; i < 4; i++) {
7239 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7240 alu.op = ALU_OP2_MULLO_INT;
7241 alu.src[0].sel = src_gpr;
7242 alu.src[0].chan = sample_chan;
7243 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7244 alu.src[1].value = 4;
7245 alu.dst.sel = temp;
7246 alu.dst.chan = i;
7247 alu.dst.write = i == 0;
7248 if (i == 3)
7249 alu.last = 1;
7250 r = r600_bytecode_add_alu(ctx->bc, &alu);
7251 if (r)
7252 return r;
7253 }
7254 } else {
7255 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7256 alu.op = ALU_OP2_MULLO_INT;
7257 alu.src[0].sel = src_gpr;
7258 alu.src[0].chan = sample_chan;
7259 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7260 alu.src[1].value = 4;
7261 alu.dst.sel = temp;
7262 alu.dst.chan = 0;
7263 alu.dst.write = 1;
7264 alu.last = 1;
7265 r = r600_bytecode_add_alu(ctx->bc, &alu);
7266 if (r)
7267 return r;
7268 }
7269
7270 /* sample_index = temp.w >> temp.x */
7271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7272 alu.op = ALU_OP2_LSHR_INT;
7273 alu.src[0].sel = temp;
7274 alu.src[0].chan = 3;
7275 alu.src[1].sel = temp;
7276 alu.src[1].chan = 0;
7277 alu.dst.sel = src_gpr;
7278 alu.dst.chan = sample_chan;
7279 alu.dst.write = 1;
7280 alu.last = 1;
7281 r = r600_bytecode_add_alu(ctx->bc, &alu);
7282 if (r)
7283 return r;
7284
7285 /* sample_index & 0xF */
7286 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7287 alu.op = ALU_OP2_AND_INT;
7288 alu.src[0].sel = src_gpr;
7289 alu.src[0].chan = sample_chan;
7290 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7291 alu.src[1].value = 0xF;
7292 alu.dst.sel = src_gpr;
7293 alu.dst.chan = sample_chan;
7294 alu.dst.write = 1;
7295 alu.last = 1;
7296 r = r600_bytecode_add_alu(ctx->bc, &alu);
7297 if (r)
7298 return r;
7299 #if 0
7300 /* visualize the FMASK */
7301 for (i = 0; i < 4; i++) {
7302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7303 alu.op = ALU_OP1_INT_TO_FLT;
7304 alu.src[0].sel = src_gpr;
7305 alu.src[0].chan = sample_chan;
7306 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7307 alu.dst.chan = i;
7308 alu.dst.write = 1;
7309 alu.last = 1;
7310 r = r600_bytecode_add_alu(ctx->bc, &alu);
7311 if (r)
7312 return r;
7313 }
7314 return 0;
7315 #endif
7316 }
7317
7318 /* does this shader want a num layers from TXQ for a cube array? */
7319 if (has_txq_cube_array_z) {
7320 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7321
7322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7323 alu.op = ALU_OP1_MOV;
7324
7325 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7326 if (ctx->bc->chip_class >= EVERGREEN) {
7327 /* channel 1 or 3 of each word */
7328 alu.src[0].sel += (id / 2);
7329 alu.src[0].chan = ((id % 2) * 2) + 1;
7330 } else {
7331 /* r600 we have them at channel 2 of the second dword */
7332 alu.src[0].sel += (id * 2) + 1;
7333 alu.src[0].chan = 2;
7334 }
7335 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7336 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7337 alu.last = 1;
7338 r = r600_bytecode_add_alu(ctx->bc, &alu);
7339 if (r)
7340 return r;
7341 /* disable writemask from texture instruction */
7342 inst->Dst[0].Register.WriteMask &= ~4;
7343 }
7344
7345 opcode = ctx->inst_info->op;
7346 if (opcode == FETCH_OP_GATHER4 &&
7347 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7348 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7349 opcode = FETCH_OP_GATHER4_O;
7350
7351 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7352 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7353 encoded in the instruction are ignored. */
7354 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7355 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7356 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7357 tex.sampler_index_mode = sampler_index_mode;
7358 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7359 tex.resource_index_mode = sampler_index_mode;
7360
7361 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7362 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7363 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7364 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7365 tex.src_sel_w = 4;
7366
7367 tex.dst_sel_x = 7;
7368 tex.dst_sel_y = 7;
7369 tex.dst_sel_z = 7;
7370 tex.dst_sel_w = 7;
7371
7372 r = r600_bytecode_add_tex(ctx->bc, &tex);
7373 if (r)
7374 return r;
7375 }
7376
7377 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7378 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7379 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7380 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7381 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7382 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7383 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7384 switch (opcode) {
7385 case FETCH_OP_SAMPLE:
7386 opcode = FETCH_OP_SAMPLE_C;
7387 break;
7388 case FETCH_OP_SAMPLE_L:
7389 opcode = FETCH_OP_SAMPLE_C_L;
7390 break;
7391 case FETCH_OP_SAMPLE_LB:
7392 opcode = FETCH_OP_SAMPLE_C_LB;
7393 break;
7394 case FETCH_OP_SAMPLE_G:
7395 opcode = FETCH_OP_SAMPLE_C_G;
7396 break;
7397 /* Texture gather variants */
7398 case FETCH_OP_GATHER4:
7399 opcode = FETCH_OP_GATHER4_C;
7400 break;
7401 case FETCH_OP_GATHER4_O:
7402 opcode = FETCH_OP_GATHER4_C_O;
7403 break;
7404 }
7405 }
7406
7407 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7408 tex.op = opcode;
7409
7410 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7411 tex.sampler_index_mode = sampler_index_mode;
7412 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7413 tex.resource_index_mode = sampler_index_mode;
7414 tex.src_gpr = src_gpr;
7415 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7416
7417 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7418 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7419 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7420 }
7421
7422 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7423 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7424 tex.inst_mod = texture_component_select;
7425
7426 if (ctx->bc->chip_class == CAYMAN) {
7427 /* GATHER4 result order is different from TGSI TG4 */
7428 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7429 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7430 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7431 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7432 } else {
7433 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7434 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7435 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7436 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7437 }
7438 }
7439 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7440 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7441 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7442 tex.dst_sel_z = 7;
7443 tex.dst_sel_w = 7;
7444 }
7445 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7446 tex.dst_sel_x = 3;
7447 tex.dst_sel_y = 7;
7448 tex.dst_sel_z = 7;
7449 tex.dst_sel_w = 7;
7450 }
7451 else {
7452 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7453 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7454 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7455 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7456 }
7457
7458
7459 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7460 tex.src_sel_x = 4;
7461 tex.src_sel_y = 4;
7462 tex.src_sel_z = 4;
7463 tex.src_sel_w = 4;
7464 } else if (src_loaded) {
7465 tex.src_sel_x = 0;
7466 tex.src_sel_y = 1;
7467 tex.src_sel_z = 2;
7468 tex.src_sel_w = 3;
7469 } else {
7470 tex.src_sel_x = ctx->src[0].swizzle[0];
7471 tex.src_sel_y = ctx->src[0].swizzle[1];
7472 tex.src_sel_z = ctx->src[0].swizzle[2];
7473 tex.src_sel_w = ctx->src[0].swizzle[3];
7474 tex.src_rel = ctx->src[0].rel;
7475 }
7476
7477 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7478 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7479 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7480 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7481 tex.src_sel_x = 1;
7482 tex.src_sel_y = 0;
7483 tex.src_sel_z = 3;
7484 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7485 }
7486
7487 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7488 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7489 tex.coord_type_x = 1;
7490 tex.coord_type_y = 1;
7491 }
7492 tex.coord_type_z = 1;
7493 tex.coord_type_w = 1;
7494
7495 tex.offset_x = offset_x;
7496 tex.offset_y = offset_y;
7497 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7498 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7499 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7500 tex.offset_z = 0;
7501 }
7502 else {
7503 tex.offset_z = offset_z;
7504 }
7505
7506 /* Put the depth for comparison in W.
7507 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7508 * Some instructions expect the depth in Z. */
7509 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7510 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7511 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7512 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7513 opcode != FETCH_OP_SAMPLE_C_L &&
7514 opcode != FETCH_OP_SAMPLE_C_LB) {
7515 tex.src_sel_w = tex.src_sel_z;
7516 }
7517
7518 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7519 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7520 if (opcode == FETCH_OP_SAMPLE_C_L ||
7521 opcode == FETCH_OP_SAMPLE_C_LB) {
7522 /* the array index is read from Y */
7523 tex.coord_type_y = 0;
7524 } else {
7525 /* the array index is read from Z */
7526 tex.coord_type_z = 0;
7527 tex.src_sel_z = tex.src_sel_y;
7528 }
7529 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7530 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7531 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7532 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7533 (ctx->bc->chip_class >= EVERGREEN)))
7534 /* the array index is read from Z */
7535 tex.coord_type_z = 0;
7536
7537 /* mask unused source components */
7538 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7539 switch (inst->Texture.Texture) {
7540 case TGSI_TEXTURE_2D:
7541 case TGSI_TEXTURE_RECT:
7542 tex.src_sel_z = 7;
7543 tex.src_sel_w = 7;
7544 break;
7545 case TGSI_TEXTURE_1D_ARRAY:
7546 tex.src_sel_y = 7;
7547 tex.src_sel_w = 7;
7548 break;
7549 case TGSI_TEXTURE_1D:
7550 tex.src_sel_y = 7;
7551 tex.src_sel_z = 7;
7552 tex.src_sel_w = 7;
7553 break;
7554 }
7555 }
7556
7557 r = r600_bytecode_add_tex(ctx->bc, &tex);
7558 if (r)
7559 return r;
7560
7561 /* add shadow ambient support - gallium doesn't do it yet */
7562 return 0;
7563 }
7564
7565 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7566 struct tgsi_full_src_register *src)
7567 {
7568 int i;
7569
7570 if (src->Register.Indirect) {
7571 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7572 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7573 return ctx->shader->atomics[i].hw_idx;
7574 }
7575 } else {
7576 uint32_t index = src->Register.Index;
7577 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7578 if (ctx->shader->atomics[i].buffer_id != src->Dimension.Index)
7579 continue;
7580 if (index > ctx->shader->atomics[i].end)
7581 continue;
7582 if (index < ctx->shader->atomics[i].start)
7583 continue;
7584 uint32_t offset = (index - ctx->shader->atomics[i].start);
7585 return ctx->shader->atomics[i].hw_idx + offset;
7586 }
7587 }
7588 assert(0);
7589 return -1;
7590 }
7591
7592
7593 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7594 {
7595 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7596 int r;
7597 struct r600_bytecode_gds gds;
7598 int uav_id = 0;
7599 int uav_index_mode = 0;
7600
7601 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7602
7603 if (inst->Src[0].Register.Indirect)
7604 uav_index_mode = 2;
7605
7606 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7607 gds.op = FETCH_OP_GDS_READ_RET;
7608 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7609 gds.uav_id = uav_id;
7610 gds.uav_index_mode = uav_index_mode;
7611 gds.src_gpr = ctx->temp_reg;
7612 gds.src_sel_x = 4;
7613 gds.src_sel_y = 4;
7614 gds.src_sel_z = 4;
7615 gds.dst_sel_x = 0;
7616 gds.dst_sel_y = 7;
7617 gds.dst_sel_z = 7;
7618 gds.dst_sel_w = 7;
7619 gds.src_gpr2 = ctx->temp_reg;
7620 gds.alloc_consume = 1;
7621 r = r600_bytecode_add_gds(ctx->bc, &gds);
7622 if (r)
7623 return r;
7624
7625 ctx->bc->cf_last->vpm = 1;
7626 return 0;
7627 }
7628
7629 static int tgsi_load(struct r600_shader_ctx *ctx)
7630 {
7631 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7632 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7633 return tgsi_load_gds(ctx);
7634 return 0;
7635 }
7636
7637 static int get_gds_op(int opcode)
7638 {
7639 switch (opcode) {
7640 case TGSI_OPCODE_ATOMUADD:
7641 return FETCH_OP_GDS_ADD_RET;
7642 case TGSI_OPCODE_ATOMAND:
7643 return FETCH_OP_GDS_AND_RET;
7644 case TGSI_OPCODE_ATOMOR:
7645 return FETCH_OP_GDS_OR_RET;
7646 case TGSI_OPCODE_ATOMXOR:
7647 return FETCH_OP_GDS_XOR_RET;
7648 case TGSI_OPCODE_ATOMUMIN:
7649 return FETCH_OP_GDS_MIN_UINT_RET;
7650 case TGSI_OPCODE_ATOMUMAX:
7651 return FETCH_OP_GDS_MAX_UINT_RET;
7652 case TGSI_OPCODE_ATOMXCHG:
7653 return FETCH_OP_GDS_XCHG_RET;
7654 case TGSI_OPCODE_ATOMCAS:
7655 return FETCH_OP_GDS_CMP_XCHG_RET;
7656 default:
7657 return -1;
7658 }
7659 }
7660
7661 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
7662 {
7663 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7664 struct r600_bytecode_gds gds;
7665 struct r600_bytecode_alu alu;
7666 int gds_op = get_gds_op(inst->Instruction.Opcode);
7667 int r;
7668 int uav_id = 0;
7669 int uav_index_mode = 0;
7670
7671 if (gds_op == -1) {
7672 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
7673 return -1;
7674 }
7675
7676 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7677
7678 if (inst->Src[0].Register.Indirect)
7679 uav_index_mode = 2;
7680
7681 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
7682 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
7683 int abs_value = abs(value);
7684 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
7685 gds_op = FETCH_OP_GDS_SUB_RET;
7686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7687 alu.op = ALU_OP1_MOV;
7688 alu.dst.sel = ctx->temp_reg;
7689 alu.dst.chan = 0;
7690 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7691 alu.src[0].value = abs_value;
7692 alu.last = 1;
7693 alu.dst.write = 1;
7694 r = r600_bytecode_add_alu(ctx->bc, &alu);
7695 if (r)
7696 return r;
7697 } else {
7698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7699 alu.op = ALU_OP1_MOV;
7700 alu.dst.sel = ctx->temp_reg;
7701 alu.dst.chan = 0;
7702 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
7703 alu.last = 1;
7704 alu.dst.write = 1;
7705 r = r600_bytecode_add_alu(ctx->bc, &alu);
7706 if (r)
7707 return r;
7708 }
7709
7710 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7711 gds.op = gds_op;
7712 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7713 gds.uav_id = uav_id;
7714 gds.uav_index_mode = uav_index_mode;
7715 gds.src_gpr = ctx->temp_reg;
7716 gds.src_gpr2 = ctx->temp_reg;
7717 gds.src_sel_x = 4;
7718 gds.src_sel_y = 0;
7719 gds.src_sel_z = 4;
7720 gds.dst_sel_x = 0;
7721 gds.dst_sel_y = 7;
7722 gds.dst_sel_z = 7;
7723 gds.dst_sel_w = 7;
7724 gds.alloc_consume = 1;
7725 r = r600_bytecode_add_gds(ctx->bc, &gds);
7726 if (r)
7727 return r;
7728 ctx->bc->cf_last->vpm = 1;
7729 return 0;
7730 }
7731
7732 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
7733 {
7734 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7735 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7736 return tgsi_atomic_op_gds(ctx);
7737 return 0;
7738 }
7739
7740 static int tgsi_lrp(struct r600_shader_ctx *ctx)
7741 {
7742 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7743 struct r600_bytecode_alu alu;
7744 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7745 unsigned i, temp_regs[2];
7746 int r;
7747
7748 /* optimize if it's just an equal balance */
7749 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
7750 for (i = 0; i < lasti + 1; i++) {
7751 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7752 continue;
7753
7754 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7755 alu.op = ALU_OP2_ADD;
7756 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7757 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7758 alu.omod = 3;
7759 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7760 alu.dst.chan = i;
7761 if (i == lasti) {
7762 alu.last = 1;
7763 }
7764 r = r600_bytecode_add_alu(ctx->bc, &alu);
7765 if (r)
7766 return r;
7767 }
7768 return 0;
7769 }
7770
7771 /* 1 - src0 */
7772 for (i = 0; i < lasti + 1; i++) {
7773 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7774 continue;
7775
7776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7777 alu.op = ALU_OP2_ADD;
7778 alu.src[0].sel = V_SQ_ALU_SRC_1;
7779 alu.src[0].chan = 0;
7780 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7781 r600_bytecode_src_toggle_neg(&alu.src[1]);
7782 alu.dst.sel = ctx->temp_reg;
7783 alu.dst.chan = i;
7784 if (i == lasti) {
7785 alu.last = 1;
7786 }
7787 alu.dst.write = 1;
7788 r = r600_bytecode_add_alu(ctx->bc, &alu);
7789 if (r)
7790 return r;
7791 }
7792
7793 /* (1 - src0) * src2 */
7794 for (i = 0; i < lasti + 1; i++) {
7795 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7796 continue;
7797
7798 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7799 alu.op = ALU_OP2_MUL;
7800 alu.src[0].sel = ctx->temp_reg;
7801 alu.src[0].chan = i;
7802 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7803 alu.dst.sel = ctx->temp_reg;
7804 alu.dst.chan = i;
7805 if (i == lasti) {
7806 alu.last = 1;
7807 }
7808 alu.dst.write = 1;
7809 r = r600_bytecode_add_alu(ctx->bc, &alu);
7810 if (r)
7811 return r;
7812 }
7813
7814 /* src0 * src1 + (1 - src0) * src2 */
7815 if (ctx->src[0].abs)
7816 temp_regs[0] = r600_get_temp(ctx);
7817 else
7818 temp_regs[0] = 0;
7819 if (ctx->src[1].abs)
7820 temp_regs[1] = r600_get_temp(ctx);
7821 else
7822 temp_regs[1] = 0;
7823
7824 for (i = 0; i < lasti + 1; i++) {
7825 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7826 continue;
7827
7828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7829 alu.op = ALU_OP3_MULADD;
7830 alu.is_op3 = 1;
7831 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7832 if (r)
7833 return r;
7834 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
7835 if (r)
7836 return r;
7837 alu.src[2].sel = ctx->temp_reg;
7838 alu.src[2].chan = i;
7839
7840 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7841 alu.dst.chan = i;
7842 if (i == lasti) {
7843 alu.last = 1;
7844 }
7845 r = r600_bytecode_add_alu(ctx->bc, &alu);
7846 if (r)
7847 return r;
7848 }
7849 return 0;
7850 }
7851
7852 static int tgsi_cmp(struct r600_shader_ctx *ctx)
7853 {
7854 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7855 struct r600_bytecode_alu alu;
7856 int i, r, j;
7857 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7858 int temp_regs[3];
7859 unsigned op;
7860
7861 if (ctx->src[0].abs && ctx->src[0].neg) {
7862 op = ALU_OP3_CNDE;
7863 ctx->src[0].abs = 0;
7864 ctx->src[0].neg = 0;
7865 } else {
7866 op = ALU_OP3_CNDGE;
7867 }
7868
7869 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7870 temp_regs[j] = 0;
7871 if (ctx->src[j].abs)
7872 temp_regs[j] = r600_get_temp(ctx);
7873 }
7874
7875 for (i = 0; i < lasti + 1; i++) {
7876 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7877 continue;
7878
7879 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7880 alu.op = op;
7881 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
7882 if (r)
7883 return r;
7884 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
7885 if (r)
7886 return r;
7887 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
7888 if (r)
7889 return r;
7890 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7891 alu.dst.chan = i;
7892 alu.dst.write = 1;
7893 alu.is_op3 = 1;
7894 if (i == lasti)
7895 alu.last = 1;
7896 r = r600_bytecode_add_alu(ctx->bc, &alu);
7897 if (r)
7898 return r;
7899 }
7900 return 0;
7901 }
7902
7903 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
7904 {
7905 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7906 struct r600_bytecode_alu alu;
7907 int i, r;
7908 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7909
7910 for (i = 0; i < lasti + 1; i++) {
7911 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7912 continue;
7913
7914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7915 alu.op = ALU_OP3_CNDE_INT;
7916 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7917 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7918 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
7919 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7920 alu.dst.chan = i;
7921 alu.dst.write = 1;
7922 alu.is_op3 = 1;
7923 if (i == lasti)
7924 alu.last = 1;
7925 r = r600_bytecode_add_alu(ctx->bc, &alu);
7926 if (r)
7927 return r;
7928 }
7929 return 0;
7930 }
7931
7932 static int tgsi_exp(struct r600_shader_ctx *ctx)
7933 {
7934 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7935 struct r600_bytecode_alu alu;
7936 int r;
7937 unsigned i;
7938
7939 /* result.x = 2^floor(src); */
7940 if (inst->Dst[0].Register.WriteMask & 1) {
7941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7942
7943 alu.op = ALU_OP1_FLOOR;
7944 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7945
7946 alu.dst.sel = ctx->temp_reg;
7947 alu.dst.chan = 0;
7948 alu.dst.write = 1;
7949 alu.last = 1;
7950 r = r600_bytecode_add_alu(ctx->bc, &alu);
7951 if (r)
7952 return r;
7953
7954 if (ctx->bc->chip_class == CAYMAN) {
7955 for (i = 0; i < 3; i++) {
7956 alu.op = ALU_OP1_EXP_IEEE;
7957 alu.src[0].sel = ctx->temp_reg;
7958 alu.src[0].chan = 0;
7959
7960 alu.dst.sel = ctx->temp_reg;
7961 alu.dst.chan = i;
7962 alu.dst.write = i == 0;
7963 alu.last = i == 2;
7964 r = r600_bytecode_add_alu(ctx->bc, &alu);
7965 if (r)
7966 return r;
7967 }
7968 } else {
7969 alu.op = ALU_OP1_EXP_IEEE;
7970 alu.src[0].sel = ctx->temp_reg;
7971 alu.src[0].chan = 0;
7972
7973 alu.dst.sel = ctx->temp_reg;
7974 alu.dst.chan = 0;
7975 alu.dst.write = 1;
7976 alu.last = 1;
7977 r = r600_bytecode_add_alu(ctx->bc, &alu);
7978 if (r)
7979 return r;
7980 }
7981 }
7982
7983 /* result.y = tmp - floor(tmp); */
7984 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7986
7987 alu.op = ALU_OP1_FRACT;
7988 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7989
7990 alu.dst.sel = ctx->temp_reg;
7991 #if 0
7992 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7993 if (r)
7994 return r;
7995 #endif
7996 alu.dst.write = 1;
7997 alu.dst.chan = 1;
7998
7999 alu.last = 1;
8000
8001 r = r600_bytecode_add_alu(ctx->bc, &alu);
8002 if (r)
8003 return r;
8004 }
8005
8006 /* result.z = RoughApprox2ToX(tmp);*/
8007 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8008 if (ctx->bc->chip_class == CAYMAN) {
8009 for (i = 0; i < 3; i++) {
8010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8011 alu.op = ALU_OP1_EXP_IEEE;
8012 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8013
8014 alu.dst.sel = ctx->temp_reg;
8015 alu.dst.chan = i;
8016 if (i == 2) {
8017 alu.dst.write = 1;
8018 alu.last = 1;
8019 }
8020
8021 r = r600_bytecode_add_alu(ctx->bc, &alu);
8022 if (r)
8023 return r;
8024 }
8025 } else {
8026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8027 alu.op = ALU_OP1_EXP_IEEE;
8028 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8029
8030 alu.dst.sel = ctx->temp_reg;
8031 alu.dst.write = 1;
8032 alu.dst.chan = 2;
8033
8034 alu.last = 1;
8035
8036 r = r600_bytecode_add_alu(ctx->bc, &alu);
8037 if (r)
8038 return r;
8039 }
8040 }
8041
8042 /* result.w = 1.0;*/
8043 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8045
8046 alu.op = ALU_OP1_MOV;
8047 alu.src[0].sel = V_SQ_ALU_SRC_1;
8048 alu.src[0].chan = 0;
8049
8050 alu.dst.sel = ctx->temp_reg;
8051 alu.dst.chan = 3;
8052 alu.dst.write = 1;
8053 alu.last = 1;
8054 r = r600_bytecode_add_alu(ctx->bc, &alu);
8055 if (r)
8056 return r;
8057 }
8058 return tgsi_helper_copy(ctx, inst);
8059 }
8060
8061 static int tgsi_log(struct r600_shader_ctx *ctx)
8062 {
8063 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8064 struct r600_bytecode_alu alu;
8065 int r;
8066 unsigned i;
8067
8068 /* result.x = floor(log2(|src|)); */
8069 if (inst->Dst[0].Register.WriteMask & 1) {
8070 if (ctx->bc->chip_class == CAYMAN) {
8071 for (i = 0; i < 3; i++) {
8072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8073
8074 alu.op = ALU_OP1_LOG_IEEE;
8075 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8076 r600_bytecode_src_set_abs(&alu.src[0]);
8077
8078 alu.dst.sel = ctx->temp_reg;
8079 alu.dst.chan = i;
8080 if (i == 0)
8081 alu.dst.write = 1;
8082 if (i == 2)
8083 alu.last = 1;
8084 r = r600_bytecode_add_alu(ctx->bc, &alu);
8085 if (r)
8086 return r;
8087 }
8088
8089 } else {
8090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8091
8092 alu.op = ALU_OP1_LOG_IEEE;
8093 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8094 r600_bytecode_src_set_abs(&alu.src[0]);
8095
8096 alu.dst.sel = ctx->temp_reg;
8097 alu.dst.chan = 0;
8098 alu.dst.write = 1;
8099 alu.last = 1;
8100 r = r600_bytecode_add_alu(ctx->bc, &alu);
8101 if (r)
8102 return r;
8103 }
8104
8105 alu.op = ALU_OP1_FLOOR;
8106 alu.src[0].sel = ctx->temp_reg;
8107 alu.src[0].chan = 0;
8108
8109 alu.dst.sel = ctx->temp_reg;
8110 alu.dst.chan = 0;
8111 alu.dst.write = 1;
8112 alu.last = 1;
8113
8114 r = r600_bytecode_add_alu(ctx->bc, &alu);
8115 if (r)
8116 return r;
8117 }
8118
8119 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8120 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8121
8122 if (ctx->bc->chip_class == CAYMAN) {
8123 for (i = 0; i < 3; i++) {
8124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8125
8126 alu.op = ALU_OP1_LOG_IEEE;
8127 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8128 r600_bytecode_src_set_abs(&alu.src[0]);
8129
8130 alu.dst.sel = ctx->temp_reg;
8131 alu.dst.chan = i;
8132 if (i == 1)
8133 alu.dst.write = 1;
8134 if (i == 2)
8135 alu.last = 1;
8136
8137 r = r600_bytecode_add_alu(ctx->bc, &alu);
8138 if (r)
8139 return r;
8140 }
8141 } else {
8142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8143
8144 alu.op = ALU_OP1_LOG_IEEE;
8145 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8146 r600_bytecode_src_set_abs(&alu.src[0]);
8147
8148 alu.dst.sel = ctx->temp_reg;
8149 alu.dst.chan = 1;
8150 alu.dst.write = 1;
8151 alu.last = 1;
8152
8153 r = r600_bytecode_add_alu(ctx->bc, &alu);
8154 if (r)
8155 return r;
8156 }
8157
8158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8159
8160 alu.op = ALU_OP1_FLOOR;
8161 alu.src[0].sel = ctx->temp_reg;
8162 alu.src[0].chan = 1;
8163
8164 alu.dst.sel = ctx->temp_reg;
8165 alu.dst.chan = 1;
8166 alu.dst.write = 1;
8167 alu.last = 1;
8168
8169 r = r600_bytecode_add_alu(ctx->bc, &alu);
8170 if (r)
8171 return r;
8172
8173 if (ctx->bc->chip_class == CAYMAN) {
8174 for (i = 0; i < 3; i++) {
8175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8176 alu.op = ALU_OP1_EXP_IEEE;
8177 alu.src[0].sel = ctx->temp_reg;
8178 alu.src[0].chan = 1;
8179
8180 alu.dst.sel = ctx->temp_reg;
8181 alu.dst.chan = i;
8182 if (i == 1)
8183 alu.dst.write = 1;
8184 if (i == 2)
8185 alu.last = 1;
8186
8187 r = r600_bytecode_add_alu(ctx->bc, &alu);
8188 if (r)
8189 return r;
8190 }
8191 } else {
8192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8193 alu.op = ALU_OP1_EXP_IEEE;
8194 alu.src[0].sel = ctx->temp_reg;
8195 alu.src[0].chan = 1;
8196
8197 alu.dst.sel = ctx->temp_reg;
8198 alu.dst.chan = 1;
8199 alu.dst.write = 1;
8200 alu.last = 1;
8201
8202 r = r600_bytecode_add_alu(ctx->bc, &alu);
8203 if (r)
8204 return r;
8205 }
8206
8207 if (ctx->bc->chip_class == CAYMAN) {
8208 for (i = 0; i < 3; i++) {
8209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8210 alu.op = ALU_OP1_RECIP_IEEE;
8211 alu.src[0].sel = ctx->temp_reg;
8212 alu.src[0].chan = 1;
8213
8214 alu.dst.sel = ctx->temp_reg;
8215 alu.dst.chan = i;
8216 if (i == 1)
8217 alu.dst.write = 1;
8218 if (i == 2)
8219 alu.last = 1;
8220
8221 r = r600_bytecode_add_alu(ctx->bc, &alu);
8222 if (r)
8223 return r;
8224 }
8225 } else {
8226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8227 alu.op = ALU_OP1_RECIP_IEEE;
8228 alu.src[0].sel = ctx->temp_reg;
8229 alu.src[0].chan = 1;
8230
8231 alu.dst.sel = ctx->temp_reg;
8232 alu.dst.chan = 1;
8233 alu.dst.write = 1;
8234 alu.last = 1;
8235
8236 r = r600_bytecode_add_alu(ctx->bc, &alu);
8237 if (r)
8238 return r;
8239 }
8240
8241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8242
8243 alu.op = ALU_OP2_MUL;
8244
8245 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8246 r600_bytecode_src_set_abs(&alu.src[0]);
8247
8248 alu.src[1].sel = ctx->temp_reg;
8249 alu.src[1].chan = 1;
8250
8251 alu.dst.sel = ctx->temp_reg;
8252 alu.dst.chan = 1;
8253 alu.dst.write = 1;
8254 alu.last = 1;
8255
8256 r = r600_bytecode_add_alu(ctx->bc, &alu);
8257 if (r)
8258 return r;
8259 }
8260
8261 /* result.z = log2(|src|);*/
8262 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8263 if (ctx->bc->chip_class == CAYMAN) {
8264 for (i = 0; i < 3; i++) {
8265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8266
8267 alu.op = ALU_OP1_LOG_IEEE;
8268 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8269 r600_bytecode_src_set_abs(&alu.src[0]);
8270
8271 alu.dst.sel = ctx->temp_reg;
8272 if (i == 2)
8273 alu.dst.write = 1;
8274 alu.dst.chan = i;
8275 if (i == 2)
8276 alu.last = 1;
8277
8278 r = r600_bytecode_add_alu(ctx->bc, &alu);
8279 if (r)
8280 return r;
8281 }
8282 } else {
8283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8284
8285 alu.op = ALU_OP1_LOG_IEEE;
8286 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8287 r600_bytecode_src_set_abs(&alu.src[0]);
8288
8289 alu.dst.sel = ctx->temp_reg;
8290 alu.dst.write = 1;
8291 alu.dst.chan = 2;
8292 alu.last = 1;
8293
8294 r = r600_bytecode_add_alu(ctx->bc, &alu);
8295 if (r)
8296 return r;
8297 }
8298 }
8299
8300 /* result.w = 1.0; */
8301 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8303
8304 alu.op = ALU_OP1_MOV;
8305 alu.src[0].sel = V_SQ_ALU_SRC_1;
8306 alu.src[0].chan = 0;
8307
8308 alu.dst.sel = ctx->temp_reg;
8309 alu.dst.chan = 3;
8310 alu.dst.write = 1;
8311 alu.last = 1;
8312
8313 r = r600_bytecode_add_alu(ctx->bc, &alu);
8314 if (r)
8315 return r;
8316 }
8317
8318 return tgsi_helper_copy(ctx, inst);
8319 }
8320
8321 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8322 {
8323 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8324 struct r600_bytecode_alu alu;
8325 int r;
8326 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8327 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8328
8329 assert(inst->Dst[0].Register.Index < 3);
8330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8331
8332 switch (inst->Instruction.Opcode) {
8333 case TGSI_OPCODE_ARL:
8334 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8335 break;
8336 case TGSI_OPCODE_ARR:
8337 alu.op = ALU_OP1_FLT_TO_INT;
8338 break;
8339 case TGSI_OPCODE_UARL:
8340 alu.op = ALU_OP1_MOV;
8341 break;
8342 default:
8343 assert(0);
8344 return -1;
8345 }
8346
8347 for (i = 0; i <= lasti; ++i) {
8348 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8349 continue;
8350 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8351 alu.last = i == lasti;
8352 alu.dst.sel = reg;
8353 alu.dst.chan = i;
8354 alu.dst.write = 1;
8355 r = r600_bytecode_add_alu(ctx->bc, &alu);
8356 if (r)
8357 return r;
8358 }
8359
8360 if (inst->Dst[0].Register.Index > 0)
8361 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8362 else
8363 ctx->bc->ar_loaded = 0;
8364
8365 return 0;
8366 }
8367 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8368 {
8369 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8370 struct r600_bytecode_alu alu;
8371 int r;
8372 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8373
8374 switch (inst->Instruction.Opcode) {
8375 case TGSI_OPCODE_ARL:
8376 memset(&alu, 0, sizeof(alu));
8377 alu.op = ALU_OP1_FLOOR;
8378 alu.dst.sel = ctx->bc->ar_reg;
8379 alu.dst.write = 1;
8380 for (i = 0; i <= lasti; ++i) {
8381 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8382 alu.dst.chan = i;
8383 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8384 alu.last = i == lasti;
8385 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8386 return r;
8387 }
8388 }
8389
8390 memset(&alu, 0, sizeof(alu));
8391 alu.op = ALU_OP1_FLT_TO_INT;
8392 alu.src[0].sel = ctx->bc->ar_reg;
8393 alu.dst.sel = ctx->bc->ar_reg;
8394 alu.dst.write = 1;
8395 /* FLT_TO_INT is trans-only on r600/r700 */
8396 alu.last = TRUE;
8397 for (i = 0; i <= lasti; ++i) {
8398 alu.dst.chan = i;
8399 alu.src[0].chan = i;
8400 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8401 return r;
8402 }
8403 break;
8404 case TGSI_OPCODE_ARR:
8405 memset(&alu, 0, sizeof(alu));
8406 alu.op = ALU_OP1_FLT_TO_INT;
8407 alu.dst.sel = ctx->bc->ar_reg;
8408 alu.dst.write = 1;
8409 /* FLT_TO_INT is trans-only on r600/r700 */
8410 alu.last = TRUE;
8411 for (i = 0; i <= lasti; ++i) {
8412 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8413 alu.dst.chan = i;
8414 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8415 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8416 return r;
8417 }
8418 }
8419 break;
8420 case TGSI_OPCODE_UARL:
8421 memset(&alu, 0, sizeof(alu));
8422 alu.op = ALU_OP1_MOV;
8423 alu.dst.sel = ctx->bc->ar_reg;
8424 alu.dst.write = 1;
8425 for (i = 0; i <= lasti; ++i) {
8426 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8427 alu.dst.chan = i;
8428 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8429 alu.last = i == lasti;
8430 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8431 return r;
8432 }
8433 }
8434 break;
8435 default:
8436 assert(0);
8437 return -1;
8438 }
8439
8440 ctx->bc->ar_loaded = 0;
8441 return 0;
8442 }
8443
8444 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8445 {
8446 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8447 struct r600_bytecode_alu alu;
8448 int i, r = 0;
8449
8450 for (i = 0; i < 4; i++) {
8451 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8452
8453 alu.op = ALU_OP2_MUL;
8454 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8455
8456 if (i == 0 || i == 3) {
8457 alu.src[0].sel = V_SQ_ALU_SRC_1;
8458 } else {
8459 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8460 }
8461
8462 if (i == 0 || i == 2) {
8463 alu.src[1].sel = V_SQ_ALU_SRC_1;
8464 } else {
8465 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8466 }
8467 if (i == 3)
8468 alu.last = 1;
8469 r = r600_bytecode_add_alu(ctx->bc, &alu);
8470 if (r)
8471 return r;
8472 }
8473 return 0;
8474 }
8475
8476 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
8477 {
8478 struct r600_bytecode_alu alu;
8479 int r;
8480
8481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8482 alu.op = opcode;
8483 alu.execute_mask = 1;
8484 alu.update_pred = 1;
8485
8486 alu.dst.sel = ctx->temp_reg;
8487 alu.dst.write = 1;
8488 alu.dst.chan = 0;
8489
8490 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8491 alu.src[1].sel = V_SQ_ALU_SRC_0;
8492 alu.src[1].chan = 0;
8493
8494 alu.last = 1;
8495
8496 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
8497 if (r)
8498 return r;
8499 return 0;
8500 }
8501
8502 static int pops(struct r600_shader_ctx *ctx, int pops)
8503 {
8504 unsigned force_pop = ctx->bc->force_add_cf;
8505
8506 if (!force_pop) {
8507 int alu_pop = 3;
8508 if (ctx->bc->cf_last) {
8509 if (ctx->bc->cf_last->op == CF_OP_ALU)
8510 alu_pop = 0;
8511 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
8512 alu_pop = 1;
8513 }
8514 alu_pop += pops;
8515 if (alu_pop == 1) {
8516 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
8517 ctx->bc->force_add_cf = 1;
8518 } else if (alu_pop == 2) {
8519 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
8520 ctx->bc->force_add_cf = 1;
8521 } else {
8522 force_pop = 1;
8523 }
8524 }
8525
8526 if (force_pop) {
8527 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
8528 ctx->bc->cf_last->pop_count = pops;
8529 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8530 }
8531
8532 return 0;
8533 }
8534
8535 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
8536 unsigned reason)
8537 {
8538 struct r600_stack_info *stack = &ctx->bc->stack;
8539 unsigned elements, entries;
8540
8541 unsigned entry_size = stack->entry_size;
8542
8543 elements = (stack->loop + stack->push_wqm ) * entry_size;
8544 elements += stack->push;
8545
8546 switch (ctx->bc->chip_class) {
8547 case R600:
8548 case R700:
8549 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
8550 * the stack must be reserved to hold the current active/continue
8551 * masks */
8552 if (reason == FC_PUSH_VPM) {
8553 elements += 2;
8554 }
8555 break;
8556
8557 case CAYMAN:
8558 /* r9xx: any stack operation on empty stack consumes 2 additional
8559 * elements */
8560 elements += 2;
8561
8562 /* fallthrough */
8563 /* FIXME: do the two elements added above cover the cases for the
8564 * r8xx+ below? */
8565
8566 case EVERGREEN:
8567 /* r8xx+: 2 extra elements are not always required, but one extra
8568 * element must be added for each of the following cases:
8569 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
8570 * stack usage.
8571 * (Currently we don't use ALU_ELSE_AFTER.)
8572 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
8573 * PUSH instruction executed.
8574 *
8575 * NOTE: it seems we also need to reserve additional element in some
8576 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8577 * then STACK_SIZE should be 2 instead of 1 */
8578 if (reason == FC_PUSH_VPM) {
8579 elements += 1;
8580 }
8581 break;
8582
8583 default:
8584 assert(0);
8585 break;
8586 }
8587
8588 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
8589 * for all chips, so we use 4 in the final formula, not the real entry_size
8590 * for the chip */
8591 entry_size = 4;
8592
8593 entries = (elements + (entry_size - 1)) / entry_size;
8594
8595 if (entries > stack->max_entries)
8596 stack->max_entries = entries;
8597 }
8598
8599 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
8600 {
8601 switch(reason) {
8602 case FC_PUSH_VPM:
8603 --ctx->bc->stack.push;
8604 assert(ctx->bc->stack.push >= 0);
8605 break;
8606 case FC_PUSH_WQM:
8607 --ctx->bc->stack.push_wqm;
8608 assert(ctx->bc->stack.push_wqm >= 0);
8609 break;
8610 case FC_LOOP:
8611 --ctx->bc->stack.loop;
8612 assert(ctx->bc->stack.loop >= 0);
8613 break;
8614 default:
8615 assert(0);
8616 break;
8617 }
8618 }
8619
8620 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
8621 {
8622 switch (reason) {
8623 case FC_PUSH_VPM:
8624 ++ctx->bc->stack.push;
8625 break;
8626 case FC_PUSH_WQM:
8627 ++ctx->bc->stack.push_wqm;
8628 case FC_LOOP:
8629 ++ctx->bc->stack.loop;
8630 break;
8631 default:
8632 assert(0);
8633 }
8634
8635 callstack_update_max_depth(ctx, reason);
8636 }
8637
8638 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
8639 {
8640 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
8641
8642 sp->mid = realloc((void *)sp->mid,
8643 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
8644 sp->mid[sp->num_mid] = ctx->bc->cf_last;
8645 sp->num_mid++;
8646 }
8647
8648 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
8649 {
8650 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
8651 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
8652 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
8653 ctx->bc->fc_sp++;
8654 }
8655
8656 static void fc_poplevel(struct r600_shader_ctx *ctx)
8657 {
8658 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
8659 free(sp->mid);
8660 sp->mid = NULL;
8661 sp->num_mid = 0;
8662 sp->start = NULL;
8663 sp->type = 0;
8664 ctx->bc->fc_sp--;
8665 }
8666
8667 #if 0
8668 static int emit_return(struct r600_shader_ctx *ctx)
8669 {
8670 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
8671 return 0;
8672 }
8673
8674 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
8675 {
8676
8677 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
8678 ctx->bc->cf_last->pop_count = pops;
8679 /* XXX work out offset */
8680 return 0;
8681 }
8682
8683 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
8684 {
8685 return 0;
8686 }
8687
8688 static void emit_testflag(struct r600_shader_ctx *ctx)
8689 {
8690
8691 }
8692
8693 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
8694 {
8695 emit_testflag(ctx);
8696 emit_jump_to_offset(ctx, 1, 4);
8697 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
8698 pops(ctx, ifidx + 1);
8699 emit_return(ctx);
8700 }
8701
8702 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
8703 {
8704 emit_testflag(ctx);
8705
8706 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8707 ctx->bc->cf_last->pop_count = 1;
8708
8709 fc_set_mid(ctx, fc_sp);
8710
8711 pops(ctx, 1);
8712 }
8713 #endif
8714
8715 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
8716 {
8717 int alu_type = CF_OP_ALU_PUSH_BEFORE;
8718
8719 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
8720 * LOOP_STARTxxx for nested loops may put the branch stack into a state
8721 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
8722 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
8723 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
8724 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
8725 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
8726 alu_type = CF_OP_ALU;
8727 }
8728
8729 emit_logic_pred(ctx, opcode, alu_type);
8730
8731 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
8732
8733 fc_pushlevel(ctx, FC_IF);
8734
8735 callstack_push(ctx, FC_PUSH_VPM);
8736 return 0;
8737 }
8738
8739 static int tgsi_if(struct r600_shader_ctx *ctx)
8740 {
8741 return emit_if(ctx, ALU_OP2_PRED_SETNE);
8742 }
8743
8744 static int tgsi_uif(struct r600_shader_ctx *ctx)
8745 {
8746 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
8747 }
8748
8749 static int tgsi_else(struct r600_shader_ctx *ctx)
8750 {
8751 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
8752 ctx->bc->cf_last->pop_count = 1;
8753
8754 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
8755 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
8756 return 0;
8757 }
8758
8759 static int tgsi_endif(struct r600_shader_ctx *ctx)
8760 {
8761 pops(ctx, 1);
8762 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
8763 R600_ERR("if/endif unbalanced in shader\n");
8764 return -1;
8765 }
8766
8767 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
8768 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8769 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
8770 } else {
8771 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
8772 }
8773 fc_poplevel(ctx);
8774
8775 callstack_pop(ctx, FC_PUSH_VPM);
8776 return 0;
8777 }
8778
8779 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
8780 {
8781 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
8782 * limited to 4096 iterations, like the other LOOP_* instructions. */
8783 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
8784
8785 fc_pushlevel(ctx, FC_LOOP);
8786
8787 /* check stack depth */
8788 callstack_push(ctx, FC_LOOP);
8789 return 0;
8790 }
8791
8792 static int tgsi_endloop(struct r600_shader_ctx *ctx)
8793 {
8794 unsigned i;
8795
8796 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
8797
8798 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
8799 R600_ERR("loop/endloop in shader code are not paired.\n");
8800 return -EINVAL;
8801 }
8802
8803 /* fixup loop pointers - from r600isa
8804 LOOP END points to CF after LOOP START,
8805 LOOP START point to CF after LOOP END
8806 BRK/CONT point to LOOP END CF
8807 */
8808 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
8809
8810 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
8811
8812 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
8813 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
8814 }
8815 /* XXX add LOOPRET support */
8816 fc_poplevel(ctx);
8817 callstack_pop(ctx, FC_LOOP);
8818 return 0;
8819 }
8820
8821 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
8822 {
8823 unsigned int fscp;
8824
8825 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
8826 {
8827 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
8828 break;
8829 }
8830
8831 if (fscp == 0) {
8832 R600_ERR("Break not inside loop/endloop pair\n");
8833 return -EINVAL;
8834 }
8835
8836 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8837
8838 fc_set_mid(ctx, fscp - 1);
8839
8840 return 0;
8841 }
8842
8843 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
8844 {
8845 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8846 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
8847 int r;
8848
8849 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8850 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
8851
8852 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
8853 if (!r) {
8854 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
8855 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
8856 return emit_inc_ring_offset(ctx, stream, TRUE);
8857 }
8858 return r;
8859 }
8860
8861 static int tgsi_umad(struct r600_shader_ctx *ctx)
8862 {
8863 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8864 struct r600_bytecode_alu alu;
8865 int i, j, k, r;
8866 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8867
8868 /* src0 * src1 */
8869 for (i = 0; i < lasti + 1; i++) {
8870 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8871 continue;
8872
8873 if (ctx->bc->chip_class == CAYMAN) {
8874 for (j = 0 ; j < 4; j++) {
8875 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8876
8877 alu.op = ALU_OP2_MULLO_UINT;
8878 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
8879 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
8880 }
8881 alu.dst.chan = j;
8882 alu.dst.sel = ctx->temp_reg;
8883 alu.dst.write = (j == i);
8884 if (j == 3)
8885 alu.last = 1;
8886 r = r600_bytecode_add_alu(ctx->bc, &alu);
8887 if (r)
8888 return r;
8889 }
8890 } else {
8891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8892
8893 alu.dst.chan = i;
8894 alu.dst.sel = ctx->temp_reg;
8895 alu.dst.write = 1;
8896
8897 alu.op = ALU_OP2_MULLO_UINT;
8898 for (j = 0; j < 2; j++) {
8899 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
8900 }
8901
8902 alu.last = 1;
8903 r = r600_bytecode_add_alu(ctx->bc, &alu);
8904 if (r)
8905 return r;
8906 }
8907 }
8908
8909
8910 for (i = 0; i < lasti + 1; i++) {
8911 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8912 continue;
8913
8914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8915 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8916
8917 alu.op = ALU_OP2_ADD_INT;
8918
8919 alu.src[0].sel = ctx->temp_reg;
8920 alu.src[0].chan = i;
8921
8922 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8923 if (i == lasti) {
8924 alu.last = 1;
8925 }
8926 r = r600_bytecode_add_alu(ctx->bc, &alu);
8927 if (r)
8928 return r;
8929 }
8930 return 0;
8931 }
8932
8933 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
8934 {
8935 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8936 struct r600_bytecode_alu alu;
8937 int r, i;
8938 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8939
8940 /* temp.xy = f32_to_f16(src) */
8941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8942 alu.op = ALU_OP1_FLT32_TO_FLT16;
8943 alu.dst.chan = 0;
8944 alu.dst.sel = ctx->temp_reg;
8945 alu.dst.write = 1;
8946 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8947 r = r600_bytecode_add_alu(ctx->bc, &alu);
8948 if (r)
8949 return r;
8950 alu.dst.chan = 1;
8951 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
8952 alu.last = 1;
8953 r = r600_bytecode_add_alu(ctx->bc, &alu);
8954 if (r)
8955 return r;
8956
8957 /* dst.x = temp.y * 0x10000 + temp.x */
8958 for (i = 0; i < lasti + 1; i++) {
8959 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8960 continue;
8961
8962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8963 alu.op = ALU_OP3_MULADD_UINT24;
8964 alu.is_op3 = 1;
8965 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8966 alu.last = i == lasti;
8967 alu.src[0].sel = ctx->temp_reg;
8968 alu.src[0].chan = 1;
8969 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8970 alu.src[1].value = 0x10000;
8971 alu.src[2].sel = ctx->temp_reg;
8972 alu.src[2].chan = 0;
8973 r = r600_bytecode_add_alu(ctx->bc, &alu);
8974 if (r)
8975 return r;
8976 }
8977
8978 return 0;
8979 }
8980
8981 static int tgsi_up2h(struct r600_shader_ctx *ctx)
8982 {
8983 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8984 struct r600_bytecode_alu alu;
8985 int r, i;
8986 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8987
8988 /* temp.x = src.x */
8989 /* note: no need to mask out the high bits */
8990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8991 alu.op = ALU_OP1_MOV;
8992 alu.dst.chan = 0;
8993 alu.dst.sel = ctx->temp_reg;
8994 alu.dst.write = 1;
8995 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8996 r = r600_bytecode_add_alu(ctx->bc, &alu);
8997 if (r)
8998 return r;
8999
9000 /* temp.y = src.x >> 16 */
9001 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9002 alu.op = ALU_OP2_LSHR_INT;
9003 alu.dst.chan = 1;
9004 alu.dst.sel = ctx->temp_reg;
9005 alu.dst.write = 1;
9006 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9007 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9008 alu.src[1].value = 16;
9009 alu.last = 1;
9010 r = r600_bytecode_add_alu(ctx->bc, &alu);
9011 if (r)
9012 return r;
9013
9014 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9015 for (i = 0; i < lasti + 1; i++) {
9016 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9017 continue;
9018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9019 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9020 alu.op = ALU_OP1_FLT16_TO_FLT32;
9021 alu.src[0].sel = ctx->temp_reg;
9022 alu.src[0].chan = i % 2;
9023 alu.last = i == lasti;
9024 r = r600_bytecode_add_alu(ctx->bc, &alu);
9025 if (r)
9026 return r;
9027 }
9028
9029 return 0;
9030 }
9031
9032 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9033 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9034 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9035 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9036
9037 /* XXX:
9038 * For state trackers other than OpenGL, we'll want to use
9039 * _RECIP_IEEE instead.
9040 */
9041 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
9042
9043 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9044 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9045 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9046 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9047 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9048 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9049 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9050 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9051 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9052 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9053 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9054 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9055 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9056 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9057 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9058 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9059 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9060 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9061 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9062 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9063 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9064 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9065 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9066 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9067 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9068 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9069 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9070 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9071 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9072 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9073 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9074 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9075 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9076 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9077 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9078 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9079 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9080 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9081 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9082 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9083 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9084 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9085 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9086 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9087 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9088 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9089 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9090 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9091 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9092 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9093 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9094 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9095 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9096 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9097 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9098 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9099 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9100 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9101 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9102 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9103 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9104 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9105 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9106 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9107 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9108 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9109 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9110 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9111 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9112 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9113 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9114 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9115 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9116 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9117 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9118 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9119 [81] = { ALU_OP0_NOP, tgsi_unsupported},
9120 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9121 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9122 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9123 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9124 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9125 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9126 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9127 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9128 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9129 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9130 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9131 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9132 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9133 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9134 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9135 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9136 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9137 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9138 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9139 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9140 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9141 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9142 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9143 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9144 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9145 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9146 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9147 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9148 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9149 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9150 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9151 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9152 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9153 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9154 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9155 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9156 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9157 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9158 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9159 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9160 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9161 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9162 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9163 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9164 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9165 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9166 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9167 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9168 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9169 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9170 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9171 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9172 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9173 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9174 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9175 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9176 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9177 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9178 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9179 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9180 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9181 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9182 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9183 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9184 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9185 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9186 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9187 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9188 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9189 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9190 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9191 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9192 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9193 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9194 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9195 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9196 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9197 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9198 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9199 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9200 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9201 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9202 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9203 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9204 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9205 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9206 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9207 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9208 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9209 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9210 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9211 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9212 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9213 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9214 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9215 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9216 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9217 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9218 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9219 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9220 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9221 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9222 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9223 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9224 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9225 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9226 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9227 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9228 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9229 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9230 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9231 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9232 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9233 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9234 };
9235
9236 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9237 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9238 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9239 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9240 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9241 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
9242 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9243 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9244 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9245 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9246 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9247 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9248 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9249 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9250 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9251 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9252 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9253 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9254 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9255 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9256 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9257 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9258 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9259 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9260 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9261 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9262 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9263 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9264 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9265 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9266 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9267 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9268 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9269 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9270 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9271 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9272 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9273 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9274 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9275 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9276 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9277 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9278 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9279 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9280 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9281 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9282 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9283 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9284 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9285 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9286 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9287 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9288 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9289 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9290 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9291 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9292 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9293 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9294 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9295 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9296 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9297 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9298 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9299 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9300 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9301 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9302 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9303 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9304 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9305 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9306 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9307 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9308 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9309 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9310 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9311 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9312 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9313 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9314 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9315 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9316 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9317 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9318 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9319 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9320 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9321 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9322 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9323 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9324 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9325 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9326 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9327 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9328 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9329 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9330 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9331 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9332 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9333 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9334 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9335 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9336 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9337 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9338 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9339 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9340 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9341 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9342 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9343 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9344 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9345 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9346 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9347 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9348 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9349 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9350 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9351 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9352 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9353 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9354 /* Refer below for TGSI_OPCODE_DFMA */
9355 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9356 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9357 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9358 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9359 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9360 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9361 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9362 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9363 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9364 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9365 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9366 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9367 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9368 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9369 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9370 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9371 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9372 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9373 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9374 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9375 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9376 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9377 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9378 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9379 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9380 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9381 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9382 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9383 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9384 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9385 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9386 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9387 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9388 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9389 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9390 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9391 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9392 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9393 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9394 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9395 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9396 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9397 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9398 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9399 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9400 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9401 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9402 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9403 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9404 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9405 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9406 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9407 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9408 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9409 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9410 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9411 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9412 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9413 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9414 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9415 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9416 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9417 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9418 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9419 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9420 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9421 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9422 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9423 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9424 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9425 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9426 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9427 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9428 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9429 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9430 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9431 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9432 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9433 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9434 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9435 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9436 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9437 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9438 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9439 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9440 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9441 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9442 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9443 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9444 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9445 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9446 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9447 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9448 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9449 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9450 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9451 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9452 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9453 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9454 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9455 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9456 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9457 };
9458
9459 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
9460 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9461 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9462 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9463 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
9464 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
9465 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9466 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9467 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9468 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9469 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9470 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9471 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9472 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
9473 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
9474 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9475 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9476 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9477 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9478 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9479 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
9480 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9481 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9482 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9483 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9484 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9485 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9486 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9487 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
9488 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
9489 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
9490 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9491 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9492 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9493 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9494 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9495 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
9496 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9497 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9498 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9499 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9500 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9501 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9502 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9503 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9504 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9505 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9506 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9507 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
9508 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9509 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9510 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9511 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9512 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9513 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9514 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9515 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9516 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9517 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9518 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9519 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9520 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9521 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9522 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9523 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9524 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9525 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9526 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9527 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9528 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9529 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9530 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9531 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9532 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9533 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9534 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9535 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9536 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9537 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9538 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9539 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9540 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9541 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9542 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9543 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
9544 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9545 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9546 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9547 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9548 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9549 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9550 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9551 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9552 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9553 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9554 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9555 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9556 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9557 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9558 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9559 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9560 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9561 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9562 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9563 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9564 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9565 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9566 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9567 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9568 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9569 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9570 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9571 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9572 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9573 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9574 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9575 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9576 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9577 /* Refer below for TGSI_OPCODE_DFMA */
9578 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
9579 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9580 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9581 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9582 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9583 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9584 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9585 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9586 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
9587 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
9588 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9589 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9590 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9591 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9592 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9593 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9594 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
9595 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9596 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9597 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9598 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9599 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9600 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9601 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9602 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9603 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9604 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9605 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9606 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9607 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9608 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9609 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9610 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9611 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9612 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9613 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9614 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9615 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9616 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9617 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9618 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9619 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9620 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9621 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9622 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9623 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9624 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9625 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9626 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9627 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9628 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9629 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9630 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9631 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9632 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9633 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9634 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9635 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9636 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9637 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9638 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9639 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
9640 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
9641 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9642 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9643 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
9644 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
9645 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9646 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9647 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
9648 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
9649 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
9650 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
9651 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
9652 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
9653 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
9654 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
9655 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
9656 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
9657 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
9658 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
9659 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
9660 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
9661 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
9662 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
9663 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
9664 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
9665 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
9666 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
9667 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
9668 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
9669 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
9670 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
9671 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
9672 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
9673 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
9674 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
9675 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
9676 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
9677 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
9678 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
9679 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9680 };