projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: Implement gpu_shader5 integer ops
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_context *rctx,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static void r600_dump_streamout(struct pipe_stream_output_info *so)
88 {
89 unsigned i;
90
91 fprintf(stderr, "STREAMOUT\n");
92 for (i = 0; i < so->num_outputs; i++) {
93 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
94 so->output[i].start_component;
95 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
96 i, so->output[i].output_buffer,
97 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
98 so->output[i].register_index,
99 mask & 1 ? "x" : "",
100 mask & 2 ? "y" : "",
101 mask & 4 ? "z" : "",
102 mask & 8 ? "w" : "",
103 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
104 }
105 }
106
107 static int store_shader(struct pipe_context *ctx,
108 struct r600_pipe_shader *shader)
109 {
110 struct r600_context *rctx = (struct r600_context *)ctx;
111 uint32_t *ptr, i;
112
113 if (shader->bo == NULL) {
114 shader->bo = (struct r600_resource*)
115 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
116 if (shader->bo == NULL) {
117 return -ENOMEM;
118 }
119 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
120 if (R600_BIG_ENDIAN) {
121 for (i = 0; i < shader->shader.bc.ndw; ++i) {
122 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
123 }
124 } else {
125 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
126 }
127 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
128 }
129
130 return 0;
131 }
132
133 int r600_pipe_shader_create(struct pipe_context *ctx,
134 struct r600_pipe_shader *shader,
135 struct r600_shader_key key)
136 {
137 struct r600_context *rctx = (struct r600_context *)ctx;
138 struct r600_pipe_shader_selector *sel = shader->selector;
139 int r;
140 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
141 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
142 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
143 unsigned export_shader = key.vs_as_es;
144
145 shader->shader.bc.isa = rctx->isa;
146
147 if (dump) {
148 fprintf(stderr, "--------------------------------------------------------------\n");
149 tgsi_dump(sel->tokens, 0);
150
151 if (sel->so.num_outputs) {
152 r600_dump_streamout(&sel->so);
153 }
154 }
155 r = r600_shader_from_tgsi(rctx, shader, key);
156 if (r) {
157 R600_ERR("translation from TGSI failed !\n");
158 goto error;
159 }
160
161 /* disable SB for geom shaders - it can't handle the CF_EMIT instructions */
162 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_GEOMETRY);
163
164 /* Check if the bytecode has already been built. When using the llvm
165 * backend, r600_shader_from_tgsi() will take care of building the
166 * bytecode.
167 */
168 if (!shader->shader.bc.bytecode) {
169 r = r600_bytecode_build(&shader->shader.bc);
170 if (r) {
171 R600_ERR("building bytecode failed !\n");
172 goto error;
173 }
174 }
175
176 if (dump && !sb_disasm) {
177 fprintf(stderr, "--------------------------------------------------------------\n");
178 r600_bytecode_disasm(&shader->shader.bc);
179 fprintf(stderr, "______________________________________________________________\n");
180 } else if ((dump && sb_disasm) || use_sb) {
181 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
182 dump, use_sb);
183 if (r) {
184 R600_ERR("r600_sb_bytecode_process failed !\n");
185 goto error;
186 }
187 }
188
189 if (shader->gs_copy_shader) {
190 if (dump) {
191 // dump copy shader
192 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
193 &shader->gs_copy_shader->shader, dump, 0);
194 if (r)
195 goto error;
196 }
197
198 if ((r = store_shader(ctx, shader->gs_copy_shader)))
199 goto error;
200 }
201
202 /* Store the shader in a buffer. */
203 if ((r = store_shader(ctx, shader)))
204 goto error;
205
206 /* Build state. */
207 switch (shader->shader.processor_type) {
208 case TGSI_PROCESSOR_GEOMETRY:
209 if (rctx->b.chip_class >= EVERGREEN) {
210 evergreen_update_gs_state(ctx, shader);
211 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
212 } else {
213 r600_update_gs_state(ctx, shader);
214 r600_update_vs_state(ctx, shader->gs_copy_shader);
215 }
216 break;
217 case TGSI_PROCESSOR_VERTEX:
218 if (rctx->b.chip_class >= EVERGREEN) {
219 if (export_shader)
220 evergreen_update_es_state(ctx, shader);
221 else
222 evergreen_update_vs_state(ctx, shader);
223 } else {
224 if (export_shader)
225 r600_update_es_state(ctx, shader);
226 else
227 r600_update_vs_state(ctx, shader);
228 }
229 break;
230 case TGSI_PROCESSOR_FRAGMENT:
231 if (rctx->b.chip_class >= EVERGREEN) {
232 evergreen_update_ps_state(ctx, shader);
233 } else {
234 r600_update_ps_state(ctx, shader);
235 }
236 break;
237 default:
238 r = -EINVAL;
239 goto error;
240 }
241 return 0;
242
243 error:
244 r600_pipe_shader_destroy(ctx, shader);
245 return r;
246 }
247
248 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
249 {
250 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
251 r600_bytecode_clear(&shader->shader.bc);
252 r600_release_command_buffer(&shader->command_buffer);
253 }
254
255 /*
256 * tgsi -> r600 shader
257 */
258 struct r600_shader_tgsi_instruction;
259
260 struct r600_shader_src {
261 unsigned sel;
262 unsigned swizzle[4];
263 unsigned neg;
264 unsigned abs;
265 unsigned rel;
266 unsigned kc_bank;
267 uint32_t value[4];
268 };
269
270 struct r600_shader_ctx {
271 struct tgsi_shader_info info;
272 struct tgsi_parse_context parse;
273 const struct tgsi_token *tokens;
274 unsigned type;
275 unsigned file_offset[TGSI_FILE_COUNT];
276 unsigned temp_reg;
277 struct r600_shader_tgsi_instruction *inst_info;
278 struct r600_bytecode *bc;
279 struct r600_shader *shader;
280 struct r600_shader_src src[4];
281 uint32_t *literals;
282 uint32_t nliterals;
283 uint32_t max_driver_temp_used;
284 boolean use_llvm;
285 /* needed for evergreen interpolation */
286 boolean input_centroid;
287 boolean input_linear;
288 boolean input_perspective;
289 int num_interp_gpr;
290 int face_gpr;
291 int colors_used;
292 boolean clip_vertex_write;
293 unsigned cv_output;
294 unsigned edgeflag_output;
295 int fragcoord_input;
296 int native_integers;
297 int next_ring_offset;
298 int gs_out_ring_offset;
299 int gs_next_vertex;
300 struct r600_shader *gs_for_vs;
301 int gs_export_gpr_treg;
302 };
303
304 struct r600_shader_tgsi_instruction {
305 unsigned tgsi_opcode;
306 unsigned is_op3;
307 unsigned op;
308 int (*process)(struct r600_shader_ctx *ctx);
309 };
310
311 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind);
312 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
313 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
314 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
315 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
316 static int tgsi_else(struct r600_shader_ctx *ctx);
317 static int tgsi_endif(struct r600_shader_ctx *ctx);
318 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
319 static int tgsi_endloop(struct r600_shader_ctx *ctx);
320 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
321
322 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
323 {
324 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
325 int j;
326
327 if (i->Instruction.NumDstRegs > 1) {
328 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
329 return -EINVAL;
330 }
331 if (i->Instruction.Predicate) {
332 R600_ERR("predicate unsupported\n");
333 return -EINVAL;
334 }
335 #if 0
336 if (i->Instruction.Label) {
337 R600_ERR("label unsupported\n");
338 return -EINVAL;
339 }
340 #endif
341 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
342 if (i->Src[j].Register.Dimension) {
343 switch (i->Src[j].Register.File) {
344 case TGSI_FILE_CONSTANT:
345 break;
346 case TGSI_FILE_INPUT:
347 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
348 break;
349 default:
350 R600_ERR("unsupported src %d (dimension %d)\n", j,
351 i->Src[j].Register.Dimension);
352 return -EINVAL;
353 }
354 }
355 }
356 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
357 if (i->Dst[j].Register.Dimension) {
358 R600_ERR("unsupported dst (dimension)\n");
359 return -EINVAL;
360 }
361 }
362 return 0;
363 }
364
365 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
366 int input)
367 {
368 int ij_index = 0;
369
370 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
371 if (ctx->shader->input[input].centroid)
372 ij_index++;
373 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
374 /* if we have perspective add one */
375 if (ctx->input_perspective) {
376 ij_index++;
377 /* if we have perspective centroid */
378 if (ctx->input_centroid)
379 ij_index++;
380 }
381 if (ctx->shader->input[input].centroid)
382 ij_index++;
383 }
384
385 ctx->shader->input[input].ij_index = ij_index;
386 }
387
388 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
389 {
390 int i, r;
391 struct r600_bytecode_alu alu;
392 int gpr = 0, base_chan = 0;
393 int ij_index = ctx->shader->input[input].ij_index;
394
395 /* work out gpr and base_chan from index */
396 gpr = ij_index / 2;
397 base_chan = (2 * (ij_index % 2)) + 1;
398
399 for (i = 0; i < 8; i++) {
400 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
401
402 if (i < 4)
403 alu.op = ALU_OP2_INTERP_ZW;
404 else
405 alu.op = ALU_OP2_INTERP_XY;
406
407 if ((i > 1) && (i < 6)) {
408 alu.dst.sel = ctx->shader->input[input].gpr;
409 alu.dst.write = 1;
410 }
411
412 alu.dst.chan = i % 4;
413
414 alu.src[0].sel = gpr;
415 alu.src[0].chan = (base_chan - (i % 2));
416
417 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
418
419 alu.bank_swizzle_force = SQ_ALU_VEC_210;
420 if ((i % 4) == 3)
421 alu.last = 1;
422 r = r600_bytecode_add_alu(ctx->bc, &alu);
423 if (r)
424 return r;
425 }
426 return 0;
427 }
428
429 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
430 {
431 int i, r;
432 struct r600_bytecode_alu alu;
433
434 for (i = 0; i < 4; i++) {
435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
436
437 alu.op = ALU_OP1_INTERP_LOAD_P0;
438
439 alu.dst.sel = ctx->shader->input[input].gpr;
440 alu.dst.write = 1;
441
442 alu.dst.chan = i;
443
444 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
445 alu.src[0].chan = i;
446
447 if (i == 3)
448 alu.last = 1;
449 r = r600_bytecode_add_alu(ctx->bc, &alu);
450 if (r)
451 return r;
452 }
453 return 0;
454 }
455
456 /*
457 * Special export handling in shaders
458 *
459 * shader export ARRAY_BASE for EXPORT_POS:
460 * 60 is position
461 * 61 is misc vector
462 * 62, 63 are clip distance vectors
463 *
464 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
465 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
466 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
467 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
468 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
469 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
470 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
471 * exclusive from render target index)
472 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
473 *
474 *
475 * shader export ARRAY_BASE for EXPORT_PIXEL:
476 * 0-7 CB targets
477 * 61 computed Z vector
478 *
479 * The use of the values exported in the computed Z vector are controlled
480 * by DB_SHADER_CONTROL:
481 * Z_EXPORT_ENABLE - Z as a float in RED
482 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
483 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
484 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
485 * DB_SOURCE_FORMAT - export control restrictions
486 *
487 */
488
489
490 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
491 static int r600_spi_sid(struct r600_shader_io * io)
492 {
493 int index, name = io->name;
494
495 /* These params are handled differently, they don't need
496 * semantic indices, so we'll use 0 for them.
497 */
498 if (name == TGSI_SEMANTIC_POSITION ||
499 name == TGSI_SEMANTIC_PSIZE ||
500 name == TGSI_SEMANTIC_EDGEFLAG ||
501 name == TGSI_SEMANTIC_FACE)
502 index = 0;
503 else {
504 if (name == TGSI_SEMANTIC_GENERIC) {
505 /* For generic params simply use sid from tgsi */
506 index = io->sid;
507 } else {
508 /* For non-generic params - pack name and sid into 8 bits */
509 index = 0x80 | (name<<3) | (io->sid);
510 }
511
512 /* Make sure that all really used indices have nonzero value, so
513 * we can just compare it to 0 later instead of comparing the name
514 * with different values to detect special cases. */
515 index++;
516 }
517
518 return index;
519 };
520
521 /* turn input into interpolate on EG */
522 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
523 {
524 int r = 0;
525
526 if (ctx->shader->input[index].spi_sid) {
527 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
528 if (ctx->shader->input[index].interpolate > 0) {
529 evergreen_interp_assign_ij_index(ctx, index);
530 if (!ctx->use_llvm)
531 r = evergreen_interp_alu(ctx, index);
532 } else {
533 if (!ctx->use_llvm)
534 r = evergreen_interp_flat(ctx, index);
535 }
536 }
537 return r;
538 }
539
540 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
541 {
542 struct r600_bytecode_alu alu;
543 int i, r;
544 int gpr_front = ctx->shader->input[front].gpr;
545 int gpr_back = ctx->shader->input[back].gpr;
546
547 for (i = 0; i < 4; i++) {
548 memset(&alu, 0, sizeof(alu));
549 alu.op = ALU_OP3_CNDGT;
550 alu.is_op3 = 1;
551 alu.dst.write = 1;
552 alu.dst.sel = gpr_front;
553 alu.src[0].sel = ctx->face_gpr;
554 alu.src[1].sel = gpr_front;
555 alu.src[2].sel = gpr_back;
556
557 alu.dst.chan = i;
558 alu.src[1].chan = i;
559 alu.src[2].chan = i;
560 alu.last = (i==3);
561
562 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
563 return r;
564 }
565
566 return 0;
567 }
568
569 static int tgsi_declaration(struct r600_shader_ctx *ctx)
570 {
571 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
572 int r, i, j, count = d->Range.Last - d->Range.First + 1;
573
574 switch (d->Declaration.File) {
575 case TGSI_FILE_INPUT:
576 i = ctx->shader->ninput;
577 assert(i < Elements(ctx->shader->input));
578 ctx->shader->ninput += count;
579 ctx->shader->input[i].name = d->Semantic.Name;
580 ctx->shader->input[i].sid = d->Semantic.Index;
581 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
582 ctx->shader->input[i].centroid = d->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID;
583 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
584 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
585 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
586 switch (ctx->shader->input[i].name) {
587 case TGSI_SEMANTIC_FACE:
588 ctx->face_gpr = ctx->shader->input[i].gpr;
589 break;
590 case TGSI_SEMANTIC_COLOR:
591 ctx->colors_used++;
592 break;
593 case TGSI_SEMANTIC_POSITION:
594 ctx->fragcoord_input = i;
595 break;
596 }
597 if (ctx->bc->chip_class >= EVERGREEN) {
598 if ((r = evergreen_interp_input(ctx, i)))
599 return r;
600 }
601 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
602 /* FIXME probably skip inputs if they aren't passed in the ring */
603 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
604 ctx->next_ring_offset += 16;
605 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
606 ctx->shader->gs_prim_id_input = true;
607 }
608 for (j = 1; j < count; ++j) {
609 ctx->shader->input[i + j] = ctx->shader->input[i];
610 ctx->shader->input[i + j].gpr += j;
611 }
612 break;
613 case TGSI_FILE_OUTPUT:
614 i = ctx->shader->noutput++;
615 assert(i < Elements(ctx->shader->output));
616 ctx->shader->output[i].name = d->Semantic.Name;
617 ctx->shader->output[i].sid = d->Semantic.Index;
618 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
619 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
620 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
621 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
622 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
623 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
624 switch (d->Semantic.Name) {
625 case TGSI_SEMANTIC_CLIPDIST:
626 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
627 break;
628 case TGSI_SEMANTIC_PSIZE:
629 ctx->shader->vs_out_misc_write = 1;
630 ctx->shader->vs_out_point_size = 1;
631 break;
632 case TGSI_SEMANTIC_EDGEFLAG:
633 ctx->shader->vs_out_misc_write = 1;
634 ctx->shader->vs_out_edgeflag = 1;
635 ctx->edgeflag_output = i;
636 break;
637 case TGSI_SEMANTIC_VIEWPORT_INDEX:
638 ctx->shader->vs_out_misc_write = 1;
639 ctx->shader->vs_out_viewport = 1;
640 break;
641 case TGSI_SEMANTIC_LAYER:
642 ctx->shader->vs_out_misc_write = 1;
643 ctx->shader->vs_out_layer = 1;
644 break;
645 case TGSI_SEMANTIC_CLIPVERTEX:
646 ctx->clip_vertex_write = TRUE;
647 ctx->cv_output = i;
648 break;
649 }
650 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
651 ctx->gs_out_ring_offset += 16;
652 }
653 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
654 switch (d->Semantic.Name) {
655 case TGSI_SEMANTIC_COLOR:
656 ctx->shader->nr_ps_max_color_exports++;
657 break;
658 }
659 }
660 break;
661 case TGSI_FILE_TEMPORARY:
662 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
663 if (d->Array.ArrayID) {
664 r600_add_gpr_array(ctx->shader,
665 ctx->file_offset[TGSI_FILE_TEMPORARY] +
666 d->Range.First,
667 d->Range.Last - d->Range.First + 1, 0x0F);
668 }
669 }
670 break;
671
672 case TGSI_FILE_CONSTANT:
673 case TGSI_FILE_SAMPLER:
674 case TGSI_FILE_ADDRESS:
675 break;
676
677 case TGSI_FILE_SYSTEM_VALUE:
678 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
679 if (!ctx->native_integers) {
680 struct r600_bytecode_alu alu;
681 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
682
683 alu.op = ALU_OP1_INT_TO_FLT;
684 alu.src[0].sel = 0;
685 alu.src[0].chan = 3;
686
687 alu.dst.sel = 0;
688 alu.dst.chan = 3;
689 alu.dst.write = 1;
690 alu.last = 1;
691
692 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
693 return r;
694 }
695 break;
696 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
697 break;
698 default:
699 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
700 return -EINVAL;
701 }
702 return 0;
703 }
704
705 static int r600_get_temp(struct r600_shader_ctx *ctx)
706 {
707 return ctx->temp_reg + ctx->max_driver_temp_used++;
708 }
709
710 /*
711 * for evergreen we need to scan the shader to find the number of GPRs we need to
712 * reserve for interpolation.
713 *
714 * we need to know if we are going to emit
715 * any centroid inputs
716 * if perspective and linear are required
717 */
718 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
719 {
720 int i;
721 int num_baryc;
722
723 ctx->input_linear = FALSE;
724 ctx->input_perspective = FALSE;
725 ctx->input_centroid = FALSE;
726 ctx->num_interp_gpr = 1;
727
728 /* any centroid inputs */
729 for (i = 0; i < ctx->info.num_inputs; i++) {
730 /* skip position/face */
731 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
732 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
733 continue;
734 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
735 ctx->input_linear = TRUE;
736 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
737 ctx->input_perspective = TRUE;
738 if (ctx->info.input_interpolate_loc[i] == TGSI_INTERPOLATE_LOC_CENTROID)
739 ctx->input_centroid = TRUE;
740 }
741
742 num_baryc = 0;
743 /* ignoring sample for now */
744 if (ctx->input_perspective)
745 num_baryc++;
746 if (ctx->input_linear)
747 num_baryc++;
748 if (ctx->input_centroid)
749 num_baryc *= 2;
750
751 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
752
753 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
754 return ctx->num_interp_gpr;
755 }
756
757 static void tgsi_src(struct r600_shader_ctx *ctx,
758 const struct tgsi_full_src_register *tgsi_src,
759 struct r600_shader_src *r600_src)
760 {
761 memset(r600_src, 0, sizeof(*r600_src));
762 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
763 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
764 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
765 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
766 r600_src->neg = tgsi_src->Register.Negate;
767 r600_src->abs = tgsi_src->Register.Absolute;
768
769 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
770 int index;
771 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
772 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
773 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
774
775 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
776 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
777 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
778 return;
779 }
780 index = tgsi_src->Register.Index;
781 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
782 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
783 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
784 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
785 r600_src->swizzle[0] = 3;
786 r600_src->swizzle[1] = 3;
787 r600_src->swizzle[2] = 3;
788 r600_src->swizzle[3] = 3;
789 r600_src->sel = 0;
790 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
791 r600_src->swizzle[0] = 0;
792 r600_src->swizzle[1] = 0;
793 r600_src->swizzle[2] = 0;
794 r600_src->swizzle[3] = 0;
795 r600_src->sel = 0;
796 }
797 } else {
798 if (tgsi_src->Register.Indirect)
799 r600_src->rel = V_SQ_REL_RELATIVE;
800 r600_src->sel = tgsi_src->Register.Index;
801 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
802 }
803 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
804 if (tgsi_src->Register.Dimension) {
805 r600_src->kc_bank = tgsi_src->Dimension.Index;
806 }
807 }
808 }
809
810 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
811 unsigned int cb_idx, unsigned int offset, unsigned ar_chan,
812 unsigned int dst_reg)
813 {
814 struct r600_bytecode_vtx vtx;
815 unsigned int ar_reg;
816 int r;
817
818 if (offset) {
819 struct r600_bytecode_alu alu;
820
821 memset(&alu, 0, sizeof(alu));
822
823 alu.op = ALU_OP2_ADD_INT;
824 alu.src[0].sel = ctx->bc->ar_reg;
825 alu.src[0].chan = ar_chan;
826
827 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
828 alu.src[1].value = offset;
829
830 alu.dst.sel = dst_reg;
831 alu.dst.chan = ar_chan;
832 alu.dst.write = 1;
833 alu.last = 1;
834
835 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
836 return r;
837
838 ar_reg = dst_reg;
839 } else {
840 ar_reg = ctx->bc->ar_reg;
841 }
842
843 memset(&vtx, 0, sizeof(vtx));
844 vtx.buffer_id = cb_idx;
845 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
846 vtx.src_gpr = ar_reg;
847 vtx.src_sel_x = ar_chan;
848 vtx.mega_fetch_count = 16;
849 vtx.dst_gpr = dst_reg;
850 vtx.dst_sel_x = 0; /* SEL_X */
851 vtx.dst_sel_y = 1; /* SEL_Y */
852 vtx.dst_sel_z = 2; /* SEL_Z */
853 vtx.dst_sel_w = 3; /* SEL_W */
854 vtx.data_format = FMT_32_32_32_32_FLOAT;
855 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
856 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
857 vtx.endian = r600_endian_swap(32);
858
859 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
860 return r;
861
862 return 0;
863 }
864
865 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
866 {
867 struct r600_bytecode_vtx vtx;
868 int r;
869 unsigned index = src->Register.Index;
870 unsigned vtx_id = src->Dimension.Index;
871 int offset_reg = vtx_id / 3;
872 int offset_chan = vtx_id % 3;
873
874 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
875 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
876
877 if (offset_reg == 0 && offset_chan == 2)
878 offset_chan = 3;
879
880 if (src->Dimension.Indirect) {
881 int treg[3];
882 int t2;
883 struct r600_bytecode_alu alu;
884 int r, i;
885
886 /* you have got to be shitting me -
887 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
888 at least this is what fglrx seems to do. */
889 for (i = 0; i < 3; i++) {
890 treg[i] = r600_get_temp(ctx);
891 }
892 t2 = r600_get_temp(ctx);
893 for (i = 0; i < 3; i++) {
894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
895 alu.op = ALU_OP1_MOV;
896 alu.src[0].sel = 0;
897 alu.src[0].chan = i == 2 ? 3 : i;
898 alu.dst.sel = treg[i];
899 alu.dst.chan = 0;
900 alu.dst.write = 1;
901 alu.last = 1;
902 r = r600_bytecode_add_alu(ctx->bc, &alu);
903 if (r)
904 return r;
905 }
906 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
907 alu.op = ALU_OP1_MOV;
908 alu.src[0].sel = treg[0];
909 alu.src[0].rel = 1;
910 alu.dst.sel = t2;
911 alu.dst.write = 1;
912 alu.last = 1;
913 r = r600_bytecode_add_alu(ctx->bc, &alu);
914 if (r)
915 return r;
916 offset_reg = t2;
917 }
918
919
920 memset(&vtx, 0, sizeof(vtx));
921 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
922 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
923 vtx.src_gpr = offset_reg;
924 vtx.src_sel_x = offset_chan;
925 vtx.offset = index * 16; /*bytes*/
926 vtx.mega_fetch_count = 16;
927 vtx.dst_gpr = dst_reg;
928 vtx.dst_sel_x = 0; /* SEL_X */
929 vtx.dst_sel_y = 1; /* SEL_Y */
930 vtx.dst_sel_z = 2; /* SEL_Z */
931 vtx.dst_sel_w = 3; /* SEL_W */
932 if (ctx->bc->chip_class >= EVERGREEN) {
933 vtx.use_const_fields = 1;
934 } else {
935 vtx.data_format = FMT_32_32_32_32_FLOAT;
936 }
937
938 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
939 return r;
940
941 return 0;
942 }
943
944 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
945 {
946 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
947 int i;
948
949 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
950 struct tgsi_full_src_register *src = &inst->Src[i];
951
952 if (src->Register.File == TGSI_FILE_INPUT) {
953 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
954 /* primitive id is in R0.z */
955 ctx->src[i].sel = 0;
956 ctx->src[i].swizzle[0] = 2;
957 }
958 }
959 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
960 int treg = r600_get_temp(ctx);
961
962 fetch_gs_input(ctx, src, treg);
963 ctx->src[i].sel = treg;
964 }
965 }
966 return 0;
967 }
968
969 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
970 {
971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
972 struct r600_bytecode_alu alu;
973 int i, j, k, nconst, r;
974
975 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
976 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
977 nconst++;
978 }
979 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
980 }
981 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
982 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
983 continue;
984 }
985
986 if (ctx->src[i].rel) {
987 int chan = inst->Src[i].Indirect.Swizzle;
988 int treg = r600_get_temp(ctx);
989 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, chan, treg)))
990 return r;
991
992 ctx->src[i].kc_bank = 0;
993 ctx->src[i].sel = treg;
994 ctx->src[i].rel = 0;
995 j--;
996 } else if (j > 0) {
997 int treg = r600_get_temp(ctx);
998 for (k = 0; k < 4; k++) {
999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1000 alu.op = ALU_OP1_MOV;
1001 alu.src[0].sel = ctx->src[i].sel;
1002 alu.src[0].chan = k;
1003 alu.src[0].rel = ctx->src[i].rel;
1004 alu.dst.sel = treg;
1005 alu.dst.chan = k;
1006 alu.dst.write = 1;
1007 if (k == 3)
1008 alu.last = 1;
1009 r = r600_bytecode_add_alu(ctx->bc, &alu);
1010 if (r)
1011 return r;
1012 }
1013 ctx->src[i].sel = treg;
1014 ctx->src[i].rel =0;
1015 j--;
1016 }
1017 }
1018 return 0;
1019 }
1020
1021 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1022 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1023 {
1024 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1025 struct r600_bytecode_alu alu;
1026 int i, j, k, nliteral, r;
1027
1028 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1029 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1030 nliteral++;
1031 }
1032 }
1033 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1034 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1035 int treg = r600_get_temp(ctx);
1036 for (k = 0; k < 4; k++) {
1037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1038 alu.op = ALU_OP1_MOV;
1039 alu.src[0].sel = ctx->src[i].sel;
1040 alu.src[0].chan = k;
1041 alu.src[0].value = ctx->src[i].value[k];
1042 alu.dst.sel = treg;
1043 alu.dst.chan = k;
1044 alu.dst.write = 1;
1045 if (k == 3)
1046 alu.last = 1;
1047 r = r600_bytecode_add_alu(ctx->bc, &alu);
1048 if (r)
1049 return r;
1050 }
1051 ctx->src[i].sel = treg;
1052 j--;
1053 }
1054 }
1055 return 0;
1056 }
1057
1058 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1059 {
1060 int i, r, count = ctx->shader->ninput;
1061
1062 for (i = 0; i < count; i++) {
1063 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1064 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1065 if (r)
1066 return r;
1067 }
1068 }
1069 return 0;
1070 }
1071
1072 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so)
1073 {
1074 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1075 int i, j, r;
1076
1077 /* Sanity checking. */
1078 if (so->num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1079 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1080 r = -EINVAL;
1081 goto out_err;
1082 }
1083 for (i = 0; i < so->num_outputs; i++) {
1084 if (so->output[i].output_buffer >= 4) {
1085 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1086 so->output[i].output_buffer);
1087 r = -EINVAL;
1088 goto out_err;
1089 }
1090 }
1091
1092 /* Initialize locations where the outputs are stored. */
1093 for (i = 0; i < so->num_outputs; i++) {
1094 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1095
1096 /* Lower outputs with dst_offset < start_component.
1097 *
1098 * We can only output 4D vectors with a write mask, e.g. we can
1099 * only output the W component at offset 3, etc. If we want
1100 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1101 * to move it to X and output X. */
1102 if (so->output[i].dst_offset < so->output[i].start_component) {
1103 unsigned tmp = r600_get_temp(ctx);
1104
1105 for (j = 0; j < so->output[i].num_components; j++) {
1106 struct r600_bytecode_alu alu;
1107 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1108 alu.op = ALU_OP1_MOV;
1109 alu.src[0].sel = so_gpr[i];
1110 alu.src[0].chan = so->output[i].start_component + j;
1111
1112 alu.dst.sel = tmp;
1113 alu.dst.chan = j;
1114 alu.dst.write = 1;
1115 if (j == so->output[i].num_components - 1)
1116 alu.last = 1;
1117 r = r600_bytecode_add_alu(ctx->bc, &alu);
1118 if (r)
1119 return r;
1120 }
1121 so->output[i].start_component = 0;
1122 so_gpr[i] = tmp;
1123 }
1124 }
1125
1126 /* Write outputs to buffers. */
1127 for (i = 0; i < so->num_outputs; i++) {
1128 struct r600_bytecode_output output;
1129
1130 memset(&output, 0, sizeof(struct r600_bytecode_output));
1131 output.gpr = so_gpr[i];
1132 output.elem_size = so->output[i].num_components;
1133 output.array_base = so->output[i].dst_offset - so->output[i].start_component;
1134 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1135 output.burst_count = 1;
1136 /* array_size is an upper limit for the burst_count
1137 * with MEM_STREAM instructions */
1138 output.array_size = 0xFFF;
1139 output.comp_mask = ((1 << so->output[i].num_components) - 1) << so->output[i].start_component;
1140 if (ctx->bc->chip_class >= EVERGREEN) {
1141 switch (so->output[i].output_buffer) {
1142 case 0:
1143 output.op = CF_OP_MEM_STREAM0_BUF0;
1144 break;
1145 case 1:
1146 output.op = CF_OP_MEM_STREAM0_BUF1;
1147 break;
1148 case 2:
1149 output.op = CF_OP_MEM_STREAM0_BUF2;
1150 break;
1151 case 3:
1152 output.op = CF_OP_MEM_STREAM0_BUF3;
1153 break;
1154 }
1155 } else {
1156 switch (so->output[i].output_buffer) {
1157 case 0:
1158 output.op = CF_OP_MEM_STREAM0;
1159 break;
1160 case 1:
1161 output.op = CF_OP_MEM_STREAM1;
1162 break;
1163 case 2:
1164 output.op = CF_OP_MEM_STREAM2;
1165 break;
1166 case 3:
1167 output.op = CF_OP_MEM_STREAM3;
1168 break;
1169 }
1170 }
1171 r = r600_bytecode_add_output(ctx->bc, &output);
1172 if (r)
1173 goto out_err;
1174 }
1175 return 0;
1176 out_err:
1177 return r;
1178 }
1179
1180 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1181 {
1182 struct r600_bytecode_alu alu;
1183 unsigned reg;
1184
1185 if (!ctx->shader->vs_out_edgeflag)
1186 return;
1187
1188 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1189
1190 /* clamp(x, 0, 1) */
1191 memset(&alu, 0, sizeof(alu));
1192 alu.op = ALU_OP1_MOV;
1193 alu.src[0].sel = reg;
1194 alu.dst.sel = reg;
1195 alu.dst.write = 1;
1196 alu.dst.clamp = 1;
1197 alu.last = 1;
1198 r600_bytecode_add_alu(ctx->bc, &alu);
1199
1200 memset(&alu, 0, sizeof(alu));
1201 alu.op = ALU_OP1_FLT_TO_INT;
1202 alu.src[0].sel = reg;
1203 alu.dst.sel = reg;
1204 alu.dst.write = 1;
1205 alu.last = 1;
1206 r600_bytecode_add_alu(ctx->bc, &alu);
1207 }
1208
1209 static int generate_gs_copy_shader(struct r600_context *rctx,
1210 struct r600_pipe_shader *gs,
1211 struct pipe_stream_output_info *so)
1212 {
1213 struct r600_shader_ctx ctx = {};
1214 struct r600_shader *gs_shader = &gs->shader;
1215 struct r600_pipe_shader *cshader;
1216 int ocnt = gs_shader->noutput;
1217 struct r600_bytecode_alu alu;
1218 struct r600_bytecode_vtx vtx;
1219 struct r600_bytecode_output output;
1220 struct r600_bytecode_cf *cf_jump, *cf_pop,
1221 *last_exp_pos = NULL, *last_exp_param = NULL;
1222 int i, next_clip_pos = 61, next_param = 0;
1223
1224 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1225 if (!cshader)
1226 return 0;
1227
1228 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1229 sizeof(struct r600_shader_io));
1230
1231 cshader->shader.noutput = ocnt;
1232
1233 ctx.shader = &cshader->shader;
1234 ctx.bc = &ctx.shader->bc;
1235 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1236
1237 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1238 rctx->screen->has_compressed_msaa_texturing);
1239
1240 ctx.bc->isa = rctx->isa;
1241
1242 /* R0.x = R0.x & 0x3fffffff */
1243 memset(&alu, 0, sizeof(alu));
1244 alu.op = ALU_OP2_AND_INT;
1245 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1246 alu.src[1].value = 0x3fffffff;
1247 alu.dst.write = 1;
1248 r600_bytecode_add_alu(ctx.bc, &alu);
1249
1250 /* R0.y = R0.x >> 30 */
1251 memset(&alu, 0, sizeof(alu));
1252 alu.op = ALU_OP2_LSHR_INT;
1253 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1254 alu.src[1].value = 0x1e;
1255 alu.dst.chan = 1;
1256 alu.dst.write = 1;
1257 alu.last = 1;
1258 r600_bytecode_add_alu(ctx.bc, &alu);
1259
1260 /* PRED_SETE_INT __, R0.y, 0 */
1261 memset(&alu, 0, sizeof(alu));
1262 alu.op = ALU_OP2_PRED_SETE_INT;
1263 alu.src[0].chan = 1;
1264 alu.src[1].sel = V_SQ_ALU_SRC_0;
1265 alu.execute_mask = 1;
1266 alu.update_pred = 1;
1267 alu.last = 1;
1268 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1269
1270 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1271 cf_jump = ctx.bc->cf_last;
1272
1273 /* fetch vertex data from GSVS ring */
1274 for (i = 0; i < ocnt; ++i) {
1275 struct r600_shader_io *out = &ctx.shader->output[i];
1276 out->gpr = i + 1;
1277 out->ring_offset = i * 16;
1278
1279 memset(&vtx, 0, sizeof(vtx));
1280 vtx.op = FETCH_OP_VFETCH;
1281 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1282 vtx.fetch_type = 2;
1283 vtx.offset = out->ring_offset;
1284 vtx.dst_gpr = out->gpr;
1285 vtx.dst_sel_x = 0;
1286 vtx.dst_sel_y = 1;
1287 vtx.dst_sel_z = 2;
1288 vtx.dst_sel_w = 3;
1289 if (rctx->b.chip_class >= EVERGREEN) {
1290 vtx.use_const_fields = 1;
1291 } else {
1292 vtx.data_format = FMT_32_32_32_32_FLOAT;
1293 }
1294
1295 r600_bytecode_add_vtx(ctx.bc, &vtx);
1296 }
1297
1298 /* XXX handle clipvertex, streamout? */
1299 emit_streamout(&ctx, so);
1300
1301 /* export vertex data */
1302 /* XXX factor out common code with r600_shader_from_tgsi ? */
1303 for (i = 0; i < ocnt; ++i) {
1304 struct r600_shader_io *out = &ctx.shader->output[i];
1305
1306 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1307 continue;
1308
1309 memset(&output, 0, sizeof(output));
1310 output.gpr = out->gpr;
1311 output.elem_size = 3;
1312 output.swizzle_x = 0;
1313 output.swizzle_y = 1;
1314 output.swizzle_z = 2;
1315 output.swizzle_w = 3;
1316 output.burst_count = 1;
1317 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1318 output.op = CF_OP_EXPORT;
1319 switch (out->name) {
1320 case TGSI_SEMANTIC_POSITION:
1321 output.array_base = 60;
1322 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1323 break;
1324
1325 case TGSI_SEMANTIC_PSIZE:
1326 output.array_base = 61;
1327 if (next_clip_pos == 61)
1328 next_clip_pos = 62;
1329 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1330 output.swizzle_y = 7;
1331 output.swizzle_z = 7;
1332 output.swizzle_w = 7;
1333 ctx.shader->vs_out_misc_write = 1;
1334 ctx.shader->vs_out_point_size = 1;
1335 break;
1336 case TGSI_SEMANTIC_LAYER:
1337 if (out->spi_sid) {
1338 /* duplicate it as PARAM to pass to the pixel shader */
1339 output.array_base = next_param++;
1340 r600_bytecode_add_output(ctx.bc, &output);
1341 last_exp_param = ctx.bc->cf_last;
1342 }
1343 output.array_base = 61;
1344 if (next_clip_pos == 61)
1345 next_clip_pos = 62;
1346 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1347 output.swizzle_x = 7;
1348 output.swizzle_y = 7;
1349 output.swizzle_z = 0;
1350 output.swizzle_w = 7;
1351 ctx.shader->vs_out_misc_write = 1;
1352 ctx.shader->vs_out_layer = 1;
1353 break;
1354 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1355 if (out->spi_sid) {
1356 /* duplicate it as PARAM to pass to the pixel shader */
1357 output.array_base = next_param++;
1358 r600_bytecode_add_output(ctx.bc, &output);
1359 last_exp_param = ctx.bc->cf_last;
1360 }
1361 output.array_base = 61;
1362 if (next_clip_pos == 61)
1363 next_clip_pos = 62;
1364 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1365 ctx.shader->vs_out_misc_write = 1;
1366 ctx.shader->vs_out_viewport = 1;
1367 output.swizzle_x = 7;
1368 output.swizzle_y = 7;
1369 output.swizzle_z = 7;
1370 output.swizzle_w = 0;
1371 break;
1372 case TGSI_SEMANTIC_CLIPDIST:
1373 /* spi_sid is 0 for clipdistance outputs that were generated
1374 * for clipvertex - we don't need to pass them to PS */
1375 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1376 if (out->spi_sid) {
1377 /* duplicate it as PARAM to pass to the pixel shader */
1378 output.array_base = next_param++;
1379 r600_bytecode_add_output(ctx.bc, &output);
1380 last_exp_param = ctx.bc->cf_last;
1381 }
1382 output.array_base = next_clip_pos++;
1383 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1384 break;
1385 case TGSI_SEMANTIC_FOG:
1386 output.swizzle_y = 4; /* 0 */
1387 output.swizzle_z = 4; /* 0 */
1388 output.swizzle_w = 5; /* 1 */
1389 break;
1390 default:
1391 output.array_base = next_param++;
1392 break;
1393 }
1394 r600_bytecode_add_output(ctx.bc, &output);
1395 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1396 last_exp_param = ctx.bc->cf_last;
1397 else
1398 last_exp_pos = ctx.bc->cf_last;
1399 }
1400
1401 if (!last_exp_pos) {
1402 memset(&output, 0, sizeof(output));
1403 output.gpr = 0;
1404 output.elem_size = 3;
1405 output.swizzle_x = 7;
1406 output.swizzle_y = 7;
1407 output.swizzle_z = 7;
1408 output.swizzle_w = 7;
1409 output.burst_count = 1;
1410 output.type = 2;
1411 output.op = CF_OP_EXPORT;
1412 output.array_base = 60;
1413 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1414 r600_bytecode_add_output(ctx.bc, &output);
1415 last_exp_pos = ctx.bc->cf_last;
1416 }
1417
1418 if (!last_exp_param) {
1419 memset(&output, 0, sizeof(output));
1420 output.gpr = 0;
1421 output.elem_size = 3;
1422 output.swizzle_x = 7;
1423 output.swizzle_y = 7;
1424 output.swizzle_z = 7;
1425 output.swizzle_w = 7;
1426 output.burst_count = 1;
1427 output.type = 2;
1428 output.op = CF_OP_EXPORT;
1429 output.array_base = next_param++;
1430 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1431 r600_bytecode_add_output(ctx.bc, &output);
1432 last_exp_param = ctx.bc->cf_last;
1433 }
1434
1435 last_exp_pos->op = CF_OP_EXPORT_DONE;
1436 last_exp_param->op = CF_OP_EXPORT_DONE;
1437
1438 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1439 cf_pop = ctx.bc->cf_last;
1440
1441 cf_jump->cf_addr = cf_pop->id + 2;
1442 cf_jump->pop_count = 1;
1443 cf_pop->cf_addr = cf_pop->id + 2;
1444 cf_pop->pop_count = 1;
1445
1446 if (ctx.bc->chip_class == CAYMAN)
1447 cm_bytecode_add_cf_end(ctx.bc);
1448 else {
1449 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1450 ctx.bc->cf_last->end_of_program = 1;
1451 }
1452
1453 gs->gs_copy_shader = cshader;
1454
1455 ctx.bc->nstack = 1;
1456 cshader->shader.ring_item_size = ocnt * 16;
1457
1458 return r600_bytecode_build(ctx.bc);
1459 }
1460
1461 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind)
1462 {
1463 struct r600_bytecode_output output;
1464 int i, k, ring_offset;
1465
1466 for (i = 0; i < ctx->shader->noutput; i++) {
1467 if (ctx->gs_for_vs) {
1468 /* for ES we need to lookup corresponding ring offset expected by GS
1469 * (map this output to GS input by name and sid) */
1470 /* FIXME precompute offsets */
1471 ring_offset = -1;
1472 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1473 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1474 struct r600_shader_io *out = &ctx->shader->output[i];
1475 if (in->name == out->name && in->sid == out->sid)
1476 ring_offset = in->ring_offset;
1477 }
1478
1479 if (ring_offset == -1)
1480 continue;
1481 } else
1482 ring_offset = i * 16;
1483
1484 /* next_ring_offset after parsing input decls contains total size of
1485 * single vertex data, gs_next_vertex - current vertex index */
1486 if (!ind)
1487 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1488
1489 /* get a temp and add the ring offset to the next vertex base in the shader */
1490 memset(&output, 0, sizeof(struct r600_bytecode_output));
1491 output.gpr = ctx->shader->output[i].gpr;
1492 output.elem_size = 3;
1493 output.comp_mask = 0xF;
1494 output.burst_count = 1;
1495
1496 if (ind)
1497 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1498 else
1499 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1500 output.op = CF_OP_MEM_RING;
1501
1502
1503 if (ind) {
1504 output.array_base = ring_offset >> 2; /* in dwords */
1505 output.array_size = 0xfff;
1506 output.index_gpr = ctx->gs_export_gpr_treg;
1507 } else
1508 output.array_base = ring_offset >> 2; /* in dwords */
1509 r600_bytecode_add_output(ctx->bc, &output);
1510 }
1511
1512 if (ind) {
1513 struct r600_bytecode_alu alu;
1514 int r;
1515
1516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1517 alu.op = ALU_OP2_ADD_INT;
1518 alu.src[0].sel = ctx->gs_export_gpr_treg;
1519 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1520 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1521 alu.dst.sel = ctx->gs_export_gpr_treg;
1522 alu.dst.write = 1;
1523 alu.last = 1;
1524 r = r600_bytecode_add_alu(ctx->bc, &alu);
1525 if (r)
1526 return r;
1527 }
1528 ++ctx->gs_next_vertex;
1529 return 0;
1530 }
1531
1532 static int r600_shader_from_tgsi(struct r600_context *rctx,
1533 struct r600_pipe_shader *pipeshader,
1534 struct r600_shader_key key)
1535 {
1536 struct r600_screen *rscreen = rctx->screen;
1537 struct r600_shader *shader = &pipeshader->shader;
1538 struct tgsi_token *tokens = pipeshader->selector->tokens;
1539 struct pipe_stream_output_info so = pipeshader->selector->so;
1540 struct tgsi_full_immediate *immediate;
1541 struct tgsi_full_property *property;
1542 struct r600_shader_ctx ctx;
1543 struct r600_bytecode_output output[32];
1544 unsigned output_done, noutput;
1545 unsigned opcode;
1546 int i, j, k, r = 0;
1547 int next_param_base = 0, next_clip_base;
1548 int max_color_exports = MAX2(key.nr_cbufs, 1);
1549 /* Declarations used by llvm code */
1550 bool use_llvm = false;
1551 bool indirect_gprs;
1552 bool ring_outputs = false;
1553 bool pos_emitted = false;
1554
1555 #ifdef R600_USE_LLVM
1556 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
1557 #endif
1558 ctx.bc = &shader->bc;
1559 ctx.shader = shader;
1560 ctx.native_integers = true;
1561
1562 shader->vs_as_es = key.vs_as_es;
1563
1564 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1565 rscreen->has_compressed_msaa_texturing);
1566 ctx.tokens = tokens;
1567 tgsi_scan_shader(tokens, &ctx.info);
1568 shader->indirect_files = ctx.info.indirect_files;
1569 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
1570 tgsi_parse_init(&ctx.parse, tokens);
1571 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1572 shader->processor_type = ctx.type;
1573 ctx.bc->type = shader->processor_type;
1574
1575 ring_outputs = key.vs_as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
1576
1577 if (key.vs_as_es) {
1578 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1579 } else {
1580 ctx.gs_for_vs = NULL;
1581 }
1582
1583 ctx.next_ring_offset = 0;
1584 ctx.gs_out_ring_offset = 0;
1585 ctx.gs_next_vertex = 0;
1586
1587 ctx.face_gpr = -1;
1588 ctx.fragcoord_input = -1;
1589 ctx.colors_used = 0;
1590 ctx.clip_vertex_write = 0;
1591
1592 shader->nr_ps_color_exports = 0;
1593 shader->nr_ps_max_color_exports = 0;
1594
1595 shader->two_side = key.color_two_side;
1596
1597 /* register allocations */
1598 /* Values [0,127] correspond to GPR[0..127].
1599 * Values [128,159] correspond to constant buffer bank 0
1600 * Values [160,191] correspond to constant buffer bank 1
1601 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1602 * Values [256,287] correspond to constant buffer bank 2 (EG)
1603 * Values [288,319] correspond to constant buffer bank 3 (EG)
1604 * Other special values are shown in the list below.
1605 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1606 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1607 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1608 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1609 * 248 SQ_ALU_SRC_0: special constant 0.0.
1610 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1611 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1612 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1613 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1614 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1615 * 254 SQ_ALU_SRC_PV: previous vector result.
1616 * 255 SQ_ALU_SRC_PS: previous scalar result.
1617 */
1618 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1619 ctx.file_offset[i] = 0;
1620 }
1621
1622 #ifdef R600_USE_LLVM
1623 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1624 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1625 "indirect adressing. Falling back to TGSI "
1626 "backend.\n");
1627 use_llvm = 0;
1628 }
1629 #endif
1630 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1631 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1632 if (!use_llvm) {
1633 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1634 }
1635 }
1636 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1637 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1638 }
1639 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1640 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1641 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1642 }
1643 ctx.use_llvm = use_llvm;
1644
1645 if (use_llvm) {
1646 ctx.file_offset[TGSI_FILE_OUTPUT] =
1647 ctx.file_offset[TGSI_FILE_INPUT];
1648 } else {
1649 ctx.file_offset[TGSI_FILE_OUTPUT] =
1650 ctx.file_offset[TGSI_FILE_INPUT] +
1651 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1652 }
1653 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1654 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1655
1656 /* Outside the GPR range. This will be translated to one of the
1657 * kcache banks later. */
1658 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1659
1660 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1661 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1662 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1663 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1664 ctx.gs_export_gpr_treg = ctx.bc->ar_reg + 1;
1665 ctx.temp_reg = ctx.bc->ar_reg + 2;
1666 } else
1667 ctx.temp_reg = ctx.bc->ar_reg + 1;
1668
1669 if (indirect_gprs) {
1670 shader->max_arrays = 0;
1671 shader->num_arrays = 0;
1672
1673 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1674 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1675 ctx.file_offset[TGSI_FILE_OUTPUT] -
1676 ctx.file_offset[TGSI_FILE_INPUT],
1677 0x0F);
1678 }
1679 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1680 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1681 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1682 ctx.file_offset[TGSI_FILE_OUTPUT],
1683 0x0F);
1684 }
1685 }
1686
1687 ctx.nliterals = 0;
1688 ctx.literals = NULL;
1689 shader->fs_write_all = FALSE;
1690 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1691 tgsi_parse_token(&ctx.parse);
1692 switch (ctx.parse.FullToken.Token.Type) {
1693 case TGSI_TOKEN_TYPE_IMMEDIATE:
1694 immediate = &ctx.parse.FullToken.FullImmediate;
1695 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1696 if(ctx.literals == NULL) {
1697 r = -ENOMEM;
1698 goto out_err;
1699 }
1700 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1701 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1702 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1703 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1704 ctx.nliterals++;
1705 break;
1706 case TGSI_TOKEN_TYPE_DECLARATION:
1707 r = tgsi_declaration(&ctx);
1708 if (r)
1709 goto out_err;
1710 break;
1711 case TGSI_TOKEN_TYPE_INSTRUCTION:
1712 break;
1713 case TGSI_TOKEN_TYPE_PROPERTY:
1714 property = &ctx.parse.FullToken.FullProperty;
1715 switch (property->Property.PropertyName) {
1716 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1717 if (property->u[0].Data == 1)
1718 shader->fs_write_all = TRUE;
1719 break;
1720 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
1721 if (property->u[0].Data == 1)
1722 shader->vs_position_window_space = TRUE;
1723 break;
1724 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1725 /* we don't need this one */
1726 break;
1727 case TGSI_PROPERTY_GS_INPUT_PRIM:
1728 shader->gs_input_prim = property->u[0].Data;
1729 break;
1730 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1731 shader->gs_output_prim = property->u[0].Data;
1732 break;
1733 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1734 shader->gs_max_out_vertices = property->u[0].Data;
1735 break;
1736 }
1737 break;
1738 default:
1739 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1740 r = -EINVAL;
1741 goto out_err;
1742 }
1743 }
1744
1745 shader->ring_item_size = ctx.next_ring_offset;
1746
1747 /* Process two side if needed */
1748 if (shader->two_side && ctx.colors_used) {
1749 int i, count = ctx.shader->ninput;
1750 unsigned next_lds_loc = ctx.shader->nlds;
1751
1752 /* additional inputs will be allocated right after the existing inputs,
1753 * we won't need them after the color selection, so we don't need to
1754 * reserve these gprs for the rest of the shader code and to adjust
1755 * output offsets etc. */
1756 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1757 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1758
1759 if (ctx.face_gpr == -1) {
1760 i = ctx.shader->ninput++;
1761 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1762 ctx.shader->input[i].spi_sid = 0;
1763 ctx.shader->input[i].gpr = gpr++;
1764 ctx.face_gpr = ctx.shader->input[i].gpr;
1765 }
1766
1767 for (i = 0; i < count; i++) {
1768 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1769 int ni = ctx.shader->ninput++;
1770 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1771 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1772 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1773 ctx.shader->input[ni].gpr = gpr++;
1774 // TGSI to LLVM needs to know the lds position of inputs.
1775 // Non LLVM path computes it later (in process_twoside_color)
1776 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1777 ctx.shader->input[i].back_color_input = ni;
1778 if (ctx.bc->chip_class >= EVERGREEN) {
1779 if ((r = evergreen_interp_input(&ctx, ni)))
1780 return r;
1781 }
1782 }
1783 }
1784 }
1785
1786 /* LLVM backend setup */
1787 #ifdef R600_USE_LLVM
1788 if (use_llvm) {
1789 struct radeon_llvm_context radeon_llvm_ctx;
1790 LLVMModuleRef mod;
1791 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
1792 boolean use_kill = false;
1793
1794 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1795 radeon_llvm_ctx.type = ctx.type;
1796 radeon_llvm_ctx.two_side = shader->two_side;
1797 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1798 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
1799 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1800 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1801 radeon_llvm_ctx.color_buffer_count = max_color_exports;
1802 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1803 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
1804 radeon_llvm_ctx.stream_outputs = &so;
1805 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1806 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1807 radeon_llvm_ctx.has_compressed_msaa_texturing =
1808 ctx.bc->has_compressed_msaa_texturing;
1809 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1810 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1811 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
1812
1813 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
1814 radeon_llvm_dispose(&radeon_llvm_ctx);
1815 use_llvm = 0;
1816 fprintf(stderr, "R600 LLVM backend failed to compile "
1817 "shader. Falling back to TGSI\n");
1818 } else {
1819 ctx.file_offset[TGSI_FILE_OUTPUT] =
1820 ctx.file_offset[TGSI_FILE_INPUT];
1821 }
1822 if (use_kill)
1823 ctx.shader->uses_kill = use_kill;
1824 radeon_llvm_dispose(&radeon_llvm_ctx);
1825 }
1826 #endif
1827 /* End of LLVM backend setup */
1828
1829 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
1830 shader->nr_ps_max_color_exports = 8;
1831
1832 if (!use_llvm) {
1833 if (ctx.fragcoord_input >= 0) {
1834 if (ctx.bc->chip_class == CAYMAN) {
1835 for (j = 0 ; j < 4; j++) {
1836 struct r600_bytecode_alu alu;
1837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1838 alu.op = ALU_OP1_RECIP_IEEE;
1839 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1840 alu.src[0].chan = 3;
1841
1842 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1843 alu.dst.chan = j;
1844 alu.dst.write = (j == 3);
1845 alu.last = 1;
1846 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1847 return r;
1848 }
1849 } else {
1850 struct r600_bytecode_alu alu;
1851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1852 alu.op = ALU_OP1_RECIP_IEEE;
1853 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1854 alu.src[0].chan = 3;
1855
1856 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1857 alu.dst.chan = 3;
1858 alu.dst.write = 1;
1859 alu.last = 1;
1860 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1861 return r;
1862 }
1863 }
1864
1865 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1866 struct r600_bytecode_alu alu;
1867 int r;
1868
1869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1870 alu.op = ALU_OP1_MOV;
1871 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1872 alu.src[0].value = 0;
1873 alu.dst.sel = ctx.gs_export_gpr_treg;
1874 alu.dst.write = 1;
1875 alu.last = 1;
1876 r = r600_bytecode_add_alu(ctx.bc, &alu);
1877 if (r)
1878 return r;
1879 }
1880 if (shader->two_side && ctx.colors_used) {
1881 if ((r = process_twoside_color_inputs(&ctx)))
1882 return r;
1883 }
1884
1885 tgsi_parse_init(&ctx.parse, tokens);
1886 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1887 tgsi_parse_token(&ctx.parse);
1888 switch (ctx.parse.FullToken.Token.Type) {
1889 case TGSI_TOKEN_TYPE_INSTRUCTION:
1890 r = tgsi_is_supported(&ctx);
1891 if (r)
1892 goto out_err;
1893 ctx.max_driver_temp_used = 0;
1894 /* reserve first tmp for everyone */
1895 r600_get_temp(&ctx);
1896
1897 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1898 if ((r = tgsi_split_constant(&ctx)))
1899 goto out_err;
1900 if ((r = tgsi_split_literal_constant(&ctx)))
1901 goto out_err;
1902 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
1903 if ((r = tgsi_split_gs_inputs(&ctx)))
1904 goto out_err;
1905 if (ctx.bc->chip_class == CAYMAN)
1906 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1907 else if (ctx.bc->chip_class >= EVERGREEN)
1908 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1909 else
1910 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1911 r = ctx.inst_info->process(&ctx);
1912 if (r)
1913 goto out_err;
1914 break;
1915 default:
1916 break;
1917 }
1918 }
1919 }
1920
1921 /* Reset the temporary register counter. */
1922 ctx.max_driver_temp_used = 0;
1923
1924 noutput = shader->noutput;
1925
1926 if (!ring_outputs && ctx.clip_vertex_write) {
1927 unsigned clipdist_temp[2];
1928
1929 clipdist_temp[0] = r600_get_temp(&ctx);
1930 clipdist_temp[1] = r600_get_temp(&ctx);
1931
1932 /* need to convert a clipvertex write into clipdistance writes and not export
1933 the clip vertex anymore */
1934
1935 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1936 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1937 shader->output[noutput].gpr = clipdist_temp[0];
1938 noutput++;
1939 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1940 shader->output[noutput].gpr = clipdist_temp[1];
1941 noutput++;
1942
1943 /* reset spi_sid for clipvertex output to avoid confusing spi */
1944 shader->output[ctx.cv_output].spi_sid = 0;
1945
1946 shader->clip_dist_write = 0xFF;
1947
1948 for (i = 0; i < 8; i++) {
1949 int oreg = i >> 2;
1950 int ochan = i & 3;
1951
1952 for (j = 0; j < 4; j++) {
1953 struct r600_bytecode_alu alu;
1954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1955 alu.op = ALU_OP2_DOT4;
1956 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1957 alu.src[0].chan = j;
1958
1959 alu.src[1].sel = 512 + i;
1960 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1961 alu.src[1].chan = j;
1962
1963 alu.dst.sel = clipdist_temp[oreg];
1964 alu.dst.chan = j;
1965 alu.dst.write = (j == ochan);
1966 if (j == 3)
1967 alu.last = 1;
1968 if (!use_llvm)
1969 r = r600_bytecode_add_alu(ctx.bc, &alu);
1970 if (r)
1971 return r;
1972 }
1973 }
1974 }
1975
1976 /* Add stream outputs. */
1977 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
1978 so.num_outputs && !use_llvm)
1979 emit_streamout(&ctx, &so);
1980
1981 convert_edgeflag_to_int(&ctx);
1982
1983 if (ring_outputs) {
1984 if (key.vs_as_es)
1985 emit_gs_ring_writes(&ctx, FALSE);
1986 } else {
1987 /* Export output */
1988 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
1989
1990 for (i = 0, j = 0; i < noutput; i++, j++) {
1991 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1992 output[j].gpr = shader->output[i].gpr;
1993 output[j].elem_size = 3;
1994 output[j].swizzle_x = 0;
1995 output[j].swizzle_y = 1;
1996 output[j].swizzle_z = 2;
1997 output[j].swizzle_w = 3;
1998 output[j].burst_count = 1;
1999 output[j].type = -1;
2000 output[j].op = CF_OP_EXPORT;
2001 switch (ctx.type) {
2002 case TGSI_PROCESSOR_VERTEX:
2003 switch (shader->output[i].name) {
2004 case TGSI_SEMANTIC_POSITION:
2005 output[j].array_base = 60;
2006 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2007 pos_emitted = true;
2008 break;
2009
2010 case TGSI_SEMANTIC_PSIZE:
2011 output[j].array_base = 61;
2012 output[j].swizzle_y = 7;
2013 output[j].swizzle_z = 7;
2014 output[j].swizzle_w = 7;
2015 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2016 pos_emitted = true;
2017 break;
2018 case TGSI_SEMANTIC_EDGEFLAG:
2019 output[j].array_base = 61;
2020 output[j].swizzle_x = 7;
2021 output[j].swizzle_y = 0;
2022 output[j].swizzle_z = 7;
2023 output[j].swizzle_w = 7;
2024 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2025 pos_emitted = true;
2026 break;
2027 case TGSI_SEMANTIC_LAYER:
2028 /* spi_sid is 0 for outputs that are
2029 * not consumed by PS */
2030 if (shader->output[i].spi_sid) {
2031 output[j].array_base = next_param_base++;
2032 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2033 j++;
2034 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2035 }
2036 output[j].array_base = 61;
2037 output[j].swizzle_x = 7;
2038 output[j].swizzle_y = 7;
2039 output[j].swizzle_z = 0;
2040 output[j].swizzle_w = 7;
2041 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2042 pos_emitted = true;
2043 break;
2044 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2045 /* spi_sid is 0 for outputs that are
2046 * not consumed by PS */
2047 if (shader->output[i].spi_sid) {
2048 output[j].array_base = next_param_base++;
2049 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2050 j++;
2051 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2052 }
2053 output[j].array_base = 61;
2054 output[j].swizzle_x = 7;
2055 output[j].swizzle_y = 7;
2056 output[j].swizzle_z = 7;
2057 output[j].swizzle_w = 0;
2058 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2059 pos_emitted = true;
2060 break;
2061 case TGSI_SEMANTIC_CLIPVERTEX:
2062 j--;
2063 break;
2064 case TGSI_SEMANTIC_CLIPDIST:
2065 output[j].array_base = next_clip_base++;
2066 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2067 pos_emitted = true;
2068 /* spi_sid is 0 for clipdistance outputs that were generated
2069 * for clipvertex - we don't need to pass them to PS */
2070 if (shader->output[i].spi_sid) {
2071 j++;
2072 /* duplicate it as PARAM to pass to the pixel shader */
2073 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2074 output[j].array_base = next_param_base++;
2075 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2076 }
2077 break;
2078 case TGSI_SEMANTIC_FOG:
2079 output[j].swizzle_y = 4; /* 0 */
2080 output[j].swizzle_z = 4; /* 0 */
2081 output[j].swizzle_w = 5; /* 1 */
2082 break;
2083 }
2084 break;
2085 case TGSI_PROCESSOR_FRAGMENT:
2086 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2087 /* never export more colors than the number of CBs */
2088 if (shader->output[i].sid >= max_color_exports) {
2089 /* skip export */
2090 j--;
2091 continue;
2092 }
2093 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
2094 output[j].array_base = shader->output[i].sid;
2095 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2096 shader->nr_ps_color_exports++;
2097 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2098 for (k = 1; k < max_color_exports; k++) {
2099 j++;
2100 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2101 output[j].gpr = shader->output[i].gpr;
2102 output[j].elem_size = 3;
2103 output[j].swizzle_x = 0;
2104 output[j].swizzle_y = 1;
2105 output[j].swizzle_z = 2;
2106 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
2107 output[j].burst_count = 1;
2108 output[j].array_base = k;
2109 output[j].op = CF_OP_EXPORT;
2110 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2111 shader->nr_ps_color_exports++;
2112 }
2113 }
2114 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2115 output[j].array_base = 61;
2116 output[j].swizzle_x = 2;
2117 output[j].swizzle_y = 7;
2118 output[j].swizzle_z = output[j].swizzle_w = 7;
2119 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2120 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2121 output[j].array_base = 61;
2122 output[j].swizzle_x = 7;
2123 output[j].swizzle_y = 1;
2124 output[j].swizzle_z = output[j].swizzle_w = 7;
2125 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2126 } else {
2127 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2128 r = -EINVAL;
2129 goto out_err;
2130 }
2131 break;
2132 default:
2133 R600_ERR("unsupported processor type %d\n", ctx.type);
2134 r = -EINVAL;
2135 goto out_err;
2136 }
2137
2138 if (output[j].type==-1) {
2139 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2140 output[j].array_base = next_param_base++;
2141 }
2142 }
2143
2144 /* add fake position export */
2145 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2146 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2147 output[j].gpr = 0;
2148 output[j].elem_size = 3;
2149 output[j].swizzle_x = 7;
2150 output[j].swizzle_y = 7;
2151 output[j].swizzle_z = 7;
2152 output[j].swizzle_w = 7;
2153 output[j].burst_count = 1;
2154 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2155 output[j].array_base = 60;
2156 output[j].op = CF_OP_EXPORT;
2157 j++;
2158 }
2159
2160 /* add fake param output for vertex shader if no param is exported */
2161 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2162 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2163 output[j].gpr = 0;
2164 output[j].elem_size = 3;
2165 output[j].swizzle_x = 7;
2166 output[j].swizzle_y = 7;
2167 output[j].swizzle_z = 7;
2168 output[j].swizzle_w = 7;
2169 output[j].burst_count = 1;
2170 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2171 output[j].array_base = 0;
2172 output[j].op = CF_OP_EXPORT;
2173 j++;
2174 }
2175
2176 /* add fake pixel export */
2177 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2178 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2179 output[j].gpr = 0;
2180 output[j].elem_size = 3;
2181 output[j].swizzle_x = 7;
2182 output[j].swizzle_y = 7;
2183 output[j].swizzle_z = 7;
2184 output[j].swizzle_w = 7;
2185 output[j].burst_count = 1;
2186 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2187 output[j].array_base = 0;
2188 output[j].op = CF_OP_EXPORT;
2189 j++;
2190 }
2191
2192 noutput = j;
2193
2194 /* set export done on last export of each type */
2195 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2196 if (!(output_done & (1 << output[i].type))) {
2197 output_done |= (1 << output[i].type);
2198 output[i].op = CF_OP_EXPORT_DONE;
2199 }
2200 }
2201 /* add output to bytecode */
2202 if (!use_llvm) {
2203 for (i = 0; i < noutput; i++) {
2204 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2205 if (r)
2206 goto out_err;
2207 }
2208 }
2209 }
2210
2211 /* add program end */
2212 if (!use_llvm) {
2213 if (ctx.bc->chip_class == CAYMAN)
2214 cm_bytecode_add_cf_end(ctx.bc);
2215 else {
2216 const struct cf_op_info *last = NULL;
2217
2218 if (ctx.bc->cf_last)
2219 last = r600_isa_cf(ctx.bc->cf_last->op);
2220
2221 /* alu clause instructions don't have EOP bit, so add NOP */
2222 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2223 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2224
2225 ctx.bc->cf_last->end_of_program = 1;
2226 }
2227 }
2228
2229 /* check GPR limit - we have 124 = 128 - 4
2230 * (4 are reserved as alu clause temporary registers) */
2231 if (ctx.bc->ngpr > 124) {
2232 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2233 r = -ENOMEM;
2234 goto out_err;
2235 }
2236
2237 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2238 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2239 return r;
2240 }
2241
2242 free(ctx.literals);
2243 tgsi_parse_free(&ctx.parse);
2244 return 0;
2245 out_err:
2246 free(ctx.literals);
2247 tgsi_parse_free(&ctx.parse);
2248 return r;
2249 }
2250
2251 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2252 {
2253 R600_ERR("%s tgsi opcode unsupported\n",
2254 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
2255 return -EINVAL;
2256 }
2257
2258 static int tgsi_end(struct r600_shader_ctx *ctx)
2259 {
2260 return 0;
2261 }
2262
2263 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2264 const struct r600_shader_src *shader_src,
2265 unsigned chan)
2266 {
2267 bc_src->sel = shader_src->sel;
2268 bc_src->chan = shader_src->swizzle[chan];
2269 bc_src->neg = shader_src->neg;
2270 bc_src->abs = shader_src->abs;
2271 bc_src->rel = shader_src->rel;
2272 bc_src->value = shader_src->value[bc_src->chan];
2273 bc_src->kc_bank = shader_src->kc_bank;
2274 }
2275
2276 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2277 {
2278 bc_src->abs = 1;
2279 bc_src->neg = 0;
2280 }
2281
2282 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2283 {
2284 bc_src->neg = !bc_src->neg;
2285 }
2286
2287 static void tgsi_dst(struct r600_shader_ctx *ctx,
2288 const struct tgsi_full_dst_register *tgsi_dst,
2289 unsigned swizzle,
2290 struct r600_bytecode_alu_dst *r600_dst)
2291 {
2292 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2293
2294 r600_dst->sel = tgsi_dst->Register.Index;
2295 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2296 r600_dst->chan = swizzle;
2297 r600_dst->write = 1;
2298 if (tgsi_dst->Register.Indirect)
2299 r600_dst->rel = V_SQ_REL_RELATIVE;
2300 if (inst->Instruction.Saturate) {
2301 r600_dst->clamp = 1;
2302 }
2303 }
2304
2305 static int tgsi_last_instruction(unsigned writemask)
2306 {
2307 int i, lasti = 0;
2308
2309 for (i = 0; i < 4; i++) {
2310 if (writemask & (1 << i)) {
2311 lasti = i;
2312 }
2313 }
2314 return lasti;
2315 }
2316
2317 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2318 {
2319 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2320 struct r600_bytecode_alu alu;
2321 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2322 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2323 /* use temp register if trans_only and more than one dst component */
2324 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2325
2326 for (i = 0; i <= lasti; i++) {
2327 if (!(write_mask & (1 << i)))
2328 continue;
2329
2330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2331 if (use_tmp) {
2332 alu.dst.sel = ctx->temp_reg;
2333 alu.dst.chan = i;
2334 alu.dst.write = 1;
2335 } else
2336 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2337
2338 alu.op = ctx->inst_info->op;
2339 if (!swap) {
2340 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2341 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2342 }
2343 } else {
2344 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2345 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2346 }
2347 /* handle some special cases */
2348 switch (ctx->inst_info->tgsi_opcode) {
2349 case TGSI_OPCODE_SUB:
2350 r600_bytecode_src_toggle_neg(&alu.src[1]);
2351 break;
2352 case TGSI_OPCODE_ABS:
2353 r600_bytecode_src_set_abs(&alu.src[0]);
2354 break;
2355 default:
2356 break;
2357 }
2358 if (i == lasti || trans_only) {
2359 alu.last = 1;
2360 }
2361 r = r600_bytecode_add_alu(ctx->bc, &alu);
2362 if (r)
2363 return r;
2364 }
2365
2366 if (use_tmp) {
2367 /* move result from temp to dst */
2368 for (i = 0; i <= lasti; i++) {
2369 if (!(write_mask & (1 << i)))
2370 continue;
2371
2372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2373 alu.op = ALU_OP1_MOV;
2374 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2375 alu.src[0].sel = ctx->temp_reg;
2376 alu.src[0].chan = i;
2377 alu.last = (i == lasti);
2378
2379 r = r600_bytecode_add_alu(ctx->bc, &alu);
2380 if (r)
2381 return r;
2382 }
2383 }
2384 return 0;
2385 }
2386
2387 static int tgsi_op2(struct r600_shader_ctx *ctx)
2388 {
2389 return tgsi_op2_s(ctx, 0, 0);
2390 }
2391
2392 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2393 {
2394 return tgsi_op2_s(ctx, 1, 0);
2395 }
2396
2397 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2398 {
2399 return tgsi_op2_s(ctx, 0, 1);
2400 }
2401
2402 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2403 {
2404 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2405 struct r600_bytecode_alu alu;
2406 int i, r;
2407 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2408
2409 for (i = 0; i < lasti + 1; i++) {
2410
2411 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2412 continue;
2413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2414 alu.op = ctx->inst_info->op;
2415
2416 alu.src[0].sel = V_SQ_ALU_SRC_0;
2417
2418 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2419
2420 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2421
2422 if (i == lasti) {
2423 alu.last = 1;
2424 }
2425 r = r600_bytecode_add_alu(ctx->bc, &alu);
2426 if (r)
2427 return r;
2428 }
2429 return 0;
2430
2431 }
2432
2433 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2434 {
2435 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2436 int i, j, r;
2437 struct r600_bytecode_alu alu;
2438 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2439
2440 for (i = 0 ; i < last_slot; i++) {
2441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2442 alu.op = ctx->inst_info->op;
2443 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2444 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2445
2446 /* RSQ should take the absolute value of src */
2447 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
2448 r600_bytecode_src_set_abs(&alu.src[j]);
2449 }
2450 }
2451 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2452 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2453
2454 if (i == last_slot - 1)
2455 alu.last = 1;
2456 r = r600_bytecode_add_alu(ctx->bc, &alu);
2457 if (r)
2458 return r;
2459 }
2460 return 0;
2461 }
2462
2463 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2464 {
2465 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2466 int i, j, k, r;
2467 struct r600_bytecode_alu alu;
2468 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2469 for (k = 0; k < last_slot; k++) {
2470 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2471 continue;
2472
2473 for (i = 0 ; i < 4; i++) {
2474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2475 alu.op = ctx->inst_info->op;
2476 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2477 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2478 }
2479 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2480 alu.dst.write = (i == k);
2481 if (i == 3)
2482 alu.last = 1;
2483 r = r600_bytecode_add_alu(ctx->bc, &alu);
2484 if (r)
2485 return r;
2486 }
2487 }
2488 return 0;
2489 }
2490
2491 /*
2492 * r600 - trunc to -PI..PI range
2493 * r700 - normalize by dividing by 2PI
2494 * see fdo bug 27901
2495 */
2496 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2497 {
2498 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2499 static float double_pi = 3.1415926535 * 2;
2500 static float neg_pi = -3.1415926535;
2501
2502 int r;
2503 struct r600_bytecode_alu alu;
2504
2505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2506 alu.op = ALU_OP3_MULADD;
2507 alu.is_op3 = 1;
2508
2509 alu.dst.chan = 0;
2510 alu.dst.sel = ctx->temp_reg;
2511 alu.dst.write = 1;
2512
2513 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2514
2515 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2516 alu.src[1].chan = 0;
2517 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2518 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2519 alu.src[2].chan = 0;
2520 alu.last = 1;
2521 r = r600_bytecode_add_alu(ctx->bc, &alu);
2522 if (r)
2523 return r;
2524
2525 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2526 alu.op = ALU_OP1_FRACT;
2527
2528 alu.dst.chan = 0;
2529 alu.dst.sel = ctx->temp_reg;
2530 alu.dst.write = 1;
2531
2532 alu.src[0].sel = ctx->temp_reg;
2533 alu.src[0].chan = 0;
2534 alu.last = 1;
2535 r = r600_bytecode_add_alu(ctx->bc, &alu);
2536 if (r)
2537 return r;
2538
2539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2540 alu.op = ALU_OP3_MULADD;
2541 alu.is_op3 = 1;
2542
2543 alu.dst.chan = 0;
2544 alu.dst.sel = ctx->temp_reg;
2545 alu.dst.write = 1;
2546
2547 alu.src[0].sel = ctx->temp_reg;
2548 alu.src[0].chan = 0;
2549
2550 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2551 alu.src[1].chan = 0;
2552 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2553 alu.src[2].chan = 0;
2554
2555 if (ctx->bc->chip_class == R600) {
2556 alu.src[1].value = *(uint32_t *)&double_pi;
2557 alu.src[2].value = *(uint32_t *)&neg_pi;
2558 } else {
2559 alu.src[1].sel = V_SQ_ALU_SRC_1;
2560 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2561 alu.src[2].neg = 1;
2562 }
2563
2564 alu.last = 1;
2565 r = r600_bytecode_add_alu(ctx->bc, &alu);
2566 if (r)
2567 return r;
2568 return 0;
2569 }
2570
2571 static int cayman_trig(struct r600_shader_ctx *ctx)
2572 {
2573 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2574 struct r600_bytecode_alu alu;
2575 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2576 int i, r;
2577
2578 r = tgsi_setup_trig(ctx);
2579 if (r)
2580 return r;
2581
2582
2583 for (i = 0; i < last_slot; i++) {
2584 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2585 alu.op = ctx->inst_info->op;
2586 alu.dst.chan = i;
2587
2588 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2589 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2590
2591 alu.src[0].sel = ctx->temp_reg;
2592 alu.src[0].chan = 0;
2593 if (i == last_slot - 1)
2594 alu.last = 1;
2595 r = r600_bytecode_add_alu(ctx->bc, &alu);
2596 if (r)
2597 return r;
2598 }
2599 return 0;
2600 }
2601
2602 static int tgsi_trig(struct r600_shader_ctx *ctx)
2603 {
2604 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2605 struct r600_bytecode_alu alu;
2606 int i, r;
2607 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2608
2609 r = tgsi_setup_trig(ctx);
2610 if (r)
2611 return r;
2612
2613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2614 alu.op = ctx->inst_info->op;
2615 alu.dst.chan = 0;
2616 alu.dst.sel = ctx->temp_reg;
2617 alu.dst.write = 1;
2618
2619 alu.src[0].sel = ctx->temp_reg;
2620 alu.src[0].chan = 0;
2621 alu.last = 1;
2622 r = r600_bytecode_add_alu(ctx->bc, &alu);
2623 if (r)
2624 return r;
2625
2626 /* replicate result */
2627 for (i = 0; i < lasti + 1; i++) {
2628 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2629 continue;
2630
2631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2632 alu.op = ALU_OP1_MOV;
2633
2634 alu.src[0].sel = ctx->temp_reg;
2635 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2636 if (i == lasti)
2637 alu.last = 1;
2638 r = r600_bytecode_add_alu(ctx->bc, &alu);
2639 if (r)
2640 return r;
2641 }
2642 return 0;
2643 }
2644
2645 static int tgsi_scs(struct r600_shader_ctx *ctx)
2646 {
2647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2648 struct r600_bytecode_alu alu;
2649 int i, r;
2650
2651 /* We'll only need the trig stuff if we are going to write to the
2652 * X or Y components of the destination vector.
2653 */
2654 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2655 r = tgsi_setup_trig(ctx);
2656 if (r)
2657 return r;
2658 }
2659
2660 /* dst.x = COS */
2661 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2662 if (ctx->bc->chip_class == CAYMAN) {
2663 for (i = 0 ; i < 3; i++) {
2664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2665 alu.op = ALU_OP1_COS;
2666 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2667
2668 if (i == 0)
2669 alu.dst.write = 1;
2670 else
2671 alu.dst.write = 0;
2672 alu.src[0].sel = ctx->temp_reg;
2673 alu.src[0].chan = 0;
2674 if (i == 2)
2675 alu.last = 1;
2676 r = r600_bytecode_add_alu(ctx->bc, &alu);
2677 if (r)
2678 return r;
2679 }
2680 } else {
2681 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2682 alu.op = ALU_OP1_COS;
2683 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2684
2685 alu.src[0].sel = ctx->temp_reg;
2686 alu.src[0].chan = 0;
2687 alu.last = 1;
2688 r = r600_bytecode_add_alu(ctx->bc, &alu);
2689 if (r)
2690 return r;
2691 }
2692 }
2693
2694 /* dst.y = SIN */
2695 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2696 if (ctx->bc->chip_class == CAYMAN) {
2697 for (i = 0 ; i < 3; i++) {
2698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2699 alu.op = ALU_OP1_SIN;
2700 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2701 if (i == 1)
2702 alu.dst.write = 1;
2703 else
2704 alu.dst.write = 0;
2705 alu.src[0].sel = ctx->temp_reg;
2706 alu.src[0].chan = 0;
2707 if (i == 2)
2708 alu.last = 1;
2709 r = r600_bytecode_add_alu(ctx->bc, &alu);
2710 if (r)
2711 return r;
2712 }
2713 } else {
2714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2715 alu.op = ALU_OP1_SIN;
2716 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2717
2718 alu.src[0].sel = ctx->temp_reg;
2719 alu.src[0].chan = 0;
2720 alu.last = 1;
2721 r = r600_bytecode_add_alu(ctx->bc, &alu);
2722 if (r)
2723 return r;
2724 }
2725 }
2726
2727 /* dst.z = 0.0; */
2728 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2730
2731 alu.op = ALU_OP1_MOV;
2732
2733 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2734
2735 alu.src[0].sel = V_SQ_ALU_SRC_0;
2736 alu.src[0].chan = 0;
2737
2738 alu.last = 1;
2739
2740 r = r600_bytecode_add_alu(ctx->bc, &alu);
2741 if (r)
2742 return r;
2743 }
2744
2745 /* dst.w = 1.0; */
2746 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2747 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2748
2749 alu.op = ALU_OP1_MOV;
2750
2751 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2752
2753 alu.src[0].sel = V_SQ_ALU_SRC_1;
2754 alu.src[0].chan = 0;
2755
2756 alu.last = 1;
2757
2758 r = r600_bytecode_add_alu(ctx->bc, &alu);
2759 if (r)
2760 return r;
2761 }
2762
2763 return 0;
2764 }
2765
2766 static int tgsi_kill(struct r600_shader_ctx *ctx)
2767 {
2768 struct r600_bytecode_alu alu;
2769 int i, r;
2770
2771 for (i = 0; i < 4; i++) {
2772 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2773 alu.op = ctx->inst_info->op;
2774
2775 alu.dst.chan = i;
2776
2777 alu.src[0].sel = V_SQ_ALU_SRC_0;
2778
2779 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILL) {
2780 alu.src[1].sel = V_SQ_ALU_SRC_1;
2781 alu.src[1].neg = 1;
2782 } else {
2783 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2784 }
2785 if (i == 3) {
2786 alu.last = 1;
2787 }
2788 r = r600_bytecode_add_alu(ctx->bc, &alu);
2789 if (r)
2790 return r;
2791 }
2792
2793 /* kill must be last in ALU */
2794 ctx->bc->force_add_cf = 1;
2795 ctx->shader->uses_kill = TRUE;
2796 return 0;
2797 }
2798
2799 static int tgsi_lit(struct r600_shader_ctx *ctx)
2800 {
2801 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2802 struct r600_bytecode_alu alu;
2803 int r;
2804
2805 /* tmp.x = max(src.y, 0.0) */
2806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2807 alu.op = ALU_OP2_MAX;
2808 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2809 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2810 alu.src[1].chan = 1;
2811
2812 alu.dst.sel = ctx->temp_reg;
2813 alu.dst.chan = 0;
2814 alu.dst.write = 1;
2815
2816 alu.last = 1;
2817 r = r600_bytecode_add_alu(ctx->bc, &alu);
2818 if (r)
2819 return r;
2820
2821 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2822 {
2823 int chan;
2824 int sel;
2825 int i;
2826
2827 if (ctx->bc->chip_class == CAYMAN) {
2828 for (i = 0; i < 3; i++) {
2829 /* tmp.z = log(tmp.x) */
2830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2831 alu.op = ALU_OP1_LOG_CLAMPED;
2832 alu.src[0].sel = ctx->temp_reg;
2833 alu.src[0].chan = 0;
2834 alu.dst.sel = ctx->temp_reg;
2835 alu.dst.chan = i;
2836 if (i == 2) {
2837 alu.dst.write = 1;
2838 alu.last = 1;
2839 } else
2840 alu.dst.write = 0;
2841
2842 r = r600_bytecode_add_alu(ctx->bc, &alu);
2843 if (r)
2844 return r;
2845 }
2846 } else {
2847 /* tmp.z = log(tmp.x) */
2848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2849 alu.op = ALU_OP1_LOG_CLAMPED;
2850 alu.src[0].sel = ctx->temp_reg;
2851 alu.src[0].chan = 0;
2852 alu.dst.sel = ctx->temp_reg;
2853 alu.dst.chan = 2;
2854 alu.dst.write = 1;
2855 alu.last = 1;
2856 r = r600_bytecode_add_alu(ctx->bc, &alu);
2857 if (r)
2858 return r;
2859 }
2860
2861 chan = alu.dst.chan;
2862 sel = alu.dst.sel;
2863
2864 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2866 alu.op = ALU_OP3_MUL_LIT;
2867 alu.src[0].sel = sel;
2868 alu.src[0].chan = chan;
2869 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2870 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2871 alu.dst.sel = ctx->temp_reg;
2872 alu.dst.chan = 0;
2873 alu.dst.write = 1;
2874 alu.is_op3 = 1;
2875 alu.last = 1;
2876 r = r600_bytecode_add_alu(ctx->bc, &alu);
2877 if (r)
2878 return r;
2879
2880 if (ctx->bc->chip_class == CAYMAN) {
2881 for (i = 0; i < 3; i++) {
2882 /* dst.z = exp(tmp.x) */
2883 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2884 alu.op = ALU_OP1_EXP_IEEE;
2885 alu.src[0].sel = ctx->temp_reg;
2886 alu.src[0].chan = 0;
2887 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2888 if (i == 2) {
2889 alu.dst.write = 1;
2890 alu.last = 1;
2891 } else
2892 alu.dst.write = 0;
2893 r = r600_bytecode_add_alu(ctx->bc, &alu);
2894 if (r)
2895 return r;
2896 }
2897 } else {
2898 /* dst.z = exp(tmp.x) */
2899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2900 alu.op = ALU_OP1_EXP_IEEE;
2901 alu.src[0].sel = ctx->temp_reg;
2902 alu.src[0].chan = 0;
2903 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2904 alu.last = 1;
2905 r = r600_bytecode_add_alu(ctx->bc, &alu);
2906 if (r)
2907 return r;
2908 }
2909 }
2910
2911 /* dst.x, <- 1.0 */
2912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2913 alu.op = ALU_OP1_MOV;
2914 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2915 alu.src[0].chan = 0;
2916 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2917 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2918 r = r600_bytecode_add_alu(ctx->bc, &alu);
2919 if (r)
2920 return r;
2921
2922 /* dst.y = max(src.x, 0.0) */
2923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2924 alu.op = ALU_OP2_MAX;
2925 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2926 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2927 alu.src[1].chan = 0;
2928 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2929 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2930 r = r600_bytecode_add_alu(ctx->bc, &alu);
2931 if (r)
2932 return r;
2933
2934 /* dst.w, <- 1.0 */
2935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2936 alu.op = ALU_OP1_MOV;
2937 alu.src[0].sel = V_SQ_ALU_SRC_1;
2938 alu.src[0].chan = 0;
2939 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2940 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2941 alu.last = 1;
2942 r = r600_bytecode_add_alu(ctx->bc, &alu);
2943 if (r)
2944 return r;
2945
2946 return 0;
2947 }
2948
2949 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2950 {
2951 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2952 struct r600_bytecode_alu alu;
2953 int i, r;
2954
2955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2956
2957 /* XXX:
2958 * For state trackers other than OpenGL, we'll want to use
2959 * _RECIPSQRT_IEEE instead.
2960 */
2961 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2962
2963 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2964 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2965 r600_bytecode_src_set_abs(&alu.src[i]);
2966 }
2967 alu.dst.sel = ctx->temp_reg;
2968 alu.dst.write = 1;
2969 alu.last = 1;
2970 r = r600_bytecode_add_alu(ctx->bc, &alu);
2971 if (r)
2972 return r;
2973 /* replicate result */
2974 return tgsi_helper_tempx_replicate(ctx);
2975 }
2976
2977 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2978 {
2979 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2980 struct r600_bytecode_alu alu;
2981 int i, r;
2982
2983 for (i = 0; i < 4; i++) {
2984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2985 alu.src[0].sel = ctx->temp_reg;
2986 alu.op = ALU_OP1_MOV;
2987 alu.dst.chan = i;
2988 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2989 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2990 if (i == 3)
2991 alu.last = 1;
2992 r = r600_bytecode_add_alu(ctx->bc, &alu);
2993 if (r)
2994 return r;
2995 }
2996 return 0;
2997 }
2998
2999 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
3000 {
3001 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3002 struct r600_bytecode_alu alu;
3003 int i, r;
3004
3005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3006 alu.op = ctx->inst_info->op;
3007 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3008 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3009 }
3010 alu.dst.sel = ctx->temp_reg;
3011 alu.dst.write = 1;
3012 alu.last = 1;
3013 r = r600_bytecode_add_alu(ctx->bc, &alu);
3014 if (r)
3015 return r;
3016 /* replicate result */
3017 return tgsi_helper_tempx_replicate(ctx);
3018 }
3019
3020 static int cayman_pow(struct r600_shader_ctx *ctx)
3021 {
3022 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3023 int i, r;
3024 struct r600_bytecode_alu alu;
3025 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3026
3027 for (i = 0; i < 3; i++) {
3028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3029 alu.op = ALU_OP1_LOG_IEEE;
3030 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3031 alu.dst.sel = ctx->temp_reg;
3032 alu.dst.chan = i;
3033 alu.dst.write = 1;
3034 if (i == 2)
3035 alu.last = 1;
3036 r = r600_bytecode_add_alu(ctx->bc, &alu);
3037 if (r)
3038 return r;
3039 }
3040
3041 /* b * LOG2(a) */
3042 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3043 alu.op = ALU_OP2_MUL;
3044 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3045 alu.src[1].sel = ctx->temp_reg;
3046 alu.dst.sel = ctx->temp_reg;
3047 alu.dst.write = 1;
3048 alu.last = 1;
3049 r = r600_bytecode_add_alu(ctx->bc, &alu);
3050 if (r)
3051 return r;
3052
3053 for (i = 0; i < last_slot; i++) {
3054 /* POW(a,b) = EXP2(b * LOG2(a))*/
3055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3056 alu.op = ALU_OP1_EXP_IEEE;
3057 alu.src[0].sel = ctx->temp_reg;
3058
3059 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3060 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3061 if (i == last_slot - 1)
3062 alu.last = 1;
3063 r = r600_bytecode_add_alu(ctx->bc, &alu);
3064 if (r)
3065 return r;
3066 }
3067 return 0;
3068 }
3069
3070 static int tgsi_pow(struct r600_shader_ctx *ctx)
3071 {
3072 struct r600_bytecode_alu alu;
3073 int r;
3074
3075 /* LOG2(a) */
3076 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3077 alu.op = ALU_OP1_LOG_IEEE;
3078 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3079 alu.dst.sel = ctx->temp_reg;
3080 alu.dst.write = 1;
3081 alu.last = 1;
3082 r = r600_bytecode_add_alu(ctx->bc, &alu);
3083 if (r)
3084 return r;
3085 /* b * LOG2(a) */
3086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3087 alu.op = ALU_OP2_MUL;
3088 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3089 alu.src[1].sel = ctx->temp_reg;
3090 alu.dst.sel = ctx->temp_reg;
3091 alu.dst.write = 1;
3092 alu.last = 1;
3093 r = r600_bytecode_add_alu(ctx->bc, &alu);
3094 if (r)
3095 return r;
3096 /* POW(a,b) = EXP2(b * LOG2(a))*/
3097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3098 alu.op = ALU_OP1_EXP_IEEE;
3099 alu.src[0].sel = ctx->temp_reg;
3100 alu.dst.sel = ctx->temp_reg;
3101 alu.dst.write = 1;
3102 alu.last = 1;
3103 r = r600_bytecode_add_alu(ctx->bc, &alu);
3104 if (r)
3105 return r;
3106 return tgsi_helper_tempx_replicate(ctx);
3107 }
3108
3109 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
3110 {
3111 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3112 struct r600_bytecode_alu alu;
3113 int i, r, j;
3114 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3115 int tmp0 = ctx->temp_reg;
3116 int tmp1 = r600_get_temp(ctx);
3117 int tmp2 = r600_get_temp(ctx);
3118 int tmp3 = r600_get_temp(ctx);
3119 /* Unsigned path:
3120 *
3121 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3122 *
3123 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3124 * 2. tmp0.z = lo (tmp0.x * src2)
3125 * 3. tmp0.w = -tmp0.z
3126 * 4. tmp0.y = hi (tmp0.x * src2)
3127 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3128 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3129 * 7. tmp1.x = tmp0.x - tmp0.w
3130 * 8. tmp1.y = tmp0.x + tmp0.w
3131 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3132 * 10. tmp0.z = hi(tmp0.x * src1) = q
3133 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3134 *
3135 * 12. tmp0.w = src1 - tmp0.y = r
3136 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3137 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3138 *
3139 * if DIV
3140 *
3141 * 15. tmp1.z = tmp0.z + 1 = q + 1
3142 * 16. tmp1.w = tmp0.z - 1 = q - 1
3143 *
3144 * else MOD
3145 *
3146 * 15. tmp1.z = tmp0.w - src2 = r - src2
3147 * 16. tmp1.w = tmp0.w + src2 = r + src2
3148 *
3149 * endif
3150 *
3151 * 17. tmp1.x = tmp1.x & tmp1.y
3152 *
3153 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3154 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3155 *
3156 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3157 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
3158 *
3159 * Signed path:
3160 *
3161 * Same as unsigned, using abs values of the operands,
3162 * and fixing the sign of the result in the end.
3163 */
3164
3165 for (i = 0; i < 4; i++) {
3166 if (!(write_mask & (1<<i)))
3167 continue;
3168
3169 if (signed_op) {
3170
3171 /* tmp2.x = -src0 */
3172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3173 alu.op = ALU_OP2_SUB_INT;
3174
3175 alu.dst.sel = tmp2;
3176 alu.dst.chan = 0;
3177 alu.dst.write = 1;
3178
3179 alu.src[0].sel = V_SQ_ALU_SRC_0;
3180
3181 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3182
3183 alu.last = 1;
3184 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3185 return r;
3186
3187 /* tmp2.y = -src1 */
3188 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3189 alu.op = ALU_OP2_SUB_INT;
3190
3191 alu.dst.sel = tmp2;
3192 alu.dst.chan = 1;
3193 alu.dst.write = 1;
3194
3195 alu.src[0].sel = V_SQ_ALU_SRC_0;
3196
3197 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3198
3199 alu.last = 1;
3200 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3201 return r;
3202
3203 /* tmp2.z sign bit is set if src0 and src2 signs are different */
3204 /* it will be a sign of the quotient */
3205 if (!mod) {
3206
3207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3208 alu.op = ALU_OP2_XOR_INT;
3209
3210 alu.dst.sel = tmp2;
3211 alu.dst.chan = 2;
3212 alu.dst.write = 1;
3213
3214 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3215 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3216
3217 alu.last = 1;
3218 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3219 return r;
3220 }
3221
3222 /* tmp2.x = |src0| */
3223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3224 alu.op = ALU_OP3_CNDGE_INT;
3225 alu.is_op3 = 1;
3226
3227 alu.dst.sel = tmp2;
3228 alu.dst.chan = 0;
3229 alu.dst.write = 1;
3230
3231 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3232 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3233 alu.src[2].sel = tmp2;
3234 alu.src[2].chan = 0;
3235
3236 alu.last = 1;
3237 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3238 return r;
3239
3240 /* tmp2.y = |src1| */
3241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3242 alu.op = ALU_OP3_CNDGE_INT;
3243 alu.is_op3 = 1;
3244
3245 alu.dst.sel = tmp2;
3246 alu.dst.chan = 1;
3247 alu.dst.write = 1;
3248
3249 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3250 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3251 alu.src[2].sel = tmp2;
3252 alu.src[2].chan = 1;
3253
3254 alu.last = 1;
3255 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3256 return r;
3257
3258 }
3259
3260 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
3261 if (ctx->bc->chip_class == CAYMAN) {
3262 /* tmp3.x = u2f(src2) */
3263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3264 alu.op = ALU_OP1_UINT_TO_FLT;
3265
3266 alu.dst.sel = tmp3;
3267 alu.dst.chan = 0;
3268 alu.dst.write = 1;
3269
3270 if (signed_op) {
3271 alu.src[0].sel = tmp2;
3272 alu.src[0].chan = 1;
3273 } else {
3274 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3275 }
3276
3277 alu.last = 1;
3278 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3279 return r;
3280
3281 /* tmp0.x = recip(tmp3.x) */
3282 for (j = 0 ; j < 3; j++) {
3283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3284 alu.op = ALU_OP1_RECIP_IEEE;
3285
3286 alu.dst.sel = tmp0;
3287 alu.dst.chan = j;
3288 alu.dst.write = (j == 0);
3289
3290 alu.src[0].sel = tmp3;
3291 alu.src[0].chan = 0;
3292
3293 if (j == 2)
3294 alu.last = 1;
3295 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3296 return r;
3297 }
3298
3299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3300 alu.op = ALU_OP2_MUL;
3301
3302 alu.src[0].sel = tmp0;
3303 alu.src[0].chan = 0;
3304
3305 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3306 alu.src[1].value = 0x4f800000;
3307
3308 alu.dst.sel = tmp3;
3309 alu.dst.write = 1;
3310 alu.last = 1;
3311 r = r600_bytecode_add_alu(ctx->bc, &alu);
3312 if (r)
3313 return r;
3314
3315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3316 alu.op = ALU_OP1_FLT_TO_UINT;
3317
3318 alu.dst.sel = tmp0;
3319 alu.dst.chan = 0;
3320 alu.dst.write = 1;
3321
3322 alu.src[0].sel = tmp3;
3323 alu.src[0].chan = 0;
3324
3325 alu.last = 1;
3326 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3327 return r;
3328
3329 } else {
3330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3331 alu.op = ALU_OP1_RECIP_UINT;
3332
3333 alu.dst.sel = tmp0;
3334 alu.dst.chan = 0;
3335 alu.dst.write = 1;
3336
3337 if (signed_op) {
3338 alu.src[0].sel = tmp2;
3339 alu.src[0].chan = 1;
3340 } else {
3341 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3342 }
3343
3344 alu.last = 1;
3345 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3346 return r;
3347 }
3348
3349 /* 2. tmp0.z = lo (tmp0.x * src2) */
3350 if (ctx->bc->chip_class == CAYMAN) {
3351 for (j = 0 ; j < 4; j++) {
3352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3353 alu.op = ALU_OP2_MULLO_UINT;
3354
3355 alu.dst.sel = tmp0;
3356 alu.dst.chan = j;
3357 alu.dst.write = (j == 2);
3358
3359 alu.src[0].sel = tmp0;
3360 alu.src[0].chan = 0;
3361 if (signed_op) {
3362 alu.src[1].sel = tmp2;
3363 alu.src[1].chan = 1;
3364 } else {
3365 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3366 }
3367
3368 alu.last = (j == 3);
3369 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3370 return r;
3371 }
3372 } else {
3373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3374 alu.op = ALU_OP2_MULLO_UINT;
3375
3376 alu.dst.sel = tmp0;
3377 alu.dst.chan = 2;
3378 alu.dst.write = 1;
3379
3380 alu.src[0].sel = tmp0;
3381 alu.src[0].chan = 0;
3382 if (signed_op) {
3383 alu.src[1].sel = tmp2;
3384 alu.src[1].chan = 1;
3385 } else {
3386 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3387 }
3388
3389 alu.last = 1;
3390 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3391 return r;
3392 }
3393
3394 /* 3. tmp0.w = -tmp0.z */
3395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3396 alu.op = ALU_OP2_SUB_INT;
3397
3398 alu.dst.sel = tmp0;
3399 alu.dst.chan = 3;
3400 alu.dst.write = 1;
3401
3402 alu.src[0].sel = V_SQ_ALU_SRC_0;
3403 alu.src[1].sel = tmp0;
3404 alu.src[1].chan = 2;
3405
3406 alu.last = 1;
3407 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3408 return r;
3409
3410 /* 4. tmp0.y = hi (tmp0.x * src2) */
3411 if (ctx->bc->chip_class == CAYMAN) {
3412 for (j = 0 ; j < 4; j++) {
3413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3414 alu.op = ALU_OP2_MULHI_UINT;
3415
3416 alu.dst.sel = tmp0;
3417 alu.dst.chan = j;
3418 alu.dst.write = (j == 1);
3419
3420 alu.src[0].sel = tmp0;
3421 alu.src[0].chan = 0;
3422
3423 if (signed_op) {
3424 alu.src[1].sel = tmp2;
3425 alu.src[1].chan = 1;
3426 } else {
3427 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3428 }
3429 alu.last = (j == 3);
3430 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3431 return r;
3432 }
3433 } else {
3434 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3435 alu.op = ALU_OP2_MULHI_UINT;
3436
3437 alu.dst.sel = tmp0;
3438 alu.dst.chan = 1;
3439 alu.dst.write = 1;
3440
3441 alu.src[0].sel = tmp0;
3442 alu.src[0].chan = 0;
3443
3444 if (signed_op) {
3445 alu.src[1].sel = tmp2;
3446 alu.src[1].chan = 1;
3447 } else {
3448 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3449 }
3450
3451 alu.last = 1;
3452 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3453 return r;
3454 }
3455
3456 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3457 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3458 alu.op = ALU_OP3_CNDE_INT;
3459 alu.is_op3 = 1;
3460
3461 alu.dst.sel = tmp0;
3462 alu.dst.chan = 2;
3463 alu.dst.write = 1;
3464
3465 alu.src[0].sel = tmp0;
3466 alu.src[0].chan = 1;
3467 alu.src[1].sel = tmp0;
3468 alu.src[1].chan = 3;
3469 alu.src[2].sel = tmp0;
3470 alu.src[2].chan = 2;
3471
3472 alu.last = 1;
3473 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3474 return r;
3475
3476 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3477 if (ctx->bc->chip_class == CAYMAN) {
3478 for (j = 0 ; j < 4; j++) {
3479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3480 alu.op = ALU_OP2_MULHI_UINT;
3481
3482 alu.dst.sel = tmp0;
3483 alu.dst.chan = j;
3484 alu.dst.write = (j == 3);
3485
3486 alu.src[0].sel = tmp0;
3487 alu.src[0].chan = 2;
3488
3489 alu.src[1].sel = tmp0;
3490 alu.src[1].chan = 0;
3491
3492 alu.last = (j == 3);
3493 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3494 return r;
3495 }
3496 } else {
3497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3498 alu.op = ALU_OP2_MULHI_UINT;
3499
3500 alu.dst.sel = tmp0;
3501 alu.dst.chan = 3;
3502 alu.dst.write = 1;
3503
3504 alu.src[0].sel = tmp0;
3505 alu.src[0].chan = 2;
3506
3507 alu.src[1].sel = tmp0;
3508 alu.src[1].chan = 0;
3509
3510 alu.last = 1;
3511 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3512 return r;
3513 }
3514
3515 /* 7. tmp1.x = tmp0.x - tmp0.w */
3516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3517 alu.op = ALU_OP2_SUB_INT;
3518
3519 alu.dst.sel = tmp1;
3520 alu.dst.chan = 0;
3521 alu.dst.write = 1;
3522
3523 alu.src[0].sel = tmp0;
3524 alu.src[0].chan = 0;
3525 alu.src[1].sel = tmp0;
3526 alu.src[1].chan = 3;
3527
3528 alu.last = 1;
3529 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3530 return r;
3531
3532 /* 8. tmp1.y = tmp0.x + tmp0.w */
3533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3534 alu.op = ALU_OP2_ADD_INT;
3535
3536 alu.dst.sel = tmp1;
3537 alu.dst.chan = 1;
3538 alu.dst.write = 1;
3539
3540 alu.src[0].sel = tmp0;
3541 alu.src[0].chan = 0;
3542 alu.src[1].sel = tmp0;
3543 alu.src[1].chan = 3;
3544
3545 alu.last = 1;
3546 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3547 return r;
3548
3549 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3550 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3551 alu.op = ALU_OP3_CNDE_INT;
3552 alu.is_op3 = 1;
3553
3554 alu.dst.sel = tmp0;
3555 alu.dst.chan = 0;
3556 alu.dst.write = 1;
3557
3558 alu.src[0].sel = tmp0;
3559 alu.src[0].chan = 1;
3560 alu.src[1].sel = tmp1;
3561 alu.src[1].chan = 1;
3562 alu.src[2].sel = tmp1;
3563 alu.src[2].chan = 0;
3564
3565 alu.last = 1;
3566 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3567 return r;
3568
3569 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3570 if (ctx->bc->chip_class == CAYMAN) {
3571 for (j = 0 ; j < 4; j++) {
3572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3573 alu.op = ALU_OP2_MULHI_UINT;
3574
3575 alu.dst.sel = tmp0;
3576 alu.dst.chan = j;
3577 alu.dst.write = (j == 2);
3578
3579 alu.src[0].sel = tmp0;
3580 alu.src[0].chan = 0;
3581
3582 if (signed_op) {
3583 alu.src[1].sel = tmp2;
3584 alu.src[1].chan = 0;
3585 } else {
3586 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3587 }
3588
3589 alu.last = (j == 3);
3590 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3591 return r;
3592 }
3593 } else {
3594 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3595 alu.op = ALU_OP2_MULHI_UINT;
3596
3597 alu.dst.sel = tmp0;
3598 alu.dst.chan = 2;
3599 alu.dst.write = 1;
3600
3601 alu.src[0].sel = tmp0;
3602 alu.src[0].chan = 0;
3603
3604 if (signed_op) {
3605 alu.src[1].sel = tmp2;
3606 alu.src[1].chan = 0;
3607 } else {
3608 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3609 }
3610
3611 alu.last = 1;
3612 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3613 return r;
3614 }
3615
3616 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3617 if (ctx->bc->chip_class == CAYMAN) {
3618 for (j = 0 ; j < 4; j++) {
3619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3620 alu.op = ALU_OP2_MULLO_UINT;
3621
3622 alu.dst.sel = tmp0;
3623 alu.dst.chan = j;
3624 alu.dst.write = (j == 1);
3625
3626 if (signed_op) {
3627 alu.src[0].sel = tmp2;
3628 alu.src[0].chan = 1;
3629 } else {
3630 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3631 }
3632
3633 alu.src[1].sel = tmp0;
3634 alu.src[1].chan = 2;
3635
3636 alu.last = (j == 3);
3637 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3638 return r;
3639 }
3640 } else {
3641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3642 alu.op = ALU_OP2_MULLO_UINT;
3643
3644 alu.dst.sel = tmp0;
3645 alu.dst.chan = 1;
3646 alu.dst.write = 1;
3647
3648 if (signed_op) {
3649 alu.src[0].sel = tmp2;
3650 alu.src[0].chan = 1;
3651 } else {
3652 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3653 }
3654
3655 alu.src[1].sel = tmp0;
3656 alu.src[1].chan = 2;
3657
3658 alu.last = 1;
3659 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3660 return r;
3661 }
3662
3663 /* 12. tmp0.w = src1 - tmp0.y = r */
3664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3665 alu.op = ALU_OP2_SUB_INT;
3666
3667 alu.dst.sel = tmp0;
3668 alu.dst.chan = 3;
3669 alu.dst.write = 1;
3670
3671 if (signed_op) {
3672 alu.src[0].sel = tmp2;
3673 alu.src[0].chan = 0;
3674 } else {
3675 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3676 }
3677
3678 alu.src[1].sel = tmp0;
3679 alu.src[1].chan = 1;
3680
3681 alu.last = 1;
3682 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3683 return r;
3684
3685 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3687 alu.op = ALU_OP2_SETGE_UINT;
3688
3689 alu.dst.sel = tmp1;
3690 alu.dst.chan = 0;
3691 alu.dst.write = 1;
3692
3693 alu.src[0].sel = tmp0;
3694 alu.src[0].chan = 3;
3695 if (signed_op) {
3696 alu.src[1].sel = tmp2;
3697 alu.src[1].chan = 1;
3698 } else {
3699 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3700 }
3701
3702 alu.last = 1;
3703 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3704 return r;
3705
3706 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3708 alu.op = ALU_OP2_SETGE_UINT;
3709
3710 alu.dst.sel = tmp1;
3711 alu.dst.chan = 1;
3712 alu.dst.write = 1;
3713
3714 if (signed_op) {
3715 alu.src[0].sel = tmp2;
3716 alu.src[0].chan = 0;
3717 } else {
3718 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3719 }
3720
3721 alu.src[1].sel = tmp0;
3722 alu.src[1].chan = 1;
3723
3724 alu.last = 1;
3725 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3726 return r;
3727
3728 if (mod) { /* UMOD */
3729
3730 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3732 alu.op = ALU_OP2_SUB_INT;
3733
3734 alu.dst.sel = tmp1;
3735 alu.dst.chan = 2;
3736 alu.dst.write = 1;
3737
3738 alu.src[0].sel = tmp0;
3739 alu.src[0].chan = 3;
3740
3741 if (signed_op) {
3742 alu.src[1].sel = tmp2;
3743 alu.src[1].chan = 1;
3744 } else {
3745 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3746 }
3747
3748 alu.last = 1;
3749 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3750 return r;
3751
3752 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3754 alu.op = ALU_OP2_ADD_INT;
3755
3756 alu.dst.sel = tmp1;
3757 alu.dst.chan = 3;
3758 alu.dst.write = 1;
3759
3760 alu.src[0].sel = tmp0;
3761 alu.src[0].chan = 3;
3762 if (signed_op) {
3763 alu.src[1].sel = tmp2;
3764 alu.src[1].chan = 1;
3765 } else {
3766 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3767 }
3768
3769 alu.last = 1;
3770 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3771 return r;
3772
3773 } else { /* UDIV */
3774
3775 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3777 alu.op = ALU_OP2_ADD_INT;
3778
3779 alu.dst.sel = tmp1;
3780 alu.dst.chan = 2;
3781 alu.dst.write = 1;
3782
3783 alu.src[0].sel = tmp0;
3784 alu.src[0].chan = 2;
3785 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3786
3787 alu.last = 1;
3788 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3789 return r;
3790
3791 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3793 alu.op = ALU_OP2_ADD_INT;
3794
3795 alu.dst.sel = tmp1;
3796 alu.dst.chan = 3;
3797 alu.dst.write = 1;
3798
3799 alu.src[0].sel = tmp0;
3800 alu.src[0].chan = 2;
3801 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3802
3803 alu.last = 1;
3804 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3805 return r;
3806
3807 }
3808
3809 /* 17. tmp1.x = tmp1.x & tmp1.y */
3810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3811 alu.op = ALU_OP2_AND_INT;
3812
3813 alu.dst.sel = tmp1;
3814 alu.dst.chan = 0;
3815 alu.dst.write = 1;
3816
3817 alu.src[0].sel = tmp1;
3818 alu.src[0].chan = 0;
3819 alu.src[1].sel = tmp1;
3820 alu.src[1].chan = 1;
3821
3822 alu.last = 1;
3823 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3824 return r;
3825
3826 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3827 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3829 alu.op = ALU_OP3_CNDE_INT;
3830 alu.is_op3 = 1;
3831
3832 alu.dst.sel = tmp0;
3833 alu.dst.chan = 2;
3834 alu.dst.write = 1;
3835
3836 alu.src[0].sel = tmp1;
3837 alu.src[0].chan = 0;
3838 alu.src[1].sel = tmp0;
3839 alu.src[1].chan = mod ? 3 : 2;
3840 alu.src[2].sel = tmp1;
3841 alu.src[2].chan = 2;
3842
3843 alu.last = 1;
3844 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3845 return r;
3846
3847 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3849 alu.op = ALU_OP3_CNDE_INT;
3850 alu.is_op3 = 1;
3851
3852 if (signed_op) {
3853 alu.dst.sel = tmp0;
3854 alu.dst.chan = 2;
3855 alu.dst.write = 1;
3856 } else {
3857 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3858 }
3859
3860 alu.src[0].sel = tmp1;
3861 alu.src[0].chan = 1;
3862 alu.src[1].sel = tmp1;
3863 alu.src[1].chan = 3;
3864 alu.src[2].sel = tmp0;
3865 alu.src[2].chan = 2;
3866
3867 alu.last = 1;
3868 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3869 return r;
3870
3871 if (signed_op) {
3872
3873 /* fix the sign of the result */
3874
3875 if (mod) {
3876
3877 /* tmp0.x = -tmp0.z */
3878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3879 alu.op = ALU_OP2_SUB_INT;
3880
3881 alu.dst.sel = tmp0;
3882 alu.dst.chan = 0;
3883 alu.dst.write = 1;
3884
3885 alu.src[0].sel = V_SQ_ALU_SRC_0;
3886 alu.src[1].sel = tmp0;
3887 alu.src[1].chan = 2;
3888
3889 alu.last = 1;
3890 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3891 return r;
3892
3893 /* sign of the remainder is the same as the sign of src0 */
3894 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3896 alu.op = ALU_OP3_CNDGE_INT;
3897 alu.is_op3 = 1;
3898
3899 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3900
3901 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3902 alu.src[1].sel = tmp0;
3903 alu.src[1].chan = 2;
3904 alu.src[2].sel = tmp0;
3905 alu.src[2].chan = 0;
3906
3907 alu.last = 1;
3908 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3909 return r;
3910
3911 } else {
3912
3913 /* tmp0.x = -tmp0.z */
3914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3915 alu.op = ALU_OP2_SUB_INT;
3916
3917 alu.dst.sel = tmp0;
3918 alu.dst.chan = 0;
3919 alu.dst.write = 1;
3920
3921 alu.src[0].sel = V_SQ_ALU_SRC_0;
3922 alu.src[1].sel = tmp0;
3923 alu.src[1].chan = 2;
3924
3925 alu.last = 1;
3926 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3927 return r;
3928
3929 /* fix the quotient sign (same as the sign of src0*src1) */
3930 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3932 alu.op = ALU_OP3_CNDGE_INT;
3933 alu.is_op3 = 1;
3934
3935 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3936
3937 alu.src[0].sel = tmp2;
3938 alu.src[0].chan = 2;
3939 alu.src[1].sel = tmp0;
3940 alu.src[1].chan = 2;
3941 alu.src[2].sel = tmp0;
3942 alu.src[2].chan = 0;
3943
3944 alu.last = 1;
3945 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3946 return r;
3947 }
3948 }
3949 }
3950 return 0;
3951 }
3952
3953 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3954 {
3955 return tgsi_divmod(ctx, 0, 0);
3956 }
3957
3958 static int tgsi_umod(struct r600_shader_ctx *ctx)
3959 {
3960 return tgsi_divmod(ctx, 1, 0);
3961 }
3962
3963 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3964 {
3965 return tgsi_divmod(ctx, 0, 1);
3966 }
3967
3968 static int tgsi_imod(struct r600_shader_ctx *ctx)
3969 {
3970 return tgsi_divmod(ctx, 1, 1);
3971 }
3972
3973
3974 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3975 {
3976 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3977 struct r600_bytecode_alu alu;
3978 int i, r;
3979 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3980 int last_inst = tgsi_last_instruction(write_mask);
3981
3982 for (i = 0; i < 4; i++) {
3983 if (!(write_mask & (1<<i)))
3984 continue;
3985
3986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3987 alu.op = ALU_OP1_TRUNC;
3988
3989 alu.dst.sel = ctx->temp_reg;
3990 alu.dst.chan = i;
3991 alu.dst.write = 1;
3992
3993 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3994 if (i == last_inst)
3995 alu.last = 1;
3996 r = r600_bytecode_add_alu(ctx->bc, &alu);
3997 if (r)
3998 return r;
3999 }
4000
4001 for (i = 0; i < 4; i++) {
4002 if (!(write_mask & (1<<i)))
4003 continue;
4004
4005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4006 alu.op = ctx->inst_info->op;
4007
4008 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4009
4010 alu.src[0].sel = ctx->temp_reg;
4011 alu.src[0].chan = i;
4012
4013 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
4014 alu.last = 1;
4015 r = r600_bytecode_add_alu(ctx->bc, &alu);
4016 if (r)
4017 return r;
4018 }
4019
4020 return 0;
4021 }
4022
4023 static int tgsi_iabs(struct r600_shader_ctx *ctx)
4024 {
4025 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4026 struct r600_bytecode_alu alu;
4027 int i, r;
4028 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4029 int last_inst = tgsi_last_instruction(write_mask);
4030
4031 /* tmp = -src */
4032 for (i = 0; i < 4; i++) {
4033 if (!(write_mask & (1<<i)))
4034 continue;
4035
4036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4037 alu.op = ALU_OP2_SUB_INT;
4038
4039 alu.dst.sel = ctx->temp_reg;
4040 alu.dst.chan = i;
4041 alu.dst.write = 1;
4042
4043 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4044 alu.src[0].sel = V_SQ_ALU_SRC_0;
4045
4046 if (i == last_inst)
4047 alu.last = 1;
4048 r = r600_bytecode_add_alu(ctx->bc, &alu);
4049 if (r)
4050 return r;
4051 }
4052
4053 /* dst = (src >= 0 ? src : tmp) */
4054 for (i = 0; i < 4; i++) {
4055 if (!(write_mask & (1<<i)))
4056 continue;
4057
4058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4059 alu.op = ALU_OP3_CNDGE_INT;
4060 alu.is_op3 = 1;
4061 alu.dst.write = 1;
4062
4063 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4064
4065 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4066 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4067 alu.src[2].sel = ctx->temp_reg;
4068 alu.src[2].chan = i;
4069
4070 if (i == last_inst)
4071 alu.last = 1;
4072 r = r600_bytecode_add_alu(ctx->bc, &alu);
4073 if (r)
4074 return r;
4075 }
4076 return 0;
4077 }
4078
4079 static int tgsi_issg(struct r600_shader_ctx *ctx)
4080 {
4081 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4082 struct r600_bytecode_alu alu;
4083 int i, r;
4084 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4085 int last_inst = tgsi_last_instruction(write_mask);
4086
4087 /* tmp = (src >= 0 ? src : -1) */
4088 for (i = 0; i < 4; i++) {
4089 if (!(write_mask & (1<<i)))
4090 continue;
4091
4092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4093 alu.op = ALU_OP3_CNDGE_INT;
4094 alu.is_op3 = 1;
4095
4096 alu.dst.sel = ctx->temp_reg;
4097 alu.dst.chan = i;
4098 alu.dst.write = 1;
4099
4100 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4101 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4102 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
4103
4104 if (i == last_inst)
4105 alu.last = 1;
4106 r = r600_bytecode_add_alu(ctx->bc, &alu);
4107 if (r)
4108 return r;
4109 }
4110
4111 /* dst = (tmp > 0 ? 1 : tmp) */
4112 for (i = 0; i < 4; i++) {
4113 if (!(write_mask & (1<<i)))
4114 continue;
4115
4116 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4117 alu.op = ALU_OP3_CNDGT_INT;
4118 alu.is_op3 = 1;
4119 alu.dst.write = 1;
4120
4121 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4122
4123 alu.src[0].sel = ctx->temp_reg;
4124 alu.src[0].chan = i;
4125
4126 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4127
4128 alu.src[2].sel = ctx->temp_reg;
4129 alu.src[2].chan = i;
4130
4131 if (i == last_inst)
4132 alu.last = 1;
4133 r = r600_bytecode_add_alu(ctx->bc, &alu);
4134 if (r)
4135 return r;
4136 }
4137 return 0;
4138 }
4139
4140
4141
4142 static int tgsi_ssg(struct r600_shader_ctx *ctx)
4143 {
4144 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4145 struct r600_bytecode_alu alu;
4146 int i, r;
4147
4148 /* tmp = (src > 0 ? 1 : src) */
4149 for (i = 0; i < 4; i++) {
4150 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4151 alu.op = ALU_OP3_CNDGT;
4152 alu.is_op3 = 1;
4153
4154 alu.dst.sel = ctx->temp_reg;
4155 alu.dst.chan = i;
4156
4157 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4158 alu.src[1].sel = V_SQ_ALU_SRC_1;
4159 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4160
4161 if (i == 3)
4162 alu.last = 1;
4163 r = r600_bytecode_add_alu(ctx->bc, &alu);
4164 if (r)
4165 return r;
4166 }
4167
4168 /* dst = (-tmp > 0 ? -1 : tmp) */
4169 for (i = 0; i < 4; i++) {
4170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4171 alu.op = ALU_OP3_CNDGT;
4172 alu.is_op3 = 1;
4173 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4174
4175 alu.src[0].sel = ctx->temp_reg;
4176 alu.src[0].chan = i;
4177 alu.src[0].neg = 1;
4178
4179 alu.src[1].sel = V_SQ_ALU_SRC_1;
4180 alu.src[1].neg = 1;
4181
4182 alu.src[2].sel = ctx->temp_reg;
4183 alu.src[2].chan = i;
4184
4185 if (i == 3)
4186 alu.last = 1;
4187 r = r600_bytecode_add_alu(ctx->bc, &alu);
4188 if (r)
4189 return r;
4190 }
4191 return 0;
4192 }
4193
4194 static int tgsi_bfi(struct r600_shader_ctx *ctx)
4195 {
4196 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4197 struct r600_bytecode_alu alu;
4198 int i, r, t1, t2;
4199
4200 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4201 int last_inst = tgsi_last_instruction(write_mask);
4202
4203 t1 = ctx->temp_reg;
4204
4205 for (i = 0; i < 4; i++) {
4206 if (!(write_mask & (1<<i)))
4207 continue;
4208
4209 /* create mask tmp */
4210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4211 alu.op = ALU_OP2_BFM_INT;
4212 alu.dst.sel = t1;
4213 alu.dst.chan = i;
4214 alu.dst.write = 1;
4215 alu.last = i == last_inst;
4216
4217 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
4218 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4219
4220 r = r600_bytecode_add_alu(ctx->bc, &alu);
4221 if (r)
4222 return r;
4223 }
4224
4225 t2 = r600_get_temp(ctx);
4226
4227 for (i = 0; i < 4; i++) {
4228 if (!(write_mask & (1<<i)))
4229 continue;
4230
4231 /* shift insert left */
4232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4233 alu.op = ALU_OP2_LSHL_INT;
4234 alu.dst.sel = t2;
4235 alu.dst.chan = i;
4236 alu.dst.write = 1;
4237 alu.last = i == last_inst;
4238
4239 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4240 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4241
4242 r = r600_bytecode_add_alu(ctx->bc, &alu);
4243 if (r)
4244 return r;
4245 }
4246
4247 for (i = 0; i < 4; i++) {
4248 if (!(write_mask & (1<<i)))
4249 continue;
4250
4251 /* actual bitfield insert */
4252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4253 alu.op = ALU_OP3_BFI_INT;
4254 alu.is_op3 = 1;
4255 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4256 alu.dst.chan = i;
4257 alu.dst.write = 1;
4258 alu.last = i == last_inst;
4259
4260 alu.src[0].sel = t1;
4261 alu.src[0].chan = i;
4262 alu.src[1].sel = t2;
4263 alu.src[1].chan = i;
4264 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4265
4266 r = r600_bytecode_add_alu(ctx->bc, &alu);
4267 if (r)
4268 return r;
4269 }
4270
4271 return 0;
4272 }
4273
4274 static int tgsi_msb(struct r600_shader_ctx *ctx)
4275 {
4276 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4277 struct r600_bytecode_alu alu;
4278 int i, r, t1, t2;
4279
4280 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4281 int last_inst = tgsi_last_instruction(write_mask);
4282
4283 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
4284 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
4285
4286 t1 = ctx->temp_reg;
4287
4288 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
4289 for (i = 0; i < 4; i++) {
4290 if (!(write_mask & (1<<i)))
4291 continue;
4292
4293 /* t1 = FFBH_INT / FFBH_UINT */
4294 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4295 alu.op = ctx->inst_info->op;
4296 alu.dst.sel = t1;
4297 alu.dst.chan = i;
4298 alu.dst.write = 1;
4299 alu.last = i == last_inst;
4300
4301 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4302
4303 r = r600_bytecode_add_alu(ctx->bc, &alu);
4304 if (r)
4305 return r;
4306 }
4307
4308 t2 = r600_get_temp(ctx);
4309
4310 for (i = 0; i < 4; i++) {
4311 if (!(write_mask & (1<<i)))
4312 continue;
4313
4314 /* t2 = 31 - t1 */
4315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4316 alu.op = ALU_OP2_SUB_INT;
4317 alu.dst.sel = t2;
4318 alu.dst.chan = i;
4319 alu.dst.write = 1;
4320 alu.last = i == last_inst;
4321
4322 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4323 alu.src[0].value = 31;
4324 alu.src[1].sel = t1;
4325 alu.src[1].chan = i;
4326
4327 r = r600_bytecode_add_alu(ctx->bc, &alu);
4328 if (r)
4329 return r;
4330 }
4331
4332 for (i = 0; i < 4; i++) {
4333 if (!(write_mask & (1<<i)))
4334 continue;
4335
4336 /* result = t1 >= 0 ? t2 : t1 */
4337 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4338 alu.op = ALU_OP3_CNDGE_INT;
4339 alu.is_op3 = 1;
4340 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4341 alu.dst.chan = i;
4342 alu.dst.write = 1;
4343 alu.last = i == last_inst;
4344
4345 alu.src[0].sel = t1;
4346 alu.src[0].chan = i;
4347 alu.src[1].sel = t2;
4348 alu.src[1].chan = i;
4349 alu.src[2].sel = t1;
4350 alu.src[2].chan = i;
4351
4352 r = r600_bytecode_add_alu(ctx->bc, &alu);
4353 if (r)
4354 return r;
4355 }
4356
4357 return 0;
4358 }
4359
4360 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
4361 {
4362 struct r600_bytecode_alu alu;
4363 int i, r;
4364
4365 for (i = 0; i < 4; i++) {
4366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4367 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
4368 alu.op = ALU_OP0_NOP;
4369 alu.dst.chan = i;
4370 } else {
4371 alu.op = ALU_OP1_MOV;
4372 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4373 alu.src[0].sel = ctx->temp_reg;
4374 alu.src[0].chan = i;
4375 }
4376 if (i == 3) {
4377 alu.last = 1;
4378 }
4379 r = r600_bytecode_add_alu(ctx->bc, &alu);
4380 if (r)
4381 return r;
4382 }
4383 return 0;
4384 }
4385
4386 static int tgsi_op3(struct r600_shader_ctx *ctx)
4387 {
4388 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4389 struct r600_bytecode_alu alu;
4390 int i, j, r;
4391 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4392
4393 for (i = 0; i < lasti + 1; i++) {
4394 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4395 continue;
4396
4397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4398 alu.op = ctx->inst_info->op;
4399 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4400 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4401 }
4402
4403 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4404 alu.dst.chan = i;
4405 alu.dst.write = 1;
4406 alu.is_op3 = 1;
4407 if (i == lasti) {
4408 alu.last = 1;
4409 }
4410 r = r600_bytecode_add_alu(ctx->bc, &alu);
4411 if (r)
4412 return r;
4413 }
4414 return 0;
4415 }
4416
4417 static int tgsi_dp(struct r600_shader_ctx *ctx)
4418 {
4419 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4420 struct r600_bytecode_alu alu;
4421 int i, j, r;
4422
4423 for (i = 0; i < 4; i++) {
4424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4425 alu.op = ctx->inst_info->op;
4426 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4427 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4428 }
4429
4430 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4431 alu.dst.chan = i;
4432 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4433 /* handle some special cases */
4434 switch (ctx->inst_info->tgsi_opcode) {
4435 case TGSI_OPCODE_DP2:
4436 if (i > 1) {
4437 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4438 alu.src[0].chan = alu.src[1].chan = 0;
4439 }
4440 break;
4441 case TGSI_OPCODE_DP3:
4442 if (i > 2) {
4443 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4444 alu.src[0].chan = alu.src[1].chan = 0;
4445 }
4446 break;
4447 case TGSI_OPCODE_DPH:
4448 if (i == 3) {
4449 alu.src[0].sel = V_SQ_ALU_SRC_1;
4450 alu.src[0].chan = 0;
4451 alu.src[0].neg = 0;
4452 }
4453 break;
4454 default:
4455 break;
4456 }
4457 if (i == 3) {
4458 alu.last = 1;
4459 }
4460 r = r600_bytecode_add_alu(ctx->bc, &alu);
4461 if (r)
4462 return r;
4463 }
4464 return 0;
4465 }
4466
4467 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
4468 unsigned index)
4469 {
4470 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4471 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
4472 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
4473 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
4474 ctx->src[index].neg || ctx->src[index].abs;
4475 }
4476
4477 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
4478 unsigned index)
4479 {
4480 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4481 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
4482 }
4483
4484 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
4485 {
4486 struct r600_bytecode_vtx vtx;
4487 struct r600_bytecode_alu alu;
4488 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4489 int src_gpr, r, i;
4490 int id = tgsi_tex_get_src_gpr(ctx, 1);
4491
4492 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4493 if (src_requires_loading) {
4494 for (i = 0; i < 4; i++) {
4495 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4496 alu.op = ALU_OP1_MOV;
4497 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4498 alu.dst.sel = ctx->temp_reg;
4499 alu.dst.chan = i;
4500 if (i == 3)
4501 alu.last = 1;
4502 alu.dst.write = 1;
4503 r = r600_bytecode_add_alu(ctx->bc, &alu);
4504 if (r)
4505 return r;
4506 }
4507 src_gpr = ctx->temp_reg;
4508 }
4509
4510 memset(&vtx, 0, sizeof(vtx));
4511 vtx.op = FETCH_OP_VFETCH;
4512 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
4513 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
4514 vtx.src_gpr = src_gpr;
4515 vtx.mega_fetch_count = 16;
4516 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4517 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
4518 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
4519 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
4520 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
4521 vtx.use_const_fields = 1;
4522
4523 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
4524 return r;
4525
4526 if (ctx->bc->chip_class >= EVERGREEN)
4527 return 0;
4528
4529 for (i = 0; i < 4; i++) {
4530 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4531 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4532 continue;
4533
4534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4535 alu.op = ALU_OP2_AND_INT;
4536
4537 alu.dst.chan = i;
4538 alu.dst.sel = vtx.dst_gpr;
4539 alu.dst.write = 1;
4540
4541 alu.src[0].sel = vtx.dst_gpr;
4542 alu.src[0].chan = i;
4543
4544 alu.src[1].sel = 512 + (id * 2);
4545 alu.src[1].chan = i % 4;
4546 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4547
4548 if (i == lasti)
4549 alu.last = 1;
4550 r = r600_bytecode_add_alu(ctx->bc, &alu);
4551 if (r)
4552 return r;
4553 }
4554
4555 if (inst->Dst[0].Register.WriteMask & 3) {
4556 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4557 alu.op = ALU_OP2_OR_INT;
4558
4559 alu.dst.chan = 3;
4560 alu.dst.sel = vtx.dst_gpr;
4561 alu.dst.write = 1;
4562
4563 alu.src[0].sel = vtx.dst_gpr;
4564 alu.src[0].chan = 3;
4565
4566 alu.src[1].sel = 512 + (id * 2) + 1;
4567 alu.src[1].chan = 0;
4568 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4569
4570 alu.last = 1;
4571 r = r600_bytecode_add_alu(ctx->bc, &alu);
4572 if (r)
4573 return r;
4574 }
4575 return 0;
4576 }
4577
4578 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
4579 {
4580 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4581 struct r600_bytecode_alu alu;
4582 int r;
4583 int id = tgsi_tex_get_src_gpr(ctx, 1);
4584
4585 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4586 alu.op = ALU_OP1_MOV;
4587
4588 if (ctx->bc->chip_class >= EVERGREEN) {
4589 alu.src[0].sel = 512 + (id / 4);
4590 alu.src[0].chan = id % 4;
4591 } else {
4592 /* r600 we have them at channel 2 of the second dword */
4593 alu.src[0].sel = 512 + (id * 2) + 1;
4594 alu.src[0].chan = 1;
4595 }
4596 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4597 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4598 alu.last = 1;
4599 r = r600_bytecode_add_alu(ctx->bc, &alu);
4600 if (r)
4601 return r;
4602 return 0;
4603 }
4604
4605 static int tgsi_tex(struct r600_shader_ctx *ctx)
4606 {
4607 static float one_point_five = 1.5f;
4608 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4609 struct r600_bytecode_tex tex;
4610 struct r600_bytecode_alu alu;
4611 unsigned src_gpr;
4612 int r, i, j;
4613 int opcode;
4614 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
4615 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4616 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
4617 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
4618
4619 bool txf_add_offsets = inst->Texture.NumOffsets &&
4620 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4621 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
4622
4623 /* Texture fetch instructions can only use gprs as source.
4624 * Also they cannot negate the source or take the absolute value */
4625 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
4626 tgsi_tex_src_requires_loading(ctx, 0)) ||
4627 read_compressed_msaa || txf_add_offsets;
4628
4629 boolean src_loaded = FALSE;
4630 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
4631 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
4632 boolean has_txq_cube_array_z = false;
4633
4634 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
4635 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4636 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
4637 if (inst->Dst[0].Register.WriteMask & 4) {
4638 ctx->shader->has_txq_cube_array_z_comp = true;
4639 has_txq_cube_array_z = true;
4640 }
4641
4642 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
4643 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4644 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
4645 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
4646 sampler_src_reg = 2;
4647
4648 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4649
4650 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
4651 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
4652 ctx->shader->uses_tex_buffers = true;
4653 return r600_do_buffer_txq(ctx);
4654 }
4655 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4656 if (ctx->bc->chip_class < EVERGREEN)
4657 ctx->shader->uses_tex_buffers = true;
4658 return do_vtx_fetch_inst(ctx, src_requires_loading);
4659 }
4660 }
4661
4662 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
4663 /* TGSI moves the sampler to src reg 3 for TXD */
4664 sampler_src_reg = 3;
4665
4666 for (i = 1; i < 3; i++) {
4667 /* set gradients h/v */
4668 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4669 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
4670 FETCH_OP_SET_GRADIENTS_V;
4671 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4672 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4673
4674 if (tgsi_tex_src_requires_loading(ctx, i)) {
4675 tex.src_gpr = r600_get_temp(ctx);
4676 tex.src_sel_x = 0;
4677 tex.src_sel_y = 1;
4678 tex.src_sel_z = 2;
4679 tex.src_sel_w = 3;
4680
4681 for (j = 0; j < 4; j++) {
4682 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4683 alu.op = ALU_OP1_MOV;
4684 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
4685 alu.dst.sel = tex.src_gpr;
4686 alu.dst.chan = j;
4687 if (j == 3)
4688 alu.last = 1;
4689 alu.dst.write = 1;
4690 r = r600_bytecode_add_alu(ctx->bc, &alu);
4691 if (r)
4692 return r;
4693 }
4694
4695 } else {
4696 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
4697 tex.src_sel_x = ctx->src[i].swizzle[0];
4698 tex.src_sel_y = ctx->src[i].swizzle[1];
4699 tex.src_sel_z = ctx->src[i].swizzle[2];
4700 tex.src_sel_w = ctx->src[i].swizzle[3];
4701 tex.src_rel = ctx->src[i].rel;
4702 }
4703 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
4704 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4705 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
4706 tex.coord_type_x = 1;
4707 tex.coord_type_y = 1;
4708 tex.coord_type_z = 1;
4709 tex.coord_type_w = 1;
4710 }
4711 r = r600_bytecode_add_tex(ctx->bc, &tex);
4712 if (r)
4713 return r;
4714 }
4715 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
4716 int out_chan;
4717 /* Add perspective divide */
4718 if (ctx->bc->chip_class == CAYMAN) {
4719 out_chan = 2;
4720 for (i = 0; i < 3; i++) {
4721 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4722 alu.op = ALU_OP1_RECIP_IEEE;
4723 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4724
4725 alu.dst.sel = ctx->temp_reg;
4726 alu.dst.chan = i;
4727 if (i == 2)
4728 alu.last = 1;
4729 if (out_chan == i)
4730 alu.dst.write = 1;
4731 r = r600_bytecode_add_alu(ctx->bc, &alu);
4732 if (r)
4733 return r;
4734 }
4735
4736 } else {
4737 out_chan = 3;
4738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4739 alu.op = ALU_OP1_RECIP_IEEE;
4740 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4741
4742 alu.dst.sel = ctx->temp_reg;
4743 alu.dst.chan = out_chan;
4744 alu.last = 1;
4745 alu.dst.write = 1;
4746 r = r600_bytecode_add_alu(ctx->bc, &alu);
4747 if (r)
4748 return r;
4749 }
4750
4751 for (i = 0; i < 3; i++) {
4752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4753 alu.op = ALU_OP2_MUL;
4754 alu.src[0].sel = ctx->temp_reg;
4755 alu.src[0].chan = out_chan;
4756 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4757 alu.dst.sel = ctx->temp_reg;
4758 alu.dst.chan = i;
4759 alu.dst.write = 1;
4760 r = r600_bytecode_add_alu(ctx->bc, &alu);
4761 if (r)
4762 return r;
4763 }
4764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4765 alu.op = ALU_OP1_MOV;
4766 alu.src[0].sel = V_SQ_ALU_SRC_1;
4767 alu.src[0].chan = 0;
4768 alu.dst.sel = ctx->temp_reg;
4769 alu.dst.chan = 3;
4770 alu.last = 1;
4771 alu.dst.write = 1;
4772 r = r600_bytecode_add_alu(ctx->bc, &alu);
4773 if (r)
4774 return r;
4775 src_loaded = TRUE;
4776 src_gpr = ctx->temp_reg;
4777 }
4778
4779 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4780 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4781 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4782 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4783 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
4784 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4785
4786 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
4787 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
4788
4789 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
4790 for (i = 0; i < 4; i++) {
4791 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4792 alu.op = ALU_OP2_CUBE;
4793 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4794 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4795 alu.dst.sel = ctx->temp_reg;
4796 alu.dst.chan = i;
4797 if (i == 3)
4798 alu.last = 1;
4799 alu.dst.write = 1;
4800 r = r600_bytecode_add_alu(ctx->bc, &alu);
4801 if (r)
4802 return r;
4803 }
4804
4805 /* tmp1.z = RCP_e(|tmp1.z|) */
4806 if (ctx->bc->chip_class == CAYMAN) {
4807 for (i = 0; i < 3; i++) {
4808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4809 alu.op = ALU_OP1_RECIP_IEEE;
4810 alu.src[0].sel = ctx->temp_reg;
4811 alu.src[0].chan = 2;
4812 alu.src[0].abs = 1;
4813 alu.dst.sel = ctx->temp_reg;
4814 alu.dst.chan = i;
4815 if (i == 2)
4816 alu.dst.write = 1;
4817 if (i == 2)
4818 alu.last = 1;
4819 r = r600_bytecode_add_alu(ctx->bc, &alu);
4820 if (r)
4821 return r;
4822 }
4823 } else {
4824 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4825 alu.op = ALU_OP1_RECIP_IEEE;
4826 alu.src[0].sel = ctx->temp_reg;
4827 alu.src[0].chan = 2;
4828 alu.src[0].abs = 1;
4829 alu.dst.sel = ctx->temp_reg;
4830 alu.dst.chan = 2;
4831 alu.dst.write = 1;
4832 alu.last = 1;
4833 r = r600_bytecode_add_alu(ctx->bc, &alu);
4834 if (r)
4835 return r;
4836 }
4837
4838 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4839 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4840 * muladd has no writemask, have to use another temp
4841 */
4842 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4843 alu.op = ALU_OP3_MULADD;
4844 alu.is_op3 = 1;
4845
4846 alu.src[0].sel = ctx->temp_reg;
4847 alu.src[0].chan = 0;
4848 alu.src[1].sel = ctx->temp_reg;
4849 alu.src[1].chan = 2;
4850
4851 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4852 alu.src[2].chan = 0;
4853 alu.src[2].value = *(uint32_t *)&one_point_five;
4854
4855 alu.dst.sel = ctx->temp_reg;
4856 alu.dst.chan = 0;
4857 alu.dst.write = 1;
4858
4859 r = r600_bytecode_add_alu(ctx->bc, &alu);
4860 if (r)
4861 return r;
4862
4863 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4864 alu.op = ALU_OP3_MULADD;
4865 alu.is_op3 = 1;
4866
4867 alu.src[0].sel = ctx->temp_reg;
4868 alu.src[0].chan = 1;
4869 alu.src[1].sel = ctx->temp_reg;
4870 alu.src[1].chan = 2;
4871
4872 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4873 alu.src[2].chan = 0;
4874 alu.src[2].value = *(uint32_t *)&one_point_five;
4875
4876 alu.dst.sel = ctx->temp_reg;
4877 alu.dst.chan = 1;
4878 alu.dst.write = 1;
4879
4880 alu.last = 1;
4881 r = r600_bytecode_add_alu(ctx->bc, &alu);
4882 if (r)
4883 return r;
4884 /* write initial compare value into Z component
4885 - W src 0 for shadow cube
4886 - X src 1 for shadow cube array */
4887 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4888 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4890 alu.op = ALU_OP1_MOV;
4891 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4892 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4893 else
4894 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4895 alu.dst.sel = ctx->temp_reg;
4896 alu.dst.chan = 2;
4897 alu.dst.write = 1;
4898 alu.last = 1;
4899 r = r600_bytecode_add_alu(ctx->bc, &alu);
4900 if (r)
4901 return r;
4902 }
4903
4904 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4905 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4906 if (ctx->bc->chip_class >= EVERGREEN) {
4907 int mytmp = r600_get_temp(ctx);
4908 static const float eight = 8.0f;
4909 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4910 alu.op = ALU_OP1_MOV;
4911 alu.src[0].sel = ctx->temp_reg;
4912 alu.src[0].chan = 3;
4913 alu.dst.sel = mytmp;
4914 alu.dst.chan = 0;
4915 alu.dst.write = 1;
4916 alu.last = 1;
4917 r = r600_bytecode_add_alu(ctx->bc, &alu);
4918 if (r)
4919 return r;
4920
4921 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4922 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4923 alu.op = ALU_OP3_MULADD;
4924 alu.is_op3 = 1;
4925 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4926 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4927 alu.src[1].chan = 0;
4928 alu.src[1].value = *(uint32_t *)&eight;
4929 alu.src[2].sel = mytmp;
4930 alu.src[2].chan = 0;
4931 alu.dst.sel = ctx->temp_reg;
4932 alu.dst.chan = 3;
4933 alu.dst.write = 1;
4934 alu.last = 1;
4935 r = r600_bytecode_add_alu(ctx->bc, &alu);
4936 if (r)
4937 return r;
4938 } else if (ctx->bc->chip_class < EVERGREEN) {
4939 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4940 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4941 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4942 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4943 tex.src_gpr = r600_get_temp(ctx);
4944 tex.src_sel_x = 0;
4945 tex.src_sel_y = 0;
4946 tex.src_sel_z = 0;
4947 tex.src_sel_w = 0;
4948 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4949 tex.coord_type_x = 1;
4950 tex.coord_type_y = 1;
4951 tex.coord_type_z = 1;
4952 tex.coord_type_w = 1;
4953 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4954 alu.op = ALU_OP1_MOV;
4955 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4956 alu.dst.sel = tex.src_gpr;
4957 alu.dst.chan = 0;
4958 alu.last = 1;
4959 alu.dst.write = 1;
4960 r = r600_bytecode_add_alu(ctx->bc, &alu);
4961 if (r)
4962 return r;
4963
4964 r = r600_bytecode_add_tex(ctx->bc, &tex);
4965 if (r)
4966 return r;
4967 }
4968
4969 }
4970
4971 /* for cube forms of lod and bias we need to route things */
4972 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4973 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4974 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4975 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4977 alu.op = ALU_OP1_MOV;
4978 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4979 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4980 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4981 else
4982 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4983 alu.dst.sel = ctx->temp_reg;
4984 alu.dst.chan = 2;
4985 alu.last = 1;
4986 alu.dst.write = 1;
4987 r = r600_bytecode_add_alu(ctx->bc, &alu);
4988 if (r)
4989 return r;
4990 }
4991
4992 src_loaded = TRUE;
4993 src_gpr = ctx->temp_reg;
4994 }
4995
4996 if (src_requires_loading && !src_loaded) {
4997 for (i = 0; i < 4; i++) {
4998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4999 alu.op = ALU_OP1_MOV;
5000 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5001 alu.dst.sel = ctx->temp_reg;
5002 alu.dst.chan = i;
5003 if (i == 3)
5004 alu.last = 1;
5005 alu.dst.write = 1;
5006 r = r600_bytecode_add_alu(ctx->bc, &alu);
5007 if (r)
5008 return r;
5009 }
5010 src_loaded = TRUE;
5011 src_gpr = ctx->temp_reg;
5012 }
5013
5014 /* get offset values */
5015 if (inst->Texture.NumOffsets) {
5016 assert(inst->Texture.NumOffsets == 1);
5017
5018 /* The texture offset feature doesn't work with the TXF instruction
5019 * and must be emulated by adding the offset to the texture coordinates. */
5020 if (txf_add_offsets) {
5021 const struct tgsi_texture_offset *off = inst->TexOffsets;
5022
5023 switch (inst->Texture.Texture) {
5024 case TGSI_TEXTURE_3D:
5025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5026 alu.op = ALU_OP2_ADD_INT;
5027 alu.src[0].sel = src_gpr;
5028 alu.src[0].chan = 2;
5029 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5030 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
5031 alu.dst.sel = src_gpr;
5032 alu.dst.chan = 2;
5033 alu.dst.write = 1;
5034 alu.last = 1;
5035 r = r600_bytecode_add_alu(ctx->bc, &alu);
5036 if (r)
5037 return r;
5038 /* fall through */
5039
5040 case TGSI_TEXTURE_2D:
5041 case TGSI_TEXTURE_SHADOW2D:
5042 case TGSI_TEXTURE_RECT:
5043 case TGSI_TEXTURE_SHADOWRECT:
5044 case TGSI_TEXTURE_2D_ARRAY:
5045 case TGSI_TEXTURE_SHADOW2D_ARRAY:
5046 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5047 alu.op = ALU_OP2_ADD_INT;
5048 alu.src[0].sel = src_gpr;
5049 alu.src[0].chan = 1;
5050 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5051 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
5052 alu.dst.sel = src_gpr;
5053 alu.dst.chan = 1;
5054 alu.dst.write = 1;
5055 alu.last = 1;
5056 r = r600_bytecode_add_alu(ctx->bc, &alu);
5057 if (r)
5058 return r;
5059 /* fall through */
5060
5061 case TGSI_TEXTURE_1D:
5062 case TGSI_TEXTURE_SHADOW1D:
5063 case TGSI_TEXTURE_1D_ARRAY:
5064 case TGSI_TEXTURE_SHADOW1D_ARRAY:
5065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5066 alu.op = ALU_OP2_ADD_INT;
5067 alu.src[0].sel = src_gpr;
5068 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5069 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
5070 alu.dst.sel = src_gpr;
5071 alu.dst.write = 1;
5072 alu.last = 1;
5073 r = r600_bytecode_add_alu(ctx->bc, &alu);
5074 if (r)
5075 return r;
5076 break;
5077 /* texture offsets do not apply to other texture targets */
5078 }
5079 } else {
5080 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
5081 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
5082 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
5083 }
5084 }
5085
5086 /* Obtain the sample index for reading a compressed MSAA color texture.
5087 * To read the FMASK, we use the ldfptr instruction, which tells us
5088 * where the samples are stored.
5089 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
5090 * which is the identity mapping. Each nibble says which physical sample
5091 * should be fetched to get that sample.
5092 *
5093 * Assume src.z contains the sample index. It should be modified like this:
5094 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
5095 * Then fetch the texel with src.
5096 */
5097 if (read_compressed_msaa) {
5098 unsigned sample_chan = 3;
5099 unsigned temp = r600_get_temp(ctx);
5100 assert(src_loaded);
5101
5102 /* temp.w = ldfptr() */
5103 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5104 tex.op = FETCH_OP_LD;
5105 tex.inst_mod = 1; /* to indicate this is ldfptr */
5106 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5107 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5108 tex.src_gpr = src_gpr;
5109 tex.dst_gpr = temp;
5110 tex.dst_sel_x = 7; /* mask out these components */
5111 tex.dst_sel_y = 7;
5112 tex.dst_sel_z = 7;
5113 tex.dst_sel_w = 0; /* store X */
5114 tex.src_sel_x = 0;
5115 tex.src_sel_y = 1;
5116 tex.src_sel_z = 2;
5117 tex.src_sel_w = 3;
5118 tex.offset_x = offset_x;
5119 tex.offset_y = offset_y;
5120 tex.offset_z = offset_z;
5121 r = r600_bytecode_add_tex(ctx->bc, &tex);
5122 if (r)
5123 return r;
5124
5125 /* temp.x = sample_index*4 */
5126 if (ctx->bc->chip_class == CAYMAN) {
5127 for (i = 0 ; i < 4; i++) {
5128 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5129 alu.op = ALU_OP2_MULLO_INT;
5130 alu.src[0].sel = src_gpr;
5131 alu.src[0].chan = sample_chan;
5132 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5133 alu.src[1].value = 4;
5134 alu.dst.sel = temp;
5135 alu.dst.chan = i;
5136 alu.dst.write = i == 0;
5137 if (i == 3)
5138 alu.last = 1;
5139 r = r600_bytecode_add_alu(ctx->bc, &alu);
5140 if (r)
5141 return r;
5142 }
5143 } else {
5144 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5145 alu.op = ALU_OP2_MULLO_INT;
5146 alu.src[0].sel = src_gpr;
5147 alu.src[0].chan = sample_chan;
5148 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5149 alu.src[1].value = 4;
5150 alu.dst.sel = temp;
5151 alu.dst.chan = 0;
5152 alu.dst.write = 1;
5153 alu.last = 1;
5154 r = r600_bytecode_add_alu(ctx->bc, &alu);
5155 if (r)
5156 return r;
5157 }
5158
5159 /* sample_index = temp.w >> temp.x */
5160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5161 alu.op = ALU_OP2_LSHR_INT;
5162 alu.src[0].sel = temp;
5163 alu.src[0].chan = 3;
5164 alu.src[1].sel = temp;
5165 alu.src[1].chan = 0;
5166 alu.dst.sel = src_gpr;
5167 alu.dst.chan = sample_chan;
5168 alu.dst.write = 1;
5169 alu.last = 1;
5170 r = r600_bytecode_add_alu(ctx->bc, &alu);
5171 if (r)
5172 return r;
5173
5174 /* sample_index & 0xF */
5175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5176 alu.op = ALU_OP2_AND_INT;
5177 alu.src[0].sel = src_gpr;
5178 alu.src[0].chan = sample_chan;
5179 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5180 alu.src[1].value = 0xF;
5181 alu.dst.sel = src_gpr;
5182 alu.dst.chan = sample_chan;
5183 alu.dst.write = 1;
5184 alu.last = 1;
5185 r = r600_bytecode_add_alu(ctx->bc, &alu);
5186 if (r)
5187 return r;
5188 #if 0
5189 /* visualize the FMASK */
5190 for (i = 0; i < 4; i++) {
5191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5192 alu.op = ALU_OP1_INT_TO_FLT;
5193 alu.src[0].sel = src_gpr;
5194 alu.src[0].chan = sample_chan;
5195 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5196 alu.dst.chan = i;
5197 alu.dst.write = 1;
5198 alu.last = 1;
5199 r = r600_bytecode_add_alu(ctx->bc, &alu);
5200 if (r)
5201 return r;
5202 }
5203 return 0;
5204 #endif
5205 }
5206
5207 /* does this shader want a num layers from TXQ for a cube array? */
5208 if (has_txq_cube_array_z) {
5209 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5210
5211 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5212 alu.op = ALU_OP1_MOV;
5213
5214 alu.src[0].sel = 512 + (id / 4);
5215 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
5216 alu.src[0].chan = id % 4;
5217 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5218 alu.last = 1;
5219 r = r600_bytecode_add_alu(ctx->bc, &alu);
5220 if (r)
5221 return r;
5222 /* disable writemask from texture instruction */
5223 inst->Dst[0].Register.WriteMask &= ~4;
5224 }
5225
5226 opcode = ctx->inst_info->op;
5227 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
5228 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
5229 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
5230 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5231 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
5232 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
5233 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5234 switch (opcode) {
5235 case FETCH_OP_SAMPLE:
5236 opcode = FETCH_OP_SAMPLE_C;
5237 break;
5238 case FETCH_OP_SAMPLE_L:
5239 opcode = FETCH_OP_SAMPLE_C_L;
5240 break;
5241 case FETCH_OP_SAMPLE_LB:
5242 opcode = FETCH_OP_SAMPLE_C_LB;
5243 break;
5244 case FETCH_OP_SAMPLE_G:
5245 opcode = FETCH_OP_SAMPLE_C_G;
5246 break;
5247 /* Texture gather variants */
5248 case FETCH_OP_GATHER4:
5249 tex.op = FETCH_OP_GATHER4_C;
5250 break;
5251 case FETCH_OP_GATHER4_O:
5252 tex.op = FETCH_OP_GATHER4_C_O;
5253 break;
5254 }
5255 }
5256
5257 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5258 tex.op = opcode;
5259
5260 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5261 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5262 tex.src_gpr = src_gpr;
5263 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5264
5265 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
5266 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
5267 tex.inst_mod = texture_component_select;
5268
5269 /* GATHER4 result order is different from TGSI TG4 */
5270 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5271 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
5272 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5273 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
5274 }
5275 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
5276 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5277 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5278 tex.dst_sel_z = 7;
5279 tex.dst_sel_w = 7;
5280 }
5281 else {
5282 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5283 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5284 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
5285 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
5286 }
5287
5288
5289 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
5290 tex.src_sel_x = 4;
5291 tex.src_sel_y = 4;
5292 tex.src_sel_z = 4;
5293 tex.src_sel_w = 4;
5294 } else if (src_loaded) {
5295 tex.src_sel_x = 0;
5296 tex.src_sel_y = 1;
5297 tex.src_sel_z = 2;
5298 tex.src_sel_w = 3;
5299 } else {
5300 tex.src_sel_x = ctx->src[0].swizzle[0];
5301 tex.src_sel_y = ctx->src[0].swizzle[1];
5302 tex.src_sel_z = ctx->src[0].swizzle[2];
5303 tex.src_sel_w = ctx->src[0].swizzle[3];
5304 tex.src_rel = ctx->src[0].rel;
5305 }
5306
5307 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5308 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5309 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5310 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5311 tex.src_sel_x = 1;
5312 tex.src_sel_y = 0;
5313 tex.src_sel_z = 3;
5314 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
5315 }
5316
5317 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
5318 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
5319 tex.coord_type_x = 1;
5320 tex.coord_type_y = 1;
5321 }
5322 tex.coord_type_z = 1;
5323 tex.coord_type_w = 1;
5324
5325 tex.offset_x = offset_x;
5326 tex.offset_y = offset_y;
5327 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
5328 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY) {
5329 tex.offset_z = 0;
5330 }
5331 else {
5332 tex.offset_z = offset_z;
5333 }
5334
5335 /* Put the depth for comparison in W.
5336 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
5337 * Some instructions expect the depth in Z. */
5338 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
5339 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
5340 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
5341 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
5342 opcode != FETCH_OP_SAMPLE_C_L &&
5343 opcode != FETCH_OP_SAMPLE_C_LB) {
5344 tex.src_sel_w = tex.src_sel_z;
5345 }
5346
5347 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
5348 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
5349 if (opcode == FETCH_OP_SAMPLE_C_L ||
5350 opcode == FETCH_OP_SAMPLE_C_LB) {
5351 /* the array index is read from Y */
5352 tex.coord_type_y = 0;
5353 } else {
5354 /* the array index is read from Z */
5355 tex.coord_type_z = 0;
5356 tex.src_sel_z = tex.src_sel_y;
5357 }
5358 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
5359 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
5360 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5361 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5362 (ctx->bc->chip_class >= EVERGREEN)))
5363 /* the array index is read from Z */
5364 tex.coord_type_z = 0;
5365
5366 /* mask unused source components */
5367 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
5368 switch (inst->Texture.Texture) {
5369 case TGSI_TEXTURE_2D:
5370 case TGSI_TEXTURE_RECT:
5371 tex.src_sel_z = 7;
5372 tex.src_sel_w = 7;
5373 break;
5374 case TGSI_TEXTURE_1D_ARRAY:
5375 tex.src_sel_y = 7;
5376 tex.src_sel_w = 7;
5377 break;
5378 case TGSI_TEXTURE_1D:
5379 tex.src_sel_y = 7;
5380 tex.src_sel_z = 7;
5381 tex.src_sel_w = 7;
5382 break;
5383 }
5384 }
5385
5386 r = r600_bytecode_add_tex(ctx->bc, &tex);
5387 if (r)
5388 return r;
5389
5390 /* add shadow ambient support - gallium doesn't do it yet */
5391 return 0;
5392 }
5393
5394 static int tgsi_lrp(struct r600_shader_ctx *ctx)
5395 {
5396 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5397 struct r600_bytecode_alu alu;
5398 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5399 unsigned i;
5400 int r;
5401
5402 /* optimize if it's just an equal balance */
5403 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
5404 for (i = 0; i < lasti + 1; i++) {
5405 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5406 continue;
5407
5408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5409 alu.op = ALU_OP2_ADD;
5410 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5411 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5412 alu.omod = 3;
5413 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5414 alu.dst.chan = i;
5415 if (i == lasti) {
5416 alu.last = 1;
5417 }
5418 r = r600_bytecode_add_alu(ctx->bc, &alu);
5419 if (r)
5420 return r;
5421 }
5422 return 0;
5423 }
5424
5425 /* 1 - src0 */
5426 for (i = 0; i < lasti + 1; i++) {
5427 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5428 continue;
5429
5430 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5431 alu.op = ALU_OP2_ADD;
5432 alu.src[0].sel = V_SQ_ALU_SRC_1;
5433 alu.src[0].chan = 0;
5434 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5435 r600_bytecode_src_toggle_neg(&alu.src[1]);
5436 alu.dst.sel = ctx->temp_reg;
5437 alu.dst.chan = i;
5438 if (i == lasti) {
5439 alu.last = 1;
5440 }
5441 alu.dst.write = 1;
5442 r = r600_bytecode_add_alu(ctx->bc, &alu);
5443 if (r)
5444 return r;
5445 }
5446
5447 /* (1 - src0) * src2 */
5448 for (i = 0; i < lasti + 1; i++) {
5449 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5450 continue;
5451
5452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5453 alu.op = ALU_OP2_MUL;
5454 alu.src[0].sel = ctx->temp_reg;
5455 alu.src[0].chan = i;
5456 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5457 alu.dst.sel = ctx->temp_reg;
5458 alu.dst.chan = i;
5459 if (i == lasti) {
5460 alu.last = 1;
5461 }
5462 alu.dst.write = 1;
5463 r = r600_bytecode_add_alu(ctx->bc, &alu);
5464 if (r)
5465 return r;
5466 }
5467
5468 /* src0 * src1 + (1 - src0) * src2 */
5469 for (i = 0; i < lasti + 1; i++) {
5470 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5471 continue;
5472
5473 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5474 alu.op = ALU_OP3_MULADD;
5475 alu.is_op3 = 1;
5476 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5477 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5478 alu.src[2].sel = ctx->temp_reg;
5479 alu.src[2].chan = i;
5480
5481 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5482 alu.dst.chan = i;
5483 if (i == lasti) {
5484 alu.last = 1;
5485 }
5486 r = r600_bytecode_add_alu(ctx->bc, &alu);
5487 if (r)
5488 return r;
5489 }
5490 return 0;
5491 }
5492
5493 static int tgsi_cmp(struct r600_shader_ctx *ctx)
5494 {
5495 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5496 struct r600_bytecode_alu alu;
5497 int i, r;
5498 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5499
5500 for (i = 0; i < lasti + 1; i++) {
5501 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5502 continue;
5503
5504 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5505 alu.op = ALU_OP3_CNDGE;
5506 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5507 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5508 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
5509 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5510 alu.dst.chan = i;
5511 alu.dst.write = 1;
5512 alu.is_op3 = 1;
5513 if (i == lasti)
5514 alu.last = 1;
5515 r = r600_bytecode_add_alu(ctx->bc, &alu);
5516 if (r)
5517 return r;
5518 }
5519 return 0;
5520 }
5521
5522 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
5523 {
5524 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5525 struct r600_bytecode_alu alu;
5526 int i, r;
5527 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5528
5529 for (i = 0; i < lasti + 1; i++) {
5530 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5531 continue;
5532
5533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5534 alu.op = ALU_OP3_CNDGE_INT;
5535 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5536 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5537 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
5538 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5539 alu.dst.chan = i;
5540 alu.dst.write = 1;
5541 alu.is_op3 = 1;
5542 if (i == lasti)
5543 alu.last = 1;
5544 r = r600_bytecode_add_alu(ctx->bc, &alu);
5545 if (r)
5546 return r;
5547 }
5548 return 0;
5549 }
5550
5551 static int tgsi_xpd(struct r600_shader_ctx *ctx)
5552 {
5553 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5554 static const unsigned int src0_swizzle[] = {2, 0, 1};
5555 static const unsigned int src1_swizzle[] = {1, 2, 0};
5556 struct r600_bytecode_alu alu;
5557 uint32_t use_temp = 0;
5558 int i, r;
5559
5560 if (inst->Dst[0].Register.WriteMask != 0xf)
5561 use_temp = 1;
5562
5563 for (i = 0; i < 4; i++) {
5564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5565 alu.op = ALU_OP2_MUL;
5566 if (i < 3) {
5567 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5568 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
5569 } else {
5570 alu.src[0].sel = V_SQ_ALU_SRC_0;
5571 alu.src[0].chan = i;
5572 alu.src[1].sel = V_SQ_ALU_SRC_0;
5573 alu.src[1].chan = i;
5574 }
5575
5576 alu.dst.sel = ctx->temp_reg;
5577 alu.dst.chan = i;
5578 alu.dst.write = 1;
5579
5580 if (i == 3)
5581 alu.last = 1;
5582 r = r600_bytecode_add_alu(ctx->bc, &alu);
5583 if (r)
5584 return r;
5585 }
5586
5587 for (i = 0; i < 4; i++) {
5588 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5589 alu.op = ALU_OP3_MULADD;
5590
5591 if (i < 3) {
5592 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
5593 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
5594 } else {
5595 alu.src[0].sel = V_SQ_ALU_SRC_0;
5596 alu.src[0].chan = i;
5597 alu.src[1].sel = V_SQ_ALU_SRC_0;
5598 alu.src[1].chan = i;
5599 }
5600
5601 alu.src[2].sel = ctx->temp_reg;
5602 alu.src[2].neg = 1;
5603 alu.src[2].chan = i;
5604
5605 if (use_temp)
5606 alu.dst.sel = ctx->temp_reg;
5607 else
5608 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5609 alu.dst.chan = i;
5610 alu.dst.write = 1;
5611 alu.is_op3 = 1;
5612 if (i == 3)
5613 alu.last = 1;
5614 r = r600_bytecode_add_alu(ctx->bc, &alu);
5615 if (r)
5616 return r;
5617 }
5618 if (use_temp)
5619 return tgsi_helper_copy(ctx, inst);
5620 return 0;
5621 }
5622
5623 static int tgsi_exp(struct r600_shader_ctx *ctx)
5624 {
5625 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5626 struct r600_bytecode_alu alu;
5627 int r;
5628 int i;
5629
5630 /* result.x = 2^floor(src); */
5631 if (inst->Dst[0].Register.WriteMask & 1) {
5632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5633
5634 alu.op = ALU_OP1_FLOOR;
5635 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5636
5637 alu.dst.sel = ctx->temp_reg;
5638 alu.dst.chan = 0;
5639 alu.dst.write = 1;
5640 alu.last = 1;
5641 r = r600_bytecode_add_alu(ctx->bc, &alu);
5642 if (r)
5643 return r;
5644
5645 if (ctx->bc->chip_class == CAYMAN) {
5646 for (i = 0; i < 3; i++) {
5647 alu.op = ALU_OP1_EXP_IEEE;
5648 alu.src[0].sel = ctx->temp_reg;
5649 alu.src[0].chan = 0;
5650
5651 alu.dst.sel = ctx->temp_reg;
5652 alu.dst.chan = i;
5653 alu.dst.write = i == 0;
5654 alu.last = i == 2;
5655 r = r600_bytecode_add_alu(ctx->bc, &alu);
5656 if (r)
5657 return r;
5658 }
5659 } else {
5660 alu.op = ALU_OP1_EXP_IEEE;
5661 alu.src[0].sel = ctx->temp_reg;
5662 alu.src[0].chan = 0;
5663
5664 alu.dst.sel = ctx->temp_reg;
5665 alu.dst.chan = 0;
5666 alu.dst.write = 1;
5667 alu.last = 1;
5668 r = r600_bytecode_add_alu(ctx->bc, &alu);
5669 if (r)
5670 return r;
5671 }
5672 }
5673
5674 /* result.y = tmp - floor(tmp); */
5675 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5677
5678 alu.op = ALU_OP1_FRACT;
5679 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5680
5681 alu.dst.sel = ctx->temp_reg;
5682 #if 0
5683 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5684 if (r)
5685 return r;
5686 #endif
5687 alu.dst.write = 1;
5688 alu.dst.chan = 1;
5689
5690 alu.last = 1;
5691
5692 r = r600_bytecode_add_alu(ctx->bc, &alu);
5693 if (r)
5694 return r;
5695 }
5696
5697 /* result.z = RoughApprox2ToX(tmp);*/
5698 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
5699 if (ctx->bc->chip_class == CAYMAN) {
5700 for (i = 0; i < 3; i++) {
5701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5702 alu.op = ALU_OP1_EXP_IEEE;
5703 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5704
5705 alu.dst.sel = ctx->temp_reg;
5706 alu.dst.chan = i;
5707 if (i == 2) {
5708 alu.dst.write = 1;
5709 alu.last = 1;
5710 }
5711
5712 r = r600_bytecode_add_alu(ctx->bc, &alu);
5713 if (r)
5714 return r;
5715 }
5716 } else {
5717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5718 alu.op = ALU_OP1_EXP_IEEE;
5719 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5720
5721 alu.dst.sel = ctx->temp_reg;
5722 alu.dst.write = 1;
5723 alu.dst.chan = 2;
5724
5725 alu.last = 1;
5726
5727 r = r600_bytecode_add_alu(ctx->bc, &alu);
5728 if (r)
5729 return r;
5730 }
5731 }
5732
5733 /* result.w = 1.0;*/
5734 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
5735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5736
5737 alu.op = ALU_OP1_MOV;
5738 alu.src[0].sel = V_SQ_ALU_SRC_1;
5739 alu.src[0].chan = 0;
5740
5741 alu.dst.sel = ctx->temp_reg;
5742 alu.dst.chan = 3;
5743 alu.dst.write = 1;
5744 alu.last = 1;
5745 r = r600_bytecode_add_alu(ctx->bc, &alu);
5746 if (r)
5747 return r;
5748 }
5749 return tgsi_helper_copy(ctx, inst);
5750 }
5751
5752 static int tgsi_log(struct r600_shader_ctx *ctx)
5753 {
5754 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5755 struct r600_bytecode_alu alu;
5756 int r;
5757 int i;
5758
5759 /* result.x = floor(log2(|src|)); */
5760 if (inst->Dst[0].Register.WriteMask & 1) {
5761 if (ctx->bc->chip_class == CAYMAN) {
5762 for (i = 0; i < 3; i++) {
5763 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5764
5765 alu.op = ALU_OP1_LOG_IEEE;
5766 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5767 r600_bytecode_src_set_abs(&alu.src[0]);
5768
5769 alu.dst.sel = ctx->temp_reg;
5770 alu.dst.chan = i;
5771 if (i == 0)
5772 alu.dst.write = 1;
5773 if (i == 2)
5774 alu.last = 1;
5775 r = r600_bytecode_add_alu(ctx->bc, &alu);
5776 if (r)
5777 return r;
5778 }
5779
5780 } else {
5781 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5782
5783 alu.op = ALU_OP1_LOG_IEEE;
5784 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5785 r600_bytecode_src_set_abs(&alu.src[0]);
5786
5787 alu.dst.sel = ctx->temp_reg;
5788 alu.dst.chan = 0;
5789 alu.dst.write = 1;
5790 alu.last = 1;
5791 r = r600_bytecode_add_alu(ctx->bc, &alu);
5792 if (r)
5793 return r;
5794 }
5795
5796 alu.op = ALU_OP1_FLOOR;
5797 alu.src[0].sel = ctx->temp_reg;
5798 alu.src[0].chan = 0;
5799
5800 alu.dst.sel = ctx->temp_reg;
5801 alu.dst.chan = 0;
5802 alu.dst.write = 1;
5803 alu.last = 1;
5804
5805 r = r600_bytecode_add_alu(ctx->bc, &alu);
5806 if (r)
5807 return r;
5808 }
5809
5810 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
5811 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5812
5813 if (ctx->bc->chip_class == CAYMAN) {
5814 for (i = 0; i < 3; i++) {
5815 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5816
5817 alu.op = ALU_OP1_LOG_IEEE;
5818 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5819 r600_bytecode_src_set_abs(&alu.src[0]);
5820
5821 alu.dst.sel = ctx->temp_reg;
5822 alu.dst.chan = i;
5823 if (i == 1)
5824 alu.dst.write = 1;
5825 if (i == 2)
5826 alu.last = 1;
5827
5828 r = r600_bytecode_add_alu(ctx->bc, &alu);
5829 if (r)
5830 return r;
5831 }
5832 } else {
5833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5834
5835 alu.op = ALU_OP1_LOG_IEEE;
5836 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5837 r600_bytecode_src_set_abs(&alu.src[0]);
5838
5839 alu.dst.sel = ctx->temp_reg;
5840 alu.dst.chan = 1;
5841 alu.dst.write = 1;
5842 alu.last = 1;
5843
5844 r = r600_bytecode_add_alu(ctx->bc, &alu);
5845 if (r)
5846 return r;
5847 }
5848
5849 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5850
5851 alu.op = ALU_OP1_FLOOR;
5852 alu.src[0].sel = ctx->temp_reg;
5853 alu.src[0].chan = 1;
5854
5855 alu.dst.sel = ctx->temp_reg;
5856 alu.dst.chan = 1;
5857 alu.dst.write = 1;
5858 alu.last = 1;
5859
5860 r = r600_bytecode_add_alu(ctx->bc, &alu);
5861 if (r)
5862 return r;
5863
5864 if (ctx->bc->chip_class == CAYMAN) {
5865 for (i = 0; i < 3; i++) {
5866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5867 alu.op = ALU_OP1_EXP_IEEE;
5868 alu.src[0].sel = ctx->temp_reg;
5869 alu.src[0].chan = 1;
5870
5871 alu.dst.sel = ctx->temp_reg;
5872 alu.dst.chan = i;
5873 if (i == 1)
5874 alu.dst.write = 1;
5875 if (i == 2)
5876 alu.last = 1;
5877
5878 r = r600_bytecode_add_alu(ctx->bc, &alu);
5879 if (r)
5880 return r;
5881 }
5882 } else {
5883 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5884 alu.op = ALU_OP1_EXP_IEEE;
5885 alu.src[0].sel = ctx->temp_reg;
5886 alu.src[0].chan = 1;
5887
5888 alu.dst.sel = ctx->temp_reg;
5889 alu.dst.chan = 1;
5890 alu.dst.write = 1;
5891 alu.last = 1;
5892
5893 r = r600_bytecode_add_alu(ctx->bc, &alu);
5894 if (r)
5895 return r;
5896 }
5897
5898 if (ctx->bc->chip_class == CAYMAN) {
5899 for (i = 0; i < 3; i++) {
5900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5901 alu.op = ALU_OP1_RECIP_IEEE;
5902 alu.src[0].sel = ctx->temp_reg;
5903 alu.src[0].chan = 1;
5904
5905 alu.dst.sel = ctx->temp_reg;
5906 alu.dst.chan = i;
5907 if (i == 1)
5908 alu.dst.write = 1;
5909 if (i == 2)
5910 alu.last = 1;
5911
5912 r = r600_bytecode_add_alu(ctx->bc, &alu);
5913 if (r)
5914 return r;
5915 }
5916 } else {
5917 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5918 alu.op = ALU_OP1_RECIP_IEEE;
5919 alu.src[0].sel = ctx->temp_reg;
5920 alu.src[0].chan = 1;
5921
5922 alu.dst.sel = ctx->temp_reg;
5923 alu.dst.chan = 1;
5924 alu.dst.write = 1;
5925 alu.last = 1;
5926
5927 r = r600_bytecode_add_alu(ctx->bc, &alu);
5928 if (r)
5929 return r;
5930 }
5931
5932 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5933
5934 alu.op = ALU_OP2_MUL;
5935
5936 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5937 r600_bytecode_src_set_abs(&alu.src[0]);
5938
5939 alu.src[1].sel = ctx->temp_reg;
5940 alu.src[1].chan = 1;
5941
5942 alu.dst.sel = ctx->temp_reg;
5943 alu.dst.chan = 1;
5944 alu.dst.write = 1;
5945 alu.last = 1;
5946
5947 r = r600_bytecode_add_alu(ctx->bc, &alu);
5948 if (r)
5949 return r;
5950 }
5951
5952 /* result.z = log2(|src|);*/
5953 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5954 if (ctx->bc->chip_class == CAYMAN) {
5955 for (i = 0; i < 3; i++) {
5956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5957
5958 alu.op = ALU_OP1_LOG_IEEE;
5959 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5960 r600_bytecode_src_set_abs(&alu.src[0]);
5961
5962 alu.dst.sel = ctx->temp_reg;
5963 if (i == 2)
5964 alu.dst.write = 1;
5965 alu.dst.chan = i;
5966 if (i == 2)
5967 alu.last = 1;
5968
5969 r = r600_bytecode_add_alu(ctx->bc, &alu);
5970 if (r)
5971 return r;
5972 }
5973 } else {
5974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5975
5976 alu.op = ALU_OP1_LOG_IEEE;
5977 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5978 r600_bytecode_src_set_abs(&alu.src[0]);
5979
5980 alu.dst.sel = ctx->temp_reg;
5981 alu.dst.write = 1;
5982 alu.dst.chan = 2;
5983 alu.last = 1;
5984
5985 r = r600_bytecode_add_alu(ctx->bc, &alu);
5986 if (r)
5987 return r;
5988 }
5989 }
5990
5991 /* result.w = 1.0; */
5992 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5994
5995 alu.op = ALU_OP1_MOV;
5996 alu.src[0].sel = V_SQ_ALU_SRC_1;
5997 alu.src[0].chan = 0;
5998
5999 alu.dst.sel = ctx->temp_reg;
6000 alu.dst.chan = 3;
6001 alu.dst.write = 1;
6002 alu.last = 1;
6003
6004 r = r600_bytecode_add_alu(ctx->bc, &alu);
6005 if (r)
6006 return r;
6007 }
6008
6009 return tgsi_helper_copy(ctx, inst);
6010 }
6011
6012 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
6013 {
6014 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6015 struct r600_bytecode_alu alu;
6016 int r;
6017 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6018
6019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6020
6021 switch (inst->Instruction.Opcode) {
6022 case TGSI_OPCODE_ARL:
6023 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
6024 break;
6025 case TGSI_OPCODE_ARR:
6026 alu.op = ALU_OP1_FLT_TO_INT;
6027 break;
6028 case TGSI_OPCODE_UARL:
6029 alu.op = ALU_OP1_MOV;
6030 break;
6031 default:
6032 assert(0);
6033 return -1;
6034 }
6035
6036 for (i = 0; i <= lasti; ++i) {
6037 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6038 continue;
6039 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6040 alu.last = i == lasti;
6041 alu.dst.sel = ctx->bc->ar_reg;
6042 alu.dst.chan = i;
6043 alu.dst.write = 1;
6044 r = r600_bytecode_add_alu(ctx->bc, &alu);
6045 if (r)
6046 return r;
6047 }
6048
6049 ctx->bc->ar_loaded = 0;
6050 return 0;
6051 }
6052 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
6053 {
6054 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6055 struct r600_bytecode_alu alu;
6056 int r;
6057 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6058
6059 switch (inst->Instruction.Opcode) {
6060 case TGSI_OPCODE_ARL:
6061 memset(&alu, 0, sizeof(alu));
6062 alu.op = ALU_OP1_FLOOR;
6063 alu.dst.sel = ctx->bc->ar_reg;
6064 alu.dst.write = 1;
6065 for (i = 0; i <= lasti; ++i) {
6066 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
6067 alu.dst.chan = i;
6068 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6069 alu.last = i == lasti;
6070 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6071 return r;
6072 }
6073 }
6074
6075 memset(&alu, 0, sizeof(alu));
6076 alu.op = ALU_OP1_FLT_TO_INT;
6077 alu.src[0].sel = ctx->bc->ar_reg;
6078 alu.dst.sel = ctx->bc->ar_reg;
6079 alu.dst.write = 1;
6080 /* FLT_TO_INT is trans-only on r600/r700 */
6081 alu.last = TRUE;
6082 for (i = 0; i <= lasti; ++i) {
6083 alu.dst.chan = i;
6084 alu.src[0].chan = i;
6085 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6086 return r;
6087 }
6088 break;
6089 case TGSI_OPCODE_ARR:
6090 memset(&alu, 0, sizeof(alu));
6091 alu.op = ALU_OP1_FLT_TO_INT;
6092 alu.dst.sel = ctx->bc->ar_reg;
6093 alu.dst.write = 1;
6094 /* FLT_TO_INT is trans-only on r600/r700 */
6095 alu.last = TRUE;
6096 for (i = 0; i <= lasti; ++i) {
6097 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
6098 alu.dst.chan = i;
6099 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6100 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6101 return r;
6102 }
6103 }
6104 break;
6105 case TGSI_OPCODE_UARL:
6106 memset(&alu, 0, sizeof(alu));
6107 alu.op = ALU_OP1_MOV;
6108 alu.dst.sel = ctx->bc->ar_reg;
6109 alu.dst.write = 1;
6110 for (i = 0; i <= lasti; ++i) {
6111 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
6112 alu.dst.chan = i;
6113 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6114 alu.last = i == lasti;
6115 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6116 return r;
6117 }
6118 }
6119 break;
6120 default:
6121 assert(0);
6122 return -1;
6123 }
6124
6125 ctx->bc->ar_loaded = 0;
6126 return 0;
6127 }
6128
6129 static int tgsi_opdst(struct r600_shader_ctx *ctx)
6130 {
6131 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6132 struct r600_bytecode_alu alu;
6133 int i, r = 0;
6134
6135 for (i = 0; i < 4; i++) {
6136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6137
6138 alu.op = ALU_OP2_MUL;
6139 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6140
6141 if (i == 0 || i == 3) {
6142 alu.src[0].sel = V_SQ_ALU_SRC_1;
6143 } else {
6144 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6145 }
6146
6147 if (i == 0 || i == 2) {
6148 alu.src[1].sel = V_SQ_ALU_SRC_1;
6149 } else {
6150 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
6151 }
6152 if (i == 3)
6153 alu.last = 1;
6154 r = r600_bytecode_add_alu(ctx->bc, &alu);
6155 if (r)
6156 return r;
6157 }
6158 return 0;
6159 }
6160
6161 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
6162 {
6163 struct r600_bytecode_alu alu;
6164 int r;
6165
6166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6167 alu.op = opcode;
6168 alu.execute_mask = 1;
6169 alu.update_pred = 1;
6170
6171 alu.dst.sel = ctx->temp_reg;
6172 alu.dst.write = 1;
6173 alu.dst.chan = 0;
6174
6175 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6176 alu.src[1].sel = V_SQ_ALU_SRC_0;
6177 alu.src[1].chan = 0;
6178
6179 alu.last = 1;
6180
6181 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
6182 if (r)
6183 return r;
6184 return 0;
6185 }
6186
6187 static int pops(struct r600_shader_ctx *ctx, int pops)
6188 {
6189 unsigned force_pop = ctx->bc->force_add_cf;
6190
6191 if (!force_pop) {
6192 int alu_pop = 3;
6193 if (ctx->bc->cf_last) {
6194 if (ctx->bc->cf_last->op == CF_OP_ALU)
6195 alu_pop = 0;
6196 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
6197 alu_pop = 1;
6198 }
6199 alu_pop += pops;
6200 if (alu_pop == 1) {
6201 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
6202 ctx->bc->force_add_cf = 1;
6203 } else if (alu_pop == 2) {
6204 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
6205 ctx->bc->force_add_cf = 1;
6206 } else {
6207 force_pop = 1;
6208 }
6209 }
6210
6211 if (force_pop) {
6212 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
6213 ctx->bc->cf_last->pop_count = pops;
6214 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
6215 }
6216
6217 return 0;
6218 }
6219
6220 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
6221 unsigned reason)
6222 {
6223 struct r600_stack_info *stack = &ctx->bc->stack;
6224 unsigned elements, entries;
6225
6226 unsigned entry_size = stack->entry_size;
6227
6228 elements = (stack->loop + stack->push_wqm ) * entry_size;
6229 elements += stack->push;
6230
6231 switch (ctx->bc->chip_class) {
6232 case R600:
6233 case R700:
6234 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
6235 * the stack must be reserved to hold the current active/continue
6236 * masks */
6237 if (reason == FC_PUSH_VPM) {
6238 elements += 2;
6239 }
6240 break;
6241
6242 case CAYMAN:
6243 /* r9xx: any stack operation on empty stack consumes 2 additional
6244 * elements */
6245 elements += 2;
6246
6247 /* fallthrough */
6248 /* FIXME: do the two elements added above cover the cases for the
6249 * r8xx+ below? */
6250
6251 case EVERGREEN:
6252 /* r8xx+: 2 extra elements are not always required, but one extra
6253 * element must be added for each of the following cases:
6254 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
6255 * stack usage.
6256 * (Currently we don't use ALU_ELSE_AFTER.)
6257 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
6258 * PUSH instruction executed.
6259 *
6260 * NOTE: it seems we also need to reserve additional element in some
6261 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
6262 * then STACK_SIZE should be 2 instead of 1 */
6263 if (reason == FC_PUSH_VPM) {
6264 elements += 1;
6265 }
6266 break;
6267
6268 default:
6269 assert(0);
6270 break;
6271 }
6272
6273 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
6274 * for all chips, so we use 4 in the final formula, not the real entry_size
6275 * for the chip */
6276 entry_size = 4;
6277
6278 entries = (elements + (entry_size - 1)) / entry_size;
6279
6280 if (entries > stack->max_entries)
6281 stack->max_entries = entries;
6282 }
6283
6284 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
6285 {
6286 switch(reason) {
6287 case FC_PUSH_VPM:
6288 --ctx->bc->stack.push;
6289 assert(ctx->bc->stack.push >= 0);
6290 break;
6291 case FC_PUSH_WQM:
6292 --ctx->bc->stack.push_wqm;
6293 assert(ctx->bc->stack.push_wqm >= 0);
6294 break;
6295 case FC_LOOP:
6296 --ctx->bc->stack.loop;
6297 assert(ctx->bc->stack.loop >= 0);
6298 break;
6299 default:
6300 assert(0);
6301 break;
6302 }
6303 }
6304
6305 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
6306 {
6307 switch (reason) {
6308 case FC_PUSH_VPM:
6309 ++ctx->bc->stack.push;
6310 break;
6311 case FC_PUSH_WQM:
6312 ++ctx->bc->stack.push_wqm;
6313 case FC_LOOP:
6314 ++ctx->bc->stack.loop;
6315 break;
6316 default:
6317 assert(0);
6318 }
6319
6320 callstack_update_max_depth(ctx, reason);
6321 }
6322
6323 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
6324 {
6325 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
6326
6327 sp->mid = realloc((void *)sp->mid,
6328 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
6329 sp->mid[sp->num_mid] = ctx->bc->cf_last;
6330 sp->num_mid++;
6331 }
6332
6333 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
6334 {
6335 ctx->bc->fc_sp++;
6336 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
6337 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
6338 }
6339
6340 static void fc_poplevel(struct r600_shader_ctx *ctx)
6341 {
6342 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
6343 free(sp->mid);
6344 sp->mid = NULL;
6345 sp->num_mid = 0;
6346 sp->start = NULL;
6347 sp->type = 0;
6348 ctx->bc->fc_sp--;
6349 }
6350
6351 #if 0
6352 static int emit_return(struct r600_shader_ctx *ctx)
6353 {
6354 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
6355 return 0;
6356 }
6357
6358 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
6359 {
6360
6361 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
6362 ctx->bc->cf_last->pop_count = pops;
6363 /* XXX work out offset */
6364 return 0;
6365 }
6366
6367 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
6368 {
6369 return 0;
6370 }
6371
6372 static void emit_testflag(struct r600_shader_ctx *ctx)
6373 {
6374
6375 }
6376
6377 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
6378 {
6379 emit_testflag(ctx);
6380 emit_jump_to_offset(ctx, 1, 4);
6381 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
6382 pops(ctx, ifidx + 1);
6383 emit_return(ctx);
6384 }
6385
6386 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
6387 {
6388 emit_testflag(ctx);
6389
6390 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6391 ctx->bc->cf_last->pop_count = 1;
6392
6393 fc_set_mid(ctx, fc_sp);
6394
6395 pops(ctx, 1);
6396 }
6397 #endif
6398
6399 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
6400 {
6401 int alu_type = CF_OP_ALU_PUSH_BEFORE;
6402
6403 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
6404 * LOOP_STARTxxx for nested loops may put the branch stack into a state
6405 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
6406 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
6407 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
6408 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
6409 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
6410 alu_type = CF_OP_ALU;
6411 }
6412
6413 emit_logic_pred(ctx, opcode, alu_type);
6414
6415 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
6416
6417 fc_pushlevel(ctx, FC_IF);
6418
6419 callstack_push(ctx, FC_PUSH_VPM);
6420 return 0;
6421 }
6422
6423 static int tgsi_if(struct r600_shader_ctx *ctx)
6424 {
6425 return emit_if(ctx, ALU_OP2_PRED_SETNE);
6426 }
6427
6428 static int tgsi_uif(struct r600_shader_ctx *ctx)
6429 {
6430 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
6431 }
6432
6433 static int tgsi_else(struct r600_shader_ctx *ctx)
6434 {
6435 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
6436 ctx->bc->cf_last->pop_count = 1;
6437
6438 fc_set_mid(ctx, ctx->bc->fc_sp);
6439 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
6440 return 0;
6441 }
6442
6443 static int tgsi_endif(struct r600_shader_ctx *ctx)
6444 {
6445 pops(ctx, 1);
6446 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
6447 R600_ERR("if/endif unbalanced in shader\n");
6448 return -1;
6449 }
6450
6451 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
6452 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
6453 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
6454 } else {
6455 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
6456 }
6457 fc_poplevel(ctx);
6458
6459 callstack_pop(ctx, FC_PUSH_VPM);
6460 return 0;
6461 }
6462
6463 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
6464 {
6465 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
6466 * limited to 4096 iterations, like the other LOOP_* instructions. */
6467 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
6468
6469 fc_pushlevel(ctx, FC_LOOP);
6470
6471 /* check stack depth */
6472 callstack_push(ctx, FC_LOOP);
6473 return 0;
6474 }
6475
6476 static int tgsi_endloop(struct r600_shader_ctx *ctx)
6477 {
6478 int i;
6479
6480 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
6481
6482 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
6483 R600_ERR("loop/endloop in shader code are not paired.\n");
6484 return -EINVAL;
6485 }
6486
6487 /* fixup loop pointers - from r600isa
6488 LOOP END points to CF after LOOP START,
6489 LOOP START point to CF after LOOP END
6490 BRK/CONT point to LOOP END CF
6491 */
6492 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
6493
6494 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
6495
6496 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
6497 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
6498 }
6499 /* XXX add LOOPRET support */
6500 fc_poplevel(ctx);
6501 callstack_pop(ctx, FC_LOOP);
6502 return 0;
6503 }
6504
6505 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
6506 {
6507 int r;
6508 unsigned int fscp;
6509
6510 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
6511 {
6512 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
6513 break;
6514 }
6515 if (fscp == 0) {
6516 R600_ERR("BREAKC not inside loop/endloop pair\n");
6517 return -EINVAL;
6518 }
6519
6520 if (ctx->bc->chip_class == EVERGREEN &&
6521 ctx->bc->family != CHIP_CYPRESS &&
6522 ctx->bc->family != CHIP_JUNIPER) {
6523 /* HW bug: ALU_BREAK does not save the active mask correctly */
6524 r = tgsi_uif(ctx);
6525 if (r)
6526 return r;
6527
6528 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
6529 if (r)
6530 return r;
6531 fc_set_mid(ctx, fscp);
6532
6533 return tgsi_endif(ctx);
6534 } else {
6535 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
6536 if (r)
6537 return r;
6538 fc_set_mid(ctx, fscp);
6539 }
6540
6541 return 0;
6542 }
6543
6544 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
6545 {
6546 unsigned int fscp;
6547
6548 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
6549 {
6550 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
6551 break;
6552 }
6553
6554 if (fscp == 0) {
6555 R600_ERR("Break not inside loop/endloop pair\n");
6556 return -EINVAL;
6557 }
6558
6559 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6560
6561 fc_set_mid(ctx, fscp);
6562
6563 return 0;
6564 }
6565
6566 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
6567 {
6568 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
6569 emit_gs_ring_writes(ctx, TRUE);
6570
6571 return r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6572 }
6573
6574 static int tgsi_umad(struct r600_shader_ctx *ctx)
6575 {
6576 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6577 struct r600_bytecode_alu alu;
6578 int i, j, k, r;
6579 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6580
6581 /* src0 * src1 */
6582 for (i = 0; i < lasti + 1; i++) {
6583 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6584 continue;
6585
6586 if (ctx->bc->chip_class == CAYMAN) {
6587 for (j = 0 ; j < 4; j++) {
6588 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6589
6590 alu.op = ALU_OP2_MULLO_UINT;
6591 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
6592 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
6593 }
6594 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
6595 alu.dst.sel = ctx->temp_reg;
6596 alu.dst.write = (j == i);
6597 if (j == 3)
6598 alu.last = 1;
6599 r = r600_bytecode_add_alu(ctx->bc, &alu);
6600 if (r)
6601 return r;
6602 }
6603 } else {
6604 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6605
6606 alu.dst.chan = i;
6607 alu.dst.sel = ctx->temp_reg;
6608 alu.dst.write = 1;
6609
6610 alu.op = ALU_OP2_MULLO_UINT;
6611 for (j = 0; j < 2; j++) {
6612 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6613 }
6614
6615 alu.last = 1;
6616 r = r600_bytecode_add_alu(ctx->bc, &alu);
6617 if (r)
6618 return r;
6619 }
6620 }
6621
6622
6623 for (i = 0; i < lasti + 1; i++) {
6624 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6625 continue;
6626
6627 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6628 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6629
6630 alu.op = ALU_OP2_ADD_INT;
6631
6632 alu.src[0].sel = ctx->temp_reg;
6633 alu.src[0].chan = i;
6634
6635 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6636 if (i == lasti) {
6637 alu.last = 1;
6638 }
6639 r = r600_bytecode_add_alu(ctx->bc, &alu);
6640 if (r)
6641 return r;
6642 }
6643 return 0;
6644 }
6645
6646 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
6647 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
6648 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6649 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6650
6651 /* XXX:
6652 * For state trackers other than OpenGL, we'll want to use
6653 * _RECIP_IEEE instead.
6654 */
6655 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
6656
6657 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
6658 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6659 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6660 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6661 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6662 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6663 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6664 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6665 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6666 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6667 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6668 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6669 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6670 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6671 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6672 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6673 {TGSI_OPCODE_SQRT, 0, ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
6674 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6675 /* gap */
6676 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6677 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6678 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6679 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6680 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6681 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6682 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6683 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6684 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6685 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6686 /* gap */
6687 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6688 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6689 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6690 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6691 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6692 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6693 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6694 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6695 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6696 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6697 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6698 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6699 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6700 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6701 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6702 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6703 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6704 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6705 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6706 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6707 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6708 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6709 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6710 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6711 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6712 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6713 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6714 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6715 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6716 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
6717 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6718 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6719 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6720 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6721 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6722 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6723 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6724 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6725 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6726 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6727 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6728 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6729 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6730 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6731 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6732 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6733 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6734 /* gap */
6735 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6736 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6737 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6738 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6739 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6740 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6741 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6742 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6743 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
6744 /* gap */
6745 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6746 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6747 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6748 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6749 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6750 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6751 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6752 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6753 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6754 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6755 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6756 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6757 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6758 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6759 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6760 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6761 /* gap */
6762 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6763 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6764 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6765 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6766 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6767 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6768 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6769 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6770 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6771 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6772 /* gap */
6773 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6774 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_loop_breakc},
6775 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6776 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6777 /* gap */
6778 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6779 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
6780 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6781 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6782 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6783 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6784 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6785 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
6786 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6787 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
6788 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6789 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6790 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6791 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6792 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6793 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6794 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6795 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6796 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6797 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6798 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
6799 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6800 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
6801 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6802 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6803 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6804 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6805 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6806 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6807 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6808 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6809 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6810 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6811 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6812 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6813 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6814 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6815 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6816 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6817 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
6818 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6819 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6820 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6821 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6822 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6823 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6824 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6825 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6826 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6827 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6828 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6829 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6830 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6831 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6832 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6833 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6834 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6835 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6836 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6837 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6838 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6839 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6840 {TGSI_OPCODE_IMUL_HI, 0, ALU_OP2_MULHI_INT, tgsi_op2_trans},
6841 {TGSI_OPCODE_UMUL_HI, 0, ALU_OP2_MULHI_UINT, tgsi_op2_trans},
6842 {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_unsupported},
6843 {TGSI_OPCODE_LODQ, 0, FETCH_OP_GET_LOD, tgsi_unsupported},
6844 {TGSI_OPCODE_IBFE, 1, ALU_OP3_BFE_INT, tgsi_unsupported},
6845 {TGSI_OPCODE_UBFE, 1, ALU_OP3_BFE_UINT, tgsi_unsupported},
6846 {TGSI_OPCODE_BFI, 0, ALU_OP0_NOP, tgsi_unsupported},
6847 {TGSI_OPCODE_BREV, 0, ALU_OP1_BFREV_INT, tgsi_unsupported},
6848 {TGSI_OPCODE_POPC, 0, ALU_OP1_BCNT_INT, tgsi_unsupported},
6849 {TGSI_OPCODE_LSB, 0, ALU_OP1_FFBL_INT, tgsi_unsupported},
6850 {TGSI_OPCODE_IMSB, 0, ALU_OP1_FFBH_INT, tgsi_unsupported},
6851 {TGSI_OPCODE_UMSB, 0, ALU_OP1_FFBH_UINT, tgsi_unsupported},
6852 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6853 };
6854
6855 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
6856 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6857 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6858 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6859 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
6860 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
6861 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6862 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6863 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6864 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6865 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6866 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6867 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6868 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6869 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6870 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6871 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6872 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6873 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6874 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6875 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6876 {TGSI_OPCODE_SQRT, 0, ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
6877 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6878 /* gap */
6879 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6880 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6881 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6882 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6883 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6884 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6885 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6886 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6887 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6888 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6889 /* gap */
6890 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6891 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6892 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6893 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6894 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6895 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6896 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6897 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6898 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6899 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6900 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6901 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6902 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6903 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6904 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6905 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6906 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6907 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6908 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6909 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6910 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6911 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6912 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6913 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6914 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6915 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6916 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6917 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6918 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6919 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6920 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6921 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6922 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6923 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6924 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6925 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6926 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6927 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6928 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6929 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6930 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6931 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6932 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6933 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6934 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6935 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6936 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6937 /* gap */
6938 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6939 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6940 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6941 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6942 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6943 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6944 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6945 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6946 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6947 /* gap */
6948 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6949 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6950 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6951 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6952 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6953 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6954 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6955 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6956 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6957 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6958 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6959 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6960 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6961 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6962 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6963 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6964 /* gap */
6965 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6966 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6967 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6968 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6969 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6970 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6971 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6972 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6973 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6974 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6975 /* gap */
6976 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6977 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6978 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6979 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6980 /* gap */
6981 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6982 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
6983 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6984 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6985 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6986 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6987 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6988 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6989 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6990 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
6991 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6992 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6993 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6994 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6995 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6996 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6997 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6998 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6999 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
7000 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
7001 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
7002 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7003 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
7004 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
7005 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
7006 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
7007 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
7008 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
7009 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
7010 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
7011 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
7012 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
7013 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
7014 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
7015 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
7016 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
7017 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
7018 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
7019 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
7020 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
7021 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
7022 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
7023 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
7024 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
7025 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
7026 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7027 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7028 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7029 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
7030 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
7031 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
7032 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
7033 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
7034 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
7035 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
7036 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
7037 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
7038 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
7039 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
7040 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
7041 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
7042 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
7043 {TGSI_OPCODE_IMUL_HI, 0, ALU_OP2_MULHI_INT, tgsi_op2_trans},
7044 {TGSI_OPCODE_UMUL_HI, 0, ALU_OP2_MULHI_UINT, tgsi_op2_trans},
7045 {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_tex},
7046 {TGSI_OPCODE_LODQ, 0, FETCH_OP_GET_LOD, tgsi_tex},
7047 {TGSI_OPCODE_IBFE, 1, ALU_OP3_BFE_INT, tgsi_op3},
7048 {TGSI_OPCODE_UBFE, 1, ALU_OP3_BFE_UINT, tgsi_op3},
7049 {TGSI_OPCODE_BFI, 0, ALU_OP0_NOP, tgsi_bfi},
7050 {TGSI_OPCODE_BREV, 0, ALU_OP1_BFREV_INT, tgsi_op2},
7051 {TGSI_OPCODE_POPC, 0, ALU_OP1_BCNT_INT, tgsi_op2},
7052 {TGSI_OPCODE_LSB, 0, ALU_OP1_FFBL_INT, tgsi_op2},
7053 {TGSI_OPCODE_IMSB, 0, ALU_OP1_FFBH_INT, tgsi_msb},
7054 {TGSI_OPCODE_UMSB, 0, ALU_OP1_FFBH_UINT, tgsi_msb},
7055 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
7056 };
7057
7058 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
7059 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
7060 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
7061 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
7062 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
7063 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
7064 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
7065 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
7066 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
7067 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
7068 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
7069 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
7070 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
7071 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
7072 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
7073 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
7074 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
7075 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
7076 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
7077 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
7078 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
7079 {TGSI_OPCODE_SQRT, 0, ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
7080 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
7081 /* gap */
7082 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
7083 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
7084 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
7085 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
7086 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
7087 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
7088 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
7089 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
7090 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
7091 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
7092 /* gap */
7093 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
7094 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
7095 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
7096 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
7097 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
7098 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7099 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7100 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7101 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
7102 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
7103 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
7104 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
7105 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
7106 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
7107 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
7108 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
7109 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
7110 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
7111 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
7112 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
7113 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
7114 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
7115 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
7116 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
7117 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
7118 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
7119 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
7120 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
7121 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
7122 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
7123 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
7124 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
7125 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
7126 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
7127 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
7128 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
7129 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
7130 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
7131 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
7132 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
7133 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
7134 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
7135 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
7136 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
7137 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
7138 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
7139 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
7140 /* gap */
7141 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
7142 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
7143 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
7144 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
7145 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
7146 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
7147 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
7148 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
7149 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
7150 /* gap */
7151 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
7152 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
7153 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
7154 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
7155 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
7156 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
7157 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
7158 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7159 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
7160 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
7161 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
7162 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
7163 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
7164 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
7165 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
7166 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
7167 /* gap */
7168 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
7169 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
7170 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
7171 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
7172 /* gap */
7173 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
7174 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
7175 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
7176 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
7177 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
7178 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
7179 /* gap */
7180 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
7181 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
7182 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
7183 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
7184 /* gap */
7185 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
7186 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
7187 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
7188 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
7189 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
7190 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
7191 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
7192 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
7193 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
7194 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
7195 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
7196 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
7197 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
7198 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
7199 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
7200 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
7201 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
7202 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
7203 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
7204 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
7205 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
7206 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7207 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
7208 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
7209 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
7210 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
7211 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
7212 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
7213 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
7214 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
7215 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
7216 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
7217 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
7218 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
7219 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
7220 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
7221 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
7222 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
7223 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
7224 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
7225 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
7226 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
7227 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
7228 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
7229 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
7230 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7231 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7232 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7233 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
7234 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
7235 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
7236 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
7237 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
7238 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
7239 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
7240 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
7241 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
7242 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
7243 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
7244 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
7245 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
7246 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
7247 {TGSI_OPCODE_IMUL_HI, 0, ALU_OP2_MULHI_INT, cayman_mul_int_instr},
7248 {TGSI_OPCODE_UMUL_HI, 0, ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
7249 {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_tex},
7250 {TGSI_OPCODE_LODQ, 0, FETCH_OP_GET_LOD, tgsi_tex},
7251 {TGSI_OPCODE_IBFE, 1, ALU_OP3_BFE_INT, tgsi_op3},
7252 {TGSI_OPCODE_UBFE, 1, ALU_OP3_BFE_UINT, tgsi_op3},
7253 {TGSI_OPCODE_BFI, 0, ALU_OP0_NOP, tgsi_bfi},
7254 {TGSI_OPCODE_BREV, 0, ALU_OP1_BFREV_INT, tgsi_op2},
7255 {TGSI_OPCODE_POPC, 0, ALU_OP1_BCNT_INT, tgsi_op2},
7256 {TGSI_OPCODE_LSB, 0, ALU_OP1_FFBL_INT, tgsi_op2},
7257 {TGSI_OPCODE_IMSB, 0, ALU_OP1_FFBH_INT, tgsi_msb},
7258 {TGSI_OPCODE_UMSB, 0, ALU_OP1_FFBH_UINT, tgsi_msb},
7259 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
7260 };