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r600: port over the get_lds_unique_index from radeonsi
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
64 static int r600_shader_from_tgsi(struct r600_context *rctx,
65 struct r600_pipe_shader *pipeshader,
66 union r600_shader_key key);
67
68
69 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
70 int size, unsigned comp_mask) {
71
72 if (!size)
73 return;
74
75 if (ps->num_arrays == ps->max_arrays) {
76 ps->max_arrays += 64;
77 ps->arrays = realloc(ps->arrays, ps->max_arrays *
78 sizeof(struct r600_shader_array));
79 }
80
81 int n = ps->num_arrays;
82 ++ps->num_arrays;
83
84 ps->arrays[n].comp_mask = comp_mask;
85 ps->arrays[n].gpr_start = start_gpr;
86 ps->arrays[n].gpr_count = size;
87 }
88
89 static void r600_dump_streamout(struct pipe_stream_output_info *so)
90 {
91 unsigned i;
92
93 fprintf(stderr, "STREAMOUT\n");
94 for (i = 0; i < so->num_outputs; i++) {
95 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
96 so->output[i].start_component;
97 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
98 i,
99 so->output[i].stream,
100 so->output[i].output_buffer,
101 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
102 so->output[i].register_index,
103 mask & 1 ? "x" : "",
104 mask & 2 ? "y" : "",
105 mask & 4 ? "z" : "",
106 mask & 8 ? "w" : "",
107 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
108 }
109 }
110
111 static int store_shader(struct pipe_context *ctx,
112 struct r600_pipe_shader *shader)
113 {
114 struct r600_context *rctx = (struct r600_context *)ctx;
115 uint32_t *ptr, i;
116
117 if (shader->bo == NULL) {
118 shader->bo = (struct r600_resource*)
119 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
120 if (shader->bo == NULL) {
121 return -ENOMEM;
122 }
123 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
124 if (R600_BIG_ENDIAN) {
125 for (i = 0; i < shader->shader.bc.ndw; ++i) {
126 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
127 }
128 } else {
129 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
130 }
131 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
132 }
133
134 return 0;
135 }
136
137 int r600_pipe_shader_create(struct pipe_context *ctx,
138 struct r600_pipe_shader *shader,
139 union r600_shader_key key)
140 {
141 struct r600_context *rctx = (struct r600_context *)ctx;
142 struct r600_pipe_shader_selector *sel = shader->selector;
143 int r;
144 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
145 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
146 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
147 unsigned export_shader;
148
149 shader->shader.bc.isa = rctx->isa;
150
151 if (dump) {
152 fprintf(stderr, "--------------------------------------------------------------\n");
153 tgsi_dump(sel->tokens, 0);
154
155 if (sel->so.num_outputs) {
156 r600_dump_streamout(&sel->so);
157 }
158 }
159 r = r600_shader_from_tgsi(rctx, shader, key);
160 if (r) {
161 R600_ERR("translation from TGSI failed !\n");
162 goto error;
163 }
164 if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) {
165 /* only disable for vertex shaders in tess paths */
166 if (key.vs.as_ls)
167 use_sb = 0;
168 }
169 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL);
170 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL);
171
172 /* disable SB for shaders using doubles */
173 use_sb &= !shader->shader.uses_doubles;
174
175 /* Check if the bytecode has already been built. When using the llvm
176 * backend, r600_shader_from_tgsi() will take care of building the
177 * bytecode.
178 */
179 if (!shader->shader.bc.bytecode) {
180 r = r600_bytecode_build(&shader->shader.bc);
181 if (r) {
182 R600_ERR("building bytecode failed !\n");
183 goto error;
184 }
185 }
186
187 if (dump && !sb_disasm) {
188 fprintf(stderr, "--------------------------------------------------------------\n");
189 r600_bytecode_disasm(&shader->shader.bc);
190 fprintf(stderr, "______________________________________________________________\n");
191 } else if ((dump && sb_disasm) || use_sb) {
192 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
193 dump, use_sb);
194 if (r) {
195 R600_ERR("r600_sb_bytecode_process failed !\n");
196 goto error;
197 }
198 }
199
200 if (shader->gs_copy_shader) {
201 if (dump) {
202 // dump copy shader
203 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
204 &shader->gs_copy_shader->shader, dump, 0);
205 if (r)
206 goto error;
207 }
208
209 if ((r = store_shader(ctx, shader->gs_copy_shader)))
210 goto error;
211 }
212
213 /* Store the shader in a buffer. */
214 if ((r = store_shader(ctx, shader)))
215 goto error;
216
217 /* Build state. */
218 switch (shader->shader.processor_type) {
219 case TGSI_PROCESSOR_TESS_CTRL:
220 evergreen_update_hs_state(ctx, shader);
221 break;
222 case TGSI_PROCESSOR_TESS_EVAL:
223 if (key.tes.as_es)
224 evergreen_update_es_state(ctx, shader);
225 else
226 evergreen_update_vs_state(ctx, shader);
227 break;
228 case TGSI_PROCESSOR_GEOMETRY:
229 if (rctx->b.chip_class >= EVERGREEN) {
230 evergreen_update_gs_state(ctx, shader);
231 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
232 } else {
233 r600_update_gs_state(ctx, shader);
234 r600_update_vs_state(ctx, shader->gs_copy_shader);
235 }
236 break;
237 case TGSI_PROCESSOR_VERTEX:
238 export_shader = key.vs.as_es;
239 if (rctx->b.chip_class >= EVERGREEN) {
240 if (key.vs.as_ls)
241 evergreen_update_ls_state(ctx, shader);
242 else if (key.vs.as_es)
243 evergreen_update_es_state(ctx, shader);
244 else
245 evergreen_update_vs_state(ctx, shader);
246 } else {
247 if (export_shader)
248 r600_update_es_state(ctx, shader);
249 else
250 r600_update_vs_state(ctx, shader);
251 }
252 break;
253 case TGSI_PROCESSOR_FRAGMENT:
254 if (rctx->b.chip_class >= EVERGREEN) {
255 evergreen_update_ps_state(ctx, shader);
256 } else {
257 r600_update_ps_state(ctx, shader);
258 }
259 break;
260 default:
261 r = -EINVAL;
262 goto error;
263 }
264 return 0;
265
266 error:
267 r600_pipe_shader_destroy(ctx, shader);
268 return r;
269 }
270
271 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
272 {
273 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
274 r600_bytecode_clear(&shader->shader.bc);
275 r600_release_command_buffer(&shader->command_buffer);
276 }
277
278 /*
279 * tgsi -> r600 shader
280 */
281 struct r600_shader_tgsi_instruction;
282
283 struct r600_shader_src {
284 unsigned sel;
285 unsigned swizzle[4];
286 unsigned neg;
287 unsigned abs;
288 unsigned rel;
289 unsigned kc_bank;
290 boolean kc_rel; /* true if cache bank is indexed */
291 uint32_t value[4];
292 };
293
294 struct eg_interp {
295 boolean enabled;
296 unsigned ij_index;
297 };
298
299 struct r600_shader_ctx {
300 struct tgsi_shader_info info;
301 struct tgsi_parse_context parse;
302 const struct tgsi_token *tokens;
303 unsigned type;
304 unsigned file_offset[TGSI_FILE_COUNT];
305 unsigned temp_reg;
306 const struct r600_shader_tgsi_instruction *inst_info;
307 struct r600_bytecode *bc;
308 struct r600_shader *shader;
309 struct r600_shader_src src[4];
310 uint32_t *literals;
311 uint32_t nliterals;
312 uint32_t max_driver_temp_used;
313 boolean use_llvm;
314 /* needed for evergreen interpolation */
315 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
316 /* evergreen/cayman also store sample mask in face register */
317 int face_gpr;
318 /* sample id is .w component stored in fixed point position register */
319 int fixed_pt_position_gpr;
320 int colors_used;
321 boolean clip_vertex_write;
322 unsigned cv_output;
323 unsigned edgeflag_output;
324 int fragcoord_input;
325 int native_integers;
326 int next_ring_offset;
327 int gs_out_ring_offset;
328 int gs_next_vertex;
329 struct r600_shader *gs_for_vs;
330 int gs_export_gpr_tregs[4];
331 const struct pipe_stream_output_info *gs_stream_output_info;
332 unsigned enabled_stream_buffers_mask;
333 };
334
335 struct r600_shader_tgsi_instruction {
336 unsigned op;
337 int (*process)(struct r600_shader_ctx *ctx);
338 };
339
340 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
341 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
342 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
343 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
344 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
345 static int tgsi_else(struct r600_shader_ctx *ctx);
346 static int tgsi_endif(struct r600_shader_ctx *ctx);
347 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
348 static int tgsi_endloop(struct r600_shader_ctx *ctx);
349 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
350 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
351 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
352 unsigned int dst_reg);
353 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
354 const struct r600_shader_src *shader_src,
355 unsigned chan);
356
357 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
358 {
359 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
360 int j;
361
362 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
363 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
364 return -EINVAL;
365 }
366 if (i->Instruction.Predicate) {
367 R600_ERR("predicate unsupported\n");
368 return -EINVAL;
369 }
370 #if 0
371 if (i->Instruction.Label) {
372 R600_ERR("label unsupported\n");
373 return -EINVAL;
374 }
375 #endif
376 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
377 if (i->Src[j].Register.Dimension) {
378 switch (i->Src[j].Register.File) {
379 case TGSI_FILE_CONSTANT:
380 break;
381 case TGSI_FILE_INPUT:
382 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
383 break;
384 default:
385 R600_ERR("unsupported src %d (dimension %d)\n", j,
386 i->Src[j].Register.Dimension);
387 return -EINVAL;
388 }
389 }
390 }
391 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
392 if (i->Dst[j].Register.Dimension) {
393 R600_ERR("unsupported dst (dimension)\n");
394 return -EINVAL;
395 }
396 }
397 return 0;
398 }
399
400 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
401 {
402 if (interpolate == TGSI_INTERPOLATE_COLOR ||
403 interpolate == TGSI_INTERPOLATE_LINEAR ||
404 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
405 {
406 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
407 int loc;
408
409 switch(location) {
410 case TGSI_INTERPOLATE_LOC_CENTER:
411 loc = 1;
412 break;
413 case TGSI_INTERPOLATE_LOC_CENTROID:
414 loc = 2;
415 break;
416 case TGSI_INTERPOLATE_LOC_SAMPLE:
417 default:
418 loc = 0; break;
419 }
420
421 return is_linear * 3 + loc;
422 }
423
424 return -1;
425 }
426
427 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
428 int input)
429 {
430 int i = eg_get_interpolator_index(
431 ctx->shader->input[input].interpolate,
432 ctx->shader->input[input].interpolate_location);
433 assert(i >= 0);
434 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
435 }
436
437 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
438 {
439 int i, r;
440 struct r600_bytecode_alu alu;
441 int gpr = 0, base_chan = 0;
442 int ij_index = ctx->shader->input[input].ij_index;
443
444 /* work out gpr and base_chan from index */
445 gpr = ij_index / 2;
446 base_chan = (2 * (ij_index % 2)) + 1;
447
448 for (i = 0; i < 8; i++) {
449 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
450
451 if (i < 4)
452 alu.op = ALU_OP2_INTERP_ZW;
453 else
454 alu.op = ALU_OP2_INTERP_XY;
455
456 if ((i > 1) && (i < 6)) {
457 alu.dst.sel = ctx->shader->input[input].gpr;
458 alu.dst.write = 1;
459 }
460
461 alu.dst.chan = i % 4;
462
463 alu.src[0].sel = gpr;
464 alu.src[0].chan = (base_chan - (i % 2));
465
466 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
467
468 alu.bank_swizzle_force = SQ_ALU_VEC_210;
469 if ((i % 4) == 3)
470 alu.last = 1;
471 r = r600_bytecode_add_alu(ctx->bc, &alu);
472 if (r)
473 return r;
474 }
475 return 0;
476 }
477
478 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
479 {
480 int i, r;
481 struct r600_bytecode_alu alu;
482
483 for (i = 0; i < 4; i++) {
484 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
485
486 alu.op = ALU_OP1_INTERP_LOAD_P0;
487
488 alu.dst.sel = ctx->shader->input[input].gpr;
489 alu.dst.write = 1;
490
491 alu.dst.chan = i;
492
493 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
494 alu.src[0].chan = i;
495
496 if (i == 3)
497 alu.last = 1;
498 r = r600_bytecode_add_alu(ctx->bc, &alu);
499 if (r)
500 return r;
501 }
502 return 0;
503 }
504
505 /*
506 * Special export handling in shaders
507 *
508 * shader export ARRAY_BASE for EXPORT_POS:
509 * 60 is position
510 * 61 is misc vector
511 * 62, 63 are clip distance vectors
512 *
513 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
514 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
515 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
516 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
517 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
518 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
519 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
520 * exclusive from render target index)
521 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
522 *
523 *
524 * shader export ARRAY_BASE for EXPORT_PIXEL:
525 * 0-7 CB targets
526 * 61 computed Z vector
527 *
528 * The use of the values exported in the computed Z vector are controlled
529 * by DB_SHADER_CONTROL:
530 * Z_EXPORT_ENABLE - Z as a float in RED
531 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
532 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
533 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
534 * DB_SOURCE_FORMAT - export control restrictions
535 *
536 */
537
538
539 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
540 static int r600_spi_sid(struct r600_shader_io * io)
541 {
542 int index, name = io->name;
543
544 /* These params are handled differently, they don't need
545 * semantic indices, so we'll use 0 for them.
546 */
547 if (name == TGSI_SEMANTIC_POSITION ||
548 name == TGSI_SEMANTIC_PSIZE ||
549 name == TGSI_SEMANTIC_EDGEFLAG ||
550 name == TGSI_SEMANTIC_FACE ||
551 name == TGSI_SEMANTIC_SAMPLEMASK)
552 index = 0;
553 else {
554 if (name == TGSI_SEMANTIC_GENERIC) {
555 /* For generic params simply use sid from tgsi */
556 index = io->sid;
557 } else {
558 /* For non-generic params - pack name and sid into 8 bits */
559 index = 0x80 | (name<<3) | (io->sid);
560 }
561
562 /* Make sure that all really used indices have nonzero value, so
563 * we can just compare it to 0 later instead of comparing the name
564 * with different values to detect special cases. */
565 index++;
566 }
567
568 return index;
569 };
570
571 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
572 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
573 {
574 switch (semantic_name) {
575 case TGSI_SEMANTIC_POSITION:
576 return 0;
577 case TGSI_SEMANTIC_PSIZE:
578 return 1;
579 case TGSI_SEMANTIC_CLIPDIST:
580 assert(index <= 1);
581 return 2 + index;
582 case TGSI_SEMANTIC_GENERIC:
583 if (index <= 63-4)
584 return 4 + index - 9;
585 else
586 /* same explanation as in the default statement,
587 * the only user hitting this is st/nine.
588 */
589 return 0;
590
591 /* patch indices are completely separate and thus start from 0 */
592 case TGSI_SEMANTIC_TESSOUTER:
593 return 0;
594 case TGSI_SEMANTIC_TESSINNER:
595 return 1;
596 case TGSI_SEMANTIC_PATCH:
597 return 2 + index;
598
599 default:
600 /* Don't fail here. The result of this function is only used
601 * for LS, TCS, TES, and GS, where legacy GL semantics can't
602 * occur, but this function is called for all vertex shaders
603 * before it's known whether LS will be compiled or not.
604 */
605 return 0;
606 }
607 }
608
609 /* turn input into interpolate on EG */
610 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
611 {
612 int r = 0;
613
614 if (ctx->shader->input[index].spi_sid) {
615 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
616 if (ctx->shader->input[index].interpolate > 0) {
617 evergreen_interp_assign_ij_index(ctx, index);
618 if (!ctx->use_llvm)
619 r = evergreen_interp_alu(ctx, index);
620 } else {
621 if (!ctx->use_llvm)
622 r = evergreen_interp_flat(ctx, index);
623 }
624 }
625 return r;
626 }
627
628 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
629 {
630 struct r600_bytecode_alu alu;
631 int i, r;
632 int gpr_front = ctx->shader->input[front].gpr;
633 int gpr_back = ctx->shader->input[back].gpr;
634
635 for (i = 0; i < 4; i++) {
636 memset(&alu, 0, sizeof(alu));
637 alu.op = ALU_OP3_CNDGT;
638 alu.is_op3 = 1;
639 alu.dst.write = 1;
640 alu.dst.sel = gpr_front;
641 alu.src[0].sel = ctx->face_gpr;
642 alu.src[1].sel = gpr_front;
643 alu.src[2].sel = gpr_back;
644
645 alu.dst.chan = i;
646 alu.src[1].chan = i;
647 alu.src[2].chan = i;
648 alu.last = (i==3);
649
650 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
651 return r;
652 }
653
654 return 0;
655 }
656
657 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
658 {
659 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
660 }
661
662 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
663 {
664 int i;
665 i = ctx->shader->noutput++;
666 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
667 ctx->shader->output[i].sid = 0;
668 ctx->shader->output[i].gpr = 0;
669 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
670 ctx->shader->output[i].write_mask = 0x4;
671 ctx->shader->output[i].spi_sid = prim_id_sid;
672
673 return 0;
674 }
675
676 static int tgsi_declaration(struct r600_shader_ctx *ctx)
677 {
678 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
679 int r, i, j, count = d->Range.Last - d->Range.First + 1;
680
681 switch (d->Declaration.File) {
682 case TGSI_FILE_INPUT:
683 for (j = 0; j < count; j++) {
684 i = ctx->shader->ninput + j;
685 assert(i < Elements(ctx->shader->input));
686 ctx->shader->input[i].name = d->Semantic.Name;
687 ctx->shader->input[i].sid = d->Semantic.Index + j;
688 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
689 ctx->shader->input[i].interpolate_location = d->Interp.Location;
690 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
691 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
692 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
693 switch (ctx->shader->input[i].name) {
694 case TGSI_SEMANTIC_FACE:
695 if (ctx->face_gpr != -1)
696 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
697 else
698 ctx->face_gpr = ctx->shader->input[i].gpr;
699 break;
700 case TGSI_SEMANTIC_COLOR:
701 ctx->colors_used++;
702 break;
703 case TGSI_SEMANTIC_POSITION:
704 ctx->fragcoord_input = i;
705 break;
706 case TGSI_SEMANTIC_PRIMID:
707 /* set this for now */
708 ctx->shader->gs_prim_id_input = true;
709 ctx->shader->ps_prim_id_input = i;
710 break;
711 }
712 if (ctx->bc->chip_class >= EVERGREEN) {
713 if ((r = evergreen_interp_input(ctx, i)))
714 return r;
715 }
716 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
717 /* FIXME probably skip inputs if they aren't passed in the ring */
718 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
719 ctx->next_ring_offset += 16;
720 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
721 ctx->shader->gs_prim_id_input = true;
722 }
723 }
724 ctx->shader->ninput += count;
725 break;
726 case TGSI_FILE_OUTPUT:
727 for (j = 0; j < count; j++) {
728 i = ctx->shader->noutput + j;
729 assert(i < Elements(ctx->shader->output));
730 ctx->shader->output[i].name = d->Semantic.Name;
731 ctx->shader->output[i].sid = d->Semantic.Index + j;
732 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
733 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
734 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
735 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
736 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
737 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
738 switch (d->Semantic.Name) {
739 case TGSI_SEMANTIC_CLIPDIST:
740 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
741 ((d->Semantic.Index + j) << 2);
742 break;
743 case TGSI_SEMANTIC_PSIZE:
744 ctx->shader->vs_out_misc_write = 1;
745 ctx->shader->vs_out_point_size = 1;
746 break;
747 case TGSI_SEMANTIC_EDGEFLAG:
748 ctx->shader->vs_out_misc_write = 1;
749 ctx->shader->vs_out_edgeflag = 1;
750 ctx->edgeflag_output = i;
751 break;
752 case TGSI_SEMANTIC_VIEWPORT_INDEX:
753 ctx->shader->vs_out_misc_write = 1;
754 ctx->shader->vs_out_viewport = 1;
755 break;
756 case TGSI_SEMANTIC_LAYER:
757 ctx->shader->vs_out_misc_write = 1;
758 ctx->shader->vs_out_layer = 1;
759 break;
760 case TGSI_SEMANTIC_CLIPVERTEX:
761 ctx->clip_vertex_write = TRUE;
762 ctx->cv_output = i;
763 break;
764 }
765 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
766 ctx->gs_out_ring_offset += 16;
767 }
768 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
769 switch (d->Semantic.Name) {
770 case TGSI_SEMANTIC_COLOR:
771 ctx->shader->nr_ps_max_color_exports++;
772 break;
773 }
774 }
775 }
776 ctx->shader->noutput += count;
777 break;
778 case TGSI_FILE_TEMPORARY:
779 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
780 if (d->Array.ArrayID) {
781 r600_add_gpr_array(ctx->shader,
782 ctx->file_offset[TGSI_FILE_TEMPORARY] +
783 d->Range.First,
784 d->Range.Last - d->Range.First + 1, 0x0F);
785 }
786 }
787 break;
788
789 case TGSI_FILE_CONSTANT:
790 case TGSI_FILE_SAMPLER:
791 case TGSI_FILE_SAMPLER_VIEW:
792 case TGSI_FILE_ADDRESS:
793 break;
794
795 case TGSI_FILE_SYSTEM_VALUE:
796 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
797 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
798 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
799 break; /* Already handled from allocate_system_value_inputs */
800 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
801 if (!ctx->native_integers) {
802 struct r600_bytecode_alu alu;
803 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
804
805 alu.op = ALU_OP1_INT_TO_FLT;
806 alu.src[0].sel = 0;
807 alu.src[0].chan = 3;
808
809 alu.dst.sel = 0;
810 alu.dst.chan = 3;
811 alu.dst.write = 1;
812 alu.last = 1;
813
814 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
815 return r;
816 }
817 break;
818 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
819 break;
820 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
821 break;
822 default:
823 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
824 return -EINVAL;
825 }
826 return 0;
827 }
828
829 static int r600_get_temp(struct r600_shader_ctx *ctx)
830 {
831 return ctx->temp_reg + ctx->max_driver_temp_used++;
832 }
833
834 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
835 {
836 struct tgsi_parse_context parse;
837 struct {
838 boolean enabled;
839 int *reg;
840 unsigned name, alternate_name;
841 } inputs[2] = {
842 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
843
844 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
845 };
846 int i, k, num_regs = 0;
847
848 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
849 return 0;
850 }
851
852 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
853 while (!tgsi_parse_end_of_tokens(&parse)) {
854 tgsi_parse_token(&parse);
855
856 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
857 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
858 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
859 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
860 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
861 {
862 int interpolate, location, k;
863
864 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
865 location = TGSI_INTERPOLATE_LOC_CENTER;
866 inputs[1].enabled = true; /* needs SAMPLEID */
867 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
868 location = TGSI_INTERPOLATE_LOC_CENTER;
869 /* Needs sample positions, currently those are always available */
870 } else {
871 location = TGSI_INTERPOLATE_LOC_CENTROID;
872 }
873
874 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
875 k = eg_get_interpolator_index(interpolate, location);
876 ctx->eg_interpolators[k].enabled = true;
877 }
878 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
879 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
880 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
881 for (k = 0; k < Elements(inputs); k++) {
882 if (d->Semantic.Name == inputs[k].name ||
883 d->Semantic.Name == inputs[k].alternate_name) {
884 inputs[k].enabled = true;
885 }
886 }
887 }
888 }
889 }
890
891 tgsi_parse_free(&parse);
892
893 for (i = 0; i < Elements(inputs); i++) {
894 boolean enabled = inputs[i].enabled;
895 int *reg = inputs[i].reg;
896 unsigned name = inputs[i].name;
897
898 if (enabled) {
899 int gpr = gpr_offset + num_regs++;
900
901 // add to inputs, allocate a gpr
902 k = ctx->shader->ninput ++;
903 ctx->shader->input[k].name = name;
904 ctx->shader->input[k].sid = 0;
905 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
906 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
907 *reg = ctx->shader->input[k].gpr = gpr;
908 }
909 }
910
911 return gpr_offset + num_regs;
912 }
913
914 /*
915 * for evergreen we need to scan the shader to find the number of GPRs we need to
916 * reserve for interpolation and system values
917 *
918 * we need to know if we are going to emit
919 * any sample or centroid inputs
920 * if perspective and linear are required
921 */
922 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
923 {
924 int i;
925 int num_baryc;
926 struct tgsi_parse_context parse;
927
928 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
929
930 for (i = 0; i < ctx->info.num_inputs; i++) {
931 int k;
932 /* skip position/face/mask/sampleid */
933 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
934 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
935 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
936 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
937 continue;
938
939 k = eg_get_interpolator_index(
940 ctx->info.input_interpolate[i],
941 ctx->info.input_interpolate_loc[i]);
942 if (k >= 0)
943 ctx->eg_interpolators[k].enabled = TRUE;
944 }
945
946 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
947 return 0;
948 }
949
950 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
951 while (!tgsi_parse_end_of_tokens(&parse)) {
952 tgsi_parse_token(&parse);
953
954 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
955 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
956 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
957 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
958 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
959 {
960 int interpolate, location, k;
961
962 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
963 location = TGSI_INTERPOLATE_LOC_CENTER;
964 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
965 location = TGSI_INTERPOLATE_LOC_CENTER;
966 } else {
967 location = TGSI_INTERPOLATE_LOC_CENTROID;
968 }
969
970 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
971 k = eg_get_interpolator_index(interpolate, location);
972 ctx->eg_interpolators[k].enabled = true;
973 }
974 }
975 }
976
977 tgsi_parse_free(&parse);
978
979 /* assign gpr to each interpolator according to priority */
980 num_baryc = 0;
981 for (i = 0; i < Elements(ctx->eg_interpolators); i++) {
982 if (ctx->eg_interpolators[i].enabled) {
983 ctx->eg_interpolators[i].ij_index = num_baryc;
984 num_baryc ++;
985 }
986 }
987
988 /* XXX PULL MODEL and LINE STIPPLE */
989
990 num_baryc = (num_baryc + 1) >> 1;
991 return allocate_system_value_inputs(ctx, num_baryc);
992 }
993
994 /* sample_id_sel == NULL means fetch for current sample */
995 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
996 {
997 struct r600_bytecode_vtx vtx;
998 int r, t1;
999
1000 assert(ctx->fixed_pt_position_gpr != -1);
1001
1002 t1 = r600_get_temp(ctx);
1003
1004 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1005 vtx.op = FETCH_OP_VFETCH;
1006 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1007 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1008 if (sample_id == NULL) {
1009 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1010 vtx.src_sel_x = 3;
1011 }
1012 else {
1013 struct r600_bytecode_alu alu;
1014
1015 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1016 alu.op = ALU_OP1_MOV;
1017 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1018 alu.dst.sel = t1;
1019 alu.dst.write = 1;
1020 alu.last = 1;
1021 r = r600_bytecode_add_alu(ctx->bc, &alu);
1022 if (r)
1023 return r;
1024
1025 vtx.src_gpr = t1;
1026 vtx.src_sel_x = 0;
1027 }
1028 vtx.mega_fetch_count = 16;
1029 vtx.dst_gpr = t1;
1030 vtx.dst_sel_x = 0;
1031 vtx.dst_sel_y = 1;
1032 vtx.dst_sel_z = 2;
1033 vtx.dst_sel_w = 3;
1034 vtx.data_format = FMT_32_32_32_32_FLOAT;
1035 vtx.num_format_all = 2;
1036 vtx.format_comp_all = 1;
1037 vtx.use_const_fields = 0;
1038 vtx.offset = 1; // first element is size of buffer
1039 vtx.endian = r600_endian_swap(32);
1040 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1041
1042 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1043 if (r)
1044 return r;
1045
1046 return t1;
1047 }
1048
1049 static void tgsi_src(struct r600_shader_ctx *ctx,
1050 const struct tgsi_full_src_register *tgsi_src,
1051 struct r600_shader_src *r600_src)
1052 {
1053 memset(r600_src, 0, sizeof(*r600_src));
1054 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1055 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1056 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1057 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1058 r600_src->neg = tgsi_src->Register.Negate;
1059 r600_src->abs = tgsi_src->Register.Absolute;
1060
1061 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1062 int index;
1063 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1064 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1065 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1066
1067 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1068 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1069 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1070 return;
1071 }
1072 index = tgsi_src->Register.Index;
1073 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1074 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1075 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1076 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1077 r600_src->swizzle[0] = 2; // Z value
1078 r600_src->swizzle[1] = 2;
1079 r600_src->swizzle[2] = 2;
1080 r600_src->swizzle[3] = 2;
1081 r600_src->sel = ctx->face_gpr;
1082 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1083 r600_src->swizzle[0] = 3; // W value
1084 r600_src->swizzle[1] = 3;
1085 r600_src->swizzle[2] = 3;
1086 r600_src->swizzle[3] = 3;
1087 r600_src->sel = ctx->fixed_pt_position_gpr;
1088 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1089 r600_src->swizzle[0] = 0;
1090 r600_src->swizzle[1] = 1;
1091 r600_src->swizzle[2] = 4;
1092 r600_src->swizzle[3] = 4;
1093 r600_src->sel = load_sample_position(ctx, NULL, -1);
1094 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1095 r600_src->swizzle[0] = 3;
1096 r600_src->swizzle[1] = 3;
1097 r600_src->swizzle[2] = 3;
1098 r600_src->swizzle[3] = 3;
1099 r600_src->sel = 0;
1100 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1101 r600_src->swizzle[0] = 0;
1102 r600_src->swizzle[1] = 0;
1103 r600_src->swizzle[2] = 0;
1104 r600_src->swizzle[3] = 0;
1105 r600_src->sel = 0;
1106 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1107 r600_src->swizzle[0] = 3;
1108 r600_src->swizzle[1] = 3;
1109 r600_src->swizzle[2] = 3;
1110 r600_src->swizzle[3] = 3;
1111 r600_src->sel = 1;
1112 }
1113 } else {
1114 if (tgsi_src->Register.Indirect)
1115 r600_src->rel = V_SQ_REL_RELATIVE;
1116 r600_src->sel = tgsi_src->Register.Index;
1117 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1118 }
1119 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1120 if (tgsi_src->Register.Dimension) {
1121 r600_src->kc_bank = tgsi_src->Dimension.Index;
1122 if (tgsi_src->Dimension.Indirect) {
1123 r600_src->kc_rel = 1;
1124 }
1125 }
1126 }
1127 }
1128
1129 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1130 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1131 unsigned int dst_reg)
1132 {
1133 struct r600_bytecode_vtx vtx;
1134 unsigned int ar_reg;
1135 int r;
1136
1137 if (offset) {
1138 struct r600_bytecode_alu alu;
1139
1140 memset(&alu, 0, sizeof(alu));
1141
1142 alu.op = ALU_OP2_ADD_INT;
1143 alu.src[0].sel = ctx->bc->ar_reg;
1144 alu.src[0].chan = ar_chan;
1145
1146 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1147 alu.src[1].value = offset;
1148
1149 alu.dst.sel = dst_reg;
1150 alu.dst.chan = ar_chan;
1151 alu.dst.write = 1;
1152 alu.last = 1;
1153
1154 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1155 return r;
1156
1157 ar_reg = dst_reg;
1158 } else {
1159 ar_reg = ctx->bc->ar_reg;
1160 }
1161
1162 memset(&vtx, 0, sizeof(vtx));
1163 vtx.buffer_id = cb_idx;
1164 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1165 vtx.src_gpr = ar_reg;
1166 vtx.src_sel_x = ar_chan;
1167 vtx.mega_fetch_count = 16;
1168 vtx.dst_gpr = dst_reg;
1169 vtx.dst_sel_x = 0; /* SEL_X */
1170 vtx.dst_sel_y = 1; /* SEL_Y */
1171 vtx.dst_sel_z = 2; /* SEL_Z */
1172 vtx.dst_sel_w = 3; /* SEL_W */
1173 vtx.data_format = FMT_32_32_32_32_FLOAT;
1174 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1175 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1176 vtx.endian = r600_endian_swap(32);
1177 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1178
1179 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1180 return r;
1181
1182 return 0;
1183 }
1184
1185 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1186 {
1187 struct r600_bytecode_vtx vtx;
1188 int r;
1189 unsigned index = src->Register.Index;
1190 unsigned vtx_id = src->Dimension.Index;
1191 int offset_reg = vtx_id / 3;
1192 int offset_chan = vtx_id % 3;
1193
1194 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1195 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1196
1197 if (offset_reg == 0 && offset_chan == 2)
1198 offset_chan = 3;
1199
1200 if (src->Dimension.Indirect) {
1201 int treg[3];
1202 int t2;
1203 struct r600_bytecode_alu alu;
1204 int r, i;
1205
1206 /* you have got to be shitting me -
1207 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1208 at least this is what fglrx seems to do. */
1209 for (i = 0; i < 3; i++) {
1210 treg[i] = r600_get_temp(ctx);
1211 }
1212 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1213
1214 t2 = r600_get_temp(ctx);
1215 for (i = 0; i < 3; i++) {
1216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1217 alu.op = ALU_OP1_MOV;
1218 alu.src[0].sel = 0;
1219 alu.src[0].chan = i == 2 ? 3 : i;
1220 alu.dst.sel = treg[i];
1221 alu.dst.chan = 0;
1222 alu.dst.write = 1;
1223 alu.last = 1;
1224 r = r600_bytecode_add_alu(ctx->bc, &alu);
1225 if (r)
1226 return r;
1227 }
1228 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1229 alu.op = ALU_OP1_MOV;
1230 alu.src[0].sel = treg[0];
1231 alu.src[0].rel = 1;
1232 alu.dst.sel = t2;
1233 alu.dst.write = 1;
1234 alu.last = 1;
1235 r = r600_bytecode_add_alu(ctx->bc, &alu);
1236 if (r)
1237 return r;
1238 offset_reg = t2;
1239 }
1240
1241
1242 memset(&vtx, 0, sizeof(vtx));
1243 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1244 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1245 vtx.src_gpr = offset_reg;
1246 vtx.src_sel_x = offset_chan;
1247 vtx.offset = index * 16; /*bytes*/
1248 vtx.mega_fetch_count = 16;
1249 vtx.dst_gpr = dst_reg;
1250 vtx.dst_sel_x = 0; /* SEL_X */
1251 vtx.dst_sel_y = 1; /* SEL_Y */
1252 vtx.dst_sel_z = 2; /* SEL_Z */
1253 vtx.dst_sel_w = 3; /* SEL_W */
1254 if (ctx->bc->chip_class >= EVERGREEN) {
1255 vtx.use_const_fields = 1;
1256 } else {
1257 vtx.data_format = FMT_32_32_32_32_FLOAT;
1258 }
1259
1260 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1261 return r;
1262
1263 return 0;
1264 }
1265
1266 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1267 {
1268 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1269 int i;
1270
1271 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1272 struct tgsi_full_src_register *src = &inst->Src[i];
1273
1274 if (src->Register.File == TGSI_FILE_INPUT) {
1275 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1276 /* primitive id is in R0.z */
1277 ctx->src[i].sel = 0;
1278 ctx->src[i].swizzle[0] = 2;
1279 }
1280 }
1281 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1282 int treg = r600_get_temp(ctx);
1283
1284 fetch_gs_input(ctx, src, treg);
1285 ctx->src[i].sel = treg;
1286 }
1287 }
1288 return 0;
1289 }
1290
1291 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1292 {
1293 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1294 struct r600_bytecode_alu alu;
1295 int i, j, k, nconst, r;
1296
1297 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1298 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1299 nconst++;
1300 }
1301 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1302 }
1303 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1304 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1305 continue;
1306 }
1307
1308 if (ctx->src[i].rel) {
1309 int chan = inst->Src[i].Indirect.Swizzle;
1310 int treg = r600_get_temp(ctx);
1311 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1312 return r;
1313
1314 ctx->src[i].kc_bank = 0;
1315 ctx->src[i].kc_rel = 0;
1316 ctx->src[i].sel = treg;
1317 ctx->src[i].rel = 0;
1318 j--;
1319 } else if (j > 0) {
1320 int treg = r600_get_temp(ctx);
1321 for (k = 0; k < 4; k++) {
1322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1323 alu.op = ALU_OP1_MOV;
1324 alu.src[0].sel = ctx->src[i].sel;
1325 alu.src[0].chan = k;
1326 alu.src[0].rel = ctx->src[i].rel;
1327 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1328 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1329 alu.dst.sel = treg;
1330 alu.dst.chan = k;
1331 alu.dst.write = 1;
1332 if (k == 3)
1333 alu.last = 1;
1334 r = r600_bytecode_add_alu(ctx->bc, &alu);
1335 if (r)
1336 return r;
1337 }
1338 ctx->src[i].sel = treg;
1339 ctx->src[i].rel =0;
1340 j--;
1341 }
1342 }
1343 return 0;
1344 }
1345
1346 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1347 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1348 {
1349 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1350 struct r600_bytecode_alu alu;
1351 int i, j, k, nliteral, r;
1352
1353 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1354 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1355 nliteral++;
1356 }
1357 }
1358 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1359 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1360 int treg = r600_get_temp(ctx);
1361 for (k = 0; k < 4; k++) {
1362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1363 alu.op = ALU_OP1_MOV;
1364 alu.src[0].sel = ctx->src[i].sel;
1365 alu.src[0].chan = k;
1366 alu.src[0].value = ctx->src[i].value[k];
1367 alu.dst.sel = treg;
1368 alu.dst.chan = k;
1369 alu.dst.write = 1;
1370 if (k == 3)
1371 alu.last = 1;
1372 r = r600_bytecode_add_alu(ctx->bc, &alu);
1373 if (r)
1374 return r;
1375 }
1376 ctx->src[i].sel = treg;
1377 j--;
1378 }
1379 }
1380 return 0;
1381 }
1382
1383 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1384 {
1385 int i, r, count = ctx->shader->ninput;
1386
1387 for (i = 0; i < count; i++) {
1388 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1389 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1390 if (r)
1391 return r;
1392 }
1393 }
1394 return 0;
1395 }
1396
1397 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
1398 int stream, unsigned *stream_item_size)
1399 {
1400 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1401 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
1402 int i, j, r;
1403
1404 /* Sanity checking. */
1405 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
1406 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1407 r = -EINVAL;
1408 goto out_err;
1409 }
1410 for (i = 0; i < so->num_outputs; i++) {
1411 if (so->output[i].output_buffer >= 4) {
1412 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1413 so->output[i].output_buffer);
1414 r = -EINVAL;
1415 goto out_err;
1416 }
1417 }
1418
1419 /* Initialize locations where the outputs are stored. */
1420 for (i = 0; i < so->num_outputs; i++) {
1421
1422 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1423 start_comp[i] = so->output[i].start_component;
1424 /* Lower outputs with dst_offset < start_component.
1425 *
1426 * We can only output 4D vectors with a write mask, e.g. we can
1427 * only output the W component at offset 3, etc. If we want
1428 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1429 * to move it to X and output X. */
1430 if (so->output[i].dst_offset < so->output[i].start_component) {
1431 unsigned tmp = r600_get_temp(ctx);
1432
1433 for (j = 0; j < so->output[i].num_components; j++) {
1434 struct r600_bytecode_alu alu;
1435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1436 alu.op = ALU_OP1_MOV;
1437 alu.src[0].sel = so_gpr[i];
1438 alu.src[0].chan = so->output[i].start_component + j;
1439
1440 alu.dst.sel = tmp;
1441 alu.dst.chan = j;
1442 alu.dst.write = 1;
1443 if (j == so->output[i].num_components - 1)
1444 alu.last = 1;
1445 r = r600_bytecode_add_alu(ctx->bc, &alu);
1446 if (r)
1447 return r;
1448 }
1449 start_comp[i] = 0;
1450 so_gpr[i] = tmp;
1451 }
1452 }
1453
1454 /* Write outputs to buffers. */
1455 for (i = 0; i < so->num_outputs; i++) {
1456 struct r600_bytecode_output output;
1457
1458 if (stream != -1 && stream != so->output[i].output_buffer)
1459 continue;
1460
1461 memset(&output, 0, sizeof(struct r600_bytecode_output));
1462 output.gpr = so_gpr[i];
1463 output.elem_size = so->output[i].num_components - 1;
1464 if (output.elem_size == 2)
1465 output.elem_size = 3; // 3 not supported, write 4 with junk at end
1466 output.array_base = so->output[i].dst_offset - start_comp[i];
1467 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1468 output.burst_count = 1;
1469 /* array_size is an upper limit for the burst_count
1470 * with MEM_STREAM instructions */
1471 output.array_size = 0xFFF;
1472 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
1473
1474 if (ctx->bc->chip_class >= EVERGREEN) {
1475 switch (so->output[i].output_buffer) {
1476 case 0:
1477 output.op = CF_OP_MEM_STREAM0_BUF0;
1478 break;
1479 case 1:
1480 output.op = CF_OP_MEM_STREAM0_BUF1;
1481 break;
1482 case 2:
1483 output.op = CF_OP_MEM_STREAM0_BUF2;
1484 break;
1485 case 3:
1486 output.op = CF_OP_MEM_STREAM0_BUF3;
1487 break;
1488 }
1489 output.op += so->output[i].stream * 4;
1490 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
1491 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
1492 } else {
1493 switch (so->output[i].output_buffer) {
1494 case 0:
1495 output.op = CF_OP_MEM_STREAM0;
1496 break;
1497 case 1:
1498 output.op = CF_OP_MEM_STREAM1;
1499 break;
1500 case 2:
1501 output.op = CF_OP_MEM_STREAM2;
1502 break;
1503 case 3:
1504 output.op = CF_OP_MEM_STREAM3;
1505 break;
1506 }
1507 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
1508 }
1509 r = r600_bytecode_add_output(ctx->bc, &output);
1510 if (r)
1511 goto out_err;
1512 }
1513 return 0;
1514 out_err:
1515 return r;
1516 }
1517
1518 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1519 {
1520 struct r600_bytecode_alu alu;
1521 unsigned reg;
1522
1523 if (!ctx->shader->vs_out_edgeflag)
1524 return;
1525
1526 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1527
1528 /* clamp(x, 0, 1) */
1529 memset(&alu, 0, sizeof(alu));
1530 alu.op = ALU_OP1_MOV;
1531 alu.src[0].sel = reg;
1532 alu.dst.sel = reg;
1533 alu.dst.write = 1;
1534 alu.dst.clamp = 1;
1535 alu.last = 1;
1536 r600_bytecode_add_alu(ctx->bc, &alu);
1537
1538 memset(&alu, 0, sizeof(alu));
1539 alu.op = ALU_OP1_FLT_TO_INT;
1540 alu.src[0].sel = reg;
1541 alu.dst.sel = reg;
1542 alu.dst.write = 1;
1543 alu.last = 1;
1544 r600_bytecode_add_alu(ctx->bc, &alu);
1545 }
1546
1547 static int generate_gs_copy_shader(struct r600_context *rctx,
1548 struct r600_pipe_shader *gs,
1549 struct pipe_stream_output_info *so)
1550 {
1551 struct r600_shader_ctx ctx = {};
1552 struct r600_shader *gs_shader = &gs->shader;
1553 struct r600_pipe_shader *cshader;
1554 int ocnt = gs_shader->noutput;
1555 struct r600_bytecode_alu alu;
1556 struct r600_bytecode_vtx vtx;
1557 struct r600_bytecode_output output;
1558 struct r600_bytecode_cf *cf_jump, *cf_pop,
1559 *last_exp_pos = NULL, *last_exp_param = NULL;
1560 int i, j, next_clip_pos = 61, next_param = 0;
1561 int ring;
1562
1563 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1564 if (!cshader)
1565 return 0;
1566
1567 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1568 sizeof(struct r600_shader_io));
1569
1570 cshader->shader.noutput = ocnt;
1571
1572 ctx.shader = &cshader->shader;
1573 ctx.bc = &ctx.shader->bc;
1574 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1575
1576 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1577 rctx->screen->has_compressed_msaa_texturing);
1578
1579 ctx.bc->isa = rctx->isa;
1580
1581 cf_jump = NULL;
1582 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
1583
1584 /* R0.x = R0.x & 0x3fffffff */
1585 memset(&alu, 0, sizeof(alu));
1586 alu.op = ALU_OP2_AND_INT;
1587 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1588 alu.src[1].value = 0x3fffffff;
1589 alu.dst.write = 1;
1590 r600_bytecode_add_alu(ctx.bc, &alu);
1591
1592 /* R0.y = R0.x >> 30 */
1593 memset(&alu, 0, sizeof(alu));
1594 alu.op = ALU_OP2_LSHR_INT;
1595 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1596 alu.src[1].value = 0x1e;
1597 alu.dst.chan = 1;
1598 alu.dst.write = 1;
1599 alu.last = 1;
1600 r600_bytecode_add_alu(ctx.bc, &alu);
1601
1602 /* fetch vertex data from GSVS ring */
1603 for (i = 0; i < ocnt; ++i) {
1604 struct r600_shader_io *out = &ctx.shader->output[i];
1605
1606 out->gpr = i + 1;
1607 out->ring_offset = i * 16;
1608
1609 memset(&vtx, 0, sizeof(vtx));
1610 vtx.op = FETCH_OP_VFETCH;
1611 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1612 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1613 vtx.mega_fetch_count = 16;
1614 vtx.offset = out->ring_offset;
1615 vtx.dst_gpr = out->gpr;
1616 vtx.src_gpr = 0;
1617 vtx.dst_sel_x = 0;
1618 vtx.dst_sel_y = 1;
1619 vtx.dst_sel_z = 2;
1620 vtx.dst_sel_w = 3;
1621 if (rctx->b.chip_class >= EVERGREEN) {
1622 vtx.use_const_fields = 1;
1623 } else {
1624 vtx.data_format = FMT_32_32_32_32_FLOAT;
1625 }
1626
1627 r600_bytecode_add_vtx(ctx.bc, &vtx);
1628 }
1629 ctx.temp_reg = i + 1;
1630 for (ring = 3; ring >= 0; --ring) {
1631 bool enabled = false;
1632 for (i = 0; i < so->num_outputs; i++) {
1633 if (so->output[i].stream == ring) {
1634 enabled = true;
1635 break;
1636 }
1637 }
1638 if (ring != 0 && !enabled) {
1639 cshader->shader.ring_item_sizes[ring] = 0;
1640 continue;
1641 }
1642
1643 if (cf_jump) {
1644 // Patch up jump label
1645 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1646 cf_pop = ctx.bc->cf_last;
1647
1648 cf_jump->cf_addr = cf_pop->id + 2;
1649 cf_jump->pop_count = 1;
1650 cf_pop->cf_addr = cf_pop->id + 2;
1651 cf_pop->pop_count = 1;
1652 }
1653
1654 /* PRED_SETE_INT __, R0.y, ring */
1655 memset(&alu, 0, sizeof(alu));
1656 alu.op = ALU_OP2_PRED_SETE_INT;
1657 alu.src[0].chan = 1;
1658 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1659 alu.src[1].value = ring;
1660 alu.execute_mask = 1;
1661 alu.update_pred = 1;
1662 alu.last = 1;
1663 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1664
1665 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1666 cf_jump = ctx.bc->cf_last;
1667
1668 if (enabled)
1669 emit_streamout(&ctx, so, ring, &cshader->shader.ring_item_sizes[ring]);
1670 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
1671 }
1672
1673 /* bc adds nops - copy it */
1674 if (ctx.bc->chip_class == R600) {
1675 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1676 alu.op = ALU_OP0_NOP;
1677 alu.last = 1;
1678 r600_bytecode_add_alu(ctx.bc, &alu);
1679
1680 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1681 }
1682
1683 /* export vertex data */
1684 /* XXX factor out common code with r600_shader_from_tgsi ? */
1685 for (i = 0; i < ocnt; ++i) {
1686 struct r600_shader_io *out = &ctx.shader->output[i];
1687 bool instream0 = true;
1688 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1689 continue;
1690
1691 for (j = 0; j < so->num_outputs; j++) {
1692 if (so->output[j].register_index == i) {
1693 if (so->output[j].stream == 0)
1694 break;
1695 if (so->output[j].stream > 0)
1696 instream0 = false;
1697 }
1698 }
1699 if (!instream0)
1700 continue;
1701 memset(&output, 0, sizeof(output));
1702 output.gpr = out->gpr;
1703 output.elem_size = 3;
1704 output.swizzle_x = 0;
1705 output.swizzle_y = 1;
1706 output.swizzle_z = 2;
1707 output.swizzle_w = 3;
1708 output.burst_count = 1;
1709 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1710 output.op = CF_OP_EXPORT;
1711 switch (out->name) {
1712 case TGSI_SEMANTIC_POSITION:
1713 output.array_base = 60;
1714 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1715 break;
1716
1717 case TGSI_SEMANTIC_PSIZE:
1718 output.array_base = 61;
1719 if (next_clip_pos == 61)
1720 next_clip_pos = 62;
1721 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1722 output.swizzle_y = 7;
1723 output.swizzle_z = 7;
1724 output.swizzle_w = 7;
1725 ctx.shader->vs_out_misc_write = 1;
1726 ctx.shader->vs_out_point_size = 1;
1727 break;
1728 case TGSI_SEMANTIC_LAYER:
1729 if (out->spi_sid) {
1730 /* duplicate it as PARAM to pass to the pixel shader */
1731 output.array_base = next_param++;
1732 r600_bytecode_add_output(ctx.bc, &output);
1733 last_exp_param = ctx.bc->cf_last;
1734 }
1735 output.array_base = 61;
1736 if (next_clip_pos == 61)
1737 next_clip_pos = 62;
1738 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1739 output.swizzle_x = 7;
1740 output.swizzle_y = 7;
1741 output.swizzle_z = 0;
1742 output.swizzle_w = 7;
1743 ctx.shader->vs_out_misc_write = 1;
1744 ctx.shader->vs_out_layer = 1;
1745 break;
1746 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1747 if (out->spi_sid) {
1748 /* duplicate it as PARAM to pass to the pixel shader */
1749 output.array_base = next_param++;
1750 r600_bytecode_add_output(ctx.bc, &output);
1751 last_exp_param = ctx.bc->cf_last;
1752 }
1753 output.array_base = 61;
1754 if (next_clip_pos == 61)
1755 next_clip_pos = 62;
1756 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1757 ctx.shader->vs_out_misc_write = 1;
1758 ctx.shader->vs_out_viewport = 1;
1759 output.swizzle_x = 7;
1760 output.swizzle_y = 7;
1761 output.swizzle_z = 7;
1762 output.swizzle_w = 0;
1763 break;
1764 case TGSI_SEMANTIC_CLIPDIST:
1765 /* spi_sid is 0 for clipdistance outputs that were generated
1766 * for clipvertex - we don't need to pass them to PS */
1767 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1768 if (out->spi_sid) {
1769 /* duplicate it as PARAM to pass to the pixel shader */
1770 output.array_base = next_param++;
1771 r600_bytecode_add_output(ctx.bc, &output);
1772 last_exp_param = ctx.bc->cf_last;
1773 }
1774 output.array_base = next_clip_pos++;
1775 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1776 break;
1777 case TGSI_SEMANTIC_FOG:
1778 output.swizzle_y = 4; /* 0 */
1779 output.swizzle_z = 4; /* 0 */
1780 output.swizzle_w = 5; /* 1 */
1781 break;
1782 default:
1783 output.array_base = next_param++;
1784 break;
1785 }
1786 r600_bytecode_add_output(ctx.bc, &output);
1787 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1788 last_exp_param = ctx.bc->cf_last;
1789 else
1790 last_exp_pos = ctx.bc->cf_last;
1791 }
1792
1793 if (!last_exp_pos) {
1794 memset(&output, 0, sizeof(output));
1795 output.gpr = 0;
1796 output.elem_size = 3;
1797 output.swizzle_x = 7;
1798 output.swizzle_y = 7;
1799 output.swizzle_z = 7;
1800 output.swizzle_w = 7;
1801 output.burst_count = 1;
1802 output.type = 2;
1803 output.op = CF_OP_EXPORT;
1804 output.array_base = 60;
1805 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1806 r600_bytecode_add_output(ctx.bc, &output);
1807 last_exp_pos = ctx.bc->cf_last;
1808 }
1809
1810 if (!last_exp_param) {
1811 memset(&output, 0, sizeof(output));
1812 output.gpr = 0;
1813 output.elem_size = 3;
1814 output.swizzle_x = 7;
1815 output.swizzle_y = 7;
1816 output.swizzle_z = 7;
1817 output.swizzle_w = 7;
1818 output.burst_count = 1;
1819 output.type = 2;
1820 output.op = CF_OP_EXPORT;
1821 output.array_base = next_param++;
1822 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1823 r600_bytecode_add_output(ctx.bc, &output);
1824 last_exp_param = ctx.bc->cf_last;
1825 }
1826
1827 last_exp_pos->op = CF_OP_EXPORT_DONE;
1828 last_exp_param->op = CF_OP_EXPORT_DONE;
1829
1830 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1831 cf_pop = ctx.bc->cf_last;
1832
1833 cf_jump->cf_addr = cf_pop->id + 2;
1834 cf_jump->pop_count = 1;
1835 cf_pop->cf_addr = cf_pop->id + 2;
1836 cf_pop->pop_count = 1;
1837
1838 if (ctx.bc->chip_class == CAYMAN)
1839 cm_bytecode_add_cf_end(ctx.bc);
1840 else {
1841 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1842 ctx.bc->cf_last->end_of_program = 1;
1843 }
1844
1845 gs->gs_copy_shader = cshader;
1846 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
1847
1848 ctx.bc->nstack = 1;
1849
1850 return r600_bytecode_build(ctx.bc);
1851 }
1852
1853 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
1854 {
1855 if (ind) {
1856 struct r600_bytecode_alu alu;
1857 int r;
1858
1859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1860 alu.op = ALU_OP2_ADD_INT;
1861 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
1862 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1863 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1864 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
1865 alu.dst.write = 1;
1866 alu.last = 1;
1867 r = r600_bytecode_add_alu(ctx->bc, &alu);
1868 if (r)
1869 return r;
1870 }
1871 return 0;
1872 }
1873
1874 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
1875 {
1876 struct r600_bytecode_output output;
1877 int i, k, ring_offset;
1878 int effective_stream = stream == -1 ? 0 : stream;
1879 int idx = 0;
1880
1881 for (i = 0; i < ctx->shader->noutput; i++) {
1882 if (ctx->gs_for_vs) {
1883 /* for ES we need to lookup corresponding ring offset expected by GS
1884 * (map this output to GS input by name and sid) */
1885 /* FIXME precompute offsets */
1886 ring_offset = -1;
1887 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1888 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1889 struct r600_shader_io *out = &ctx->shader->output[i];
1890 if (in->name == out->name && in->sid == out->sid)
1891 ring_offset = in->ring_offset;
1892 }
1893
1894 if (ring_offset == -1)
1895 continue;
1896 } else {
1897 ring_offset = idx * 16;
1898 idx++;
1899 }
1900
1901 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
1902 continue;
1903 /* next_ring_offset after parsing input decls contains total size of
1904 * single vertex data, gs_next_vertex - current vertex index */
1905 if (!ind)
1906 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1907
1908 memset(&output, 0, sizeof(struct r600_bytecode_output));
1909 output.gpr = ctx->shader->output[i].gpr;
1910 output.elem_size = 3;
1911 output.comp_mask = 0xF;
1912 output.burst_count = 1;
1913
1914 if (ind)
1915 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1916 else
1917 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1918
1919 switch (stream) {
1920 default:
1921 case 0:
1922 output.op = CF_OP_MEM_RING; break;
1923 case 1:
1924 output.op = CF_OP_MEM_RING1; break;
1925 case 2:
1926 output.op = CF_OP_MEM_RING2; break;
1927 case 3:
1928 output.op = CF_OP_MEM_RING3; break;
1929 }
1930
1931 if (ind) {
1932 output.array_base = ring_offset >> 2; /* in dwords */
1933 output.array_size = 0xfff;
1934 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
1935 } else
1936 output.array_base = ring_offset >> 2; /* in dwords */
1937 r600_bytecode_add_output(ctx->bc, &output);
1938 }
1939
1940 ++ctx->gs_next_vertex;
1941 return 0;
1942 }
1943
1944 static int r600_shader_from_tgsi(struct r600_context *rctx,
1945 struct r600_pipe_shader *pipeshader,
1946 union r600_shader_key key)
1947 {
1948 struct r600_screen *rscreen = rctx->screen;
1949 struct r600_shader *shader = &pipeshader->shader;
1950 struct tgsi_token *tokens = pipeshader->selector->tokens;
1951 struct pipe_stream_output_info so = pipeshader->selector->so;
1952 struct tgsi_full_immediate *immediate;
1953 struct r600_shader_ctx ctx;
1954 struct r600_bytecode_output output[32];
1955 unsigned output_done, noutput;
1956 unsigned opcode;
1957 int i, j, k, r = 0;
1958 int next_param_base = 0, next_clip_base;
1959 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
1960 /* Declarations used by llvm code */
1961 bool use_llvm = false;
1962 bool indirect_gprs;
1963 bool ring_outputs = false;
1964 bool pos_emitted = false;
1965
1966 #ifdef R600_USE_LLVM
1967 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
1968 #endif
1969 ctx.bc = &shader->bc;
1970 ctx.shader = shader;
1971 ctx.native_integers = true;
1972
1973
1974 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1975 rscreen->has_compressed_msaa_texturing);
1976 ctx.tokens = tokens;
1977 tgsi_scan_shader(tokens, &ctx.info);
1978 shader->indirect_files = ctx.info.indirect_files;
1979
1980 shader->uses_doubles = ctx.info.uses_doubles;
1981
1982 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
1983 tgsi_parse_init(&ctx.parse, tokens);
1984 ctx.type = ctx.info.processor;
1985 shader->processor_type = ctx.type;
1986 ctx.bc->type = shader->processor_type;
1987
1988 switch (ctx.type) {
1989 case TGSI_PROCESSOR_VERTEX:
1990 shader->vs_as_gs_a = key.vs.as_gs_a;
1991 shader->vs_as_es = key.vs.as_es;
1992 shader->vs_as_ls = key.vs.as_ls;
1993 if (shader->vs_as_es)
1994 ring_outputs = true;
1995 break;
1996 case TGSI_PROCESSOR_GEOMETRY:
1997 ring_outputs = true;
1998 break;
1999 case TGSI_PROCESSOR_TESS_CTRL:
2000 shader->tcs_prim_mode = key.tcs.prim_mode;
2001 break;
2002 case TGSI_PROCESSOR_TESS_EVAL:
2003 shader->tes_as_es = key.tes.as_es;
2004 if (shader->tes_as_es)
2005 ring_outputs = true;
2006 break;
2007 case TGSI_PROCESSOR_FRAGMENT:
2008 shader->two_side = key.ps.color_two_side;
2009 break;
2010 default:
2011 break;
2012 }
2013
2014 if (shader->vs_as_es || shader->tes_as_es) {
2015 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
2016 } else {
2017 ctx.gs_for_vs = NULL;
2018 }
2019
2020 ctx.next_ring_offset = 0;
2021 ctx.gs_out_ring_offset = 0;
2022 ctx.gs_next_vertex = 0;
2023 ctx.gs_stream_output_info = &so;
2024
2025 ctx.face_gpr = -1;
2026 ctx.fixed_pt_position_gpr = -1;
2027 ctx.fragcoord_input = -1;
2028 ctx.colors_used = 0;
2029 ctx.clip_vertex_write = 0;
2030
2031 shader->nr_ps_color_exports = 0;
2032 shader->nr_ps_max_color_exports = 0;
2033
2034
2035 /* register allocations */
2036 /* Values [0,127] correspond to GPR[0..127].
2037 * Values [128,159] correspond to constant buffer bank 0
2038 * Values [160,191] correspond to constant buffer bank 1
2039 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
2040 * Values [256,287] correspond to constant buffer bank 2 (EG)
2041 * Values [288,319] correspond to constant buffer bank 3 (EG)
2042 * Other special values are shown in the list below.
2043 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
2044 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
2045 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
2046 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
2047 * 248 SQ_ALU_SRC_0: special constant 0.0.
2048 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
2049 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
2050 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
2051 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
2052 * 253 SQ_ALU_SRC_LITERAL: literal constant.
2053 * 254 SQ_ALU_SRC_PV: previous vector result.
2054 * 255 SQ_ALU_SRC_PS: previous scalar result.
2055 */
2056 for (i = 0; i < TGSI_FILE_COUNT; i++) {
2057 ctx.file_offset[i] = 0;
2058 }
2059
2060 #ifdef R600_USE_LLVM
2061 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
2062 fprintf(stderr, "Warning: R600 LLVM backend does not support "
2063 "indirect adressing. Falling back to TGSI "
2064 "backend.\n");
2065 use_llvm = 0;
2066 }
2067 #endif
2068 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
2069 ctx.file_offset[TGSI_FILE_INPUT] = 1;
2070 if (!use_llvm) {
2071 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
2072 }
2073 }
2074 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
2075 if (ctx.bc->chip_class >= EVERGREEN)
2076 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
2077 else
2078 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
2079 }
2080 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2081 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
2082 ctx.file_offset[TGSI_FILE_INPUT] = 2;
2083 }
2084 ctx.use_llvm = use_llvm;
2085
2086 if (use_llvm) {
2087 ctx.file_offset[TGSI_FILE_OUTPUT] =
2088 ctx.file_offset[TGSI_FILE_INPUT];
2089 } else {
2090 ctx.file_offset[TGSI_FILE_OUTPUT] =
2091 ctx.file_offset[TGSI_FILE_INPUT] +
2092 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2093 }
2094 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
2095 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
2096
2097 /* Outside the GPR range. This will be translated to one of the
2098 * kcache banks later. */
2099 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
2100
2101 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
2102 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
2103 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
2104 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
2105 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
2106
2107 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2108 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
2109 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
2110 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
2111 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
2112 ctx.temp_reg = ctx.bc->ar_reg + 7;
2113 } else {
2114 ctx.temp_reg = ctx.bc->ar_reg + 3;
2115 }
2116
2117 shader->max_arrays = 0;
2118 shader->num_arrays = 0;
2119 if (indirect_gprs) {
2120
2121 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
2122 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
2123 ctx.file_offset[TGSI_FILE_OUTPUT] -
2124 ctx.file_offset[TGSI_FILE_INPUT],
2125 0x0F);
2126 }
2127 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
2128 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
2129 ctx.file_offset[TGSI_FILE_TEMPORARY] -
2130 ctx.file_offset[TGSI_FILE_OUTPUT],
2131 0x0F);
2132 }
2133 }
2134
2135 ctx.nliterals = 0;
2136 ctx.literals = NULL;
2137
2138 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS];
2139 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2140 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
2141
2142 if (shader->vs_as_gs_a)
2143 vs_add_primid_output(&ctx, key.vs.prim_id_out);
2144
2145 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2146 tgsi_parse_token(&ctx.parse);
2147 switch (ctx.parse.FullToken.Token.Type) {
2148 case TGSI_TOKEN_TYPE_IMMEDIATE:
2149 immediate = &ctx.parse.FullToken.FullImmediate;
2150 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
2151 if(ctx.literals == NULL) {
2152 r = -ENOMEM;
2153 goto out_err;
2154 }
2155 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
2156 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
2157 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
2158 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
2159 ctx.nliterals++;
2160 break;
2161 case TGSI_TOKEN_TYPE_DECLARATION:
2162 r = tgsi_declaration(&ctx);
2163 if (r)
2164 goto out_err;
2165 break;
2166 case TGSI_TOKEN_TYPE_INSTRUCTION:
2167 case TGSI_TOKEN_TYPE_PROPERTY:
2168 break;
2169 default:
2170 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
2171 r = -EINVAL;
2172 goto out_err;
2173 }
2174 }
2175
2176 shader->ring_item_sizes[0] = ctx.next_ring_offset;
2177 shader->ring_item_sizes[1] = 0;
2178 shader->ring_item_sizes[2] = 0;
2179 shader->ring_item_sizes[3] = 0;
2180
2181 /* Process two side if needed */
2182 if (shader->two_side && ctx.colors_used) {
2183 int i, count = ctx.shader->ninput;
2184 unsigned next_lds_loc = ctx.shader->nlds;
2185
2186 /* additional inputs will be allocated right after the existing inputs,
2187 * we won't need them after the color selection, so we don't need to
2188 * reserve these gprs for the rest of the shader code and to adjust
2189 * output offsets etc. */
2190 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
2191 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
2192
2193 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
2194 if (ctx.face_gpr == -1) {
2195 i = ctx.shader->ninput++;
2196 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
2197 ctx.shader->input[i].spi_sid = 0;
2198 ctx.shader->input[i].gpr = gpr++;
2199 ctx.face_gpr = ctx.shader->input[i].gpr;
2200 }
2201
2202 for (i = 0; i < count; i++) {
2203 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2204 int ni = ctx.shader->ninput++;
2205 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
2206 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
2207 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
2208 ctx.shader->input[ni].gpr = gpr++;
2209 // TGSI to LLVM needs to know the lds position of inputs.
2210 // Non LLVM path computes it later (in process_twoside_color)
2211 ctx.shader->input[ni].lds_pos = next_lds_loc++;
2212 ctx.shader->input[i].back_color_input = ni;
2213 if (ctx.bc->chip_class >= EVERGREEN) {
2214 if ((r = evergreen_interp_input(&ctx, ni)))
2215 return r;
2216 }
2217 }
2218 }
2219 }
2220
2221 /* LLVM backend setup */
2222 #ifdef R600_USE_LLVM
2223 if (use_llvm) {
2224 struct radeon_llvm_context radeon_llvm_ctx;
2225 LLVMModuleRef mod;
2226 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
2227 boolean use_kill = false;
2228
2229 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
2230 radeon_llvm_ctx.type = ctx.type;
2231 radeon_llvm_ctx.two_side = shader->two_side;
2232 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
2233 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
2234 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
2235 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
2236 radeon_llvm_ctx.color_buffer_count = max_color_exports;
2237 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
2238 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
2239 radeon_llvm_ctx.stream_outputs = &so;
2240 radeon_llvm_ctx.alpha_to_one = key.ps.alpha_to_one;
2241 radeon_llvm_ctx.has_compressed_msaa_texturing =
2242 ctx.bc->has_compressed_msaa_texturing;
2243 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
2244 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
2245 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
2246
2247 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
2248 radeon_llvm_dispose(&radeon_llvm_ctx);
2249 use_llvm = 0;
2250 fprintf(stderr, "R600 LLVM backend failed to compile "
2251 "shader. Falling back to TGSI\n");
2252 } else {
2253 ctx.file_offset[TGSI_FILE_OUTPUT] =
2254 ctx.file_offset[TGSI_FILE_INPUT];
2255 }
2256 if (use_kill)
2257 ctx.shader->uses_kill = use_kill;
2258 radeon_llvm_dispose(&radeon_llvm_ctx);
2259 }
2260 #endif
2261 /* End of LLVM backend setup */
2262
2263 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
2264 shader->nr_ps_max_color_exports = 8;
2265
2266 if (!use_llvm) {
2267 if (ctx.fragcoord_input >= 0) {
2268 if (ctx.bc->chip_class == CAYMAN) {
2269 for (j = 0 ; j < 4; j++) {
2270 struct r600_bytecode_alu alu;
2271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2272 alu.op = ALU_OP1_RECIP_IEEE;
2273 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2274 alu.src[0].chan = 3;
2275
2276 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2277 alu.dst.chan = j;
2278 alu.dst.write = (j == 3);
2279 alu.last = 1;
2280 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2281 return r;
2282 }
2283 } else {
2284 struct r600_bytecode_alu alu;
2285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2286 alu.op = ALU_OP1_RECIP_IEEE;
2287 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
2288 alu.src[0].chan = 3;
2289
2290 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
2291 alu.dst.chan = 3;
2292 alu.dst.write = 1;
2293 alu.last = 1;
2294 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
2295 return r;
2296 }
2297 }
2298
2299 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2300 struct r600_bytecode_alu alu;
2301 int r;
2302
2303 /* GS thread with no output workaround - emit a cut at start of GS */
2304 if (ctx.bc->chip_class == R600)
2305 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
2306
2307 for (j = 0; j < 4; j++) {
2308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2309 alu.op = ALU_OP1_MOV;
2310 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2311 alu.src[0].value = 0;
2312 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
2313 alu.dst.write = 1;
2314 alu.last = 1;
2315 r = r600_bytecode_add_alu(ctx.bc, &alu);
2316 if (r)
2317 return r;
2318 }
2319 }
2320 if (shader->two_side && ctx.colors_used) {
2321 if ((r = process_twoside_color_inputs(&ctx)))
2322 return r;
2323 }
2324
2325 tgsi_parse_init(&ctx.parse, tokens);
2326 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
2327 tgsi_parse_token(&ctx.parse);
2328 switch (ctx.parse.FullToken.Token.Type) {
2329 case TGSI_TOKEN_TYPE_INSTRUCTION:
2330 r = tgsi_is_supported(&ctx);
2331 if (r)
2332 goto out_err;
2333 ctx.max_driver_temp_used = 0;
2334 /* reserve first tmp for everyone */
2335 r600_get_temp(&ctx);
2336
2337 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
2338 if ((r = tgsi_split_constant(&ctx)))
2339 goto out_err;
2340 if ((r = tgsi_split_literal_constant(&ctx)))
2341 goto out_err;
2342 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
2343 if ((r = tgsi_split_gs_inputs(&ctx)))
2344 goto out_err;
2345 if (ctx.bc->chip_class == CAYMAN)
2346 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
2347 else if (ctx.bc->chip_class >= EVERGREEN)
2348 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
2349 else
2350 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
2351 r = ctx.inst_info->process(&ctx);
2352 if (r)
2353 goto out_err;
2354 break;
2355 default:
2356 break;
2357 }
2358 }
2359 }
2360
2361 /* Reset the temporary register counter. */
2362 ctx.max_driver_temp_used = 0;
2363
2364 noutput = shader->noutput;
2365
2366 if (!ring_outputs && ctx.clip_vertex_write) {
2367 unsigned clipdist_temp[2];
2368
2369 clipdist_temp[0] = r600_get_temp(&ctx);
2370 clipdist_temp[1] = r600_get_temp(&ctx);
2371
2372 /* need to convert a clipvertex write into clipdistance writes and not export
2373 the clip vertex anymore */
2374
2375 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
2376 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2377 shader->output[noutput].gpr = clipdist_temp[0];
2378 noutput++;
2379 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
2380 shader->output[noutput].gpr = clipdist_temp[1];
2381 noutput++;
2382
2383 /* reset spi_sid for clipvertex output to avoid confusing spi */
2384 shader->output[ctx.cv_output].spi_sid = 0;
2385
2386 shader->clip_dist_write = 0xFF;
2387
2388 for (i = 0; i < 8; i++) {
2389 int oreg = i >> 2;
2390 int ochan = i & 3;
2391
2392 for (j = 0; j < 4; j++) {
2393 struct r600_bytecode_alu alu;
2394 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2395 alu.op = ALU_OP2_DOT4;
2396 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
2397 alu.src[0].chan = j;
2398
2399 alu.src[1].sel = 512 + i;
2400 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
2401 alu.src[1].chan = j;
2402
2403 alu.dst.sel = clipdist_temp[oreg];
2404 alu.dst.chan = j;
2405 alu.dst.write = (j == ochan);
2406 if (j == 3)
2407 alu.last = 1;
2408 if (!use_llvm)
2409 r = r600_bytecode_add_alu(ctx.bc, &alu);
2410 if (r)
2411 return r;
2412 }
2413 }
2414 }
2415
2416 /* Add stream outputs. */
2417 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
2418 so.num_outputs && !use_llvm)
2419 emit_streamout(&ctx, &so, -1, NULL);
2420
2421 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2422 convert_edgeflag_to_int(&ctx);
2423
2424 if (ring_outputs) {
2425 if (shader->vs_as_es || shader->tes_as_es) {
2426 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
2427 ctx.gs_export_gpr_tregs[1] = -1;
2428 ctx.gs_export_gpr_tregs[2] = -1;
2429 ctx.gs_export_gpr_tregs[3] = -1;
2430
2431 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
2432 }
2433 } else {
2434 /* Export output */
2435 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
2436
2437 for (i = 0, j = 0; i < noutput; i++, j++) {
2438 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2439 output[j].gpr = shader->output[i].gpr;
2440 output[j].elem_size = 3;
2441 output[j].swizzle_x = 0;
2442 output[j].swizzle_y = 1;
2443 output[j].swizzle_z = 2;
2444 output[j].swizzle_w = 3;
2445 output[j].burst_count = 1;
2446 output[j].type = -1;
2447 output[j].op = CF_OP_EXPORT;
2448 switch (ctx.type) {
2449 case TGSI_PROCESSOR_VERTEX:
2450 switch (shader->output[i].name) {
2451 case TGSI_SEMANTIC_POSITION:
2452 output[j].array_base = 60;
2453 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2454 pos_emitted = true;
2455 break;
2456
2457 case TGSI_SEMANTIC_PSIZE:
2458 output[j].array_base = 61;
2459 output[j].swizzle_y = 7;
2460 output[j].swizzle_z = 7;
2461 output[j].swizzle_w = 7;
2462 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2463 pos_emitted = true;
2464 break;
2465 case TGSI_SEMANTIC_EDGEFLAG:
2466 output[j].array_base = 61;
2467 output[j].swizzle_x = 7;
2468 output[j].swizzle_y = 0;
2469 output[j].swizzle_z = 7;
2470 output[j].swizzle_w = 7;
2471 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2472 pos_emitted = true;
2473 break;
2474 case TGSI_SEMANTIC_LAYER:
2475 /* spi_sid is 0 for outputs that are
2476 * not consumed by PS */
2477 if (shader->output[i].spi_sid) {
2478 output[j].array_base = next_param_base++;
2479 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2480 j++;
2481 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2482 }
2483 output[j].array_base = 61;
2484 output[j].swizzle_x = 7;
2485 output[j].swizzle_y = 7;
2486 output[j].swizzle_z = 0;
2487 output[j].swizzle_w = 7;
2488 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2489 pos_emitted = true;
2490 break;
2491 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2492 /* spi_sid is 0 for outputs that are
2493 * not consumed by PS */
2494 if (shader->output[i].spi_sid) {
2495 output[j].array_base = next_param_base++;
2496 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2497 j++;
2498 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2499 }
2500 output[j].array_base = 61;
2501 output[j].swizzle_x = 7;
2502 output[j].swizzle_y = 7;
2503 output[j].swizzle_z = 7;
2504 output[j].swizzle_w = 0;
2505 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2506 pos_emitted = true;
2507 break;
2508 case TGSI_SEMANTIC_CLIPVERTEX:
2509 j--;
2510 break;
2511 case TGSI_SEMANTIC_CLIPDIST:
2512 output[j].array_base = next_clip_base++;
2513 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2514 pos_emitted = true;
2515 /* spi_sid is 0 for clipdistance outputs that were generated
2516 * for clipvertex - we don't need to pass them to PS */
2517 if (shader->output[i].spi_sid) {
2518 j++;
2519 /* duplicate it as PARAM to pass to the pixel shader */
2520 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2521 output[j].array_base = next_param_base++;
2522 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2523 }
2524 break;
2525 case TGSI_SEMANTIC_FOG:
2526 output[j].swizzle_y = 4; /* 0 */
2527 output[j].swizzle_z = 4; /* 0 */
2528 output[j].swizzle_w = 5; /* 1 */
2529 break;
2530 case TGSI_SEMANTIC_PRIMID:
2531 output[j].swizzle_x = 2;
2532 output[j].swizzle_y = 4; /* 0 */
2533 output[j].swizzle_z = 4; /* 0 */
2534 output[j].swizzle_w = 4; /* 0 */
2535 break;
2536 }
2537
2538 break;
2539 case TGSI_PROCESSOR_FRAGMENT:
2540 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2541 /* never export more colors than the number of CBs */
2542 if (shader->output[i].sid >= max_color_exports) {
2543 /* skip export */
2544 j--;
2545 continue;
2546 }
2547 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2548 output[j].array_base = shader->output[i].sid;
2549 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2550 shader->nr_ps_color_exports++;
2551 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2552 for (k = 1; k < max_color_exports; k++) {
2553 j++;
2554 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2555 output[j].gpr = shader->output[i].gpr;
2556 output[j].elem_size = 3;
2557 output[j].swizzle_x = 0;
2558 output[j].swizzle_y = 1;
2559 output[j].swizzle_z = 2;
2560 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
2561 output[j].burst_count = 1;
2562 output[j].array_base = k;
2563 output[j].op = CF_OP_EXPORT;
2564 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2565 shader->nr_ps_color_exports++;
2566 }
2567 }
2568 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2569 output[j].array_base = 61;
2570 output[j].swizzle_x = 2;
2571 output[j].swizzle_y = 7;
2572 output[j].swizzle_z = output[j].swizzle_w = 7;
2573 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2574 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2575 output[j].array_base = 61;
2576 output[j].swizzle_x = 7;
2577 output[j].swizzle_y = 1;
2578 output[j].swizzle_z = output[j].swizzle_w = 7;
2579 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2580 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
2581 output[j].array_base = 61;
2582 output[j].swizzle_x = 7;
2583 output[j].swizzle_y = 7;
2584 output[j].swizzle_z = 0;
2585 output[j].swizzle_w = 7;
2586 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2587 } else {
2588 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2589 r = -EINVAL;
2590 goto out_err;
2591 }
2592 break;
2593 default:
2594 R600_ERR("unsupported processor type %d\n", ctx.type);
2595 r = -EINVAL;
2596 goto out_err;
2597 }
2598
2599 if (output[j].type==-1) {
2600 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2601 output[j].array_base = next_param_base++;
2602 }
2603 }
2604
2605 /* add fake position export */
2606 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2607 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2608 output[j].gpr = 0;
2609 output[j].elem_size = 3;
2610 output[j].swizzle_x = 7;
2611 output[j].swizzle_y = 7;
2612 output[j].swizzle_z = 7;
2613 output[j].swizzle_w = 7;
2614 output[j].burst_count = 1;
2615 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2616 output[j].array_base = 60;
2617 output[j].op = CF_OP_EXPORT;
2618 j++;
2619 }
2620
2621 /* add fake param output for vertex shader if no param is exported */
2622 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2623 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2624 output[j].gpr = 0;
2625 output[j].elem_size = 3;
2626 output[j].swizzle_x = 7;
2627 output[j].swizzle_y = 7;
2628 output[j].swizzle_z = 7;
2629 output[j].swizzle_w = 7;
2630 output[j].burst_count = 1;
2631 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2632 output[j].array_base = 0;
2633 output[j].op = CF_OP_EXPORT;
2634 j++;
2635 }
2636
2637 /* add fake pixel export */
2638 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2639 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2640 output[j].gpr = 0;
2641 output[j].elem_size = 3;
2642 output[j].swizzle_x = 7;
2643 output[j].swizzle_y = 7;
2644 output[j].swizzle_z = 7;
2645 output[j].swizzle_w = 7;
2646 output[j].burst_count = 1;
2647 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2648 output[j].array_base = 0;
2649 output[j].op = CF_OP_EXPORT;
2650 j++;
2651 shader->nr_ps_color_exports++;
2652 }
2653
2654 noutput = j;
2655
2656 /* set export done on last export of each type */
2657 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2658 if (!(output_done & (1 << output[i].type))) {
2659 output_done |= (1 << output[i].type);
2660 output[i].op = CF_OP_EXPORT_DONE;
2661 }
2662 }
2663 /* add output to bytecode */
2664 if (!use_llvm) {
2665 for (i = 0; i < noutput; i++) {
2666 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2667 if (r)
2668 goto out_err;
2669 }
2670 }
2671 }
2672
2673 /* add program end */
2674 if (!use_llvm) {
2675 if (ctx.bc->chip_class == CAYMAN)
2676 cm_bytecode_add_cf_end(ctx.bc);
2677 else {
2678 const struct cf_op_info *last = NULL;
2679
2680 if (ctx.bc->cf_last)
2681 last = r600_isa_cf(ctx.bc->cf_last->op);
2682
2683 /* alu clause instructions don't have EOP bit, so add NOP */
2684 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2685 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2686
2687 ctx.bc->cf_last->end_of_program = 1;
2688 }
2689 }
2690
2691 /* check GPR limit - we have 124 = 128 - 4
2692 * (4 are reserved as alu clause temporary registers) */
2693 if (ctx.bc->ngpr > 124) {
2694 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2695 r = -ENOMEM;
2696 goto out_err;
2697 }
2698
2699 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2700 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2701 return r;
2702 }
2703
2704 free(ctx.literals);
2705 tgsi_parse_free(&ctx.parse);
2706 return 0;
2707 out_err:
2708 free(ctx.literals);
2709 tgsi_parse_free(&ctx.parse);
2710 return r;
2711 }
2712
2713 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2714 {
2715 const unsigned tgsi_opcode =
2716 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
2717 R600_ERR("%s tgsi opcode unsupported\n",
2718 tgsi_get_opcode_name(tgsi_opcode));
2719 return -EINVAL;
2720 }
2721
2722 static int tgsi_end(struct r600_shader_ctx *ctx)
2723 {
2724 return 0;
2725 }
2726
2727 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2728 const struct r600_shader_src *shader_src,
2729 unsigned chan)
2730 {
2731 bc_src->sel = shader_src->sel;
2732 bc_src->chan = shader_src->swizzle[chan];
2733 bc_src->neg = shader_src->neg;
2734 bc_src->abs = shader_src->abs;
2735 bc_src->rel = shader_src->rel;
2736 bc_src->value = shader_src->value[bc_src->chan];
2737 bc_src->kc_bank = shader_src->kc_bank;
2738 bc_src->kc_rel = shader_src->kc_rel;
2739 }
2740
2741 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2742 {
2743 bc_src->abs = 1;
2744 bc_src->neg = 0;
2745 }
2746
2747 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2748 {
2749 bc_src->neg = !bc_src->neg;
2750 }
2751
2752 static void tgsi_dst(struct r600_shader_ctx *ctx,
2753 const struct tgsi_full_dst_register *tgsi_dst,
2754 unsigned swizzle,
2755 struct r600_bytecode_alu_dst *r600_dst)
2756 {
2757 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2758
2759 r600_dst->sel = tgsi_dst->Register.Index;
2760 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2761 r600_dst->chan = swizzle;
2762 r600_dst->write = 1;
2763 if (tgsi_dst->Register.Indirect)
2764 r600_dst->rel = V_SQ_REL_RELATIVE;
2765 if (inst->Instruction.Saturate) {
2766 r600_dst->clamp = 1;
2767 }
2768 }
2769
2770 static int tgsi_last_instruction(unsigned writemask)
2771 {
2772 int i, lasti = 0;
2773
2774 for (i = 0; i < 4; i++) {
2775 if (writemask & (1 << i)) {
2776 lasti = i;
2777 }
2778 }
2779 return lasti;
2780 }
2781
2782
2783
2784 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
2785 {
2786 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2787 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2788 struct r600_bytecode_alu alu;
2789 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2790 int use_tmp = 0;
2791
2792 if (singledest) {
2793 switch (write_mask) {
2794 case 0x1:
2795 write_mask = 0x3;
2796 break;
2797 case 0x2:
2798 use_tmp = 1;
2799 write_mask = 0x3;
2800 break;
2801 case 0x4:
2802 write_mask = 0xc;
2803 break;
2804 case 0x8:
2805 write_mask = 0xc;
2806 use_tmp = 3;
2807 break;
2808 }
2809 }
2810
2811 lasti = tgsi_last_instruction(write_mask);
2812 for (i = 0; i <= lasti; i++) {
2813
2814 if (!(write_mask & (1 << i)))
2815 continue;
2816
2817 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2818
2819 if (singledest) {
2820 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2821 if (use_tmp) {
2822 alu.dst.sel = ctx->temp_reg;
2823 alu.dst.chan = i;
2824 alu.dst.write = 1;
2825 }
2826 if (i == 1 || i == 3)
2827 alu.dst.write = 0;
2828 } else
2829 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2830
2831 alu.op = ctx->inst_info->op;
2832 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
2833 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2834 } else if (!swap) {
2835 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2836 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
2837 }
2838 } else {
2839 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
2840 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
2841 }
2842
2843 /* handle some special cases */
2844 if (i == 1 || i == 3) {
2845 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
2846 case TGSI_OPCODE_SUB:
2847 r600_bytecode_src_toggle_neg(&alu.src[1]);
2848 break;
2849 case TGSI_OPCODE_DABS:
2850 r600_bytecode_src_set_abs(&alu.src[0]);
2851 break;
2852 default:
2853 break;
2854 }
2855 }
2856 if (i == lasti) {
2857 alu.last = 1;
2858 }
2859 r = r600_bytecode_add_alu(ctx->bc, &alu);
2860 if (r)
2861 return r;
2862 }
2863
2864 if (use_tmp) {
2865 write_mask = inst->Dst[0].Register.WriteMask;
2866
2867 /* move result from temp to dst */
2868 for (i = 0; i <= lasti; i++) {
2869 if (!(write_mask & (1 << i)))
2870 continue;
2871
2872 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2873 alu.op = ALU_OP1_MOV;
2874 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2875 alu.src[0].sel = ctx->temp_reg;
2876 alu.src[0].chan = use_tmp - 1;
2877 alu.last = (i == lasti);
2878
2879 r = r600_bytecode_add_alu(ctx->bc, &alu);
2880 if (r)
2881 return r;
2882 }
2883 }
2884 return 0;
2885 }
2886
2887 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
2888 {
2889 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2890 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2891 /* confirm writemasking */
2892 if ((write_mask & 0x3) != 0x3 &&
2893 (write_mask & 0xc) != 0xc) {
2894 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
2895 return -1;
2896 }
2897 return tgsi_op2_64_params(ctx, false, false);
2898 }
2899
2900 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
2901 {
2902 return tgsi_op2_64_params(ctx, true, false);
2903 }
2904
2905 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
2906 {
2907 return tgsi_op2_64_params(ctx, true, true);
2908 }
2909
2910 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
2911 {
2912 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2913 struct r600_bytecode_alu alu;
2914 int i, j, r;
2915 int lasti = 3;
2916 int tmp = r600_get_temp(ctx);
2917
2918 for (i = 0; i < lasti + 1; i++) {
2919
2920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2921 alu.op = ctx->inst_info->op;
2922 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2923 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
2924 }
2925
2926 if (inst->Dst[0].Register.WriteMask & (1 << i))
2927 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2928 else
2929 alu.dst.sel = tmp;
2930
2931 alu.dst.chan = i;
2932 alu.is_op3 = 1;
2933 if (i == lasti) {
2934 alu.last = 1;
2935 }
2936 r = r600_bytecode_add_alu(ctx->bc, &alu);
2937 if (r)
2938 return r;
2939 }
2940 return 0;
2941 }
2942
2943 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2944 {
2945 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2946 struct r600_bytecode_alu alu;
2947 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2948 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2949 /* use temp register if trans_only and more than one dst component */
2950 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2951
2952 for (i = 0; i <= lasti; i++) {
2953 if (!(write_mask & (1 << i)))
2954 continue;
2955
2956 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2957 if (use_tmp) {
2958 alu.dst.sel = ctx->temp_reg;
2959 alu.dst.chan = i;
2960 alu.dst.write = 1;
2961 } else
2962 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2963
2964 alu.op = ctx->inst_info->op;
2965 if (!swap) {
2966 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2967 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2968 }
2969 } else {
2970 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2971 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2972 }
2973 /* handle some special cases */
2974 switch (inst->Instruction.Opcode) {
2975 case TGSI_OPCODE_SUB:
2976 r600_bytecode_src_toggle_neg(&alu.src[1]);
2977 break;
2978 case TGSI_OPCODE_ABS:
2979 r600_bytecode_src_set_abs(&alu.src[0]);
2980 break;
2981 default:
2982 break;
2983 }
2984 if (i == lasti || trans_only) {
2985 alu.last = 1;
2986 }
2987 r = r600_bytecode_add_alu(ctx->bc, &alu);
2988 if (r)
2989 return r;
2990 }
2991
2992 if (use_tmp) {
2993 /* move result from temp to dst */
2994 for (i = 0; i <= lasti; i++) {
2995 if (!(write_mask & (1 << i)))
2996 continue;
2997
2998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2999 alu.op = ALU_OP1_MOV;
3000 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3001 alu.src[0].sel = ctx->temp_reg;
3002 alu.src[0].chan = i;
3003 alu.last = (i == lasti);
3004
3005 r = r600_bytecode_add_alu(ctx->bc, &alu);
3006 if (r)
3007 return r;
3008 }
3009 }
3010 return 0;
3011 }
3012
3013 static int tgsi_op2(struct r600_shader_ctx *ctx)
3014 {
3015 return tgsi_op2_s(ctx, 0, 0);
3016 }
3017
3018 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
3019 {
3020 return tgsi_op2_s(ctx, 1, 0);
3021 }
3022
3023 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
3024 {
3025 return tgsi_op2_s(ctx, 0, 1);
3026 }
3027
3028 static int tgsi_ineg(struct r600_shader_ctx *ctx)
3029 {
3030 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3031 struct r600_bytecode_alu alu;
3032 int i, r;
3033 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3034
3035 for (i = 0; i < lasti + 1; i++) {
3036
3037 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3038 continue;
3039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3040 alu.op = ctx->inst_info->op;
3041
3042 alu.src[0].sel = V_SQ_ALU_SRC_0;
3043
3044 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3045
3046 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3047
3048 if (i == lasti) {
3049 alu.last = 1;
3050 }
3051 r = r600_bytecode_add_alu(ctx->bc, &alu);
3052 if (r)
3053 return r;
3054 }
3055 return 0;
3056
3057 }
3058
3059 static int tgsi_dneg(struct r600_shader_ctx *ctx)
3060 {
3061 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3062 struct r600_bytecode_alu alu;
3063 int i, r;
3064 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3065
3066 for (i = 0; i < lasti + 1; i++) {
3067
3068 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3069 continue;
3070 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3071 alu.op = ALU_OP1_MOV;
3072
3073 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3074
3075 if (i == 1 || i == 3)
3076 r600_bytecode_src_toggle_neg(&alu.src[0]);
3077 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3078
3079 if (i == lasti) {
3080 alu.last = 1;
3081 }
3082 r = r600_bytecode_add_alu(ctx->bc, &alu);
3083 if (r)
3084 return r;
3085 }
3086 return 0;
3087
3088 }
3089
3090 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
3091 {
3092 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3093 struct r600_bytecode_alu alu;
3094 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3095 int i, j, r;
3096 int firsti = write_mask == 0xc ? 2 : 0;
3097
3098 for (i = 0; i <= 3; i++) {
3099 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3100 alu.op = ctx->inst_info->op;
3101
3102 alu.dst.sel = ctx->temp_reg;
3103 alu.dst.chan = i;
3104 alu.dst.write = 1;
3105 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3106 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3107 }
3108
3109 if (i == 3)
3110 alu.last = 1;
3111
3112 r = r600_bytecode_add_alu(ctx->bc, &alu);
3113 if (r)
3114 return r;
3115 }
3116
3117 /* MOV first two channels to writemask dst0 */
3118 for (i = 0; i <= 1; i++) {
3119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3120 alu.op = ALU_OP1_MOV;
3121 alu.src[0].chan = i + 2;
3122 alu.src[0].sel = ctx->temp_reg;
3123
3124 tgsi_dst(ctx, &inst->Dst[0], firsti + i, &alu.dst);
3125 alu.dst.write = (inst->Dst[0].Register.WriteMask >> (firsti + i)) & 1;
3126 alu.last = 1;
3127 r = r600_bytecode_add_alu(ctx->bc, &alu);
3128 if (r)
3129 return r;
3130 }
3131
3132 for (i = 0; i <= 3; i++) {
3133 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
3134 /* MOV third channels to writemask dst1 */
3135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3136 alu.op = ALU_OP1_MOV;
3137 alu.src[0].chan = 1;
3138 alu.src[0].sel = ctx->temp_reg;
3139
3140 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
3141 alu.last = 1;
3142 r = r600_bytecode_add_alu(ctx->bc, &alu);
3143 if (r)
3144 return r;
3145 break;
3146 }
3147 }
3148 return 0;
3149 }
3150
3151
3152 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
3153 {
3154 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3155 struct r600_bytecode_alu alu;
3156 int i, r;
3157 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3158
3159 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
3160 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
3161
3162 for (i = 0; i <= (lasti+1)/2; i++) {
3163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3164 alu.op = ctx->inst_info->op;
3165
3166 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3167 alu.dst.sel = ctx->temp_reg;
3168 alu.dst.chan = i;
3169 alu.dst.write = 1;
3170 alu.last = 1;
3171
3172 r = r600_bytecode_add_alu(ctx->bc, &alu);
3173 if (r)
3174 return r;
3175 }
3176
3177 for (i = 0; i <= lasti; i++) {
3178 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3179 alu.op = ALU_OP1_FLT32_TO_FLT64;
3180
3181 alu.src[0].chan = i/2;
3182 if (i%2 == 0)
3183 alu.src[0].sel = ctx->temp_reg;
3184 else {
3185 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3186 alu.src[0].value = 0x0;
3187 }
3188 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3189 alu.last = i == lasti;
3190
3191 r = r600_bytecode_add_alu(ctx->bc, &alu);
3192 if (r)
3193 return r;
3194 }
3195
3196 return 0;
3197 }
3198
3199 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
3200 {
3201 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3202 struct r600_bytecode_alu alu;
3203 int i, r;
3204 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3205
3206 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
3207 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
3208
3209 for (i = 0; i <= lasti; i++) {
3210 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3211 alu.op = ALU_OP1_FLT64_TO_FLT32;
3212
3213 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
3214 alu.dst.chan = i;
3215 alu.dst.sel = ctx->temp_reg;
3216 alu.dst.write = i%2 == 0;
3217 alu.last = i == lasti;
3218
3219 r = r600_bytecode_add_alu(ctx->bc, &alu);
3220 if (r)
3221 return r;
3222 }
3223
3224 for (i = 0; i <= (lasti+1)/2; i++) {
3225 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3226 alu.op = ctx->inst_info->op;
3227
3228 alu.src[0].chan = i*2;
3229 alu.src[0].sel = ctx->temp_reg;
3230 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3231 alu.last = 1;
3232
3233 r = r600_bytecode_add_alu(ctx->bc, &alu);
3234 if (r)
3235 return r;
3236 }
3237
3238 return 0;
3239 }
3240
3241 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
3242 {
3243 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3244 int i, r;
3245 struct r600_bytecode_alu alu;
3246 int last_slot = 3;
3247 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3248 int t1 = ctx->temp_reg;
3249
3250 /* these have to write the result to X/Y by the looks of it */
3251 for (i = 0 ; i < last_slot; i++) {
3252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3253 alu.op = ctx->inst_info->op;
3254
3255 /* should only be one src regs */
3256 assert (inst->Instruction.NumSrcRegs == 1);
3257
3258 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3259 r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
3260
3261 /* RSQ should take the absolute value of src */
3262 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
3263 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT) {
3264 r600_bytecode_src_set_abs(&alu.src[1]);
3265 }
3266 alu.dst.sel = t1;
3267 alu.dst.chan = i;
3268 alu.dst.write = (i == 0 || i == 1);
3269
3270 if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
3271 alu.last = 1;
3272 r = r600_bytecode_add_alu(ctx->bc, &alu);
3273 if (r)
3274 return r;
3275 }
3276
3277 for (i = 0 ; i <= lasti; i++) {
3278 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3279 continue;
3280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3281 alu.op = ALU_OP1_MOV;
3282 alu.src[0].sel = t1;
3283 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
3284 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3285 alu.dst.write = 1;
3286 if (i == lasti)
3287 alu.last = 1;
3288 r = r600_bytecode_add_alu(ctx->bc, &alu);
3289 if (r)
3290 return r;
3291 }
3292 return 0;
3293 }
3294
3295 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
3296 {
3297 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3298 int i, j, r;
3299 struct r600_bytecode_alu alu;
3300 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3301
3302 for (i = 0 ; i < last_slot; i++) {
3303 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3304 alu.op = ctx->inst_info->op;
3305 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3306 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
3307
3308 /* RSQ should take the absolute value of src */
3309 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
3310 r600_bytecode_src_set_abs(&alu.src[j]);
3311 }
3312 }
3313 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3314 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3315
3316 if (i == last_slot - 1)
3317 alu.last = 1;
3318 r = r600_bytecode_add_alu(ctx->bc, &alu);
3319 if (r)
3320 return r;
3321 }
3322 return 0;
3323 }
3324
3325 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
3326 {
3327 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3328 int i, j, k, r;
3329 struct r600_bytecode_alu alu;
3330 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3331 int t1 = ctx->temp_reg;
3332
3333 for (k = 0; k <= lasti; k++) {
3334 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
3335 continue;
3336
3337 for (i = 0 ; i < 4; i++) {
3338 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3339 alu.op = ctx->inst_info->op;
3340 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3341 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
3342 }
3343 alu.dst.sel = t1;
3344 alu.dst.chan = i;
3345 alu.dst.write = (i == k);
3346 if (i == 3)
3347 alu.last = 1;
3348 r = r600_bytecode_add_alu(ctx->bc, &alu);
3349 if (r)
3350 return r;
3351 }
3352 }
3353
3354 for (i = 0 ; i <= lasti; i++) {
3355 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3356 continue;
3357 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3358 alu.op = ALU_OP1_MOV;
3359 alu.src[0].sel = t1;
3360 alu.src[0].chan = i;
3361 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3362 alu.dst.write = 1;
3363 if (i == lasti)
3364 alu.last = 1;
3365 r = r600_bytecode_add_alu(ctx->bc, &alu);
3366 if (r)
3367 return r;
3368 }
3369
3370 return 0;
3371 }
3372
3373
3374 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
3375 {
3376 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3377 int i, j, k, r;
3378 struct r600_bytecode_alu alu;
3379 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3380 int t1 = ctx->temp_reg;
3381
3382 for (k = 0; k < 2; k++) {
3383 if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2))))
3384 continue;
3385
3386 for (i = 0; i < 4; i++) {
3387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3388 alu.op = ctx->inst_info->op;
3389 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3390 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));;
3391 }
3392 alu.dst.sel = t1;
3393 alu.dst.chan = i;
3394 alu.dst.write = 1;
3395 if (i == 3)
3396 alu.last = 1;
3397 r = r600_bytecode_add_alu(ctx->bc, &alu);
3398 if (r)
3399 return r;
3400 }
3401 }
3402
3403 for (i = 0; i <= lasti; i++) {
3404 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3405 continue;
3406 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3407 alu.op = ALU_OP1_MOV;
3408 alu.src[0].sel = t1;
3409 alu.src[0].chan = i;
3410 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3411 alu.dst.write = 1;
3412 if (i == lasti)
3413 alu.last = 1;
3414 r = r600_bytecode_add_alu(ctx->bc, &alu);
3415 if (r)
3416 return r;
3417 }
3418
3419 return 0;
3420 }
3421
3422 /*
3423 * r600 - trunc to -PI..PI range
3424 * r700 - normalize by dividing by 2PI
3425 * see fdo bug 27901
3426 */
3427 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
3428 {
3429 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
3430 static float double_pi = 3.1415926535 * 2;
3431 static float neg_pi = -3.1415926535;
3432
3433 int r;
3434 struct r600_bytecode_alu alu;
3435
3436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3437 alu.op = ALU_OP3_MULADD;
3438 alu.is_op3 = 1;
3439
3440 alu.dst.chan = 0;
3441 alu.dst.sel = ctx->temp_reg;
3442 alu.dst.write = 1;
3443
3444 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3445
3446 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3447 alu.src[1].chan = 0;
3448 alu.src[1].value = *(uint32_t *)&half_inv_pi;
3449 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3450 alu.src[2].chan = 0;
3451 alu.last = 1;
3452 r = r600_bytecode_add_alu(ctx->bc, &alu);
3453 if (r)
3454 return r;
3455
3456 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3457 alu.op = ALU_OP1_FRACT;
3458
3459 alu.dst.chan = 0;
3460 alu.dst.sel = ctx->temp_reg;
3461 alu.dst.write = 1;
3462
3463 alu.src[0].sel = ctx->temp_reg;
3464 alu.src[0].chan = 0;
3465 alu.last = 1;
3466 r = r600_bytecode_add_alu(ctx->bc, &alu);
3467 if (r)
3468 return r;
3469
3470 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3471 alu.op = ALU_OP3_MULADD;
3472 alu.is_op3 = 1;
3473
3474 alu.dst.chan = 0;
3475 alu.dst.sel = ctx->temp_reg;
3476 alu.dst.write = 1;
3477
3478 alu.src[0].sel = ctx->temp_reg;
3479 alu.src[0].chan = 0;
3480
3481 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3482 alu.src[1].chan = 0;
3483 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3484 alu.src[2].chan = 0;
3485
3486 if (ctx->bc->chip_class == R600) {
3487 alu.src[1].value = *(uint32_t *)&double_pi;
3488 alu.src[2].value = *(uint32_t *)&neg_pi;
3489 } else {
3490 alu.src[1].sel = V_SQ_ALU_SRC_1;
3491 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
3492 alu.src[2].neg = 1;
3493 }
3494
3495 alu.last = 1;
3496 r = r600_bytecode_add_alu(ctx->bc, &alu);
3497 if (r)
3498 return r;
3499 return 0;
3500 }
3501
3502 static int cayman_trig(struct r600_shader_ctx *ctx)
3503 {
3504 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3505 struct r600_bytecode_alu alu;
3506 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3507 int i, r;
3508
3509 r = tgsi_setup_trig(ctx);
3510 if (r)
3511 return r;
3512
3513
3514 for (i = 0; i < last_slot; i++) {
3515 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3516 alu.op = ctx->inst_info->op;
3517 alu.dst.chan = i;
3518
3519 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3520 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3521
3522 alu.src[0].sel = ctx->temp_reg;
3523 alu.src[0].chan = 0;
3524 if (i == last_slot - 1)
3525 alu.last = 1;
3526 r = r600_bytecode_add_alu(ctx->bc, &alu);
3527 if (r)
3528 return r;
3529 }
3530 return 0;
3531 }
3532
3533 static int tgsi_trig(struct r600_shader_ctx *ctx)
3534 {
3535 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3536 struct r600_bytecode_alu alu;
3537 int i, r;
3538 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3539
3540 r = tgsi_setup_trig(ctx);
3541 if (r)
3542 return r;
3543
3544 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3545 alu.op = ctx->inst_info->op;
3546 alu.dst.chan = 0;
3547 alu.dst.sel = ctx->temp_reg;
3548 alu.dst.write = 1;
3549
3550 alu.src[0].sel = ctx->temp_reg;
3551 alu.src[0].chan = 0;
3552 alu.last = 1;
3553 r = r600_bytecode_add_alu(ctx->bc, &alu);
3554 if (r)
3555 return r;
3556
3557 /* replicate result */
3558 for (i = 0; i < lasti + 1; i++) {
3559 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3560 continue;
3561
3562 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3563 alu.op = ALU_OP1_MOV;
3564
3565 alu.src[0].sel = ctx->temp_reg;
3566 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3567 if (i == lasti)
3568 alu.last = 1;
3569 r = r600_bytecode_add_alu(ctx->bc, &alu);
3570 if (r)
3571 return r;
3572 }
3573 return 0;
3574 }
3575
3576 static int tgsi_scs(struct r600_shader_ctx *ctx)
3577 {
3578 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3579 struct r600_bytecode_alu alu;
3580 int i, r;
3581
3582 /* We'll only need the trig stuff if we are going to write to the
3583 * X or Y components of the destination vector.
3584 */
3585 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
3586 r = tgsi_setup_trig(ctx);
3587 if (r)
3588 return r;
3589 }
3590
3591 /* dst.x = COS */
3592 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3593 if (ctx->bc->chip_class == CAYMAN) {
3594 for (i = 0 ; i < 3; i++) {
3595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3596 alu.op = ALU_OP1_COS;
3597 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3598
3599 if (i == 0)
3600 alu.dst.write = 1;
3601 else
3602 alu.dst.write = 0;
3603 alu.src[0].sel = ctx->temp_reg;
3604 alu.src[0].chan = 0;
3605 if (i == 2)
3606 alu.last = 1;
3607 r = r600_bytecode_add_alu(ctx->bc, &alu);
3608 if (r)
3609 return r;
3610 }
3611 } else {
3612 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3613 alu.op = ALU_OP1_COS;
3614 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3615
3616 alu.src[0].sel = ctx->temp_reg;
3617 alu.src[0].chan = 0;
3618 alu.last = 1;
3619 r = r600_bytecode_add_alu(ctx->bc, &alu);
3620 if (r)
3621 return r;
3622 }
3623 }
3624
3625 /* dst.y = SIN */
3626 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3627 if (ctx->bc->chip_class == CAYMAN) {
3628 for (i = 0 ; i < 3; i++) {
3629 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3630 alu.op = ALU_OP1_SIN;
3631 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3632 if (i == 1)
3633 alu.dst.write = 1;
3634 else
3635 alu.dst.write = 0;
3636 alu.src[0].sel = ctx->temp_reg;
3637 alu.src[0].chan = 0;
3638 if (i == 2)
3639 alu.last = 1;
3640 r = r600_bytecode_add_alu(ctx->bc, &alu);
3641 if (r)
3642 return r;
3643 }
3644 } else {
3645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3646 alu.op = ALU_OP1_SIN;
3647 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3648
3649 alu.src[0].sel = ctx->temp_reg;
3650 alu.src[0].chan = 0;
3651 alu.last = 1;
3652 r = r600_bytecode_add_alu(ctx->bc, &alu);
3653 if (r)
3654 return r;
3655 }
3656 }
3657
3658 /* dst.z = 0.0; */
3659 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3660 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3661
3662 alu.op = ALU_OP1_MOV;
3663
3664 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3665
3666 alu.src[0].sel = V_SQ_ALU_SRC_0;
3667 alu.src[0].chan = 0;
3668
3669 alu.last = 1;
3670
3671 r = r600_bytecode_add_alu(ctx->bc, &alu);
3672 if (r)
3673 return r;
3674 }
3675
3676 /* dst.w = 1.0; */
3677 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3679
3680 alu.op = ALU_OP1_MOV;
3681
3682 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3683
3684 alu.src[0].sel = V_SQ_ALU_SRC_1;
3685 alu.src[0].chan = 0;
3686
3687 alu.last = 1;
3688
3689 r = r600_bytecode_add_alu(ctx->bc, &alu);
3690 if (r)
3691 return r;
3692 }
3693
3694 return 0;
3695 }
3696
3697 static int tgsi_kill(struct r600_shader_ctx *ctx)
3698 {
3699 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3700 struct r600_bytecode_alu alu;
3701 int i, r;
3702
3703 for (i = 0; i < 4; i++) {
3704 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3705 alu.op = ctx->inst_info->op;
3706
3707 alu.dst.chan = i;
3708
3709 alu.src[0].sel = V_SQ_ALU_SRC_0;
3710
3711 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
3712 alu.src[1].sel = V_SQ_ALU_SRC_1;
3713 alu.src[1].neg = 1;
3714 } else {
3715 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3716 }
3717 if (i == 3) {
3718 alu.last = 1;
3719 }
3720 r = r600_bytecode_add_alu(ctx->bc, &alu);
3721 if (r)
3722 return r;
3723 }
3724
3725 /* kill must be last in ALU */
3726 ctx->bc->force_add_cf = 1;
3727 ctx->shader->uses_kill = TRUE;
3728 return 0;
3729 }
3730
3731 static int tgsi_lit(struct r600_shader_ctx *ctx)
3732 {
3733 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3734 struct r600_bytecode_alu alu;
3735 int r;
3736
3737 /* tmp.x = max(src.y, 0.0) */
3738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3739 alu.op = ALU_OP2_MAX;
3740 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
3741 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3742 alu.src[1].chan = 1;
3743
3744 alu.dst.sel = ctx->temp_reg;
3745 alu.dst.chan = 0;
3746 alu.dst.write = 1;
3747
3748 alu.last = 1;
3749 r = r600_bytecode_add_alu(ctx->bc, &alu);
3750 if (r)
3751 return r;
3752
3753 if (inst->Dst[0].Register.WriteMask & (1 << 2))
3754 {
3755 int chan;
3756 int sel;
3757 int i;
3758
3759 if (ctx->bc->chip_class == CAYMAN) {
3760 for (i = 0; i < 3; i++) {
3761 /* tmp.z = log(tmp.x) */
3762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3763 alu.op = ALU_OP1_LOG_CLAMPED;
3764 alu.src[0].sel = ctx->temp_reg;
3765 alu.src[0].chan = 0;
3766 alu.dst.sel = ctx->temp_reg;
3767 alu.dst.chan = i;
3768 if (i == 2) {
3769 alu.dst.write = 1;
3770 alu.last = 1;
3771 } else
3772 alu.dst.write = 0;
3773
3774 r = r600_bytecode_add_alu(ctx->bc, &alu);
3775 if (r)
3776 return r;
3777 }
3778 } else {
3779 /* tmp.z = log(tmp.x) */
3780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3781 alu.op = ALU_OP1_LOG_CLAMPED;
3782 alu.src[0].sel = ctx->temp_reg;
3783 alu.src[0].chan = 0;
3784 alu.dst.sel = ctx->temp_reg;
3785 alu.dst.chan = 2;
3786 alu.dst.write = 1;
3787 alu.last = 1;
3788 r = r600_bytecode_add_alu(ctx->bc, &alu);
3789 if (r)
3790 return r;
3791 }
3792
3793 chan = alu.dst.chan;
3794 sel = alu.dst.sel;
3795
3796 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
3797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3798 alu.op = ALU_OP3_MUL_LIT;
3799 alu.src[0].sel = sel;
3800 alu.src[0].chan = chan;
3801 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
3802 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
3803 alu.dst.sel = ctx->temp_reg;
3804 alu.dst.chan = 0;
3805 alu.dst.write = 1;
3806 alu.is_op3 = 1;
3807 alu.last = 1;
3808 r = r600_bytecode_add_alu(ctx->bc, &alu);
3809 if (r)
3810 return r;
3811
3812 if (ctx->bc->chip_class == CAYMAN) {
3813 for (i = 0; i < 3; i++) {
3814 /* dst.z = exp(tmp.x) */
3815 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3816 alu.op = ALU_OP1_EXP_IEEE;
3817 alu.src[0].sel = ctx->temp_reg;
3818 alu.src[0].chan = 0;
3819 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3820 if (i == 2) {
3821 alu.dst.write = 1;
3822 alu.last = 1;
3823 } else
3824 alu.dst.write = 0;
3825 r = r600_bytecode_add_alu(ctx->bc, &alu);
3826 if (r)
3827 return r;
3828 }
3829 } else {
3830 /* dst.z = exp(tmp.x) */
3831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3832 alu.op = ALU_OP1_EXP_IEEE;
3833 alu.src[0].sel = ctx->temp_reg;
3834 alu.src[0].chan = 0;
3835 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
3836 alu.last = 1;
3837 r = r600_bytecode_add_alu(ctx->bc, &alu);
3838 if (r)
3839 return r;
3840 }
3841 }
3842
3843 /* dst.x, <- 1.0 */
3844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3845 alu.op = ALU_OP1_MOV;
3846 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
3847 alu.src[0].chan = 0;
3848 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3849 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
3850 r = r600_bytecode_add_alu(ctx->bc, &alu);
3851 if (r)
3852 return r;
3853
3854 /* dst.y = max(src.x, 0.0) */
3855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3856 alu.op = ALU_OP2_MAX;
3857 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3858 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
3859 alu.src[1].chan = 0;
3860 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
3861 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
3862 r = r600_bytecode_add_alu(ctx->bc, &alu);
3863 if (r)
3864 return r;
3865
3866 /* dst.w, <- 1.0 */
3867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3868 alu.op = ALU_OP1_MOV;
3869 alu.src[0].sel = V_SQ_ALU_SRC_1;
3870 alu.src[0].chan = 0;
3871 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
3872 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
3873 alu.last = 1;
3874 r = r600_bytecode_add_alu(ctx->bc, &alu);
3875 if (r)
3876 return r;
3877
3878 return 0;
3879 }
3880
3881 static int tgsi_rsq(struct r600_shader_ctx *ctx)
3882 {
3883 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3884 struct r600_bytecode_alu alu;
3885 int i, r;
3886
3887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3888
3889 /* XXX:
3890 * For state trackers other than OpenGL, we'll want to use
3891 * _RECIPSQRT_IEEE instead.
3892 */
3893 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
3894
3895 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3896 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3897 r600_bytecode_src_set_abs(&alu.src[i]);
3898 }
3899 alu.dst.sel = ctx->temp_reg;
3900 alu.dst.write = 1;
3901 alu.last = 1;
3902 r = r600_bytecode_add_alu(ctx->bc, &alu);
3903 if (r)
3904 return r;
3905 /* replicate result */
3906 return tgsi_helper_tempx_replicate(ctx);
3907 }
3908
3909 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
3910 {
3911 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3912 struct r600_bytecode_alu alu;
3913 int i, r;
3914
3915 for (i = 0; i < 4; i++) {
3916 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3917 alu.src[0].sel = ctx->temp_reg;
3918 alu.op = ALU_OP1_MOV;
3919 alu.dst.chan = i;
3920 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3921 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3922 if (i == 3)
3923 alu.last = 1;
3924 r = r600_bytecode_add_alu(ctx->bc, &alu);
3925 if (r)
3926 return r;
3927 }
3928 return 0;
3929 }
3930
3931 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
3932 {
3933 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3934 struct r600_bytecode_alu alu;
3935 int i, r;
3936
3937 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3938 alu.op = ctx->inst_info->op;
3939 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3940 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3941 }
3942 alu.dst.sel = ctx->temp_reg;
3943 alu.dst.write = 1;
3944 alu.last = 1;
3945 r = r600_bytecode_add_alu(ctx->bc, &alu);
3946 if (r)
3947 return r;
3948 /* replicate result */
3949 return tgsi_helper_tempx_replicate(ctx);
3950 }
3951
3952 static int cayman_pow(struct r600_shader_ctx *ctx)
3953 {
3954 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3955 int i, r;
3956 struct r600_bytecode_alu alu;
3957 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3958
3959 for (i = 0; i < 3; i++) {
3960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3961 alu.op = ALU_OP1_LOG_IEEE;
3962 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3963 alu.dst.sel = ctx->temp_reg;
3964 alu.dst.chan = i;
3965 alu.dst.write = 1;
3966 if (i == 2)
3967 alu.last = 1;
3968 r = r600_bytecode_add_alu(ctx->bc, &alu);
3969 if (r)
3970 return r;
3971 }
3972
3973 /* b * LOG2(a) */
3974 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3975 alu.op = ALU_OP2_MUL;
3976 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3977 alu.src[1].sel = ctx->temp_reg;
3978 alu.dst.sel = ctx->temp_reg;
3979 alu.dst.write = 1;
3980 alu.last = 1;
3981 r = r600_bytecode_add_alu(ctx->bc, &alu);
3982 if (r)
3983 return r;
3984
3985 for (i = 0; i < last_slot; i++) {
3986 /* POW(a,b) = EXP2(b * LOG2(a))*/
3987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3988 alu.op = ALU_OP1_EXP_IEEE;
3989 alu.src[0].sel = ctx->temp_reg;
3990
3991 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3992 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3993 if (i == last_slot - 1)
3994 alu.last = 1;
3995 r = r600_bytecode_add_alu(ctx->bc, &alu);
3996 if (r)
3997 return r;
3998 }
3999 return 0;
4000 }
4001
4002 static int tgsi_pow(struct r600_shader_ctx *ctx)
4003 {
4004 struct r600_bytecode_alu alu;
4005 int r;
4006
4007 /* LOG2(a) */
4008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4009 alu.op = ALU_OP1_LOG_IEEE;
4010 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4011 alu.dst.sel = ctx->temp_reg;
4012 alu.dst.write = 1;
4013 alu.last = 1;
4014 r = r600_bytecode_add_alu(ctx->bc, &alu);
4015 if (r)
4016 return r;
4017 /* b * LOG2(a) */
4018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4019 alu.op = ALU_OP2_MUL;
4020 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4021 alu.src[1].sel = ctx->temp_reg;
4022 alu.dst.sel = ctx->temp_reg;
4023 alu.dst.write = 1;
4024 alu.last = 1;
4025 r = r600_bytecode_add_alu(ctx->bc, &alu);
4026 if (r)
4027 return r;
4028 /* POW(a,b) = EXP2(b * LOG2(a))*/
4029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4030 alu.op = ALU_OP1_EXP_IEEE;
4031 alu.src[0].sel = ctx->temp_reg;
4032 alu.dst.sel = ctx->temp_reg;
4033 alu.dst.write = 1;
4034 alu.last = 1;
4035 r = r600_bytecode_add_alu(ctx->bc, &alu);
4036 if (r)
4037 return r;
4038 return tgsi_helper_tempx_replicate(ctx);
4039 }
4040
4041 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
4042 {
4043 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4044 struct r600_bytecode_alu alu;
4045 int i, r, j;
4046 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4047 int tmp0 = ctx->temp_reg;
4048 int tmp1 = r600_get_temp(ctx);
4049 int tmp2 = r600_get_temp(ctx);
4050 int tmp3 = r600_get_temp(ctx);
4051 /* Unsigned path:
4052 *
4053 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
4054 *
4055 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
4056 * 2. tmp0.z = lo (tmp0.x * src2)
4057 * 3. tmp0.w = -tmp0.z
4058 * 4. tmp0.y = hi (tmp0.x * src2)
4059 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
4060 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
4061 * 7. tmp1.x = tmp0.x - tmp0.w
4062 * 8. tmp1.y = tmp0.x + tmp0.w
4063 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
4064 * 10. tmp0.z = hi(tmp0.x * src1) = q
4065 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
4066 *
4067 * 12. tmp0.w = src1 - tmp0.y = r
4068 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
4069 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
4070 *
4071 * if DIV
4072 *
4073 * 15. tmp1.z = tmp0.z + 1 = q + 1
4074 * 16. tmp1.w = tmp0.z - 1 = q - 1
4075 *
4076 * else MOD
4077 *
4078 * 15. tmp1.z = tmp0.w - src2 = r - src2
4079 * 16. tmp1.w = tmp0.w + src2 = r + src2
4080 *
4081 * endif
4082 *
4083 * 17. tmp1.x = tmp1.x & tmp1.y
4084 *
4085 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
4086 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
4087 *
4088 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
4089 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
4090 *
4091 * Signed path:
4092 *
4093 * Same as unsigned, using abs values of the operands,
4094 * and fixing the sign of the result in the end.
4095 */
4096
4097 for (i = 0; i < 4; i++) {
4098 if (!(write_mask & (1<<i)))
4099 continue;
4100
4101 if (signed_op) {
4102
4103 /* tmp2.x = -src0 */
4104 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4105 alu.op = ALU_OP2_SUB_INT;
4106
4107 alu.dst.sel = tmp2;
4108 alu.dst.chan = 0;
4109 alu.dst.write = 1;
4110
4111 alu.src[0].sel = V_SQ_ALU_SRC_0;
4112
4113 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4114
4115 alu.last = 1;
4116 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4117 return r;
4118
4119 /* tmp2.y = -src1 */
4120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4121 alu.op = ALU_OP2_SUB_INT;
4122
4123 alu.dst.sel = tmp2;
4124 alu.dst.chan = 1;
4125 alu.dst.write = 1;
4126
4127 alu.src[0].sel = V_SQ_ALU_SRC_0;
4128
4129 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4130
4131 alu.last = 1;
4132 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4133 return r;
4134
4135 /* tmp2.z sign bit is set if src0 and src2 signs are different */
4136 /* it will be a sign of the quotient */
4137 if (!mod) {
4138
4139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4140 alu.op = ALU_OP2_XOR_INT;
4141
4142 alu.dst.sel = tmp2;
4143 alu.dst.chan = 2;
4144 alu.dst.write = 1;
4145
4146 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4147 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4148
4149 alu.last = 1;
4150 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4151 return r;
4152 }
4153
4154 /* tmp2.x = |src0| */
4155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4156 alu.op = ALU_OP3_CNDGE_INT;
4157 alu.is_op3 = 1;
4158
4159 alu.dst.sel = tmp2;
4160 alu.dst.chan = 0;
4161 alu.dst.write = 1;
4162
4163 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4164 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4165 alu.src[2].sel = tmp2;
4166 alu.src[2].chan = 0;
4167
4168 alu.last = 1;
4169 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4170 return r;
4171
4172 /* tmp2.y = |src1| */
4173 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4174 alu.op = ALU_OP3_CNDGE_INT;
4175 alu.is_op3 = 1;
4176
4177 alu.dst.sel = tmp2;
4178 alu.dst.chan = 1;
4179 alu.dst.write = 1;
4180
4181 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4182 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4183 alu.src[2].sel = tmp2;
4184 alu.src[2].chan = 1;
4185
4186 alu.last = 1;
4187 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4188 return r;
4189
4190 }
4191
4192 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
4193 if (ctx->bc->chip_class == CAYMAN) {
4194 /* tmp3.x = u2f(src2) */
4195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4196 alu.op = ALU_OP1_UINT_TO_FLT;
4197
4198 alu.dst.sel = tmp3;
4199 alu.dst.chan = 0;
4200 alu.dst.write = 1;
4201
4202 if (signed_op) {
4203 alu.src[0].sel = tmp2;
4204 alu.src[0].chan = 1;
4205 } else {
4206 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4207 }
4208
4209 alu.last = 1;
4210 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4211 return r;
4212
4213 /* tmp0.x = recip(tmp3.x) */
4214 for (j = 0 ; j < 3; j++) {
4215 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4216 alu.op = ALU_OP1_RECIP_IEEE;
4217
4218 alu.dst.sel = tmp0;
4219 alu.dst.chan = j;
4220 alu.dst.write = (j == 0);
4221
4222 alu.src[0].sel = tmp3;
4223 alu.src[0].chan = 0;
4224
4225 if (j == 2)
4226 alu.last = 1;
4227 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4228 return r;
4229 }
4230
4231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4232 alu.op = ALU_OP2_MUL;
4233
4234 alu.src[0].sel = tmp0;
4235 alu.src[0].chan = 0;
4236
4237 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4238 alu.src[1].value = 0x4f800000;
4239
4240 alu.dst.sel = tmp3;
4241 alu.dst.write = 1;
4242 alu.last = 1;
4243 r = r600_bytecode_add_alu(ctx->bc, &alu);
4244 if (r)
4245 return r;
4246
4247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4248 alu.op = ALU_OP1_FLT_TO_UINT;
4249
4250 alu.dst.sel = tmp0;
4251 alu.dst.chan = 0;
4252 alu.dst.write = 1;
4253
4254 alu.src[0].sel = tmp3;
4255 alu.src[0].chan = 0;
4256
4257 alu.last = 1;
4258 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4259 return r;
4260
4261 } else {
4262 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4263 alu.op = ALU_OP1_RECIP_UINT;
4264
4265 alu.dst.sel = tmp0;
4266 alu.dst.chan = 0;
4267 alu.dst.write = 1;
4268
4269 if (signed_op) {
4270 alu.src[0].sel = tmp2;
4271 alu.src[0].chan = 1;
4272 } else {
4273 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4274 }
4275
4276 alu.last = 1;
4277 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4278 return r;
4279 }
4280
4281 /* 2. tmp0.z = lo (tmp0.x * src2) */
4282 if (ctx->bc->chip_class == CAYMAN) {
4283 for (j = 0 ; j < 4; j++) {
4284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4285 alu.op = ALU_OP2_MULLO_UINT;
4286
4287 alu.dst.sel = tmp0;
4288 alu.dst.chan = j;
4289 alu.dst.write = (j == 2);
4290
4291 alu.src[0].sel = tmp0;
4292 alu.src[0].chan = 0;
4293 if (signed_op) {
4294 alu.src[1].sel = tmp2;
4295 alu.src[1].chan = 1;
4296 } else {
4297 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4298 }
4299
4300 alu.last = (j == 3);
4301 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4302 return r;
4303 }
4304 } else {
4305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4306 alu.op = ALU_OP2_MULLO_UINT;
4307
4308 alu.dst.sel = tmp0;
4309 alu.dst.chan = 2;
4310 alu.dst.write = 1;
4311
4312 alu.src[0].sel = tmp0;
4313 alu.src[0].chan = 0;
4314 if (signed_op) {
4315 alu.src[1].sel = tmp2;
4316 alu.src[1].chan = 1;
4317 } else {
4318 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4319 }
4320
4321 alu.last = 1;
4322 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4323 return r;
4324 }
4325
4326 /* 3. tmp0.w = -tmp0.z */
4327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4328 alu.op = ALU_OP2_SUB_INT;
4329
4330 alu.dst.sel = tmp0;
4331 alu.dst.chan = 3;
4332 alu.dst.write = 1;
4333
4334 alu.src[0].sel = V_SQ_ALU_SRC_0;
4335 alu.src[1].sel = tmp0;
4336 alu.src[1].chan = 2;
4337
4338 alu.last = 1;
4339 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4340 return r;
4341
4342 /* 4. tmp0.y = hi (tmp0.x * src2) */
4343 if (ctx->bc->chip_class == CAYMAN) {
4344 for (j = 0 ; j < 4; j++) {
4345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4346 alu.op = ALU_OP2_MULHI_UINT;
4347
4348 alu.dst.sel = tmp0;
4349 alu.dst.chan = j;
4350 alu.dst.write = (j == 1);
4351
4352 alu.src[0].sel = tmp0;
4353 alu.src[0].chan = 0;
4354
4355 if (signed_op) {
4356 alu.src[1].sel = tmp2;
4357 alu.src[1].chan = 1;
4358 } else {
4359 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4360 }
4361 alu.last = (j == 3);
4362 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4363 return r;
4364 }
4365 } else {
4366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4367 alu.op = ALU_OP2_MULHI_UINT;
4368
4369 alu.dst.sel = tmp0;
4370 alu.dst.chan = 1;
4371 alu.dst.write = 1;
4372
4373 alu.src[0].sel = tmp0;
4374 alu.src[0].chan = 0;
4375
4376 if (signed_op) {
4377 alu.src[1].sel = tmp2;
4378 alu.src[1].chan = 1;
4379 } else {
4380 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4381 }
4382
4383 alu.last = 1;
4384 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4385 return r;
4386 }
4387
4388 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
4389 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4390 alu.op = ALU_OP3_CNDE_INT;
4391 alu.is_op3 = 1;
4392
4393 alu.dst.sel = tmp0;
4394 alu.dst.chan = 2;
4395 alu.dst.write = 1;
4396
4397 alu.src[0].sel = tmp0;
4398 alu.src[0].chan = 1;
4399 alu.src[1].sel = tmp0;
4400 alu.src[1].chan = 3;
4401 alu.src[2].sel = tmp0;
4402 alu.src[2].chan = 2;
4403
4404 alu.last = 1;
4405 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4406 return r;
4407
4408 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
4409 if (ctx->bc->chip_class == CAYMAN) {
4410 for (j = 0 ; j < 4; j++) {
4411 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4412 alu.op = ALU_OP2_MULHI_UINT;
4413
4414 alu.dst.sel = tmp0;
4415 alu.dst.chan = j;
4416 alu.dst.write = (j == 3);
4417
4418 alu.src[0].sel = tmp0;
4419 alu.src[0].chan = 2;
4420
4421 alu.src[1].sel = tmp0;
4422 alu.src[1].chan = 0;
4423
4424 alu.last = (j == 3);
4425 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4426 return r;
4427 }
4428 } else {
4429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4430 alu.op = ALU_OP2_MULHI_UINT;
4431
4432 alu.dst.sel = tmp0;
4433 alu.dst.chan = 3;
4434 alu.dst.write = 1;
4435
4436 alu.src[0].sel = tmp0;
4437 alu.src[0].chan = 2;
4438
4439 alu.src[1].sel = tmp0;
4440 alu.src[1].chan = 0;
4441
4442 alu.last = 1;
4443 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4444 return r;
4445 }
4446
4447 /* 7. tmp1.x = tmp0.x - tmp0.w */
4448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4449 alu.op = ALU_OP2_SUB_INT;
4450
4451 alu.dst.sel = tmp1;
4452 alu.dst.chan = 0;
4453 alu.dst.write = 1;
4454
4455 alu.src[0].sel = tmp0;
4456 alu.src[0].chan = 0;
4457 alu.src[1].sel = tmp0;
4458 alu.src[1].chan = 3;
4459
4460 alu.last = 1;
4461 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4462 return r;
4463
4464 /* 8. tmp1.y = tmp0.x + tmp0.w */
4465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4466 alu.op = ALU_OP2_ADD_INT;
4467
4468 alu.dst.sel = tmp1;
4469 alu.dst.chan = 1;
4470 alu.dst.write = 1;
4471
4472 alu.src[0].sel = tmp0;
4473 alu.src[0].chan = 0;
4474 alu.src[1].sel = tmp0;
4475 alu.src[1].chan = 3;
4476
4477 alu.last = 1;
4478 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4479 return r;
4480
4481 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
4482 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4483 alu.op = ALU_OP3_CNDE_INT;
4484 alu.is_op3 = 1;
4485
4486 alu.dst.sel = tmp0;
4487 alu.dst.chan = 0;
4488 alu.dst.write = 1;
4489
4490 alu.src[0].sel = tmp0;
4491 alu.src[0].chan = 1;
4492 alu.src[1].sel = tmp1;
4493 alu.src[1].chan = 1;
4494 alu.src[2].sel = tmp1;
4495 alu.src[2].chan = 0;
4496
4497 alu.last = 1;
4498 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4499 return r;
4500
4501 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
4502 if (ctx->bc->chip_class == CAYMAN) {
4503 for (j = 0 ; j < 4; j++) {
4504 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4505 alu.op = ALU_OP2_MULHI_UINT;
4506
4507 alu.dst.sel = tmp0;
4508 alu.dst.chan = j;
4509 alu.dst.write = (j == 2);
4510
4511 alu.src[0].sel = tmp0;
4512 alu.src[0].chan = 0;
4513
4514 if (signed_op) {
4515 alu.src[1].sel = tmp2;
4516 alu.src[1].chan = 0;
4517 } else {
4518 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4519 }
4520
4521 alu.last = (j == 3);
4522 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4523 return r;
4524 }
4525 } else {
4526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4527 alu.op = ALU_OP2_MULHI_UINT;
4528
4529 alu.dst.sel = tmp0;
4530 alu.dst.chan = 2;
4531 alu.dst.write = 1;
4532
4533 alu.src[0].sel = tmp0;
4534 alu.src[0].chan = 0;
4535
4536 if (signed_op) {
4537 alu.src[1].sel = tmp2;
4538 alu.src[1].chan = 0;
4539 } else {
4540 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4541 }
4542
4543 alu.last = 1;
4544 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4545 return r;
4546 }
4547
4548 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
4549 if (ctx->bc->chip_class == CAYMAN) {
4550 for (j = 0 ; j < 4; j++) {
4551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4552 alu.op = ALU_OP2_MULLO_UINT;
4553
4554 alu.dst.sel = tmp0;
4555 alu.dst.chan = j;
4556 alu.dst.write = (j == 1);
4557
4558 if (signed_op) {
4559 alu.src[0].sel = tmp2;
4560 alu.src[0].chan = 1;
4561 } else {
4562 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4563 }
4564
4565 alu.src[1].sel = tmp0;
4566 alu.src[1].chan = 2;
4567
4568 alu.last = (j == 3);
4569 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4570 return r;
4571 }
4572 } else {
4573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4574 alu.op = ALU_OP2_MULLO_UINT;
4575
4576 alu.dst.sel = tmp0;
4577 alu.dst.chan = 1;
4578 alu.dst.write = 1;
4579
4580 if (signed_op) {
4581 alu.src[0].sel = tmp2;
4582 alu.src[0].chan = 1;
4583 } else {
4584 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4585 }
4586
4587 alu.src[1].sel = tmp0;
4588 alu.src[1].chan = 2;
4589
4590 alu.last = 1;
4591 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4592 return r;
4593 }
4594
4595 /* 12. tmp0.w = src1 - tmp0.y = r */
4596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4597 alu.op = ALU_OP2_SUB_INT;
4598
4599 alu.dst.sel = tmp0;
4600 alu.dst.chan = 3;
4601 alu.dst.write = 1;
4602
4603 if (signed_op) {
4604 alu.src[0].sel = tmp2;
4605 alu.src[0].chan = 0;
4606 } else {
4607 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4608 }
4609
4610 alu.src[1].sel = tmp0;
4611 alu.src[1].chan = 1;
4612
4613 alu.last = 1;
4614 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4615 return r;
4616
4617 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
4618 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4619 alu.op = ALU_OP2_SETGE_UINT;
4620
4621 alu.dst.sel = tmp1;
4622 alu.dst.chan = 0;
4623 alu.dst.write = 1;
4624
4625 alu.src[0].sel = tmp0;
4626 alu.src[0].chan = 3;
4627 if (signed_op) {
4628 alu.src[1].sel = tmp2;
4629 alu.src[1].chan = 1;
4630 } else {
4631 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4632 }
4633
4634 alu.last = 1;
4635 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4636 return r;
4637
4638 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
4639 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4640 alu.op = ALU_OP2_SETGE_UINT;
4641
4642 alu.dst.sel = tmp1;
4643 alu.dst.chan = 1;
4644 alu.dst.write = 1;
4645
4646 if (signed_op) {
4647 alu.src[0].sel = tmp2;
4648 alu.src[0].chan = 0;
4649 } else {
4650 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4651 }
4652
4653 alu.src[1].sel = tmp0;
4654 alu.src[1].chan = 1;
4655
4656 alu.last = 1;
4657 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4658 return r;
4659
4660 if (mod) { /* UMOD */
4661
4662 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
4663 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4664 alu.op = ALU_OP2_SUB_INT;
4665
4666 alu.dst.sel = tmp1;
4667 alu.dst.chan = 2;
4668 alu.dst.write = 1;
4669
4670 alu.src[0].sel = tmp0;
4671 alu.src[0].chan = 3;
4672
4673 if (signed_op) {
4674 alu.src[1].sel = tmp2;
4675 alu.src[1].chan = 1;
4676 } else {
4677 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4678 }
4679
4680 alu.last = 1;
4681 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4682 return r;
4683
4684 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
4685 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4686 alu.op = ALU_OP2_ADD_INT;
4687
4688 alu.dst.sel = tmp1;
4689 alu.dst.chan = 3;
4690 alu.dst.write = 1;
4691
4692 alu.src[0].sel = tmp0;
4693 alu.src[0].chan = 3;
4694 if (signed_op) {
4695 alu.src[1].sel = tmp2;
4696 alu.src[1].chan = 1;
4697 } else {
4698 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4699 }
4700
4701 alu.last = 1;
4702 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4703 return r;
4704
4705 } else { /* UDIV */
4706
4707 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
4708 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4709 alu.op = ALU_OP2_ADD_INT;
4710
4711 alu.dst.sel = tmp1;
4712 alu.dst.chan = 2;
4713 alu.dst.write = 1;
4714
4715 alu.src[0].sel = tmp0;
4716 alu.src[0].chan = 2;
4717 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4718
4719 alu.last = 1;
4720 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4721 return r;
4722
4723 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
4724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4725 alu.op = ALU_OP2_ADD_INT;
4726
4727 alu.dst.sel = tmp1;
4728 alu.dst.chan = 3;
4729 alu.dst.write = 1;
4730
4731 alu.src[0].sel = tmp0;
4732 alu.src[0].chan = 2;
4733 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
4734
4735 alu.last = 1;
4736 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4737 return r;
4738
4739 }
4740
4741 /* 17. tmp1.x = tmp1.x & tmp1.y */
4742 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4743 alu.op = ALU_OP2_AND_INT;
4744
4745 alu.dst.sel = tmp1;
4746 alu.dst.chan = 0;
4747 alu.dst.write = 1;
4748
4749 alu.src[0].sel = tmp1;
4750 alu.src[0].chan = 0;
4751 alu.src[1].sel = tmp1;
4752 alu.src[1].chan = 1;
4753
4754 alu.last = 1;
4755 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4756 return r;
4757
4758 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
4759 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
4760 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4761 alu.op = ALU_OP3_CNDE_INT;
4762 alu.is_op3 = 1;
4763
4764 alu.dst.sel = tmp0;
4765 alu.dst.chan = 2;
4766 alu.dst.write = 1;
4767
4768 alu.src[0].sel = tmp1;
4769 alu.src[0].chan = 0;
4770 alu.src[1].sel = tmp0;
4771 alu.src[1].chan = mod ? 3 : 2;
4772 alu.src[2].sel = tmp1;
4773 alu.src[2].chan = 2;
4774
4775 alu.last = 1;
4776 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4777 return r;
4778
4779 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
4780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4781 alu.op = ALU_OP3_CNDE_INT;
4782 alu.is_op3 = 1;
4783
4784 if (signed_op) {
4785 alu.dst.sel = tmp0;
4786 alu.dst.chan = 2;
4787 alu.dst.write = 1;
4788 } else {
4789 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4790 }
4791
4792 alu.src[0].sel = tmp1;
4793 alu.src[0].chan = 1;
4794 alu.src[1].sel = tmp1;
4795 alu.src[1].chan = 3;
4796 alu.src[2].sel = tmp0;
4797 alu.src[2].chan = 2;
4798
4799 alu.last = 1;
4800 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4801 return r;
4802
4803 if (signed_op) {
4804
4805 /* fix the sign of the result */
4806
4807 if (mod) {
4808
4809 /* tmp0.x = -tmp0.z */
4810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4811 alu.op = ALU_OP2_SUB_INT;
4812
4813 alu.dst.sel = tmp0;
4814 alu.dst.chan = 0;
4815 alu.dst.write = 1;
4816
4817 alu.src[0].sel = V_SQ_ALU_SRC_0;
4818 alu.src[1].sel = tmp0;
4819 alu.src[1].chan = 2;
4820
4821 alu.last = 1;
4822 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4823 return r;
4824
4825 /* sign of the remainder is the same as the sign of src0 */
4826 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
4827 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4828 alu.op = ALU_OP3_CNDGE_INT;
4829 alu.is_op3 = 1;
4830
4831 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4832
4833 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4834 alu.src[1].sel = tmp0;
4835 alu.src[1].chan = 2;
4836 alu.src[2].sel = tmp0;
4837 alu.src[2].chan = 0;
4838
4839 alu.last = 1;
4840 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4841 return r;
4842
4843 } else {
4844
4845 /* tmp0.x = -tmp0.z */
4846 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4847 alu.op = ALU_OP2_SUB_INT;
4848
4849 alu.dst.sel = tmp0;
4850 alu.dst.chan = 0;
4851 alu.dst.write = 1;
4852
4853 alu.src[0].sel = V_SQ_ALU_SRC_0;
4854 alu.src[1].sel = tmp0;
4855 alu.src[1].chan = 2;
4856
4857 alu.last = 1;
4858 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4859 return r;
4860
4861 /* fix the quotient sign (same as the sign of src0*src1) */
4862 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
4863 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4864 alu.op = ALU_OP3_CNDGE_INT;
4865 alu.is_op3 = 1;
4866
4867 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4868
4869 alu.src[0].sel = tmp2;
4870 alu.src[0].chan = 2;
4871 alu.src[1].sel = tmp0;
4872 alu.src[1].chan = 2;
4873 alu.src[2].sel = tmp0;
4874 alu.src[2].chan = 0;
4875
4876 alu.last = 1;
4877 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4878 return r;
4879 }
4880 }
4881 }
4882 return 0;
4883 }
4884
4885 static int tgsi_udiv(struct r600_shader_ctx *ctx)
4886 {
4887 return tgsi_divmod(ctx, 0, 0);
4888 }
4889
4890 static int tgsi_umod(struct r600_shader_ctx *ctx)
4891 {
4892 return tgsi_divmod(ctx, 1, 0);
4893 }
4894
4895 static int tgsi_idiv(struct r600_shader_ctx *ctx)
4896 {
4897 return tgsi_divmod(ctx, 0, 1);
4898 }
4899
4900 static int tgsi_imod(struct r600_shader_ctx *ctx)
4901 {
4902 return tgsi_divmod(ctx, 1, 1);
4903 }
4904
4905
4906 static int tgsi_f2i(struct r600_shader_ctx *ctx)
4907 {
4908 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4909 struct r600_bytecode_alu alu;
4910 int i, r;
4911 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4912 int last_inst = tgsi_last_instruction(write_mask);
4913
4914 for (i = 0; i < 4; i++) {
4915 if (!(write_mask & (1<<i)))
4916 continue;
4917
4918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4919 alu.op = ALU_OP1_TRUNC;
4920
4921 alu.dst.sel = ctx->temp_reg;
4922 alu.dst.chan = i;
4923 alu.dst.write = 1;
4924
4925 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4926 if (i == last_inst)
4927 alu.last = 1;
4928 r = r600_bytecode_add_alu(ctx->bc, &alu);
4929 if (r)
4930 return r;
4931 }
4932
4933 for (i = 0; i < 4; i++) {
4934 if (!(write_mask & (1<<i)))
4935 continue;
4936
4937 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4938 alu.op = ctx->inst_info->op;
4939
4940 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4941
4942 alu.src[0].sel = ctx->temp_reg;
4943 alu.src[0].chan = i;
4944
4945 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
4946 alu.last = 1;
4947 r = r600_bytecode_add_alu(ctx->bc, &alu);
4948 if (r)
4949 return r;
4950 }
4951
4952 return 0;
4953 }
4954
4955 static int tgsi_iabs(struct r600_shader_ctx *ctx)
4956 {
4957 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4958 struct r600_bytecode_alu alu;
4959 int i, r;
4960 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4961 int last_inst = tgsi_last_instruction(write_mask);
4962
4963 /* tmp = -src */
4964 for (i = 0; i < 4; i++) {
4965 if (!(write_mask & (1<<i)))
4966 continue;
4967
4968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4969 alu.op = ALU_OP2_SUB_INT;
4970
4971 alu.dst.sel = ctx->temp_reg;
4972 alu.dst.chan = i;
4973 alu.dst.write = 1;
4974
4975 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4976 alu.src[0].sel = V_SQ_ALU_SRC_0;
4977
4978 if (i == last_inst)
4979 alu.last = 1;
4980 r = r600_bytecode_add_alu(ctx->bc, &alu);
4981 if (r)
4982 return r;
4983 }
4984
4985 /* dst = (src >= 0 ? src : tmp) */
4986 for (i = 0; i < 4; i++) {
4987 if (!(write_mask & (1<<i)))
4988 continue;
4989
4990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4991 alu.op = ALU_OP3_CNDGE_INT;
4992 alu.is_op3 = 1;
4993 alu.dst.write = 1;
4994
4995 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4996
4997 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4998 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4999 alu.src[2].sel = ctx->temp_reg;
5000 alu.src[2].chan = i;
5001
5002 if (i == last_inst)
5003 alu.last = 1;
5004 r = r600_bytecode_add_alu(ctx->bc, &alu);
5005 if (r)
5006 return r;
5007 }
5008 return 0;
5009 }
5010
5011 static int tgsi_issg(struct r600_shader_ctx *ctx)
5012 {
5013 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5014 struct r600_bytecode_alu alu;
5015 int i, r;
5016 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5017 int last_inst = tgsi_last_instruction(write_mask);
5018
5019 /* tmp = (src >= 0 ? src : -1) */
5020 for (i = 0; i < 4; i++) {
5021 if (!(write_mask & (1<<i)))
5022 continue;
5023
5024 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5025 alu.op = ALU_OP3_CNDGE_INT;
5026 alu.is_op3 = 1;
5027
5028 alu.dst.sel = ctx->temp_reg;
5029 alu.dst.chan = i;
5030 alu.dst.write = 1;
5031
5032 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5033 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5034 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
5035
5036 if (i == last_inst)
5037 alu.last = 1;
5038 r = r600_bytecode_add_alu(ctx->bc, &alu);
5039 if (r)
5040 return r;
5041 }
5042
5043 /* dst = (tmp > 0 ? 1 : tmp) */
5044 for (i = 0; i < 4; i++) {
5045 if (!(write_mask & (1<<i)))
5046 continue;
5047
5048 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5049 alu.op = ALU_OP3_CNDGT_INT;
5050 alu.is_op3 = 1;
5051 alu.dst.write = 1;
5052
5053 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5054
5055 alu.src[0].sel = ctx->temp_reg;
5056 alu.src[0].chan = i;
5057
5058 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5059
5060 alu.src[2].sel = ctx->temp_reg;
5061 alu.src[2].chan = i;
5062
5063 if (i == last_inst)
5064 alu.last = 1;
5065 r = r600_bytecode_add_alu(ctx->bc, &alu);
5066 if (r)
5067 return r;
5068 }
5069 return 0;
5070 }
5071
5072
5073
5074 static int tgsi_ssg(struct r600_shader_ctx *ctx)
5075 {
5076 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5077 struct r600_bytecode_alu alu;
5078 int i, r;
5079
5080 /* tmp = (src > 0 ? 1 : src) */
5081 for (i = 0; i < 4; i++) {
5082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5083 alu.op = ALU_OP3_CNDGT;
5084 alu.is_op3 = 1;
5085
5086 alu.dst.sel = ctx->temp_reg;
5087 alu.dst.chan = i;
5088
5089 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5090 alu.src[1].sel = V_SQ_ALU_SRC_1;
5091 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5092
5093 if (i == 3)
5094 alu.last = 1;
5095 r = r600_bytecode_add_alu(ctx->bc, &alu);
5096 if (r)
5097 return r;
5098 }
5099
5100 /* dst = (-tmp > 0 ? -1 : tmp) */
5101 for (i = 0; i < 4; i++) {
5102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5103 alu.op = ALU_OP3_CNDGT;
5104 alu.is_op3 = 1;
5105 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5106
5107 alu.src[0].sel = ctx->temp_reg;
5108 alu.src[0].chan = i;
5109 alu.src[0].neg = 1;
5110
5111 alu.src[1].sel = V_SQ_ALU_SRC_1;
5112 alu.src[1].neg = 1;
5113
5114 alu.src[2].sel = ctx->temp_reg;
5115 alu.src[2].chan = i;
5116
5117 if (i == 3)
5118 alu.last = 1;
5119 r = r600_bytecode_add_alu(ctx->bc, &alu);
5120 if (r)
5121 return r;
5122 }
5123 return 0;
5124 }
5125
5126 static int tgsi_bfi(struct r600_shader_ctx *ctx)
5127 {
5128 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5129 struct r600_bytecode_alu alu;
5130 int i, r, t1, t2;
5131
5132 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5133 int last_inst = tgsi_last_instruction(write_mask);
5134
5135 t1 = ctx->temp_reg;
5136
5137 for (i = 0; i < 4; i++) {
5138 if (!(write_mask & (1<<i)))
5139 continue;
5140
5141 /* create mask tmp */
5142 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5143 alu.op = ALU_OP2_BFM_INT;
5144 alu.dst.sel = t1;
5145 alu.dst.chan = i;
5146 alu.dst.write = 1;
5147 alu.last = i == last_inst;
5148
5149 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
5150 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5151
5152 r = r600_bytecode_add_alu(ctx->bc, &alu);
5153 if (r)
5154 return r;
5155 }
5156
5157 t2 = r600_get_temp(ctx);
5158
5159 for (i = 0; i < 4; i++) {
5160 if (!(write_mask & (1<<i)))
5161 continue;
5162
5163 /* shift insert left */
5164 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5165 alu.op = ALU_OP2_LSHL_INT;
5166 alu.dst.sel = t2;
5167 alu.dst.chan = i;
5168 alu.dst.write = 1;
5169 alu.last = i == last_inst;
5170
5171 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5172 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5173
5174 r = r600_bytecode_add_alu(ctx->bc, &alu);
5175 if (r)
5176 return r;
5177 }
5178
5179 for (i = 0; i < 4; i++) {
5180 if (!(write_mask & (1<<i)))
5181 continue;
5182
5183 /* actual bitfield insert */
5184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5185 alu.op = ALU_OP3_BFI_INT;
5186 alu.is_op3 = 1;
5187 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5188 alu.dst.chan = i;
5189 alu.dst.write = 1;
5190 alu.last = i == last_inst;
5191
5192 alu.src[0].sel = t1;
5193 alu.src[0].chan = i;
5194 alu.src[1].sel = t2;
5195 alu.src[1].chan = i;
5196 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
5197
5198 r = r600_bytecode_add_alu(ctx->bc, &alu);
5199 if (r)
5200 return r;
5201 }
5202
5203 return 0;
5204 }
5205
5206 static int tgsi_msb(struct r600_shader_ctx *ctx)
5207 {
5208 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5209 struct r600_bytecode_alu alu;
5210 int i, r, t1, t2;
5211
5212 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5213 int last_inst = tgsi_last_instruction(write_mask);
5214
5215 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
5216 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
5217
5218 t1 = ctx->temp_reg;
5219
5220 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
5221 for (i = 0; i < 4; i++) {
5222 if (!(write_mask & (1<<i)))
5223 continue;
5224
5225 /* t1 = FFBH_INT / FFBH_UINT */
5226 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5227 alu.op = ctx->inst_info->op;
5228 alu.dst.sel = t1;
5229 alu.dst.chan = i;
5230 alu.dst.write = 1;
5231 alu.last = i == last_inst;
5232
5233 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5234
5235 r = r600_bytecode_add_alu(ctx->bc, &alu);
5236 if (r)
5237 return r;
5238 }
5239
5240 t2 = r600_get_temp(ctx);
5241
5242 for (i = 0; i < 4; i++) {
5243 if (!(write_mask & (1<<i)))
5244 continue;
5245
5246 /* t2 = 31 - t1 */
5247 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5248 alu.op = ALU_OP2_SUB_INT;
5249 alu.dst.sel = t2;
5250 alu.dst.chan = i;
5251 alu.dst.write = 1;
5252 alu.last = i == last_inst;
5253
5254 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
5255 alu.src[0].value = 31;
5256 alu.src[1].sel = t1;
5257 alu.src[1].chan = i;
5258
5259 r = r600_bytecode_add_alu(ctx->bc, &alu);
5260 if (r)
5261 return r;
5262 }
5263
5264 for (i = 0; i < 4; i++) {
5265 if (!(write_mask & (1<<i)))
5266 continue;
5267
5268 /* result = t1 >= 0 ? t2 : t1 */
5269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5270 alu.op = ALU_OP3_CNDGE_INT;
5271 alu.is_op3 = 1;
5272 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5273 alu.dst.chan = i;
5274 alu.dst.write = 1;
5275 alu.last = i == last_inst;
5276
5277 alu.src[0].sel = t1;
5278 alu.src[0].chan = i;
5279 alu.src[1].sel = t2;
5280 alu.src[1].chan = i;
5281 alu.src[2].sel = t1;
5282 alu.src[2].chan = i;
5283
5284 r = r600_bytecode_add_alu(ctx->bc, &alu);
5285 if (r)
5286 return r;
5287 }
5288
5289 return 0;
5290 }
5291
5292 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
5293 {
5294 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5295 struct r600_bytecode_alu alu;
5296 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
5297 unsigned location;
5298 int input;
5299
5300 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5301
5302 input = inst->Src[0].Register.Index;
5303
5304 /* Interpolators have been marked for use already by allocate_system_value_inputs */
5305 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5306 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5307 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
5308 }
5309 else {
5310 location = TGSI_INTERPOLATE_LOC_CENTROID;
5311 }
5312
5313 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
5314 if (k < 0)
5315 k = 0;
5316 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
5317 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
5318
5319 /* NOTE: currently offset is not perspective correct */
5320 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5321 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5322 int sample_gpr = -1;
5323 int gradientsH, gradientsV;
5324 struct r600_bytecode_tex tex;
5325
5326 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5327 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
5328 }
5329
5330 gradientsH = r600_get_temp(ctx);
5331 gradientsV = r600_get_temp(ctx);
5332 for (i = 0; i < 2; i++) {
5333 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5334 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
5335 tex.src_gpr = interp_gpr;
5336 tex.src_sel_x = interp_base_chan + 0;
5337 tex.src_sel_y = interp_base_chan + 1;
5338 tex.src_sel_z = 0;
5339 tex.src_sel_w = 0;
5340 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
5341 tex.dst_sel_x = 0;
5342 tex.dst_sel_y = 1;
5343 tex.dst_sel_z = 7;
5344 tex.dst_sel_w = 7;
5345 tex.inst_mod = 1; // Use per pixel gradient calculation
5346 tex.sampler_id = 0;
5347 tex.resource_id = tex.sampler_id;
5348 r = r600_bytecode_add_tex(ctx->bc, &tex);
5349 if (r)
5350 return r;
5351 }
5352
5353 for (i = 0; i < 2; i++) {
5354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5355 alu.op = ALU_OP3_MULADD;
5356 alu.is_op3 = 1;
5357 alu.src[0].sel = gradientsH;
5358 alu.src[0].chan = i;
5359 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5360 alu.src[1].sel = sample_gpr;
5361 alu.src[1].chan = 2;
5362 }
5363 else {
5364 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
5365 }
5366 alu.src[2].sel = interp_gpr;
5367 alu.src[2].chan = interp_base_chan + i;
5368 alu.dst.sel = ctx->temp_reg;
5369 alu.dst.chan = i;
5370 alu.last = i == 1;
5371
5372 r = r600_bytecode_add_alu(ctx->bc, &alu);
5373 if (r)
5374 return r;
5375 }
5376
5377 for (i = 0; i < 2; i++) {
5378 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5379 alu.op = ALU_OP3_MULADD;
5380 alu.is_op3 = 1;
5381 alu.src[0].sel = gradientsV;
5382 alu.src[0].chan = i;
5383 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5384 alu.src[1].sel = sample_gpr;
5385 alu.src[1].chan = 3;
5386 }
5387 else {
5388 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
5389 }
5390 alu.src[2].sel = ctx->temp_reg;
5391 alu.src[2].chan = i;
5392 alu.dst.sel = ctx->temp_reg;
5393 alu.dst.chan = i;
5394 alu.last = i == 1;
5395
5396 r = r600_bytecode_add_alu(ctx->bc, &alu);
5397 if (r)
5398 return r;
5399 }
5400 }
5401
5402 tmp = r600_get_temp(ctx);
5403 for (i = 0; i < 8; i++) {
5404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5405 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
5406
5407 alu.dst.sel = tmp;
5408 if ((i > 1 && i < 6)) {
5409 alu.dst.write = 1;
5410 }
5411 else {
5412 alu.dst.write = 0;
5413 }
5414 alu.dst.chan = i % 4;
5415
5416 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5417 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5418 alu.src[0].sel = ctx->temp_reg;
5419 alu.src[0].chan = 1 - (i % 2);
5420 } else {
5421 alu.src[0].sel = interp_gpr;
5422 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
5423 }
5424 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
5425 alu.src[1].chan = 0;
5426
5427 alu.last = i % 4 == 3;
5428 alu.bank_swizzle_force = SQ_ALU_VEC_210;
5429
5430 r = r600_bytecode_add_alu(ctx->bc, &alu);
5431 if (r)
5432 return r;
5433 }
5434
5435 // INTERP can't swizzle dst
5436 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5437 for (i = 0; i <= lasti; i++) {
5438 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5439 continue;
5440
5441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5442 alu.op = ALU_OP1_MOV;
5443 alu.src[0].sel = tmp;
5444 alu.src[0].chan = ctx->src[0].swizzle[i];
5445 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5446 alu.dst.write = 1;
5447 alu.last = i == lasti;
5448 r = r600_bytecode_add_alu(ctx->bc, &alu);
5449 if (r)
5450 return r;
5451 }
5452
5453 return 0;
5454 }
5455
5456
5457 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
5458 {
5459 struct r600_bytecode_alu alu;
5460 int i, r;
5461
5462 for (i = 0; i < 4; i++) {
5463 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5464 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
5465 alu.op = ALU_OP0_NOP;
5466 alu.dst.chan = i;
5467 } else {
5468 alu.op = ALU_OP1_MOV;
5469 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5470 alu.src[0].sel = ctx->temp_reg;
5471 alu.src[0].chan = i;
5472 }
5473 if (i == 3) {
5474 alu.last = 1;
5475 }
5476 r = r600_bytecode_add_alu(ctx->bc, &alu);
5477 if (r)
5478 return r;
5479 }
5480 return 0;
5481 }
5482
5483 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
5484 unsigned temp, int chan,
5485 struct r600_bytecode_alu_src *bc_src,
5486 const struct r600_shader_src *shader_src)
5487 {
5488 struct r600_bytecode_alu alu;
5489 int r;
5490
5491 r600_bytecode_src(bc_src, shader_src, chan);
5492
5493 /* op3 operands don't support abs modifier */
5494 if (bc_src->abs) {
5495 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
5496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5497 alu.op = ALU_OP1_MOV;
5498 alu.dst.sel = temp;
5499 alu.dst.chan = chan;
5500 alu.dst.write = 1;
5501
5502 alu.src[0] = *bc_src;
5503 alu.last = true; // sufficient?
5504 r = r600_bytecode_add_alu(ctx->bc, &alu);
5505 if (r)
5506 return r;
5507
5508 memset(bc_src, 0, sizeof(*bc_src));
5509 bc_src->sel = temp;
5510 bc_src->chan = chan;
5511 }
5512 return 0;
5513 }
5514
5515 static int tgsi_op3(struct r600_shader_ctx *ctx)
5516 {
5517 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5518 struct r600_bytecode_alu alu;
5519 int i, j, r;
5520 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5521 int temp_regs[4];
5522
5523 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5524 temp_regs[j] = 0;
5525 if (ctx->src[j].abs)
5526 temp_regs[j] = r600_get_temp(ctx);
5527 }
5528 for (i = 0; i < lasti + 1; i++) {
5529 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5530 continue;
5531
5532 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5533 alu.op = ctx->inst_info->op;
5534 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5535 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
5536 if (r)
5537 return r;
5538 }
5539
5540 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5541 alu.dst.chan = i;
5542 alu.dst.write = 1;
5543 alu.is_op3 = 1;
5544 if (i == lasti) {
5545 alu.last = 1;
5546 }
5547 r = r600_bytecode_add_alu(ctx->bc, &alu);
5548 if (r)
5549 return r;
5550 }
5551 return 0;
5552 }
5553
5554 static int tgsi_dp(struct r600_shader_ctx *ctx)
5555 {
5556 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5557 struct r600_bytecode_alu alu;
5558 int i, j, r;
5559
5560 for (i = 0; i < 4; i++) {
5561 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5562 alu.op = ctx->inst_info->op;
5563 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5564 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5565 }
5566
5567 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5568 alu.dst.chan = i;
5569 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5570 /* handle some special cases */
5571 switch (inst->Instruction.Opcode) {
5572 case TGSI_OPCODE_DP2:
5573 if (i > 1) {
5574 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5575 alu.src[0].chan = alu.src[1].chan = 0;
5576 }
5577 break;
5578 case TGSI_OPCODE_DP3:
5579 if (i > 2) {
5580 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
5581 alu.src[0].chan = alu.src[1].chan = 0;
5582 }
5583 break;
5584 case TGSI_OPCODE_DPH:
5585 if (i == 3) {
5586 alu.src[0].sel = V_SQ_ALU_SRC_1;
5587 alu.src[0].chan = 0;
5588 alu.src[0].neg = 0;
5589 }
5590 break;
5591 default:
5592 break;
5593 }
5594 if (i == 3) {
5595 alu.last = 1;
5596 }
5597 r = r600_bytecode_add_alu(ctx->bc, &alu);
5598 if (r)
5599 return r;
5600 }
5601 return 0;
5602 }
5603
5604 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
5605 unsigned index)
5606 {
5607 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5608 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
5609 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
5610 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
5611 ctx->src[index].neg || ctx->src[index].abs ||
5612 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY);
5613 }
5614
5615 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
5616 unsigned index)
5617 {
5618 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5619 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
5620 }
5621
5622 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
5623 {
5624 struct r600_bytecode_vtx vtx;
5625 struct r600_bytecode_alu alu;
5626 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5627 int src_gpr, r, i;
5628 int id = tgsi_tex_get_src_gpr(ctx, 1);
5629
5630 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5631 if (src_requires_loading) {
5632 for (i = 0; i < 4; i++) {
5633 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5634 alu.op = ALU_OP1_MOV;
5635 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5636 alu.dst.sel = ctx->temp_reg;
5637 alu.dst.chan = i;
5638 if (i == 3)
5639 alu.last = 1;
5640 alu.dst.write = 1;
5641 r = r600_bytecode_add_alu(ctx->bc, &alu);
5642 if (r)
5643 return r;
5644 }
5645 src_gpr = ctx->temp_reg;
5646 }
5647
5648 memset(&vtx, 0, sizeof(vtx));
5649 vtx.op = FETCH_OP_VFETCH;
5650 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
5651 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
5652 vtx.src_gpr = src_gpr;
5653 vtx.mega_fetch_count = 16;
5654 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5655 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
5656 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
5657 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
5658 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
5659 vtx.use_const_fields = 1;
5660
5661 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
5662 return r;
5663
5664 if (ctx->bc->chip_class >= EVERGREEN)
5665 return 0;
5666
5667 for (i = 0; i < 4; i++) {
5668 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5669 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5670 continue;
5671
5672 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5673 alu.op = ALU_OP2_AND_INT;
5674
5675 alu.dst.chan = i;
5676 alu.dst.sel = vtx.dst_gpr;
5677 alu.dst.write = 1;
5678
5679 alu.src[0].sel = vtx.dst_gpr;
5680 alu.src[0].chan = i;
5681
5682 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
5683 alu.src[1].sel += (id * 2);
5684 alu.src[1].chan = i % 4;
5685 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5686
5687 if (i == lasti)
5688 alu.last = 1;
5689 r = r600_bytecode_add_alu(ctx->bc, &alu);
5690 if (r)
5691 return r;
5692 }
5693
5694 if (inst->Dst[0].Register.WriteMask & 3) {
5695 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5696 alu.op = ALU_OP2_OR_INT;
5697
5698 alu.dst.chan = 3;
5699 alu.dst.sel = vtx.dst_gpr;
5700 alu.dst.write = 1;
5701
5702 alu.src[0].sel = vtx.dst_gpr;
5703 alu.src[0].chan = 3;
5704
5705 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
5706 alu.src[1].chan = 0;
5707 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5708
5709 alu.last = 1;
5710 r = r600_bytecode_add_alu(ctx->bc, &alu);
5711 if (r)
5712 return r;
5713 }
5714 return 0;
5715 }
5716
5717 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
5718 {
5719 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5720 struct r600_bytecode_alu alu;
5721 int r;
5722 int id = tgsi_tex_get_src_gpr(ctx, 1);
5723
5724 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5725 alu.op = ALU_OP1_MOV;
5726 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
5727 if (ctx->bc->chip_class >= EVERGREEN) {
5728 /* channel 0 or 2 of each word */
5729 alu.src[0].sel += (id / 2);
5730 alu.src[0].chan = (id % 2) * 2;
5731 } else {
5732 /* r600 we have them at channel 2 of the second dword */
5733 alu.src[0].sel += (id * 2) + 1;
5734 alu.src[0].chan = 1;
5735 }
5736 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
5737 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5738 alu.last = 1;
5739 r = r600_bytecode_add_alu(ctx->bc, &alu);
5740 if (r)
5741 return r;
5742 return 0;
5743 }
5744
5745 static int tgsi_tex(struct r600_shader_ctx *ctx)
5746 {
5747 static float one_point_five = 1.5f;
5748 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5749 struct r600_bytecode_tex tex;
5750 struct r600_bytecode_alu alu;
5751 unsigned src_gpr;
5752 int r, i, j;
5753 int opcode;
5754 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
5755 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5756 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
5757 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
5758
5759 bool txf_add_offsets = inst->Texture.NumOffsets &&
5760 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
5761 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
5762
5763 /* Texture fetch instructions can only use gprs as source.
5764 * Also they cannot negate the source or take the absolute value */
5765 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
5766 inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
5767 tgsi_tex_src_requires_loading(ctx, 0)) ||
5768 read_compressed_msaa || txf_add_offsets;
5769
5770 boolean src_loaded = FALSE;
5771 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
5772 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
5773 boolean has_txq_cube_array_z = false;
5774 unsigned sampler_index_mode;
5775
5776 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
5777 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5778 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
5779 if (inst->Dst[0].Register.WriteMask & 4) {
5780 ctx->shader->has_txq_cube_array_z_comp = true;
5781 has_txq_cube_array_z = true;
5782 }
5783
5784 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
5785 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
5786 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
5787 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
5788 sampler_src_reg = 2;
5789
5790 /* TGSI moves the sampler to src reg 3 for TXD */
5791 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
5792 sampler_src_reg = 3;
5793
5794 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
5795
5796 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
5797
5798 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
5799 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
5800 ctx->shader->uses_tex_buffers = true;
5801 return r600_do_buffer_txq(ctx);
5802 }
5803 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
5804 if (ctx->bc->chip_class < EVERGREEN)
5805 ctx->shader->uses_tex_buffers = true;
5806 return do_vtx_fetch_inst(ctx, src_requires_loading);
5807 }
5808 }
5809
5810 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
5811 int out_chan;
5812 /* Add perspective divide */
5813 if (ctx->bc->chip_class == CAYMAN) {
5814 out_chan = 2;
5815 for (i = 0; i < 3; i++) {
5816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5817 alu.op = ALU_OP1_RECIP_IEEE;
5818 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5819
5820 alu.dst.sel = ctx->temp_reg;
5821 alu.dst.chan = i;
5822 if (i == 2)
5823 alu.last = 1;
5824 if (out_chan == i)
5825 alu.dst.write = 1;
5826 r = r600_bytecode_add_alu(ctx->bc, &alu);
5827 if (r)
5828 return r;
5829 }
5830
5831 } else {
5832 out_chan = 3;
5833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5834 alu.op = ALU_OP1_RECIP_IEEE;
5835 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5836
5837 alu.dst.sel = ctx->temp_reg;
5838 alu.dst.chan = out_chan;
5839 alu.last = 1;
5840 alu.dst.write = 1;
5841 r = r600_bytecode_add_alu(ctx->bc, &alu);
5842 if (r)
5843 return r;
5844 }
5845
5846 for (i = 0; i < 3; i++) {
5847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5848 alu.op = ALU_OP2_MUL;
5849 alu.src[0].sel = ctx->temp_reg;
5850 alu.src[0].chan = out_chan;
5851 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5852 alu.dst.sel = ctx->temp_reg;
5853 alu.dst.chan = i;
5854 alu.dst.write = 1;
5855 r = r600_bytecode_add_alu(ctx->bc, &alu);
5856 if (r)
5857 return r;
5858 }
5859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5860 alu.op = ALU_OP1_MOV;
5861 alu.src[0].sel = V_SQ_ALU_SRC_1;
5862 alu.src[0].chan = 0;
5863 alu.dst.sel = ctx->temp_reg;
5864 alu.dst.chan = 3;
5865 alu.last = 1;
5866 alu.dst.write = 1;
5867 r = r600_bytecode_add_alu(ctx->bc, &alu);
5868 if (r)
5869 return r;
5870 src_loaded = TRUE;
5871 src_gpr = ctx->temp_reg;
5872 }
5873
5874
5875 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5876 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5877 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5878 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5879 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
5880 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
5881
5882 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
5883 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
5884
5885 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
5886 for (i = 0; i < 4; i++) {
5887 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5888 alu.op = ALU_OP2_CUBE;
5889 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5890 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
5891 alu.dst.sel = ctx->temp_reg;
5892 alu.dst.chan = i;
5893 if (i == 3)
5894 alu.last = 1;
5895 alu.dst.write = 1;
5896 r = r600_bytecode_add_alu(ctx->bc, &alu);
5897 if (r)
5898 return r;
5899 }
5900
5901 /* tmp1.z = RCP_e(|tmp1.z|) */
5902 if (ctx->bc->chip_class == CAYMAN) {
5903 for (i = 0; i < 3; i++) {
5904 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5905 alu.op = ALU_OP1_RECIP_IEEE;
5906 alu.src[0].sel = ctx->temp_reg;
5907 alu.src[0].chan = 2;
5908 alu.src[0].abs = 1;
5909 alu.dst.sel = ctx->temp_reg;
5910 alu.dst.chan = i;
5911 if (i == 2)
5912 alu.dst.write = 1;
5913 if (i == 2)
5914 alu.last = 1;
5915 r = r600_bytecode_add_alu(ctx->bc, &alu);
5916 if (r)
5917 return r;
5918 }
5919 } else {
5920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5921 alu.op = ALU_OP1_RECIP_IEEE;
5922 alu.src[0].sel = ctx->temp_reg;
5923 alu.src[0].chan = 2;
5924 alu.src[0].abs = 1;
5925 alu.dst.sel = ctx->temp_reg;
5926 alu.dst.chan = 2;
5927 alu.dst.write = 1;
5928 alu.last = 1;
5929 r = r600_bytecode_add_alu(ctx->bc, &alu);
5930 if (r)
5931 return r;
5932 }
5933
5934 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
5935 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
5936 * muladd has no writemask, have to use another temp
5937 */
5938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5939 alu.op = ALU_OP3_MULADD;
5940 alu.is_op3 = 1;
5941
5942 alu.src[0].sel = ctx->temp_reg;
5943 alu.src[0].chan = 0;
5944 alu.src[1].sel = ctx->temp_reg;
5945 alu.src[1].chan = 2;
5946
5947 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5948 alu.src[2].chan = 0;
5949 alu.src[2].value = *(uint32_t *)&one_point_five;
5950
5951 alu.dst.sel = ctx->temp_reg;
5952 alu.dst.chan = 0;
5953 alu.dst.write = 1;
5954
5955 r = r600_bytecode_add_alu(ctx->bc, &alu);
5956 if (r)
5957 return r;
5958
5959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5960 alu.op = ALU_OP3_MULADD;
5961 alu.is_op3 = 1;
5962
5963 alu.src[0].sel = ctx->temp_reg;
5964 alu.src[0].chan = 1;
5965 alu.src[1].sel = ctx->temp_reg;
5966 alu.src[1].chan = 2;
5967
5968 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
5969 alu.src[2].chan = 0;
5970 alu.src[2].value = *(uint32_t *)&one_point_five;
5971
5972 alu.dst.sel = ctx->temp_reg;
5973 alu.dst.chan = 1;
5974 alu.dst.write = 1;
5975
5976 alu.last = 1;
5977 r = r600_bytecode_add_alu(ctx->bc, &alu);
5978 if (r)
5979 return r;
5980 /* write initial compare value into Z component
5981 - W src 0 for shadow cube
5982 - X src 1 for shadow cube array */
5983 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5984 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5986 alu.op = ALU_OP1_MOV;
5987 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
5988 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5989 else
5990 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
5991 alu.dst.sel = ctx->temp_reg;
5992 alu.dst.chan = 2;
5993 alu.dst.write = 1;
5994 alu.last = 1;
5995 r = r600_bytecode_add_alu(ctx->bc, &alu);
5996 if (r)
5997 return r;
5998 }
5999
6000 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6001 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6002 if (ctx->bc->chip_class >= EVERGREEN) {
6003 int mytmp = r600_get_temp(ctx);
6004 static const float eight = 8.0f;
6005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6006 alu.op = ALU_OP1_MOV;
6007 alu.src[0].sel = ctx->temp_reg;
6008 alu.src[0].chan = 3;
6009 alu.dst.sel = mytmp;
6010 alu.dst.chan = 0;
6011 alu.dst.write = 1;
6012 alu.last = 1;
6013 r = r600_bytecode_add_alu(ctx->bc, &alu);
6014 if (r)
6015 return r;
6016
6017 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
6018 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6019 alu.op = ALU_OP3_MULADD;
6020 alu.is_op3 = 1;
6021 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6022 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6023 alu.src[1].chan = 0;
6024 alu.src[1].value = *(uint32_t *)&eight;
6025 alu.src[2].sel = mytmp;
6026 alu.src[2].chan = 0;
6027 alu.dst.sel = ctx->temp_reg;
6028 alu.dst.chan = 3;
6029 alu.dst.write = 1;
6030 alu.last = 1;
6031 r = r600_bytecode_add_alu(ctx->bc, &alu);
6032 if (r)
6033 return r;
6034 } else if (ctx->bc->chip_class < EVERGREEN) {
6035 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6036 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
6037 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6038 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6039 tex.src_gpr = r600_get_temp(ctx);
6040 tex.src_sel_x = 0;
6041 tex.src_sel_y = 0;
6042 tex.src_sel_z = 0;
6043 tex.src_sel_w = 0;
6044 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6045 tex.coord_type_x = 1;
6046 tex.coord_type_y = 1;
6047 tex.coord_type_z = 1;
6048 tex.coord_type_w = 1;
6049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6050 alu.op = ALU_OP1_MOV;
6051 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6052 alu.dst.sel = tex.src_gpr;
6053 alu.dst.chan = 0;
6054 alu.last = 1;
6055 alu.dst.write = 1;
6056 r = r600_bytecode_add_alu(ctx->bc, &alu);
6057 if (r)
6058 return r;
6059
6060 r = r600_bytecode_add_tex(ctx->bc, &tex);
6061 if (r)
6062 return r;
6063 }
6064
6065 }
6066
6067 /* for cube forms of lod and bias we need to route things */
6068 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
6069 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
6070 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6071 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
6072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6073 alu.op = ALU_OP1_MOV;
6074 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6075 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
6076 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
6077 else
6078 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6079 alu.dst.sel = ctx->temp_reg;
6080 alu.dst.chan = 2;
6081 alu.last = 1;
6082 alu.dst.write = 1;
6083 r = r600_bytecode_add_alu(ctx->bc, &alu);
6084 if (r)
6085 return r;
6086 }
6087
6088 src_loaded = TRUE;
6089 src_gpr = ctx->temp_reg;
6090 }
6091
6092 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
6093 int temp_h = 0, temp_v = 0;
6094 int start_val = 0;
6095
6096 /* if we've already loaded the src (i.e. CUBE don't reload it). */
6097 if (src_loaded == TRUE)
6098 start_val = 1;
6099 else
6100 src_loaded = TRUE;
6101 for (i = start_val; i < 3; i++) {
6102 int treg = r600_get_temp(ctx);
6103
6104 if (i == 0)
6105 src_gpr = treg;
6106 else if (i == 1)
6107 temp_h = treg;
6108 else
6109 temp_v = treg;
6110
6111 for (j = 0; j < 4; j++) {
6112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6113 alu.op = ALU_OP1_MOV;
6114 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
6115 alu.dst.sel = treg;
6116 alu.dst.chan = j;
6117 if (j == 3)
6118 alu.last = 1;
6119 alu.dst.write = 1;
6120 r = r600_bytecode_add_alu(ctx->bc, &alu);
6121 if (r)
6122 return r;
6123 }
6124 }
6125 for (i = 1; i < 3; i++) {
6126 /* set gradients h/v */
6127 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6128 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
6129 FETCH_OP_SET_GRADIENTS_V;
6130 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6131 tex.sampler_index_mode = sampler_index_mode;
6132 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6133 tex.resource_index_mode = sampler_index_mode;
6134
6135 tex.src_gpr = (i == 1) ? temp_h : temp_v;
6136 tex.src_sel_x = 0;
6137 tex.src_sel_y = 1;
6138 tex.src_sel_z = 2;
6139 tex.src_sel_w = 3;
6140
6141 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
6142 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
6143 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
6144 tex.coord_type_x = 1;
6145 tex.coord_type_y = 1;
6146 tex.coord_type_z = 1;
6147 tex.coord_type_w = 1;
6148 }
6149 r = r600_bytecode_add_tex(ctx->bc, &tex);
6150 if (r)
6151 return r;
6152 }
6153 }
6154
6155 if (src_requires_loading && !src_loaded) {
6156 for (i = 0; i < 4; i++) {
6157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6158 alu.op = ALU_OP1_MOV;
6159 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6160 alu.dst.sel = ctx->temp_reg;
6161 alu.dst.chan = i;
6162 if (i == 3)
6163 alu.last = 1;
6164 alu.dst.write = 1;
6165 r = r600_bytecode_add_alu(ctx->bc, &alu);
6166 if (r)
6167 return r;
6168 }
6169 src_loaded = TRUE;
6170 src_gpr = ctx->temp_reg;
6171 }
6172
6173 /* get offset values */
6174 if (inst->Texture.NumOffsets) {
6175 assert(inst->Texture.NumOffsets == 1);
6176
6177 /* The texture offset feature doesn't work with the TXF instruction
6178 * and must be emulated by adding the offset to the texture coordinates. */
6179 if (txf_add_offsets) {
6180 const struct tgsi_texture_offset *off = inst->TexOffsets;
6181
6182 switch (inst->Texture.Texture) {
6183 case TGSI_TEXTURE_3D:
6184 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6185 alu.op = ALU_OP2_ADD_INT;
6186 alu.src[0].sel = src_gpr;
6187 alu.src[0].chan = 2;
6188 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6189 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
6190 alu.dst.sel = src_gpr;
6191 alu.dst.chan = 2;
6192 alu.dst.write = 1;
6193 alu.last = 1;
6194 r = r600_bytecode_add_alu(ctx->bc, &alu);
6195 if (r)
6196 return r;
6197 /* fall through */
6198
6199 case TGSI_TEXTURE_2D:
6200 case TGSI_TEXTURE_SHADOW2D:
6201 case TGSI_TEXTURE_RECT:
6202 case TGSI_TEXTURE_SHADOWRECT:
6203 case TGSI_TEXTURE_2D_ARRAY:
6204 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6206 alu.op = ALU_OP2_ADD_INT;
6207 alu.src[0].sel = src_gpr;
6208 alu.src[0].chan = 1;
6209 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6210 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
6211 alu.dst.sel = src_gpr;
6212 alu.dst.chan = 1;
6213 alu.dst.write = 1;
6214 alu.last = 1;
6215 r = r600_bytecode_add_alu(ctx->bc, &alu);
6216 if (r)
6217 return r;
6218 /* fall through */
6219
6220 case TGSI_TEXTURE_1D:
6221 case TGSI_TEXTURE_SHADOW1D:
6222 case TGSI_TEXTURE_1D_ARRAY:
6223 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6225 alu.op = ALU_OP2_ADD_INT;
6226 alu.src[0].sel = src_gpr;
6227 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6228 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
6229 alu.dst.sel = src_gpr;
6230 alu.dst.write = 1;
6231 alu.last = 1;
6232 r = r600_bytecode_add_alu(ctx->bc, &alu);
6233 if (r)
6234 return r;
6235 break;
6236 /* texture offsets do not apply to other texture targets */
6237 }
6238 } else {
6239 switch (inst->Texture.Texture) {
6240 case TGSI_TEXTURE_3D:
6241 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
6242 /* fallthrough */
6243 case TGSI_TEXTURE_2D:
6244 case TGSI_TEXTURE_SHADOW2D:
6245 case TGSI_TEXTURE_RECT:
6246 case TGSI_TEXTURE_SHADOWRECT:
6247 case TGSI_TEXTURE_2D_ARRAY:
6248 case TGSI_TEXTURE_SHADOW2D_ARRAY:
6249 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
6250 /* fallthrough */
6251 case TGSI_TEXTURE_1D:
6252 case TGSI_TEXTURE_SHADOW1D:
6253 case TGSI_TEXTURE_1D_ARRAY:
6254 case TGSI_TEXTURE_SHADOW1D_ARRAY:
6255 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
6256 }
6257 }
6258 }
6259
6260 /* Obtain the sample index for reading a compressed MSAA color texture.
6261 * To read the FMASK, we use the ldfptr instruction, which tells us
6262 * where the samples are stored.
6263 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
6264 * which is the identity mapping. Each nibble says which physical sample
6265 * should be fetched to get that sample.
6266 *
6267 * Assume src.z contains the sample index. It should be modified like this:
6268 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
6269 * Then fetch the texel with src.
6270 */
6271 if (read_compressed_msaa) {
6272 unsigned sample_chan = 3;
6273 unsigned temp = r600_get_temp(ctx);
6274 assert(src_loaded);
6275
6276 /* temp.w = ldfptr() */
6277 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6278 tex.op = FETCH_OP_LD;
6279 tex.inst_mod = 1; /* to indicate this is ldfptr */
6280 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6281 tex.sampler_index_mode = sampler_index_mode;
6282 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6283 tex.resource_index_mode = sampler_index_mode;
6284 tex.src_gpr = src_gpr;
6285 tex.dst_gpr = temp;
6286 tex.dst_sel_x = 7; /* mask out these components */
6287 tex.dst_sel_y = 7;
6288 tex.dst_sel_z = 7;
6289 tex.dst_sel_w = 0; /* store X */
6290 tex.src_sel_x = 0;
6291 tex.src_sel_y = 1;
6292 tex.src_sel_z = 2;
6293 tex.src_sel_w = 3;
6294 tex.offset_x = offset_x;
6295 tex.offset_y = offset_y;
6296 tex.offset_z = offset_z;
6297 r = r600_bytecode_add_tex(ctx->bc, &tex);
6298 if (r)
6299 return r;
6300
6301 /* temp.x = sample_index*4 */
6302 if (ctx->bc->chip_class == CAYMAN) {
6303 for (i = 0 ; i < 4; i++) {
6304 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6305 alu.op = ALU_OP2_MULLO_INT;
6306 alu.src[0].sel = src_gpr;
6307 alu.src[0].chan = sample_chan;
6308 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6309 alu.src[1].value = 4;
6310 alu.dst.sel = temp;
6311 alu.dst.chan = i;
6312 alu.dst.write = i == 0;
6313 if (i == 3)
6314 alu.last = 1;
6315 r = r600_bytecode_add_alu(ctx->bc, &alu);
6316 if (r)
6317 return r;
6318 }
6319 } else {
6320 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6321 alu.op = ALU_OP2_MULLO_INT;
6322 alu.src[0].sel = src_gpr;
6323 alu.src[0].chan = sample_chan;
6324 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6325 alu.src[1].value = 4;
6326 alu.dst.sel = temp;
6327 alu.dst.chan = 0;
6328 alu.dst.write = 1;
6329 alu.last = 1;
6330 r = r600_bytecode_add_alu(ctx->bc, &alu);
6331 if (r)
6332 return r;
6333 }
6334
6335 /* sample_index = temp.w >> temp.x */
6336 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6337 alu.op = ALU_OP2_LSHR_INT;
6338 alu.src[0].sel = temp;
6339 alu.src[0].chan = 3;
6340 alu.src[1].sel = temp;
6341 alu.src[1].chan = 0;
6342 alu.dst.sel = src_gpr;
6343 alu.dst.chan = sample_chan;
6344 alu.dst.write = 1;
6345 alu.last = 1;
6346 r = r600_bytecode_add_alu(ctx->bc, &alu);
6347 if (r)
6348 return r;
6349
6350 /* sample_index & 0xF */
6351 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6352 alu.op = ALU_OP2_AND_INT;
6353 alu.src[0].sel = src_gpr;
6354 alu.src[0].chan = sample_chan;
6355 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6356 alu.src[1].value = 0xF;
6357 alu.dst.sel = src_gpr;
6358 alu.dst.chan = sample_chan;
6359 alu.dst.write = 1;
6360 alu.last = 1;
6361 r = r600_bytecode_add_alu(ctx->bc, &alu);
6362 if (r)
6363 return r;
6364 #if 0
6365 /* visualize the FMASK */
6366 for (i = 0; i < 4; i++) {
6367 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6368 alu.op = ALU_OP1_INT_TO_FLT;
6369 alu.src[0].sel = src_gpr;
6370 alu.src[0].chan = sample_chan;
6371 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6372 alu.dst.chan = i;
6373 alu.dst.write = 1;
6374 alu.last = 1;
6375 r = r600_bytecode_add_alu(ctx->bc, &alu);
6376 if (r)
6377 return r;
6378 }
6379 return 0;
6380 #endif
6381 }
6382
6383 /* does this shader want a num layers from TXQ for a cube array? */
6384 if (has_txq_cube_array_z) {
6385 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6386
6387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6388 alu.op = ALU_OP1_MOV;
6389
6390 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6391 if (ctx->bc->chip_class >= EVERGREEN) {
6392 /* channel 1 or 3 of each word */
6393 alu.src[0].sel += (id / 2);
6394 alu.src[0].chan = ((id % 2) * 2) + 1;
6395 } else {
6396 /* r600 we have them at channel 2 of the second dword */
6397 alu.src[0].sel += (id * 2) + 1;
6398 alu.src[0].chan = 2;
6399 }
6400 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6401 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
6402 alu.last = 1;
6403 r = r600_bytecode_add_alu(ctx->bc, &alu);
6404 if (r)
6405 return r;
6406 /* disable writemask from texture instruction */
6407 inst->Dst[0].Register.WriteMask &= ~4;
6408 }
6409
6410 opcode = ctx->inst_info->op;
6411 if (opcode == FETCH_OP_GATHER4 &&
6412 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
6413 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
6414 opcode = FETCH_OP_GATHER4_O;
6415
6416 /* GATHER4_O/GATHER4_C_O use offset values loaded by
6417 SET_TEXTURE_OFFSETS instruction. The immediate offset values
6418 encoded in the instruction are ignored. */
6419 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6420 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
6421 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6422 tex.sampler_index_mode = sampler_index_mode;
6423 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6424 tex.resource_index_mode = sampler_index_mode;
6425
6426 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
6427 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
6428 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
6429 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
6430 tex.src_sel_w = 4;
6431
6432 tex.dst_sel_x = 7;
6433 tex.dst_sel_y = 7;
6434 tex.dst_sel_z = 7;
6435 tex.dst_sel_w = 7;
6436
6437 r = r600_bytecode_add_tex(ctx->bc, &tex);
6438 if (r)
6439 return r;
6440 }
6441
6442 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6443 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6444 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6445 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6446 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
6447 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6448 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6449 switch (opcode) {
6450 case FETCH_OP_SAMPLE:
6451 opcode = FETCH_OP_SAMPLE_C;
6452 break;
6453 case FETCH_OP_SAMPLE_L:
6454 opcode = FETCH_OP_SAMPLE_C_L;
6455 break;
6456 case FETCH_OP_SAMPLE_LB:
6457 opcode = FETCH_OP_SAMPLE_C_LB;
6458 break;
6459 case FETCH_OP_SAMPLE_G:
6460 opcode = FETCH_OP_SAMPLE_C_G;
6461 break;
6462 /* Texture gather variants */
6463 case FETCH_OP_GATHER4:
6464 opcode = FETCH_OP_GATHER4_C;
6465 break;
6466 case FETCH_OP_GATHER4_O:
6467 opcode = FETCH_OP_GATHER4_C_O;
6468 break;
6469 }
6470 }
6471
6472 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6473 tex.op = opcode;
6474
6475 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
6476 tex.sampler_index_mode = sampler_index_mode;
6477 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
6478 tex.resource_index_mode = sampler_index_mode;
6479 tex.src_gpr = src_gpr;
6480 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6481
6482 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
6483 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
6484 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
6485 }
6486
6487 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
6488 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
6489 tex.inst_mod = texture_component_select;
6490
6491 if (ctx->bc->chip_class == CAYMAN) {
6492 /* GATHER4 result order is different from TGSI TG4 */
6493 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
6494 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
6495 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
6496 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6497 } else {
6498 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6499 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6500 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6501 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6502 }
6503 }
6504 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
6505 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6506 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6507 tex.dst_sel_z = 7;
6508 tex.dst_sel_w = 7;
6509 }
6510 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6511 tex.dst_sel_x = 3;
6512 tex.dst_sel_y = 7;
6513 tex.dst_sel_z = 7;
6514 tex.dst_sel_w = 7;
6515 }
6516 else {
6517 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
6518 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
6519 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
6520 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
6521 }
6522
6523
6524 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ||
6525 inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
6526 tex.src_sel_x = 4;
6527 tex.src_sel_y = 4;
6528 tex.src_sel_z = 4;
6529 tex.src_sel_w = 4;
6530 } else if (src_loaded) {
6531 tex.src_sel_x = 0;
6532 tex.src_sel_y = 1;
6533 tex.src_sel_z = 2;
6534 tex.src_sel_w = 3;
6535 } else {
6536 tex.src_sel_x = ctx->src[0].swizzle[0];
6537 tex.src_sel_y = ctx->src[0].swizzle[1];
6538 tex.src_sel_z = ctx->src[0].swizzle[2];
6539 tex.src_sel_w = ctx->src[0].swizzle[3];
6540 tex.src_rel = ctx->src[0].rel;
6541 }
6542
6543 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6544 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6545 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6546 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
6547 tex.src_sel_x = 1;
6548 tex.src_sel_y = 0;
6549 tex.src_sel_z = 3;
6550 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
6551 }
6552
6553 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
6554 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
6555 tex.coord_type_x = 1;
6556 tex.coord_type_y = 1;
6557 }
6558 tex.coord_type_z = 1;
6559 tex.coord_type_w = 1;
6560
6561 tex.offset_x = offset_x;
6562 tex.offset_y = offset_y;
6563 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
6564 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6565 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
6566 tex.offset_z = 0;
6567 }
6568 else {
6569 tex.offset_z = offset_z;
6570 }
6571
6572 /* Put the depth for comparison in W.
6573 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
6574 * Some instructions expect the depth in Z. */
6575 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
6576 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
6577 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
6578 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
6579 opcode != FETCH_OP_SAMPLE_C_L &&
6580 opcode != FETCH_OP_SAMPLE_C_LB) {
6581 tex.src_sel_w = tex.src_sel_z;
6582 }
6583
6584 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
6585 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
6586 if (opcode == FETCH_OP_SAMPLE_C_L ||
6587 opcode == FETCH_OP_SAMPLE_C_LB) {
6588 /* the array index is read from Y */
6589 tex.coord_type_y = 0;
6590 } else {
6591 /* the array index is read from Z */
6592 tex.coord_type_z = 0;
6593 tex.src_sel_z = tex.src_sel_y;
6594 }
6595 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
6596 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
6597 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6598 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6599 (ctx->bc->chip_class >= EVERGREEN)))
6600 /* the array index is read from Z */
6601 tex.coord_type_z = 0;
6602
6603 /* mask unused source components */
6604 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
6605 switch (inst->Texture.Texture) {
6606 case TGSI_TEXTURE_2D:
6607 case TGSI_TEXTURE_RECT:
6608 tex.src_sel_z = 7;
6609 tex.src_sel_w = 7;
6610 break;
6611 case TGSI_TEXTURE_1D_ARRAY:
6612 tex.src_sel_y = 7;
6613 tex.src_sel_w = 7;
6614 break;
6615 case TGSI_TEXTURE_1D:
6616 tex.src_sel_y = 7;
6617 tex.src_sel_z = 7;
6618 tex.src_sel_w = 7;
6619 break;
6620 }
6621 }
6622
6623 r = r600_bytecode_add_tex(ctx->bc, &tex);
6624 if (r)
6625 return r;
6626
6627 /* add shadow ambient support - gallium doesn't do it yet */
6628 return 0;
6629 }
6630
6631 static int tgsi_lrp(struct r600_shader_ctx *ctx)
6632 {
6633 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6634 struct r600_bytecode_alu alu;
6635 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6636 unsigned i, temp_regs[2];
6637 int r;
6638
6639 /* optimize if it's just an equal balance */
6640 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
6641 for (i = 0; i < lasti + 1; i++) {
6642 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6643 continue;
6644
6645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6646 alu.op = ALU_OP2_ADD;
6647 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6648 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6649 alu.omod = 3;
6650 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6651 alu.dst.chan = i;
6652 if (i == lasti) {
6653 alu.last = 1;
6654 }
6655 r = r600_bytecode_add_alu(ctx->bc, &alu);
6656 if (r)
6657 return r;
6658 }
6659 return 0;
6660 }
6661
6662 /* 1 - src0 */
6663 for (i = 0; i < lasti + 1; i++) {
6664 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6665 continue;
6666
6667 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6668 alu.op = ALU_OP2_ADD;
6669 alu.src[0].sel = V_SQ_ALU_SRC_1;
6670 alu.src[0].chan = 0;
6671 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6672 r600_bytecode_src_toggle_neg(&alu.src[1]);
6673 alu.dst.sel = ctx->temp_reg;
6674 alu.dst.chan = i;
6675 if (i == lasti) {
6676 alu.last = 1;
6677 }
6678 alu.dst.write = 1;
6679 r = r600_bytecode_add_alu(ctx->bc, &alu);
6680 if (r)
6681 return r;
6682 }
6683
6684 /* (1 - src0) * src2 */
6685 for (i = 0; i < lasti + 1; i++) {
6686 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6687 continue;
6688
6689 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6690 alu.op = ALU_OP2_MUL;
6691 alu.src[0].sel = ctx->temp_reg;
6692 alu.src[0].chan = i;
6693 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6694 alu.dst.sel = ctx->temp_reg;
6695 alu.dst.chan = i;
6696 if (i == lasti) {
6697 alu.last = 1;
6698 }
6699 alu.dst.write = 1;
6700 r = r600_bytecode_add_alu(ctx->bc, &alu);
6701 if (r)
6702 return r;
6703 }
6704
6705 /* src0 * src1 + (1 - src0) * src2 */
6706 if (ctx->src[0].abs)
6707 temp_regs[0] = r600_get_temp(ctx);
6708 else
6709 temp_regs[0] = 0;
6710 if (ctx->src[1].abs)
6711 temp_regs[1] = r600_get_temp(ctx);
6712 else
6713 temp_regs[1] = 0;
6714
6715 for (i = 0; i < lasti + 1; i++) {
6716 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6717 continue;
6718
6719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6720 alu.op = ALU_OP3_MULADD;
6721 alu.is_op3 = 1;
6722 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6723 if (r)
6724 return r;
6725 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
6726 if (r)
6727 return r;
6728 alu.src[2].sel = ctx->temp_reg;
6729 alu.src[2].chan = i;
6730
6731 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6732 alu.dst.chan = i;
6733 if (i == lasti) {
6734 alu.last = 1;
6735 }
6736 r = r600_bytecode_add_alu(ctx->bc, &alu);
6737 if (r)
6738 return r;
6739 }
6740 return 0;
6741 }
6742
6743 static int tgsi_cmp(struct r600_shader_ctx *ctx)
6744 {
6745 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6746 struct r600_bytecode_alu alu;
6747 int i, r, j;
6748 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6749 int temp_regs[3];
6750
6751 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6752 temp_regs[j] = 0;
6753 if (ctx->src[j].abs)
6754 temp_regs[j] = r600_get_temp(ctx);
6755 }
6756
6757 for (i = 0; i < lasti + 1; i++) {
6758 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6759 continue;
6760
6761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6762 alu.op = ALU_OP3_CNDGE;
6763 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
6764 if (r)
6765 return r;
6766 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
6767 if (r)
6768 return r;
6769 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
6770 if (r)
6771 return r;
6772 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6773 alu.dst.chan = i;
6774 alu.dst.write = 1;
6775 alu.is_op3 = 1;
6776 if (i == lasti)
6777 alu.last = 1;
6778 r = r600_bytecode_add_alu(ctx->bc, &alu);
6779 if (r)
6780 return r;
6781 }
6782 return 0;
6783 }
6784
6785 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
6786 {
6787 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6788 struct r600_bytecode_alu alu;
6789 int i, r;
6790 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6791
6792 for (i = 0; i < lasti + 1; i++) {
6793 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6794 continue;
6795
6796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6797 alu.op = ALU_OP3_CNDE_INT;
6798 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6799 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6800 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6801 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6802 alu.dst.chan = i;
6803 alu.dst.write = 1;
6804 alu.is_op3 = 1;
6805 if (i == lasti)
6806 alu.last = 1;
6807 r = r600_bytecode_add_alu(ctx->bc, &alu);
6808 if (r)
6809 return r;
6810 }
6811 return 0;
6812 }
6813
6814 static int tgsi_xpd(struct r600_shader_ctx *ctx)
6815 {
6816 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6817 static const unsigned int src0_swizzle[] = {2, 0, 1};
6818 static const unsigned int src1_swizzle[] = {1, 2, 0};
6819 struct r600_bytecode_alu alu;
6820 uint32_t use_temp = 0;
6821 int i, r;
6822
6823 if (inst->Dst[0].Register.WriteMask != 0xf)
6824 use_temp = 1;
6825
6826 for (i = 0; i < 4; i++) {
6827 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6828 alu.op = ALU_OP2_MUL;
6829 if (i < 3) {
6830 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6831 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
6832 } else {
6833 alu.src[0].sel = V_SQ_ALU_SRC_0;
6834 alu.src[0].chan = i;
6835 alu.src[1].sel = V_SQ_ALU_SRC_0;
6836 alu.src[1].chan = i;
6837 }
6838
6839 alu.dst.sel = ctx->temp_reg;
6840 alu.dst.chan = i;
6841 alu.dst.write = 1;
6842
6843 if (i == 3)
6844 alu.last = 1;
6845 r = r600_bytecode_add_alu(ctx->bc, &alu);
6846 if (r)
6847 return r;
6848 }
6849
6850 for (i = 0; i < 4; i++) {
6851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6852 alu.op = ALU_OP3_MULADD;
6853
6854 if (i < 3) {
6855 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
6856 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
6857 } else {
6858 alu.src[0].sel = V_SQ_ALU_SRC_0;
6859 alu.src[0].chan = i;
6860 alu.src[1].sel = V_SQ_ALU_SRC_0;
6861 alu.src[1].chan = i;
6862 }
6863
6864 alu.src[2].sel = ctx->temp_reg;
6865 alu.src[2].neg = 1;
6866 alu.src[2].chan = i;
6867
6868 if (use_temp)
6869 alu.dst.sel = ctx->temp_reg;
6870 else
6871 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6872 alu.dst.chan = i;
6873 alu.dst.write = 1;
6874 alu.is_op3 = 1;
6875 if (i == 3)
6876 alu.last = 1;
6877 r = r600_bytecode_add_alu(ctx->bc, &alu);
6878 if (r)
6879 return r;
6880 }
6881 if (use_temp)
6882 return tgsi_helper_copy(ctx, inst);
6883 return 0;
6884 }
6885
6886 static int tgsi_exp(struct r600_shader_ctx *ctx)
6887 {
6888 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6889 struct r600_bytecode_alu alu;
6890 int r;
6891 int i;
6892
6893 /* result.x = 2^floor(src); */
6894 if (inst->Dst[0].Register.WriteMask & 1) {
6895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6896
6897 alu.op = ALU_OP1_FLOOR;
6898 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6899
6900 alu.dst.sel = ctx->temp_reg;
6901 alu.dst.chan = 0;
6902 alu.dst.write = 1;
6903 alu.last = 1;
6904 r = r600_bytecode_add_alu(ctx->bc, &alu);
6905 if (r)
6906 return r;
6907
6908 if (ctx->bc->chip_class == CAYMAN) {
6909 for (i = 0; i < 3; i++) {
6910 alu.op = ALU_OP1_EXP_IEEE;
6911 alu.src[0].sel = ctx->temp_reg;
6912 alu.src[0].chan = 0;
6913
6914 alu.dst.sel = ctx->temp_reg;
6915 alu.dst.chan = i;
6916 alu.dst.write = i == 0;
6917 alu.last = i == 2;
6918 r = r600_bytecode_add_alu(ctx->bc, &alu);
6919 if (r)
6920 return r;
6921 }
6922 } else {
6923 alu.op = ALU_OP1_EXP_IEEE;
6924 alu.src[0].sel = ctx->temp_reg;
6925 alu.src[0].chan = 0;
6926
6927 alu.dst.sel = ctx->temp_reg;
6928 alu.dst.chan = 0;
6929 alu.dst.write = 1;
6930 alu.last = 1;
6931 r = r600_bytecode_add_alu(ctx->bc, &alu);
6932 if (r)
6933 return r;
6934 }
6935 }
6936
6937 /* result.y = tmp - floor(tmp); */
6938 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
6939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6940
6941 alu.op = ALU_OP1_FRACT;
6942 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6943
6944 alu.dst.sel = ctx->temp_reg;
6945 #if 0
6946 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6947 if (r)
6948 return r;
6949 #endif
6950 alu.dst.write = 1;
6951 alu.dst.chan = 1;
6952
6953 alu.last = 1;
6954
6955 r = r600_bytecode_add_alu(ctx->bc, &alu);
6956 if (r)
6957 return r;
6958 }
6959
6960 /* result.z = RoughApprox2ToX(tmp);*/
6961 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
6962 if (ctx->bc->chip_class == CAYMAN) {
6963 for (i = 0; i < 3; i++) {
6964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6965 alu.op = ALU_OP1_EXP_IEEE;
6966 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6967
6968 alu.dst.sel = ctx->temp_reg;
6969 alu.dst.chan = i;
6970 if (i == 2) {
6971 alu.dst.write = 1;
6972 alu.last = 1;
6973 }
6974
6975 r = r600_bytecode_add_alu(ctx->bc, &alu);
6976 if (r)
6977 return r;
6978 }
6979 } else {
6980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6981 alu.op = ALU_OP1_EXP_IEEE;
6982 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6983
6984 alu.dst.sel = ctx->temp_reg;
6985 alu.dst.write = 1;
6986 alu.dst.chan = 2;
6987
6988 alu.last = 1;
6989
6990 r = r600_bytecode_add_alu(ctx->bc, &alu);
6991 if (r)
6992 return r;
6993 }
6994 }
6995
6996 /* result.w = 1.0;*/
6997 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
6998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6999
7000 alu.op = ALU_OP1_MOV;
7001 alu.src[0].sel = V_SQ_ALU_SRC_1;
7002 alu.src[0].chan = 0;
7003
7004 alu.dst.sel = ctx->temp_reg;
7005 alu.dst.chan = 3;
7006 alu.dst.write = 1;
7007 alu.last = 1;
7008 r = r600_bytecode_add_alu(ctx->bc, &alu);
7009 if (r)
7010 return r;
7011 }
7012 return tgsi_helper_copy(ctx, inst);
7013 }
7014
7015 static int tgsi_log(struct r600_shader_ctx *ctx)
7016 {
7017 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7018 struct r600_bytecode_alu alu;
7019 int r;
7020 int i;
7021
7022 /* result.x = floor(log2(|src|)); */
7023 if (inst->Dst[0].Register.WriteMask & 1) {
7024 if (ctx->bc->chip_class == CAYMAN) {
7025 for (i = 0; i < 3; i++) {
7026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7027
7028 alu.op = ALU_OP1_LOG_IEEE;
7029 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7030 r600_bytecode_src_set_abs(&alu.src[0]);
7031
7032 alu.dst.sel = ctx->temp_reg;
7033 alu.dst.chan = i;
7034 if (i == 0)
7035 alu.dst.write = 1;
7036 if (i == 2)
7037 alu.last = 1;
7038 r = r600_bytecode_add_alu(ctx->bc, &alu);
7039 if (r)
7040 return r;
7041 }
7042
7043 } else {
7044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7045
7046 alu.op = ALU_OP1_LOG_IEEE;
7047 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7048 r600_bytecode_src_set_abs(&alu.src[0]);
7049
7050 alu.dst.sel = ctx->temp_reg;
7051 alu.dst.chan = 0;
7052 alu.dst.write = 1;
7053 alu.last = 1;
7054 r = r600_bytecode_add_alu(ctx->bc, &alu);
7055 if (r)
7056 return r;
7057 }
7058
7059 alu.op = ALU_OP1_FLOOR;
7060 alu.src[0].sel = ctx->temp_reg;
7061 alu.src[0].chan = 0;
7062
7063 alu.dst.sel = ctx->temp_reg;
7064 alu.dst.chan = 0;
7065 alu.dst.write = 1;
7066 alu.last = 1;
7067
7068 r = r600_bytecode_add_alu(ctx->bc, &alu);
7069 if (r)
7070 return r;
7071 }
7072
7073 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
7074 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
7075
7076 if (ctx->bc->chip_class == CAYMAN) {
7077 for (i = 0; i < 3; i++) {
7078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7079
7080 alu.op = ALU_OP1_LOG_IEEE;
7081 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7082 r600_bytecode_src_set_abs(&alu.src[0]);
7083
7084 alu.dst.sel = ctx->temp_reg;
7085 alu.dst.chan = i;
7086 if (i == 1)
7087 alu.dst.write = 1;
7088 if (i == 2)
7089 alu.last = 1;
7090
7091 r = r600_bytecode_add_alu(ctx->bc, &alu);
7092 if (r)
7093 return r;
7094 }
7095 } else {
7096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7097
7098 alu.op = ALU_OP1_LOG_IEEE;
7099 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7100 r600_bytecode_src_set_abs(&alu.src[0]);
7101
7102 alu.dst.sel = ctx->temp_reg;
7103 alu.dst.chan = 1;
7104 alu.dst.write = 1;
7105 alu.last = 1;
7106
7107 r = r600_bytecode_add_alu(ctx->bc, &alu);
7108 if (r)
7109 return r;
7110 }
7111
7112 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7113
7114 alu.op = ALU_OP1_FLOOR;
7115 alu.src[0].sel = ctx->temp_reg;
7116 alu.src[0].chan = 1;
7117
7118 alu.dst.sel = ctx->temp_reg;
7119 alu.dst.chan = 1;
7120 alu.dst.write = 1;
7121 alu.last = 1;
7122
7123 r = r600_bytecode_add_alu(ctx->bc, &alu);
7124 if (r)
7125 return r;
7126
7127 if (ctx->bc->chip_class == CAYMAN) {
7128 for (i = 0; i < 3; i++) {
7129 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7130 alu.op = ALU_OP1_EXP_IEEE;
7131 alu.src[0].sel = ctx->temp_reg;
7132 alu.src[0].chan = 1;
7133
7134 alu.dst.sel = ctx->temp_reg;
7135 alu.dst.chan = i;
7136 if (i == 1)
7137 alu.dst.write = 1;
7138 if (i == 2)
7139 alu.last = 1;
7140
7141 r = r600_bytecode_add_alu(ctx->bc, &alu);
7142 if (r)
7143 return r;
7144 }
7145 } else {
7146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7147 alu.op = ALU_OP1_EXP_IEEE;
7148 alu.src[0].sel = ctx->temp_reg;
7149 alu.src[0].chan = 1;
7150
7151 alu.dst.sel = ctx->temp_reg;
7152 alu.dst.chan = 1;
7153 alu.dst.write = 1;
7154 alu.last = 1;
7155
7156 r = r600_bytecode_add_alu(ctx->bc, &alu);
7157 if (r)
7158 return r;
7159 }
7160
7161 if (ctx->bc->chip_class == CAYMAN) {
7162 for (i = 0; i < 3; i++) {
7163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7164 alu.op = ALU_OP1_RECIP_IEEE;
7165 alu.src[0].sel = ctx->temp_reg;
7166 alu.src[0].chan = 1;
7167
7168 alu.dst.sel = ctx->temp_reg;
7169 alu.dst.chan = i;
7170 if (i == 1)
7171 alu.dst.write = 1;
7172 if (i == 2)
7173 alu.last = 1;
7174
7175 r = r600_bytecode_add_alu(ctx->bc, &alu);
7176 if (r)
7177 return r;
7178 }
7179 } else {
7180 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7181 alu.op = ALU_OP1_RECIP_IEEE;
7182 alu.src[0].sel = ctx->temp_reg;
7183 alu.src[0].chan = 1;
7184
7185 alu.dst.sel = ctx->temp_reg;
7186 alu.dst.chan = 1;
7187 alu.dst.write = 1;
7188 alu.last = 1;
7189
7190 r = r600_bytecode_add_alu(ctx->bc, &alu);
7191 if (r)
7192 return r;
7193 }
7194
7195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7196
7197 alu.op = ALU_OP2_MUL;
7198
7199 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7200 r600_bytecode_src_set_abs(&alu.src[0]);
7201
7202 alu.src[1].sel = ctx->temp_reg;
7203 alu.src[1].chan = 1;
7204
7205 alu.dst.sel = ctx->temp_reg;
7206 alu.dst.chan = 1;
7207 alu.dst.write = 1;
7208 alu.last = 1;
7209
7210 r = r600_bytecode_add_alu(ctx->bc, &alu);
7211 if (r)
7212 return r;
7213 }
7214
7215 /* result.z = log2(|src|);*/
7216 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
7217 if (ctx->bc->chip_class == CAYMAN) {
7218 for (i = 0; i < 3; i++) {
7219 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7220
7221 alu.op = ALU_OP1_LOG_IEEE;
7222 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7223 r600_bytecode_src_set_abs(&alu.src[0]);
7224
7225 alu.dst.sel = ctx->temp_reg;
7226 if (i == 2)
7227 alu.dst.write = 1;
7228 alu.dst.chan = i;
7229 if (i == 2)
7230 alu.last = 1;
7231
7232 r = r600_bytecode_add_alu(ctx->bc, &alu);
7233 if (r)
7234 return r;
7235 }
7236 } else {
7237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7238
7239 alu.op = ALU_OP1_LOG_IEEE;
7240 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7241 r600_bytecode_src_set_abs(&alu.src[0]);
7242
7243 alu.dst.sel = ctx->temp_reg;
7244 alu.dst.write = 1;
7245 alu.dst.chan = 2;
7246 alu.last = 1;
7247
7248 r = r600_bytecode_add_alu(ctx->bc, &alu);
7249 if (r)
7250 return r;
7251 }
7252 }
7253
7254 /* result.w = 1.0; */
7255 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
7256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7257
7258 alu.op = ALU_OP1_MOV;
7259 alu.src[0].sel = V_SQ_ALU_SRC_1;
7260 alu.src[0].chan = 0;
7261
7262 alu.dst.sel = ctx->temp_reg;
7263 alu.dst.chan = 3;
7264 alu.dst.write = 1;
7265 alu.last = 1;
7266
7267 r = r600_bytecode_add_alu(ctx->bc, &alu);
7268 if (r)
7269 return r;
7270 }
7271
7272 return tgsi_helper_copy(ctx, inst);
7273 }
7274
7275 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
7276 {
7277 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7278 struct r600_bytecode_alu alu;
7279 int r;
7280 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7281 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
7282
7283 assert(inst->Dst[0].Register.Index < 3);
7284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7285
7286 switch (inst->Instruction.Opcode) {
7287 case TGSI_OPCODE_ARL:
7288 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
7289 break;
7290 case TGSI_OPCODE_ARR:
7291 alu.op = ALU_OP1_FLT_TO_INT;
7292 break;
7293 case TGSI_OPCODE_UARL:
7294 alu.op = ALU_OP1_MOV;
7295 break;
7296 default:
7297 assert(0);
7298 return -1;
7299 }
7300
7301 for (i = 0; i <= lasti; ++i) {
7302 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7303 continue;
7304 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7305 alu.last = i == lasti;
7306 alu.dst.sel = reg;
7307 alu.dst.chan = i;
7308 alu.dst.write = 1;
7309 r = r600_bytecode_add_alu(ctx->bc, &alu);
7310 if (r)
7311 return r;
7312 }
7313
7314 if (inst->Dst[0].Register.Index > 0)
7315 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
7316 else
7317 ctx->bc->ar_loaded = 0;
7318
7319 return 0;
7320 }
7321 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
7322 {
7323 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7324 struct r600_bytecode_alu alu;
7325 int r;
7326 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7327
7328 switch (inst->Instruction.Opcode) {
7329 case TGSI_OPCODE_ARL:
7330 memset(&alu, 0, sizeof(alu));
7331 alu.op = ALU_OP1_FLOOR;
7332 alu.dst.sel = ctx->bc->ar_reg;
7333 alu.dst.write = 1;
7334 for (i = 0; i <= lasti; ++i) {
7335 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7336 alu.dst.chan = i;
7337 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7338 alu.last = i == lasti;
7339 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7340 return r;
7341 }
7342 }
7343
7344 memset(&alu, 0, sizeof(alu));
7345 alu.op = ALU_OP1_FLT_TO_INT;
7346 alu.src[0].sel = ctx->bc->ar_reg;
7347 alu.dst.sel = ctx->bc->ar_reg;
7348 alu.dst.write = 1;
7349 /* FLT_TO_INT is trans-only on r600/r700 */
7350 alu.last = TRUE;
7351 for (i = 0; i <= lasti; ++i) {
7352 alu.dst.chan = i;
7353 alu.src[0].chan = i;
7354 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7355 return r;
7356 }
7357 break;
7358 case TGSI_OPCODE_ARR:
7359 memset(&alu, 0, sizeof(alu));
7360 alu.op = ALU_OP1_FLT_TO_INT;
7361 alu.dst.sel = ctx->bc->ar_reg;
7362 alu.dst.write = 1;
7363 /* FLT_TO_INT is trans-only on r600/r700 */
7364 alu.last = TRUE;
7365 for (i = 0; i <= lasti; ++i) {
7366 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7367 alu.dst.chan = i;
7368 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7369 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7370 return r;
7371 }
7372 }
7373 break;
7374 case TGSI_OPCODE_UARL:
7375 memset(&alu, 0, sizeof(alu));
7376 alu.op = ALU_OP1_MOV;
7377 alu.dst.sel = ctx->bc->ar_reg;
7378 alu.dst.write = 1;
7379 for (i = 0; i <= lasti; ++i) {
7380 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
7381 alu.dst.chan = i;
7382 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7383 alu.last = i == lasti;
7384 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
7385 return r;
7386 }
7387 }
7388 break;
7389 default:
7390 assert(0);
7391 return -1;
7392 }
7393
7394 ctx->bc->ar_loaded = 0;
7395 return 0;
7396 }
7397
7398 static int tgsi_opdst(struct r600_shader_ctx *ctx)
7399 {
7400 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7401 struct r600_bytecode_alu alu;
7402 int i, r = 0;
7403
7404 for (i = 0; i < 4; i++) {
7405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7406
7407 alu.op = ALU_OP2_MUL;
7408 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7409
7410 if (i == 0 || i == 3) {
7411 alu.src[0].sel = V_SQ_ALU_SRC_1;
7412 } else {
7413 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7414 }
7415
7416 if (i == 0 || i == 2) {
7417 alu.src[1].sel = V_SQ_ALU_SRC_1;
7418 } else {
7419 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
7420 }
7421 if (i == 3)
7422 alu.last = 1;
7423 r = r600_bytecode_add_alu(ctx->bc, &alu);
7424 if (r)
7425 return r;
7426 }
7427 return 0;
7428 }
7429
7430 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
7431 {
7432 struct r600_bytecode_alu alu;
7433 int r;
7434
7435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7436 alu.op = opcode;
7437 alu.execute_mask = 1;
7438 alu.update_pred = 1;
7439
7440 alu.dst.sel = ctx->temp_reg;
7441 alu.dst.write = 1;
7442 alu.dst.chan = 0;
7443
7444 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
7445 alu.src[1].sel = V_SQ_ALU_SRC_0;
7446 alu.src[1].chan = 0;
7447
7448 alu.last = 1;
7449
7450 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
7451 if (r)
7452 return r;
7453 return 0;
7454 }
7455
7456 static int pops(struct r600_shader_ctx *ctx, int pops)
7457 {
7458 unsigned force_pop = ctx->bc->force_add_cf;
7459
7460 if (!force_pop) {
7461 int alu_pop = 3;
7462 if (ctx->bc->cf_last) {
7463 if (ctx->bc->cf_last->op == CF_OP_ALU)
7464 alu_pop = 0;
7465 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
7466 alu_pop = 1;
7467 }
7468 alu_pop += pops;
7469 if (alu_pop == 1) {
7470 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
7471 ctx->bc->force_add_cf = 1;
7472 } else if (alu_pop == 2) {
7473 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
7474 ctx->bc->force_add_cf = 1;
7475 } else {
7476 force_pop = 1;
7477 }
7478 }
7479
7480 if (force_pop) {
7481 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
7482 ctx->bc->cf_last->pop_count = pops;
7483 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7484 }
7485
7486 return 0;
7487 }
7488
7489 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
7490 unsigned reason)
7491 {
7492 struct r600_stack_info *stack = &ctx->bc->stack;
7493 unsigned elements, entries;
7494
7495 unsigned entry_size = stack->entry_size;
7496
7497 elements = (stack->loop + stack->push_wqm ) * entry_size;
7498 elements += stack->push;
7499
7500 switch (ctx->bc->chip_class) {
7501 case R600:
7502 case R700:
7503 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
7504 * the stack must be reserved to hold the current active/continue
7505 * masks */
7506 if (reason == FC_PUSH_VPM) {
7507 elements += 2;
7508 }
7509 break;
7510
7511 case CAYMAN:
7512 /* r9xx: any stack operation on empty stack consumes 2 additional
7513 * elements */
7514 elements += 2;
7515
7516 /* fallthrough */
7517 /* FIXME: do the two elements added above cover the cases for the
7518 * r8xx+ below? */
7519
7520 case EVERGREEN:
7521 /* r8xx+: 2 extra elements are not always required, but one extra
7522 * element must be added for each of the following cases:
7523 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
7524 * stack usage.
7525 * (Currently we don't use ALU_ELSE_AFTER.)
7526 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
7527 * PUSH instruction executed.
7528 *
7529 * NOTE: it seems we also need to reserve additional element in some
7530 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
7531 * then STACK_SIZE should be 2 instead of 1 */
7532 if (reason == FC_PUSH_VPM) {
7533 elements += 1;
7534 }
7535 break;
7536
7537 default:
7538 assert(0);
7539 break;
7540 }
7541
7542 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
7543 * for all chips, so we use 4 in the final formula, not the real entry_size
7544 * for the chip */
7545 entry_size = 4;
7546
7547 entries = (elements + (entry_size - 1)) / entry_size;
7548
7549 if (entries > stack->max_entries)
7550 stack->max_entries = entries;
7551 }
7552
7553 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
7554 {
7555 switch(reason) {
7556 case FC_PUSH_VPM:
7557 --ctx->bc->stack.push;
7558 assert(ctx->bc->stack.push >= 0);
7559 break;
7560 case FC_PUSH_WQM:
7561 --ctx->bc->stack.push_wqm;
7562 assert(ctx->bc->stack.push_wqm >= 0);
7563 break;
7564 case FC_LOOP:
7565 --ctx->bc->stack.loop;
7566 assert(ctx->bc->stack.loop >= 0);
7567 break;
7568 default:
7569 assert(0);
7570 break;
7571 }
7572 }
7573
7574 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
7575 {
7576 switch (reason) {
7577 case FC_PUSH_VPM:
7578 ++ctx->bc->stack.push;
7579 break;
7580 case FC_PUSH_WQM:
7581 ++ctx->bc->stack.push_wqm;
7582 case FC_LOOP:
7583 ++ctx->bc->stack.loop;
7584 break;
7585 default:
7586 assert(0);
7587 }
7588
7589 callstack_update_max_depth(ctx, reason);
7590 }
7591
7592 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
7593 {
7594 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
7595
7596 sp->mid = realloc((void *)sp->mid,
7597 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
7598 sp->mid[sp->num_mid] = ctx->bc->cf_last;
7599 sp->num_mid++;
7600 }
7601
7602 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
7603 {
7604 ctx->bc->fc_sp++;
7605 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
7606 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
7607 }
7608
7609 static void fc_poplevel(struct r600_shader_ctx *ctx)
7610 {
7611 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
7612 free(sp->mid);
7613 sp->mid = NULL;
7614 sp->num_mid = 0;
7615 sp->start = NULL;
7616 sp->type = 0;
7617 ctx->bc->fc_sp--;
7618 }
7619
7620 #if 0
7621 static int emit_return(struct r600_shader_ctx *ctx)
7622 {
7623 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
7624 return 0;
7625 }
7626
7627 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
7628 {
7629
7630 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
7631 ctx->bc->cf_last->pop_count = pops;
7632 /* XXX work out offset */
7633 return 0;
7634 }
7635
7636 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
7637 {
7638 return 0;
7639 }
7640
7641 static void emit_testflag(struct r600_shader_ctx *ctx)
7642 {
7643
7644 }
7645
7646 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
7647 {
7648 emit_testflag(ctx);
7649 emit_jump_to_offset(ctx, 1, 4);
7650 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
7651 pops(ctx, ifidx + 1);
7652 emit_return(ctx);
7653 }
7654
7655 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
7656 {
7657 emit_testflag(ctx);
7658
7659 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7660 ctx->bc->cf_last->pop_count = 1;
7661
7662 fc_set_mid(ctx, fc_sp);
7663
7664 pops(ctx, 1);
7665 }
7666 #endif
7667
7668 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
7669 {
7670 int alu_type = CF_OP_ALU_PUSH_BEFORE;
7671
7672 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
7673 * LOOP_STARTxxx for nested loops may put the branch stack into a state
7674 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
7675 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
7676 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
7677 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
7678 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
7679 alu_type = CF_OP_ALU;
7680 }
7681
7682 emit_logic_pred(ctx, opcode, alu_type);
7683
7684 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
7685
7686 fc_pushlevel(ctx, FC_IF);
7687
7688 callstack_push(ctx, FC_PUSH_VPM);
7689 return 0;
7690 }
7691
7692 static int tgsi_if(struct r600_shader_ctx *ctx)
7693 {
7694 return emit_if(ctx, ALU_OP2_PRED_SETNE);
7695 }
7696
7697 static int tgsi_uif(struct r600_shader_ctx *ctx)
7698 {
7699 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
7700 }
7701
7702 static int tgsi_else(struct r600_shader_ctx *ctx)
7703 {
7704 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
7705 ctx->bc->cf_last->pop_count = 1;
7706
7707 fc_set_mid(ctx, ctx->bc->fc_sp);
7708 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
7709 return 0;
7710 }
7711
7712 static int tgsi_endif(struct r600_shader_ctx *ctx)
7713 {
7714 pops(ctx, 1);
7715 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
7716 R600_ERR("if/endif unbalanced in shader\n");
7717 return -1;
7718 }
7719
7720 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
7721 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7722 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
7723 } else {
7724 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
7725 }
7726 fc_poplevel(ctx);
7727
7728 callstack_pop(ctx, FC_PUSH_VPM);
7729 return 0;
7730 }
7731
7732 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
7733 {
7734 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
7735 * limited to 4096 iterations, like the other LOOP_* instructions. */
7736 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
7737
7738 fc_pushlevel(ctx, FC_LOOP);
7739
7740 /* check stack depth */
7741 callstack_push(ctx, FC_LOOP);
7742 return 0;
7743 }
7744
7745 static int tgsi_endloop(struct r600_shader_ctx *ctx)
7746 {
7747 int i;
7748
7749 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
7750
7751 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
7752 R600_ERR("loop/endloop in shader code are not paired.\n");
7753 return -EINVAL;
7754 }
7755
7756 /* fixup loop pointers - from r600isa
7757 LOOP END points to CF after LOOP START,
7758 LOOP START point to CF after LOOP END
7759 BRK/CONT point to LOOP END CF
7760 */
7761 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
7762
7763 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
7764
7765 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
7766 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
7767 }
7768 /* XXX add LOOPRET support */
7769 fc_poplevel(ctx);
7770 callstack_pop(ctx, FC_LOOP);
7771 return 0;
7772 }
7773
7774 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
7775 {
7776 int r;
7777 unsigned int fscp;
7778
7779 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7780 {
7781 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7782 break;
7783 }
7784 if (fscp == 0) {
7785 R600_ERR("BREAKC not inside loop/endloop pair\n");
7786 return -EINVAL;
7787 }
7788
7789 if (ctx->bc->chip_class == EVERGREEN &&
7790 ctx->bc->family != CHIP_CYPRESS &&
7791 ctx->bc->family != CHIP_JUNIPER) {
7792 /* HW bug: ALU_BREAK does not save the active mask correctly */
7793 r = tgsi_uif(ctx);
7794 if (r)
7795 return r;
7796
7797 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
7798 if (r)
7799 return r;
7800 fc_set_mid(ctx, fscp);
7801
7802 return tgsi_endif(ctx);
7803 } else {
7804 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
7805 if (r)
7806 return r;
7807 fc_set_mid(ctx, fscp);
7808 }
7809
7810 return 0;
7811 }
7812
7813 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
7814 {
7815 unsigned int fscp;
7816
7817 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
7818 {
7819 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
7820 break;
7821 }
7822
7823 if (fscp == 0) {
7824 R600_ERR("Break not inside loop/endloop pair\n");
7825 return -EINVAL;
7826 }
7827
7828 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7829
7830 fc_set_mid(ctx, fscp);
7831
7832 return 0;
7833 }
7834
7835 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
7836 {
7837 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7838 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
7839 int r;
7840
7841 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
7842 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
7843
7844 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
7845 if (!r) {
7846 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
7847 return emit_inc_ring_offset(ctx, stream, TRUE);
7848 }
7849 return r;
7850 }
7851
7852 static int tgsi_umad(struct r600_shader_ctx *ctx)
7853 {
7854 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7855 struct r600_bytecode_alu alu;
7856 int i, j, k, r;
7857 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7858
7859 /* src0 * src1 */
7860 for (i = 0; i < lasti + 1; i++) {
7861 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7862 continue;
7863
7864 if (ctx->bc->chip_class == CAYMAN) {
7865 for (j = 0 ; j < 4; j++) {
7866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7867
7868 alu.op = ALU_OP2_MULLO_UINT;
7869 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
7870 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
7871 }
7872 alu.dst.chan = j;
7873 alu.dst.sel = ctx->temp_reg;
7874 alu.dst.write = (j == i);
7875 if (j == 3)
7876 alu.last = 1;
7877 r = r600_bytecode_add_alu(ctx->bc, &alu);
7878 if (r)
7879 return r;
7880 }
7881 } else {
7882 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7883
7884 alu.dst.chan = i;
7885 alu.dst.sel = ctx->temp_reg;
7886 alu.dst.write = 1;
7887
7888 alu.op = ALU_OP2_MULLO_UINT;
7889 for (j = 0; j < 2; j++) {
7890 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
7891 }
7892
7893 alu.last = 1;
7894 r = r600_bytecode_add_alu(ctx->bc, &alu);
7895 if (r)
7896 return r;
7897 }
7898 }
7899
7900
7901 for (i = 0; i < lasti + 1; i++) {
7902 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7903 continue;
7904
7905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7906 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7907
7908 alu.op = ALU_OP2_ADD_INT;
7909
7910 alu.src[0].sel = ctx->temp_reg;
7911 alu.src[0].chan = i;
7912
7913 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
7914 if (i == lasti) {
7915 alu.last = 1;
7916 }
7917 r = r600_bytecode_add_alu(ctx->bc, &alu);
7918 if (r)
7919 return r;
7920 }
7921 return 0;
7922 }
7923
7924 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
7925 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
7926 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
7927 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
7928
7929 /* XXX:
7930 * For state trackers other than OpenGL, we'll want to use
7931 * _RECIP_IEEE instead.
7932 */
7933 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
7934
7935 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
7936 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
7937 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
7938 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
7939 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
7940 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
7941 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
7942 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
7943 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
7944 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
7945 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
7946 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
7947 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
7948 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
7949 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
7950 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
7951 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
7952 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
7953 [22] = { ALU_OP0_NOP, tgsi_unsupported},
7954 [23] = { ALU_OP0_NOP, tgsi_unsupported},
7955 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
7956 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
7957 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
7958 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
7959 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
7960 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
7961 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
7962 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
7963 [32] = { ALU_OP0_NOP, tgsi_unsupported},
7964 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
7965 [34] = { ALU_OP0_NOP, tgsi_unsupported},
7966 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
7967 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
7968 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
7969 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
7970 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
7971 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
7972 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
7973 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
7974 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7975 [44] = { ALU_OP0_NOP, tgsi_unsupported},
7976 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
7977 [46] = { ALU_OP0_NOP, tgsi_unsupported},
7978 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
7979 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
7980 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
7981 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
7982 [51] = { ALU_OP0_NOP, tgsi_unsupported},
7983 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
7984 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
7985 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
7986 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
7987 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
7988 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
7989 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
7990 [59] = { ALU_OP0_NOP, tgsi_unsupported},
7991 [60] = { ALU_OP0_NOP, tgsi_unsupported},
7992 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
7993 [62] = { ALU_OP0_NOP, tgsi_unsupported},
7994 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
7995 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
7996 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
7997 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
7998 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
7999 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8000 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8001 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8002 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8003 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8004 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8005 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8006 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8007 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8008 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8009 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8010 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
8011 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
8012 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8013 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8014 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8015 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
8016 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8017 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8018 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
8019 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8020 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8021 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8022 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8023 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8024 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8025 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8026 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8027 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8028 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8029 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8030 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8031 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8032 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8033 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8034 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8035 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8036 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8037 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8038 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8039 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8040 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8041 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8042 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8043 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8044 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8045 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8046 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_loop_breakc},
8047 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8048 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8049 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8050 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
8051 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8052 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8053 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8054 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8055 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8056 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
8057 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8058 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
8059 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
8060 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8061 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8062 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8063 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8064 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8065 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8066 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
8067 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8068 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8069 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
8070 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8071 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
8072 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8073 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8074 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8075 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8076 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8077 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8078 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8079 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8080 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8081 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8082 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8083 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8084 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8085 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8086 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8087 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8088 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
8089 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8090 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8091 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8092 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8093 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8094 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8095 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8096 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8097 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8098 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8099 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8100 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8101 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8102 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8103 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8104 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8105 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8106 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8107 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8108 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8109 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8110 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8111 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8112 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8113 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
8114 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
8115 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
8116 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
8117 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
8118 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
8119 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
8120 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
8121 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
8122 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
8123 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
8124 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
8125 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
8126 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8127 };
8128
8129 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
8130 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8131 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8132 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8133 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
8134 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
8135 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8136 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8137 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8138 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8139 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8140 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8141 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8142 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8143 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8144 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8145 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8146 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8147 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8148 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8149 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8150 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
8151 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8152 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8153 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8154 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8155 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8156 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8157 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8158 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
8159 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
8160 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
8161 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8162 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8163 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8164 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8165 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8166 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
8167 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8168 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8169 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8170 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8171 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8172 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8173 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8174 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8175 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8176 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8177 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8178 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
8179 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8180 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8181 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8182 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8183 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8184 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8185 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8186 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8187 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8188 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8189 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8190 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8191 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8192 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8193 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8194 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8195 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8196 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8197 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8198 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8199 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8200 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8201 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8202 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8203 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8204 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8205 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8206 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8207 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8208 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8209 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8210 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8211 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8212 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8213 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8214 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
8215 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8216 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8217 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8218 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8219 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8220 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8221 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8222 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8223 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8224 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8225 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8226 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8227 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8228 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8229 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8230 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8231 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8232 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8233 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8234 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8235 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8236 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8237 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8238 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8239 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8240 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8241 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8242 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8243 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8244 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8245 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8246 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8247 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8248 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8249 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
8250 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8251 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8252 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8253 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8254 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8255 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8256 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8257 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
8258 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
8259 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8260 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8261 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8262 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8263 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8264 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8265 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
8266 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8267 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8268 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8269 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8270 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8271 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8272 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8273 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8274 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8275 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8276 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8277 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8278 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8279 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8280 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8281 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8282 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8283 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8284 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8285 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8286 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8287 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8288 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8289 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8290 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8291 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8292 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8293 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8294 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8295 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8296 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8297 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8298 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8299 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8300 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8301 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8302 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8303 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8304 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8305 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8306 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8307 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8308 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8309 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8310 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
8311 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
8312 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8313 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8314 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8315 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8316 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8317 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8318 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8319 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8320 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8321 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8322 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8323 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8324 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8325 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8326 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8327 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8328 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8329 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8330 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8331 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8332 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8333 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8334 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8335 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8336 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8337 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8338 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8339 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8340 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8341 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8342 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8343 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8344 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8345 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8346 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8347 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8348 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8349 };
8350
8351 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
8352 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
8353 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
8354 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
8355 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
8356 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
8357 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
8358 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
8359 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL, tgsi_op2},
8360 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
8361 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4, tgsi_dp},
8362 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4, tgsi_dp},
8363 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
8364 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN, tgsi_op2},
8365 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX, tgsi_op2},
8366 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
8367 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
8368 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD, tgsi_op3},
8369 [TGSI_OPCODE_SUB] = { ALU_OP2_ADD, tgsi_op2},
8370 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
8371 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
8372 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
8373 [TGSI_OPCODE_DP2A] = { ALU_OP0_NOP, tgsi_unsupported},
8374 [22] = { ALU_OP0_NOP, tgsi_unsupported},
8375 [23] = { ALU_OP0_NOP, tgsi_unsupported},
8376 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
8377 [TGSI_OPCODE_CLAMP] = { ALU_OP0_NOP, tgsi_unsupported},
8378 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
8379 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
8380 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
8381 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
8382 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
8383 [TGSI_OPCODE_XPD] = { ALU_OP0_NOP, tgsi_xpd},
8384 [32] = { ALU_OP0_NOP, tgsi_unsupported},
8385 [TGSI_OPCODE_ABS] = { ALU_OP1_MOV, tgsi_op2},
8386 [34] = { ALU_OP0_NOP, tgsi_unsupported},
8387 [TGSI_OPCODE_DPH] = { ALU_OP2_DOT4, tgsi_dp},
8388 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
8389 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8390 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8391 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
8392 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
8393 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
8394 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
8395 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8396 [44] = { ALU_OP0_NOP, tgsi_unsupported},
8397 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
8398 [46] = { ALU_OP0_NOP, tgsi_unsupported},
8399 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
8400 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
8401 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
8402 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
8403 [51] = { ALU_OP0_NOP, tgsi_unsupported},
8404 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
8405 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
8406 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
8407 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
8408 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
8409 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
8410 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
8411 [59] = { ALU_OP0_NOP, tgsi_unsupported},
8412 [60] = { ALU_OP0_NOP, tgsi_unsupported},
8413 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
8414 [62] = { ALU_OP0_NOP, tgsi_unsupported},
8415 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
8416 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
8417 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
8418 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
8419 [TGSI_OPCODE_SCS] = { ALU_OP0_NOP, tgsi_scs},
8420 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8421 [69] = { ALU_OP0_NOP, tgsi_unsupported},
8422 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
8423 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4, tgsi_dp},
8424 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8425 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
8426 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
8427 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
8428 [76] = { ALU_OP0_NOP, tgsi_unsupported},
8429 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
8430 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
8431 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
8432 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
8433 [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported},
8434 [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported},
8435 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
8436 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
8437 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
8438 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
8439 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
8440 [88] = { ALU_OP0_NOP, tgsi_unsupported},
8441 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
8442 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
8443 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
8444 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
8445 [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported},
8446 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
8447 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8448 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
8449 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
8450 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
8451 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
8452 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8453 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
8454 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
8455 [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
8456 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
8457 [105] = { ALU_OP0_NOP, tgsi_unsupported},
8458 [106] = { ALU_OP0_NOP, tgsi_unsupported},
8459 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
8460 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
8461 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
8462 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
8463 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
8464 [112] = { ALU_OP0_NOP, tgsi_unsupported},
8465 [TGSI_OPCODE_CALLNZ] = { ALU_OP0_NOP, tgsi_unsupported},
8466 [114] = { ALU_OP0_NOP, tgsi_unsupported},
8467 [TGSI_OPCODE_BREAKC] = { ALU_OP0_NOP, tgsi_unsupported},
8468 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
8469 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
8470 [118] = { ALU_OP0_NOP, tgsi_unsupported},
8471 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
8472 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
8473 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
8474 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
8475 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
8476 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
8477 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
8478 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
8479 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
8480 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
8481 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
8482 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
8483 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
8484 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
8485 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
8486 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
8487 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
8488 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
8489 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
8490 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
8491 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
8492 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
8493 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8494 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
8495 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
8496 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
8497 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
8498 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
8499 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
8500 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
8501 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
8502 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
8503 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
8504 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
8505 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
8506 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
8507 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
8508 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
8509 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
8510 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
8511 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
8512 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
8513 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
8514 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
8515 [TGSI_OPCODE_MFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8516 [TGSI_OPCODE_LFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8517 [TGSI_OPCODE_SFENCE] = { ALU_OP0_NOP, tgsi_unsupported},
8518 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
8519 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
8520 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
8521 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
8522 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
8523 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
8524 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
8525 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8526 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8527 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
8528 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
8529 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
8530 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
8531 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
8532 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
8533 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
8534 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
8535 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
8536 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_op3},
8537 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_op3},
8538 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
8539 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
8540 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
8541 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
8542 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
8543 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
8544 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
8545 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
8546 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
8547 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
8548 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
8549 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
8550 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
8551 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
8552 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
8553 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
8554 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
8555 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
8556 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
8557 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
8558 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
8559 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
8560 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
8561 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
8562 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
8563 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
8564 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
8565 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
8566 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
8567 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
8568 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
8569 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
8570 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
8571 };