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r600g/compute: Move LOOP_CONST initialization to start_compute_cs atom
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600d.h"
28
29 #include "pipe/p_shader_tokens.h"
30 #include "tgsi/tgsi_info.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_scan.h"
33 #include "tgsi/tgsi_dump.h"
34 #include "util/u_memory.h"
35 #include <stdio.h>
36 #include <errno.h>
37 #include <byteswap.h>
38
39 /* CAYMAN notes
40 Why CAYMAN got loops for lots of instructions is explained here.
41
42 -These 8xx t-slot only ops are implemented in all vector slots.
43 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
44 These 8xx t-slot only opcodes become vector ops, with all four
45 slots expecting the arguments on sources a and b. Result is
46 broadcast to all channels.
47 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
48 These 8xx t-slot only opcodes become vector ops in the z, y, and
49 x slots.
50 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
51 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
52 SQRT_IEEE/_64
53 SIN/COS
54 The w slot may have an independent co-issued operation, or if the
55 result is required to be in the w slot, the opcode above may be
56 issued in the w slot as well.
57 The compiler must issue the source argument to slots z, y, and x
58 */
59
60 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
61 {
62 struct r600_context *rctx = (struct r600_context *)ctx;
63 struct r600_shader *rshader = &shader->shader;
64 uint32_t *ptr;
65 int i;
66
67 /* copy new shader */
68 if (shader->bo == NULL) {
69 shader->bo = (struct r600_resource*)
70 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, rshader->bc.ndw * 4);
71 if (shader->bo == NULL) {
72 return -ENOMEM;
73 }
74 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
75 if (R600_BIG_ENDIAN) {
76 for (i = 0; i < rshader->bc.ndw; ++i) {
77 ptr[i] = bswap_32(rshader->bc.bytecode[i]);
78 }
79 } else {
80 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * sizeof(*ptr));
81 }
82 rctx->ws->buffer_unmap(shader->bo->cs_buf);
83 }
84 /* build state */
85 switch (rshader->processor_type) {
86 case TGSI_PROCESSOR_VERTEX:
87 if (rctx->chip_class >= EVERGREEN) {
88 evergreen_pipe_shader_vs(ctx, shader);
89 } else {
90 r600_pipe_shader_vs(ctx, shader);
91 }
92 break;
93 case TGSI_PROCESSOR_FRAGMENT:
94 if (rctx->chip_class >= EVERGREEN) {
95 evergreen_pipe_shader_ps(ctx, shader);
96 } else {
97 r600_pipe_shader_ps(ctx, shader);
98 }
99 break;
100 default:
101 return -EINVAL;
102 }
103 return 0;
104 }
105
106 static int r600_shader_from_tgsi(struct r600_context * rctx, struct r600_pipe_shader *pipeshader);
107
108 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader)
109 {
110 static int dump_shaders = -1;
111 struct r600_context *rctx = (struct r600_context *)ctx;
112 struct r600_pipe_shader_selector *sel = shader->selector;
113 int r;
114
115 /* Would like some magic "get_bool_option_once" routine.
116 */
117 if (dump_shaders == -1)
118 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
119
120 if (dump_shaders) {
121 fprintf(stderr, "--------------------------------------------------------------\n");
122 tgsi_dump(sel->tokens, 0);
123
124 if (sel->so.num_outputs) {
125 unsigned i;
126 fprintf(stderr, "STREAMOUT\n");
127 for (i = 0; i < sel->so.num_outputs; i++) {
128 unsigned mask = ((1 << sel->so.output[i].num_components) - 1) <<
129 sel->so.output[i].start_component;
130 fprintf(stderr, " %i: MEM_STREAM0_BUF%i OUT[%i].%s%s%s%s\n", i,
131 sel->so.output[i].output_buffer, sel->so.output[i].register_index,
132 mask & 1 ? "x" : "_",
133 (mask >> 1) & 1 ? "y" : "_",
134 (mask >> 2) & 1 ? "z" : "_",
135 (mask >> 3) & 1 ? "w" : "_");
136 }
137 }
138 }
139 r = r600_shader_from_tgsi(rctx, shader);
140 if (r) {
141 R600_ERR("translation from TGSI failed !\n");
142 return r;
143 }
144 r = r600_bytecode_build(&shader->shader.bc);
145 if (r) {
146 R600_ERR("building bytecode failed !\n");
147 return r;
148 }
149 if (dump_shaders) {
150 r600_bytecode_dump(&shader->shader.bc);
151 fprintf(stderr, "______________________________________________________________\n");
152 }
153 return r600_pipe_shader(ctx, shader);
154 }
155
156 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
157 {
158 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
159 r600_bytecode_clear(&shader->shader.bc);
160 }
161
162 /*
163 * tgsi -> r600 shader
164 */
165 struct r600_shader_tgsi_instruction;
166
167 struct r600_shader_src {
168 unsigned sel;
169 unsigned swizzle[4];
170 unsigned neg;
171 unsigned abs;
172 unsigned rel;
173 uint32_t value[4];
174 };
175
176 struct r600_shader_ctx {
177 struct tgsi_shader_info info;
178 struct tgsi_parse_context parse;
179 const struct tgsi_token *tokens;
180 unsigned type;
181 unsigned file_offset[TGSI_FILE_COUNT];
182 unsigned temp_reg;
183 struct r600_shader_tgsi_instruction *inst_info;
184 struct r600_bytecode *bc;
185 struct r600_shader *shader;
186 struct r600_shader_src src[4];
187 uint32_t *literals;
188 uint32_t nliterals;
189 uint32_t max_driver_temp_used;
190 /* needed for evergreen interpolation */
191 boolean input_centroid;
192 boolean input_linear;
193 boolean input_perspective;
194 int num_interp_gpr;
195 int face_gpr;
196 int colors_used;
197 boolean clip_vertex_write;
198 unsigned cv_output;
199 int fragcoord_input;
200 int native_integers;
201 };
202
203 struct r600_shader_tgsi_instruction {
204 unsigned tgsi_opcode;
205 unsigned is_op3;
206 unsigned r600_opcode;
207 int (*process)(struct r600_shader_ctx *ctx);
208 };
209
210 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
211 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
212 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only);
213 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
214 static int tgsi_else(struct r600_shader_ctx *ctx);
215 static int tgsi_endif(struct r600_shader_ctx *ctx);
216 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
217 static int tgsi_endloop(struct r600_shader_ctx *ctx);
218 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
219
220 /*
221 * bytestream -> r600 shader
222 *
223 * These functions are used to transform the output of the LLVM backend into
224 * struct r600_bytecode.
225 */
226
227 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
228 unsigned char * bytes, unsigned num_bytes);
229
230 #ifdef HAVE_OPENCL
231 int r600_compute_shader_create(struct pipe_context * ctx,
232 LLVMModuleRef mod, struct r600_bytecode * bytecode)
233 {
234 struct r600_context *r600_ctx = (struct r600_context *)ctx;
235 unsigned char * bytes;
236 unsigned byte_count;
237 struct r600_shader_ctx shader_ctx;
238 unsigned dump = 0;
239
240 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
241 dump = 1;
242 }
243
244 r600_llvm_compile(mod, &bytes, &byte_count, r600_ctx->family , dump);
245 shader_ctx.bc = bytecode;
246 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family);
247 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
248 r600_bytecode_from_byte_stream(&shader_ctx, bytes, byte_count);
249 if (shader_ctx.bc->chip_class == CAYMAN) {
250 cm_bytecode_add_cf_end(shader_ctx.bc);
251 }
252 r600_bytecode_build(shader_ctx.bc);
253 if (dump) {
254 r600_bytecode_dump(shader_ctx.bc);
255 }
256 return 1;
257 }
258
259 #endif /* HAVE_OPENCL */
260
261 static uint32_t i32_from_byte_stream(unsigned char * bytes,
262 unsigned * bytes_read)
263 {
264 unsigned i;
265 uint32_t out = 0;
266 for (i = 0; i < 4; i++) {
267 out |= bytes[(*bytes_read)++] << (8 * i);
268 }
269 return out;
270 }
271
272 static unsigned r600_src_from_byte_stream(unsigned char * bytes,
273 unsigned bytes_read, struct r600_bytecode_alu * alu, unsigned src_idx)
274 {
275 unsigned i;
276 unsigned sel0, sel1;
277 sel0 = bytes[bytes_read++];
278 sel1 = bytes[bytes_read++];
279 alu->src[src_idx].sel = sel0 | (sel1 << 8);
280 alu->src[src_idx].chan = bytes[bytes_read++];
281 alu->src[src_idx].neg = bytes[bytes_read++];
282 alu->src[src_idx].abs = bytes[bytes_read++];
283 alu->src[src_idx].rel = bytes[bytes_read++];
284 alu->src[src_idx].kc_bank = bytes[bytes_read++];
285 for (i = 0; i < 4; i++) {
286 alu->src[src_idx].value |= bytes[bytes_read++] << (i * 8);
287 }
288 return bytes_read;
289 }
290
291 static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
292 unsigned char * bytes, unsigned bytes_read)
293 {
294 unsigned src_idx;
295 unsigned inst0, inst1;
296 struct r600_bytecode_alu alu;
297 memset(&alu, 0, sizeof(alu));
298 for(src_idx = 0; src_idx < 3; src_idx++) {
299 bytes_read = r600_src_from_byte_stream(bytes, bytes_read,
300 &alu, src_idx);
301 }
302
303 alu.dst.sel = bytes[bytes_read++];
304 alu.dst.chan = bytes[bytes_read++];
305 alu.dst.clamp = bytes[bytes_read++];
306 alu.dst.write = bytes[bytes_read++];
307 alu.dst.rel = bytes[bytes_read++];
308 inst0 = bytes[bytes_read++];
309 inst1 = bytes[bytes_read++];
310 alu.inst = inst0 | (inst1 << 8);
311 alu.last = bytes[bytes_read++];
312 alu.is_op3 = bytes[bytes_read++];
313 alu.predicate = bytes[bytes_read++];
314 alu.bank_swizzle = bytes[bytes_read++];
315 alu.bank_swizzle_force = bytes[bytes_read++];
316 alu.omod = bytes[bytes_read++];
317 alu.index_mode = bytes[bytes_read++];
318 r600_bytecode_add_alu(ctx->bc, &alu);
319
320 /* XXX: Handle other KILL instructions */
321 if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT)) {
322 ctx->shader->uses_kill = 1;
323 /* XXX: This should be enforced in the LLVM backend. */
324 ctx->bc->force_add_cf = 1;
325 }
326 return bytes_read;
327 }
328
329 static void llvm_if(struct r600_shader_ctx *ctx, struct r600_bytecode_alu * alu,
330 unsigned pred_inst)
331 {
332 alu->inst = pred_inst;
333 alu->predicate = 1;
334 alu->dst.write = 0;
335 alu->src[1].sel = V_SQ_ALU_SRC_0;
336 alu->src[1].chan = 0;
337 alu->last = 1;
338 r600_bytecode_add_alu_type(ctx->bc, alu,
339 CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
340
341 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
342 fc_pushlevel(ctx, FC_IF);
343 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
344 }
345
346 static void r600_break_from_byte_stream(struct r600_shader_ctx *ctx,
347 struct r600_bytecode_alu *alu, unsigned compare_opcode)
348 {
349 unsigned opcode = TGSI_OPCODE_BRK;
350 if (ctx->bc->chip_class == CAYMAN)
351 ctx->inst_info = &cm_shader_tgsi_instruction[opcode];
352 else if (ctx->bc->chip_class >= EVERGREEN)
353 ctx->inst_info = &eg_shader_tgsi_instruction[opcode];
354 else
355 ctx->inst_info = &r600_shader_tgsi_instruction[opcode];
356 llvm_if(ctx, alu, compare_opcode);
357 tgsi_loop_brk_cont(ctx);
358 tgsi_endif(ctx);
359 }
360
361 static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx *ctx,
362 unsigned char * bytes, unsigned bytes_read)
363 {
364 struct r600_bytecode_alu alu;
365 unsigned inst;
366 memset(&alu, 0, sizeof(alu));
367 bytes_read = r600_src_from_byte_stream(bytes, bytes_read, &alu, 0);
368 inst = bytes[bytes_read++];
369 switch (inst) {
370 case 0:
371 llvm_if(ctx, &alu,
372 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
373 break;
374 case 1:
375 tgsi_else(ctx);
376 break;
377 case 2:
378 tgsi_endif(ctx);
379 break;
380 case 3:
381 tgsi_bgnloop(ctx);
382 break;
383 case 4:
384 tgsi_endloop(ctx);
385 break;
386 case 5:
387 r600_break_from_byte_stream(ctx, &alu,
388 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE));
389 break;
390 case 6:
391 r600_break_from_byte_stream(ctx, &alu,
392 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
393 break;
394 case 7:
395 {
396 unsigned opcode = TGSI_OPCODE_CONT;
397 if (ctx->bc->chip_class == CAYMAN) {
398 ctx->inst_info =
399 &cm_shader_tgsi_instruction[opcode];
400 } else if (ctx->bc->chip_class >= EVERGREEN) {
401 ctx->inst_info =
402 &eg_shader_tgsi_instruction[opcode];
403 } else {
404 ctx->inst_info =
405 &r600_shader_tgsi_instruction[opcode];
406 }
407 tgsi_loop_brk_cont(ctx);
408 }
409 break;
410 case 8:
411 r600_break_from_byte_stream(ctx, &alu,
412 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT));
413 break;
414 }
415
416 return bytes_read;
417 }
418
419 static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx *ctx,
420 unsigned char * bytes, unsigned bytes_read)
421 {
422 struct r600_bytecode_tex tex;
423
424 tex.inst = bytes[bytes_read++];
425 tex.resource_id = bytes[bytes_read++];
426 tex.src_gpr = bytes[bytes_read++];
427 tex.src_rel = bytes[bytes_read++];
428 tex.dst_gpr = bytes[bytes_read++];
429 tex.dst_rel = bytes[bytes_read++];
430 tex.dst_sel_x = bytes[bytes_read++];
431 tex.dst_sel_y = bytes[bytes_read++];
432 tex.dst_sel_z = bytes[bytes_read++];
433 tex.dst_sel_w = bytes[bytes_read++];
434 tex.lod_bias = bytes[bytes_read++];
435 tex.coord_type_x = bytes[bytes_read++];
436 tex.coord_type_y = bytes[bytes_read++];
437 tex.coord_type_z = bytes[bytes_read++];
438 tex.coord_type_w = bytes[bytes_read++];
439 tex.offset_x = bytes[bytes_read++];
440 tex.offset_y = bytes[bytes_read++];
441 tex.offset_z = bytes[bytes_read++];
442 tex.sampler_id = bytes[bytes_read++];
443 tex.src_sel_x = bytes[bytes_read++];
444 tex.src_sel_y = bytes[bytes_read++];
445 tex.src_sel_z = bytes[bytes_read++];
446 tex.src_sel_w = bytes[bytes_read++];
447
448 r600_bytecode_add_tex(ctx->bc, &tex);
449
450 return bytes_read;
451 }
452
453 static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
454 unsigned char * bytes, unsigned bytes_read)
455 {
456 struct r600_bytecode_vtx vtx;
457
458 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
459 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
460 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
461
462 memset(&vtx, 0, sizeof(vtx));
463
464 /* WORD0 */
465 vtx.inst = G_SQ_VTX_WORD0_VTX_INST(word0);
466 vtx.fetch_type = G_SQ_VTX_WORD0_FETCH_TYPE(word0);
467 vtx.buffer_id = G_SQ_VTX_WORD0_BUFFER_ID(word0);
468 vtx.src_gpr = G_SQ_VTX_WORD0_SRC_GPR(word0);
469 vtx.src_sel_x = G_SQ_VTX_WORD0_SRC_SEL_X(word0);
470 vtx.mega_fetch_count = G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(word0);
471
472 /* WORD1 */
473 vtx.dst_gpr = G_SQ_VTX_WORD1_GPR_DST_GPR(word1);
474 vtx.dst_sel_x = G_SQ_VTX_WORD1_DST_SEL_X(word1);
475 vtx.dst_sel_y = G_SQ_VTX_WORD1_DST_SEL_Y(word1);
476 vtx.dst_sel_z = G_SQ_VTX_WORD1_DST_SEL_Z(word1);
477 vtx.dst_sel_w = G_SQ_VTX_WORD1_DST_SEL_W(word1);
478 vtx.use_const_fields = G_SQ_VTX_WORD1_USE_CONST_FIELDS(word1);
479 vtx.data_format = G_SQ_VTX_WORD1_DATA_FORMAT(word1);
480 vtx.num_format_all = G_SQ_VTX_WORD1_NUM_FORMAT_ALL(word1);
481 vtx.format_comp_all = G_SQ_VTX_WORD1_FORMAT_COMP_ALL(word1);
482 vtx.srf_mode_all = G_SQ_VTX_WORD1_SRF_MODE_ALL(word1);
483
484 /* WORD 2*/
485 vtx.offset = G_SQ_VTX_WORD2_OFFSET(word2);
486 vtx.endian = G_SQ_VTX_WORD2_ENDIAN_SWAP(word2);
487
488 if (r600_bytecode_add_vtx(ctx->bc, &vtx)) {
489 fprintf(stderr, "Error adding vtx\n");
490 }
491 /* Use the Texture Cache */
492 ctx->bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX;
493 return bytes_read;
494 }
495
496 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
497 unsigned char * bytes, unsigned num_bytes)
498 {
499 unsigned bytes_read = 0;
500 unsigned i, byte;
501 while (bytes_read < num_bytes) {
502 char inst_type = bytes[bytes_read++];
503 switch (inst_type) {
504 case 0:
505 bytes_read = r600_alu_from_byte_stream(ctx, bytes,
506 bytes_read);
507 break;
508 case 1:
509 bytes_read = r600_tex_from_byte_stream(ctx, bytes,
510 bytes_read);
511 break;
512 case 2:
513 bytes_read = r600_fc_from_byte_stream(ctx, bytes,
514 bytes_read);
515 break;
516 case 3:
517 r600_bytecode_add_cfinst(ctx->bc, CF_NATIVE);
518 for (i = 0; i < 2; i++) {
519 for (byte = 0 ; byte < 4; byte++) {
520 ctx->bc->cf_last->isa[i] |=
521 (bytes[bytes_read++] << (byte * 8));
522 }
523 }
524 break;
525
526 case 4:
527 bytes_read = r600_vtx_from_byte_stream(ctx, bytes,
528 bytes_read);
529 break;
530 default:
531 /* XXX: Error here */
532 break;
533 }
534 }
535 }
536
537 /* End bytestream -> r600 shader functions*/
538
539 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
540 {
541 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
542 int j;
543
544 if (i->Instruction.NumDstRegs > 1) {
545 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
546 return -EINVAL;
547 }
548 if (i->Instruction.Predicate) {
549 R600_ERR("predicate unsupported\n");
550 return -EINVAL;
551 }
552 #if 0
553 if (i->Instruction.Label) {
554 R600_ERR("label unsupported\n");
555 return -EINVAL;
556 }
557 #endif
558 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
559 if (i->Src[j].Register.Dimension) {
560 R600_ERR("unsupported src %d (dimension %d)\n", j,
561 i->Src[j].Register.Dimension);
562 return -EINVAL;
563 }
564 }
565 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
566 if (i->Dst[j].Register.Dimension) {
567 R600_ERR("unsupported dst (dimension)\n");
568 return -EINVAL;
569 }
570 }
571 return 0;
572 }
573
574 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
575 {
576 int i, r;
577 struct r600_bytecode_alu alu;
578 int gpr = 0, base_chan = 0;
579 int ij_index = 0;
580
581 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
582 ij_index = 0;
583 if (ctx->shader->input[input].centroid)
584 ij_index++;
585 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
586 ij_index = 0;
587 /* if we have perspective add one */
588 if (ctx->input_perspective) {
589 ij_index++;
590 /* if we have perspective centroid */
591 if (ctx->input_centroid)
592 ij_index++;
593 }
594 if (ctx->shader->input[input].centroid)
595 ij_index++;
596 }
597
598 /* work out gpr and base_chan from index */
599 gpr = ij_index / 2;
600 base_chan = (2 * (ij_index % 2)) + 1;
601
602 for (i = 0; i < 8; i++) {
603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
604
605 if (i < 4)
606 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW;
607 else
608 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY;
609
610 if ((i > 1) && (i < 6)) {
611 alu.dst.sel = ctx->shader->input[input].gpr;
612 alu.dst.write = 1;
613 }
614
615 alu.dst.chan = i % 4;
616
617 alu.src[0].sel = gpr;
618 alu.src[0].chan = (base_chan - (i % 2));
619
620 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
621
622 alu.bank_swizzle_force = SQ_ALU_VEC_210;
623 if ((i % 4) == 3)
624 alu.last = 1;
625 r = r600_bytecode_add_alu(ctx->bc, &alu);
626 if (r)
627 return r;
628 }
629 return 0;
630 }
631
632 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
633 {
634 int i, r;
635 struct r600_bytecode_alu alu;
636
637 for (i = 0; i < 4; i++) {
638 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
639
640 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0;
641
642 alu.dst.sel = ctx->shader->input[input].gpr;
643 alu.dst.write = 1;
644
645 alu.dst.chan = i;
646
647 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
648 alu.src[0].chan = i;
649
650 if (i == 3)
651 alu.last = 1;
652 r = r600_bytecode_add_alu(ctx->bc, &alu);
653 if (r)
654 return r;
655 }
656 return 0;
657 }
658
659 /*
660 * Special export handling in shaders
661 *
662 * shader export ARRAY_BASE for EXPORT_POS:
663 * 60 is position
664 * 61 is misc vector
665 * 62, 63 are clip distance vectors
666 *
667 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
668 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
669 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
670 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
671 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
672 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
673 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
674 * exclusive from render target index)
675 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
676 *
677 *
678 * shader export ARRAY_BASE for EXPORT_PIXEL:
679 * 0-7 CB targets
680 * 61 computed Z vector
681 *
682 * The use of the values exported in the computed Z vector are controlled
683 * by DB_SHADER_CONTROL:
684 * Z_EXPORT_ENABLE - Z as a float in RED
685 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
686 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
687 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
688 * DB_SOURCE_FORMAT - export control restrictions
689 *
690 */
691
692
693 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
694 static int r600_spi_sid(struct r600_shader_io * io)
695 {
696 int index, name = io->name;
697
698 /* These params are handled differently, they don't need
699 * semantic indices, so we'll use 0 for them.
700 */
701 if (name == TGSI_SEMANTIC_POSITION ||
702 name == TGSI_SEMANTIC_PSIZE ||
703 name == TGSI_SEMANTIC_FACE)
704 index = 0;
705 else {
706 if (name == TGSI_SEMANTIC_GENERIC) {
707 /* For generic params simply use sid from tgsi */
708 index = io->sid;
709 } else {
710 /* For non-generic params - pack name and sid into 8 bits */
711 index = 0x80 | (name<<3) | (io->sid);
712 }
713
714 /* Make sure that all really used indices have nonzero value, so
715 * we can just compare it to 0 later instead of comparing the name
716 * with different values to detect special cases. */
717 index++;
718 }
719
720 return index;
721 };
722
723 /* turn input into interpolate on EG */
724 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
725 {
726 int r = 0;
727
728 if (ctx->shader->input[index].spi_sid) {
729 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
730 if (ctx->shader->input[index].interpolate > 0) {
731 r = evergreen_interp_alu(ctx, index);
732 } else {
733 r = evergreen_interp_flat(ctx, index);
734 }
735 }
736 return r;
737 }
738
739 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
740 {
741 struct r600_bytecode_alu alu;
742 int i, r;
743 int gpr_front = ctx->shader->input[front].gpr;
744 int gpr_back = ctx->shader->input[back].gpr;
745
746 for (i = 0; i < 4; i++) {
747 memset(&alu, 0, sizeof(alu));
748 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
749 alu.is_op3 = 1;
750 alu.dst.write = 1;
751 alu.dst.sel = gpr_front;
752 alu.src[0].sel = ctx->face_gpr;
753 alu.src[1].sel = gpr_front;
754 alu.src[2].sel = gpr_back;
755
756 alu.dst.chan = i;
757 alu.src[1].chan = i;
758 alu.src[2].chan = i;
759 alu.last = (i==3);
760
761 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
762 return r;
763 }
764
765 return 0;
766 }
767
768 static int tgsi_declaration(struct r600_shader_ctx *ctx)
769 {
770 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
771 unsigned i;
772 int r;
773
774 switch (d->Declaration.File) {
775 case TGSI_FILE_INPUT:
776 i = ctx->shader->ninput++;
777 ctx->shader->input[i].name = d->Semantic.Name;
778 ctx->shader->input[i].sid = d->Semantic.Index;
779 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
780 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
781 ctx->shader->input[i].centroid = d->Interp.Centroid;
782 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
783 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
784 switch (ctx->shader->input[i].name) {
785 case TGSI_SEMANTIC_FACE:
786 ctx->face_gpr = ctx->shader->input[i].gpr;
787 break;
788 case TGSI_SEMANTIC_COLOR:
789 ctx->colors_used++;
790 break;
791 case TGSI_SEMANTIC_POSITION:
792 ctx->fragcoord_input = i;
793 break;
794 }
795 if (ctx->bc->chip_class >= EVERGREEN) {
796 if ((r = evergreen_interp_input(ctx, i)))
797 return r;
798 }
799 }
800 break;
801 case TGSI_FILE_OUTPUT:
802 i = ctx->shader->noutput++;
803 ctx->shader->output[i].name = d->Semantic.Name;
804 ctx->shader->output[i].sid = d->Semantic.Index;
805 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
806 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
807 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
808 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
809 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
810 switch (d->Semantic.Name) {
811 case TGSI_SEMANTIC_CLIPDIST:
812 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
813 break;
814 case TGSI_SEMANTIC_PSIZE:
815 ctx->shader->vs_out_misc_write = 1;
816 ctx->shader->vs_out_point_size = 1;
817 break;
818 case TGSI_SEMANTIC_CLIPVERTEX:
819 ctx->clip_vertex_write = TRUE;
820 ctx->cv_output = i;
821 break;
822 }
823 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
824 switch (d->Semantic.Name) {
825 case TGSI_SEMANTIC_COLOR:
826 ctx->shader->nr_ps_max_color_exports++;
827 break;
828 }
829 }
830 break;
831 case TGSI_FILE_CONSTANT:
832 case TGSI_FILE_TEMPORARY:
833 case TGSI_FILE_SAMPLER:
834 case TGSI_FILE_ADDRESS:
835 break;
836
837 case TGSI_FILE_SYSTEM_VALUE:
838 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
839 if (!ctx->native_integers) {
840 struct r600_bytecode_alu alu;
841 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
842
843 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
844 alu.src[0].sel = 0;
845 alu.src[0].chan = 3;
846
847 alu.dst.sel = 0;
848 alu.dst.chan = 3;
849 alu.dst.write = 1;
850 alu.last = 1;
851
852 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
853 return r;
854 }
855 break;
856 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
857 break;
858 default:
859 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
860 return -EINVAL;
861 }
862 return 0;
863 }
864
865 static int r600_get_temp(struct r600_shader_ctx *ctx)
866 {
867 return ctx->temp_reg + ctx->max_driver_temp_used++;
868 }
869
870 /*
871 * for evergreen we need to scan the shader to find the number of GPRs we need to
872 * reserve for interpolation.
873 *
874 * we need to know if we are going to emit
875 * any centroid inputs
876 * if perspective and linear are required
877 */
878 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
879 {
880 int i;
881 int num_baryc;
882
883 ctx->input_linear = FALSE;
884 ctx->input_perspective = FALSE;
885 ctx->input_centroid = FALSE;
886 ctx->num_interp_gpr = 1;
887
888 /* any centroid inputs */
889 for (i = 0; i < ctx->info.num_inputs; i++) {
890 /* skip position/face */
891 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
892 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
893 continue;
894 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
895 ctx->input_linear = TRUE;
896 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
897 ctx->input_perspective = TRUE;
898 if (ctx->info.input_centroid[i])
899 ctx->input_centroid = TRUE;
900 }
901
902 num_baryc = 0;
903 /* ignoring sample for now */
904 if (ctx->input_perspective)
905 num_baryc++;
906 if (ctx->input_linear)
907 num_baryc++;
908 if (ctx->input_centroid)
909 num_baryc *= 2;
910
911 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
912
913 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
914 return ctx->num_interp_gpr;
915 }
916
917 static void tgsi_src(struct r600_shader_ctx *ctx,
918 const struct tgsi_full_src_register *tgsi_src,
919 struct r600_shader_src *r600_src)
920 {
921 memset(r600_src, 0, sizeof(*r600_src));
922 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
923 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
924 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
925 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
926 r600_src->neg = tgsi_src->Register.Negate;
927 r600_src->abs = tgsi_src->Register.Absolute;
928
929 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
930 int index;
931 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
932 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
933 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
934
935 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
936 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
937 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
938 return;
939 }
940 index = tgsi_src->Register.Index;
941 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
942 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
943 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
944 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
945 r600_src->swizzle[0] = 3;
946 r600_src->swizzle[1] = 3;
947 r600_src->swizzle[2] = 3;
948 r600_src->swizzle[3] = 3;
949 r600_src->sel = 0;
950 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
951 r600_src->swizzle[0] = 0;
952 r600_src->swizzle[1] = 0;
953 r600_src->swizzle[2] = 0;
954 r600_src->swizzle[3] = 0;
955 r600_src->sel = 0;
956 }
957 } else {
958 if (tgsi_src->Register.Indirect)
959 r600_src->rel = V_SQ_REL_RELATIVE;
960 r600_src->sel = tgsi_src->Register.Index;
961 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
962 }
963 }
964
965 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg)
966 {
967 struct r600_bytecode_vtx vtx;
968 unsigned int ar_reg;
969 int r;
970
971 if (offset) {
972 struct r600_bytecode_alu alu;
973
974 memset(&alu, 0, sizeof(alu));
975
976 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
977 alu.src[0].sel = ctx->bc->ar_reg;
978
979 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
980 alu.src[1].value = offset;
981
982 alu.dst.sel = dst_reg;
983 alu.dst.write = 1;
984 alu.last = 1;
985
986 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
987 return r;
988
989 ar_reg = dst_reg;
990 } else {
991 ar_reg = ctx->bc->ar_reg;
992 }
993
994 memset(&vtx, 0, sizeof(vtx));
995 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
996 vtx.src_gpr = ar_reg;
997 vtx.mega_fetch_count = 16;
998 vtx.dst_gpr = dst_reg;
999 vtx.dst_sel_x = 0; /* SEL_X */
1000 vtx.dst_sel_y = 1; /* SEL_Y */
1001 vtx.dst_sel_z = 2; /* SEL_Z */
1002 vtx.dst_sel_w = 3; /* SEL_W */
1003 vtx.data_format = FMT_32_32_32_32_FLOAT;
1004 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1005 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1006 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1007 vtx.endian = r600_endian_swap(32);
1008
1009 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1010 return r;
1011
1012 return 0;
1013 }
1014
1015 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1016 {
1017 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1018 struct r600_bytecode_alu alu;
1019 int i, j, k, nconst, r;
1020
1021 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1022 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1023 nconst++;
1024 }
1025 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1026 }
1027 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1028 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1029 continue;
1030 }
1031
1032 if (ctx->src[i].rel) {
1033 int treg = r600_get_temp(ctx);
1034 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].sel - 512, treg)))
1035 return r;
1036
1037 ctx->src[i].sel = treg;
1038 ctx->src[i].rel = 0;
1039 j--;
1040 } else if (j > 0) {
1041 int treg = r600_get_temp(ctx);
1042 for (k = 0; k < 4; k++) {
1043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1044 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1045 alu.src[0].sel = ctx->src[i].sel;
1046 alu.src[0].chan = k;
1047 alu.src[0].rel = ctx->src[i].rel;
1048 alu.dst.sel = treg;
1049 alu.dst.chan = k;
1050 alu.dst.write = 1;
1051 if (k == 3)
1052 alu.last = 1;
1053 r = r600_bytecode_add_alu(ctx->bc, &alu);
1054 if (r)
1055 return r;
1056 }
1057 ctx->src[i].sel = treg;
1058 ctx->src[i].rel =0;
1059 j--;
1060 }
1061 }
1062 return 0;
1063 }
1064
1065 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1066 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1067 {
1068 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1069 struct r600_bytecode_alu alu;
1070 int i, j, k, nliteral, r;
1071
1072 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1073 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1074 nliteral++;
1075 }
1076 }
1077 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1078 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1079 int treg = r600_get_temp(ctx);
1080 for (k = 0; k < 4; k++) {
1081 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1082 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1083 alu.src[0].sel = ctx->src[i].sel;
1084 alu.src[0].chan = k;
1085 alu.src[0].value = ctx->src[i].value[k];
1086 alu.dst.sel = treg;
1087 alu.dst.chan = k;
1088 alu.dst.write = 1;
1089 if (k == 3)
1090 alu.last = 1;
1091 r = r600_bytecode_add_alu(ctx->bc, &alu);
1092 if (r)
1093 return r;
1094 }
1095 ctx->src[i].sel = treg;
1096 j--;
1097 }
1098 }
1099 return 0;
1100 }
1101
1102 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1103 {
1104 int i, r, count = ctx->shader->ninput;
1105
1106 /* additional inputs will be allocated right after the existing inputs,
1107 * we won't need them after the color selection, so we don't need to
1108 * reserve these gprs for the rest of the shader code and to adjust
1109 * output offsets etc. */
1110 int gpr = ctx->file_offset[TGSI_FILE_INPUT] +
1111 ctx->info.file_max[TGSI_FILE_INPUT] + 1;
1112
1113 if (ctx->face_gpr == -1) {
1114 i = ctx->shader->ninput++;
1115 ctx->shader->input[i].name = TGSI_SEMANTIC_FACE;
1116 ctx->shader->input[i].spi_sid = 0;
1117 ctx->shader->input[i].gpr = gpr++;
1118 ctx->face_gpr = ctx->shader->input[i].gpr;
1119 }
1120
1121 for (i = 0; i < count; i++) {
1122 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1123 int ni = ctx->shader->ninput++;
1124 memcpy(&ctx->shader->input[ni],&ctx->shader->input[i], sizeof(struct r600_shader_io));
1125 ctx->shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1126 ctx->shader->input[ni].spi_sid = r600_spi_sid(&ctx->shader->input[ni]);
1127 ctx->shader->input[ni].gpr = gpr++;
1128
1129 if (ctx->bc->chip_class >= EVERGREEN) {
1130 r = evergreen_interp_input(ctx, ni);
1131 if (r)
1132 return r;
1133 }
1134
1135 r = select_twoside_color(ctx, i, ni);
1136 if (r)
1137 return r;
1138 }
1139 }
1140 return 0;
1141 }
1142
1143 static int r600_shader_from_tgsi(struct r600_context * rctx, struct r600_pipe_shader *pipeshader)
1144 {
1145 struct r600_shader *shader = &pipeshader->shader;
1146 struct tgsi_token *tokens = pipeshader->selector->tokens;
1147 struct pipe_stream_output_info so = pipeshader->selector->so;
1148 struct tgsi_full_immediate *immediate;
1149 struct tgsi_full_property *property;
1150 struct r600_shader_ctx ctx;
1151 struct r600_bytecode_output output[32];
1152 unsigned output_done, noutput;
1153 unsigned opcode;
1154 int i, j, k, r = 0;
1155 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
1156 /* Declarations used by llvm code */
1157 bool use_llvm = false;
1158 unsigned char * inst_bytes = NULL;
1159 unsigned inst_byte_count = 0;
1160
1161 #ifdef R600_USE_LLVM
1162 use_llvm = debug_get_bool_option("R600_LLVM", TRUE);
1163 #endif
1164 ctx.bc = &shader->bc;
1165 ctx.shader = shader;
1166 ctx.native_integers = (rctx->screen->glsl_feature_level >= 130);
1167
1168 r600_bytecode_init(ctx.bc, rctx->chip_class, rctx->family);
1169 ctx.tokens = tokens;
1170 tgsi_scan_shader(tokens, &ctx.info);
1171 tgsi_parse_init(&ctx.parse, tokens);
1172 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1173 shader->processor_type = ctx.type;
1174 ctx.bc->type = shader->processor_type;
1175
1176 ctx.face_gpr = -1;
1177 ctx.fragcoord_input = -1;
1178 ctx.colors_used = 0;
1179 ctx.clip_vertex_write = 0;
1180
1181 shader->nr_ps_color_exports = 0;
1182 shader->nr_ps_max_color_exports = 0;
1183
1184 shader->two_side = (ctx.type == TGSI_PROCESSOR_FRAGMENT) && rctx->two_side;
1185
1186 /* register allocations */
1187 /* Values [0,127] correspond to GPR[0..127].
1188 * Values [128,159] correspond to constant buffer bank 0
1189 * Values [160,191] correspond to constant buffer bank 1
1190 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1191 * Values [256,287] correspond to constant buffer bank 2 (EG)
1192 * Values [288,319] correspond to constant buffer bank 3 (EG)
1193 * Other special values are shown in the list below.
1194 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1195 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1196 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1197 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1198 * 248 SQ_ALU_SRC_0: special constant 0.0.
1199 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1200 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1201 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1202 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1203 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1204 * 254 SQ_ALU_SRC_PV: previous vector result.
1205 * 255 SQ_ALU_SRC_PS: previous scalar result.
1206 */
1207 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1208 ctx.file_offset[i] = 0;
1209 }
1210 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1211 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1212 if (ctx.bc->chip_class >= EVERGREEN) {
1213 r600_bytecode_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
1214 } else {
1215 r600_bytecode_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
1216 }
1217 }
1218 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1219 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1220 }
1221
1222 /* LLVM backend setup */
1223 #ifdef R600_USE_LLVM
1224 if (use_llvm && ctx.info.indirect_files) {
1225 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1226 "indirect adressing. Falling back to TGSI "
1227 "backend.\n");
1228 use_llvm = 0;
1229 }
1230 if (use_llvm) {
1231 struct radeon_llvm_context radeon_llvm_ctx;
1232 LLVMModuleRef mod;
1233 unsigned dump = 0;
1234 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1235 radeon_llvm_ctx.reserved_reg_count = ctx.file_offset[TGSI_FILE_INPUT];
1236 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1237 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
1238 dump = 1;
1239 }
1240 if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
1241 rctx->family, dump)) {
1242 FREE(inst_bytes);
1243 radeon_llvm_dispose(&radeon_llvm_ctx);
1244 use_llvm = 0;
1245 fprintf(stderr, "R600 LLVM backend failed to compile "
1246 "shader. Falling back to TGSI\n");
1247 } else {
1248 ctx.file_offset[TGSI_FILE_OUTPUT] =
1249 ctx.file_offset[TGSI_FILE_INPUT];
1250 }
1251 radeon_llvm_dispose(&radeon_llvm_ctx);
1252 }
1253 #endif
1254 /* End of LLVM backend setup */
1255
1256 if (!use_llvm) {
1257 ctx.file_offset[TGSI_FILE_OUTPUT] =
1258 ctx.file_offset[TGSI_FILE_INPUT] +
1259 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1260 }
1261 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1262 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1263
1264 /* Outside the GPR range. This will be translated to one of the
1265 * kcache banks later. */
1266 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1267
1268 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1269 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1270 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1271 ctx.temp_reg = ctx.bc->ar_reg + 1;
1272
1273 ctx.nliterals = 0;
1274 ctx.literals = NULL;
1275 shader->fs_write_all = FALSE;
1276 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1277 tgsi_parse_token(&ctx.parse);
1278 switch (ctx.parse.FullToken.Token.Type) {
1279 case TGSI_TOKEN_TYPE_IMMEDIATE:
1280 immediate = &ctx.parse.FullToken.FullImmediate;
1281 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1282 if(ctx.literals == NULL) {
1283 r = -ENOMEM;
1284 goto out_err;
1285 }
1286 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1287 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1288 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1289 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1290 ctx.nliterals++;
1291 break;
1292 case TGSI_TOKEN_TYPE_DECLARATION:
1293 r = tgsi_declaration(&ctx);
1294 if (r)
1295 goto out_err;
1296 break;
1297 case TGSI_TOKEN_TYPE_INSTRUCTION:
1298 break;
1299 case TGSI_TOKEN_TYPE_PROPERTY:
1300 property = &ctx.parse.FullToken.FullProperty;
1301 switch (property->Property.PropertyName) {
1302 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1303 if (property->u[0].Data == 1)
1304 shader->fs_write_all = TRUE;
1305 break;
1306 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1307 if (property->u[0].Data == 1)
1308 shader->vs_prohibit_ucps = TRUE;
1309 break;
1310 }
1311 break;
1312 default:
1313 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1314 r = -EINVAL;
1315 goto out_err;
1316 }
1317 }
1318
1319 if (shader->fs_write_all && rctx->chip_class >= EVERGREEN)
1320 shader->nr_ps_max_color_exports = 8;
1321
1322 if (ctx.fragcoord_input >= 0) {
1323 if (ctx.bc->chip_class == CAYMAN) {
1324 for (j = 0 ; j < 4; j++) {
1325 struct r600_bytecode_alu alu;
1326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1327 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1328 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1329 alu.src[0].chan = 3;
1330
1331 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1332 alu.dst.chan = j;
1333 alu.dst.write = (j == 3);
1334 alu.last = 1;
1335 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1336 return r;
1337 }
1338 } else {
1339 struct r600_bytecode_alu alu;
1340 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1341 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1342 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1343 alu.src[0].chan = 3;
1344
1345 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1346 alu.dst.chan = 3;
1347 alu.dst.write = 1;
1348 alu.last = 1;
1349 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1350 return r;
1351 }
1352 }
1353
1354 if (shader->two_side && ctx.colors_used) {
1355 if ((r = process_twoside_color_inputs(&ctx)))
1356 return r;
1357 }
1358
1359 tgsi_parse_init(&ctx.parse, tokens);
1360 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1361 tgsi_parse_token(&ctx.parse);
1362 switch (ctx.parse.FullToken.Token.Type) {
1363 case TGSI_TOKEN_TYPE_INSTRUCTION:
1364 if (use_llvm) {
1365 continue;
1366 }
1367 r = tgsi_is_supported(&ctx);
1368 if (r)
1369 goto out_err;
1370 ctx.max_driver_temp_used = 0;
1371 /* reserve first tmp for everyone */
1372 r600_get_temp(&ctx);
1373
1374 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1375 if ((r = tgsi_split_constant(&ctx)))
1376 goto out_err;
1377 if ((r = tgsi_split_literal_constant(&ctx)))
1378 goto out_err;
1379 if (ctx.bc->chip_class == CAYMAN)
1380 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1381 else if (ctx.bc->chip_class >= EVERGREEN)
1382 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1383 else
1384 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1385 r = ctx.inst_info->process(&ctx);
1386 if (r)
1387 goto out_err;
1388 break;
1389 default:
1390 break;
1391 }
1392 }
1393
1394 /* Get instructions if we are using the LLVM backend. */
1395 if (use_llvm) {
1396 r600_bytecode_from_byte_stream(&ctx, inst_bytes, inst_byte_count);
1397 FREE(inst_bytes);
1398 }
1399
1400 noutput = shader->noutput;
1401
1402 if (ctx.clip_vertex_write) {
1403 /* need to convert a clipvertex write into clipdistance writes and not export
1404 the clip vertex anymore */
1405
1406 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1407 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1408 shader->output[noutput].gpr = ctx.temp_reg;
1409 noutput++;
1410 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1411 shader->output[noutput].gpr = ctx.temp_reg+1;
1412 noutput++;
1413
1414 /* reset spi_sid for clipvertex output to avoid confusing spi */
1415 shader->output[ctx.cv_output].spi_sid = 0;
1416
1417 shader->clip_dist_write = 0xFF;
1418
1419 for (i = 0; i < 8; i++) {
1420 int oreg = i >> 2;
1421 int ochan = i & 3;
1422
1423 for (j = 0; j < 4; j++) {
1424 struct r600_bytecode_alu alu;
1425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1426 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4);
1427 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1428 alu.src[0].chan = j;
1429
1430 alu.src[1].sel = 512 + i;
1431 alu.src[1].kc_bank = 1;
1432 alu.src[1].chan = j;
1433
1434 alu.dst.sel = ctx.temp_reg + oreg;
1435 alu.dst.chan = j;
1436 alu.dst.write = (j == ochan);
1437 if (j == 3)
1438 alu.last = 1;
1439 r = r600_bytecode_add_alu(ctx.bc, &alu);
1440 if (r)
1441 return r;
1442 }
1443 }
1444 }
1445
1446 /* Add stream outputs. */
1447 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs) {
1448 for (i = 0; i < so.num_outputs; i++) {
1449 struct r600_bytecode_output output;
1450
1451 if (so.output[i].output_buffer >= 4) {
1452 R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1453 so.output[i].output_buffer);
1454 r = -EINVAL;
1455 goto out_err;
1456 }
1457 if (so.output[i].dst_offset < so.output[i].start_component) {
1458 R600_ERR("stream_output - dst_offset cannot be less than start_component\n");
1459 r = -EINVAL;
1460 goto out_err;
1461 }
1462
1463 memset(&output, 0, sizeof(struct r600_bytecode_output));
1464 output.gpr = shader->output[so.output[i].register_index].gpr;
1465 output.elem_size = 0;
1466 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1467 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1468 output.burst_count = 1;
1469 output.barrier = 1;
1470 /* array_size is an upper limit for the burst_count
1471 * with MEM_STREAM instructions */
1472 output.array_size = 0xFFF;
1473 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1474 if (ctx.bc->chip_class >= EVERGREEN) {
1475 switch (so.output[i].output_buffer) {
1476 case 0:
1477 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0;
1478 break;
1479 case 1:
1480 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1;
1481 break;
1482 case 2:
1483 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2;
1484 break;
1485 case 3:
1486 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3;
1487 break;
1488 }
1489 } else {
1490 switch (so.output[i].output_buffer) {
1491 case 0:
1492 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0;
1493 break;
1494 case 1:
1495 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1;
1496 break;
1497 case 2:
1498 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2;
1499 break;
1500 case 3:
1501 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3;
1502 break;
1503 }
1504 }
1505 r = r600_bytecode_add_output(ctx.bc, &output);
1506 if (r)
1507 goto out_err;
1508 }
1509 }
1510
1511 /* export output */
1512 for (i = 0, j = 0; i < noutput; i++, j++) {
1513 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1514 output[j].gpr = shader->output[i].gpr;
1515 output[j].elem_size = 3;
1516 output[j].swizzle_x = 0;
1517 output[j].swizzle_y = 1;
1518 output[j].swizzle_z = 2;
1519 output[j].swizzle_w = 3;
1520 output[j].burst_count = 1;
1521 output[j].barrier = 1;
1522 output[j].type = -1;
1523 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1524 switch (ctx.type) {
1525 case TGSI_PROCESSOR_VERTEX:
1526 switch (shader->output[i].name) {
1527 case TGSI_SEMANTIC_POSITION:
1528 output[j].array_base = next_pos_base++;
1529 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1530 break;
1531
1532 case TGSI_SEMANTIC_PSIZE:
1533 output[j].array_base = next_pos_base++;
1534 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1535 break;
1536 case TGSI_SEMANTIC_CLIPVERTEX:
1537 j--;
1538 break;
1539 case TGSI_SEMANTIC_CLIPDIST:
1540 output[j].array_base = next_pos_base++;
1541 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1542 /* spi_sid is 0 for clipdistance outputs that were generated
1543 * for clipvertex - we don't need to pass them to PS */
1544 if (shader->output[i].spi_sid) {
1545 j++;
1546 /* duplicate it as PARAM to pass to the pixel shader */
1547 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1548 output[j].array_base = next_param_base++;
1549 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1550 }
1551 break;
1552 case TGSI_SEMANTIC_FOG:
1553 output[j].swizzle_y = 4; /* 0 */
1554 output[j].swizzle_z = 4; /* 0 */
1555 output[j].swizzle_w = 5; /* 1 */
1556 break;
1557 }
1558 break;
1559 case TGSI_PROCESSOR_FRAGMENT:
1560 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1561 /* never export more colors than the number of CBs */
1562 if (next_pixel_base && next_pixel_base >= (rctx->nr_cbufs + rctx->dual_src_blend * 1)) {
1563 /* skip export */
1564 j--;
1565 continue;
1566 }
1567 output[j].array_base = next_pixel_base++;
1568 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1569 shader->nr_ps_color_exports++;
1570 if (shader->fs_write_all && (rctx->chip_class >= EVERGREEN)) {
1571 for (k = 1; k < rctx->nr_cbufs; k++) {
1572 j++;
1573 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1574 output[j].gpr = shader->output[i].gpr;
1575 output[j].elem_size = 3;
1576 output[j].swizzle_x = 0;
1577 output[j].swizzle_y = 1;
1578 output[j].swizzle_z = 2;
1579 output[j].swizzle_w = 3;
1580 output[j].burst_count = 1;
1581 output[j].barrier = 1;
1582 output[j].array_base = next_pixel_base++;
1583 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1584 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1585 shader->nr_ps_color_exports++;
1586 }
1587 }
1588 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1589 output[j].array_base = 61;
1590 output[j].swizzle_x = 2;
1591 output[j].swizzle_y = 7;
1592 output[j].swizzle_z = output[j].swizzle_w = 7;
1593 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1594 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1595 output[j].array_base = 61;
1596 output[j].swizzle_x = 7;
1597 output[j].swizzle_y = 1;
1598 output[j].swizzle_z = output[j].swizzle_w = 7;
1599 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1600 } else {
1601 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1602 r = -EINVAL;
1603 goto out_err;
1604 }
1605 break;
1606 default:
1607 R600_ERR("unsupported processor type %d\n", ctx.type);
1608 r = -EINVAL;
1609 goto out_err;
1610 }
1611
1612 if (output[j].type==-1) {
1613 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1614 output[j].array_base = next_param_base++;
1615 }
1616 }
1617
1618 /* add fake param output for vertex shader if no param is exported */
1619 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1620 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1621 output[j].gpr = 0;
1622 output[j].elem_size = 3;
1623 output[j].swizzle_x = 7;
1624 output[j].swizzle_y = 7;
1625 output[j].swizzle_z = 7;
1626 output[j].swizzle_w = 7;
1627 output[j].burst_count = 1;
1628 output[j].barrier = 1;
1629 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1630 output[j].array_base = 0;
1631 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1632 j++;
1633 }
1634
1635 /* add fake pixel export */
1636 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1637 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1638 output[j].gpr = 0;
1639 output[j].elem_size = 3;
1640 output[j].swizzle_x = 7;
1641 output[j].swizzle_y = 7;
1642 output[j].swizzle_z = 7;
1643 output[j].swizzle_w = 7;
1644 output[j].burst_count = 1;
1645 output[j].barrier = 1;
1646 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1647 output[j].array_base = 0;
1648 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1649 j++;
1650 }
1651
1652 noutput = j;
1653
1654 /* set export done on last export of each type */
1655 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1656 if (ctx.bc->chip_class < CAYMAN) {
1657 if (i == (noutput - 1)) {
1658 output[i].end_of_program = 1;
1659 }
1660 }
1661 if (!(output_done & (1 << output[i].type))) {
1662 output_done |= (1 << output[i].type);
1663 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
1664 }
1665 }
1666 /* add output to bytecode */
1667 for (i = 0; i < noutput; i++) {
1668 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1669 if (r)
1670 goto out_err;
1671 }
1672 /* add program end */
1673 if (ctx.bc->chip_class == CAYMAN)
1674 cm_bytecode_add_cf_end(ctx.bc);
1675
1676 /* check GPR limit - we have 124 = 128 - 4
1677 * (4 are reserved as alu clause temporary registers) */
1678 if (ctx.bc->ngpr > 124) {
1679 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1680 r = -ENOMEM;
1681 goto out_err;
1682 }
1683
1684 free(ctx.literals);
1685 tgsi_parse_free(&ctx.parse);
1686 return 0;
1687 out_err:
1688 free(ctx.literals);
1689 tgsi_parse_free(&ctx.parse);
1690 return r;
1691 }
1692
1693 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1694 {
1695 R600_ERR("%s tgsi opcode unsupported\n",
1696 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1697 return -EINVAL;
1698 }
1699
1700 static int tgsi_end(struct r600_shader_ctx *ctx)
1701 {
1702 return 0;
1703 }
1704
1705 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1706 const struct r600_shader_src *shader_src,
1707 unsigned chan)
1708 {
1709 bc_src->sel = shader_src->sel;
1710 bc_src->chan = shader_src->swizzle[chan];
1711 bc_src->neg = shader_src->neg;
1712 bc_src->abs = shader_src->abs;
1713 bc_src->rel = shader_src->rel;
1714 bc_src->value = shader_src->value[bc_src->chan];
1715 }
1716
1717 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1718 {
1719 bc_src->abs = 1;
1720 bc_src->neg = 0;
1721 }
1722
1723 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1724 {
1725 bc_src->neg = !bc_src->neg;
1726 }
1727
1728 static void tgsi_dst(struct r600_shader_ctx *ctx,
1729 const struct tgsi_full_dst_register *tgsi_dst,
1730 unsigned swizzle,
1731 struct r600_bytecode_alu_dst *r600_dst)
1732 {
1733 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1734
1735 r600_dst->sel = tgsi_dst->Register.Index;
1736 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1737 r600_dst->chan = swizzle;
1738 r600_dst->write = 1;
1739 if (tgsi_dst->Register.Indirect)
1740 r600_dst->rel = V_SQ_REL_RELATIVE;
1741 if (inst->Instruction.Saturate) {
1742 r600_dst->clamp = 1;
1743 }
1744 }
1745
1746 static int tgsi_last_instruction(unsigned writemask)
1747 {
1748 int i, lasti = 0;
1749
1750 for (i = 0; i < 4; i++) {
1751 if (writemask & (1 << i)) {
1752 lasti = i;
1753 }
1754 }
1755 return lasti;
1756 }
1757
1758 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1759 {
1760 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1761 struct r600_bytecode_alu alu;
1762 int i, j, r;
1763 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1764
1765 for (i = 0; i < lasti + 1; i++) {
1766 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1767 continue;
1768
1769 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1770 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1771
1772 alu.inst = ctx->inst_info->r600_opcode;
1773 if (!swap) {
1774 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1775 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1776 }
1777 } else {
1778 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1779 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1780 }
1781 /* handle some special cases */
1782 switch (ctx->inst_info->tgsi_opcode) {
1783 case TGSI_OPCODE_SUB:
1784 r600_bytecode_src_toggle_neg(&alu.src[1]);
1785 break;
1786 case TGSI_OPCODE_ABS:
1787 r600_bytecode_src_set_abs(&alu.src[0]);
1788 break;
1789 default:
1790 break;
1791 }
1792 if (i == lasti || trans_only) {
1793 alu.last = 1;
1794 }
1795 r = r600_bytecode_add_alu(ctx->bc, &alu);
1796 if (r)
1797 return r;
1798 }
1799 return 0;
1800 }
1801
1802 static int tgsi_op2(struct r600_shader_ctx *ctx)
1803 {
1804 return tgsi_op2_s(ctx, 0, 0);
1805 }
1806
1807 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1808 {
1809 return tgsi_op2_s(ctx, 1, 0);
1810 }
1811
1812 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1813 {
1814 return tgsi_op2_s(ctx, 0, 1);
1815 }
1816
1817 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1818 {
1819 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1820 struct r600_bytecode_alu alu;
1821 int i, r;
1822 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1823
1824 for (i = 0; i < lasti + 1; i++) {
1825
1826 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1827 continue;
1828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1829 alu.inst = ctx->inst_info->r600_opcode;
1830
1831 alu.src[0].sel = V_SQ_ALU_SRC_0;
1832
1833 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1834
1835 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1836
1837 if (i == lasti) {
1838 alu.last = 1;
1839 }
1840 r = r600_bytecode_add_alu(ctx->bc, &alu);
1841 if (r)
1842 return r;
1843 }
1844 return 0;
1845
1846 }
1847
1848 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1849 {
1850 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1851 int i, j, r;
1852 struct r600_bytecode_alu alu;
1853 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1854
1855 for (i = 0 ; i < last_slot; i++) {
1856 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1857 alu.inst = ctx->inst_info->r600_opcode;
1858 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1859 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1860 }
1861 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1862 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1863
1864 if (i == last_slot - 1)
1865 alu.last = 1;
1866 r = r600_bytecode_add_alu(ctx->bc, &alu);
1867 if (r)
1868 return r;
1869 }
1870 return 0;
1871 }
1872
1873 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1874 {
1875 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1876 int i, j, k, r;
1877 struct r600_bytecode_alu alu;
1878 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1879 for (k = 0; k < last_slot; k++) {
1880 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1881 continue;
1882
1883 for (i = 0 ; i < 4; i++) {
1884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1885 alu.inst = ctx->inst_info->r600_opcode;
1886 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1887 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1888 }
1889 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1890 alu.dst.write = (i == k);
1891 if (i == 3)
1892 alu.last = 1;
1893 r = r600_bytecode_add_alu(ctx->bc, &alu);
1894 if (r)
1895 return r;
1896 }
1897 }
1898 return 0;
1899 }
1900
1901 /*
1902 * r600 - trunc to -PI..PI range
1903 * r700 - normalize by dividing by 2PI
1904 * see fdo bug 27901
1905 */
1906 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1907 {
1908 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1909 static float double_pi = 3.1415926535 * 2;
1910 static float neg_pi = -3.1415926535;
1911
1912 int r;
1913 struct r600_bytecode_alu alu;
1914
1915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1916 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1917 alu.is_op3 = 1;
1918
1919 alu.dst.chan = 0;
1920 alu.dst.sel = ctx->temp_reg;
1921 alu.dst.write = 1;
1922
1923 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1924
1925 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1926 alu.src[1].chan = 0;
1927 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1928 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1929 alu.src[2].chan = 0;
1930 alu.last = 1;
1931 r = r600_bytecode_add_alu(ctx->bc, &alu);
1932 if (r)
1933 return r;
1934
1935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1936 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1937
1938 alu.dst.chan = 0;
1939 alu.dst.sel = ctx->temp_reg;
1940 alu.dst.write = 1;
1941
1942 alu.src[0].sel = ctx->temp_reg;
1943 alu.src[0].chan = 0;
1944 alu.last = 1;
1945 r = r600_bytecode_add_alu(ctx->bc, &alu);
1946 if (r)
1947 return r;
1948
1949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1950 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1951 alu.is_op3 = 1;
1952
1953 alu.dst.chan = 0;
1954 alu.dst.sel = ctx->temp_reg;
1955 alu.dst.write = 1;
1956
1957 alu.src[0].sel = ctx->temp_reg;
1958 alu.src[0].chan = 0;
1959
1960 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1961 alu.src[1].chan = 0;
1962 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1963 alu.src[2].chan = 0;
1964
1965 if (ctx->bc->chip_class == R600) {
1966 alu.src[1].value = *(uint32_t *)&double_pi;
1967 alu.src[2].value = *(uint32_t *)&neg_pi;
1968 } else {
1969 alu.src[1].sel = V_SQ_ALU_SRC_1;
1970 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1971 alu.src[2].neg = 1;
1972 }
1973
1974 alu.last = 1;
1975 r = r600_bytecode_add_alu(ctx->bc, &alu);
1976 if (r)
1977 return r;
1978 return 0;
1979 }
1980
1981 static int cayman_trig(struct r600_shader_ctx *ctx)
1982 {
1983 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1984 struct r600_bytecode_alu alu;
1985 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1986 int i, r;
1987
1988 r = tgsi_setup_trig(ctx);
1989 if (r)
1990 return r;
1991
1992
1993 for (i = 0; i < last_slot; i++) {
1994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1995 alu.inst = ctx->inst_info->r600_opcode;
1996 alu.dst.chan = i;
1997
1998 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1999 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2000
2001 alu.src[0].sel = ctx->temp_reg;
2002 alu.src[0].chan = 0;
2003 if (i == last_slot - 1)
2004 alu.last = 1;
2005 r = r600_bytecode_add_alu(ctx->bc, &alu);
2006 if (r)
2007 return r;
2008 }
2009 return 0;
2010 }
2011
2012 static int tgsi_trig(struct r600_shader_ctx *ctx)
2013 {
2014 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2015 struct r600_bytecode_alu alu;
2016 int i, r;
2017 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2018
2019 r = tgsi_setup_trig(ctx);
2020 if (r)
2021 return r;
2022
2023 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2024 alu.inst = ctx->inst_info->r600_opcode;
2025 alu.dst.chan = 0;
2026 alu.dst.sel = ctx->temp_reg;
2027 alu.dst.write = 1;
2028
2029 alu.src[0].sel = ctx->temp_reg;
2030 alu.src[0].chan = 0;
2031 alu.last = 1;
2032 r = r600_bytecode_add_alu(ctx->bc, &alu);
2033 if (r)
2034 return r;
2035
2036 /* replicate result */
2037 for (i = 0; i < lasti + 1; i++) {
2038 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2039 continue;
2040
2041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2042 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2043
2044 alu.src[0].sel = ctx->temp_reg;
2045 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2046 if (i == lasti)
2047 alu.last = 1;
2048 r = r600_bytecode_add_alu(ctx->bc, &alu);
2049 if (r)
2050 return r;
2051 }
2052 return 0;
2053 }
2054
2055 static int tgsi_scs(struct r600_shader_ctx *ctx)
2056 {
2057 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2058 struct r600_bytecode_alu alu;
2059 int i, r;
2060
2061 /* We'll only need the trig stuff if we are going to write to the
2062 * X or Y components of the destination vector.
2063 */
2064 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2065 r = tgsi_setup_trig(ctx);
2066 if (r)
2067 return r;
2068 }
2069
2070 /* dst.x = COS */
2071 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2072 if (ctx->bc->chip_class == CAYMAN) {
2073 for (i = 0 ; i < 3; i++) {
2074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2075 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
2076 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2077
2078 if (i == 0)
2079 alu.dst.write = 1;
2080 else
2081 alu.dst.write = 0;
2082 alu.src[0].sel = ctx->temp_reg;
2083 alu.src[0].chan = 0;
2084 if (i == 2)
2085 alu.last = 1;
2086 r = r600_bytecode_add_alu(ctx->bc, &alu);
2087 if (r)
2088 return r;
2089 }
2090 } else {
2091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2092 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
2093 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2094
2095 alu.src[0].sel = ctx->temp_reg;
2096 alu.src[0].chan = 0;
2097 alu.last = 1;
2098 r = r600_bytecode_add_alu(ctx->bc, &alu);
2099 if (r)
2100 return r;
2101 }
2102 }
2103
2104 /* dst.y = SIN */
2105 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2106 if (ctx->bc->chip_class == CAYMAN) {
2107 for (i = 0 ; i < 3; i++) {
2108 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2109 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
2110 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2111 if (i == 1)
2112 alu.dst.write = 1;
2113 else
2114 alu.dst.write = 0;
2115 alu.src[0].sel = ctx->temp_reg;
2116 alu.src[0].chan = 0;
2117 if (i == 2)
2118 alu.last = 1;
2119 r = r600_bytecode_add_alu(ctx->bc, &alu);
2120 if (r)
2121 return r;
2122 }
2123 } else {
2124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2125 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
2126 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2127
2128 alu.src[0].sel = ctx->temp_reg;
2129 alu.src[0].chan = 0;
2130 alu.last = 1;
2131 r = r600_bytecode_add_alu(ctx->bc, &alu);
2132 if (r)
2133 return r;
2134 }
2135 }
2136
2137 /* dst.z = 0.0; */
2138 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2140
2141 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2142
2143 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2144
2145 alu.src[0].sel = V_SQ_ALU_SRC_0;
2146 alu.src[0].chan = 0;
2147
2148 alu.last = 1;
2149
2150 r = r600_bytecode_add_alu(ctx->bc, &alu);
2151 if (r)
2152 return r;
2153 }
2154
2155 /* dst.w = 1.0; */
2156 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2157 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2158
2159 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2160
2161 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2162
2163 alu.src[0].sel = V_SQ_ALU_SRC_1;
2164 alu.src[0].chan = 0;
2165
2166 alu.last = 1;
2167
2168 r = r600_bytecode_add_alu(ctx->bc, &alu);
2169 if (r)
2170 return r;
2171 }
2172
2173 return 0;
2174 }
2175
2176 static int tgsi_kill(struct r600_shader_ctx *ctx)
2177 {
2178 struct r600_bytecode_alu alu;
2179 int i, r;
2180
2181 for (i = 0; i < 4; i++) {
2182 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2183 alu.inst = ctx->inst_info->r600_opcode;
2184
2185 alu.dst.chan = i;
2186
2187 alu.src[0].sel = V_SQ_ALU_SRC_0;
2188
2189 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2190 alu.src[1].sel = V_SQ_ALU_SRC_1;
2191 alu.src[1].neg = 1;
2192 } else {
2193 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2194 }
2195 if (i == 3) {
2196 alu.last = 1;
2197 }
2198 r = r600_bytecode_add_alu(ctx->bc, &alu);
2199 if (r)
2200 return r;
2201 }
2202
2203 /* kill must be last in ALU */
2204 ctx->bc->force_add_cf = 1;
2205 ctx->shader->uses_kill = TRUE;
2206 return 0;
2207 }
2208
2209 static int tgsi_lit(struct r600_shader_ctx *ctx)
2210 {
2211 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2212 struct r600_bytecode_alu alu;
2213 int r;
2214
2215 /* tmp.x = max(src.y, 0.0) */
2216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2217 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
2218 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2219 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2220 alu.src[1].chan = 1;
2221
2222 alu.dst.sel = ctx->temp_reg;
2223 alu.dst.chan = 0;
2224 alu.dst.write = 1;
2225
2226 alu.last = 1;
2227 r = r600_bytecode_add_alu(ctx->bc, &alu);
2228 if (r)
2229 return r;
2230
2231 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2232 {
2233 int chan;
2234 int sel;
2235 int i;
2236
2237 if (ctx->bc->chip_class == CAYMAN) {
2238 for (i = 0; i < 3; i++) {
2239 /* tmp.z = log(tmp.x) */
2240 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2241 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
2242 alu.src[0].sel = ctx->temp_reg;
2243 alu.src[0].chan = 0;
2244 alu.dst.sel = ctx->temp_reg;
2245 alu.dst.chan = i;
2246 if (i == 2) {
2247 alu.dst.write = 1;
2248 alu.last = 1;
2249 } else
2250 alu.dst.write = 0;
2251
2252 r = r600_bytecode_add_alu(ctx->bc, &alu);
2253 if (r)
2254 return r;
2255 }
2256 } else {
2257 /* tmp.z = log(tmp.x) */
2258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2259 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
2260 alu.src[0].sel = ctx->temp_reg;
2261 alu.src[0].chan = 0;
2262 alu.dst.sel = ctx->temp_reg;
2263 alu.dst.chan = 2;
2264 alu.dst.write = 1;
2265 alu.last = 1;
2266 r = r600_bytecode_add_alu(ctx->bc, &alu);
2267 if (r)
2268 return r;
2269 }
2270
2271 chan = alu.dst.chan;
2272 sel = alu.dst.sel;
2273
2274 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2276 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
2277 alu.src[0].sel = sel;
2278 alu.src[0].chan = chan;
2279 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2280 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2281 alu.dst.sel = ctx->temp_reg;
2282 alu.dst.chan = 0;
2283 alu.dst.write = 1;
2284 alu.is_op3 = 1;
2285 alu.last = 1;
2286 r = r600_bytecode_add_alu(ctx->bc, &alu);
2287 if (r)
2288 return r;
2289
2290 if (ctx->bc->chip_class == CAYMAN) {
2291 for (i = 0; i < 3; i++) {
2292 /* dst.z = exp(tmp.x) */
2293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2294 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2295 alu.src[0].sel = ctx->temp_reg;
2296 alu.src[0].chan = 0;
2297 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2298 if (i == 2) {
2299 alu.dst.write = 1;
2300 alu.last = 1;
2301 } else
2302 alu.dst.write = 0;
2303 r = r600_bytecode_add_alu(ctx->bc, &alu);
2304 if (r)
2305 return r;
2306 }
2307 } else {
2308 /* dst.z = exp(tmp.x) */
2309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2310 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2311 alu.src[0].sel = ctx->temp_reg;
2312 alu.src[0].chan = 0;
2313 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2314 alu.last = 1;
2315 r = r600_bytecode_add_alu(ctx->bc, &alu);
2316 if (r)
2317 return r;
2318 }
2319 }
2320
2321 /* dst.x, <- 1.0 */
2322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2323 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2324 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2325 alu.src[0].chan = 0;
2326 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2327 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2328 r = r600_bytecode_add_alu(ctx->bc, &alu);
2329 if (r)
2330 return r;
2331
2332 /* dst.y = max(src.x, 0.0) */
2333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2334 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
2335 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2336 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2337 alu.src[1].chan = 0;
2338 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2339 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2340 r = r600_bytecode_add_alu(ctx->bc, &alu);
2341 if (r)
2342 return r;
2343
2344 /* dst.w, <- 1.0 */
2345 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2346 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2347 alu.src[0].sel = V_SQ_ALU_SRC_1;
2348 alu.src[0].chan = 0;
2349 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2350 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2351 alu.last = 1;
2352 r = r600_bytecode_add_alu(ctx->bc, &alu);
2353 if (r)
2354 return r;
2355
2356 return 0;
2357 }
2358
2359 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2360 {
2361 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2362 struct r600_bytecode_alu alu;
2363 int i, r;
2364
2365 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2366
2367 /* XXX:
2368 * For state trackers other than OpenGL, we'll want to use
2369 * _RECIPSQRT_IEEE instead.
2370 */
2371 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
2372
2373 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2374 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2375 r600_bytecode_src_set_abs(&alu.src[i]);
2376 }
2377 alu.dst.sel = ctx->temp_reg;
2378 alu.dst.write = 1;
2379 alu.last = 1;
2380 r = r600_bytecode_add_alu(ctx->bc, &alu);
2381 if (r)
2382 return r;
2383 /* replicate result */
2384 return tgsi_helper_tempx_replicate(ctx);
2385 }
2386
2387 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2388 {
2389 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2390 struct r600_bytecode_alu alu;
2391 int i, r;
2392
2393 for (i = 0; i < 4; i++) {
2394 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2395 alu.src[0].sel = ctx->temp_reg;
2396 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2397 alu.dst.chan = i;
2398 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2399 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2400 if (i == 3)
2401 alu.last = 1;
2402 r = r600_bytecode_add_alu(ctx->bc, &alu);
2403 if (r)
2404 return r;
2405 }
2406 return 0;
2407 }
2408
2409 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2410 {
2411 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2412 struct r600_bytecode_alu alu;
2413 int i, r;
2414
2415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2416 alu.inst = ctx->inst_info->r600_opcode;
2417 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2418 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2419 }
2420 alu.dst.sel = ctx->temp_reg;
2421 alu.dst.write = 1;
2422 alu.last = 1;
2423 r = r600_bytecode_add_alu(ctx->bc, &alu);
2424 if (r)
2425 return r;
2426 /* replicate result */
2427 return tgsi_helper_tempx_replicate(ctx);
2428 }
2429
2430 static int cayman_pow(struct r600_shader_ctx *ctx)
2431 {
2432 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2433 int i, r;
2434 struct r600_bytecode_alu alu;
2435 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2436
2437 for (i = 0; i < 3; i++) {
2438 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2439 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2440 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2441 alu.dst.sel = ctx->temp_reg;
2442 alu.dst.chan = i;
2443 alu.dst.write = 1;
2444 if (i == 2)
2445 alu.last = 1;
2446 r = r600_bytecode_add_alu(ctx->bc, &alu);
2447 if (r)
2448 return r;
2449 }
2450
2451 /* b * LOG2(a) */
2452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2453 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2454 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2455 alu.src[1].sel = ctx->temp_reg;
2456 alu.dst.sel = ctx->temp_reg;
2457 alu.dst.write = 1;
2458 alu.last = 1;
2459 r = r600_bytecode_add_alu(ctx->bc, &alu);
2460 if (r)
2461 return r;
2462
2463 for (i = 0; i < last_slot; i++) {
2464 /* POW(a,b) = EXP2(b * LOG2(a))*/
2465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2466 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2467 alu.src[0].sel = ctx->temp_reg;
2468
2469 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2470 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2471 if (i == last_slot - 1)
2472 alu.last = 1;
2473 r = r600_bytecode_add_alu(ctx->bc, &alu);
2474 if (r)
2475 return r;
2476 }
2477 return 0;
2478 }
2479
2480 static int tgsi_pow(struct r600_shader_ctx *ctx)
2481 {
2482 struct r600_bytecode_alu alu;
2483 int r;
2484
2485 /* LOG2(a) */
2486 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2487 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2488 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2489 alu.dst.sel = ctx->temp_reg;
2490 alu.dst.write = 1;
2491 alu.last = 1;
2492 r = r600_bytecode_add_alu(ctx->bc, &alu);
2493 if (r)
2494 return r;
2495 /* b * LOG2(a) */
2496 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2497 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2498 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2499 alu.src[1].sel = ctx->temp_reg;
2500 alu.dst.sel = ctx->temp_reg;
2501 alu.dst.write = 1;
2502 alu.last = 1;
2503 r = r600_bytecode_add_alu(ctx->bc, &alu);
2504 if (r)
2505 return r;
2506 /* POW(a,b) = EXP2(b * LOG2(a))*/
2507 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2508 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2509 alu.src[0].sel = ctx->temp_reg;
2510 alu.dst.sel = ctx->temp_reg;
2511 alu.dst.write = 1;
2512 alu.last = 1;
2513 r = r600_bytecode_add_alu(ctx->bc, &alu);
2514 if (r)
2515 return r;
2516 return tgsi_helper_tempx_replicate(ctx);
2517 }
2518
2519 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2520 {
2521 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2522 struct r600_bytecode_alu alu;
2523 int i, r, j;
2524 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2525 int tmp0 = ctx->temp_reg;
2526 int tmp1 = r600_get_temp(ctx);
2527 int tmp2 = r600_get_temp(ctx);
2528 int tmp3 = r600_get_temp(ctx);
2529 /* Unsigned path:
2530 *
2531 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2532 *
2533 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2534 * 2. tmp0.z = lo (tmp0.x * src2)
2535 * 3. tmp0.w = -tmp0.z
2536 * 4. tmp0.y = hi (tmp0.x * src2)
2537 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2538 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2539 * 7. tmp1.x = tmp0.x - tmp0.w
2540 * 8. tmp1.y = tmp0.x + tmp0.w
2541 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2542 * 10. tmp0.z = hi(tmp0.x * src1) = q
2543 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2544 *
2545 * 12. tmp0.w = src1 - tmp0.y = r
2546 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2547 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2548 *
2549 * if DIV
2550 *
2551 * 15. tmp1.z = tmp0.z + 1 = q + 1
2552 * 16. tmp1.w = tmp0.z - 1 = q - 1
2553 *
2554 * else MOD
2555 *
2556 * 15. tmp1.z = tmp0.w - src2 = r - src2
2557 * 16. tmp1.w = tmp0.w + src2 = r + src2
2558 *
2559 * endif
2560 *
2561 * 17. tmp1.x = tmp1.x & tmp1.y
2562 *
2563 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2564 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2565 *
2566 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2567 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2568 *
2569 * Signed path:
2570 *
2571 * Same as unsigned, using abs values of the operands,
2572 * and fixing the sign of the result in the end.
2573 */
2574
2575 for (i = 0; i < 4; i++) {
2576 if (!(write_mask & (1<<i)))
2577 continue;
2578
2579 if (signed_op) {
2580
2581 /* tmp2.x = -src0 */
2582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2583 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2584
2585 alu.dst.sel = tmp2;
2586 alu.dst.chan = 0;
2587 alu.dst.write = 1;
2588
2589 alu.src[0].sel = V_SQ_ALU_SRC_0;
2590
2591 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2592
2593 alu.last = 1;
2594 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2595 return r;
2596
2597 /* tmp2.y = -src1 */
2598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2599 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2600
2601 alu.dst.sel = tmp2;
2602 alu.dst.chan = 1;
2603 alu.dst.write = 1;
2604
2605 alu.src[0].sel = V_SQ_ALU_SRC_0;
2606
2607 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2608
2609 alu.last = 1;
2610 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2611 return r;
2612
2613 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2614 /* it will be a sign of the quotient */
2615 if (!mod) {
2616
2617 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2618 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT);
2619
2620 alu.dst.sel = tmp2;
2621 alu.dst.chan = 2;
2622 alu.dst.write = 1;
2623
2624 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2625 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2626
2627 alu.last = 1;
2628 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2629 return r;
2630 }
2631
2632 /* tmp2.x = |src0| */
2633 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2634 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2635 alu.is_op3 = 1;
2636
2637 alu.dst.sel = tmp2;
2638 alu.dst.chan = 0;
2639 alu.dst.write = 1;
2640
2641 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2642 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2643 alu.src[2].sel = tmp2;
2644 alu.src[2].chan = 0;
2645
2646 alu.last = 1;
2647 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2648 return r;
2649
2650 /* tmp2.y = |src1| */
2651 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2652 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2653 alu.is_op3 = 1;
2654
2655 alu.dst.sel = tmp2;
2656 alu.dst.chan = 1;
2657 alu.dst.write = 1;
2658
2659 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2660 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2661 alu.src[2].sel = tmp2;
2662 alu.src[2].chan = 1;
2663
2664 alu.last = 1;
2665 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2666 return r;
2667
2668 }
2669
2670 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2671 if (ctx->bc->chip_class == CAYMAN) {
2672 /* tmp3.x = u2f(src2) */
2673 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2674 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
2675
2676 alu.dst.sel = tmp3;
2677 alu.dst.chan = 0;
2678 alu.dst.write = 1;
2679
2680 if (signed_op) {
2681 alu.src[0].sel = tmp2;
2682 alu.src[0].chan = 1;
2683 } else {
2684 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2685 }
2686
2687 alu.last = 1;
2688 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2689 return r;
2690
2691 /* tmp0.x = recip(tmp3.x) */
2692 for (j = 0 ; j < 3; j++) {
2693 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2694 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
2695
2696 alu.dst.sel = tmp0;
2697 alu.dst.chan = j;
2698 alu.dst.write = (j == 0);
2699
2700 alu.src[0].sel = tmp3;
2701 alu.src[0].chan = 0;
2702
2703 if (j == 2)
2704 alu.last = 1;
2705 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2706 return r;
2707 }
2708
2709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2710 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2711
2712 alu.src[0].sel = tmp0;
2713 alu.src[0].chan = 0;
2714
2715 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2716 alu.src[1].value = 0x4f800000;
2717
2718 alu.dst.sel = tmp3;
2719 alu.dst.write = 1;
2720 alu.last = 1;
2721 r = r600_bytecode_add_alu(ctx->bc, &alu);
2722 if (r)
2723 return r;
2724
2725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2726 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
2727
2728 alu.dst.sel = tmp0;
2729 alu.dst.chan = 0;
2730 alu.dst.write = 1;
2731
2732 alu.src[0].sel = tmp3;
2733 alu.src[0].chan = 0;
2734
2735 alu.last = 1;
2736 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2737 return r;
2738
2739 } else {
2740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2741 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT);
2742
2743 alu.dst.sel = tmp0;
2744 alu.dst.chan = 0;
2745 alu.dst.write = 1;
2746
2747 if (signed_op) {
2748 alu.src[0].sel = tmp2;
2749 alu.src[0].chan = 1;
2750 } else {
2751 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2752 }
2753
2754 alu.last = 1;
2755 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2756 return r;
2757 }
2758
2759 /* 2. tmp0.z = lo (tmp0.x * src2) */
2760 if (ctx->bc->chip_class == CAYMAN) {
2761 for (j = 0 ; j < 4; j++) {
2762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2763 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
2764
2765 alu.dst.sel = tmp0;
2766 alu.dst.chan = j;
2767 alu.dst.write = (j == 2);
2768
2769 alu.src[0].sel = tmp0;
2770 alu.src[0].chan = 0;
2771 if (signed_op) {
2772 alu.src[1].sel = tmp2;
2773 alu.src[1].chan = 1;
2774 } else {
2775 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2776 }
2777
2778 alu.last = (j == 3);
2779 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2780 return r;
2781 }
2782 } else {
2783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2784 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
2785
2786 alu.dst.sel = tmp0;
2787 alu.dst.chan = 2;
2788 alu.dst.write = 1;
2789
2790 alu.src[0].sel = tmp0;
2791 alu.src[0].chan = 0;
2792 if (signed_op) {
2793 alu.src[1].sel = tmp2;
2794 alu.src[1].chan = 1;
2795 } else {
2796 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2797 }
2798
2799 alu.last = 1;
2800 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2801 return r;
2802 }
2803
2804 /* 3. tmp0.w = -tmp0.z */
2805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2806 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2807
2808 alu.dst.sel = tmp0;
2809 alu.dst.chan = 3;
2810 alu.dst.write = 1;
2811
2812 alu.src[0].sel = V_SQ_ALU_SRC_0;
2813 alu.src[1].sel = tmp0;
2814 alu.src[1].chan = 2;
2815
2816 alu.last = 1;
2817 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2818 return r;
2819
2820 /* 4. tmp0.y = hi (tmp0.x * src2) */
2821 if (ctx->bc->chip_class == CAYMAN) {
2822 for (j = 0 ; j < 4; j++) {
2823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2824 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2825
2826 alu.dst.sel = tmp0;
2827 alu.dst.chan = j;
2828 alu.dst.write = (j == 1);
2829
2830 alu.src[0].sel = tmp0;
2831 alu.src[0].chan = 0;
2832
2833 if (signed_op) {
2834 alu.src[1].sel = tmp2;
2835 alu.src[1].chan = 1;
2836 } else {
2837 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2838 }
2839 alu.last = (j == 3);
2840 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2841 return r;
2842 }
2843 } else {
2844 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2845 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2846
2847 alu.dst.sel = tmp0;
2848 alu.dst.chan = 1;
2849 alu.dst.write = 1;
2850
2851 alu.src[0].sel = tmp0;
2852 alu.src[0].chan = 0;
2853
2854 if (signed_op) {
2855 alu.src[1].sel = tmp2;
2856 alu.src[1].chan = 1;
2857 } else {
2858 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2859 }
2860
2861 alu.last = 1;
2862 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2863 return r;
2864 }
2865
2866 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2867 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2868 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
2869 alu.is_op3 = 1;
2870
2871 alu.dst.sel = tmp0;
2872 alu.dst.chan = 2;
2873 alu.dst.write = 1;
2874
2875 alu.src[0].sel = tmp0;
2876 alu.src[0].chan = 1;
2877 alu.src[1].sel = tmp0;
2878 alu.src[1].chan = 3;
2879 alu.src[2].sel = tmp0;
2880 alu.src[2].chan = 2;
2881
2882 alu.last = 1;
2883 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2884 return r;
2885
2886 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2887 if (ctx->bc->chip_class == CAYMAN) {
2888 for (j = 0 ; j < 4; j++) {
2889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2890 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2891
2892 alu.dst.sel = tmp0;
2893 alu.dst.chan = j;
2894 alu.dst.write = (j == 3);
2895
2896 alu.src[0].sel = tmp0;
2897 alu.src[0].chan = 2;
2898
2899 alu.src[1].sel = tmp0;
2900 alu.src[1].chan = 0;
2901
2902 alu.last = (j == 3);
2903 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2904 return r;
2905 }
2906 } else {
2907 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2908 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2909
2910 alu.dst.sel = tmp0;
2911 alu.dst.chan = 3;
2912 alu.dst.write = 1;
2913
2914 alu.src[0].sel = tmp0;
2915 alu.src[0].chan = 2;
2916
2917 alu.src[1].sel = tmp0;
2918 alu.src[1].chan = 0;
2919
2920 alu.last = 1;
2921 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2922 return r;
2923 }
2924
2925 /* 7. tmp1.x = tmp0.x - tmp0.w */
2926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2927 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2928
2929 alu.dst.sel = tmp1;
2930 alu.dst.chan = 0;
2931 alu.dst.write = 1;
2932
2933 alu.src[0].sel = tmp0;
2934 alu.src[0].chan = 0;
2935 alu.src[1].sel = tmp0;
2936 alu.src[1].chan = 3;
2937
2938 alu.last = 1;
2939 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2940 return r;
2941
2942 /* 8. tmp1.y = tmp0.x + tmp0.w */
2943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2944 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
2945
2946 alu.dst.sel = tmp1;
2947 alu.dst.chan = 1;
2948 alu.dst.write = 1;
2949
2950 alu.src[0].sel = tmp0;
2951 alu.src[0].chan = 0;
2952 alu.src[1].sel = tmp0;
2953 alu.src[1].chan = 3;
2954
2955 alu.last = 1;
2956 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2957 return r;
2958
2959 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2960 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2961 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
2962 alu.is_op3 = 1;
2963
2964 alu.dst.sel = tmp0;
2965 alu.dst.chan = 0;
2966 alu.dst.write = 1;
2967
2968 alu.src[0].sel = tmp0;
2969 alu.src[0].chan = 1;
2970 alu.src[1].sel = tmp1;
2971 alu.src[1].chan = 1;
2972 alu.src[2].sel = tmp1;
2973 alu.src[2].chan = 0;
2974
2975 alu.last = 1;
2976 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2977 return r;
2978
2979 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2980 if (ctx->bc->chip_class == CAYMAN) {
2981 for (j = 0 ; j < 4; j++) {
2982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2983 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2984
2985 alu.dst.sel = tmp0;
2986 alu.dst.chan = j;
2987 alu.dst.write = (j == 2);
2988
2989 alu.src[0].sel = tmp0;
2990 alu.src[0].chan = 0;
2991
2992 if (signed_op) {
2993 alu.src[1].sel = tmp2;
2994 alu.src[1].chan = 0;
2995 } else {
2996 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2997 }
2998
2999 alu.last = (j == 3);
3000 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3001 return r;
3002 }
3003 } else {
3004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3005 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
3006
3007 alu.dst.sel = tmp0;
3008 alu.dst.chan = 2;
3009 alu.dst.write = 1;
3010
3011 alu.src[0].sel = tmp0;
3012 alu.src[0].chan = 0;
3013
3014 if (signed_op) {
3015 alu.src[1].sel = tmp2;
3016 alu.src[1].chan = 0;
3017 } else {
3018 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3019 }
3020
3021 alu.last = 1;
3022 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3023 return r;
3024 }
3025
3026 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3027 if (ctx->bc->chip_class == CAYMAN) {
3028 for (j = 0 ; j < 4; j++) {
3029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3030 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
3031
3032 alu.dst.sel = tmp0;
3033 alu.dst.chan = j;
3034 alu.dst.write = (j == 1);
3035
3036 if (signed_op) {
3037 alu.src[0].sel = tmp2;
3038 alu.src[0].chan = 1;
3039 } else {
3040 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3041 }
3042
3043 alu.src[1].sel = tmp0;
3044 alu.src[1].chan = 2;
3045
3046 alu.last = (j == 3);
3047 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3048 return r;
3049 }
3050 } else {
3051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3052 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
3053
3054 alu.dst.sel = tmp0;
3055 alu.dst.chan = 1;
3056 alu.dst.write = 1;
3057
3058 if (signed_op) {
3059 alu.src[0].sel = tmp2;
3060 alu.src[0].chan = 1;
3061 } else {
3062 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3063 }
3064
3065 alu.src[1].sel = tmp0;
3066 alu.src[1].chan = 2;
3067
3068 alu.last = 1;
3069 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3070 return r;
3071 }
3072
3073 /* 12. tmp0.w = src1 - tmp0.y = r */
3074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3075 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3076
3077 alu.dst.sel = tmp0;
3078 alu.dst.chan = 3;
3079 alu.dst.write = 1;
3080
3081 if (signed_op) {
3082 alu.src[0].sel = tmp2;
3083 alu.src[0].chan = 0;
3084 } else {
3085 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3086 }
3087
3088 alu.src[1].sel = tmp0;
3089 alu.src[1].chan = 1;
3090
3091 alu.last = 1;
3092 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3093 return r;
3094
3095 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3097 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
3098
3099 alu.dst.sel = tmp1;
3100 alu.dst.chan = 0;
3101 alu.dst.write = 1;
3102
3103 alu.src[0].sel = tmp0;
3104 alu.src[0].chan = 3;
3105 if (signed_op) {
3106 alu.src[1].sel = tmp2;
3107 alu.src[1].chan = 1;
3108 } else {
3109 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3110 }
3111
3112 alu.last = 1;
3113 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3114 return r;
3115
3116 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3117 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3118 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
3119
3120 alu.dst.sel = tmp1;
3121 alu.dst.chan = 1;
3122 alu.dst.write = 1;
3123
3124 if (signed_op) {
3125 alu.src[0].sel = tmp2;
3126 alu.src[0].chan = 0;
3127 } else {
3128 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3129 }
3130
3131 alu.src[1].sel = tmp0;
3132 alu.src[1].chan = 1;
3133
3134 alu.last = 1;
3135 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3136 return r;
3137
3138 if (mod) { /* UMOD */
3139
3140 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3142 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3143
3144 alu.dst.sel = tmp1;
3145 alu.dst.chan = 2;
3146 alu.dst.write = 1;
3147
3148 alu.src[0].sel = tmp0;
3149 alu.src[0].chan = 3;
3150
3151 if (signed_op) {
3152 alu.src[1].sel = tmp2;
3153 alu.src[1].chan = 1;
3154 } else {
3155 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3156 }
3157
3158 alu.last = 1;
3159 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3160 return r;
3161
3162 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3164 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3165
3166 alu.dst.sel = tmp1;
3167 alu.dst.chan = 3;
3168 alu.dst.write = 1;
3169
3170 alu.src[0].sel = tmp0;
3171 alu.src[0].chan = 3;
3172 if (signed_op) {
3173 alu.src[1].sel = tmp2;
3174 alu.src[1].chan = 1;
3175 } else {
3176 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3177 }
3178
3179 alu.last = 1;
3180 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3181 return r;
3182
3183 } else { /* UDIV */
3184
3185 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3187 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3188
3189 alu.dst.sel = tmp1;
3190 alu.dst.chan = 2;
3191 alu.dst.write = 1;
3192
3193 alu.src[0].sel = tmp0;
3194 alu.src[0].chan = 2;
3195 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3196
3197 alu.last = 1;
3198 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3199 return r;
3200
3201 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3203 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3204
3205 alu.dst.sel = tmp1;
3206 alu.dst.chan = 3;
3207 alu.dst.write = 1;
3208
3209 alu.src[0].sel = tmp0;
3210 alu.src[0].chan = 2;
3211 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3212
3213 alu.last = 1;
3214 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3215 return r;
3216
3217 }
3218
3219 /* 17. tmp1.x = tmp1.x & tmp1.y */
3220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3221 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
3222
3223 alu.dst.sel = tmp1;
3224 alu.dst.chan = 0;
3225 alu.dst.write = 1;
3226
3227 alu.src[0].sel = tmp1;
3228 alu.src[0].chan = 0;
3229 alu.src[1].sel = tmp1;
3230 alu.src[1].chan = 1;
3231
3232 alu.last = 1;
3233 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3234 return r;
3235
3236 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3237 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3238 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3239 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
3240 alu.is_op3 = 1;
3241
3242 alu.dst.sel = tmp0;
3243 alu.dst.chan = 2;
3244 alu.dst.write = 1;
3245
3246 alu.src[0].sel = tmp1;
3247 alu.src[0].chan = 0;
3248 alu.src[1].sel = tmp0;
3249 alu.src[1].chan = mod ? 3 : 2;
3250 alu.src[2].sel = tmp1;
3251 alu.src[2].chan = 2;
3252
3253 alu.last = 1;
3254 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3255 return r;
3256
3257 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3259 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
3260 alu.is_op3 = 1;
3261
3262 if (signed_op) {
3263 alu.dst.sel = tmp0;
3264 alu.dst.chan = 2;
3265 alu.dst.write = 1;
3266 } else {
3267 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3268 }
3269
3270 alu.src[0].sel = tmp1;
3271 alu.src[0].chan = 1;
3272 alu.src[1].sel = tmp1;
3273 alu.src[1].chan = 3;
3274 alu.src[2].sel = tmp0;
3275 alu.src[2].chan = 2;
3276
3277 alu.last = 1;
3278 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3279 return r;
3280
3281 if (signed_op) {
3282
3283 /* fix the sign of the result */
3284
3285 if (mod) {
3286
3287 /* tmp0.x = -tmp0.z */
3288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3289 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3290
3291 alu.dst.sel = tmp0;
3292 alu.dst.chan = 0;
3293 alu.dst.write = 1;
3294
3295 alu.src[0].sel = V_SQ_ALU_SRC_0;
3296 alu.src[1].sel = tmp0;
3297 alu.src[1].chan = 2;
3298
3299 alu.last = 1;
3300 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3301 return r;
3302
3303 /* sign of the remainder is the same as the sign of src0 */
3304 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3306 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3307 alu.is_op3 = 1;
3308
3309 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3310
3311 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3312 alu.src[1].sel = tmp0;
3313 alu.src[1].chan = 2;
3314 alu.src[2].sel = tmp0;
3315 alu.src[2].chan = 0;
3316
3317 alu.last = 1;
3318 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3319 return r;
3320
3321 } else {
3322
3323 /* tmp0.x = -tmp0.z */
3324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3325 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3326
3327 alu.dst.sel = tmp0;
3328 alu.dst.chan = 0;
3329 alu.dst.write = 1;
3330
3331 alu.src[0].sel = V_SQ_ALU_SRC_0;
3332 alu.src[1].sel = tmp0;
3333 alu.src[1].chan = 2;
3334
3335 alu.last = 1;
3336 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3337 return r;
3338
3339 /* fix the quotient sign (same as the sign of src0*src1) */
3340 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3341 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3342 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3343 alu.is_op3 = 1;
3344
3345 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3346
3347 alu.src[0].sel = tmp2;
3348 alu.src[0].chan = 2;
3349 alu.src[1].sel = tmp0;
3350 alu.src[1].chan = 2;
3351 alu.src[2].sel = tmp0;
3352 alu.src[2].chan = 0;
3353
3354 alu.last = 1;
3355 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3356 return r;
3357 }
3358 }
3359 }
3360 return 0;
3361 }
3362
3363 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3364 {
3365 return tgsi_divmod(ctx, 0, 0);
3366 }
3367
3368 static int tgsi_umod(struct r600_shader_ctx *ctx)
3369 {
3370 return tgsi_divmod(ctx, 1, 0);
3371 }
3372
3373 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3374 {
3375 return tgsi_divmod(ctx, 0, 1);
3376 }
3377
3378 static int tgsi_imod(struct r600_shader_ctx *ctx)
3379 {
3380 return tgsi_divmod(ctx, 1, 1);
3381 }
3382
3383
3384 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3385 {
3386 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3387 struct r600_bytecode_alu alu;
3388 int i, r;
3389 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3390 int last_inst = tgsi_last_instruction(write_mask);
3391
3392 for (i = 0; i < 4; i++) {
3393 if (!(write_mask & (1<<i)))
3394 continue;
3395
3396 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3397 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
3398
3399 alu.dst.sel = ctx->temp_reg;
3400 alu.dst.chan = i;
3401 alu.dst.write = 1;
3402
3403 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3404 if (i == last_inst)
3405 alu.last = 1;
3406 r = r600_bytecode_add_alu(ctx->bc, &alu);
3407 if (r)
3408 return r;
3409 }
3410
3411 for (i = 0; i < 4; i++) {
3412 if (!(write_mask & (1<<i)))
3413 continue;
3414
3415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3416 alu.inst = ctx->inst_info->r600_opcode;
3417
3418 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3419
3420 alu.src[0].sel = ctx->temp_reg;
3421 alu.src[0].chan = i;
3422
3423 if (i == last_inst)
3424 alu.last = 1;
3425 r = r600_bytecode_add_alu(ctx->bc, &alu);
3426 if (r)
3427 return r;
3428 }
3429
3430 return 0;
3431 }
3432
3433 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3434 {
3435 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3436 struct r600_bytecode_alu alu;
3437 int i, r;
3438 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3439 int last_inst = tgsi_last_instruction(write_mask);
3440
3441 /* tmp = -src */
3442 for (i = 0; i < 4; i++) {
3443 if (!(write_mask & (1<<i)))
3444 continue;
3445
3446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3447 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3448
3449 alu.dst.sel = ctx->temp_reg;
3450 alu.dst.chan = i;
3451 alu.dst.write = 1;
3452
3453 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3454 alu.src[0].sel = V_SQ_ALU_SRC_0;
3455
3456 if (i == last_inst)
3457 alu.last = 1;
3458 r = r600_bytecode_add_alu(ctx->bc, &alu);
3459 if (r)
3460 return r;
3461 }
3462
3463 /* dst = (src >= 0 ? src : tmp) */
3464 for (i = 0; i < 4; i++) {
3465 if (!(write_mask & (1<<i)))
3466 continue;
3467
3468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3469 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3470 alu.is_op3 = 1;
3471 alu.dst.write = 1;
3472
3473 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3474
3475 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3476 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3477 alu.src[2].sel = ctx->temp_reg;
3478 alu.src[2].chan = i;
3479
3480 if (i == last_inst)
3481 alu.last = 1;
3482 r = r600_bytecode_add_alu(ctx->bc, &alu);
3483 if (r)
3484 return r;
3485 }
3486 return 0;
3487 }
3488
3489 static int tgsi_issg(struct r600_shader_ctx *ctx)
3490 {
3491 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3492 struct r600_bytecode_alu alu;
3493 int i, r;
3494 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3495 int last_inst = tgsi_last_instruction(write_mask);
3496
3497 /* tmp = (src >= 0 ? src : -1) */
3498 for (i = 0; i < 4; i++) {
3499 if (!(write_mask & (1<<i)))
3500 continue;
3501
3502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3503 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3504 alu.is_op3 = 1;
3505
3506 alu.dst.sel = ctx->temp_reg;
3507 alu.dst.chan = i;
3508 alu.dst.write = 1;
3509
3510 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3511 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3512 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3513
3514 if (i == last_inst)
3515 alu.last = 1;
3516 r = r600_bytecode_add_alu(ctx->bc, &alu);
3517 if (r)
3518 return r;
3519 }
3520
3521 /* dst = (tmp > 0 ? 1 : tmp) */
3522 for (i = 0; i < 4; i++) {
3523 if (!(write_mask & (1<<i)))
3524 continue;
3525
3526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3527 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT);
3528 alu.is_op3 = 1;
3529 alu.dst.write = 1;
3530
3531 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3532
3533 alu.src[0].sel = ctx->temp_reg;
3534 alu.src[0].chan = i;
3535
3536 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3537
3538 alu.src[2].sel = ctx->temp_reg;
3539 alu.src[2].chan = i;
3540
3541 if (i == last_inst)
3542 alu.last = 1;
3543 r = r600_bytecode_add_alu(ctx->bc, &alu);
3544 if (r)
3545 return r;
3546 }
3547 return 0;
3548 }
3549
3550
3551
3552 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3553 {
3554 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3555 struct r600_bytecode_alu alu;
3556 int i, r;
3557
3558 /* tmp = (src > 0 ? 1 : src) */
3559 for (i = 0; i < 4; i++) {
3560 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3561 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
3562 alu.is_op3 = 1;
3563
3564 alu.dst.sel = ctx->temp_reg;
3565 alu.dst.chan = i;
3566
3567 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3568 alu.src[1].sel = V_SQ_ALU_SRC_1;
3569 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3570
3571 if (i == 3)
3572 alu.last = 1;
3573 r = r600_bytecode_add_alu(ctx->bc, &alu);
3574 if (r)
3575 return r;
3576 }
3577
3578 /* dst = (-tmp > 0 ? -1 : tmp) */
3579 for (i = 0; i < 4; i++) {
3580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3581 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
3582 alu.is_op3 = 1;
3583 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3584
3585 alu.src[0].sel = ctx->temp_reg;
3586 alu.src[0].chan = i;
3587 alu.src[0].neg = 1;
3588
3589 alu.src[1].sel = V_SQ_ALU_SRC_1;
3590 alu.src[1].neg = 1;
3591
3592 alu.src[2].sel = ctx->temp_reg;
3593 alu.src[2].chan = i;
3594
3595 if (i == 3)
3596 alu.last = 1;
3597 r = r600_bytecode_add_alu(ctx->bc, &alu);
3598 if (r)
3599 return r;
3600 }
3601 return 0;
3602 }
3603
3604 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3605 {
3606 struct r600_bytecode_alu alu;
3607 int i, r;
3608
3609 for (i = 0; i < 4; i++) {
3610 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3611 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3612 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
3613 alu.dst.chan = i;
3614 } else {
3615 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3616 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3617 alu.src[0].sel = ctx->temp_reg;
3618 alu.src[0].chan = i;
3619 }
3620 if (i == 3) {
3621 alu.last = 1;
3622 }
3623 r = r600_bytecode_add_alu(ctx->bc, &alu);
3624 if (r)
3625 return r;
3626 }
3627 return 0;
3628 }
3629
3630 static int tgsi_op3(struct r600_shader_ctx *ctx)
3631 {
3632 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3633 struct r600_bytecode_alu alu;
3634 int i, j, r;
3635 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3636
3637 for (i = 0; i < lasti + 1; i++) {
3638 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3639 continue;
3640
3641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3642 alu.inst = ctx->inst_info->r600_opcode;
3643 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3644 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3645 }
3646
3647 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3648 alu.dst.chan = i;
3649 alu.dst.write = 1;
3650 alu.is_op3 = 1;
3651 if (i == lasti) {
3652 alu.last = 1;
3653 }
3654 r = r600_bytecode_add_alu(ctx->bc, &alu);
3655 if (r)
3656 return r;
3657 }
3658 return 0;
3659 }
3660
3661 static int tgsi_dp(struct r600_shader_ctx *ctx)
3662 {
3663 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3664 struct r600_bytecode_alu alu;
3665 int i, j, r;
3666
3667 for (i = 0; i < 4; i++) {
3668 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3669 alu.inst = ctx->inst_info->r600_opcode;
3670 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3671 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3672 }
3673
3674 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3675 alu.dst.chan = i;
3676 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3677 /* handle some special cases */
3678 switch (ctx->inst_info->tgsi_opcode) {
3679 case TGSI_OPCODE_DP2:
3680 if (i > 1) {
3681 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3682 alu.src[0].chan = alu.src[1].chan = 0;
3683 }
3684 break;
3685 case TGSI_OPCODE_DP3:
3686 if (i > 2) {
3687 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3688 alu.src[0].chan = alu.src[1].chan = 0;
3689 }
3690 break;
3691 case TGSI_OPCODE_DPH:
3692 if (i == 3) {
3693 alu.src[0].sel = V_SQ_ALU_SRC_1;
3694 alu.src[0].chan = 0;
3695 alu.src[0].neg = 0;
3696 }
3697 break;
3698 default:
3699 break;
3700 }
3701 if (i == 3) {
3702 alu.last = 1;
3703 }
3704 r = r600_bytecode_add_alu(ctx->bc, &alu);
3705 if (r)
3706 return r;
3707 }
3708 return 0;
3709 }
3710
3711 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3712 unsigned index)
3713 {
3714 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3715 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3716 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3717 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3718 ctx->src[index].neg || ctx->src[index].abs;
3719 }
3720
3721 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3722 unsigned index)
3723 {
3724 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3725 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3726 }
3727
3728 static int tgsi_tex(struct r600_shader_ctx *ctx)
3729 {
3730 static float one_point_five = 1.5f;
3731 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3732 struct r600_bytecode_tex tex;
3733 struct r600_bytecode_alu alu;
3734 unsigned src_gpr;
3735 int r, i, j;
3736 int opcode;
3737 /* Texture fetch instructions can only use gprs as source.
3738 * Also they cannot negate the source or take the absolute value */
3739 const boolean src_requires_loading = tgsi_tex_src_requires_loading(ctx, 0);
3740 boolean src_loaded = FALSE;
3741 unsigned sampler_src_reg = 1;
3742 uint8_t offset_x = 0, offset_y = 0, offset_z = 0;
3743
3744 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3745
3746 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3747 /* get offset values */
3748 if (inst->Texture.NumOffsets) {
3749 assert(inst->Texture.NumOffsets == 1);
3750
3751 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3752 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3753 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3754 }
3755 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3756 /* TGSI moves the sampler to src reg 3 for TXD */
3757 sampler_src_reg = 3;
3758
3759 for (i = 1; i < 3; i++) {
3760 /* set gradients h/v */
3761 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3762 tex.inst = (i == 1) ? SQ_TEX_INST_SET_GRADIENTS_H :
3763 SQ_TEX_INST_SET_GRADIENTS_V;
3764 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3765 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3766
3767 if (tgsi_tex_src_requires_loading(ctx, i)) {
3768 tex.src_gpr = r600_get_temp(ctx);
3769 tex.src_sel_x = 0;
3770 tex.src_sel_y = 1;
3771 tex.src_sel_z = 2;
3772 tex.src_sel_w = 3;
3773
3774 for (j = 0; j < 4; j++) {
3775 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3776 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3777 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3778 alu.dst.sel = tex.src_gpr;
3779 alu.dst.chan = j;
3780 if (j == 3)
3781 alu.last = 1;
3782 alu.dst.write = 1;
3783 r = r600_bytecode_add_alu(ctx->bc, &alu);
3784 if (r)
3785 return r;
3786 }
3787
3788 } else {
3789 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3790 tex.src_sel_x = ctx->src[i].swizzle[0];
3791 tex.src_sel_y = ctx->src[i].swizzle[1];
3792 tex.src_sel_z = ctx->src[i].swizzle[2];
3793 tex.src_sel_w = ctx->src[i].swizzle[3];
3794 tex.src_rel = ctx->src[i].rel;
3795 }
3796 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3797 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3798 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3799 tex.coord_type_x = 1;
3800 tex.coord_type_y = 1;
3801 tex.coord_type_z = 1;
3802 tex.coord_type_w = 1;
3803 }
3804 r = r600_bytecode_add_tex(ctx->bc, &tex);
3805 if (r)
3806 return r;
3807 }
3808 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3809 int out_chan;
3810 /* Add perspective divide */
3811 if (ctx->bc->chip_class == CAYMAN) {
3812 out_chan = 2;
3813 for (i = 0; i < 3; i++) {
3814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3815 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3816 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3817
3818 alu.dst.sel = ctx->temp_reg;
3819 alu.dst.chan = i;
3820 if (i == 2)
3821 alu.last = 1;
3822 if (out_chan == i)
3823 alu.dst.write = 1;
3824 r = r600_bytecode_add_alu(ctx->bc, &alu);
3825 if (r)
3826 return r;
3827 }
3828
3829 } else {
3830 out_chan = 3;
3831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3832 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3833 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3834
3835 alu.dst.sel = ctx->temp_reg;
3836 alu.dst.chan = out_chan;
3837 alu.last = 1;
3838 alu.dst.write = 1;
3839 r = r600_bytecode_add_alu(ctx->bc, &alu);
3840 if (r)
3841 return r;
3842 }
3843
3844 for (i = 0; i < 3; i++) {
3845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3846 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3847 alu.src[0].sel = ctx->temp_reg;
3848 alu.src[0].chan = out_chan;
3849 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3850 alu.dst.sel = ctx->temp_reg;
3851 alu.dst.chan = i;
3852 alu.dst.write = 1;
3853 r = r600_bytecode_add_alu(ctx->bc, &alu);
3854 if (r)
3855 return r;
3856 }
3857 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3858 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3859 alu.src[0].sel = V_SQ_ALU_SRC_1;
3860 alu.src[0].chan = 0;
3861 alu.dst.sel = ctx->temp_reg;
3862 alu.dst.chan = 3;
3863 alu.last = 1;
3864 alu.dst.write = 1;
3865 r = r600_bytecode_add_alu(ctx->bc, &alu);
3866 if (r)
3867 return r;
3868 src_loaded = TRUE;
3869 src_gpr = ctx->temp_reg;
3870 }
3871
3872 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3873 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
3874 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
3875
3876 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3877 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3878
3879 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3880 for (i = 0; i < 4; i++) {
3881 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3882 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
3883 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3884 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3885 alu.dst.sel = ctx->temp_reg;
3886 alu.dst.chan = i;
3887 if (i == 3)
3888 alu.last = 1;
3889 alu.dst.write = 1;
3890 r = r600_bytecode_add_alu(ctx->bc, &alu);
3891 if (r)
3892 return r;
3893 }
3894
3895 /* tmp1.z = RCP_e(|tmp1.z|) */
3896 if (ctx->bc->chip_class == CAYMAN) {
3897 for (i = 0; i < 3; i++) {
3898 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3899 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3900 alu.src[0].sel = ctx->temp_reg;
3901 alu.src[0].chan = 2;
3902 alu.src[0].abs = 1;
3903 alu.dst.sel = ctx->temp_reg;
3904 alu.dst.chan = i;
3905 if (i == 2)
3906 alu.dst.write = 1;
3907 if (i == 2)
3908 alu.last = 1;
3909 r = r600_bytecode_add_alu(ctx->bc, &alu);
3910 if (r)
3911 return r;
3912 }
3913 } else {
3914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3915 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3916 alu.src[0].sel = ctx->temp_reg;
3917 alu.src[0].chan = 2;
3918 alu.src[0].abs = 1;
3919 alu.dst.sel = ctx->temp_reg;
3920 alu.dst.chan = 2;
3921 alu.dst.write = 1;
3922 alu.last = 1;
3923 r = r600_bytecode_add_alu(ctx->bc, &alu);
3924 if (r)
3925 return r;
3926 }
3927
3928 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3929 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3930 * muladd has no writemask, have to use another temp
3931 */
3932 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3933 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3934 alu.is_op3 = 1;
3935
3936 alu.src[0].sel = ctx->temp_reg;
3937 alu.src[0].chan = 0;
3938 alu.src[1].sel = ctx->temp_reg;
3939 alu.src[1].chan = 2;
3940
3941 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3942 alu.src[2].chan = 0;
3943 alu.src[2].value = *(uint32_t *)&one_point_five;
3944
3945 alu.dst.sel = ctx->temp_reg;
3946 alu.dst.chan = 0;
3947 alu.dst.write = 1;
3948
3949 r = r600_bytecode_add_alu(ctx->bc, &alu);
3950 if (r)
3951 return r;
3952
3953 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3954 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3955 alu.is_op3 = 1;
3956
3957 alu.src[0].sel = ctx->temp_reg;
3958 alu.src[0].chan = 1;
3959 alu.src[1].sel = ctx->temp_reg;
3960 alu.src[1].chan = 2;
3961
3962 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
3963 alu.src[2].chan = 0;
3964 alu.src[2].value = *(uint32_t *)&one_point_five;
3965
3966 alu.dst.sel = ctx->temp_reg;
3967 alu.dst.chan = 1;
3968 alu.dst.write = 1;
3969
3970 alu.last = 1;
3971 r = r600_bytecode_add_alu(ctx->bc, &alu);
3972 if (r)
3973 return r;
3974 /* write initial W value into Z component */
3975 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
3976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3977 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3978 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3979 alu.dst.sel = ctx->temp_reg;
3980 alu.dst.chan = 2;
3981 alu.dst.write = 1;
3982 alu.last = 1;
3983 r = r600_bytecode_add_alu(ctx->bc, &alu);
3984 if (r)
3985 return r;
3986 }
3987 src_loaded = TRUE;
3988 src_gpr = ctx->temp_reg;
3989 }
3990
3991 if (src_requires_loading && !src_loaded) {
3992 for (i = 0; i < 4; i++) {
3993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3994 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3995 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3996 alu.dst.sel = ctx->temp_reg;
3997 alu.dst.chan = i;
3998 if (i == 3)
3999 alu.last = 1;
4000 alu.dst.write = 1;
4001 r = r600_bytecode_add_alu(ctx->bc, &alu);
4002 if (r)
4003 return r;
4004 }
4005 src_loaded = TRUE;
4006 src_gpr = ctx->temp_reg;
4007 }
4008
4009 opcode = ctx->inst_info->r600_opcode;
4010 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4011 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4012 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4013 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4014 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4015 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) {
4016 switch (opcode) {
4017 case SQ_TEX_INST_SAMPLE:
4018 opcode = SQ_TEX_INST_SAMPLE_C;
4019 break;
4020 case SQ_TEX_INST_SAMPLE_L:
4021 opcode = SQ_TEX_INST_SAMPLE_C_L;
4022 break;
4023 case SQ_TEX_INST_SAMPLE_LB:
4024 opcode = SQ_TEX_INST_SAMPLE_C_LB;
4025 break;
4026 case SQ_TEX_INST_SAMPLE_G:
4027 opcode = SQ_TEX_INST_SAMPLE_C_G;
4028 break;
4029 }
4030 }
4031
4032 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4033 tex.inst = opcode;
4034
4035 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4036 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4037 tex.src_gpr = src_gpr;
4038 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4039 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4040 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4041 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4042 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4043 if (src_loaded) {
4044 tex.src_sel_x = 0;
4045 tex.src_sel_y = 1;
4046 tex.src_sel_z = 2;
4047 tex.src_sel_w = 3;
4048 } else {
4049 tex.src_sel_x = ctx->src[0].swizzle[0];
4050 tex.src_sel_y = ctx->src[0].swizzle[1];
4051 tex.src_sel_z = ctx->src[0].swizzle[2];
4052 tex.src_sel_w = ctx->src[0].swizzle[3];
4053 tex.src_rel = ctx->src[0].rel;
4054 }
4055
4056 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
4057 tex.src_sel_x = 1;
4058 tex.src_sel_y = 0;
4059 tex.src_sel_z = 3;
4060 tex.src_sel_w = 1;
4061 }
4062 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {
4063 tex.src_sel_x = 1;
4064 tex.src_sel_y = 0;
4065 tex.src_sel_z = 3;
4066 tex.src_sel_w = 2; /* route Z compare value into W */
4067 }
4068
4069 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4070 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4071 tex.coord_type_x = 1;
4072 tex.coord_type_y = 1;
4073 }
4074 tex.coord_type_z = 1;
4075 tex.coord_type_w = 1;
4076
4077 tex.offset_x = offset_x;
4078 tex.offset_y = offset_y;
4079 tex.offset_z = offset_z;
4080
4081 /* Put the depth for comparison in W.
4082 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4083 * Some instructions expect the depth in Z. */
4084 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4085 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4086 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4087 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4088 opcode != SQ_TEX_INST_SAMPLE_C_L &&
4089 opcode != SQ_TEX_INST_SAMPLE_C_LB) {
4090 tex.src_sel_w = tex.src_sel_z;
4091 }
4092
4093 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4094 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4095 if (opcode == SQ_TEX_INST_SAMPLE_C_L ||
4096 opcode == SQ_TEX_INST_SAMPLE_C_LB) {
4097 /* the array index is read from Y */
4098 tex.coord_type_y = 0;
4099 } else {
4100 /* the array index is read from Z */
4101 tex.coord_type_z = 0;
4102 tex.src_sel_z = tex.src_sel_y;
4103 }
4104 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4105 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
4106 /* the array index is read from Z */
4107 tex.coord_type_z = 0;
4108
4109 r = r600_bytecode_add_tex(ctx->bc, &tex);
4110 if (r)
4111 return r;
4112
4113 /* add shadow ambient support - gallium doesn't do it yet */
4114 return 0;
4115 }
4116
4117 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4118 {
4119 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4120 struct r600_bytecode_alu alu;
4121 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4122 unsigned i;
4123 int r;
4124
4125 /* optimize if it's just an equal balance */
4126 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4127 for (i = 0; i < lasti + 1; i++) {
4128 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4129 continue;
4130
4131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4132 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
4133 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4134 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4135 alu.omod = 3;
4136 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4137 alu.dst.chan = i;
4138 if (i == lasti) {
4139 alu.last = 1;
4140 }
4141 r = r600_bytecode_add_alu(ctx->bc, &alu);
4142 if (r)
4143 return r;
4144 }
4145 return 0;
4146 }
4147
4148 /* 1 - src0 */
4149 for (i = 0; i < lasti + 1; i++) {
4150 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4151 continue;
4152
4153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4154 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
4155 alu.src[0].sel = V_SQ_ALU_SRC_1;
4156 alu.src[0].chan = 0;
4157 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4158 r600_bytecode_src_toggle_neg(&alu.src[1]);
4159 alu.dst.sel = ctx->temp_reg;
4160 alu.dst.chan = i;
4161 if (i == lasti) {
4162 alu.last = 1;
4163 }
4164 alu.dst.write = 1;
4165 r = r600_bytecode_add_alu(ctx->bc, &alu);
4166 if (r)
4167 return r;
4168 }
4169
4170 /* (1 - src0) * src2 */
4171 for (i = 0; i < lasti + 1; i++) {
4172 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4173 continue;
4174
4175 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4176 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4177 alu.src[0].sel = ctx->temp_reg;
4178 alu.src[0].chan = i;
4179 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4180 alu.dst.sel = ctx->temp_reg;
4181 alu.dst.chan = i;
4182 if (i == lasti) {
4183 alu.last = 1;
4184 }
4185 alu.dst.write = 1;
4186 r = r600_bytecode_add_alu(ctx->bc, &alu);
4187 if (r)
4188 return r;
4189 }
4190
4191 /* src0 * src1 + (1 - src0) * src2 */
4192 for (i = 0; i < lasti + 1; i++) {
4193 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4194 continue;
4195
4196 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4197 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
4198 alu.is_op3 = 1;
4199 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4200 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4201 alu.src[2].sel = ctx->temp_reg;
4202 alu.src[2].chan = i;
4203
4204 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4205 alu.dst.chan = i;
4206 if (i == lasti) {
4207 alu.last = 1;
4208 }
4209 r = r600_bytecode_add_alu(ctx->bc, &alu);
4210 if (r)
4211 return r;
4212 }
4213 return 0;
4214 }
4215
4216 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4217 {
4218 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4219 struct r600_bytecode_alu alu;
4220 int i, r;
4221 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4222
4223 for (i = 0; i < lasti + 1; i++) {
4224 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4225 continue;
4226
4227 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4228 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
4229 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4230 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4231 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4232 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4233 alu.dst.chan = i;
4234 alu.dst.write = 1;
4235 alu.is_op3 = 1;
4236 if (i == lasti)
4237 alu.last = 1;
4238 r = r600_bytecode_add_alu(ctx->bc, &alu);
4239 if (r)
4240 return r;
4241 }
4242 return 0;
4243 }
4244
4245 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4246 {
4247 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4248 static const unsigned int src0_swizzle[] = {2, 0, 1};
4249 static const unsigned int src1_swizzle[] = {1, 2, 0};
4250 struct r600_bytecode_alu alu;
4251 uint32_t use_temp = 0;
4252 int i, r;
4253
4254 if (inst->Dst[0].Register.WriteMask != 0xf)
4255 use_temp = 1;
4256
4257 for (i = 0; i < 4; i++) {
4258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4259 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4260 if (i < 3) {
4261 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4262 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4263 } else {
4264 alu.src[0].sel = V_SQ_ALU_SRC_0;
4265 alu.src[0].chan = i;
4266 alu.src[1].sel = V_SQ_ALU_SRC_0;
4267 alu.src[1].chan = i;
4268 }
4269
4270 alu.dst.sel = ctx->temp_reg;
4271 alu.dst.chan = i;
4272 alu.dst.write = 1;
4273
4274 if (i == 3)
4275 alu.last = 1;
4276 r = r600_bytecode_add_alu(ctx->bc, &alu);
4277 if (r)
4278 return r;
4279 }
4280
4281 for (i = 0; i < 4; i++) {
4282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4283 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
4284
4285 if (i < 3) {
4286 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4287 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4288 } else {
4289 alu.src[0].sel = V_SQ_ALU_SRC_0;
4290 alu.src[0].chan = i;
4291 alu.src[1].sel = V_SQ_ALU_SRC_0;
4292 alu.src[1].chan = i;
4293 }
4294
4295 alu.src[2].sel = ctx->temp_reg;
4296 alu.src[2].neg = 1;
4297 alu.src[2].chan = i;
4298
4299 if (use_temp)
4300 alu.dst.sel = ctx->temp_reg;
4301 else
4302 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4303 alu.dst.chan = i;
4304 alu.dst.write = 1;
4305 alu.is_op3 = 1;
4306 if (i == 3)
4307 alu.last = 1;
4308 r = r600_bytecode_add_alu(ctx->bc, &alu);
4309 if (r)
4310 return r;
4311 }
4312 if (use_temp)
4313 return tgsi_helper_copy(ctx, inst);
4314 return 0;
4315 }
4316
4317 static int tgsi_exp(struct r600_shader_ctx *ctx)
4318 {
4319 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4320 struct r600_bytecode_alu alu;
4321 int r;
4322 int i;
4323
4324 /* result.x = 2^floor(src); */
4325 if (inst->Dst[0].Register.WriteMask & 1) {
4326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4327
4328 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
4329 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4330
4331 alu.dst.sel = ctx->temp_reg;
4332 alu.dst.chan = 0;
4333 alu.dst.write = 1;
4334 alu.last = 1;
4335 r = r600_bytecode_add_alu(ctx->bc, &alu);
4336 if (r)
4337 return r;
4338
4339 if (ctx->bc->chip_class == CAYMAN) {
4340 for (i = 0; i < 3; i++) {
4341 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4342 alu.src[0].sel = ctx->temp_reg;
4343 alu.src[0].chan = 0;
4344
4345 alu.dst.sel = ctx->temp_reg;
4346 alu.dst.chan = i;
4347 if (i == 0)
4348 alu.dst.write = 1;
4349 if (i == 2)
4350 alu.last = 1;
4351 r = r600_bytecode_add_alu(ctx->bc, &alu);
4352 if (r)
4353 return r;
4354 }
4355 } else {
4356 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4357 alu.src[0].sel = ctx->temp_reg;
4358 alu.src[0].chan = 0;
4359
4360 alu.dst.sel = ctx->temp_reg;
4361 alu.dst.chan = 0;
4362 alu.dst.write = 1;
4363 alu.last = 1;
4364 r = r600_bytecode_add_alu(ctx->bc, &alu);
4365 if (r)
4366 return r;
4367 }
4368 }
4369
4370 /* result.y = tmp - floor(tmp); */
4371 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4373
4374 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
4375 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4376
4377 alu.dst.sel = ctx->temp_reg;
4378 #if 0
4379 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4380 if (r)
4381 return r;
4382 #endif
4383 alu.dst.write = 1;
4384 alu.dst.chan = 1;
4385
4386 alu.last = 1;
4387
4388 r = r600_bytecode_add_alu(ctx->bc, &alu);
4389 if (r)
4390 return r;
4391 }
4392
4393 /* result.z = RoughApprox2ToX(tmp);*/
4394 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4395 if (ctx->bc->chip_class == CAYMAN) {
4396 for (i = 0; i < 3; i++) {
4397 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4398 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4399 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4400
4401 alu.dst.sel = ctx->temp_reg;
4402 alu.dst.chan = i;
4403 if (i == 2) {
4404 alu.dst.write = 1;
4405 alu.last = 1;
4406 }
4407
4408 r = r600_bytecode_add_alu(ctx->bc, &alu);
4409 if (r)
4410 return r;
4411 }
4412 } else {
4413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4414 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4415 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4416
4417 alu.dst.sel = ctx->temp_reg;
4418 alu.dst.write = 1;
4419 alu.dst.chan = 2;
4420
4421 alu.last = 1;
4422
4423 r = r600_bytecode_add_alu(ctx->bc, &alu);
4424 if (r)
4425 return r;
4426 }
4427 }
4428
4429 /* result.w = 1.0;*/
4430 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4432
4433 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4434 alu.src[0].sel = V_SQ_ALU_SRC_1;
4435 alu.src[0].chan = 0;
4436
4437 alu.dst.sel = ctx->temp_reg;
4438 alu.dst.chan = 3;
4439 alu.dst.write = 1;
4440 alu.last = 1;
4441 r = r600_bytecode_add_alu(ctx->bc, &alu);
4442 if (r)
4443 return r;
4444 }
4445 return tgsi_helper_copy(ctx, inst);
4446 }
4447
4448 static int tgsi_log(struct r600_shader_ctx *ctx)
4449 {
4450 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4451 struct r600_bytecode_alu alu;
4452 int r;
4453 int i;
4454
4455 /* result.x = floor(log2(|src|)); */
4456 if (inst->Dst[0].Register.WriteMask & 1) {
4457 if (ctx->bc->chip_class == CAYMAN) {
4458 for (i = 0; i < 3; i++) {
4459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4460
4461 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4462 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4463 r600_bytecode_src_set_abs(&alu.src[0]);
4464
4465 alu.dst.sel = ctx->temp_reg;
4466 alu.dst.chan = i;
4467 if (i == 0)
4468 alu.dst.write = 1;
4469 if (i == 2)
4470 alu.last = 1;
4471 r = r600_bytecode_add_alu(ctx->bc, &alu);
4472 if (r)
4473 return r;
4474 }
4475
4476 } else {
4477 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4478
4479 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4480 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4481 r600_bytecode_src_set_abs(&alu.src[0]);
4482
4483 alu.dst.sel = ctx->temp_reg;
4484 alu.dst.chan = 0;
4485 alu.dst.write = 1;
4486 alu.last = 1;
4487 r = r600_bytecode_add_alu(ctx->bc, &alu);
4488 if (r)
4489 return r;
4490 }
4491
4492 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
4493 alu.src[0].sel = ctx->temp_reg;
4494 alu.src[0].chan = 0;
4495
4496 alu.dst.sel = ctx->temp_reg;
4497 alu.dst.chan = 0;
4498 alu.dst.write = 1;
4499 alu.last = 1;
4500
4501 r = r600_bytecode_add_alu(ctx->bc, &alu);
4502 if (r)
4503 return r;
4504 }
4505
4506 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4507 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4508
4509 if (ctx->bc->chip_class == CAYMAN) {
4510 for (i = 0; i < 3; i++) {
4511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4512
4513 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4514 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4515 r600_bytecode_src_set_abs(&alu.src[0]);
4516
4517 alu.dst.sel = ctx->temp_reg;
4518 alu.dst.chan = i;
4519 if (i == 1)
4520 alu.dst.write = 1;
4521 if (i == 2)
4522 alu.last = 1;
4523
4524 r = r600_bytecode_add_alu(ctx->bc, &alu);
4525 if (r)
4526 return r;
4527 }
4528 } else {
4529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4530
4531 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4532 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4533 r600_bytecode_src_set_abs(&alu.src[0]);
4534
4535 alu.dst.sel = ctx->temp_reg;
4536 alu.dst.chan = 1;
4537 alu.dst.write = 1;
4538 alu.last = 1;
4539
4540 r = r600_bytecode_add_alu(ctx->bc, &alu);
4541 if (r)
4542 return r;
4543 }
4544
4545 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4546
4547 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
4548 alu.src[0].sel = ctx->temp_reg;
4549 alu.src[0].chan = 1;
4550
4551 alu.dst.sel = ctx->temp_reg;
4552 alu.dst.chan = 1;
4553 alu.dst.write = 1;
4554 alu.last = 1;
4555
4556 r = r600_bytecode_add_alu(ctx->bc, &alu);
4557 if (r)
4558 return r;
4559
4560 if (ctx->bc->chip_class == CAYMAN) {
4561 for (i = 0; i < 3; i++) {
4562 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4563 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4564 alu.src[0].sel = ctx->temp_reg;
4565 alu.src[0].chan = 1;
4566
4567 alu.dst.sel = ctx->temp_reg;
4568 alu.dst.chan = i;
4569 if (i == 1)
4570 alu.dst.write = 1;
4571 if (i == 2)
4572 alu.last = 1;
4573
4574 r = r600_bytecode_add_alu(ctx->bc, &alu);
4575 if (r)
4576 return r;
4577 }
4578 } else {
4579 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4580 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4581 alu.src[0].sel = ctx->temp_reg;
4582 alu.src[0].chan = 1;
4583
4584 alu.dst.sel = ctx->temp_reg;
4585 alu.dst.chan = 1;
4586 alu.dst.write = 1;
4587 alu.last = 1;
4588
4589 r = r600_bytecode_add_alu(ctx->bc, &alu);
4590 if (r)
4591 return r;
4592 }
4593
4594 if (ctx->bc->chip_class == CAYMAN) {
4595 for (i = 0; i < 3; i++) {
4596 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4597 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
4598 alu.src[0].sel = ctx->temp_reg;
4599 alu.src[0].chan = 1;
4600
4601 alu.dst.sel = ctx->temp_reg;
4602 alu.dst.chan = i;
4603 if (i == 1)
4604 alu.dst.write = 1;
4605 if (i == 2)
4606 alu.last = 1;
4607
4608 r = r600_bytecode_add_alu(ctx->bc, &alu);
4609 if (r)
4610 return r;
4611 }
4612 } else {
4613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4614 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
4615 alu.src[0].sel = ctx->temp_reg;
4616 alu.src[0].chan = 1;
4617
4618 alu.dst.sel = ctx->temp_reg;
4619 alu.dst.chan = 1;
4620 alu.dst.write = 1;
4621 alu.last = 1;
4622
4623 r = r600_bytecode_add_alu(ctx->bc, &alu);
4624 if (r)
4625 return r;
4626 }
4627
4628 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4629
4630 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4631
4632 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4633 r600_bytecode_src_set_abs(&alu.src[0]);
4634
4635 alu.src[1].sel = ctx->temp_reg;
4636 alu.src[1].chan = 1;
4637
4638 alu.dst.sel = ctx->temp_reg;
4639 alu.dst.chan = 1;
4640 alu.dst.write = 1;
4641 alu.last = 1;
4642
4643 r = r600_bytecode_add_alu(ctx->bc, &alu);
4644 if (r)
4645 return r;
4646 }
4647
4648 /* result.z = log2(|src|);*/
4649 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
4650 if (ctx->bc->chip_class == CAYMAN) {
4651 for (i = 0; i < 3; i++) {
4652 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4653
4654 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4655 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4656 r600_bytecode_src_set_abs(&alu.src[0]);
4657
4658 alu.dst.sel = ctx->temp_reg;
4659 if (i == 2)
4660 alu.dst.write = 1;
4661 alu.dst.chan = i;
4662 if (i == 2)
4663 alu.last = 1;
4664
4665 r = r600_bytecode_add_alu(ctx->bc, &alu);
4666 if (r)
4667 return r;
4668 }
4669 } else {
4670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4671
4672 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4673 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4674 r600_bytecode_src_set_abs(&alu.src[0]);
4675
4676 alu.dst.sel = ctx->temp_reg;
4677 alu.dst.write = 1;
4678 alu.dst.chan = 2;
4679 alu.last = 1;
4680
4681 r = r600_bytecode_add_alu(ctx->bc, &alu);
4682 if (r)
4683 return r;
4684 }
4685 }
4686
4687 /* result.w = 1.0; */
4688 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
4689 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4690
4691 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4692 alu.src[0].sel = V_SQ_ALU_SRC_1;
4693 alu.src[0].chan = 0;
4694
4695 alu.dst.sel = ctx->temp_reg;
4696 alu.dst.chan = 3;
4697 alu.dst.write = 1;
4698 alu.last = 1;
4699
4700 r = r600_bytecode_add_alu(ctx->bc, &alu);
4701 if (r)
4702 return r;
4703 }
4704
4705 return tgsi_helper_copy(ctx, inst);
4706 }
4707
4708 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
4709 {
4710 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4711 struct r600_bytecode_alu alu;
4712 int r;
4713
4714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4715
4716 switch (inst->Instruction.Opcode) {
4717 case TGSI_OPCODE_ARL:
4718 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
4719 break;
4720 case TGSI_OPCODE_ARR:
4721 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
4722 break;
4723 case TGSI_OPCODE_UARL:
4724 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
4725 break;
4726 default:
4727 assert(0);
4728 return -1;
4729 }
4730
4731 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4732 alu.last = 1;
4733 alu.dst.sel = ctx->bc->ar_reg;
4734 alu.dst.write = 1;
4735 r = r600_bytecode_add_alu(ctx->bc, &alu);
4736 if (r)
4737 return r;
4738
4739 ctx->bc->ar_loaded = 0;
4740 return 0;
4741 }
4742 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
4743 {
4744 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4745 struct r600_bytecode_alu alu;
4746 int r;
4747
4748 switch (inst->Instruction.Opcode) {
4749 case TGSI_OPCODE_ARL:
4750 memset(&alu, 0, sizeof(alu));
4751 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
4752 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4753 alu.dst.sel = ctx->bc->ar_reg;
4754 alu.dst.write = 1;
4755 alu.last = 1;
4756
4757 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4758 return r;
4759
4760 memset(&alu, 0, sizeof(alu));
4761 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
4762 alu.src[0].sel = ctx->bc->ar_reg;
4763 alu.dst.sel = ctx->bc->ar_reg;
4764 alu.dst.write = 1;
4765 alu.last = 1;
4766
4767 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4768 return r;
4769 break;
4770 case TGSI_OPCODE_ARR:
4771 memset(&alu, 0, sizeof(alu));
4772 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
4773 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4774 alu.dst.sel = ctx->bc->ar_reg;
4775 alu.dst.write = 1;
4776 alu.last = 1;
4777
4778 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4779 return r;
4780 break;
4781 case TGSI_OPCODE_UARL:
4782 memset(&alu, 0, sizeof(alu));
4783 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
4784 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4785 alu.dst.sel = ctx->bc->ar_reg;
4786 alu.dst.write = 1;
4787 alu.last = 1;
4788
4789 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
4790 return r;
4791 break;
4792 default:
4793 assert(0);
4794 return -1;
4795 }
4796
4797 ctx->bc->ar_loaded = 0;
4798 return 0;
4799 }
4800
4801 static int tgsi_opdst(struct r600_shader_ctx *ctx)
4802 {
4803 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4804 struct r600_bytecode_alu alu;
4805 int i, r = 0;
4806
4807 for (i = 0; i < 4; i++) {
4808 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4809
4810 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4811 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4812
4813 if (i == 0 || i == 3) {
4814 alu.src[0].sel = V_SQ_ALU_SRC_1;
4815 } else {
4816 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4817 }
4818
4819 if (i == 0 || i == 2) {
4820 alu.src[1].sel = V_SQ_ALU_SRC_1;
4821 } else {
4822 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4823 }
4824 if (i == 3)
4825 alu.last = 1;
4826 r = r600_bytecode_add_alu(ctx->bc, &alu);
4827 if (r)
4828 return r;
4829 }
4830 return 0;
4831 }
4832
4833 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
4834 {
4835 struct r600_bytecode_alu alu;
4836 int r;
4837
4838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4839 alu.inst = opcode;
4840 alu.predicate = 1;
4841
4842 alu.dst.sel = ctx->temp_reg;
4843 alu.dst.write = 1;
4844 alu.dst.chan = 0;
4845
4846 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4847 alu.src[1].sel = V_SQ_ALU_SRC_0;
4848 alu.src[1].chan = 0;
4849
4850 alu.last = 1;
4851
4852 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
4853 if (r)
4854 return r;
4855 return 0;
4856 }
4857
4858 static int pops(struct r600_shader_ctx *ctx, int pops)
4859 {
4860 unsigned force_pop = ctx->bc->force_add_cf;
4861
4862 if (!force_pop) {
4863 int alu_pop = 3;
4864 if (ctx->bc->cf_last) {
4865 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU))
4866 alu_pop = 0;
4867 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER))
4868 alu_pop = 1;
4869 }
4870 alu_pop += pops;
4871 if (alu_pop == 1) {
4872 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER);
4873 ctx->bc->force_add_cf = 1;
4874 } else if (alu_pop == 2) {
4875 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER);
4876 ctx->bc->force_add_cf = 1;
4877 } else {
4878 force_pop = 1;
4879 }
4880 }
4881
4882 if (force_pop) {
4883 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
4884 ctx->bc->cf_last->pop_count = pops;
4885 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
4886 }
4887
4888 return 0;
4889 }
4890
4891 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
4892 {
4893 switch(reason) {
4894 case FC_PUSH_VPM:
4895 ctx->bc->callstack[ctx->bc->call_sp].current--;
4896 break;
4897 case FC_PUSH_WQM:
4898 case FC_LOOP:
4899 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
4900 break;
4901 case FC_REP:
4902 /* TOODO : for 16 vp asic should -= 2; */
4903 ctx->bc->callstack[ctx->bc->call_sp].current --;
4904 break;
4905 }
4906 }
4907
4908 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
4909 {
4910 if (check_max_only) {
4911 int diff;
4912 switch (reason) {
4913 case FC_PUSH_VPM:
4914 diff = 1;
4915 break;
4916 case FC_PUSH_WQM:
4917 diff = 4;
4918 break;
4919 default:
4920 assert(0);
4921 diff = 0;
4922 }
4923 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
4924 ctx->bc->callstack[ctx->bc->call_sp].max) {
4925 ctx->bc->callstack[ctx->bc->call_sp].max =
4926 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
4927 }
4928 return;
4929 }
4930 switch (reason) {
4931 case FC_PUSH_VPM:
4932 ctx->bc->callstack[ctx->bc->call_sp].current++;
4933 break;
4934 case FC_PUSH_WQM:
4935 case FC_LOOP:
4936 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
4937 break;
4938 case FC_REP:
4939 ctx->bc->callstack[ctx->bc->call_sp].current++;
4940 break;
4941 }
4942
4943 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
4944 ctx->bc->callstack[ctx->bc->call_sp].max) {
4945 ctx->bc->callstack[ctx->bc->call_sp].max =
4946 ctx->bc->callstack[ctx->bc->call_sp].current;
4947 }
4948 }
4949
4950 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
4951 {
4952 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
4953
4954 sp->mid = (struct r600_bytecode_cf **)realloc((void *)sp->mid,
4955 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
4956 sp->mid[sp->num_mid] = ctx->bc->cf_last;
4957 sp->num_mid++;
4958 }
4959
4960 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
4961 {
4962 ctx->bc->fc_sp++;
4963 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
4964 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
4965 }
4966
4967 static void fc_poplevel(struct r600_shader_ctx *ctx)
4968 {
4969 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
4970 if (sp->mid) {
4971 free(sp->mid);
4972 sp->mid = NULL;
4973 }
4974 sp->num_mid = 0;
4975 sp->start = NULL;
4976 sp->type = 0;
4977 ctx->bc->fc_sp--;
4978 }
4979
4980 #if 0
4981 static int emit_return(struct r600_shader_ctx *ctx)
4982 {
4983 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
4984 return 0;
4985 }
4986
4987 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
4988 {
4989
4990 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
4991 ctx->bc->cf_last->pop_count = pops;
4992 /* XXX work out offset */
4993 return 0;
4994 }
4995
4996 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
4997 {
4998 return 0;
4999 }
5000
5001 static void emit_testflag(struct r600_shader_ctx *ctx)
5002 {
5003
5004 }
5005
5006 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5007 {
5008 emit_testflag(ctx);
5009 emit_jump_to_offset(ctx, 1, 4);
5010 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5011 pops(ctx, ifidx + 1);
5012 emit_return(ctx);
5013 }
5014
5015 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5016 {
5017 emit_testflag(ctx);
5018
5019 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
5020 ctx->bc->cf_last->pop_count = 1;
5021
5022 fc_set_mid(ctx, fc_sp);
5023
5024 pops(ctx, 1);
5025 }
5026 #endif
5027
5028 static int tgsi_if(struct r600_shader_ctx *ctx)
5029 {
5030 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
5031
5032 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
5033
5034 fc_pushlevel(ctx, FC_IF);
5035
5036 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
5037 return 0;
5038 }
5039
5040 static int tgsi_else(struct r600_shader_ctx *ctx)
5041 {
5042 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
5043 ctx->bc->cf_last->pop_count = 1;
5044
5045 fc_set_mid(ctx, ctx->bc->fc_sp);
5046 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5047 return 0;
5048 }
5049
5050 static int tgsi_endif(struct r600_shader_ctx *ctx)
5051 {
5052 pops(ctx, 1);
5053 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5054 R600_ERR("if/endif unbalanced in shader\n");
5055 return -1;
5056 }
5057
5058 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5059 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5060 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5061 } else {
5062 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5063 }
5064 fc_poplevel(ctx);
5065
5066 callstack_decrease_current(ctx, FC_PUSH_VPM);
5067 return 0;
5068 }
5069
5070 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5071 {
5072 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
5073
5074 fc_pushlevel(ctx, FC_LOOP);
5075
5076 /* check stack depth */
5077 callstack_check_depth(ctx, FC_LOOP, 0);
5078 return 0;
5079 }
5080
5081 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5082 {
5083 int i;
5084
5085 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
5086
5087 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5088 R600_ERR("loop/endloop in shader code are not paired.\n");
5089 return -EINVAL;
5090 }
5091
5092 /* fixup loop pointers - from r600isa
5093 LOOP END points to CF after LOOP START,
5094 LOOP START point to CF after LOOP END
5095 BRK/CONT point to LOOP END CF
5096 */
5097 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5098
5099 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5100
5101 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5102 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5103 }
5104 /* XXX add LOOPRET support */
5105 fc_poplevel(ctx);
5106 callstack_decrease_current(ctx, FC_LOOP);
5107 return 0;
5108 }
5109
5110 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5111 {
5112 unsigned int fscp;
5113
5114 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5115 {
5116 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5117 break;
5118 }
5119
5120 if (fscp == 0) {
5121 R600_ERR("Break not inside loop/endloop pair\n");
5122 return -EINVAL;
5123 }
5124
5125 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
5126
5127 fc_set_mid(ctx, fscp);
5128
5129 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
5130 return 0;
5131 }
5132
5133 static int tgsi_umad(struct r600_shader_ctx *ctx)
5134 {
5135 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5136 struct r600_bytecode_alu alu;
5137 int i, j, r;
5138 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5139
5140 /* src0 * src1 */
5141 for (i = 0; i < lasti + 1; i++) {
5142 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5143 continue;
5144
5145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5146
5147 alu.dst.chan = i;
5148 alu.dst.sel = ctx->temp_reg;
5149 alu.dst.write = 1;
5150
5151 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
5152 for (j = 0; j < 2; j++) {
5153 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5154 }
5155
5156 alu.last = 1;
5157 r = r600_bytecode_add_alu(ctx->bc, &alu);
5158 if (r)
5159 return r;
5160 }
5161
5162
5163 for (i = 0; i < lasti + 1; i++) {
5164 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5165 continue;
5166
5167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5168 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5169
5170 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
5171
5172 alu.src[0].sel = ctx->temp_reg;
5173 alu.src[0].chan = i;
5174
5175 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5176 if (i == lasti) {
5177 alu.last = 1;
5178 }
5179 r = r600_bytecode_add_alu(ctx->bc, &alu);
5180 if (r)
5181 return r;
5182 }
5183 return 0;
5184 }
5185
5186 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5187 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
5188 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5189 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
5190
5191 /* XXX:
5192 * For state trackers other than OpenGL, we'll want to use
5193 * _RECIP_IEEE instead.
5194 */
5195 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5196
5197 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
5198 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
5199 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
5200 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
5201 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5202 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5203 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5204 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
5205 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
5206 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
5207 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
5208 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
5209 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
5210 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5211 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
5212 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5213 /* gap */
5214 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5215 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5216 /* gap */
5217 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5218 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5219 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
5220 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5221 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
5222 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
5223 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
5224 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
5225 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
5226 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
5227 /* gap */
5228 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5229 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5230 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5231 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5232 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
5233 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5234 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
5235 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
5236 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5237 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5238 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5239 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5240 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5241 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
5242 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5243 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
5244 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
5245 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
5246 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
5247 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5248 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5249 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
5250 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5251 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5252 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5253 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5254 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5255 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5256 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5257 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
5258 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5259 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5260 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5261 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
5262 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
5263 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
5264 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
5265 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5266 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5267 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5268 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
5269 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
5270 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
5271 /* gap */
5272 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5273 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5274 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
5275 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
5276 /* gap */
5277 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5278 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5279 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5280 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5281 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
5282 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
5283 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
5284 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
5285 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2_trans},
5286 /* gap */
5287 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5288 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
5289 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
5290 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
5291 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
5292 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5293 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
5294 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
5295 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
5296 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5297 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5298 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
5299 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5300 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
5301 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5302 /* gap */
5303 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5304 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5305 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5306 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5307 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5308 /* gap */
5309 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5310 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5311 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5312 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5313 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5314 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5315 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5316 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5317 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
5318 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
5319 /* gap */
5320 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5321 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2_trans},
5322 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
5323 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
5324 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
5325 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
5326 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
5327 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2_trans},
5328 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
5329 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
5330 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
5331 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
5332 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
5333 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
5334 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
5335 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
5336 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
5337 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
5338 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
5339 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
5340 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2_trans},
5341 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
5342 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2_swap},
5343 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5344 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5345 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5346 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5347 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5348 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5349 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5350 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5351 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5352 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5353 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5354 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5355 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5356 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5357 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5358 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5359 {TGSI_OPCODE_UARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
5360 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
5361 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5362 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5363 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5364 };
5365
5366 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5367 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5368 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5369 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
5370 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
5371 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_rsq},
5372 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
5373 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
5374 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
5375 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5376 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5377 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5378 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
5379 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
5380 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
5381 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
5382 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
5383 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
5384 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5385 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
5386 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5387 /* gap */
5388 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5389 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5390 /* gap */
5391 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5392 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5393 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
5394 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5395 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
5396 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
5397 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
5398 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
5399 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
5400 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
5401 /* gap */
5402 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5403 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5404 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5405 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5406 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
5407 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5408 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
5409 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
5410 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5411 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5412 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5413 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5414 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5415 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
5416 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5417 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
5418 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
5419 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
5420 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
5421 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5422 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5423 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
5424 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5425 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5426 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5427 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5428 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5429 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5430 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5431 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5432 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5433 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5434 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5435 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
5436 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
5437 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
5438 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
5439 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5440 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5441 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5442 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
5443 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
5444 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
5445 /* gap */
5446 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5447 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5448 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
5449 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
5450 /* gap */
5451 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5452 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5453 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5454 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5455 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
5456 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
5457 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
5458 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
5459 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
5460 /* gap */
5461 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5462 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
5463 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
5464 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
5465 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
5466 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5467 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
5468 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
5469 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
5470 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5471 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5472 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
5473 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5474 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
5475 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5476 /* gap */
5477 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5478 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5479 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5480 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5481 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5482 /* gap */
5483 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5484 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5485 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5486 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5487 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5488 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5489 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5490 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5491 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
5492 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
5493 /* gap */
5494 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5495 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_f2i},
5496 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
5497 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
5498 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
5499 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
5500 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
5501 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
5502 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
5503 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_f2i},
5504 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
5505 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
5506 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
5507 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
5508 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
5509 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
5510 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
5511 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
5512 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
5513 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
5514 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
5515 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
5516 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
5517 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5518 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5519 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5520 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5521 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5522 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5523 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5524 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5525 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5526 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5527 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5528 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5529 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5530 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5531 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5532 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5533 {TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
5534 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
5535 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5536 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5537 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5538 };
5539
5540 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
5541 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5542 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5543 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
5544 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, cayman_emit_float_instr},
5545 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, cayman_emit_float_instr},
5546 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
5547 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
5548 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
5549 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5550 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5551 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5552 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
5553 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
5554 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
5555 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
5556 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
5557 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
5558 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5559 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
5560 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5561 /* gap */
5562 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5563 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5564 /* gap */
5565 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5566 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5567 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
5568 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5569 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
5570 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
5571 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, cayman_emit_float_instr},
5572 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, cayman_emit_float_instr},
5573 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, cayman_pow},
5574 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
5575 /* gap */
5576 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5577 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5578 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5579 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5580 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, cayman_trig},
5581 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5582 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
5583 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
5584 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5585 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5586 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5587 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5588 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5589 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
5590 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5591 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
5592 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, cayman_trig},
5593 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
5594 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
5595 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5596 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5597 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
5598 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5599 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5600 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5601 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5602 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5603 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5604 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5605 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5606 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5607 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5608 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5609 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
5610 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
5611 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
5612 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
5613 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5614 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5615 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5616 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
5617 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
5618 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
5619 /* gap */
5620 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5621 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5622 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
5623 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
5624 /* gap */
5625 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5626 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5627 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5628 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5629 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
5630 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2},
5631 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
5632 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
5633 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
5634 /* gap */
5635 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5636 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
5637 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
5638 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
5639 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
5640 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5641 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
5642 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
5643 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
5644 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5645 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5646 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
5647 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5648 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
5649 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5650 /* gap */
5651 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5652 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5653 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5654 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5655 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5656 /* gap */
5657 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5658 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5659 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5660 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5661 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5662 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5663 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5664 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5665 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
5666 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
5667 /* gap */
5668 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5669 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
5670 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
5671 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
5672 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
5673 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
5674 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
5675 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
5676 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
5677 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
5678 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
5679 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
5680 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
5681 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
5682 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
5683 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
5684 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
5685 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT, cayman_mul_int_instr},
5686 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
5687 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
5688 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
5689 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
5690 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
5691 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5692 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5693 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5694 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5695 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5696 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5697 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5698 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5699 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5700 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5701 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5702 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5703 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5704 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5705 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5706 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5707 {TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
5708 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
5709 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5710 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5711 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5712 };