2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
38 struct r600_shader_tgsi_instruction
;
40 struct r600_shader_ctx
{
41 struct tgsi_shader_info info
;
42 struct tgsi_parse_context parse
;
43 const struct tgsi_token
*tokens
;
45 unsigned file_offset
[TGSI_FILE_COUNT
];
47 struct r600_shader_tgsi_instruction
*inst_info
;
49 struct r600_shader
*shader
;
53 struct r600_shader_tgsi_instruction
{
57 int (*process
)(struct r600_shader_ctx
*ctx
);
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[];
61 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
63 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_shader
*shader
)
65 struct r600_context
*rctx
= r600_context(ctx
);
66 const struct util_format_description
*desc
;
67 enum pipe_format resource_format
[160];
68 unsigned i
, nresources
= 0;
69 struct r600_bc
*bc
= &shader
->bc
;
70 struct r600_bc_cf
*cf
;
71 struct r600_bc_vtx
*vtx
;
73 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
75 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
76 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
78 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
82 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
83 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
85 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
88 vtx
->dst_sel_x
= desc
->swizzle
[0];
89 vtx
->dst_sel_y
= desc
->swizzle
[1];
90 vtx
->dst_sel_z
= desc
->swizzle
[2];
91 vtx
->dst_sel_w
= desc
->swizzle
[3];
98 return r600_bc_build(&shader
->bc
);
101 int r600_pipe_shader_create(struct pipe_context
*ctx
,
102 struct r600_context_state
*rpshader
,
103 const struct tgsi_token
*tokens
)
105 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
108 fprintf(stderr
, "--------------------------------------------------------------\n");
109 tgsi_dump(tokens
, 0);
110 if (rpshader
== NULL
)
112 rpshader
->shader
.family
= radeon_get_family(rscreen
->rw
);
113 r
= r600_shader_from_tgsi(tokens
, &rpshader
->shader
);
115 R600_ERR("translation from TGSI failed !\n");
118 r
= r600_bc_build(&rpshader
->shader
.bc
);
120 R600_ERR("building bytecode failed !\n");
123 fprintf(stderr
, "______________________________________________________________\n");
127 static int r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
129 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
130 struct r600_shader
*rshader
= &rpshader
->shader
;
131 struct radeon_state
*state
;
134 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
135 state
= radeon_state(rscreen
->rw
, R600_VS_SHADER_TYPE
, R600_VS_SHADER
);
138 for (i
= 0; i
< 10; i
++) {
139 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
141 /* so far never got proper semantic id from tgsi */
142 for (i
= 0; i
< 32; i
++) {
143 tmp
= i
<< ((i
& 3) * 8);
144 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
146 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] = S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
147 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
148 rpshader
->rstate
= state
;
149 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
150 rpshader
->rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
151 rpshader
->rstate
->nbo
= 2;
152 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
153 return radeon_state_pm4(state
);
156 static int r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
158 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
159 struct r600_shader
*rshader
= &rpshader
->shader
;
160 struct radeon_state
*state
;
163 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
164 state
= radeon_state(rscreen
->rw
, R600_PS_SHADER_TYPE
, R600_PS_SHADER
);
167 for (i
= 0; i
< rshader
->ninput
; i
++) {
168 tmp
= S_028644_SEMANTIC(i
);
169 tmp
|= S_028644_SEL_CENTROID(1);
170 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
171 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
) {
172 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
174 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
176 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = S_0286CC_NUM_INTERP(rshader
->ninput
) |
177 S_0286CC_PERSP_GRADIENT_ENA(1);
178 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] = 0x00000000;
179 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
180 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = 0x00000002;
181 rpshader
->rstate
= state
;
182 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
183 rpshader
->rstate
->nbo
= 1;
184 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
185 return radeon_state_pm4(state
);
188 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
190 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
191 struct r600_context
*rctx
= r600_context(ctx
);
192 struct r600_shader
*rshader
= &rpshader
->shader
;
195 /* copy new shader */
196 radeon_bo_decref(rscreen
->rw
, rpshader
->bo
);
198 rpshader
->bo
= radeon_bo(rscreen
->rw
, 0, rshader
->bc
.ndw
* 4,
200 if (rpshader
->bo
== NULL
) {
203 radeon_bo_map(rscreen
->rw
, rpshader
->bo
);
204 memcpy(rpshader
->bo
->data
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
205 radeon_bo_unmap(rscreen
->rw
, rpshader
->bo
);
207 rshader
->flat_shade
= rctx
->flat_shade
;
208 switch (rshader
->processor_type
) {
209 case TGSI_PROCESSOR_VERTEX
:
210 r
= r600_pipe_shader_vs(ctx
, rpshader
);
212 case TGSI_PROCESSOR_FRAGMENT
:
213 r
= r600_pipe_shader_ps(ctx
, rpshader
);
222 int r600_pipe_shader_update(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
224 struct r600_context
*rctx
= r600_context(ctx
);
227 if (rpshader
== NULL
)
229 /* there should be enough input */
230 if (rctx
->vertex_elements
->count
< rpshader
->shader
.bc
.nresource
) {
231 R600_ERR("%d resources provided, expecting %d\n",
232 rctx
->vertex_elements
->count
, rpshader
->shader
.bc
.nresource
);
235 r
= r600_shader_update(ctx
, &rpshader
->shader
);
238 return r600_pipe_shader(ctx
, rpshader
);
241 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
243 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
246 if (i
->Instruction
.NumDstRegs
> 1) {
247 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
250 if (i
->Instruction
.Predicate
) {
251 R600_ERR("predicate unsupported\n");
254 if (i
->Instruction
.Label
) {
255 R600_ERR("label unsupported\n");
258 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
259 if (i
->Src
[j
].Register
.Indirect
||
260 i
->Src
[j
].Register
.Dimension
||
261 i
->Src
[j
].Register
.Absolute
) {
262 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
266 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
267 if (i
->Dst
[j
].Register
.Indirect
|| i
->Dst
[j
].Register
.Dimension
) {
268 R600_ERR("unsupported dst (indirect|dimension)\n");
275 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
277 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
278 struct r600_bc_vtx vtx
;
282 switch (d
->Declaration
.File
) {
283 case TGSI_FILE_INPUT
:
284 i
= ctx
->shader
->ninput
++;
285 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
286 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
287 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
288 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
289 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
290 /* turn input into fetch */
291 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
295 /* register containing the index into the buffer */
298 vtx
.mega_fetch_count
= 0x1F;
299 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
304 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
309 case TGSI_FILE_OUTPUT
:
310 i
= ctx
->shader
->noutput
++;
311 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
312 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
313 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
314 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
316 case TGSI_FILE_CONSTANT
:
317 case TGSI_FILE_TEMPORARY
:
318 case TGSI_FILE_SAMPLER
:
321 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
327 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
329 struct tgsi_full_immediate
*immediate
;
330 struct r600_shader_ctx ctx
;
331 struct r600_bc_output output
;
335 ctx
.bc
= &shader
->bc
;
337 r
= r600_bc_init(ctx
.bc
, shader
->family
);
341 tgsi_scan_shader(tokens
, &ctx
.info
);
342 tgsi_parse_init(&ctx
.parse
, tokens
);
343 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
344 shader
->processor_type
= ctx
.type
;
346 /* register allocations */
347 /* Values [0,127] correspond to GPR[0..127].
348 * Values [256,511] correspond to cfile constants c[0..255].
349 * Other special values are shown in the list below.
350 * 248 SQ_ALU_SRC_0: special constant 0.0.
351 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
352 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
353 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
354 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
355 * 253 SQ_ALU_SRC_LITERAL: literal constant.
356 * 254 SQ_ALU_SRC_PV: previous vector result.
357 * 255 SQ_ALU_SRC_PS: previous scalar result.
359 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
360 ctx
.file_offset
[i
] = 0;
362 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
363 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
365 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
366 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
367 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
368 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
369 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
370 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
371 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
372 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
374 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
375 tgsi_parse_token(&ctx
.parse
);
376 switch (ctx
.parse
.FullToken
.Token
.Type
) {
377 case TGSI_TOKEN_TYPE_IMMEDIATE
:
378 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
379 ctx
.value
[0] = immediate
->u
[0].Uint
;
380 ctx
.value
[1] = immediate
->u
[1].Uint
;
381 ctx
.value
[2] = immediate
->u
[2].Uint
;
382 ctx
.value
[3] = immediate
->u
[3].Uint
;
384 case TGSI_TOKEN_TYPE_DECLARATION
:
385 r
= tgsi_declaration(&ctx
);
389 case TGSI_TOKEN_TYPE_INSTRUCTION
:
390 r
= tgsi_is_supported(&ctx
);
393 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
394 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
395 r
= ctx
.inst_info
->process(&ctx
);
398 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
403 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
409 for (i
= 0, pos0
= 0; i
< shader
->noutput
; i
++) {
410 memset(&output
, 0, sizeof(struct r600_bc_output
));
411 output
.gpr
= shader
->output
[i
].gpr
;
412 output
.elem_size
= 3;
413 output
.swizzle_x
= 0;
414 output
.swizzle_y
= 1;
415 output
.swizzle_z
= 2;
416 output
.swizzle_w
= 3;
418 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
419 output
.array_base
= i
- pos0
;
420 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
;
421 switch (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
422 case TGSI_PROCESSOR_VERTEX
:
423 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
424 output
.array_base
= 60;
425 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
426 /* position doesn't count in array_base */
430 case TGSI_PROCESSOR_FRAGMENT
:
431 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
432 output
.array_base
= 0;
433 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
435 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
441 R600_ERR("unsupported processor type %d\n", ctx
.type
);
445 if (i
== (shader
->noutput
- 1)) {
446 output
.end_of_program
= 1;
448 r
= r600_bc_add_output(ctx
.bc
, &output
);
452 tgsi_parse_free(&ctx
.parse
);
455 tgsi_parse_free(&ctx
.parse
);
459 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
461 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
465 static int tgsi_end(struct r600_shader_ctx
*ctx
)
470 static int tgsi_src(struct r600_shader_ctx
*ctx
,
471 const struct tgsi_full_src_register
*tgsi_src
,
472 struct r600_bc_alu_src
*r600_src
)
474 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
475 r600_src
->sel
= tgsi_src
->Register
.Index
;
476 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
479 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
483 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
484 const struct tgsi_full_dst_register
*tgsi_dst
,
486 struct r600_bc_alu_dst
*r600_dst
)
488 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
490 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
491 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
492 r600_dst
->chan
= swizzle
;
494 if (inst
->Instruction
.Saturate
) {
500 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
504 return tgsi_src
->Register
.SwizzleX
;
506 return tgsi_src
->Register
.SwizzleY
;
508 return tgsi_src
->Register
.SwizzleZ
;
510 return tgsi_src
->Register
.SwizzleW
;
516 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
518 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
519 struct r600_bc_alu alu
;
520 int i
, j
, k
, nconst
, r
;
522 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
523 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
526 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
531 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
532 if (inst
->Src
[j
].Register
.File
== TGSI_FILE_CONSTANT
&& j
> 0) {
533 for (k
= 0; k
< 4; k
++) {
534 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
535 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
536 alu
.src
[0].sel
= r600_src
[0].sel
;
538 alu
.dst
.sel
= ctx
->temp_reg
+ j
;
543 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
547 r600_src
[0].sel
= ctx
->temp_reg
+ j
;
554 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
556 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
557 struct r600_bc_alu_src r600_src
[3];
558 struct r600_bc_alu alu
;
561 r
= tgsi_split_constant(ctx
, r600_src
);
564 for (i
= 0; i
< 4; i
++) {
565 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
566 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
567 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
570 alu
.inst
= ctx
->inst_info
->r600_opcode
;
571 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
572 alu
.src
[j
] = r600_src
[j
];
573 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
575 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
579 /* handle some special cases */
580 switch (ctx
->inst_info
->tgsi_opcode
) {
581 case TGSI_OPCODE_SUB
:
584 case TGSI_OPCODE_ABS
:
593 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
600 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
602 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
603 struct r600_bc_alu alu
;
606 for (i
= 0; i
< 4; i
++) {
607 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
608 alu
.inst
= ctx
->inst_info
->r600_opcode
;
610 alu
.src
[0].sel
= 248;
611 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
614 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
618 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
625 static int tgsi_slt(struct r600_shader_ctx
*ctx
)
627 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
628 struct r600_bc_alu_src r600_src
[3];
629 struct r600_bc_alu alu
;
632 r
= tgsi_split_constant(ctx
, r600_src
);
635 for (i
= 0; i
< 4; i
++) {
636 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
637 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
638 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
641 alu
.inst
= ctx
->inst_info
->r600_opcode
;
642 alu
.src
[1] = r600_src
[0];
643 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
644 alu
.src
[0] = r600_src
[1];
645 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
646 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
653 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
660 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
662 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
663 struct r600_bc_alu alu
;
667 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
668 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
669 alu
.src
[0].sel
= 249; /*1.0*/
671 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
674 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
675 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
679 /* dst.y = max(src.x, 0.0) */
680 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
681 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
;
682 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
685 alu
.src
[1].sel
= 248; /*0.0*/
686 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 0);
687 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
690 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
691 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
695 /* dst.z = NOP - fill Z slot */
696 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
697 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
699 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
704 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
705 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
706 alu
.src
[0].sel
= 249;
708 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
711 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
713 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
717 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
722 /* dst.z = log(src.y) */
723 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
724 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
;
725 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
728 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
729 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
733 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
740 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
741 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
742 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
743 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
746 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
747 alu
.src
[1].sel
= sel
;
748 alu
.src
[1].chan
= chan
;
749 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[2]);
752 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
753 alu
.dst
.sel
= ctx
->temp_reg
;
758 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
762 /* dst.z = exp(tmp.x) */
763 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
764 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
765 alu
.src
[0].sel
= ctx
->temp_reg
;
767 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
771 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
778 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
780 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
781 struct r600_bc_alu alu
;
784 for (i
= 0; i
< 4; i
++) {
785 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
786 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
787 alu
.inst
= ctx
->inst_info
->r600_opcode
;
788 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
789 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
792 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
794 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
798 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
806 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
808 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
809 struct r600_bc_alu alu
;
812 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
813 alu
.inst
= ctx
->inst_info
->r600_opcode
;
814 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
815 r
= tgsi_src(ctx
, &inst
->Src
[j
], &alu
.src
[j
]);
818 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], 0);
820 alu
.dst
.sel
= ctx
->temp_reg
;
823 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
826 /* replicate result */
827 for (i
= 0; i
< 4; i
++) {
828 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
829 alu
.src
[0].sel
= ctx
->temp_reg
;
830 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
832 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
835 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
838 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
845 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
847 struct r600_bc_alu alu
;
850 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
853 for (i
= 0; i
< 4; i
++) {
854 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
855 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
856 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
859 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
860 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
863 alu
.src
[0].sel
= ctx
->temp_reg
;
869 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
876 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
878 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
879 struct r600_bc_alu_src r600_src
[3];
880 struct r600_bc_alu alu
;
883 r
= tgsi_split_constant(ctx
, r600_src
);
886 /* do it in 2 step as op3 doesn't support writemask */
887 for (i
= 0; i
< 4; i
++) {
888 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
889 alu
.inst
= ctx
->inst_info
->r600_opcode
;
890 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
891 alu
.src
[j
] = r600_src
[j
];
892 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
894 alu
.dst
.sel
= ctx
->temp_reg
;
901 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
905 return tgsi_helper_copy(ctx
, inst
);
908 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
910 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
911 struct r600_bc_alu_src r600_src
[3];
912 struct r600_bc_alu alu
;
915 r
= tgsi_split_constant(ctx
, r600_src
);
918 for (i
= 0; i
< 4; i
++) {
919 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
920 alu
.inst
= ctx
->inst_info
->r600_opcode
;
921 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
922 alu
.src
[j
] = r600_src
[j
];
923 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
925 alu
.dst
.sel
= ctx
->temp_reg
;
928 /* handle some special cases */
929 switch (ctx
->inst_info
->tgsi_opcode
) {
930 case TGSI_OPCODE_DP2
:
932 alu
.src
[0].sel
= alu
.src
[1].sel
= 248;
933 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
936 case TGSI_OPCODE_DP3
:
938 alu
.src
[0].sel
= alu
.src
[1].sel
= 248;
939 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
948 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
952 return tgsi_helper_copy(ctx
, inst
);
955 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
957 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
958 struct r600_bc_tex tex
;
959 struct r600_bc_alu alu
;
963 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
965 /* Add perspective divide */
966 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_TXP
) {
967 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
968 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
969 alu
.src
[0].sel
= src_gpr
;
970 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
971 alu
.dst
.sel
= ctx
->temp_reg
;
975 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
979 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
980 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
981 alu
.src
[0].sel
= ctx
->temp_reg
;
983 alu
.src
[1].sel
= src_gpr
;
984 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 0);
985 alu
.dst
.sel
= ctx
->temp_reg
;
988 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
991 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
992 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
993 alu
.src
[0].sel
= ctx
->temp_reg
;
995 alu
.src
[1].sel
= src_gpr
;
996 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 1);
997 alu
.dst
.sel
= ctx
->temp_reg
;
1000 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1003 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1004 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1005 alu
.src
[0].sel
= ctx
->temp_reg
;
1006 alu
.src
[0].chan
= 3;
1007 alu
.src
[1].sel
= src_gpr
;
1008 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], 2);
1009 alu
.dst
.sel
= ctx
->temp_reg
;
1012 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1015 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1016 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
1017 alu
.src
[0].sel
= 249;
1018 alu
.src
[0].chan
= 0;
1019 alu
.dst
.sel
= ctx
->temp_reg
;
1023 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1026 src_gpr
= ctx
->temp_reg
;
1029 /* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
1030 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1031 tex
.inst
= ctx
->inst_info
->r600_opcode
;
1032 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1033 tex
.sampler_id
= tex
.resource_id
;
1034 tex
.src_gpr
= src_gpr
;
1035 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1044 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1045 tex
.coord_type_x
= 1;
1046 tex
.coord_type_y
= 1;
1047 tex
.coord_type_z
= 1;
1048 tex
.coord_type_w
= 1;
1050 return r600_bc_add_tex(ctx
->bc
, &tex
);
1053 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1055 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1056 struct r600_bc_alu_src r600_src
[3];
1057 struct r600_bc_alu alu
;
1061 r
= tgsi_split_constant(ctx
, r600_src
);
1065 for (i
= 0; i
< 4; i
++) {
1066 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1067 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
;
1068 alu
.src
[0].sel
= 249;
1069 alu
.src
[0].chan
= 0;
1070 alu
.src
[1] = r600_src
[0];
1071 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1073 alu
.dst
.sel
= ctx
->temp_reg
;
1079 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1083 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1087 /* (1 - src0) * src2 */
1088 for (i
= 0; i
< 4; i
++) {
1089 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1090 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
1091 alu
.src
[0].sel
= ctx
->temp_reg
;
1092 alu
.src
[0].chan
= i
;
1093 alu
.src
[1] = r600_src
[2];
1094 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1095 alu
.dst
.sel
= ctx
->temp_reg
;
1101 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1105 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1109 /* src0 * src1 + (1 - src0) * src2 */
1110 for (i
= 0; i
< 4; i
++) {
1111 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1112 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1114 alu
.src
[0] = r600_src
[0];
1115 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1116 alu
.src
[1] = r600_src
[1];
1117 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1118 alu
.src
[2].sel
= ctx
->temp_reg
;
1119 alu
.src
[2].chan
= i
;
1120 alu
.dst
.sel
= ctx
->temp_reg
;
1125 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1129 return tgsi_helper_copy(ctx
, inst
);
1132 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
1133 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1134 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1135 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
1136 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
1137 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
1138 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1139 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1140 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
1141 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1142 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1143 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1144 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1145 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1146 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
1147 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_slt
},
1148 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1149 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
1150 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1151 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
1152 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1154 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1155 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1157 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1158 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1159 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1160 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1161 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1162 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1163 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
1164 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1165 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1166 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1168 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1169 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1170 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1171 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1172 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1173 {TGSI_OPCODE_DDX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1174 {TGSI_OPCODE_DDY
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1175 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* predicated kill */
1176 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1177 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1178 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1179 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1180 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1181 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1182 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1183 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1184 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1185 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1186 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1187 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1188 {TGSI_OPCODE_TEX
, 0, 0x10, tgsi_tex
},
1189 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1190 {TGSI_OPCODE_TXP
, 0, 0x10, tgsi_tex
},
1191 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1192 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1193 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1194 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1195 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1196 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1197 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1198 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1199 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1200 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1201 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* SGN */
1202 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1203 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1204 {TGSI_OPCODE_TXB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1205 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1206 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1207 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1208 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1209 {TGSI_OPCODE_BRK
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1210 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1212 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1213 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1214 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1215 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1217 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1218 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1219 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1220 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1221 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1222 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1223 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1224 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1225 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1227 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1228 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1229 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1230 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1231 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1232 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1233 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1234 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1235 {TGSI_OPCODE_CONT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1236 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1237 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1238 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1239 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1240 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1241 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1243 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1244 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1245 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1246 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1247 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1249 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1250 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1251 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1252 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1253 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1254 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1255 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1256 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1257 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
1258 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
1260 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1261 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1262 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1263 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1264 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1265 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1266 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1267 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1268 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1269 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1270 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1271 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1272 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1273 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1274 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1275 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1276 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1277 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1278 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1279 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1280 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1281 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1282 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1283 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1284 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1285 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1286 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1287 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},