2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_screen.h"
29 #include "r600_context.h"
30 #include "r600_shader.h"
38 struct r600_shader_tgsi_instruction
;
40 struct r600_shader_ctx
{
41 struct tgsi_shader_info info
;
42 struct tgsi_parse_context parse
;
43 const struct tgsi_token
*tokens
;
45 unsigned file_offset
[TGSI_FILE_COUNT
];
47 struct r600_shader_tgsi_instruction
*inst_info
;
49 struct r600_shader
*shader
;
53 struct r600_shader_tgsi_instruction
{
57 int (*process
)(struct r600_shader_ctx
*ctx
);
60 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[];
61 static int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
);
63 static int r600_shader_update(struct pipe_context
*ctx
, struct r600_shader
*shader
)
65 struct r600_context
*rctx
= r600_context(ctx
);
66 const struct util_format_description
*desc
;
67 enum pipe_format resource_format
[160];
68 unsigned i
, nresources
= 0;
69 struct r600_bc
*bc
= &shader
->bc
;
70 struct r600_bc_cf
*cf
;
71 struct r600_bc_vtx
*vtx
;
73 if (shader
->processor_type
!= TGSI_PROCESSOR_VERTEX
)
75 for (i
= 0; i
< rctx
->vertex_elements
->count
; i
++) {
76 resource_format
[nresources
++] = rctx
->vertex_elements
->elements
[i
].src_format
;
78 LIST_FOR_EACH_ENTRY(cf
, &bc
->cf
, list
) {
80 case V_SQ_CF_WORD1_SQ_CF_INST_VTX
:
81 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC
:
82 LIST_FOR_EACH_ENTRY(vtx
, &cf
->vtx
, list
) {
83 desc
= util_format_description(resource_format
[vtx
->buffer_id
]);
85 R600_ERR("unknown format %d\n", resource_format
[vtx
->buffer_id
]);
88 vtx
->dst_sel_x
= desc
->swizzle
[0];
89 vtx
->dst_sel_y
= desc
->swizzle
[1];
90 vtx
->dst_sel_z
= desc
->swizzle
[2];
91 vtx
->dst_sel_w
= desc
->swizzle
[3];
98 return r600_bc_build(&shader
->bc
);
101 int r600_pipe_shader_create(struct pipe_context
*ctx
,
102 struct r600_context_state
*rpshader
,
103 const struct tgsi_token
*tokens
)
105 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
108 fprintf(stderr
, "--------------------------------------------------------------\n");
109 tgsi_dump(tokens
, 0);
110 if (rpshader
== NULL
)
112 rpshader
->shader
.family
= radeon_get_family(rscreen
->rw
);
113 r
= r600_shader_from_tgsi(tokens
, &rpshader
->shader
);
115 R600_ERR("translation from TGSI failed !\n");
118 r
= r600_bc_build(&rpshader
->shader
.bc
);
120 R600_ERR("building bytecode failed !\n");
123 fprintf(stderr
, "______________________________________________________________\n");
127 static int r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
129 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
130 struct r600_shader
*rshader
= &rpshader
->shader
;
131 struct radeon_state
*state
;
134 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
135 state
= radeon_state(rscreen
->rw
, R600_VS_SHADER_TYPE
, R600_VS_SHADER
);
138 for (i
= 0; i
< 10; i
++) {
139 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
] = 0;
141 /* so far never got proper semantic id from tgsi */
142 for (i
= 0; i
< 32; i
++) {
143 tmp
= i
<< ((i
& 3) * 8);
144 state
->states
[R600_VS_SHADER__SPI_VS_OUT_ID_0
+ i
/ 4] |= tmp
;
146 state
->states
[R600_VS_SHADER__SPI_VS_OUT_CONFIG
] = S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2);
147 state
->states
[R600_VS_SHADER__SQ_PGM_RESOURCES_VS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
148 rpshader
->rstate
= state
;
149 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
150 rpshader
->rstate
->bo
[1] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
151 rpshader
->rstate
->nbo
= 2;
152 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
153 return radeon_state_pm4(state
);
156 static int r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
158 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
159 struct r600_shader
*rshader
= &rpshader
->shader
;
160 struct radeon_state
*state
;
163 rpshader
->rstate
= radeon_state_decref(rpshader
->rstate
);
164 state
= radeon_state(rscreen
->rw
, R600_PS_SHADER_TYPE
, R600_PS_SHADER
);
167 for (i
= 0; i
< rshader
->ninput
; i
++) {
168 tmp
= S_028644_SEMANTIC(i
);
169 tmp
|= S_028644_SEL_CENTROID(1);
170 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
||
171 rshader
->input
[i
].name
== TGSI_SEMANTIC_BCOLOR
) {
172 tmp
|= S_028644_FLAT_SHADE(rshader
->flat_shade
);
174 state
->states
[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0
+ i
] = tmp
;
176 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_0
] = S_0286CC_NUM_INTERP(rshader
->ninput
) |
177 S_0286CC_PERSP_GRADIENT_ENA(1);
178 state
->states
[R600_PS_SHADER__SPI_PS_IN_CONTROL_1
] = 0x00000000;
179 state
->states
[R600_PS_SHADER__SQ_PGM_RESOURCES_PS
] = S_028868_NUM_GPRS(rshader
->bc
.ngpr
);
180 state
->states
[R600_PS_SHADER__SQ_PGM_EXPORTS_PS
] = 0x00000002;
181 rpshader
->rstate
= state
;
182 rpshader
->rstate
->bo
[0] = radeon_bo_incref(rscreen
->rw
, rpshader
->bo
);
183 rpshader
->rstate
->nbo
= 1;
184 rpshader
->rstate
->placement
[0] = RADEON_GEM_DOMAIN_GTT
;
185 return radeon_state_pm4(state
);
188 static int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
190 struct r600_screen
*rscreen
= r600_screen(ctx
->screen
);
191 struct r600_context
*rctx
= r600_context(ctx
);
192 struct r600_shader
*rshader
= &rpshader
->shader
;
195 /* copy new shader */
196 radeon_bo_decref(rscreen
->rw
, rpshader
->bo
);
198 rpshader
->bo
= radeon_bo(rscreen
->rw
, 0, rshader
->bc
.ndw
* 4,
200 if (rpshader
->bo
== NULL
) {
203 radeon_bo_map(rscreen
->rw
, rpshader
->bo
);
204 memcpy(rpshader
->bo
->data
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
205 radeon_bo_unmap(rscreen
->rw
, rpshader
->bo
);
207 rshader
->flat_shade
= rctx
->flat_shade
;
208 switch (rshader
->processor_type
) {
209 case TGSI_PROCESSOR_VERTEX
:
210 r
= r600_pipe_shader_vs(ctx
, rpshader
);
212 case TGSI_PROCESSOR_FRAGMENT
:
213 r
= r600_pipe_shader_ps(ctx
, rpshader
);
222 int r600_pipe_shader_update(struct pipe_context
*ctx
, struct r600_context_state
*rpshader
)
224 struct r600_context
*rctx
= r600_context(ctx
);
227 if (rpshader
== NULL
)
229 /* there should be enough input */
230 if (rctx
->vertex_elements
->count
< rpshader
->shader
.bc
.nresource
) {
231 R600_ERR("%d resources provided, expecting %d\n",
232 rctx
->vertex_elements
->count
, rpshader
->shader
.bc
.nresource
);
235 r
= r600_shader_update(ctx
, &rpshader
->shader
);
238 return r600_pipe_shader(ctx
, rpshader
);
241 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
243 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
246 if (i
->Instruction
.NumDstRegs
> 1) {
247 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
250 if (i
->Instruction
.Predicate
) {
251 R600_ERR("predicate unsupported\n");
254 if (i
->Instruction
.Label
) {
255 R600_ERR("label unsupported\n");
258 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
259 if (i
->Src
[j
].Register
.Indirect
||
260 i
->Src
[j
].Register
.Dimension
||
261 i
->Src
[j
].Register
.Absolute
) {
262 R600_ERR("unsupported src (indirect|dimension|absolute)\n");
266 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
267 if (i
->Dst
[j
].Register
.Indirect
|| i
->Dst
[j
].Register
.Dimension
) {
268 R600_ERR("unsupported dst (indirect|dimension)\n");
275 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
277 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
278 struct r600_bc_vtx vtx
;
282 switch (d
->Declaration
.File
) {
283 case TGSI_FILE_INPUT
:
284 i
= ctx
->shader
->ninput
++;
285 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
286 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
287 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
288 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
289 if (ctx
->type
== TGSI_PROCESSOR_VERTEX
) {
290 /* turn input into fetch */
291 memset(&vtx
, 0, sizeof(struct r600_bc_vtx
));
295 /* register containing the index into the buffer */
298 vtx
.mega_fetch_count
= 0x1F;
299 vtx
.dst_gpr
= ctx
->shader
->input
[i
].gpr
;
304 r
= r600_bc_add_vtx(ctx
->bc
, &vtx
);
309 case TGSI_FILE_OUTPUT
:
310 i
= ctx
->shader
->noutput
++;
311 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
312 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
313 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
314 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
316 case TGSI_FILE_CONSTANT
:
317 case TGSI_FILE_TEMPORARY
:
318 case TGSI_FILE_SAMPLER
:
321 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
327 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
)
329 struct tgsi_full_immediate
*immediate
;
330 struct r600_shader_ctx ctx
;
331 struct r600_bc_output output
;
335 ctx
.bc
= &shader
->bc
;
337 r
= r600_bc_init(ctx
.bc
, shader
->family
);
341 tgsi_scan_shader(tokens
, &ctx
.info
);
342 tgsi_parse_init(&ctx
.parse
, tokens
);
343 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
344 shader
->processor_type
= ctx
.type
;
346 /* register allocations */
347 /* Values [0,127] correspond to GPR[0..127].
348 * Values [256,511] correspond to cfile constants c[0..255].
349 * Other special values are shown in the list below.
350 * 248 SQ_ALU_SRC_0: special constant 0.0.
351 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
352 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
353 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
354 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
355 * 253 SQ_ALU_SRC_LITERAL: literal constant.
356 * 254 SQ_ALU_SRC_PV: previous vector result.
357 * 255 SQ_ALU_SRC_PS: previous scalar result.
359 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
360 ctx
.file_offset
[i
] = 0;
362 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
363 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
365 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
366 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
367 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
368 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
369 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 256;
370 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = 253;
371 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
372 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
374 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
375 tgsi_parse_token(&ctx
.parse
);
376 switch (ctx
.parse
.FullToken
.Token
.Type
) {
377 case TGSI_TOKEN_TYPE_IMMEDIATE
:
378 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
379 ctx
.value
[0] = immediate
->u
[0].Uint
;
380 ctx
.value
[1] = immediate
->u
[1].Uint
;
381 ctx
.value
[2] = immediate
->u
[2].Uint
;
382 ctx
.value
[3] = immediate
->u
[3].Uint
;
384 case TGSI_TOKEN_TYPE_DECLARATION
:
385 r
= tgsi_declaration(&ctx
);
389 case TGSI_TOKEN_TYPE_INSTRUCTION
:
390 r
= tgsi_is_supported(&ctx
);
393 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
394 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
395 r
= ctx
.inst_info
->process(&ctx
);
398 r
= r600_bc_add_literal(ctx
.bc
, ctx
.value
);
403 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
409 for (i
= 0, pos0
= 0; i
< shader
->noutput
; i
++) {
410 memset(&output
, 0, sizeof(struct r600_bc_output
));
411 output
.gpr
= shader
->output
[i
].gpr
;
412 output
.elem_size
= 3;
413 output
.swizzle_x
= 0;
414 output
.swizzle_y
= 1;
415 output
.swizzle_z
= 2;
416 output
.swizzle_w
= 3;
418 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
419 output
.array_base
= i
- pos0
;
420 output
.inst
= V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE
;
421 switch (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
422 case TGSI_PROCESSOR_VERTEX
:
423 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
424 output
.array_base
= 60;
425 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
426 /* position doesn't count in array_base */
430 case TGSI_PROCESSOR_FRAGMENT
:
431 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
432 output
.array_base
= 0;
433 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
435 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
441 R600_ERR("unsupported processor type %d\n", ctx
.type
);
445 if (i
== (shader
->noutput
- 1)) {
446 output
.end_of_program
= 1;
448 r
= r600_bc_add_output(ctx
.bc
, &output
);
452 tgsi_parse_free(&ctx
.parse
);
455 tgsi_parse_free(&ctx
.parse
);
459 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
461 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
465 static int tgsi_end(struct r600_shader_ctx
*ctx
)
470 static int tgsi_src(struct r600_shader_ctx
*ctx
,
471 const struct tgsi_full_src_register
*tgsi_src
,
473 struct r600_bc_alu_src
*r600_src
)
475 r600_src
->sel
= tgsi_src
->Register
.Index
;
476 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
479 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
482 r600_src
->chan
= tgsi_src
->Register
.SwizzleX
;
485 r600_src
->chan
= tgsi_src
->Register
.SwizzleY
;
488 r600_src
->chan
= tgsi_src
->Register
.SwizzleZ
;
491 r600_src
->chan
= tgsi_src
->Register
.SwizzleW
;
499 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
500 const struct tgsi_full_dst_register
*tgsi_dst
,
502 struct r600_bc_alu_dst
*r600_dst
)
504 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
506 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
507 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
508 r600_dst
->chan
= swizzle
;
510 if (inst
->Instruction
.Saturate
) {
516 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
518 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
519 struct r600_bc_alu alu
;
522 for (i
= 0; i
< 4; i
++) {
523 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
524 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
525 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
528 alu
.inst
= ctx
->inst_info
->r600_opcode
;
529 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
530 r
= tgsi_src(ctx
, &inst
->Src
[j
], i
, &alu
.src
[j
]);
534 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
538 /* handle some special cases */
539 switch (ctx
->inst_info
->tgsi_opcode
) {
540 case TGSI_OPCODE_SUB
:
543 case TGSI_OPCODE_ABS
:
552 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
559 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
561 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
562 struct r600_bc_alu alu
;
565 for (i
= 0; i
< 4; i
++) {
566 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
567 alu
.inst
= ctx
->inst_info
->r600_opcode
;
569 alu
.src
[0].sel
= 248;
570 r
= tgsi_src(ctx
, &inst
->Src
[0], i
, &alu
.src
[1]);
576 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
583 static int tgsi_slt(struct r600_shader_ctx
*ctx
)
585 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
586 struct r600_bc_alu alu
;
589 for (i
= 0; i
< 4; i
++) {
590 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
591 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
592 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
595 alu
.inst
= ctx
->inst_info
->r600_opcode
;
596 r
= tgsi_src(ctx
, &inst
->Src
[0], i
, &alu
.src
[1]);
599 r
= tgsi_src(ctx
, &inst
->Src
[1], i
, &alu
.src
[0]);
602 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
609 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
616 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
618 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
619 struct r600_bc_alu alu
;
622 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 0))
625 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
626 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
627 alu
.src
[0].sel
= 249; /*1.0*/
629 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
632 if ((inst
->Dst
[0].Register
.WriteMask
& 0xe) == 0)
634 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
640 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 1))
642 /* dst.y = max(src.x, 0.0) */
643 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
644 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
;
645 r
= tgsi_src(ctx
, &inst
->Src
[0], 0, &alu
.src
[0]);
648 alu
.src
[1].sel
= 248; /*0.0*/
650 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
653 if ((inst
->Dst
[0].Register
.WriteMask
& 0xa) == 0)
655 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
660 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 3))
663 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
664 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
665 alu
.src
[0].sel
= 249;
667 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
670 if ((inst
->Dst
[0].Register
.WriteMask
& 0x4) == 0)
672 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
677 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
682 /* dst.z = log(src.y) */
683 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
684 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
;
685 r
= tgsi_src(ctx
, &inst
->Src
[0], 1, &alu
.src
[0]);
688 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
692 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
699 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
700 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
701 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
;
702 r
= tgsi_src(ctx
, &inst
->Src
[0], 3, &alu
.src
[0]);
705 alu
.src
[1].sel
= sel
;
706 alu
.src
[1].chan
= chan
;
707 r
= tgsi_src(ctx
, &inst
->Src
[0], 0, &alu
.src
[2]);
710 alu
.dst
.sel
= ctx
->temp_reg
;
715 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
719 /* dst.z = exp(tmp.x) */
720 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
721 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
;
722 alu
.src
[0].sel
= ctx
->temp_reg
;
724 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
728 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
735 static int tgsi_trans(struct r600_shader_ctx
*ctx
)
737 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
738 struct r600_bc_alu alu
;
741 for (i
= 0; i
< 4; i
++) {
742 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
743 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
744 alu
.inst
= ctx
->inst_info
->r600_opcode
;
745 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
746 r
= tgsi_src(ctx
, &inst
->Src
[j
], i
, &alu
.src
[j
]);
750 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
754 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
762 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
764 struct r600_bc_alu alu
;
767 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
770 for (i
= 0; i
< 4; i
++) {
771 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
772 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
773 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
;
776 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
777 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
780 alu
.src
[0].sel
= ctx
->temp_reg
;
786 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
793 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
795 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
796 struct r600_bc_alu alu
;
799 /* do it in 2 step as op3 doesn't support writemask */
800 for (i
= 0; i
< 4; i
++) {
801 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
802 alu
.inst
= ctx
->inst_info
->r600_opcode
;
803 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
804 r
= tgsi_src(ctx
, &inst
->Src
[j
], i
, &alu
.src
[j
]);
808 alu
.dst
.sel
= ctx
->temp_reg
;
815 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
819 return tgsi_helper_copy(ctx
, inst
);
822 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
824 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
825 struct r600_bc_alu alu
;
828 for (i
= 0; i
< 4; i
++) {
829 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
830 alu
.inst
= ctx
->inst_info
->r600_opcode
;
831 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
832 r
= tgsi_src(ctx
, &inst
->Src
[j
], i
, &alu
.src
[j
]);
836 alu
.dst
.sel
= ctx
->temp_reg
;
839 /* handle some special cases */
840 switch (ctx
->inst_info
->tgsi_opcode
) {
841 case TGSI_OPCODE_DP2
:
843 alu
.src
[0].sel
= alu
.src
[1].sel
= 248;
844 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
847 case TGSI_OPCODE_DP3
:
849 alu
.src
[0].sel
= alu
.src
[1].sel
= 248;
850 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
859 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
863 return tgsi_helper_copy(ctx
, inst
);
866 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
868 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
869 struct r600_bc_tex tex
;
870 struct r600_bc_alu alu
;
874 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
876 /* Add perspective divide */
877 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_TXP
) {
878 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
879 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
;
880 alu
.src
[0].sel
= src_gpr
;
882 alu
.dst
.sel
= ctx
->temp_reg
;
886 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
890 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
891 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
892 alu
.src
[0].sel
= ctx
->temp_reg
;
894 alu
.src
[1].sel
= src_gpr
;
896 alu
.dst
.sel
= ctx
->temp_reg
;
899 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
902 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
903 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
904 alu
.src
[0].sel
= ctx
->temp_reg
;
906 alu
.src
[1].sel
= src_gpr
;
908 alu
.dst
.sel
= ctx
->temp_reg
;
911 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
914 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
915 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
916 alu
.src
[0].sel
= ctx
->temp_reg
;
918 alu
.src
[1].sel
= src_gpr
;
920 alu
.dst
.sel
= ctx
->temp_reg
;
923 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
926 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
927 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
;
928 alu
.src
[0].sel
= 249;
930 alu
.dst
.sel
= ctx
->temp_reg
;
934 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
937 src_gpr
= ctx
->temp_reg
;
940 /* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
941 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
942 tex
.inst
= ctx
->inst_info
->r600_opcode
;
943 tex
.resource_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
944 tex
.sampler_id
= tex
.resource_id
;
945 tex
.src_gpr
= src_gpr
;
946 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
955 tex
.coord_type_x
= 1;
956 tex
.coord_type_y
= 1;
957 tex
.coord_type_z
= 1;
958 tex
.coord_type_w
= 1;
959 return r600_bc_add_tex(ctx
->bc
, &tex
);
962 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
964 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
965 struct r600_bc_alu alu
;
970 for (i
= 0; i
< 4; i
++) {
971 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
972 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
;
973 alu
.src
[0].sel
= 249;
975 r
= tgsi_src(ctx
, &inst
->Src
[0], i
, &alu
.src
[1]);
979 alu
.dst
.sel
= ctx
->temp_reg
;
985 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
989 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
993 /* (1 - src0) * src2 */
994 for (i
= 0; i
< 4; i
++) {
995 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
996 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
;
997 alu
.src
[0].sel
= ctx
->temp_reg
;
999 r
= tgsi_src(ctx
, &inst
->Src
[2], i
, &alu
.src
[1]);
1002 alu
.dst
.sel
= ctx
->temp_reg
;
1008 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1012 r
= r600_bc_add_literal(ctx
->bc
, ctx
->value
);
1016 /* src0 * src1 + (1 - src0) * src2 */
1017 for (i
= 0; i
< 4; i
++) {
1018 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1019 alu
.inst
= V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
;
1021 r
= tgsi_src(ctx
, &inst
->Src
[0], i
, &alu
.src
[0]);
1024 r
= tgsi_src(ctx
, &inst
->Src
[1], i
, &alu
.src
[1]);
1027 alu
.src
[2].sel
= ctx
->temp_reg
;
1028 alu
.src
[2].chan
= i
;
1029 alu
.dst
.sel
= ctx
->temp_reg
;
1034 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1038 return tgsi_helper_copy(ctx
, inst
);
1041 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
1042 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1043 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1044 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
1045 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1046 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans
},
1047 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1048 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1049 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
1050 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1051 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1052 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1053 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1054 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1055 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
1056 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_slt
},
1057 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1058 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
1059 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
1060 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
1061 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1063 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1064 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1066 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1067 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1068 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1069 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1070 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1071 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1072 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans
},
1073 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1074 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1075 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1077 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1078 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
1079 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1080 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1081 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1082 {TGSI_OPCODE_DDX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1083 {TGSI_OPCODE_DDY
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1084 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* predicated kill */
1085 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1086 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1087 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1088 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1089 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1090 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1091 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1092 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1093 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1094 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1095 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1096 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1097 {TGSI_OPCODE_TEX
, 0, 0x10, tgsi_tex
},
1098 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1099 {TGSI_OPCODE_TXP
, 0, 0x10, tgsi_tex
},
1100 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1101 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1102 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1103 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1104 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1105 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1106 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1107 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1108 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1109 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1110 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
}, /* SGN */
1111 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1112 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1113 {TGSI_OPCODE_TXB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1114 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1115 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1116 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
1117 {TGSI_OPCODE_TXL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1118 {TGSI_OPCODE_BRK
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1119 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1121 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1122 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1123 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1124 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1126 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1127 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1128 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1129 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1130 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1131 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1132 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1133 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1134 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1136 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1137 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1138 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1139 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1140 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1141 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1142 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1143 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1144 {TGSI_OPCODE_CONT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1145 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1146 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1147 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1148 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1149 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1150 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1152 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1153 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1154 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1155 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1156 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1158 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1159 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1160 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1161 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1162 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1163 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1164 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1165 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1166 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
1167 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
1169 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1170 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1171 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1172 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1173 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1174 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1175 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1176 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1177 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1178 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1179 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1180 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1181 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1182 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1183 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1184 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1185 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1186 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1187 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1188 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1189 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1190 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1191 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1192 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1193 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1194 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1195 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
1196 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},