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gallium/u_blitter: make clearing independent of the number of bound colorbuffers
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include <stdio.h>
39 #include <errno.h>
40 #include <byteswap.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
88 {
89 struct tgsi_parse_context parse;
90
91 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
92 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
93 return ~0;
94 }
95 return parse.FullHeader.Processor.Processor;
96 }
97
98 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
99 {
100 switch (processor_type) {
101 case TGSI_PROCESSOR_VERTEX:
102 return (rscreen->debug_flags & DBG_VS) != 0;
103 case TGSI_PROCESSOR_GEOMETRY:
104 return (rscreen->debug_flags & DBG_GS) != 0;
105 case TGSI_PROCESSOR_FRAGMENT:
106 return (rscreen->debug_flags & DBG_PS) != 0;
107 case TGSI_PROCESSOR_COMPUTE:
108 return (rscreen->debug_flags & DBG_CS) != 0;
109 default:
110 return false;
111 }
112 }
113
114 static void r600_dump_streamout(struct pipe_stream_output_info *so)
115 {
116 unsigned i;
117
118 fprintf(stderr, "STREAMOUT\n");
119 for (i = 0; i < so->num_outputs; i++) {
120 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
121 so->output[i].start_component;
122 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
123 i, so->output[i].output_buffer,
124 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
125 so->output[i].register_index,
126 mask & 1 ? "x" : "",
127 mask & 2 ? "y" : "",
128 mask & 4 ? "z" : "",
129 mask & 8 ? "w" : "",
130 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
131 }
132 }
133
134 int r600_pipe_shader_create(struct pipe_context *ctx,
135 struct r600_pipe_shader *shader,
136 struct r600_shader_key key)
137 {
138 struct r600_context *rctx = (struct r600_context *)ctx;
139 struct r600_pipe_shader_selector *sel = shader->selector;
140 int r, i;
141 uint32_t *ptr;
142 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
143 unsigned use_sb = rctx->screen->debug_flags & DBG_SB;
144 unsigned sb_disasm = use_sb || (rctx->screen->debug_flags & DBG_SB_DISASM);
145
146 shader->shader.bc.isa = rctx->isa;
147
148 if (dump) {
149 fprintf(stderr, "--------------------------------------------------------------\n");
150 tgsi_dump(sel->tokens, 0);
151
152 if (sel->so.num_outputs) {
153 r600_dump_streamout(&sel->so);
154 }
155 }
156 r = r600_shader_from_tgsi(rctx->screen, shader, key);
157 if (r) {
158 R600_ERR("translation from TGSI failed !\n");
159 return r;
160 }
161
162 /* Check if the bytecode has already been built. When using the llvm
163 * backend, r600_shader_from_tgsi() will take care of building the
164 * bytecode.
165 */
166 if (!shader->shader.bc.bytecode) {
167 r = r600_bytecode_build(&shader->shader.bc);
168 if (r) {
169 R600_ERR("building bytecode failed !\n");
170 return r;
171 }
172 }
173
174 if (dump && !sb_disasm) {
175 fprintf(stderr, "--------------------------------------------------------------\n");
176 r600_bytecode_disasm(&shader->shader.bc);
177 fprintf(stderr, "______________________________________________________________\n");
178 } else if ((dump && sb_disasm) || use_sb) {
179 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
180 dump, use_sb);
181 if (r) {
182 R600_ERR("r600_sb_bytecode_process failed !\n");
183 return r;
184 }
185 }
186
187 /* Store the shader in a buffer. */
188 if (shader->bo == NULL) {
189 shader->bo = (struct r600_resource*)
190 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
191 if (shader->bo == NULL) {
192 return -ENOMEM;
193 }
194 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
195 if (R600_BIG_ENDIAN) {
196 for (i = 0; i < shader->shader.bc.ndw; ++i) {
197 ptr[i] = bswap_32(shader->shader.bc.bytecode[i]);
198 }
199 } else {
200 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
201 }
202 rctx->ws->buffer_unmap(shader->bo->cs_buf);
203 }
204
205 /* Build state. */
206 switch (shader->shader.processor_type) {
207 case TGSI_PROCESSOR_VERTEX:
208 if (rctx->chip_class >= EVERGREEN) {
209 evergreen_update_vs_state(ctx, shader);
210 } else {
211 r600_update_vs_state(ctx, shader);
212 }
213 break;
214 case TGSI_PROCESSOR_FRAGMENT:
215 if (rctx->chip_class >= EVERGREEN) {
216 evergreen_update_ps_state(ctx, shader);
217 } else {
218 r600_update_ps_state(ctx, shader);
219 }
220 break;
221 default:
222 return -EINVAL;
223 }
224 return 0;
225 }
226
227 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
228 {
229 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
230 r600_bytecode_clear(&shader->shader.bc);
231 r600_release_command_buffer(&shader->command_buffer);
232 }
233
234 /*
235 * tgsi -> r600 shader
236 */
237 struct r600_shader_tgsi_instruction;
238
239 struct r600_shader_src {
240 unsigned sel;
241 unsigned swizzle[4];
242 unsigned neg;
243 unsigned abs;
244 unsigned rel;
245 unsigned kc_bank;
246 uint32_t value[4];
247 };
248
249 struct r600_shader_ctx {
250 struct tgsi_shader_info info;
251 struct tgsi_parse_context parse;
252 const struct tgsi_token *tokens;
253 unsigned type;
254 unsigned file_offset[TGSI_FILE_COUNT];
255 unsigned temp_reg;
256 struct r600_shader_tgsi_instruction *inst_info;
257 struct r600_bytecode *bc;
258 struct r600_shader *shader;
259 struct r600_shader_src src[4];
260 uint32_t *literals;
261 uint32_t nliterals;
262 uint32_t max_driver_temp_used;
263 boolean use_llvm;
264 /* needed for evergreen interpolation */
265 boolean input_centroid;
266 boolean input_linear;
267 boolean input_perspective;
268 int num_interp_gpr;
269 int face_gpr;
270 int colors_used;
271 boolean clip_vertex_write;
272 unsigned cv_output;
273 int fragcoord_input;
274 int native_integers;
275 };
276
277 struct r600_shader_tgsi_instruction {
278 unsigned tgsi_opcode;
279 unsigned is_op3;
280 unsigned op;
281 int (*process)(struct r600_shader_ctx *ctx);
282 };
283
284 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
285 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
286 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
287 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
288 static int tgsi_else(struct r600_shader_ctx *ctx);
289 static int tgsi_endif(struct r600_shader_ctx *ctx);
290 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
291 static int tgsi_endloop(struct r600_shader_ctx *ctx);
292 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
293
294 #ifdef HAVE_OPENCL
295 int r600_compute_shader_create(struct pipe_context * ctx,
296 LLVMModuleRef mod, struct r600_bytecode * bytecode)
297 {
298 struct r600_context *r600_ctx = (struct r600_context *)ctx;
299 struct r600_shader_ctx shader_ctx;
300 boolean use_kill = false;
301 bool dump = (r600_ctx->screen->debug_flags & DBG_CS) != 0;
302 unsigned use_sb = r600_ctx->screen->debug_flags & DBG_SB_CS;
303 unsigned sb_disasm = use_sb ||
304 (r600_ctx->screen->debug_flags & DBG_SB_DISASM);
305
306 shader_ctx.bc = bytecode;
307 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family,
308 r600_ctx->screen->has_compressed_msaa_texturing);
309 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
310 shader_ctx.bc->isa = r600_ctx->isa;
311 r600_llvm_compile(mod, r600_ctx->family,
312 shader_ctx.bc, &use_kill, dump);
313
314 if (dump && !sb_disasm) {
315 r600_bytecode_disasm(shader_ctx.bc);
316 } else if ((dump && sb_disasm) || use_sb) {
317 if (r600_sb_bytecode_process(r600_ctx, shader_ctx.bc, NULL, dump, use_sb))
318 R600_ERR("r600_sb_bytecode_process failed!\n");
319 }
320
321 return 1;
322 }
323
324 #endif /* HAVE_OPENCL */
325
326 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
327 {
328 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
329 int j;
330
331 if (i->Instruction.NumDstRegs > 1) {
332 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
333 return -EINVAL;
334 }
335 if (i->Instruction.Predicate) {
336 R600_ERR("predicate unsupported\n");
337 return -EINVAL;
338 }
339 #if 0
340 if (i->Instruction.Label) {
341 R600_ERR("label unsupported\n");
342 return -EINVAL;
343 }
344 #endif
345 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
346 if (i->Src[j].Register.Dimension) {
347 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
348 R600_ERR("unsupported src %d (dimension %d)\n", j,
349 i->Src[j].Register.Dimension);
350 return -EINVAL;
351 }
352 }
353 }
354 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
355 if (i->Dst[j].Register.Dimension) {
356 R600_ERR("unsupported dst (dimension)\n");
357 return -EINVAL;
358 }
359 }
360 return 0;
361 }
362
363 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
364 int input)
365 {
366 int ij_index = 0;
367
368 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
369 if (ctx->shader->input[input].centroid)
370 ij_index++;
371 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
372 /* if we have perspective add one */
373 if (ctx->input_perspective) {
374 ij_index++;
375 /* if we have perspective centroid */
376 if (ctx->input_centroid)
377 ij_index++;
378 }
379 if (ctx->shader->input[input].centroid)
380 ij_index++;
381 }
382
383 ctx->shader->input[input].ij_index = ij_index;
384 }
385
386 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
387 {
388 int i, r;
389 struct r600_bytecode_alu alu;
390 int gpr = 0, base_chan = 0;
391 int ij_index = ctx->shader->input[input].ij_index;
392
393 /* work out gpr and base_chan from index */
394 gpr = ij_index / 2;
395 base_chan = (2 * (ij_index % 2)) + 1;
396
397 for (i = 0; i < 8; i++) {
398 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
399
400 if (i < 4)
401 alu.op = ALU_OP2_INTERP_ZW;
402 else
403 alu.op = ALU_OP2_INTERP_XY;
404
405 if ((i > 1) && (i < 6)) {
406 alu.dst.sel = ctx->shader->input[input].gpr;
407 alu.dst.write = 1;
408 }
409
410 alu.dst.chan = i % 4;
411
412 alu.src[0].sel = gpr;
413 alu.src[0].chan = (base_chan - (i % 2));
414
415 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
416
417 alu.bank_swizzle_force = SQ_ALU_VEC_210;
418 if ((i % 4) == 3)
419 alu.last = 1;
420 r = r600_bytecode_add_alu(ctx->bc, &alu);
421 if (r)
422 return r;
423 }
424 return 0;
425 }
426
427 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
428 {
429 int i, r;
430 struct r600_bytecode_alu alu;
431
432 for (i = 0; i < 4; i++) {
433 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
434
435 alu.op = ALU_OP1_INTERP_LOAD_P0;
436
437 alu.dst.sel = ctx->shader->input[input].gpr;
438 alu.dst.write = 1;
439
440 alu.dst.chan = i;
441
442 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
443 alu.src[0].chan = i;
444
445 if (i == 3)
446 alu.last = 1;
447 r = r600_bytecode_add_alu(ctx->bc, &alu);
448 if (r)
449 return r;
450 }
451 return 0;
452 }
453
454 /*
455 * Special export handling in shaders
456 *
457 * shader export ARRAY_BASE for EXPORT_POS:
458 * 60 is position
459 * 61 is misc vector
460 * 62, 63 are clip distance vectors
461 *
462 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
463 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
464 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
465 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
466 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
467 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
468 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
469 * exclusive from render target index)
470 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
471 *
472 *
473 * shader export ARRAY_BASE for EXPORT_PIXEL:
474 * 0-7 CB targets
475 * 61 computed Z vector
476 *
477 * The use of the values exported in the computed Z vector are controlled
478 * by DB_SHADER_CONTROL:
479 * Z_EXPORT_ENABLE - Z as a float in RED
480 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
481 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
482 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
483 * DB_SOURCE_FORMAT - export control restrictions
484 *
485 */
486
487
488 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
489 static int r600_spi_sid(struct r600_shader_io * io)
490 {
491 int index, name = io->name;
492
493 /* These params are handled differently, they don't need
494 * semantic indices, so we'll use 0 for them.
495 */
496 if (name == TGSI_SEMANTIC_POSITION ||
497 name == TGSI_SEMANTIC_PSIZE ||
498 name == TGSI_SEMANTIC_FACE)
499 index = 0;
500 else {
501 if (name == TGSI_SEMANTIC_GENERIC) {
502 /* For generic params simply use sid from tgsi */
503 index = io->sid;
504 } else {
505 /* For non-generic params - pack name and sid into 8 bits */
506 index = 0x80 | (name<<3) | (io->sid);
507 }
508
509 /* Make sure that all really used indices have nonzero value, so
510 * we can just compare it to 0 later instead of comparing the name
511 * with different values to detect special cases. */
512 index++;
513 }
514
515 return index;
516 };
517
518 /* turn input into interpolate on EG */
519 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
520 {
521 int r = 0;
522
523 if (ctx->shader->input[index].spi_sid) {
524 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
525 if (ctx->shader->input[index].interpolate > 0) {
526 evergreen_interp_assign_ij_index(ctx, index);
527 if (!ctx->use_llvm)
528 r = evergreen_interp_alu(ctx, index);
529 } else {
530 if (!ctx->use_llvm)
531 r = evergreen_interp_flat(ctx, index);
532 }
533 }
534 return r;
535 }
536
537 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
538 {
539 struct r600_bytecode_alu alu;
540 int i, r;
541 int gpr_front = ctx->shader->input[front].gpr;
542 int gpr_back = ctx->shader->input[back].gpr;
543
544 for (i = 0; i < 4; i++) {
545 memset(&alu, 0, sizeof(alu));
546 alu.op = ALU_OP3_CNDGT;
547 alu.is_op3 = 1;
548 alu.dst.write = 1;
549 alu.dst.sel = gpr_front;
550 alu.src[0].sel = ctx->face_gpr;
551 alu.src[1].sel = gpr_front;
552 alu.src[2].sel = gpr_back;
553
554 alu.dst.chan = i;
555 alu.src[1].chan = i;
556 alu.src[2].chan = i;
557 alu.last = (i==3);
558
559 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
560 return r;
561 }
562
563 return 0;
564 }
565
566 static int tgsi_declaration(struct r600_shader_ctx *ctx)
567 {
568 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
569 int r, i, j, count = d->Range.Last - d->Range.First + 1;
570
571 switch (d->Declaration.File) {
572 case TGSI_FILE_INPUT:
573 i = ctx->shader->ninput;
574 assert(i < Elements(ctx->shader->input));
575 ctx->shader->ninput += count;
576 ctx->shader->input[i].name = d->Semantic.Name;
577 ctx->shader->input[i].sid = d->Semantic.Index;
578 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
579 ctx->shader->input[i].centroid = d->Interp.Centroid;
580 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
581 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
582 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
583 switch (ctx->shader->input[i].name) {
584 case TGSI_SEMANTIC_FACE:
585 ctx->face_gpr = ctx->shader->input[i].gpr;
586 break;
587 case TGSI_SEMANTIC_COLOR:
588 ctx->colors_used++;
589 break;
590 case TGSI_SEMANTIC_POSITION:
591 ctx->fragcoord_input = i;
592 break;
593 }
594 if (ctx->bc->chip_class >= EVERGREEN) {
595 if ((r = evergreen_interp_input(ctx, i)))
596 return r;
597 }
598 }
599 for (j = 1; j < count; ++j) {
600 ctx->shader->input[i + j] = ctx->shader->input[i];
601 ctx->shader->input[i + j].gpr += j;
602 }
603 break;
604 case TGSI_FILE_OUTPUT:
605 i = ctx->shader->noutput++;
606 assert(i < Elements(ctx->shader->output));
607 ctx->shader->output[i].name = d->Semantic.Name;
608 ctx->shader->output[i].sid = d->Semantic.Index;
609 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
610 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
611 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
612 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
613 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
614 switch (d->Semantic.Name) {
615 case TGSI_SEMANTIC_CLIPDIST:
616 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
617 break;
618 case TGSI_SEMANTIC_PSIZE:
619 ctx->shader->vs_out_misc_write = 1;
620 ctx->shader->vs_out_point_size = 1;
621 break;
622 case TGSI_SEMANTIC_CLIPVERTEX:
623 ctx->clip_vertex_write = TRUE;
624 ctx->cv_output = i;
625 break;
626 }
627 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
628 switch (d->Semantic.Name) {
629 case TGSI_SEMANTIC_COLOR:
630 ctx->shader->nr_ps_max_color_exports++;
631 break;
632 }
633 }
634 break;
635 case TGSI_FILE_TEMPORARY:
636 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
637 if (d->Array.ArrayID) {
638 r600_add_gpr_array(ctx->shader,
639 ctx->file_offset[TGSI_FILE_TEMPORARY] +
640 d->Range.First,
641 d->Range.Last - d->Range.First + 1, 0x0F);
642 }
643 }
644 break;
645
646 case TGSI_FILE_CONSTANT:
647 case TGSI_FILE_SAMPLER:
648 case TGSI_FILE_ADDRESS:
649 break;
650
651 case TGSI_FILE_SYSTEM_VALUE:
652 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
653 if (!ctx->native_integers) {
654 struct r600_bytecode_alu alu;
655 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
656
657 alu.op = ALU_OP1_INT_TO_FLT;
658 alu.src[0].sel = 0;
659 alu.src[0].chan = 3;
660
661 alu.dst.sel = 0;
662 alu.dst.chan = 3;
663 alu.dst.write = 1;
664 alu.last = 1;
665
666 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
667 return r;
668 }
669 break;
670 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
671 break;
672 default:
673 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
674 return -EINVAL;
675 }
676 return 0;
677 }
678
679 static int r600_get_temp(struct r600_shader_ctx *ctx)
680 {
681 return ctx->temp_reg + ctx->max_driver_temp_used++;
682 }
683
684 /*
685 * for evergreen we need to scan the shader to find the number of GPRs we need to
686 * reserve for interpolation.
687 *
688 * we need to know if we are going to emit
689 * any centroid inputs
690 * if perspective and linear are required
691 */
692 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
693 {
694 int i;
695 int num_baryc;
696
697 ctx->input_linear = FALSE;
698 ctx->input_perspective = FALSE;
699 ctx->input_centroid = FALSE;
700 ctx->num_interp_gpr = 1;
701
702 /* any centroid inputs */
703 for (i = 0; i < ctx->info.num_inputs; i++) {
704 /* skip position/face */
705 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
706 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
707 continue;
708 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
709 ctx->input_linear = TRUE;
710 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
711 ctx->input_perspective = TRUE;
712 if (ctx->info.input_centroid[i])
713 ctx->input_centroid = TRUE;
714 }
715
716 num_baryc = 0;
717 /* ignoring sample for now */
718 if (ctx->input_perspective)
719 num_baryc++;
720 if (ctx->input_linear)
721 num_baryc++;
722 if (ctx->input_centroid)
723 num_baryc *= 2;
724
725 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
726
727 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
728 return ctx->num_interp_gpr;
729 }
730
731 static void tgsi_src(struct r600_shader_ctx *ctx,
732 const struct tgsi_full_src_register *tgsi_src,
733 struct r600_shader_src *r600_src)
734 {
735 memset(r600_src, 0, sizeof(*r600_src));
736 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
737 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
738 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
739 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
740 r600_src->neg = tgsi_src->Register.Negate;
741 r600_src->abs = tgsi_src->Register.Absolute;
742
743 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
744 int index;
745 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
746 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
747 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
748
749 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
750 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
751 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
752 return;
753 }
754 index = tgsi_src->Register.Index;
755 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
756 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
757 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
758 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
759 r600_src->swizzle[0] = 3;
760 r600_src->swizzle[1] = 3;
761 r600_src->swizzle[2] = 3;
762 r600_src->swizzle[3] = 3;
763 r600_src->sel = 0;
764 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
765 r600_src->swizzle[0] = 0;
766 r600_src->swizzle[1] = 0;
767 r600_src->swizzle[2] = 0;
768 r600_src->swizzle[3] = 0;
769 r600_src->sel = 0;
770 }
771 } else {
772 if (tgsi_src->Register.Indirect)
773 r600_src->rel = V_SQ_REL_RELATIVE;
774 r600_src->sel = tgsi_src->Register.Index;
775 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
776 }
777 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
778 if (tgsi_src->Register.Dimension) {
779 r600_src->kc_bank = tgsi_src->Dimension.Index;
780 }
781 }
782 }
783
784 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
785 {
786 struct r600_bytecode_vtx vtx;
787 unsigned int ar_reg;
788 int r;
789
790 if (offset) {
791 struct r600_bytecode_alu alu;
792
793 memset(&alu, 0, sizeof(alu));
794
795 alu.op = ALU_OP2_ADD_INT;
796 alu.src[0].sel = ctx->bc->ar_reg;
797
798 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
799 alu.src[1].value = offset;
800
801 alu.dst.sel = dst_reg;
802 alu.dst.write = 1;
803 alu.last = 1;
804
805 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
806 return r;
807
808 ar_reg = dst_reg;
809 } else {
810 ar_reg = ctx->bc->ar_reg;
811 }
812
813 memset(&vtx, 0, sizeof(vtx));
814 vtx.buffer_id = cb_idx;
815 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
816 vtx.src_gpr = ar_reg;
817 vtx.mega_fetch_count = 16;
818 vtx.dst_gpr = dst_reg;
819 vtx.dst_sel_x = 0; /* SEL_X */
820 vtx.dst_sel_y = 1; /* SEL_Y */
821 vtx.dst_sel_z = 2; /* SEL_Z */
822 vtx.dst_sel_w = 3; /* SEL_W */
823 vtx.data_format = FMT_32_32_32_32_FLOAT;
824 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
825 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
826 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
827 vtx.endian = r600_endian_swap(32);
828
829 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
830 return r;
831
832 return 0;
833 }
834
835 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
836 {
837 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
838 struct r600_bytecode_alu alu;
839 int i, j, k, nconst, r;
840
841 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
842 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
843 nconst++;
844 }
845 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
846 }
847 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
848 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
849 continue;
850 }
851
852 if (ctx->src[i].rel) {
853 int treg = r600_get_temp(ctx);
854 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
855 return r;
856
857 ctx->src[i].kc_bank = 0;
858 ctx->src[i].sel = treg;
859 ctx->src[i].rel = 0;
860 j--;
861 } else if (j > 0) {
862 int treg = r600_get_temp(ctx);
863 for (k = 0; k < 4; k++) {
864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
865 alu.op = ALU_OP1_MOV;
866 alu.src[0].sel = ctx->src[i].sel;
867 alu.src[0].chan = k;
868 alu.src[0].rel = ctx->src[i].rel;
869 alu.dst.sel = treg;
870 alu.dst.chan = k;
871 alu.dst.write = 1;
872 if (k == 3)
873 alu.last = 1;
874 r = r600_bytecode_add_alu(ctx->bc, &alu);
875 if (r)
876 return r;
877 }
878 ctx->src[i].sel = treg;
879 ctx->src[i].rel =0;
880 j--;
881 }
882 }
883 return 0;
884 }
885
886 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
887 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
888 {
889 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
890 struct r600_bytecode_alu alu;
891 int i, j, k, nliteral, r;
892
893 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
894 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
895 nliteral++;
896 }
897 }
898 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
899 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
900 int treg = r600_get_temp(ctx);
901 for (k = 0; k < 4; k++) {
902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
903 alu.op = ALU_OP1_MOV;
904 alu.src[0].sel = ctx->src[i].sel;
905 alu.src[0].chan = k;
906 alu.src[0].value = ctx->src[i].value[k];
907 alu.dst.sel = treg;
908 alu.dst.chan = k;
909 alu.dst.write = 1;
910 if (k == 3)
911 alu.last = 1;
912 r = r600_bytecode_add_alu(ctx->bc, &alu);
913 if (r)
914 return r;
915 }
916 ctx->src[i].sel = treg;
917 j--;
918 }
919 }
920 return 0;
921 }
922
923 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
924 {
925 int i, r, count = ctx->shader->ninput;
926
927 for (i = 0; i < count; i++) {
928 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
929 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
930 if (r)
931 return r;
932 }
933 }
934 return 0;
935 }
936
937
938 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
939 struct r600_pipe_shader *pipeshader,
940 struct r600_shader_key key)
941 {
942 struct r600_shader *shader = &pipeshader->shader;
943 struct tgsi_token *tokens = pipeshader->selector->tokens;
944 struct pipe_stream_output_info so = pipeshader->selector->so;
945 struct tgsi_full_immediate *immediate;
946 struct tgsi_full_property *property;
947 struct r600_shader_ctx ctx;
948 struct r600_bytecode_output output[32];
949 unsigned output_done, noutput;
950 unsigned opcode;
951 int i, j, k, r = 0;
952 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
953 /* Declarations used by llvm code */
954 bool use_llvm = false;
955 bool indirect_gprs;
956
957 #ifdef R600_USE_LLVM
958 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
959 #endif
960 ctx.bc = &shader->bc;
961 ctx.shader = shader;
962 ctx.native_integers = true;
963
964 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
965 rscreen->has_compressed_msaa_texturing);
966 ctx.tokens = tokens;
967 tgsi_scan_shader(tokens, &ctx.info);
968 shader->indirect_files = ctx.info.indirect_files;
969 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
970 tgsi_parse_init(&ctx.parse, tokens);
971 ctx.type = ctx.parse.FullHeader.Processor.Processor;
972 shader->processor_type = ctx.type;
973 ctx.bc->type = shader->processor_type;
974
975 ctx.face_gpr = -1;
976 ctx.fragcoord_input = -1;
977 ctx.colors_used = 0;
978 ctx.clip_vertex_write = 0;
979
980 shader->nr_ps_color_exports = 0;
981 shader->nr_ps_max_color_exports = 0;
982
983 shader->two_side = key.color_two_side;
984
985 /* register allocations */
986 /* Values [0,127] correspond to GPR[0..127].
987 * Values [128,159] correspond to constant buffer bank 0
988 * Values [160,191] correspond to constant buffer bank 1
989 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
990 * Values [256,287] correspond to constant buffer bank 2 (EG)
991 * Values [288,319] correspond to constant buffer bank 3 (EG)
992 * Other special values are shown in the list below.
993 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
994 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
995 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
996 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
997 * 248 SQ_ALU_SRC_0: special constant 0.0.
998 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
999 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1000 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1001 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1002 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1003 * 254 SQ_ALU_SRC_PV: previous vector result.
1004 * 255 SQ_ALU_SRC_PS: previous scalar result.
1005 */
1006 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1007 ctx.file_offset[i] = 0;
1008 }
1009
1010 #ifdef R600_USE_LLVM
1011 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1012 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1013 "indirect adressing. Falling back to TGSI "
1014 "backend.\n");
1015 use_llvm = 0;
1016 }
1017 #endif
1018 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1019 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1020 if (!use_llvm) {
1021 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1022 }
1023 }
1024 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1025 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1026 }
1027 ctx.use_llvm = use_llvm;
1028
1029 if (use_llvm) {
1030 ctx.file_offset[TGSI_FILE_OUTPUT] =
1031 ctx.file_offset[TGSI_FILE_INPUT];
1032 } else {
1033 ctx.file_offset[TGSI_FILE_OUTPUT] =
1034 ctx.file_offset[TGSI_FILE_INPUT] +
1035 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1036 }
1037 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1038 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1039
1040 /* Outside the GPR range. This will be translated to one of the
1041 * kcache banks later. */
1042 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1043
1044 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1045 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1046 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1047 ctx.temp_reg = ctx.bc->ar_reg + 1;
1048
1049 if (indirect_gprs) {
1050 shader->max_arrays = 0;
1051 shader->num_arrays = 0;
1052
1053 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1054 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1055 ctx.file_offset[TGSI_FILE_OUTPUT] -
1056 ctx.file_offset[TGSI_FILE_INPUT],
1057 0x0F);
1058 }
1059 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1060 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1061 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1062 ctx.file_offset[TGSI_FILE_OUTPUT],
1063 0x0F);
1064 }
1065 }
1066
1067 ctx.nliterals = 0;
1068 ctx.literals = NULL;
1069 shader->fs_write_all = FALSE;
1070 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1071 tgsi_parse_token(&ctx.parse);
1072 switch (ctx.parse.FullToken.Token.Type) {
1073 case TGSI_TOKEN_TYPE_IMMEDIATE:
1074 immediate = &ctx.parse.FullToken.FullImmediate;
1075 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1076 if(ctx.literals == NULL) {
1077 r = -ENOMEM;
1078 goto out_err;
1079 }
1080 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1081 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1082 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1083 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1084 ctx.nliterals++;
1085 break;
1086 case TGSI_TOKEN_TYPE_DECLARATION:
1087 r = tgsi_declaration(&ctx);
1088 if (r)
1089 goto out_err;
1090 break;
1091 case TGSI_TOKEN_TYPE_INSTRUCTION:
1092 break;
1093 case TGSI_TOKEN_TYPE_PROPERTY:
1094 property = &ctx.parse.FullToken.FullProperty;
1095 switch (property->Property.PropertyName) {
1096 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1097 if (property->u[0].Data == 1)
1098 shader->fs_write_all = TRUE;
1099 break;
1100 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1101 /* we don't need this one */
1102 break;
1103 }
1104 break;
1105 default:
1106 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1107 r = -EINVAL;
1108 goto out_err;
1109 }
1110 }
1111
1112 /* Process two side if needed */
1113 if (shader->two_side && ctx.colors_used) {
1114 int i, count = ctx.shader->ninput;
1115 unsigned next_lds_loc = ctx.shader->nlds;
1116
1117 /* additional inputs will be allocated right after the existing inputs,
1118 * we won't need them after the color selection, so we don't need to
1119 * reserve these gprs for the rest of the shader code and to adjust
1120 * output offsets etc. */
1121 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1122 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1123
1124 if (ctx.face_gpr == -1) {
1125 i = ctx.shader->ninput++;
1126 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1127 ctx.shader->input[i].spi_sid = 0;
1128 ctx.shader->input[i].gpr = gpr++;
1129 ctx.face_gpr = ctx.shader->input[i].gpr;
1130 }
1131
1132 for (i = 0; i < count; i++) {
1133 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1134 int ni = ctx.shader->ninput++;
1135 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1136 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1137 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1138 ctx.shader->input[ni].gpr = gpr++;
1139 // TGSI to LLVM needs to know the lds position of inputs.
1140 // Non LLVM path computes it later (in process_twoside_color)
1141 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1142 ctx.shader->input[i].back_color_input = ni;
1143 if (ctx.bc->chip_class >= EVERGREEN) {
1144 if ((r = evergreen_interp_input(&ctx, ni)))
1145 return r;
1146 }
1147 }
1148 }
1149 }
1150
1151 /* LLVM backend setup */
1152 #ifdef R600_USE_LLVM
1153 if (use_llvm) {
1154 struct radeon_llvm_context radeon_llvm_ctx;
1155 LLVMModuleRef mod;
1156 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1157 boolean use_kill = false;
1158
1159 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1160 radeon_llvm_ctx.type = ctx.type;
1161 radeon_llvm_ctx.two_side = shader->two_side;
1162 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1163 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1164 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1165 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1166 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1167 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1168 radeon_llvm_ctx.stream_outputs = &so;
1169 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1170 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1171 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1172 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1173
1174 if (r600_llvm_compile(mod, rscreen->family, ctx.bc, &use_kill, dump)) {
1175 radeon_llvm_dispose(&radeon_llvm_ctx);
1176 use_llvm = 0;
1177 fprintf(stderr, "R600 LLVM backend failed to compile "
1178 "shader. Falling back to TGSI\n");
1179 } else {
1180 ctx.file_offset[TGSI_FILE_OUTPUT] =
1181 ctx.file_offset[TGSI_FILE_INPUT];
1182 }
1183 if (use_kill)
1184 ctx.shader->uses_kill = use_kill;
1185 radeon_llvm_dispose(&radeon_llvm_ctx);
1186 }
1187 #endif
1188 /* End of LLVM backend setup */
1189
1190 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1191 shader->nr_ps_max_color_exports = 8;
1192
1193 if (!use_llvm) {
1194 if (ctx.fragcoord_input >= 0) {
1195 if (ctx.bc->chip_class == CAYMAN) {
1196 for (j = 0 ; j < 4; j++) {
1197 struct r600_bytecode_alu alu;
1198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1199 alu.op = ALU_OP1_RECIP_IEEE;
1200 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1201 alu.src[0].chan = 3;
1202
1203 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1204 alu.dst.chan = j;
1205 alu.dst.write = (j == 3);
1206 alu.last = 1;
1207 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1208 return r;
1209 }
1210 } else {
1211 struct r600_bytecode_alu alu;
1212 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1213 alu.op = ALU_OP1_RECIP_IEEE;
1214 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1215 alu.src[0].chan = 3;
1216
1217 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1218 alu.dst.chan = 3;
1219 alu.dst.write = 1;
1220 alu.last = 1;
1221 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1222 return r;
1223 }
1224 }
1225
1226 if (shader->two_side && ctx.colors_used) {
1227 if ((r = process_twoside_color_inputs(&ctx)))
1228 return r;
1229 }
1230
1231 tgsi_parse_init(&ctx.parse, tokens);
1232 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1233 tgsi_parse_token(&ctx.parse);
1234 switch (ctx.parse.FullToken.Token.Type) {
1235 case TGSI_TOKEN_TYPE_INSTRUCTION:
1236 r = tgsi_is_supported(&ctx);
1237 if (r)
1238 goto out_err;
1239 ctx.max_driver_temp_used = 0;
1240 /* reserve first tmp for everyone */
1241 r600_get_temp(&ctx);
1242
1243 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1244 if ((r = tgsi_split_constant(&ctx)))
1245 goto out_err;
1246 if ((r = tgsi_split_literal_constant(&ctx)))
1247 goto out_err;
1248 if (ctx.bc->chip_class == CAYMAN)
1249 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1250 else if (ctx.bc->chip_class >= EVERGREEN)
1251 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1252 else
1253 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1254 r = ctx.inst_info->process(&ctx);
1255 if (r)
1256 goto out_err;
1257 break;
1258 default:
1259 break;
1260 }
1261 }
1262 }
1263
1264 /* Reset the temporary register counter. */
1265 ctx.max_driver_temp_used = 0;
1266
1267 noutput = shader->noutput;
1268
1269 if (ctx.clip_vertex_write) {
1270 unsigned clipdist_temp[2];
1271
1272 clipdist_temp[0] = r600_get_temp(&ctx);
1273 clipdist_temp[1] = r600_get_temp(&ctx);
1274
1275 /* need to convert a clipvertex write into clipdistance writes and not export
1276 the clip vertex anymore */
1277
1278 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1279 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1280 shader->output[noutput].gpr = clipdist_temp[0];
1281 noutput++;
1282 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1283 shader->output[noutput].gpr = clipdist_temp[1];
1284 noutput++;
1285
1286 /* reset spi_sid for clipvertex output to avoid confusing spi */
1287 shader->output[ctx.cv_output].spi_sid = 0;
1288
1289 shader->clip_dist_write = 0xFF;
1290
1291 for (i = 0; i < 8; i++) {
1292 int oreg = i >> 2;
1293 int ochan = i & 3;
1294
1295 for (j = 0; j < 4; j++) {
1296 struct r600_bytecode_alu alu;
1297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1298 alu.op = ALU_OP2_DOT4;
1299 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1300 alu.src[0].chan = j;
1301
1302 alu.src[1].sel = 512 + i;
1303 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1304 alu.src[1].chan = j;
1305
1306 alu.dst.sel = clipdist_temp[oreg];
1307 alu.dst.chan = j;
1308 alu.dst.write = (j == ochan);
1309 if (j == 3)
1310 alu.last = 1;
1311 if (!use_llvm)
1312 r = r600_bytecode_add_alu(ctx.bc, &alu);
1313 if (r)
1314 return r;
1315 }
1316 }
1317 }
1318
1319 /* Add stream outputs. */
1320 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1321 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1322
1323 /* Sanity checking. */
1324 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1325 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1326 r = -EINVAL;
1327 goto out_err;
1328 }
1329 for (i = 0; i < so.num_outputs; i++) {
1330 if (so.output[i].output_buffer >= 4) {
1331 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1332 so.output[i].output_buffer);
1333 r = -EINVAL;
1334 goto out_err;
1335 }
1336 }
1337
1338 /* Initialize locations where the outputs are stored. */
1339 for (i = 0; i < so.num_outputs; i++) {
1340 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1341
1342 /* Lower outputs with dst_offset < start_component.
1343 *
1344 * We can only output 4D vectors with a write mask, e.g. we can
1345 * only output the W component at offset 3, etc. If we want
1346 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1347 * to move it to X and output X. */
1348 if (so.output[i].dst_offset < so.output[i].start_component) {
1349 unsigned tmp = r600_get_temp(&ctx);
1350
1351 for (j = 0; j < so.output[i].num_components; j++) {
1352 struct r600_bytecode_alu alu;
1353 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1354 alu.op = ALU_OP1_MOV;
1355 alu.src[0].sel = so_gpr[i];
1356 alu.src[0].chan = so.output[i].start_component + j;
1357
1358 alu.dst.sel = tmp;
1359 alu.dst.chan = j;
1360 alu.dst.write = 1;
1361 if (j == so.output[i].num_components - 1)
1362 alu.last = 1;
1363 r = r600_bytecode_add_alu(ctx.bc, &alu);
1364 if (r)
1365 return r;
1366 }
1367 so.output[i].start_component = 0;
1368 so_gpr[i] = tmp;
1369 }
1370 }
1371
1372 /* Write outputs to buffers. */
1373 for (i = 0; i < so.num_outputs; i++) {
1374 struct r600_bytecode_output output;
1375
1376 memset(&output, 0, sizeof(struct r600_bytecode_output));
1377 output.gpr = so_gpr[i];
1378 output.elem_size = so.output[i].num_components;
1379 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1380 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1381 output.burst_count = 1;
1382 output.barrier = 1;
1383 /* array_size is an upper limit for the burst_count
1384 * with MEM_STREAM instructions */
1385 output.array_size = 0xFFF;
1386 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1387 if (ctx.bc->chip_class >= EVERGREEN) {
1388 switch (so.output[i].output_buffer) {
1389 case 0:
1390 output.op = CF_OP_MEM_STREAM0_BUF0;
1391 break;
1392 case 1:
1393 output.op = CF_OP_MEM_STREAM0_BUF1;
1394 break;
1395 case 2:
1396 output.op = CF_OP_MEM_STREAM0_BUF2;
1397 break;
1398 case 3:
1399 output.op = CF_OP_MEM_STREAM0_BUF3;
1400 break;
1401 }
1402 } else {
1403 switch (so.output[i].output_buffer) {
1404 case 0:
1405 output.op = CF_OP_MEM_STREAM0;
1406 break;
1407 case 1:
1408 output.op = CF_OP_MEM_STREAM1;
1409 break;
1410 case 2:
1411 output.op = CF_OP_MEM_STREAM2;
1412 break;
1413 case 3:
1414 output.op = CF_OP_MEM_STREAM3;
1415 break;
1416 }
1417 }
1418 r = r600_bytecode_add_output(ctx.bc, &output);
1419 if (r)
1420 goto out_err;
1421 }
1422 }
1423
1424 /* export output */
1425 for (i = 0, j = 0; i < noutput; i++, j++) {
1426 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1427 output[j].gpr = shader->output[i].gpr;
1428 output[j].elem_size = 3;
1429 output[j].swizzle_x = 0;
1430 output[j].swizzle_y = 1;
1431 output[j].swizzle_z = 2;
1432 output[j].swizzle_w = 3;
1433 output[j].burst_count = 1;
1434 output[j].barrier = 1;
1435 output[j].type = -1;
1436 output[j].op = CF_OP_EXPORT;
1437 switch (ctx.type) {
1438 case TGSI_PROCESSOR_VERTEX:
1439 switch (shader->output[i].name) {
1440 case TGSI_SEMANTIC_POSITION:
1441 output[j].array_base = next_pos_base++;
1442 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1443 break;
1444
1445 case TGSI_SEMANTIC_PSIZE:
1446 output[j].array_base = next_pos_base++;
1447 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1448 break;
1449 case TGSI_SEMANTIC_CLIPVERTEX:
1450 j--;
1451 break;
1452 case TGSI_SEMANTIC_CLIPDIST:
1453 output[j].array_base = next_pos_base++;
1454 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1455 /* spi_sid is 0 for clipdistance outputs that were generated
1456 * for clipvertex - we don't need to pass them to PS */
1457 if (shader->output[i].spi_sid) {
1458 j++;
1459 /* duplicate it as PARAM to pass to the pixel shader */
1460 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1461 output[j].array_base = next_param_base++;
1462 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1463 }
1464 break;
1465 case TGSI_SEMANTIC_FOG:
1466 output[j].swizzle_y = 4; /* 0 */
1467 output[j].swizzle_z = 4; /* 0 */
1468 output[j].swizzle_w = 5; /* 1 */
1469 break;
1470 }
1471 break;
1472 case TGSI_PROCESSOR_FRAGMENT:
1473 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1474 /* never export more colors than the number of CBs */
1475 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1476 /* skip export */
1477 j--;
1478 continue;
1479 }
1480 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1481 output[j].array_base = next_pixel_base++;
1482 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1483 shader->nr_ps_color_exports++;
1484 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1485 for (k = 1; k < key.nr_cbufs; k++) {
1486 j++;
1487 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1488 output[j].gpr = shader->output[i].gpr;
1489 output[j].elem_size = 3;
1490 output[j].swizzle_x = 0;
1491 output[j].swizzle_y = 1;
1492 output[j].swizzle_z = 2;
1493 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1494 output[j].burst_count = 1;
1495 output[j].barrier = 1;
1496 output[j].array_base = next_pixel_base++;
1497 output[j].op = CF_OP_EXPORT;
1498 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1499 shader->nr_ps_color_exports++;
1500 }
1501 }
1502 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1503 output[j].array_base = 61;
1504 output[j].swizzle_x = 2;
1505 output[j].swizzle_y = 7;
1506 output[j].swizzle_z = output[j].swizzle_w = 7;
1507 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1508 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1509 output[j].array_base = 61;
1510 output[j].swizzle_x = 7;
1511 output[j].swizzle_y = 1;
1512 output[j].swizzle_z = output[j].swizzle_w = 7;
1513 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1514 } else {
1515 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1516 r = -EINVAL;
1517 goto out_err;
1518 }
1519 break;
1520 default:
1521 R600_ERR("unsupported processor type %d\n", ctx.type);
1522 r = -EINVAL;
1523 goto out_err;
1524 }
1525
1526 if (output[j].type==-1) {
1527 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1528 output[j].array_base = next_param_base++;
1529 }
1530 }
1531
1532 /* add fake position export */
1533 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1534 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1535 output[j].gpr = 0;
1536 output[j].elem_size = 3;
1537 output[j].swizzle_x = 7;
1538 output[j].swizzle_y = 7;
1539 output[j].swizzle_z = 7;
1540 output[j].swizzle_w = 7;
1541 output[j].burst_count = 1;
1542 output[j].barrier = 1;
1543 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1544 output[j].array_base = next_pos_base;
1545 output[j].op = CF_OP_EXPORT;
1546 j++;
1547 }
1548
1549 /* add fake param output for vertex shader if no param is exported */
1550 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1551 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1552 output[j].gpr = 0;
1553 output[j].elem_size = 3;
1554 output[j].swizzle_x = 7;
1555 output[j].swizzle_y = 7;
1556 output[j].swizzle_z = 7;
1557 output[j].swizzle_w = 7;
1558 output[j].burst_count = 1;
1559 output[j].barrier = 1;
1560 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1561 output[j].array_base = 0;
1562 output[j].op = CF_OP_EXPORT;
1563 j++;
1564 }
1565
1566 /* add fake pixel export */
1567 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1568 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1569 output[j].gpr = 0;
1570 output[j].elem_size = 3;
1571 output[j].swizzle_x = 7;
1572 output[j].swizzle_y = 7;
1573 output[j].swizzle_z = 7;
1574 output[j].swizzle_w = 7;
1575 output[j].burst_count = 1;
1576 output[j].barrier = 1;
1577 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1578 output[j].array_base = 0;
1579 output[j].op = CF_OP_EXPORT;
1580 j++;
1581 }
1582
1583 noutput = j;
1584
1585 /* set export done on last export of each type */
1586 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1587 if (ctx.bc->chip_class < CAYMAN) {
1588 if (i == (noutput - 1)) {
1589 output[i].end_of_program = 1;
1590 }
1591 }
1592 if (!(output_done & (1 << output[i].type))) {
1593 output_done |= (1 << output[i].type);
1594 output[i].op = CF_OP_EXPORT_DONE;
1595 }
1596 }
1597 /* add output to bytecode */
1598 if (!use_llvm) {
1599 for (i = 0; i < noutput; i++) {
1600 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1601 if (r)
1602 goto out_err;
1603 }
1604 }
1605 /* add program end */
1606 if (!use_llvm && ctx.bc->chip_class == CAYMAN)
1607 cm_bytecode_add_cf_end(ctx.bc);
1608
1609 /* check GPR limit - we have 124 = 128 - 4
1610 * (4 are reserved as alu clause temporary registers) */
1611 if (ctx.bc->ngpr > 124) {
1612 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1613 r = -ENOMEM;
1614 goto out_err;
1615 }
1616
1617 free(ctx.literals);
1618 tgsi_parse_free(&ctx.parse);
1619 return 0;
1620 out_err:
1621 free(ctx.literals);
1622 tgsi_parse_free(&ctx.parse);
1623 return r;
1624 }
1625
1626 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1627 {
1628 R600_ERR("%s tgsi opcode unsupported\n",
1629 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1630 return -EINVAL;
1631 }
1632
1633 static int tgsi_end(struct r600_shader_ctx *ctx)
1634 {
1635 return 0;
1636 }
1637
1638 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1639 const struct r600_shader_src *shader_src,
1640 unsigned chan)
1641 {
1642 bc_src->sel = shader_src->sel;
1643 bc_src->chan = shader_src->swizzle[chan];
1644 bc_src->neg = shader_src->neg;
1645 bc_src->abs = shader_src->abs;
1646 bc_src->rel = shader_src->rel;
1647 bc_src->value = shader_src->value[bc_src->chan];
1648 bc_src->kc_bank = shader_src->kc_bank;
1649 }
1650
1651 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1652 {
1653 bc_src->abs = 1;
1654 bc_src->neg = 0;
1655 }
1656
1657 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1658 {
1659 bc_src->neg = !bc_src->neg;
1660 }
1661
1662 static void tgsi_dst(struct r600_shader_ctx *ctx,
1663 const struct tgsi_full_dst_register *tgsi_dst,
1664 unsigned swizzle,
1665 struct r600_bytecode_alu_dst *r600_dst)
1666 {
1667 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1668
1669 r600_dst->sel = tgsi_dst->Register.Index;
1670 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1671 r600_dst->chan = swizzle;
1672 r600_dst->write = 1;
1673 if (tgsi_dst->Register.Indirect)
1674 r600_dst->rel = V_SQ_REL_RELATIVE;
1675 if (inst->Instruction.Saturate) {
1676 r600_dst->clamp = 1;
1677 }
1678 }
1679
1680 static int tgsi_last_instruction(unsigned writemask)
1681 {
1682 int i, lasti = 0;
1683
1684 for (i = 0; i < 4; i++) {
1685 if (writemask & (1 << i)) {
1686 lasti = i;
1687 }
1688 }
1689 return lasti;
1690 }
1691
1692 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1693 {
1694 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1695 struct r600_bytecode_alu alu;
1696 int i, j, r;
1697 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1698
1699 for (i = 0; i < lasti + 1; i++) {
1700 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1701 continue;
1702
1703 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1704 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1705
1706 alu.op = ctx->inst_info->op;
1707 if (!swap) {
1708 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1709 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1710 }
1711 } else {
1712 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1713 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1714 }
1715 /* handle some special cases */
1716 switch (ctx->inst_info->tgsi_opcode) {
1717 case TGSI_OPCODE_SUB:
1718 r600_bytecode_src_toggle_neg(&alu.src[1]);
1719 break;
1720 case TGSI_OPCODE_ABS:
1721 r600_bytecode_src_set_abs(&alu.src[0]);
1722 break;
1723 default:
1724 break;
1725 }
1726 if (i == lasti || trans_only) {
1727 alu.last = 1;
1728 }
1729 r = r600_bytecode_add_alu(ctx->bc, &alu);
1730 if (r)
1731 return r;
1732 }
1733 return 0;
1734 }
1735
1736 static int tgsi_op2(struct r600_shader_ctx *ctx)
1737 {
1738 return tgsi_op2_s(ctx, 0, 0);
1739 }
1740
1741 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1742 {
1743 return tgsi_op2_s(ctx, 1, 0);
1744 }
1745
1746 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1747 {
1748 return tgsi_op2_s(ctx, 0, 1);
1749 }
1750
1751 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1752 {
1753 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1754 struct r600_bytecode_alu alu;
1755 int i, r;
1756 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1757
1758 for (i = 0; i < lasti + 1; i++) {
1759
1760 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1761 continue;
1762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1763 alu.op = ctx->inst_info->op;
1764
1765 alu.src[0].sel = V_SQ_ALU_SRC_0;
1766
1767 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1768
1769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1770
1771 if (i == lasti) {
1772 alu.last = 1;
1773 }
1774 r = r600_bytecode_add_alu(ctx->bc, &alu);
1775 if (r)
1776 return r;
1777 }
1778 return 0;
1779
1780 }
1781
1782 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1783 {
1784 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1785 int i, j, r;
1786 struct r600_bytecode_alu alu;
1787 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1788
1789 for (i = 0 ; i < last_slot; i++) {
1790 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1791 alu.op = ctx->inst_info->op;
1792 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1793 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1794
1795 /* RSQ should take the absolute value of src */
1796 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
1797 r600_bytecode_src_set_abs(&alu.src[j]);
1798 }
1799 }
1800 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1801 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1802
1803 if (i == last_slot - 1)
1804 alu.last = 1;
1805 r = r600_bytecode_add_alu(ctx->bc, &alu);
1806 if (r)
1807 return r;
1808 }
1809 return 0;
1810 }
1811
1812 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1813 {
1814 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1815 int i, j, k, r;
1816 struct r600_bytecode_alu alu;
1817 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1818 for (k = 0; k < last_slot; k++) {
1819 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1820 continue;
1821
1822 for (i = 0 ; i < 4; i++) {
1823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1824 alu.op = ctx->inst_info->op;
1825 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1826 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1827 }
1828 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1829 alu.dst.write = (i == k);
1830 if (i == 3)
1831 alu.last = 1;
1832 r = r600_bytecode_add_alu(ctx->bc, &alu);
1833 if (r)
1834 return r;
1835 }
1836 }
1837 return 0;
1838 }
1839
1840 /*
1841 * r600 - trunc to -PI..PI range
1842 * r700 - normalize by dividing by 2PI
1843 * see fdo bug 27901
1844 */
1845 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1846 {
1847 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1848 static float double_pi = 3.1415926535 * 2;
1849 static float neg_pi = -3.1415926535;
1850
1851 int r;
1852 struct r600_bytecode_alu alu;
1853
1854 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1855 alu.op = ALU_OP3_MULADD;
1856 alu.is_op3 = 1;
1857
1858 alu.dst.chan = 0;
1859 alu.dst.sel = ctx->temp_reg;
1860 alu.dst.write = 1;
1861
1862 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1863
1864 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1865 alu.src[1].chan = 0;
1866 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1867 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1868 alu.src[2].chan = 0;
1869 alu.last = 1;
1870 r = r600_bytecode_add_alu(ctx->bc, &alu);
1871 if (r)
1872 return r;
1873
1874 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1875 alu.op = ALU_OP1_FRACT;
1876
1877 alu.dst.chan = 0;
1878 alu.dst.sel = ctx->temp_reg;
1879 alu.dst.write = 1;
1880
1881 alu.src[0].sel = ctx->temp_reg;
1882 alu.src[0].chan = 0;
1883 alu.last = 1;
1884 r = r600_bytecode_add_alu(ctx->bc, &alu);
1885 if (r)
1886 return r;
1887
1888 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1889 alu.op = ALU_OP3_MULADD;
1890 alu.is_op3 = 1;
1891
1892 alu.dst.chan = 0;
1893 alu.dst.sel = ctx->temp_reg;
1894 alu.dst.write = 1;
1895
1896 alu.src[0].sel = ctx->temp_reg;
1897 alu.src[0].chan = 0;
1898
1899 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1900 alu.src[1].chan = 0;
1901 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1902 alu.src[2].chan = 0;
1903
1904 if (ctx->bc->chip_class == R600) {
1905 alu.src[1].value = *(uint32_t *)&double_pi;
1906 alu.src[2].value = *(uint32_t *)&neg_pi;
1907 } else {
1908 alu.src[1].sel = V_SQ_ALU_SRC_1;
1909 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1910 alu.src[2].neg = 1;
1911 }
1912
1913 alu.last = 1;
1914 r = r600_bytecode_add_alu(ctx->bc, &alu);
1915 if (r)
1916 return r;
1917 return 0;
1918 }
1919
1920 static int cayman_trig(struct r600_shader_ctx *ctx)
1921 {
1922 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1923 struct r600_bytecode_alu alu;
1924 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1925 int i, r;
1926
1927 r = tgsi_setup_trig(ctx);
1928 if (r)
1929 return r;
1930
1931
1932 for (i = 0; i < last_slot; i++) {
1933 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1934 alu.op = ctx->inst_info->op;
1935 alu.dst.chan = i;
1936
1937 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1938 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1939
1940 alu.src[0].sel = ctx->temp_reg;
1941 alu.src[0].chan = 0;
1942 if (i == last_slot - 1)
1943 alu.last = 1;
1944 r = r600_bytecode_add_alu(ctx->bc, &alu);
1945 if (r)
1946 return r;
1947 }
1948 return 0;
1949 }
1950
1951 static int tgsi_trig(struct r600_shader_ctx *ctx)
1952 {
1953 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1954 struct r600_bytecode_alu alu;
1955 int i, r;
1956 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1957
1958 r = tgsi_setup_trig(ctx);
1959 if (r)
1960 return r;
1961
1962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1963 alu.op = ctx->inst_info->op;
1964 alu.dst.chan = 0;
1965 alu.dst.sel = ctx->temp_reg;
1966 alu.dst.write = 1;
1967
1968 alu.src[0].sel = ctx->temp_reg;
1969 alu.src[0].chan = 0;
1970 alu.last = 1;
1971 r = r600_bytecode_add_alu(ctx->bc, &alu);
1972 if (r)
1973 return r;
1974
1975 /* replicate result */
1976 for (i = 0; i < lasti + 1; i++) {
1977 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1978 continue;
1979
1980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1981 alu.op = ALU_OP1_MOV;
1982
1983 alu.src[0].sel = ctx->temp_reg;
1984 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1985 if (i == lasti)
1986 alu.last = 1;
1987 r = r600_bytecode_add_alu(ctx->bc, &alu);
1988 if (r)
1989 return r;
1990 }
1991 return 0;
1992 }
1993
1994 static int tgsi_scs(struct r600_shader_ctx *ctx)
1995 {
1996 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1997 struct r600_bytecode_alu alu;
1998 int i, r;
1999
2000 /* We'll only need the trig stuff if we are going to write to the
2001 * X or Y components of the destination vector.
2002 */
2003 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2004 r = tgsi_setup_trig(ctx);
2005 if (r)
2006 return r;
2007 }
2008
2009 /* dst.x = COS */
2010 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2011 if (ctx->bc->chip_class == CAYMAN) {
2012 for (i = 0 ; i < 3; i++) {
2013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2014 alu.op = ALU_OP1_COS;
2015 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2016
2017 if (i == 0)
2018 alu.dst.write = 1;
2019 else
2020 alu.dst.write = 0;
2021 alu.src[0].sel = ctx->temp_reg;
2022 alu.src[0].chan = 0;
2023 if (i == 2)
2024 alu.last = 1;
2025 r = r600_bytecode_add_alu(ctx->bc, &alu);
2026 if (r)
2027 return r;
2028 }
2029 } else {
2030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2031 alu.op = ALU_OP1_COS;
2032 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2033
2034 alu.src[0].sel = ctx->temp_reg;
2035 alu.src[0].chan = 0;
2036 alu.last = 1;
2037 r = r600_bytecode_add_alu(ctx->bc, &alu);
2038 if (r)
2039 return r;
2040 }
2041 }
2042
2043 /* dst.y = SIN */
2044 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2045 if (ctx->bc->chip_class == CAYMAN) {
2046 for (i = 0 ; i < 3; i++) {
2047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2048 alu.op = ALU_OP1_SIN;
2049 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2050 if (i == 1)
2051 alu.dst.write = 1;
2052 else
2053 alu.dst.write = 0;
2054 alu.src[0].sel = ctx->temp_reg;
2055 alu.src[0].chan = 0;
2056 if (i == 2)
2057 alu.last = 1;
2058 r = r600_bytecode_add_alu(ctx->bc, &alu);
2059 if (r)
2060 return r;
2061 }
2062 } else {
2063 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2064 alu.op = ALU_OP1_SIN;
2065 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2066
2067 alu.src[0].sel = ctx->temp_reg;
2068 alu.src[0].chan = 0;
2069 alu.last = 1;
2070 r = r600_bytecode_add_alu(ctx->bc, &alu);
2071 if (r)
2072 return r;
2073 }
2074 }
2075
2076 /* dst.z = 0.0; */
2077 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2079
2080 alu.op = ALU_OP1_MOV;
2081
2082 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2083
2084 alu.src[0].sel = V_SQ_ALU_SRC_0;
2085 alu.src[0].chan = 0;
2086
2087 alu.last = 1;
2088
2089 r = r600_bytecode_add_alu(ctx->bc, &alu);
2090 if (r)
2091 return r;
2092 }
2093
2094 /* dst.w = 1.0; */
2095 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2097
2098 alu.op = ALU_OP1_MOV;
2099
2100 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2101
2102 alu.src[0].sel = V_SQ_ALU_SRC_1;
2103 alu.src[0].chan = 0;
2104
2105 alu.last = 1;
2106
2107 r = r600_bytecode_add_alu(ctx->bc, &alu);
2108 if (r)
2109 return r;
2110 }
2111
2112 return 0;
2113 }
2114
2115 static int tgsi_kill(struct r600_shader_ctx *ctx)
2116 {
2117 struct r600_bytecode_alu alu;
2118 int i, r;
2119
2120 for (i = 0; i < 4; i++) {
2121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2122 alu.op = ctx->inst_info->op;
2123
2124 alu.dst.chan = i;
2125
2126 alu.src[0].sel = V_SQ_ALU_SRC_0;
2127
2128 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2129 alu.src[1].sel = V_SQ_ALU_SRC_1;
2130 alu.src[1].neg = 1;
2131 } else {
2132 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2133 }
2134 if (i == 3) {
2135 alu.last = 1;
2136 }
2137 r = r600_bytecode_add_alu(ctx->bc, &alu);
2138 if (r)
2139 return r;
2140 }
2141
2142 /* kill must be last in ALU */
2143 ctx->bc->force_add_cf = 1;
2144 ctx->shader->uses_kill = TRUE;
2145 return 0;
2146 }
2147
2148 static int tgsi_lit(struct r600_shader_ctx *ctx)
2149 {
2150 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2151 struct r600_bytecode_alu alu;
2152 int r;
2153
2154 /* tmp.x = max(src.y, 0.0) */
2155 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2156 alu.op = ALU_OP2_MAX;
2157 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2158 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2159 alu.src[1].chan = 1;
2160
2161 alu.dst.sel = ctx->temp_reg;
2162 alu.dst.chan = 0;
2163 alu.dst.write = 1;
2164
2165 alu.last = 1;
2166 r = r600_bytecode_add_alu(ctx->bc, &alu);
2167 if (r)
2168 return r;
2169
2170 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2171 {
2172 int chan;
2173 int sel;
2174 int i;
2175
2176 if (ctx->bc->chip_class == CAYMAN) {
2177 for (i = 0; i < 3; i++) {
2178 /* tmp.z = log(tmp.x) */
2179 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2180 alu.op = ALU_OP1_LOG_CLAMPED;
2181 alu.src[0].sel = ctx->temp_reg;
2182 alu.src[0].chan = 0;
2183 alu.dst.sel = ctx->temp_reg;
2184 alu.dst.chan = i;
2185 if (i == 2) {
2186 alu.dst.write = 1;
2187 alu.last = 1;
2188 } else
2189 alu.dst.write = 0;
2190
2191 r = r600_bytecode_add_alu(ctx->bc, &alu);
2192 if (r)
2193 return r;
2194 }
2195 } else {
2196 /* tmp.z = log(tmp.x) */
2197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2198 alu.op = ALU_OP1_LOG_CLAMPED;
2199 alu.src[0].sel = ctx->temp_reg;
2200 alu.src[0].chan = 0;
2201 alu.dst.sel = ctx->temp_reg;
2202 alu.dst.chan = 2;
2203 alu.dst.write = 1;
2204 alu.last = 1;
2205 r = r600_bytecode_add_alu(ctx->bc, &alu);
2206 if (r)
2207 return r;
2208 }
2209
2210 chan = alu.dst.chan;
2211 sel = alu.dst.sel;
2212
2213 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2214 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2215 alu.op = ALU_OP3_MUL_LIT;
2216 alu.src[0].sel = sel;
2217 alu.src[0].chan = chan;
2218 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2219 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2220 alu.dst.sel = ctx->temp_reg;
2221 alu.dst.chan = 0;
2222 alu.dst.write = 1;
2223 alu.is_op3 = 1;
2224 alu.last = 1;
2225 r = r600_bytecode_add_alu(ctx->bc, &alu);
2226 if (r)
2227 return r;
2228
2229 if (ctx->bc->chip_class == CAYMAN) {
2230 for (i = 0; i < 3; i++) {
2231 /* dst.z = exp(tmp.x) */
2232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2233 alu.op = ALU_OP1_EXP_IEEE;
2234 alu.src[0].sel = ctx->temp_reg;
2235 alu.src[0].chan = 0;
2236 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2237 if (i == 2) {
2238 alu.dst.write = 1;
2239 alu.last = 1;
2240 } else
2241 alu.dst.write = 0;
2242 r = r600_bytecode_add_alu(ctx->bc, &alu);
2243 if (r)
2244 return r;
2245 }
2246 } else {
2247 /* dst.z = exp(tmp.x) */
2248 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2249 alu.op = ALU_OP1_EXP_IEEE;
2250 alu.src[0].sel = ctx->temp_reg;
2251 alu.src[0].chan = 0;
2252 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2253 alu.last = 1;
2254 r = r600_bytecode_add_alu(ctx->bc, &alu);
2255 if (r)
2256 return r;
2257 }
2258 }
2259
2260 /* dst.x, <- 1.0 */
2261 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2262 alu.op = ALU_OP1_MOV;
2263 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2264 alu.src[0].chan = 0;
2265 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2266 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2267 r = r600_bytecode_add_alu(ctx->bc, &alu);
2268 if (r)
2269 return r;
2270
2271 /* dst.y = max(src.x, 0.0) */
2272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2273 alu.op = ALU_OP2_MAX;
2274 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2275 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2276 alu.src[1].chan = 0;
2277 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2278 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2279 r = r600_bytecode_add_alu(ctx->bc, &alu);
2280 if (r)
2281 return r;
2282
2283 /* dst.w, <- 1.0 */
2284 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2285 alu.op = ALU_OP1_MOV;
2286 alu.src[0].sel = V_SQ_ALU_SRC_1;
2287 alu.src[0].chan = 0;
2288 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2289 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2290 alu.last = 1;
2291 r = r600_bytecode_add_alu(ctx->bc, &alu);
2292 if (r)
2293 return r;
2294
2295 return 0;
2296 }
2297
2298 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2299 {
2300 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2301 struct r600_bytecode_alu alu;
2302 int i, r;
2303
2304 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2305
2306 /* XXX:
2307 * For state trackers other than OpenGL, we'll want to use
2308 * _RECIPSQRT_IEEE instead.
2309 */
2310 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2311
2312 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2313 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2314 r600_bytecode_src_set_abs(&alu.src[i]);
2315 }
2316 alu.dst.sel = ctx->temp_reg;
2317 alu.dst.write = 1;
2318 alu.last = 1;
2319 r = r600_bytecode_add_alu(ctx->bc, &alu);
2320 if (r)
2321 return r;
2322 /* replicate result */
2323 return tgsi_helper_tempx_replicate(ctx);
2324 }
2325
2326 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2327 {
2328 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2329 struct r600_bytecode_alu alu;
2330 int i, r;
2331
2332 for (i = 0; i < 4; i++) {
2333 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2334 alu.src[0].sel = ctx->temp_reg;
2335 alu.op = ALU_OP1_MOV;
2336 alu.dst.chan = i;
2337 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2338 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2339 if (i == 3)
2340 alu.last = 1;
2341 r = r600_bytecode_add_alu(ctx->bc, &alu);
2342 if (r)
2343 return r;
2344 }
2345 return 0;
2346 }
2347
2348 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2349 {
2350 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2351 struct r600_bytecode_alu alu;
2352 int i, r;
2353
2354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2355 alu.op = ctx->inst_info->op;
2356 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2357 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2358 }
2359 alu.dst.sel = ctx->temp_reg;
2360 alu.dst.write = 1;
2361 alu.last = 1;
2362 r = r600_bytecode_add_alu(ctx->bc, &alu);
2363 if (r)
2364 return r;
2365 /* replicate result */
2366 return tgsi_helper_tempx_replicate(ctx);
2367 }
2368
2369 static int cayman_pow(struct r600_shader_ctx *ctx)
2370 {
2371 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2372 int i, r;
2373 struct r600_bytecode_alu alu;
2374 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2375
2376 for (i = 0; i < 3; i++) {
2377 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2378 alu.op = ALU_OP1_LOG_IEEE;
2379 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2380 alu.dst.sel = ctx->temp_reg;
2381 alu.dst.chan = i;
2382 alu.dst.write = 1;
2383 if (i == 2)
2384 alu.last = 1;
2385 r = r600_bytecode_add_alu(ctx->bc, &alu);
2386 if (r)
2387 return r;
2388 }
2389
2390 /* b * LOG2(a) */
2391 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2392 alu.op = ALU_OP2_MUL;
2393 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2394 alu.src[1].sel = ctx->temp_reg;
2395 alu.dst.sel = ctx->temp_reg;
2396 alu.dst.write = 1;
2397 alu.last = 1;
2398 r = r600_bytecode_add_alu(ctx->bc, &alu);
2399 if (r)
2400 return r;
2401
2402 for (i = 0; i < last_slot; i++) {
2403 /* POW(a,b) = EXP2(b * LOG2(a))*/
2404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2405 alu.op = ALU_OP1_EXP_IEEE;
2406 alu.src[0].sel = ctx->temp_reg;
2407
2408 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2409 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2410 if (i == last_slot - 1)
2411 alu.last = 1;
2412 r = r600_bytecode_add_alu(ctx->bc, &alu);
2413 if (r)
2414 return r;
2415 }
2416 return 0;
2417 }
2418
2419 static int tgsi_pow(struct r600_shader_ctx *ctx)
2420 {
2421 struct r600_bytecode_alu alu;
2422 int r;
2423
2424 /* LOG2(a) */
2425 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2426 alu.op = ALU_OP1_LOG_IEEE;
2427 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2428 alu.dst.sel = ctx->temp_reg;
2429 alu.dst.write = 1;
2430 alu.last = 1;
2431 r = r600_bytecode_add_alu(ctx->bc, &alu);
2432 if (r)
2433 return r;
2434 /* b * LOG2(a) */
2435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2436 alu.op = ALU_OP2_MUL;
2437 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2438 alu.src[1].sel = ctx->temp_reg;
2439 alu.dst.sel = ctx->temp_reg;
2440 alu.dst.write = 1;
2441 alu.last = 1;
2442 r = r600_bytecode_add_alu(ctx->bc, &alu);
2443 if (r)
2444 return r;
2445 /* POW(a,b) = EXP2(b * LOG2(a))*/
2446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2447 alu.op = ALU_OP1_EXP_IEEE;
2448 alu.src[0].sel = ctx->temp_reg;
2449 alu.dst.sel = ctx->temp_reg;
2450 alu.dst.write = 1;
2451 alu.last = 1;
2452 r = r600_bytecode_add_alu(ctx->bc, &alu);
2453 if (r)
2454 return r;
2455 return tgsi_helper_tempx_replicate(ctx);
2456 }
2457
2458 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2459 {
2460 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2461 struct r600_bytecode_alu alu;
2462 int i, r, j;
2463 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2464 int tmp0 = ctx->temp_reg;
2465 int tmp1 = r600_get_temp(ctx);
2466 int tmp2 = r600_get_temp(ctx);
2467 int tmp3 = r600_get_temp(ctx);
2468 /* Unsigned path:
2469 *
2470 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2471 *
2472 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2473 * 2. tmp0.z = lo (tmp0.x * src2)
2474 * 3. tmp0.w = -tmp0.z
2475 * 4. tmp0.y = hi (tmp0.x * src2)
2476 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2477 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2478 * 7. tmp1.x = tmp0.x - tmp0.w
2479 * 8. tmp1.y = tmp0.x + tmp0.w
2480 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2481 * 10. tmp0.z = hi(tmp0.x * src1) = q
2482 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2483 *
2484 * 12. tmp0.w = src1 - tmp0.y = r
2485 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2486 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2487 *
2488 * if DIV
2489 *
2490 * 15. tmp1.z = tmp0.z + 1 = q + 1
2491 * 16. tmp1.w = tmp0.z - 1 = q - 1
2492 *
2493 * else MOD
2494 *
2495 * 15. tmp1.z = tmp0.w - src2 = r - src2
2496 * 16. tmp1.w = tmp0.w + src2 = r + src2
2497 *
2498 * endif
2499 *
2500 * 17. tmp1.x = tmp1.x & tmp1.y
2501 *
2502 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2503 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2504 *
2505 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2506 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2507 *
2508 * Signed path:
2509 *
2510 * Same as unsigned, using abs values of the operands,
2511 * and fixing the sign of the result in the end.
2512 */
2513
2514 for (i = 0; i < 4; i++) {
2515 if (!(write_mask & (1<<i)))
2516 continue;
2517
2518 if (signed_op) {
2519
2520 /* tmp2.x = -src0 */
2521 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2522 alu.op = ALU_OP2_SUB_INT;
2523
2524 alu.dst.sel = tmp2;
2525 alu.dst.chan = 0;
2526 alu.dst.write = 1;
2527
2528 alu.src[0].sel = V_SQ_ALU_SRC_0;
2529
2530 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2531
2532 alu.last = 1;
2533 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2534 return r;
2535
2536 /* tmp2.y = -src1 */
2537 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2538 alu.op = ALU_OP2_SUB_INT;
2539
2540 alu.dst.sel = tmp2;
2541 alu.dst.chan = 1;
2542 alu.dst.write = 1;
2543
2544 alu.src[0].sel = V_SQ_ALU_SRC_0;
2545
2546 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2547
2548 alu.last = 1;
2549 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2550 return r;
2551
2552 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2553 /* it will be a sign of the quotient */
2554 if (!mod) {
2555
2556 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2557 alu.op = ALU_OP2_XOR_INT;
2558
2559 alu.dst.sel = tmp2;
2560 alu.dst.chan = 2;
2561 alu.dst.write = 1;
2562
2563 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2564 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2565
2566 alu.last = 1;
2567 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2568 return r;
2569 }
2570
2571 /* tmp2.x = |src0| */
2572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2573 alu.op = ALU_OP3_CNDGE_INT;
2574 alu.is_op3 = 1;
2575
2576 alu.dst.sel = tmp2;
2577 alu.dst.chan = 0;
2578 alu.dst.write = 1;
2579
2580 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2581 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2582 alu.src[2].sel = tmp2;
2583 alu.src[2].chan = 0;
2584
2585 alu.last = 1;
2586 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2587 return r;
2588
2589 /* tmp2.y = |src1| */
2590 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2591 alu.op = ALU_OP3_CNDGE_INT;
2592 alu.is_op3 = 1;
2593
2594 alu.dst.sel = tmp2;
2595 alu.dst.chan = 1;
2596 alu.dst.write = 1;
2597
2598 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2599 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2600 alu.src[2].sel = tmp2;
2601 alu.src[2].chan = 1;
2602
2603 alu.last = 1;
2604 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2605 return r;
2606
2607 }
2608
2609 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2610 if (ctx->bc->chip_class == CAYMAN) {
2611 /* tmp3.x = u2f(src2) */
2612 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2613 alu.op = ALU_OP1_UINT_TO_FLT;
2614
2615 alu.dst.sel = tmp3;
2616 alu.dst.chan = 0;
2617 alu.dst.write = 1;
2618
2619 if (signed_op) {
2620 alu.src[0].sel = tmp2;
2621 alu.src[0].chan = 1;
2622 } else {
2623 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2624 }
2625
2626 alu.last = 1;
2627 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2628 return r;
2629
2630 /* tmp0.x = recip(tmp3.x) */
2631 for (j = 0 ; j < 3; j++) {
2632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2633 alu.op = ALU_OP1_RECIP_IEEE;
2634
2635 alu.dst.sel = tmp0;
2636 alu.dst.chan = j;
2637 alu.dst.write = (j == 0);
2638
2639 alu.src[0].sel = tmp3;
2640 alu.src[0].chan = 0;
2641
2642 if (j == 2)
2643 alu.last = 1;
2644 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2645 return r;
2646 }
2647
2648 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2649 alu.op = ALU_OP2_MUL;
2650
2651 alu.src[0].sel = tmp0;
2652 alu.src[0].chan = 0;
2653
2654 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2655 alu.src[1].value = 0x4f800000;
2656
2657 alu.dst.sel = tmp3;
2658 alu.dst.write = 1;
2659 alu.last = 1;
2660 r = r600_bytecode_add_alu(ctx->bc, &alu);
2661 if (r)
2662 return r;
2663
2664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2665 alu.op = ALU_OP1_FLT_TO_UINT;
2666
2667 alu.dst.sel = tmp0;
2668 alu.dst.chan = 0;
2669 alu.dst.write = 1;
2670
2671 alu.src[0].sel = tmp3;
2672 alu.src[0].chan = 0;
2673
2674 alu.last = 1;
2675 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2676 return r;
2677
2678 } else {
2679 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2680 alu.op = ALU_OP1_RECIP_UINT;
2681
2682 alu.dst.sel = tmp0;
2683 alu.dst.chan = 0;
2684 alu.dst.write = 1;
2685
2686 if (signed_op) {
2687 alu.src[0].sel = tmp2;
2688 alu.src[0].chan = 1;
2689 } else {
2690 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2691 }
2692
2693 alu.last = 1;
2694 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2695 return r;
2696 }
2697
2698 /* 2. tmp0.z = lo (tmp0.x * src2) */
2699 if (ctx->bc->chip_class == CAYMAN) {
2700 for (j = 0 ; j < 4; j++) {
2701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2702 alu.op = ALU_OP2_MULLO_UINT;
2703
2704 alu.dst.sel = tmp0;
2705 alu.dst.chan = j;
2706 alu.dst.write = (j == 2);
2707
2708 alu.src[0].sel = tmp0;
2709 alu.src[0].chan = 0;
2710 if (signed_op) {
2711 alu.src[1].sel = tmp2;
2712 alu.src[1].chan = 1;
2713 } else {
2714 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2715 }
2716
2717 alu.last = (j == 3);
2718 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2719 return r;
2720 }
2721 } else {
2722 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2723 alu.op = ALU_OP2_MULLO_UINT;
2724
2725 alu.dst.sel = tmp0;
2726 alu.dst.chan = 2;
2727 alu.dst.write = 1;
2728
2729 alu.src[0].sel = tmp0;
2730 alu.src[0].chan = 0;
2731 if (signed_op) {
2732 alu.src[1].sel = tmp2;
2733 alu.src[1].chan = 1;
2734 } else {
2735 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2736 }
2737
2738 alu.last = 1;
2739 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2740 return r;
2741 }
2742
2743 /* 3. tmp0.w = -tmp0.z */
2744 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2745 alu.op = ALU_OP2_SUB_INT;
2746
2747 alu.dst.sel = tmp0;
2748 alu.dst.chan = 3;
2749 alu.dst.write = 1;
2750
2751 alu.src[0].sel = V_SQ_ALU_SRC_0;
2752 alu.src[1].sel = tmp0;
2753 alu.src[1].chan = 2;
2754
2755 alu.last = 1;
2756 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2757 return r;
2758
2759 /* 4. tmp0.y = hi (tmp0.x * src2) */
2760 if (ctx->bc->chip_class == CAYMAN) {
2761 for (j = 0 ; j < 4; j++) {
2762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2763 alu.op = ALU_OP2_MULHI_UINT;
2764
2765 alu.dst.sel = tmp0;
2766 alu.dst.chan = j;
2767 alu.dst.write = (j == 1);
2768
2769 alu.src[0].sel = tmp0;
2770 alu.src[0].chan = 0;
2771
2772 if (signed_op) {
2773 alu.src[1].sel = tmp2;
2774 alu.src[1].chan = 1;
2775 } else {
2776 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2777 }
2778 alu.last = (j == 3);
2779 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2780 return r;
2781 }
2782 } else {
2783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2784 alu.op = ALU_OP2_MULHI_UINT;
2785
2786 alu.dst.sel = tmp0;
2787 alu.dst.chan = 1;
2788 alu.dst.write = 1;
2789
2790 alu.src[0].sel = tmp0;
2791 alu.src[0].chan = 0;
2792
2793 if (signed_op) {
2794 alu.src[1].sel = tmp2;
2795 alu.src[1].chan = 1;
2796 } else {
2797 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2798 }
2799
2800 alu.last = 1;
2801 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2802 return r;
2803 }
2804
2805 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2807 alu.op = ALU_OP3_CNDE_INT;
2808 alu.is_op3 = 1;
2809
2810 alu.dst.sel = tmp0;
2811 alu.dst.chan = 2;
2812 alu.dst.write = 1;
2813
2814 alu.src[0].sel = tmp0;
2815 alu.src[0].chan = 1;
2816 alu.src[1].sel = tmp0;
2817 alu.src[1].chan = 3;
2818 alu.src[2].sel = tmp0;
2819 alu.src[2].chan = 2;
2820
2821 alu.last = 1;
2822 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2823 return r;
2824
2825 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2826 if (ctx->bc->chip_class == CAYMAN) {
2827 for (j = 0 ; j < 4; j++) {
2828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2829 alu.op = ALU_OP2_MULHI_UINT;
2830
2831 alu.dst.sel = tmp0;
2832 alu.dst.chan = j;
2833 alu.dst.write = (j == 3);
2834
2835 alu.src[0].sel = tmp0;
2836 alu.src[0].chan = 2;
2837
2838 alu.src[1].sel = tmp0;
2839 alu.src[1].chan = 0;
2840
2841 alu.last = (j == 3);
2842 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2843 return r;
2844 }
2845 } else {
2846 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2847 alu.op = ALU_OP2_MULHI_UINT;
2848
2849 alu.dst.sel = tmp0;
2850 alu.dst.chan = 3;
2851 alu.dst.write = 1;
2852
2853 alu.src[0].sel = tmp0;
2854 alu.src[0].chan = 2;
2855
2856 alu.src[1].sel = tmp0;
2857 alu.src[1].chan = 0;
2858
2859 alu.last = 1;
2860 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2861 return r;
2862 }
2863
2864 /* 7. tmp1.x = tmp0.x - tmp0.w */
2865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2866 alu.op = ALU_OP2_SUB_INT;
2867
2868 alu.dst.sel = tmp1;
2869 alu.dst.chan = 0;
2870 alu.dst.write = 1;
2871
2872 alu.src[0].sel = tmp0;
2873 alu.src[0].chan = 0;
2874 alu.src[1].sel = tmp0;
2875 alu.src[1].chan = 3;
2876
2877 alu.last = 1;
2878 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2879 return r;
2880
2881 /* 8. tmp1.y = tmp0.x + tmp0.w */
2882 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2883 alu.op = ALU_OP2_ADD_INT;
2884
2885 alu.dst.sel = tmp1;
2886 alu.dst.chan = 1;
2887 alu.dst.write = 1;
2888
2889 alu.src[0].sel = tmp0;
2890 alu.src[0].chan = 0;
2891 alu.src[1].sel = tmp0;
2892 alu.src[1].chan = 3;
2893
2894 alu.last = 1;
2895 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2896 return r;
2897
2898 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2900 alu.op = ALU_OP3_CNDE_INT;
2901 alu.is_op3 = 1;
2902
2903 alu.dst.sel = tmp0;
2904 alu.dst.chan = 0;
2905 alu.dst.write = 1;
2906
2907 alu.src[0].sel = tmp0;
2908 alu.src[0].chan = 1;
2909 alu.src[1].sel = tmp1;
2910 alu.src[1].chan = 1;
2911 alu.src[2].sel = tmp1;
2912 alu.src[2].chan = 0;
2913
2914 alu.last = 1;
2915 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2916 return r;
2917
2918 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2919 if (ctx->bc->chip_class == CAYMAN) {
2920 for (j = 0 ; j < 4; j++) {
2921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2922 alu.op = ALU_OP2_MULHI_UINT;
2923
2924 alu.dst.sel = tmp0;
2925 alu.dst.chan = j;
2926 alu.dst.write = (j == 2);
2927
2928 alu.src[0].sel = tmp0;
2929 alu.src[0].chan = 0;
2930
2931 if (signed_op) {
2932 alu.src[1].sel = tmp2;
2933 alu.src[1].chan = 0;
2934 } else {
2935 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2936 }
2937
2938 alu.last = (j == 3);
2939 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2940 return r;
2941 }
2942 } else {
2943 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2944 alu.op = ALU_OP2_MULHI_UINT;
2945
2946 alu.dst.sel = tmp0;
2947 alu.dst.chan = 2;
2948 alu.dst.write = 1;
2949
2950 alu.src[0].sel = tmp0;
2951 alu.src[0].chan = 0;
2952
2953 if (signed_op) {
2954 alu.src[1].sel = tmp2;
2955 alu.src[1].chan = 0;
2956 } else {
2957 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2958 }
2959
2960 alu.last = 1;
2961 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2962 return r;
2963 }
2964
2965 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2966 if (ctx->bc->chip_class == CAYMAN) {
2967 for (j = 0 ; j < 4; j++) {
2968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2969 alu.op = ALU_OP2_MULLO_UINT;
2970
2971 alu.dst.sel = tmp0;
2972 alu.dst.chan = j;
2973 alu.dst.write = (j == 1);
2974
2975 if (signed_op) {
2976 alu.src[0].sel = tmp2;
2977 alu.src[0].chan = 1;
2978 } else {
2979 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2980 }
2981
2982 alu.src[1].sel = tmp0;
2983 alu.src[1].chan = 2;
2984
2985 alu.last = (j == 3);
2986 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2987 return r;
2988 }
2989 } else {
2990 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2991 alu.op = ALU_OP2_MULLO_UINT;
2992
2993 alu.dst.sel = tmp0;
2994 alu.dst.chan = 1;
2995 alu.dst.write = 1;
2996
2997 if (signed_op) {
2998 alu.src[0].sel = tmp2;
2999 alu.src[0].chan = 1;
3000 } else {
3001 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3002 }
3003
3004 alu.src[1].sel = tmp0;
3005 alu.src[1].chan = 2;
3006
3007 alu.last = 1;
3008 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3009 return r;
3010 }
3011
3012 /* 12. tmp0.w = src1 - tmp0.y = r */
3013 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3014 alu.op = ALU_OP2_SUB_INT;
3015
3016 alu.dst.sel = tmp0;
3017 alu.dst.chan = 3;
3018 alu.dst.write = 1;
3019
3020 if (signed_op) {
3021 alu.src[0].sel = tmp2;
3022 alu.src[0].chan = 0;
3023 } else {
3024 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3025 }
3026
3027 alu.src[1].sel = tmp0;
3028 alu.src[1].chan = 1;
3029
3030 alu.last = 1;
3031 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3032 return r;
3033
3034 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3035 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3036 alu.op = ALU_OP2_SETGE_UINT;
3037
3038 alu.dst.sel = tmp1;
3039 alu.dst.chan = 0;
3040 alu.dst.write = 1;
3041
3042 alu.src[0].sel = tmp0;
3043 alu.src[0].chan = 3;
3044 if (signed_op) {
3045 alu.src[1].sel = tmp2;
3046 alu.src[1].chan = 1;
3047 } else {
3048 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3049 }
3050
3051 alu.last = 1;
3052 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3053 return r;
3054
3055 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3057 alu.op = ALU_OP2_SETGE_UINT;
3058
3059 alu.dst.sel = tmp1;
3060 alu.dst.chan = 1;
3061 alu.dst.write = 1;
3062
3063 if (signed_op) {
3064 alu.src[0].sel = tmp2;
3065 alu.src[0].chan = 0;
3066 } else {
3067 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3068 }
3069
3070 alu.src[1].sel = tmp0;
3071 alu.src[1].chan = 1;
3072
3073 alu.last = 1;
3074 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3075 return r;
3076
3077 if (mod) { /* UMOD */
3078
3079 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3080 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3081 alu.op = ALU_OP2_SUB_INT;
3082
3083 alu.dst.sel = tmp1;
3084 alu.dst.chan = 2;
3085 alu.dst.write = 1;
3086
3087 alu.src[0].sel = tmp0;
3088 alu.src[0].chan = 3;
3089
3090 if (signed_op) {
3091 alu.src[1].sel = tmp2;
3092 alu.src[1].chan = 1;
3093 } else {
3094 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3095 }
3096
3097 alu.last = 1;
3098 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3099 return r;
3100
3101 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3103 alu.op = ALU_OP2_ADD_INT;
3104
3105 alu.dst.sel = tmp1;
3106 alu.dst.chan = 3;
3107 alu.dst.write = 1;
3108
3109 alu.src[0].sel = tmp0;
3110 alu.src[0].chan = 3;
3111 if (signed_op) {
3112 alu.src[1].sel = tmp2;
3113 alu.src[1].chan = 1;
3114 } else {
3115 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3116 }
3117
3118 alu.last = 1;
3119 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3120 return r;
3121
3122 } else { /* UDIV */
3123
3124 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3126 alu.op = ALU_OP2_ADD_INT;
3127
3128 alu.dst.sel = tmp1;
3129 alu.dst.chan = 2;
3130 alu.dst.write = 1;
3131
3132 alu.src[0].sel = tmp0;
3133 alu.src[0].chan = 2;
3134 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3135
3136 alu.last = 1;
3137 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3138 return r;
3139
3140 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3141 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3142 alu.op = ALU_OP2_ADD_INT;
3143
3144 alu.dst.sel = tmp1;
3145 alu.dst.chan = 3;
3146 alu.dst.write = 1;
3147
3148 alu.src[0].sel = tmp0;
3149 alu.src[0].chan = 2;
3150 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3151
3152 alu.last = 1;
3153 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3154 return r;
3155
3156 }
3157
3158 /* 17. tmp1.x = tmp1.x & tmp1.y */
3159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3160 alu.op = ALU_OP2_AND_INT;
3161
3162 alu.dst.sel = tmp1;
3163 alu.dst.chan = 0;
3164 alu.dst.write = 1;
3165
3166 alu.src[0].sel = tmp1;
3167 alu.src[0].chan = 0;
3168 alu.src[1].sel = tmp1;
3169 alu.src[1].chan = 1;
3170
3171 alu.last = 1;
3172 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3173 return r;
3174
3175 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3176 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3177 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3178 alu.op = ALU_OP3_CNDE_INT;
3179 alu.is_op3 = 1;
3180
3181 alu.dst.sel = tmp0;
3182 alu.dst.chan = 2;
3183 alu.dst.write = 1;
3184
3185 alu.src[0].sel = tmp1;
3186 alu.src[0].chan = 0;
3187 alu.src[1].sel = tmp0;
3188 alu.src[1].chan = mod ? 3 : 2;
3189 alu.src[2].sel = tmp1;
3190 alu.src[2].chan = 2;
3191
3192 alu.last = 1;
3193 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3194 return r;
3195
3196 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3198 alu.op = ALU_OP3_CNDE_INT;
3199 alu.is_op3 = 1;
3200
3201 if (signed_op) {
3202 alu.dst.sel = tmp0;
3203 alu.dst.chan = 2;
3204 alu.dst.write = 1;
3205 } else {
3206 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3207 }
3208
3209 alu.src[0].sel = tmp1;
3210 alu.src[0].chan = 1;
3211 alu.src[1].sel = tmp1;
3212 alu.src[1].chan = 3;
3213 alu.src[2].sel = tmp0;
3214 alu.src[2].chan = 2;
3215
3216 alu.last = 1;
3217 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3218 return r;
3219
3220 if (signed_op) {
3221
3222 /* fix the sign of the result */
3223
3224 if (mod) {
3225
3226 /* tmp0.x = -tmp0.z */
3227 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3228 alu.op = ALU_OP2_SUB_INT;
3229
3230 alu.dst.sel = tmp0;
3231 alu.dst.chan = 0;
3232 alu.dst.write = 1;
3233
3234 alu.src[0].sel = V_SQ_ALU_SRC_0;
3235 alu.src[1].sel = tmp0;
3236 alu.src[1].chan = 2;
3237
3238 alu.last = 1;
3239 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3240 return r;
3241
3242 /* sign of the remainder is the same as the sign of src0 */
3243 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3245 alu.op = ALU_OP3_CNDGE_INT;
3246 alu.is_op3 = 1;
3247
3248 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3249
3250 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3251 alu.src[1].sel = tmp0;
3252 alu.src[1].chan = 2;
3253 alu.src[2].sel = tmp0;
3254 alu.src[2].chan = 0;
3255
3256 alu.last = 1;
3257 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3258 return r;
3259
3260 } else {
3261
3262 /* tmp0.x = -tmp0.z */
3263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3264 alu.op = ALU_OP2_SUB_INT;
3265
3266 alu.dst.sel = tmp0;
3267 alu.dst.chan = 0;
3268 alu.dst.write = 1;
3269
3270 alu.src[0].sel = V_SQ_ALU_SRC_0;
3271 alu.src[1].sel = tmp0;
3272 alu.src[1].chan = 2;
3273
3274 alu.last = 1;
3275 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3276 return r;
3277
3278 /* fix the quotient sign (same as the sign of src0*src1) */
3279 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3281 alu.op = ALU_OP3_CNDGE_INT;
3282 alu.is_op3 = 1;
3283
3284 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3285
3286 alu.src[0].sel = tmp2;
3287 alu.src[0].chan = 2;
3288 alu.src[1].sel = tmp0;
3289 alu.src[1].chan = 2;
3290 alu.src[2].sel = tmp0;
3291 alu.src[2].chan = 0;
3292
3293 alu.last = 1;
3294 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3295 return r;
3296 }
3297 }
3298 }
3299 return 0;
3300 }
3301
3302 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3303 {
3304 return tgsi_divmod(ctx, 0, 0);
3305 }
3306
3307 static int tgsi_umod(struct r600_shader_ctx *ctx)
3308 {
3309 return tgsi_divmod(ctx, 1, 0);
3310 }
3311
3312 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3313 {
3314 return tgsi_divmod(ctx, 0, 1);
3315 }
3316
3317 static int tgsi_imod(struct r600_shader_ctx *ctx)
3318 {
3319 return tgsi_divmod(ctx, 1, 1);
3320 }
3321
3322
3323 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3324 {
3325 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3326 struct r600_bytecode_alu alu;
3327 int i, r;
3328 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3329 int last_inst = tgsi_last_instruction(write_mask);
3330
3331 for (i = 0; i < 4; i++) {
3332 if (!(write_mask & (1<<i)))
3333 continue;
3334
3335 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3336 alu.op = ALU_OP1_TRUNC;
3337
3338 alu.dst.sel = ctx->temp_reg;
3339 alu.dst.chan = i;
3340 alu.dst.write = 1;
3341
3342 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3343 if (i == last_inst)
3344 alu.last = 1;
3345 r = r600_bytecode_add_alu(ctx->bc, &alu);
3346 if (r)
3347 return r;
3348 }
3349
3350 for (i = 0; i < 4; i++) {
3351 if (!(write_mask & (1<<i)))
3352 continue;
3353
3354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3355 alu.op = ctx->inst_info->op;
3356
3357 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3358
3359 alu.src[0].sel = ctx->temp_reg;
3360 alu.src[0].chan = i;
3361
3362 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3363 alu.last = 1;
3364 r = r600_bytecode_add_alu(ctx->bc, &alu);
3365 if (r)
3366 return r;
3367 }
3368
3369 return 0;
3370 }
3371
3372 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3373 {
3374 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3375 struct r600_bytecode_alu alu;
3376 int i, r;
3377 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3378 int last_inst = tgsi_last_instruction(write_mask);
3379
3380 /* tmp = -src */
3381 for (i = 0; i < 4; i++) {
3382 if (!(write_mask & (1<<i)))
3383 continue;
3384
3385 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3386 alu.op = ALU_OP2_SUB_INT;
3387
3388 alu.dst.sel = ctx->temp_reg;
3389 alu.dst.chan = i;
3390 alu.dst.write = 1;
3391
3392 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3393 alu.src[0].sel = V_SQ_ALU_SRC_0;
3394
3395 if (i == last_inst)
3396 alu.last = 1;
3397 r = r600_bytecode_add_alu(ctx->bc, &alu);
3398 if (r)
3399 return r;
3400 }
3401
3402 /* dst = (src >= 0 ? src : tmp) */
3403 for (i = 0; i < 4; i++) {
3404 if (!(write_mask & (1<<i)))
3405 continue;
3406
3407 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3408 alu.op = ALU_OP3_CNDGE_INT;
3409 alu.is_op3 = 1;
3410 alu.dst.write = 1;
3411
3412 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3413
3414 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3415 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3416 alu.src[2].sel = ctx->temp_reg;
3417 alu.src[2].chan = i;
3418
3419 if (i == last_inst)
3420 alu.last = 1;
3421 r = r600_bytecode_add_alu(ctx->bc, &alu);
3422 if (r)
3423 return r;
3424 }
3425 return 0;
3426 }
3427
3428 static int tgsi_issg(struct r600_shader_ctx *ctx)
3429 {
3430 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3431 struct r600_bytecode_alu alu;
3432 int i, r;
3433 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3434 int last_inst = tgsi_last_instruction(write_mask);
3435
3436 /* tmp = (src >= 0 ? src : -1) */
3437 for (i = 0; i < 4; i++) {
3438 if (!(write_mask & (1<<i)))
3439 continue;
3440
3441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3442 alu.op = ALU_OP3_CNDGE_INT;
3443 alu.is_op3 = 1;
3444
3445 alu.dst.sel = ctx->temp_reg;
3446 alu.dst.chan = i;
3447 alu.dst.write = 1;
3448
3449 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3450 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3451 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3452
3453 if (i == last_inst)
3454 alu.last = 1;
3455 r = r600_bytecode_add_alu(ctx->bc, &alu);
3456 if (r)
3457 return r;
3458 }
3459
3460 /* dst = (tmp > 0 ? 1 : tmp) */
3461 for (i = 0; i < 4; i++) {
3462 if (!(write_mask & (1<<i)))
3463 continue;
3464
3465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3466 alu.op = ALU_OP3_CNDGT_INT;
3467 alu.is_op3 = 1;
3468 alu.dst.write = 1;
3469
3470 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3471
3472 alu.src[0].sel = ctx->temp_reg;
3473 alu.src[0].chan = i;
3474
3475 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3476
3477 alu.src[2].sel = ctx->temp_reg;
3478 alu.src[2].chan = i;
3479
3480 if (i == last_inst)
3481 alu.last = 1;
3482 r = r600_bytecode_add_alu(ctx->bc, &alu);
3483 if (r)
3484 return r;
3485 }
3486 return 0;
3487 }
3488
3489
3490
3491 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3492 {
3493 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3494 struct r600_bytecode_alu alu;
3495 int i, r;
3496
3497 /* tmp = (src > 0 ? 1 : src) */
3498 for (i = 0; i < 4; i++) {
3499 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3500 alu.op = ALU_OP3_CNDGT;
3501 alu.is_op3 = 1;
3502
3503 alu.dst.sel = ctx->temp_reg;
3504 alu.dst.chan = i;
3505
3506 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3507 alu.src[1].sel = V_SQ_ALU_SRC_1;
3508 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3509
3510 if (i == 3)
3511 alu.last = 1;
3512 r = r600_bytecode_add_alu(ctx->bc, &alu);
3513 if (r)
3514 return r;
3515 }
3516
3517 /* dst = (-tmp > 0 ? -1 : tmp) */
3518 for (i = 0; i < 4; i++) {
3519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3520 alu.op = ALU_OP3_CNDGT;
3521 alu.is_op3 = 1;
3522 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3523
3524 alu.src[0].sel = ctx->temp_reg;
3525 alu.src[0].chan = i;
3526 alu.src[0].neg = 1;
3527
3528 alu.src[1].sel = V_SQ_ALU_SRC_1;
3529 alu.src[1].neg = 1;
3530
3531 alu.src[2].sel = ctx->temp_reg;
3532 alu.src[2].chan = i;
3533
3534 if (i == 3)
3535 alu.last = 1;
3536 r = r600_bytecode_add_alu(ctx->bc, &alu);
3537 if (r)
3538 return r;
3539 }
3540 return 0;
3541 }
3542
3543 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3544 {
3545 struct r600_bytecode_alu alu;
3546 int i, r;
3547
3548 for (i = 0; i < 4; i++) {
3549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3550 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3551 alu.op = ALU_OP0_NOP;
3552 alu.dst.chan = i;
3553 } else {
3554 alu.op = ALU_OP1_MOV;
3555 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3556 alu.src[0].sel = ctx->temp_reg;
3557 alu.src[0].chan = i;
3558 }
3559 if (i == 3) {
3560 alu.last = 1;
3561 }
3562 r = r600_bytecode_add_alu(ctx->bc, &alu);
3563 if (r)
3564 return r;
3565 }
3566 return 0;
3567 }
3568
3569 static int tgsi_op3(struct r600_shader_ctx *ctx)
3570 {
3571 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3572 struct r600_bytecode_alu alu;
3573 int i, j, r;
3574 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3575
3576 for (i = 0; i < lasti + 1; i++) {
3577 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3578 continue;
3579
3580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3581 alu.op = ctx->inst_info->op;
3582 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3583 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3584 }
3585
3586 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3587 alu.dst.chan = i;
3588 alu.dst.write = 1;
3589 alu.is_op3 = 1;
3590 if (i == lasti) {
3591 alu.last = 1;
3592 }
3593 r = r600_bytecode_add_alu(ctx->bc, &alu);
3594 if (r)
3595 return r;
3596 }
3597 return 0;
3598 }
3599
3600 static int tgsi_dp(struct r600_shader_ctx *ctx)
3601 {
3602 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3603 struct r600_bytecode_alu alu;
3604 int i, j, r;
3605
3606 for (i = 0; i < 4; i++) {
3607 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3608 alu.op = ctx->inst_info->op;
3609 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3610 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3611 }
3612
3613 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3614 alu.dst.chan = i;
3615 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3616 /* handle some special cases */
3617 switch (ctx->inst_info->tgsi_opcode) {
3618 case TGSI_OPCODE_DP2:
3619 if (i > 1) {
3620 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3621 alu.src[0].chan = alu.src[1].chan = 0;
3622 }
3623 break;
3624 case TGSI_OPCODE_DP3:
3625 if (i > 2) {
3626 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3627 alu.src[0].chan = alu.src[1].chan = 0;
3628 }
3629 break;
3630 case TGSI_OPCODE_DPH:
3631 if (i == 3) {
3632 alu.src[0].sel = V_SQ_ALU_SRC_1;
3633 alu.src[0].chan = 0;
3634 alu.src[0].neg = 0;
3635 }
3636 break;
3637 default:
3638 break;
3639 }
3640 if (i == 3) {
3641 alu.last = 1;
3642 }
3643 r = r600_bytecode_add_alu(ctx->bc, &alu);
3644 if (r)
3645 return r;
3646 }
3647 return 0;
3648 }
3649
3650 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3651 unsigned index)
3652 {
3653 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3654 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3655 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3656 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3657 ctx->src[index].neg || ctx->src[index].abs;
3658 }
3659
3660 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3661 unsigned index)
3662 {
3663 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3664 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3665 }
3666
3667 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3668 {
3669 struct r600_bytecode_vtx vtx;
3670 struct r600_bytecode_alu alu;
3671 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3672 int src_gpr, r, i;
3673 int id = tgsi_tex_get_src_gpr(ctx, 1);
3674
3675 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3676 if (src_requires_loading) {
3677 for (i = 0; i < 4; i++) {
3678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3679 alu.op = ALU_OP1_MOV;
3680 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3681 alu.dst.sel = ctx->temp_reg;
3682 alu.dst.chan = i;
3683 if (i == 3)
3684 alu.last = 1;
3685 alu.dst.write = 1;
3686 r = r600_bytecode_add_alu(ctx->bc, &alu);
3687 if (r)
3688 return r;
3689 }
3690 src_gpr = ctx->temp_reg;
3691 }
3692
3693 memset(&vtx, 0, sizeof(vtx));
3694 vtx.op = FETCH_OP_VFETCH;
3695 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3696 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3697 vtx.src_gpr = src_gpr;
3698 vtx.mega_fetch_count = 16;
3699 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3700 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3701 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3702 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
3703 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
3704 vtx.use_const_fields = 1;
3705 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
3706
3707 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
3708 return r;
3709
3710 if (ctx->bc->chip_class >= EVERGREEN)
3711 return 0;
3712
3713 for (i = 0; i < 4; i++) {
3714 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3715 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3716 continue;
3717
3718 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3719 alu.op = ALU_OP2_AND_INT;
3720
3721 alu.dst.chan = i;
3722 alu.dst.sel = vtx.dst_gpr;
3723 alu.dst.write = 1;
3724
3725 alu.src[0].sel = vtx.dst_gpr;
3726 alu.src[0].chan = i;
3727
3728 alu.src[1].sel = 512 + (id * 2);
3729 alu.src[1].chan = i % 4;
3730 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3731
3732 if (i == lasti)
3733 alu.last = 1;
3734 r = r600_bytecode_add_alu(ctx->bc, &alu);
3735 if (r)
3736 return r;
3737 }
3738
3739 if (inst->Dst[0].Register.WriteMask & 3) {
3740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3741 alu.op = ALU_OP2_OR_INT;
3742
3743 alu.dst.chan = 3;
3744 alu.dst.sel = vtx.dst_gpr;
3745 alu.dst.write = 1;
3746
3747 alu.src[0].sel = vtx.dst_gpr;
3748 alu.src[0].chan = 3;
3749
3750 alu.src[1].sel = 512 + (id * 2) + 1;
3751 alu.src[1].chan = 0;
3752 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3753
3754 alu.last = 1;
3755 r = r600_bytecode_add_alu(ctx->bc, &alu);
3756 if (r)
3757 return r;
3758 }
3759 return 0;
3760 }
3761
3762 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
3763 {
3764 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3765 struct r600_bytecode_alu alu;
3766 int r;
3767 int id = tgsi_tex_get_src_gpr(ctx, 1);
3768
3769 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3770 alu.op = ALU_OP1_MOV;
3771
3772 if (ctx->bc->chip_class >= EVERGREEN) {
3773 alu.src[0].sel = 512 + (id / 4);
3774 alu.src[0].chan = id % 4;
3775 } else {
3776 /* r600 we have them at channel 2 of the second dword */
3777 alu.src[0].sel = 512 + (id * 2) + 1;
3778 alu.src[0].chan = 1;
3779 }
3780 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3781 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3782 alu.last = 1;
3783 r = r600_bytecode_add_alu(ctx->bc, &alu);
3784 if (r)
3785 return r;
3786 return 0;
3787 }
3788
3789 static int tgsi_tex(struct r600_shader_ctx *ctx)
3790 {
3791 static float one_point_five = 1.5f;
3792 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3793 struct r600_bytecode_tex tex;
3794 struct r600_bytecode_alu alu;
3795 unsigned src_gpr;
3796 int r, i, j;
3797 int opcode;
3798 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
3799 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
3800 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
3801 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
3802
3803 /* Texture fetch instructions can only use gprs as source.
3804 * Also they cannot negate the source or take the absolute value */
3805 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3806 tgsi_tex_src_requires_loading(ctx, 0)) ||
3807 read_compressed_msaa;
3808 boolean src_loaded = FALSE;
3809 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3810 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
3811 boolean has_txq_cube_array_z = false;
3812
3813 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
3814 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3815 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
3816 if (inst->Dst[0].Register.WriteMask & 4) {
3817 ctx->shader->has_txq_cube_array_z_comp = true;
3818 has_txq_cube_array_z = true;
3819 }
3820
3821 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
3822 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
3823 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
3824 sampler_src_reg = 2;
3825
3826 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3827
3828 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
3829 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
3830 ctx->shader->uses_tex_buffers = true;
3831 return r600_do_buffer_txq(ctx);
3832 }
3833 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3834 if (ctx->bc->chip_class < EVERGREEN)
3835 ctx->shader->uses_tex_buffers = true;
3836 return do_vtx_fetch_inst(ctx, src_requires_loading);
3837 }
3838 }
3839
3840 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3841 /* get offset values */
3842 if (inst->Texture.NumOffsets) {
3843 assert(inst->Texture.NumOffsets == 1);
3844
3845 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3846 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3847 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3848 }
3849 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3850 /* TGSI moves the sampler to src reg 3 for TXD */
3851 sampler_src_reg = 3;
3852
3853 for (i = 1; i < 3; i++) {
3854 /* set gradients h/v */
3855 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3856 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
3857 FETCH_OP_SET_GRADIENTS_V;
3858 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3859 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3860
3861 if (tgsi_tex_src_requires_loading(ctx, i)) {
3862 tex.src_gpr = r600_get_temp(ctx);
3863 tex.src_sel_x = 0;
3864 tex.src_sel_y = 1;
3865 tex.src_sel_z = 2;
3866 tex.src_sel_w = 3;
3867
3868 for (j = 0; j < 4; j++) {
3869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3870 alu.op = ALU_OP1_MOV;
3871 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3872 alu.dst.sel = tex.src_gpr;
3873 alu.dst.chan = j;
3874 if (j == 3)
3875 alu.last = 1;
3876 alu.dst.write = 1;
3877 r = r600_bytecode_add_alu(ctx->bc, &alu);
3878 if (r)
3879 return r;
3880 }
3881
3882 } else {
3883 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3884 tex.src_sel_x = ctx->src[i].swizzle[0];
3885 tex.src_sel_y = ctx->src[i].swizzle[1];
3886 tex.src_sel_z = ctx->src[i].swizzle[2];
3887 tex.src_sel_w = ctx->src[i].swizzle[3];
3888 tex.src_rel = ctx->src[i].rel;
3889 }
3890 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3891 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3892 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3893 tex.coord_type_x = 1;
3894 tex.coord_type_y = 1;
3895 tex.coord_type_z = 1;
3896 tex.coord_type_w = 1;
3897 }
3898 r = r600_bytecode_add_tex(ctx->bc, &tex);
3899 if (r)
3900 return r;
3901 }
3902 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3903 int out_chan;
3904 /* Add perspective divide */
3905 if (ctx->bc->chip_class == CAYMAN) {
3906 out_chan = 2;
3907 for (i = 0; i < 3; i++) {
3908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3909 alu.op = ALU_OP1_RECIP_IEEE;
3910 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3911
3912 alu.dst.sel = ctx->temp_reg;
3913 alu.dst.chan = i;
3914 if (i == 2)
3915 alu.last = 1;
3916 if (out_chan == i)
3917 alu.dst.write = 1;
3918 r = r600_bytecode_add_alu(ctx->bc, &alu);
3919 if (r)
3920 return r;
3921 }
3922
3923 } else {
3924 out_chan = 3;
3925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3926 alu.op = ALU_OP1_RECIP_IEEE;
3927 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3928
3929 alu.dst.sel = ctx->temp_reg;
3930 alu.dst.chan = out_chan;
3931 alu.last = 1;
3932 alu.dst.write = 1;
3933 r = r600_bytecode_add_alu(ctx->bc, &alu);
3934 if (r)
3935 return r;
3936 }
3937
3938 for (i = 0; i < 3; i++) {
3939 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3940 alu.op = ALU_OP2_MUL;
3941 alu.src[0].sel = ctx->temp_reg;
3942 alu.src[0].chan = out_chan;
3943 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3944 alu.dst.sel = ctx->temp_reg;
3945 alu.dst.chan = i;
3946 alu.dst.write = 1;
3947 r = r600_bytecode_add_alu(ctx->bc, &alu);
3948 if (r)
3949 return r;
3950 }
3951 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3952 alu.op = ALU_OP1_MOV;
3953 alu.src[0].sel = V_SQ_ALU_SRC_1;
3954 alu.src[0].chan = 0;
3955 alu.dst.sel = ctx->temp_reg;
3956 alu.dst.chan = 3;
3957 alu.last = 1;
3958 alu.dst.write = 1;
3959 r = r600_bytecode_add_alu(ctx->bc, &alu);
3960 if (r)
3961 return r;
3962 src_loaded = TRUE;
3963 src_gpr = ctx->temp_reg;
3964 }
3965
3966 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3967 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3968 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
3969 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
3970 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3971 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
3972
3973 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3974 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3975
3976 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3977 for (i = 0; i < 4; i++) {
3978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3979 alu.op = ALU_OP2_CUBE;
3980 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3981 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3982 alu.dst.sel = ctx->temp_reg;
3983 alu.dst.chan = i;
3984 if (i == 3)
3985 alu.last = 1;
3986 alu.dst.write = 1;
3987 r = r600_bytecode_add_alu(ctx->bc, &alu);
3988 if (r)
3989 return r;
3990 }
3991
3992 /* tmp1.z = RCP_e(|tmp1.z|) */
3993 if (ctx->bc->chip_class == CAYMAN) {
3994 for (i = 0; i < 3; i++) {
3995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3996 alu.op = ALU_OP1_RECIP_IEEE;
3997 alu.src[0].sel = ctx->temp_reg;
3998 alu.src[0].chan = 2;
3999 alu.src[0].abs = 1;
4000 alu.dst.sel = ctx->temp_reg;
4001 alu.dst.chan = i;
4002 if (i == 2)
4003 alu.dst.write = 1;
4004 if (i == 2)
4005 alu.last = 1;
4006 r = r600_bytecode_add_alu(ctx->bc, &alu);
4007 if (r)
4008 return r;
4009 }
4010 } else {
4011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4012 alu.op = ALU_OP1_RECIP_IEEE;
4013 alu.src[0].sel = ctx->temp_reg;
4014 alu.src[0].chan = 2;
4015 alu.src[0].abs = 1;
4016 alu.dst.sel = ctx->temp_reg;
4017 alu.dst.chan = 2;
4018 alu.dst.write = 1;
4019 alu.last = 1;
4020 r = r600_bytecode_add_alu(ctx->bc, &alu);
4021 if (r)
4022 return r;
4023 }
4024
4025 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4026 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4027 * muladd has no writemask, have to use another temp
4028 */
4029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4030 alu.op = ALU_OP3_MULADD;
4031 alu.is_op3 = 1;
4032
4033 alu.src[0].sel = ctx->temp_reg;
4034 alu.src[0].chan = 0;
4035 alu.src[1].sel = ctx->temp_reg;
4036 alu.src[1].chan = 2;
4037
4038 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4039 alu.src[2].chan = 0;
4040 alu.src[2].value = *(uint32_t *)&one_point_five;
4041
4042 alu.dst.sel = ctx->temp_reg;
4043 alu.dst.chan = 0;
4044 alu.dst.write = 1;
4045
4046 r = r600_bytecode_add_alu(ctx->bc, &alu);
4047 if (r)
4048 return r;
4049
4050 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4051 alu.op = ALU_OP3_MULADD;
4052 alu.is_op3 = 1;
4053
4054 alu.src[0].sel = ctx->temp_reg;
4055 alu.src[0].chan = 1;
4056 alu.src[1].sel = ctx->temp_reg;
4057 alu.src[1].chan = 2;
4058
4059 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4060 alu.src[2].chan = 0;
4061 alu.src[2].value = *(uint32_t *)&one_point_five;
4062
4063 alu.dst.sel = ctx->temp_reg;
4064 alu.dst.chan = 1;
4065 alu.dst.write = 1;
4066
4067 alu.last = 1;
4068 r = r600_bytecode_add_alu(ctx->bc, &alu);
4069 if (r)
4070 return r;
4071 /* write initial compare value into Z component
4072 - W src 0 for shadow cube
4073 - X src 1 for shadow cube array */
4074 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4075 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4076 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4077 alu.op = ALU_OP1_MOV;
4078 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4079 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4080 else
4081 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4082 alu.dst.sel = ctx->temp_reg;
4083 alu.dst.chan = 2;
4084 alu.dst.write = 1;
4085 alu.last = 1;
4086 r = r600_bytecode_add_alu(ctx->bc, &alu);
4087 if (r)
4088 return r;
4089 }
4090
4091 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4092 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4093 if (ctx->bc->chip_class >= EVERGREEN) {
4094 int mytmp = r600_get_temp(ctx);
4095 static const float eight = 8.0f;
4096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4097 alu.op = ALU_OP1_MOV;
4098 alu.src[0].sel = ctx->temp_reg;
4099 alu.src[0].chan = 3;
4100 alu.dst.sel = mytmp;
4101 alu.dst.chan = 0;
4102 alu.dst.write = 1;
4103 alu.last = 1;
4104 r = r600_bytecode_add_alu(ctx->bc, &alu);
4105 if (r)
4106 return r;
4107
4108 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4110 alu.op = ALU_OP3_MULADD;
4111 alu.is_op3 = 1;
4112 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4113 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4114 alu.src[1].chan = 0;
4115 alu.src[1].value = *(uint32_t *)&eight;
4116 alu.src[2].sel = mytmp;
4117 alu.src[2].chan = 0;
4118 alu.dst.sel = ctx->temp_reg;
4119 alu.dst.chan = 3;
4120 alu.dst.write = 1;
4121 alu.last = 1;
4122 r = r600_bytecode_add_alu(ctx->bc, &alu);
4123 if (r)
4124 return r;
4125 } else if (ctx->bc->chip_class < EVERGREEN) {
4126 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4127 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4128 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4129 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4130 tex.src_gpr = r600_get_temp(ctx);
4131 tex.src_sel_x = 0;
4132 tex.src_sel_y = 0;
4133 tex.src_sel_z = 0;
4134 tex.src_sel_w = 0;
4135 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4136 tex.coord_type_x = 1;
4137 tex.coord_type_y = 1;
4138 tex.coord_type_z = 1;
4139 tex.coord_type_w = 1;
4140 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4141 alu.op = ALU_OP1_MOV;
4142 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4143 alu.dst.sel = tex.src_gpr;
4144 alu.dst.chan = 0;
4145 alu.last = 1;
4146 alu.dst.write = 1;
4147 r = r600_bytecode_add_alu(ctx->bc, &alu);
4148 if (r)
4149 return r;
4150
4151 r = r600_bytecode_add_tex(ctx->bc, &tex);
4152 if (r)
4153 return r;
4154 }
4155
4156 }
4157
4158 /* for cube forms of lod and bias we need to route things */
4159 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4160 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4161 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4162 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4164 alu.op = ALU_OP1_MOV;
4165 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4166 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4167 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4168 else
4169 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4170 alu.dst.sel = ctx->temp_reg;
4171 alu.dst.chan = 2;
4172 alu.last = 1;
4173 alu.dst.write = 1;
4174 r = r600_bytecode_add_alu(ctx->bc, &alu);
4175 if (r)
4176 return r;
4177 }
4178
4179 src_loaded = TRUE;
4180 src_gpr = ctx->temp_reg;
4181 }
4182
4183 if (src_requires_loading && !src_loaded) {
4184 for (i = 0; i < 4; i++) {
4185 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4186 alu.op = ALU_OP1_MOV;
4187 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4188 alu.dst.sel = ctx->temp_reg;
4189 alu.dst.chan = i;
4190 if (i == 3)
4191 alu.last = 1;
4192 alu.dst.write = 1;
4193 r = r600_bytecode_add_alu(ctx->bc, &alu);
4194 if (r)
4195 return r;
4196 }
4197 src_loaded = TRUE;
4198 src_gpr = ctx->temp_reg;
4199 }
4200
4201 /* Obtain the sample index for reading a compressed MSAA color texture.
4202 * To read the FMASK, we use the ldfptr instruction, which tells us
4203 * where the samples are stored.
4204 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4205 * which is the identity mapping. Each nibble says which physical sample
4206 * should be fetched to get that sample.
4207 *
4208 * Assume src.z contains the sample index. It should be modified like this:
4209 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4210 * Then fetch the texel with src.
4211 */
4212 if (read_compressed_msaa) {
4213 unsigned sample_chan = 3;
4214 unsigned temp = r600_get_temp(ctx);
4215 assert(src_loaded);
4216
4217 /* temp.w = ldfptr() */
4218 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4219 tex.op = FETCH_OP_LD;
4220 tex.inst_mod = 1; /* to indicate this is ldfptr */
4221 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4222 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4223 tex.src_gpr = src_gpr;
4224 tex.dst_gpr = temp;
4225 tex.dst_sel_x = 7; /* mask out these components */
4226 tex.dst_sel_y = 7;
4227 tex.dst_sel_z = 7;
4228 tex.dst_sel_w = 0; /* store X */
4229 tex.src_sel_x = 0;
4230 tex.src_sel_y = 1;
4231 tex.src_sel_z = 2;
4232 tex.src_sel_w = 3;
4233 tex.offset_x = offset_x;
4234 tex.offset_y = offset_y;
4235 tex.offset_z = offset_z;
4236 r = r600_bytecode_add_tex(ctx->bc, &tex);
4237 if (r)
4238 return r;
4239
4240 /* temp.x = sample_index*4 */
4241 if (ctx->bc->chip_class == CAYMAN) {
4242 for (i = 0 ; i < 4; i++) {
4243 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4244 alu.op = ALU_OP2_MULLO_INT;
4245 alu.src[0].sel = src_gpr;
4246 alu.src[0].chan = sample_chan;
4247 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4248 alu.src[1].value = 4;
4249 alu.dst.sel = temp;
4250 alu.dst.chan = i;
4251 alu.dst.write = i == 0;
4252 if (i == 3)
4253 alu.last = 1;
4254 r = r600_bytecode_add_alu(ctx->bc, &alu);
4255 if (r)
4256 return r;
4257 }
4258 } else {
4259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4260 alu.op = ALU_OP2_MULLO_INT;
4261 alu.src[0].sel = src_gpr;
4262 alu.src[0].chan = sample_chan;
4263 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4264 alu.src[1].value = 4;
4265 alu.dst.sel = temp;
4266 alu.dst.chan = 0;
4267 alu.dst.write = 1;
4268 alu.last = 1;
4269 r = r600_bytecode_add_alu(ctx->bc, &alu);
4270 if (r)
4271 return r;
4272 }
4273
4274 /* sample_index = temp.w >> temp.x */
4275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4276 alu.op = ALU_OP2_LSHR_INT;
4277 alu.src[0].sel = temp;
4278 alu.src[0].chan = 3;
4279 alu.src[1].sel = temp;
4280 alu.src[1].chan = 0;
4281 alu.dst.sel = src_gpr;
4282 alu.dst.chan = sample_chan;
4283 alu.dst.write = 1;
4284 alu.last = 1;
4285 r = r600_bytecode_add_alu(ctx->bc, &alu);
4286 if (r)
4287 return r;
4288
4289 /* sample_index & 0xF */
4290 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4291 alu.op = ALU_OP2_AND_INT;
4292 alu.src[0].sel = src_gpr;
4293 alu.src[0].chan = sample_chan;
4294 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4295 alu.src[1].value = 0xF;
4296 alu.dst.sel = src_gpr;
4297 alu.dst.chan = sample_chan;
4298 alu.dst.write = 1;
4299 alu.last = 1;
4300 r = r600_bytecode_add_alu(ctx->bc, &alu);
4301 if (r)
4302 return r;
4303 #if 0
4304 /* visualize the FMASK */
4305 for (i = 0; i < 4; i++) {
4306 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4307 alu.op = ALU_OP1_INT_TO_FLT;
4308 alu.src[0].sel = src_gpr;
4309 alu.src[0].chan = sample_chan;
4310 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4311 alu.dst.chan = i;
4312 alu.dst.write = 1;
4313 alu.last = 1;
4314 r = r600_bytecode_add_alu(ctx->bc, &alu);
4315 if (r)
4316 return r;
4317 }
4318 return 0;
4319 #endif
4320 }
4321
4322 /* does this shader want a num layers from TXQ for a cube array? */
4323 if (has_txq_cube_array_z) {
4324 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4325
4326 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4327 alu.op = ALU_OP1_MOV;
4328
4329 alu.src[0].sel = 512 + (id / 4);
4330 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4331 alu.src[0].chan = id % 4;
4332 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4333 alu.last = 1;
4334 r = r600_bytecode_add_alu(ctx->bc, &alu);
4335 if (r)
4336 return r;
4337 /* disable writemask from texture instruction */
4338 inst->Dst[0].Register.WriteMask &= ~4;
4339 }
4340
4341 opcode = ctx->inst_info->op;
4342 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4343 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4344 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4345 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4346 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4347 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4348 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4349 switch (opcode) {
4350 case FETCH_OP_SAMPLE:
4351 opcode = FETCH_OP_SAMPLE_C;
4352 break;
4353 case FETCH_OP_SAMPLE_L:
4354 opcode = FETCH_OP_SAMPLE_C_L;
4355 break;
4356 case FETCH_OP_SAMPLE_LB:
4357 opcode = FETCH_OP_SAMPLE_C_LB;
4358 break;
4359 case FETCH_OP_SAMPLE_G:
4360 opcode = FETCH_OP_SAMPLE_C_G;
4361 break;
4362 }
4363 }
4364
4365 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4366 tex.op = opcode;
4367
4368 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4369 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4370 tex.src_gpr = src_gpr;
4371 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4372 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4373 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4374 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4375 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4376
4377 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4378 tex.src_sel_x = 4;
4379 tex.src_sel_y = 4;
4380 tex.src_sel_z = 4;
4381 tex.src_sel_w = 4;
4382 } else if (src_loaded) {
4383 tex.src_sel_x = 0;
4384 tex.src_sel_y = 1;
4385 tex.src_sel_z = 2;
4386 tex.src_sel_w = 3;
4387 } else {
4388 tex.src_sel_x = ctx->src[0].swizzle[0];
4389 tex.src_sel_y = ctx->src[0].swizzle[1];
4390 tex.src_sel_z = ctx->src[0].swizzle[2];
4391 tex.src_sel_w = ctx->src[0].swizzle[3];
4392 tex.src_rel = ctx->src[0].rel;
4393 }
4394
4395 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4396 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4397 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4398 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4399 tex.src_sel_x = 1;
4400 tex.src_sel_y = 0;
4401 tex.src_sel_z = 3;
4402 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4403 }
4404
4405 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4406 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4407 tex.coord_type_x = 1;
4408 tex.coord_type_y = 1;
4409 }
4410 tex.coord_type_z = 1;
4411 tex.coord_type_w = 1;
4412
4413 tex.offset_x = offset_x;
4414 tex.offset_y = offset_y;
4415 tex.offset_z = offset_z;
4416
4417 /* Put the depth for comparison in W.
4418 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4419 * Some instructions expect the depth in Z. */
4420 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4421 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4422 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4423 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4424 opcode != FETCH_OP_SAMPLE_C_L &&
4425 opcode != FETCH_OP_SAMPLE_C_LB) {
4426 tex.src_sel_w = tex.src_sel_z;
4427 }
4428
4429 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4430 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4431 if (opcode == FETCH_OP_SAMPLE_C_L ||
4432 opcode == FETCH_OP_SAMPLE_C_LB) {
4433 /* the array index is read from Y */
4434 tex.coord_type_y = 0;
4435 } else {
4436 /* the array index is read from Z */
4437 tex.coord_type_z = 0;
4438 tex.src_sel_z = tex.src_sel_y;
4439 }
4440 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4441 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4442 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4443 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4444 (ctx->bc->chip_class >= EVERGREEN)))
4445 /* the array index is read from Z */
4446 tex.coord_type_z = 0;
4447
4448 /* mask unused source components */
4449 if (opcode == FETCH_OP_SAMPLE) {
4450 switch (inst->Texture.Texture) {
4451 case TGSI_TEXTURE_2D:
4452 case TGSI_TEXTURE_RECT:
4453 tex.src_sel_z = 7;
4454 tex.src_sel_w = 7;
4455 break;
4456 case TGSI_TEXTURE_1D_ARRAY:
4457 tex.src_sel_y = 7;
4458 tex.src_sel_w = 7;
4459 break;
4460 case TGSI_TEXTURE_1D:
4461 tex.src_sel_y = 7;
4462 tex.src_sel_z = 7;
4463 tex.src_sel_w = 7;
4464 break;
4465 }
4466 }
4467
4468 r = r600_bytecode_add_tex(ctx->bc, &tex);
4469 if (r)
4470 return r;
4471
4472 /* add shadow ambient support - gallium doesn't do it yet */
4473 return 0;
4474 }
4475
4476 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4477 {
4478 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4479 struct r600_bytecode_alu alu;
4480 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4481 unsigned i;
4482 int r;
4483
4484 /* optimize if it's just an equal balance */
4485 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4486 for (i = 0; i < lasti + 1; i++) {
4487 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4488 continue;
4489
4490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4491 alu.op = ALU_OP2_ADD;
4492 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4493 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4494 alu.omod = 3;
4495 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4496 alu.dst.chan = i;
4497 if (i == lasti) {
4498 alu.last = 1;
4499 }
4500 r = r600_bytecode_add_alu(ctx->bc, &alu);
4501 if (r)
4502 return r;
4503 }
4504 return 0;
4505 }
4506
4507 /* 1 - src0 */
4508 for (i = 0; i < lasti + 1; i++) {
4509 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4510 continue;
4511
4512 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4513 alu.op = ALU_OP2_ADD;
4514 alu.src[0].sel = V_SQ_ALU_SRC_1;
4515 alu.src[0].chan = 0;
4516 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4517 r600_bytecode_src_toggle_neg(&alu.src[1]);
4518 alu.dst.sel = ctx->temp_reg;
4519 alu.dst.chan = i;
4520 if (i == lasti) {
4521 alu.last = 1;
4522 }
4523 alu.dst.write = 1;
4524 r = r600_bytecode_add_alu(ctx->bc, &alu);
4525 if (r)
4526 return r;
4527 }
4528
4529 /* (1 - src0) * src2 */
4530 for (i = 0; i < lasti + 1; i++) {
4531 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4532 continue;
4533
4534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4535 alu.op = ALU_OP2_MUL;
4536 alu.src[0].sel = ctx->temp_reg;
4537 alu.src[0].chan = i;
4538 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4539 alu.dst.sel = ctx->temp_reg;
4540 alu.dst.chan = i;
4541 if (i == lasti) {
4542 alu.last = 1;
4543 }
4544 alu.dst.write = 1;
4545 r = r600_bytecode_add_alu(ctx->bc, &alu);
4546 if (r)
4547 return r;
4548 }
4549
4550 /* src0 * src1 + (1 - src0) * src2 */
4551 for (i = 0; i < lasti + 1; i++) {
4552 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4553 continue;
4554
4555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4556 alu.op = ALU_OP3_MULADD;
4557 alu.is_op3 = 1;
4558 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4559 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4560 alu.src[2].sel = ctx->temp_reg;
4561 alu.src[2].chan = i;
4562
4563 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4564 alu.dst.chan = i;
4565 if (i == lasti) {
4566 alu.last = 1;
4567 }
4568 r = r600_bytecode_add_alu(ctx->bc, &alu);
4569 if (r)
4570 return r;
4571 }
4572 return 0;
4573 }
4574
4575 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4576 {
4577 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4578 struct r600_bytecode_alu alu;
4579 int i, r;
4580 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4581
4582 for (i = 0; i < lasti + 1; i++) {
4583 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4584 continue;
4585
4586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4587 alu.op = ALU_OP3_CNDGE;
4588 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4589 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4590 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4591 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4592 alu.dst.chan = i;
4593 alu.dst.write = 1;
4594 alu.is_op3 = 1;
4595 if (i == lasti)
4596 alu.last = 1;
4597 r = r600_bytecode_add_alu(ctx->bc, &alu);
4598 if (r)
4599 return r;
4600 }
4601 return 0;
4602 }
4603
4604 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4605 {
4606 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4607 struct r600_bytecode_alu alu;
4608 int i, r;
4609 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4610
4611 for (i = 0; i < lasti + 1; i++) {
4612 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4613 continue;
4614
4615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4616 alu.op = ALU_OP3_CNDGE_INT;
4617 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4618 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4619 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4620 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4621 alu.dst.chan = i;
4622 alu.dst.write = 1;
4623 alu.is_op3 = 1;
4624 if (i == lasti)
4625 alu.last = 1;
4626 r = r600_bytecode_add_alu(ctx->bc, &alu);
4627 if (r)
4628 return r;
4629 }
4630 return 0;
4631 }
4632
4633 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4634 {
4635 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4636 static const unsigned int src0_swizzle[] = {2, 0, 1};
4637 static const unsigned int src1_swizzle[] = {1, 2, 0};
4638 struct r600_bytecode_alu alu;
4639 uint32_t use_temp = 0;
4640 int i, r;
4641
4642 if (inst->Dst[0].Register.WriteMask != 0xf)
4643 use_temp = 1;
4644
4645 for (i = 0; i < 4; i++) {
4646 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4647 alu.op = ALU_OP2_MUL;
4648 if (i < 3) {
4649 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4650 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4651 } else {
4652 alu.src[0].sel = V_SQ_ALU_SRC_0;
4653 alu.src[0].chan = i;
4654 alu.src[1].sel = V_SQ_ALU_SRC_0;
4655 alu.src[1].chan = i;
4656 }
4657
4658 alu.dst.sel = ctx->temp_reg;
4659 alu.dst.chan = i;
4660 alu.dst.write = 1;
4661
4662 if (i == 3)
4663 alu.last = 1;
4664 r = r600_bytecode_add_alu(ctx->bc, &alu);
4665 if (r)
4666 return r;
4667 }
4668
4669 for (i = 0; i < 4; i++) {
4670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4671 alu.op = ALU_OP3_MULADD;
4672
4673 if (i < 3) {
4674 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4675 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4676 } else {
4677 alu.src[0].sel = V_SQ_ALU_SRC_0;
4678 alu.src[0].chan = i;
4679 alu.src[1].sel = V_SQ_ALU_SRC_0;
4680 alu.src[1].chan = i;
4681 }
4682
4683 alu.src[2].sel = ctx->temp_reg;
4684 alu.src[2].neg = 1;
4685 alu.src[2].chan = i;
4686
4687 if (use_temp)
4688 alu.dst.sel = ctx->temp_reg;
4689 else
4690 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4691 alu.dst.chan = i;
4692 alu.dst.write = 1;
4693 alu.is_op3 = 1;
4694 if (i == 3)
4695 alu.last = 1;
4696 r = r600_bytecode_add_alu(ctx->bc, &alu);
4697 if (r)
4698 return r;
4699 }
4700 if (use_temp)
4701 return tgsi_helper_copy(ctx, inst);
4702 return 0;
4703 }
4704
4705 static int tgsi_exp(struct r600_shader_ctx *ctx)
4706 {
4707 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4708 struct r600_bytecode_alu alu;
4709 int r;
4710 int i;
4711
4712 /* result.x = 2^floor(src); */
4713 if (inst->Dst[0].Register.WriteMask & 1) {
4714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4715
4716 alu.op = ALU_OP1_FLOOR;
4717 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4718
4719 alu.dst.sel = ctx->temp_reg;
4720 alu.dst.chan = 0;
4721 alu.dst.write = 1;
4722 alu.last = 1;
4723 r = r600_bytecode_add_alu(ctx->bc, &alu);
4724 if (r)
4725 return r;
4726
4727 if (ctx->bc->chip_class == CAYMAN) {
4728 for (i = 0; i < 3; i++) {
4729 alu.op = ALU_OP1_EXP_IEEE;
4730 alu.src[0].sel = ctx->temp_reg;
4731 alu.src[0].chan = 0;
4732
4733 alu.dst.sel = ctx->temp_reg;
4734 alu.dst.chan = i;
4735 alu.dst.write = i == 0;
4736 alu.last = i == 2;
4737 r = r600_bytecode_add_alu(ctx->bc, &alu);
4738 if (r)
4739 return r;
4740 }
4741 } else {
4742 alu.op = ALU_OP1_EXP_IEEE;
4743 alu.src[0].sel = ctx->temp_reg;
4744 alu.src[0].chan = 0;
4745
4746 alu.dst.sel = ctx->temp_reg;
4747 alu.dst.chan = 0;
4748 alu.dst.write = 1;
4749 alu.last = 1;
4750 r = r600_bytecode_add_alu(ctx->bc, &alu);
4751 if (r)
4752 return r;
4753 }
4754 }
4755
4756 /* result.y = tmp - floor(tmp); */
4757 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4758 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4759
4760 alu.op = ALU_OP1_FRACT;
4761 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4762
4763 alu.dst.sel = ctx->temp_reg;
4764 #if 0
4765 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4766 if (r)
4767 return r;
4768 #endif
4769 alu.dst.write = 1;
4770 alu.dst.chan = 1;
4771
4772 alu.last = 1;
4773
4774 r = r600_bytecode_add_alu(ctx->bc, &alu);
4775 if (r)
4776 return r;
4777 }
4778
4779 /* result.z = RoughApprox2ToX(tmp);*/
4780 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4781 if (ctx->bc->chip_class == CAYMAN) {
4782 for (i = 0; i < 3; i++) {
4783 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4784 alu.op = ALU_OP1_EXP_IEEE;
4785 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4786
4787 alu.dst.sel = ctx->temp_reg;
4788 alu.dst.chan = i;
4789 if (i == 2) {
4790 alu.dst.write = 1;
4791 alu.last = 1;
4792 }
4793
4794 r = r600_bytecode_add_alu(ctx->bc, &alu);
4795 if (r)
4796 return r;
4797 }
4798 } else {
4799 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4800 alu.op = ALU_OP1_EXP_IEEE;
4801 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4802
4803 alu.dst.sel = ctx->temp_reg;
4804 alu.dst.write = 1;
4805 alu.dst.chan = 2;
4806
4807 alu.last = 1;
4808
4809 r = r600_bytecode_add_alu(ctx->bc, &alu);
4810 if (r)
4811 return r;
4812 }
4813 }
4814
4815 /* result.w = 1.0;*/
4816 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4817 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4818
4819 alu.op = ALU_OP1_MOV;
4820 alu.src[0].sel = V_SQ_ALU_SRC_1;
4821 alu.src[0].chan = 0;
4822
4823 alu.dst.sel = ctx->temp_reg;
4824 alu.dst.chan = 3;
4825 alu.dst.write = 1;
4826 alu.last = 1;
4827 r = r600_bytecode_add_alu(ctx->bc, &alu);
4828 if (r)
4829 return r;
4830 }
4831 return tgsi_helper_copy(ctx, inst);
4832 }
4833
4834 static int tgsi_log(struct r600_shader_ctx *ctx)
4835 {
4836 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4837 struct r600_bytecode_alu alu;
4838 int r;
4839 int i;
4840
4841 /* result.x = floor(log2(|src|)); */
4842 if (inst->Dst[0].Register.WriteMask & 1) {
4843 if (ctx->bc->chip_class == CAYMAN) {
4844 for (i = 0; i < 3; i++) {
4845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4846
4847 alu.op = ALU_OP1_LOG_IEEE;
4848 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4849 r600_bytecode_src_set_abs(&alu.src[0]);
4850
4851 alu.dst.sel = ctx->temp_reg;
4852 alu.dst.chan = i;
4853 if (i == 0)
4854 alu.dst.write = 1;
4855 if (i == 2)
4856 alu.last = 1;
4857 r = r600_bytecode_add_alu(ctx->bc, &alu);
4858 if (r)
4859 return r;
4860 }
4861
4862 } else {
4863 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4864
4865 alu.op = ALU_OP1_LOG_IEEE;
4866 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4867 r600_bytecode_src_set_abs(&alu.src[0]);
4868
4869 alu.dst.sel = ctx->temp_reg;
4870 alu.dst.chan = 0;
4871 alu.dst.write = 1;
4872 alu.last = 1;
4873 r = r600_bytecode_add_alu(ctx->bc, &alu);
4874 if (r)
4875 return r;
4876 }
4877
4878 alu.op = ALU_OP1_FLOOR;
4879 alu.src[0].sel = ctx->temp_reg;
4880 alu.src[0].chan = 0;
4881
4882 alu.dst.sel = ctx->temp_reg;
4883 alu.dst.chan = 0;
4884 alu.dst.write = 1;
4885 alu.last = 1;
4886
4887 r = r600_bytecode_add_alu(ctx->bc, &alu);
4888 if (r)
4889 return r;
4890 }
4891
4892 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4893 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4894
4895 if (ctx->bc->chip_class == CAYMAN) {
4896 for (i = 0; i < 3; i++) {
4897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4898
4899 alu.op = ALU_OP1_LOG_IEEE;
4900 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4901 r600_bytecode_src_set_abs(&alu.src[0]);
4902
4903 alu.dst.sel = ctx->temp_reg;
4904 alu.dst.chan = i;
4905 if (i == 1)
4906 alu.dst.write = 1;
4907 if (i == 2)
4908 alu.last = 1;
4909
4910 r = r600_bytecode_add_alu(ctx->bc, &alu);
4911 if (r)
4912 return r;
4913 }
4914 } else {
4915 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4916
4917 alu.op = ALU_OP1_LOG_IEEE;
4918 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4919 r600_bytecode_src_set_abs(&alu.src[0]);
4920
4921 alu.dst.sel = ctx->temp_reg;
4922 alu.dst.chan = 1;
4923 alu.dst.write = 1;
4924 alu.last = 1;
4925
4926 r = r600_bytecode_add_alu(ctx->bc, &alu);
4927 if (r)
4928 return r;
4929 }
4930
4931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4932
4933 alu.op = ALU_OP1_FLOOR;
4934 alu.src[0].sel = ctx->temp_reg;
4935 alu.src[0].chan = 1;
4936
4937 alu.dst.sel = ctx->temp_reg;
4938 alu.dst.chan = 1;
4939 alu.dst.write = 1;
4940 alu.last = 1;
4941
4942 r = r600_bytecode_add_alu(ctx->bc, &alu);
4943 if (r)
4944 return r;
4945
4946 if (ctx->bc->chip_class == CAYMAN) {
4947 for (i = 0; i < 3; i++) {
4948 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4949 alu.op = ALU_OP1_EXP_IEEE;
4950 alu.src[0].sel = ctx->temp_reg;
4951 alu.src[0].chan = 1;
4952
4953 alu.dst.sel = ctx->temp_reg;
4954 alu.dst.chan = i;
4955 if (i == 1)
4956 alu.dst.write = 1;
4957 if (i == 2)
4958 alu.last = 1;
4959
4960 r = r600_bytecode_add_alu(ctx->bc, &alu);
4961 if (r)
4962 return r;
4963 }
4964 } else {
4965 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4966 alu.op = ALU_OP1_EXP_IEEE;
4967 alu.src[0].sel = ctx->temp_reg;
4968 alu.src[0].chan = 1;
4969
4970 alu.dst.sel = ctx->temp_reg;
4971 alu.dst.chan = 1;
4972 alu.dst.write = 1;
4973 alu.last = 1;
4974
4975 r = r600_bytecode_add_alu(ctx->bc, &alu);
4976 if (r)
4977 return r;
4978 }
4979
4980 if (ctx->bc->chip_class == CAYMAN) {
4981 for (i = 0; i < 3; i++) {
4982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4983 alu.op = ALU_OP1_RECIP_IEEE;
4984 alu.src[0].sel = ctx->temp_reg;
4985 alu.src[0].chan = 1;
4986
4987 alu.dst.sel = ctx->temp_reg;
4988 alu.dst.chan = i;
4989 if (i == 1)
4990 alu.dst.write = 1;
4991 if (i == 2)
4992 alu.last = 1;
4993
4994 r = r600_bytecode_add_alu(ctx->bc, &alu);
4995 if (r)
4996 return r;
4997 }
4998 } else {
4999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5000 alu.op = ALU_OP1_RECIP_IEEE;
5001 alu.src[0].sel = ctx->temp_reg;
5002 alu.src[0].chan = 1;
5003
5004 alu.dst.sel = ctx->temp_reg;
5005 alu.dst.chan = 1;
5006 alu.dst.write = 1;
5007 alu.last = 1;
5008
5009 r = r600_bytecode_add_alu(ctx->bc, &alu);
5010 if (r)
5011 return r;
5012 }
5013
5014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5015
5016 alu.op = ALU_OP2_MUL;
5017
5018 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5019 r600_bytecode_src_set_abs(&alu.src[0]);
5020
5021 alu.src[1].sel = ctx->temp_reg;
5022 alu.src[1].chan = 1;
5023
5024 alu.dst.sel = ctx->temp_reg;
5025 alu.dst.chan = 1;
5026 alu.dst.write = 1;
5027 alu.last = 1;
5028
5029 r = r600_bytecode_add_alu(ctx->bc, &alu);
5030 if (r)
5031 return r;
5032 }
5033
5034 /* result.z = log2(|src|);*/
5035 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5036 if (ctx->bc->chip_class == CAYMAN) {
5037 for (i = 0; i < 3; i++) {
5038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5039
5040 alu.op = ALU_OP1_LOG_IEEE;
5041 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5042 r600_bytecode_src_set_abs(&alu.src[0]);
5043
5044 alu.dst.sel = ctx->temp_reg;
5045 if (i == 2)
5046 alu.dst.write = 1;
5047 alu.dst.chan = i;
5048 if (i == 2)
5049 alu.last = 1;
5050
5051 r = r600_bytecode_add_alu(ctx->bc, &alu);
5052 if (r)
5053 return r;
5054 }
5055 } else {
5056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5057
5058 alu.op = ALU_OP1_LOG_IEEE;
5059 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5060 r600_bytecode_src_set_abs(&alu.src[0]);
5061
5062 alu.dst.sel = ctx->temp_reg;
5063 alu.dst.write = 1;
5064 alu.dst.chan = 2;
5065 alu.last = 1;
5066
5067 r = r600_bytecode_add_alu(ctx->bc, &alu);
5068 if (r)
5069 return r;
5070 }
5071 }
5072
5073 /* result.w = 1.0; */
5074 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5076
5077 alu.op = ALU_OP1_MOV;
5078 alu.src[0].sel = V_SQ_ALU_SRC_1;
5079 alu.src[0].chan = 0;
5080
5081 alu.dst.sel = ctx->temp_reg;
5082 alu.dst.chan = 3;
5083 alu.dst.write = 1;
5084 alu.last = 1;
5085
5086 r = r600_bytecode_add_alu(ctx->bc, &alu);
5087 if (r)
5088 return r;
5089 }
5090
5091 return tgsi_helper_copy(ctx, inst);
5092 }
5093
5094 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5095 {
5096 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5097 struct r600_bytecode_alu alu;
5098 int r;
5099
5100 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5101
5102 switch (inst->Instruction.Opcode) {
5103 case TGSI_OPCODE_ARL:
5104 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5105 break;
5106 case TGSI_OPCODE_ARR:
5107 alu.op = ALU_OP1_FLT_TO_INT;
5108 break;
5109 case TGSI_OPCODE_UARL:
5110 alu.op = ALU_OP1_MOV;
5111 break;
5112 default:
5113 assert(0);
5114 return -1;
5115 }
5116
5117 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5118 alu.last = 1;
5119 alu.dst.sel = ctx->bc->ar_reg;
5120 alu.dst.write = 1;
5121 r = r600_bytecode_add_alu(ctx->bc, &alu);
5122 if (r)
5123 return r;
5124
5125 ctx->bc->ar_loaded = 0;
5126 return 0;
5127 }
5128 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5129 {
5130 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5131 struct r600_bytecode_alu alu;
5132 int r;
5133
5134 switch (inst->Instruction.Opcode) {
5135 case TGSI_OPCODE_ARL:
5136 memset(&alu, 0, sizeof(alu));
5137 alu.op = ALU_OP1_FLOOR;
5138 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5139 alu.dst.sel = ctx->bc->ar_reg;
5140 alu.dst.write = 1;
5141 alu.last = 1;
5142
5143 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5144 return r;
5145
5146 memset(&alu, 0, sizeof(alu));
5147 alu.op = ALU_OP1_FLT_TO_INT;
5148 alu.src[0].sel = ctx->bc->ar_reg;
5149 alu.dst.sel = ctx->bc->ar_reg;
5150 alu.dst.write = 1;
5151 alu.last = 1;
5152
5153 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5154 return r;
5155 break;
5156 case TGSI_OPCODE_ARR:
5157 memset(&alu, 0, sizeof(alu));
5158 alu.op = ALU_OP1_FLT_TO_INT;
5159 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5160 alu.dst.sel = ctx->bc->ar_reg;
5161 alu.dst.write = 1;
5162 alu.last = 1;
5163
5164 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5165 return r;
5166 break;
5167 case TGSI_OPCODE_UARL:
5168 memset(&alu, 0, sizeof(alu));
5169 alu.op = ALU_OP1_MOV;
5170 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5171 alu.dst.sel = ctx->bc->ar_reg;
5172 alu.dst.write = 1;
5173 alu.last = 1;
5174
5175 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5176 return r;
5177 break;
5178 default:
5179 assert(0);
5180 return -1;
5181 }
5182
5183 ctx->bc->ar_loaded = 0;
5184 return 0;
5185 }
5186
5187 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5188 {
5189 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5190 struct r600_bytecode_alu alu;
5191 int i, r = 0;
5192
5193 for (i = 0; i < 4; i++) {
5194 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5195
5196 alu.op = ALU_OP2_MUL;
5197 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5198
5199 if (i == 0 || i == 3) {
5200 alu.src[0].sel = V_SQ_ALU_SRC_1;
5201 } else {
5202 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5203 }
5204
5205 if (i == 0 || i == 2) {
5206 alu.src[1].sel = V_SQ_ALU_SRC_1;
5207 } else {
5208 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5209 }
5210 if (i == 3)
5211 alu.last = 1;
5212 r = r600_bytecode_add_alu(ctx->bc, &alu);
5213 if (r)
5214 return r;
5215 }
5216 return 0;
5217 }
5218
5219 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5220 {
5221 struct r600_bytecode_alu alu;
5222 int r;
5223
5224 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5225 alu.op = opcode;
5226 alu.execute_mask = 1;
5227 alu.update_pred = 1;
5228
5229 alu.dst.sel = ctx->temp_reg;
5230 alu.dst.write = 1;
5231 alu.dst.chan = 0;
5232
5233 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5234 alu.src[1].sel = V_SQ_ALU_SRC_0;
5235 alu.src[1].chan = 0;
5236
5237 alu.last = 1;
5238
5239 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5240 if (r)
5241 return r;
5242 return 0;
5243 }
5244
5245 static int pops(struct r600_shader_ctx *ctx, int pops)
5246 {
5247 unsigned force_pop = ctx->bc->force_add_cf;
5248
5249 if (!force_pop) {
5250 int alu_pop = 3;
5251 if (ctx->bc->cf_last) {
5252 if (ctx->bc->cf_last->op == CF_OP_ALU)
5253 alu_pop = 0;
5254 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5255 alu_pop = 1;
5256 }
5257 alu_pop += pops;
5258 if (alu_pop == 1) {
5259 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5260 ctx->bc->force_add_cf = 1;
5261 } else if (alu_pop == 2) {
5262 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5263 ctx->bc->force_add_cf = 1;
5264 } else {
5265 force_pop = 1;
5266 }
5267 }
5268
5269 if (force_pop) {
5270 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5271 ctx->bc->cf_last->pop_count = pops;
5272 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5273 }
5274
5275 return 0;
5276 }
5277
5278 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5279 unsigned reason)
5280 {
5281 struct r600_stack_info *stack = &ctx->bc->stack;
5282 unsigned elements, entries;
5283
5284 unsigned entry_size = stack->entry_size;
5285
5286 elements = (stack->loop + stack->push_wqm ) * entry_size;
5287 elements += stack->push;
5288
5289 switch (ctx->bc->chip_class) {
5290 case R600:
5291 case R700:
5292 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5293 * the stack must be reserved to hold the current active/continue
5294 * masks */
5295 if (reason == FC_PUSH_VPM) {
5296 elements += 2;
5297 }
5298 break;
5299
5300 case CAYMAN:
5301 /* r9xx: any stack operation on empty stack consumes 2 additional
5302 * elements */
5303 elements += 2;
5304
5305 /* fallthrough */
5306 /* FIXME: do the two elements added above cover the cases for the
5307 * r8xx+ below? */
5308
5309 case EVERGREEN:
5310 /* r8xx+: 2 extra elements are not always required, but one extra
5311 * element must be added for each of the following cases:
5312 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5313 * stack usage.
5314 * (Currently we don't use ALU_ELSE_AFTER.)
5315 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5316 * PUSH instruction executed.
5317 *
5318 * NOTE: it seems we also need to reserve additional element in some
5319 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5320 * then STACK_SIZE should be 2 instead of 1 */
5321 if (reason == FC_PUSH_VPM) {
5322 elements += 1;
5323 }
5324 break;
5325
5326 default:
5327 assert(0);
5328 break;
5329 }
5330
5331 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5332 * for all chips, so we use 4 in the final formula, not the real entry_size
5333 * for the chip */
5334 entry_size = 4;
5335
5336 entries = (elements + (entry_size - 1)) / entry_size;
5337
5338 if (entries > stack->max_entries)
5339 stack->max_entries = entries;
5340 }
5341
5342 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5343 {
5344 switch(reason) {
5345 case FC_PUSH_VPM:
5346 --ctx->bc->stack.push;
5347 assert(ctx->bc->stack.push >= 0);
5348 break;
5349 case FC_PUSH_WQM:
5350 --ctx->bc->stack.push_wqm;
5351 assert(ctx->bc->stack.push_wqm >= 0);
5352 break;
5353 case FC_LOOP:
5354 --ctx->bc->stack.loop;
5355 assert(ctx->bc->stack.loop >= 0);
5356 break;
5357 default:
5358 assert(0);
5359 break;
5360 }
5361 }
5362
5363 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5364 {
5365 switch (reason) {
5366 case FC_PUSH_VPM:
5367 ++ctx->bc->stack.push;
5368 break;
5369 case FC_PUSH_WQM:
5370 ++ctx->bc->stack.push_wqm;
5371 case FC_LOOP:
5372 ++ctx->bc->stack.loop;
5373 break;
5374 default:
5375 assert(0);
5376 }
5377
5378 callstack_update_max_depth(ctx, reason);
5379 }
5380
5381 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5382 {
5383 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5384
5385 sp->mid = realloc((void *)sp->mid,
5386 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5387 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5388 sp->num_mid++;
5389 }
5390
5391 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5392 {
5393 ctx->bc->fc_sp++;
5394 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5395 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5396 }
5397
5398 static void fc_poplevel(struct r600_shader_ctx *ctx)
5399 {
5400 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5401 free(sp->mid);
5402 sp->mid = NULL;
5403 sp->num_mid = 0;
5404 sp->start = NULL;
5405 sp->type = 0;
5406 ctx->bc->fc_sp--;
5407 }
5408
5409 #if 0
5410 static int emit_return(struct r600_shader_ctx *ctx)
5411 {
5412 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5413 return 0;
5414 }
5415
5416 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5417 {
5418
5419 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5420 ctx->bc->cf_last->pop_count = pops;
5421 /* XXX work out offset */
5422 return 0;
5423 }
5424
5425 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5426 {
5427 return 0;
5428 }
5429
5430 static void emit_testflag(struct r600_shader_ctx *ctx)
5431 {
5432
5433 }
5434
5435 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5436 {
5437 emit_testflag(ctx);
5438 emit_jump_to_offset(ctx, 1, 4);
5439 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5440 pops(ctx, ifidx + 1);
5441 emit_return(ctx);
5442 }
5443
5444 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5445 {
5446 emit_testflag(ctx);
5447
5448 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5449 ctx->bc->cf_last->pop_count = 1;
5450
5451 fc_set_mid(ctx, fc_sp);
5452
5453 pops(ctx, 1);
5454 }
5455 #endif
5456
5457 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5458 {
5459 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5460
5461 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5462 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5463 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5464 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5465 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5466 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5467 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5468 alu_type = CF_OP_ALU;
5469 }
5470
5471 emit_logic_pred(ctx, opcode, alu_type);
5472
5473 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5474
5475 fc_pushlevel(ctx, FC_IF);
5476
5477 callstack_push(ctx, FC_PUSH_VPM);
5478 return 0;
5479 }
5480
5481 static int tgsi_if(struct r600_shader_ctx *ctx)
5482 {
5483 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5484 }
5485
5486 static int tgsi_uif(struct r600_shader_ctx *ctx)
5487 {
5488 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5489 }
5490
5491 static int tgsi_else(struct r600_shader_ctx *ctx)
5492 {
5493 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5494 ctx->bc->cf_last->pop_count = 1;
5495
5496 fc_set_mid(ctx, ctx->bc->fc_sp);
5497 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5498 return 0;
5499 }
5500
5501 static int tgsi_endif(struct r600_shader_ctx *ctx)
5502 {
5503 pops(ctx, 1);
5504 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5505 R600_ERR("if/endif unbalanced in shader\n");
5506 return -1;
5507 }
5508
5509 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5510 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5511 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5512 } else {
5513 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5514 }
5515 fc_poplevel(ctx);
5516
5517 callstack_pop(ctx, FC_PUSH_VPM);
5518 return 0;
5519 }
5520
5521 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5522 {
5523 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5524 * limited to 4096 iterations, like the other LOOP_* instructions. */
5525 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5526
5527 fc_pushlevel(ctx, FC_LOOP);
5528
5529 /* check stack depth */
5530 callstack_push(ctx, FC_LOOP);
5531 return 0;
5532 }
5533
5534 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5535 {
5536 int i;
5537
5538 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5539
5540 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5541 R600_ERR("loop/endloop in shader code are not paired.\n");
5542 return -EINVAL;
5543 }
5544
5545 /* fixup loop pointers - from r600isa
5546 LOOP END points to CF after LOOP START,
5547 LOOP START point to CF after LOOP END
5548 BRK/CONT point to LOOP END CF
5549 */
5550 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5551
5552 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5553
5554 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5555 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5556 }
5557 /* XXX add LOOPRET support */
5558 fc_poplevel(ctx);
5559 callstack_pop(ctx, FC_LOOP);
5560 return 0;
5561 }
5562
5563 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5564 {
5565 unsigned int fscp;
5566
5567 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5568 {
5569 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5570 break;
5571 }
5572
5573 if (fscp == 0) {
5574 R600_ERR("Break not inside loop/endloop pair\n");
5575 return -EINVAL;
5576 }
5577
5578 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5579
5580 fc_set_mid(ctx, fscp);
5581
5582 return 0;
5583 }
5584
5585 static int tgsi_umad(struct r600_shader_ctx *ctx)
5586 {
5587 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5588 struct r600_bytecode_alu alu;
5589 int i, j, k, r;
5590 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5591
5592 /* src0 * src1 */
5593 for (i = 0; i < lasti + 1; i++) {
5594 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5595 continue;
5596
5597 if (ctx->bc->chip_class == CAYMAN) {
5598 for (j = 0 ; j < 4; j++) {
5599 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5600
5601 alu.op = ALU_OP2_MULLO_UINT;
5602 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5603 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5604 }
5605 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5606 alu.dst.sel = ctx->temp_reg;
5607 alu.dst.write = (j == i);
5608 if (j == 3)
5609 alu.last = 1;
5610 r = r600_bytecode_add_alu(ctx->bc, &alu);
5611 if (r)
5612 return r;
5613 }
5614 } else {
5615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5616
5617 alu.dst.chan = i;
5618 alu.dst.sel = ctx->temp_reg;
5619 alu.dst.write = 1;
5620
5621 alu.op = ALU_OP2_MULLO_UINT;
5622 for (j = 0; j < 2; j++) {
5623 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5624 }
5625
5626 alu.last = 1;
5627 r = r600_bytecode_add_alu(ctx->bc, &alu);
5628 if (r)
5629 return r;
5630 }
5631 }
5632
5633
5634 for (i = 0; i < lasti + 1; i++) {
5635 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5636 continue;
5637
5638 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5639 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5640
5641 alu.op = ALU_OP2_ADD_INT;
5642
5643 alu.src[0].sel = ctx->temp_reg;
5644 alu.src[0].chan = i;
5645
5646 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5647 if (i == lasti) {
5648 alu.last = 1;
5649 }
5650 r = r600_bytecode_add_alu(ctx->bc, &alu);
5651 if (r)
5652 return r;
5653 }
5654 return 0;
5655 }
5656
5657 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5658 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5659 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5660 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5661
5662 /* XXX:
5663 * For state trackers other than OpenGL, we'll want to use
5664 * _RECIP_IEEE instead.
5665 */
5666 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5667
5668 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5669 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5670 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5671 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5672 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5673 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5674 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5675 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5676 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5677 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5678 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5679 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5680 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5681 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5682 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5683 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5684 /* gap */
5685 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5686 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5687 /* gap */
5688 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5689 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5690 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5691 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5692 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5693 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5694 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5695 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5696 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5697 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5698 /* gap */
5699 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5700 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5701 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5702 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5703 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5704 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5705 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5706 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5707 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5708 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5709 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5710 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5711 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5712 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5713 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5714 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5715 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5716 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5717 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5718 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5719 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5720 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5721 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5722 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5723 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5724 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5725 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5726 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5727 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5728 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5729 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5730 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5731 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5732 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5733 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5734 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5735 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5736 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5737 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5738 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5739 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5740 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5741 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5742 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5743 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5744 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5745 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5746 /* gap */
5747 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5748 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5749 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5750 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5751 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5752 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5753 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5754 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5755 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
5756 /* gap */
5757 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5758 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5759 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5760 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5761 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5762 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5763 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5764 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5765 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5766 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5767 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5768 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5769 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5770 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5771 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5772 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5773 /* gap */
5774 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5775 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5776 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5777 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5778 /* gap */
5779 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5780 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5781 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5782 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5783 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5784 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5785 /* gap */
5786 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5787 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5788 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5789 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5790 /* gap */
5791 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5792 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
5793 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5794 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5795 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5796 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5797 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5798 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
5799 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5800 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
5801 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5802 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5803 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5804 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5805 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5806 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5807 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5808 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5809 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5810 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5811 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
5812 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5813 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
5814 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5815 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5816 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5817 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5818 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5819 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5820 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5821 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5822 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5823 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5824 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5825 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5826 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5827 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5828 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5829 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5830 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
5831 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5832 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5833 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5834 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5835 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5836 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5837 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5838 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5839 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
5840 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
5841 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
5842 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
5843 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
5844 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5845 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5846 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5847 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5848 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5849 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5850 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
5851 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5852 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5853 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
5854 };
5855
5856 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5857 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
5858 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5859 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5860 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
5861 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
5862 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5863 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5864 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5865 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5866 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5867 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5868 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5869 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5870 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5871 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5872 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5873 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5874 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5875 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5876 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5877 /* gap */
5878 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5879 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5880 /* gap */
5881 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5882 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5883 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5884 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5885 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5886 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5887 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5888 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5889 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5890 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5891 /* gap */
5892 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5893 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5894 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5895 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5896 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5897 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5898 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5899 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
5900 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5901 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5902 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5903 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5904 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5905 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5906 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5907 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5908 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5909 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5910 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5911 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5912 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5913 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5914 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5915 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5916 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5917 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5918 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5919 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5920 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5921 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
5922 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5923 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5924 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5925 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5926 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5927 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5928 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5929 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5930 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5931 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5932 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5933 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5934 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5935 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5936 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5937 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5938 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5939 /* gap */
5940 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5941 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5942 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5943 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5944 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5945 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5946 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5947 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5948 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
5949 /* gap */
5950 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5951 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5952 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5953 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5954 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5955 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5956 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5957 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5958 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5959 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5960 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5961 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5962 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5963 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5964 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5965 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5966 /* gap */
5967 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5968 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5969 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5970 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5971 /* gap */
5972 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
5973 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
5974 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
5975 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5977 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5978 /* gap */
5979 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5980 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5981 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5982 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5983 /* gap */
5984 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5985 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
5986 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5987 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5988 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5989 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5990 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5991 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
5992 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5993 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
5994 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5995 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5996 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5997 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5998 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5999 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6000 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6001 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6002 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6003 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6004 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6005 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6006 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6007 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6008 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6009 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6010 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6011 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6012 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6013 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6014 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6015 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6016 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6017 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6018 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6019 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6020 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6021 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6022 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6023 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6024 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6025 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6026 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6027 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6028 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6029 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6030 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6031 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6032 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6033 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6034 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6035 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6036 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6037 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6038 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6039 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6040 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6041 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6042 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6043 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6044 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6045 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6046 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6047 };
6048
6049 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6050 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6051 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6052 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6053 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6054 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6055 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6056 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6057 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6058 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6059 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6060 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6061 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6062 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6063 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6064 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6065 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6066 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6067 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6068 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6069 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6070 /* gap */
6071 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6072 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6073 /* gap */
6074 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6075 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6076 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6077 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6078 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6079 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6080 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6081 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6082 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6083 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6084 /* gap */
6085 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6086 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6087 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6088 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6089 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6090 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6091 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6092 {TGSI_OPCODE_KILP, 0, ALU_OP2_KILLGT, tgsi_kill}, /* predicated kill */
6093 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6094 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6095 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6096 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6097 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6098 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6099 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6100 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6101 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6102 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6103 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6104 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6105 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6106 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6107 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6108 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6109 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6110 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6113 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6114 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6115 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6116 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6117 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6118 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6119 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6120 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6121 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6122 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6123 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6124 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6125 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6126 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6127 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6128 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6129 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6130 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6131 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6132 /* gap */
6133 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6134 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6135 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6136 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6137 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6138 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6139 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6140 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6141 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6142 /* gap */
6143 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6144 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6145 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6146 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6147 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6148 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6149 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6150 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6151 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6152 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6153 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6154 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6155 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6156 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6157 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6158 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6159 /* gap */
6160 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6161 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6162 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6163 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6164 /* gap */
6165 {108, 0, ALU_OP0_NOP, tgsi_unsupported},
6166 {109, 0, ALU_OP0_NOP, tgsi_unsupported},
6167 {110, 0, ALU_OP0_NOP, tgsi_unsupported},
6168 {111, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6170 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6171 /* gap */
6172 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6173 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6174 {TGSI_OPCODE_KIL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6175 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6176 /* gap */
6177 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6178 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6179 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6180 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6181 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6182 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6183 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6184 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6185 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6186 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6187 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6188 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6189 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6190 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6191 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6192 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6193 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6194 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6195 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6196 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6197 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6198 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6199 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6200 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6201 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6202 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6203 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6204 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6205 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6206 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6207 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6208 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6209 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6210 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6211 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6212 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6213 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6214 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6215 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6216 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6217 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6218 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6219 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6220 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6221 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6222 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6223 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6224 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6225 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6226 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6227 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6228 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6229 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6230 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6231 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6232 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6233 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6234 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6235 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6236 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6237 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6238 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6239 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6240 };