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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "pipe/p_shader_tokens.h"
31 #include "tgsi/tgsi_info.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "util/u_memory.h"
36 #include <stdio.h>
37 #include <errno.h>
38 #include <byteswap.h>
39
40 /* CAYMAN notes
41 Why CAYMAN got loops for lots of instructions is explained here.
42
43 -These 8xx t-slot only ops are implemented in all vector slots.
44 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
45 These 8xx t-slot only opcodes become vector ops, with all four
46 slots expecting the arguments on sources a and b. Result is
47 broadcast to all channels.
48 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
49 These 8xx t-slot only opcodes become vector ops in the z, y, and
50 x slots.
51 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
52 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
53 SQRT_IEEE/_64
54 SIN/COS
55 The w slot may have an independent co-issued operation, or if the
56 result is required to be in the w slot, the opcode above may be
57 issued in the w slot as well.
58 The compiler must issue the source argument to slots z, y, and x
59 */
60
61 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
62 {
63 struct r600_context *rctx = (struct r600_context *)ctx;
64 struct r600_shader *rshader = &shader->shader;
65 uint32_t *ptr;
66 int i;
67
68 /* copy new shader */
69 if (shader->bo == NULL) {
70 shader->bo = (struct r600_resource*)
71 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, rshader->bc.ndw * 4);
72 if (shader->bo == NULL) {
73 return -ENOMEM;
74 }
75 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
76 if (R600_BIG_ENDIAN) {
77 for (i = 0; i < rshader->bc.ndw; ++i) {
78 ptr[i] = bswap_32(rshader->bc.bytecode[i]);
79 }
80 } else {
81 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * sizeof(*ptr));
82 }
83 rctx->ws->buffer_unmap(shader->bo->cs_buf);
84 }
85 /* build state */
86 switch (rshader->processor_type) {
87 case TGSI_PROCESSOR_VERTEX:
88 if (rctx->chip_class >= EVERGREEN) {
89 evergreen_pipe_shader_vs(ctx, shader);
90 } else {
91 r600_pipe_shader_vs(ctx, shader);
92 }
93 break;
94 case TGSI_PROCESSOR_FRAGMENT:
95 if (rctx->chip_class >= EVERGREEN) {
96 evergreen_pipe_shader_ps(ctx, shader);
97 } else {
98 r600_pipe_shader_ps(ctx, shader);
99 }
100 break;
101 default:
102 return -EINVAL;
103 }
104 return 0;
105 }
106
107 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
108 struct r600_pipe_shader *pipeshader,
109 struct r600_shader_key key);
110
111 int r600_pipe_shader_create(struct pipe_context *ctx,
112 struct r600_pipe_shader *shader,
113 struct r600_shader_key key)
114 {
115 static int dump_shaders = -1;
116 struct r600_context *rctx = (struct r600_context *)ctx;
117 struct r600_pipe_shader_selector *sel = shader->selector;
118 int r;
119
120 /* Would like some magic "get_bool_option_once" routine.
121 */
122 if (dump_shaders == -1)
123 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
124
125 if (dump_shaders) {
126 fprintf(stderr, "--------------------------------------------------------------\n");
127 tgsi_dump(sel->tokens, 0);
128
129 if (sel->so.num_outputs) {
130 unsigned i;
131 fprintf(stderr, "STREAMOUT\n");
132 for (i = 0; i < sel->so.num_outputs; i++) {
133 unsigned mask = ((1 << sel->so.output[i].num_components) - 1) <<
134 sel->so.output[i].start_component;
135 fprintf(stderr, " %i: MEM_STREAM0_BUF%i OUT[%i].%s%s%s%s\n", i,
136 sel->so.output[i].output_buffer, sel->so.output[i].register_index,
137 mask & 1 ? "x" : "_",
138 (mask >> 1) & 1 ? "y" : "_",
139 (mask >> 2) & 1 ? "z" : "_",
140 (mask >> 3) & 1 ? "w" : "_");
141 }
142 }
143 }
144 r = r600_shader_from_tgsi(rctx->screen, shader, key);
145 if (r) {
146 R600_ERR("translation from TGSI failed !\n");
147 return r;
148 }
149 r = r600_bytecode_build(&shader->shader.bc);
150 if (r) {
151 R600_ERR("building bytecode failed !\n");
152 return r;
153 }
154 if (dump_shaders) {
155 r600_bytecode_dump(&shader->shader.bc);
156 fprintf(stderr, "______________________________________________________________\n");
157 }
158 return r600_pipe_shader(ctx, shader);
159 }
160
161 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
162 {
163 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
164 r600_bytecode_clear(&shader->shader.bc);
165 }
166
167 /*
168 * tgsi -> r600 shader
169 */
170 struct r600_shader_tgsi_instruction;
171
172 struct r600_shader_src {
173 unsigned sel;
174 unsigned swizzle[4];
175 unsigned neg;
176 unsigned abs;
177 unsigned rel;
178 uint32_t value[4];
179 };
180
181 struct r600_shader_ctx {
182 struct tgsi_shader_info info;
183 struct tgsi_parse_context parse;
184 const struct tgsi_token *tokens;
185 unsigned type;
186 unsigned file_offset[TGSI_FILE_COUNT];
187 unsigned temp_reg;
188 struct r600_shader_tgsi_instruction *inst_info;
189 struct r600_bytecode *bc;
190 struct r600_shader *shader;
191 struct r600_shader_src src[4];
192 uint32_t *literals;
193 uint32_t nliterals;
194 uint32_t max_driver_temp_used;
195 boolean use_llvm;
196 /* needed for evergreen interpolation */
197 boolean input_centroid;
198 boolean input_linear;
199 boolean input_perspective;
200 int num_interp_gpr;
201 int face_gpr;
202 int colors_used;
203 boolean clip_vertex_write;
204 unsigned cv_output;
205 int fragcoord_input;
206 int native_integers;
207 };
208
209 struct r600_shader_tgsi_instruction {
210 unsigned tgsi_opcode;
211 unsigned is_op3;
212 unsigned r600_opcode;
213 int (*process)(struct r600_shader_ctx *ctx);
214 };
215
216 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
217 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
218 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only);
219 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
220 static int tgsi_else(struct r600_shader_ctx *ctx);
221 static int tgsi_endif(struct r600_shader_ctx *ctx);
222 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
223 static int tgsi_endloop(struct r600_shader_ctx *ctx);
224 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
225
226 /*
227 * bytestream -> r600 shader
228 *
229 * These functions are used to transform the output of the LLVM backend into
230 * struct r600_bytecode.
231 */
232
233 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
234 unsigned char * bytes, unsigned num_bytes);
235
236 #ifdef HAVE_OPENCL
237 int r600_compute_shader_create(struct pipe_context * ctx,
238 LLVMModuleRef mod, struct r600_bytecode * bytecode)
239 {
240 struct r600_context *r600_ctx = (struct r600_context *)ctx;
241 unsigned char * bytes;
242 unsigned byte_count;
243 struct r600_shader_ctx shader_ctx;
244 unsigned dump = 0;
245
246 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
247 dump = 1;
248 }
249
250 r600_llvm_compile(mod, &bytes, &byte_count, r600_ctx->family , dump);
251 shader_ctx.bc = bytecode;
252 r600_bytecode_init(shader_ctx.bc, r600_ctx->chip_class, r600_ctx->family,
253 r600_ctx->screen->msaa_texture_support);
254 shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
255 r600_bytecode_from_byte_stream(&shader_ctx, bytes, byte_count);
256 if (shader_ctx.bc->chip_class == CAYMAN) {
257 cm_bytecode_add_cf_end(shader_ctx.bc);
258 }
259 r600_bytecode_build(shader_ctx.bc);
260 if (dump) {
261 r600_bytecode_dump(shader_ctx.bc);
262 }
263 free(bytes);
264 return 1;
265 }
266
267 #endif /* HAVE_OPENCL */
268
269 static uint32_t i32_from_byte_stream(unsigned char * bytes,
270 unsigned * bytes_read)
271 {
272 unsigned i;
273 uint32_t out = 0;
274 for (i = 0; i < 4; i++) {
275 out |= bytes[(*bytes_read)++] << (8 * i);
276 }
277 return out;
278 }
279
280 static unsigned r600_src_from_byte_stream(unsigned char * bytes,
281 unsigned bytes_read, struct r600_bytecode_alu * alu, unsigned src_idx)
282 {
283 unsigned i;
284 unsigned sel0, sel1;
285 sel0 = bytes[bytes_read++];
286 sel1 = bytes[bytes_read++];
287 alu->src[src_idx].sel = sel0 | (sel1 << 8);
288 alu->src[src_idx].chan = bytes[bytes_read++];
289 alu->src[src_idx].neg = bytes[bytes_read++];
290 alu->src[src_idx].abs = bytes[bytes_read++];
291 alu->src[src_idx].rel = bytes[bytes_read++];
292 alu->src[src_idx].kc_bank = bytes[bytes_read++];
293 for (i = 0; i < 4; i++) {
294 alu->src[src_idx].value |= bytes[bytes_read++] << (i * 8);
295 }
296 return bytes_read;
297 }
298
299 static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
300 unsigned char * bytes, unsigned bytes_read)
301 {
302 unsigned src_idx;
303 struct r600_bytecode_alu alu;
304 unsigned src_const_reg[3];
305 uint32_t word0, word1;
306
307 memset(&alu, 0, sizeof(alu));
308 for(src_idx = 0; src_idx < 3; src_idx++) {
309 unsigned i;
310 src_const_reg[src_idx] = bytes[bytes_read++];
311 for (i = 0; i < 4; i++) {
312 alu.src[src_idx].value |= bytes[bytes_read++] << (i * 8);
313 }
314 }
315
316 word0 = i32_from_byte_stream(bytes, &bytes_read);
317 word1 = i32_from_byte_stream(bytes, &bytes_read);
318
319 switch(ctx->bc->chip_class) {
320 case R600:
321 r600_bytecode_alu_read(&alu, word0, word1);
322 break;
323 case R700:
324 case EVERGREEN:
325 case CAYMAN:
326 r700_bytecode_alu_read(&alu, word0, word1);
327 break;
328 }
329
330 for(src_idx = 0; src_idx < 3; src_idx++) {
331 if (src_const_reg[src_idx])
332 alu.src[src_idx].sel += 512;
333 }
334
335 #if HAVE_LLVM < 0x0302
336 if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE) ||
337 alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE) ||
338 alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT) ||
339 alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT)) {
340 alu.update_pred = 1;
341 alu.dst.write = 0;
342 alu.src[1].sel = V_SQ_ALU_SRC_0;
343 alu.src[1].chan = 0;
344 alu.last = 1;
345 }
346 #endif
347
348 if (alu.execute_mask) {
349 alu.pred_sel = 0;
350 r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
351 } else {
352 r600_bytecode_add_alu(ctx->bc, &alu);
353 }
354
355 /* XXX: Handle other KILL instructions */
356 if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT)) {
357 ctx->shader->uses_kill = 1;
358 /* XXX: This should be enforced in the LLVM backend. */
359 ctx->bc->force_add_cf = 1;
360 }
361 return bytes_read;
362 }
363
364 static void llvm_if(struct r600_shader_ctx *ctx, struct r600_bytecode_alu * alu,
365 unsigned pred_inst)
366 {
367 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
368 fc_pushlevel(ctx, FC_IF);
369 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
370 }
371
372 static void r600_break_from_byte_stream(struct r600_shader_ctx *ctx,
373 struct r600_bytecode_alu *alu, unsigned compare_opcode)
374 {
375 unsigned opcode = TGSI_OPCODE_BRK;
376 if (ctx->bc->chip_class == CAYMAN)
377 ctx->inst_info = &cm_shader_tgsi_instruction[opcode];
378 else if (ctx->bc->chip_class >= EVERGREEN)
379 ctx->inst_info = &eg_shader_tgsi_instruction[opcode];
380 else
381 ctx->inst_info = &r600_shader_tgsi_instruction[opcode];
382 llvm_if(ctx, alu, compare_opcode);
383 tgsi_loop_brk_cont(ctx);
384 tgsi_endif(ctx);
385 }
386
387 static unsigned r600_fc_from_byte_stream(struct r600_shader_ctx *ctx,
388 unsigned char * bytes, unsigned bytes_read)
389 {
390 struct r600_bytecode_alu alu;
391 unsigned inst;
392 memset(&alu, 0, sizeof(alu));
393 bytes_read = r600_src_from_byte_stream(bytes, bytes_read, &alu, 0);
394 inst = bytes[bytes_read++];
395 switch (inst) {
396 case 0: /* FC_IF */
397 llvm_if(ctx, &alu,
398 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
399 break;
400 case 1: /* FC_IF_INT */
401 llvm_if(ctx, &alu,
402 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
403 break;
404 case 2: /* FC_ELSE */
405 tgsi_else(ctx);
406 break;
407 case 3: /* FC_ENDIF */
408 tgsi_endif(ctx);
409 break;
410 case 4: /* FC_BGNLOOP */
411 tgsi_bgnloop(ctx);
412 break;
413 case 5: /* FC_ENDLOOP */
414 tgsi_endloop(ctx);
415 break;
416 case 6: /* FC_BREAK */
417 r600_break_from_byte_stream(ctx, &alu,
418 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT));
419 break;
420 case 7: /* FC_BREAK_NZ_INT */
421 r600_break_from_byte_stream(ctx, &alu,
422 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
423 break;
424 case 8: /* FC_CONTINUE */
425 {
426 unsigned opcode = TGSI_OPCODE_CONT;
427 if (ctx->bc->chip_class == CAYMAN) {
428 ctx->inst_info =
429 &cm_shader_tgsi_instruction[opcode];
430 } else if (ctx->bc->chip_class >= EVERGREEN) {
431 ctx->inst_info =
432 &eg_shader_tgsi_instruction[opcode];
433 } else {
434 ctx->inst_info =
435 &r600_shader_tgsi_instruction[opcode];
436 }
437 tgsi_loop_brk_cont(ctx);
438 }
439 break;
440 case 9: /* FC_BREAK_Z_INT */
441 r600_break_from_byte_stream(ctx, &alu,
442 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT));
443 break;
444 case 10: /* FC_BREAK_NZ */
445 r600_break_from_byte_stream(ctx, &alu,
446 CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
447 break;
448 }
449
450 return bytes_read;
451 }
452
453 static unsigned r600_tex_from_byte_stream(struct r600_shader_ctx *ctx,
454 unsigned char * bytes, unsigned bytes_read)
455 {
456 struct r600_bytecode_tex tex;
457
458 tex.inst = bytes[bytes_read++];
459 tex.resource_id = bytes[bytes_read++];
460 tex.src_gpr = bytes[bytes_read++];
461 tex.src_rel = bytes[bytes_read++];
462 tex.dst_gpr = bytes[bytes_read++];
463 tex.dst_rel = bytes[bytes_read++];
464 tex.dst_sel_x = bytes[bytes_read++];
465 tex.dst_sel_y = bytes[bytes_read++];
466 tex.dst_sel_z = bytes[bytes_read++];
467 tex.dst_sel_w = bytes[bytes_read++];
468 tex.lod_bias = bytes[bytes_read++];
469 tex.coord_type_x = bytes[bytes_read++];
470 tex.coord_type_y = bytes[bytes_read++];
471 tex.coord_type_z = bytes[bytes_read++];
472 tex.coord_type_w = bytes[bytes_read++];
473 tex.offset_x = bytes[bytes_read++];
474 tex.offset_y = bytes[bytes_read++];
475 tex.offset_z = bytes[bytes_read++];
476 tex.sampler_id = bytes[bytes_read++];
477 tex.src_sel_x = bytes[bytes_read++];
478 tex.src_sel_y = bytes[bytes_read++];
479 tex.src_sel_z = bytes[bytes_read++];
480 tex.src_sel_w = bytes[bytes_read++];
481
482 r600_bytecode_add_tex(ctx->bc, &tex);
483
484 return bytes_read;
485 }
486
487 static int r600_vtx_from_byte_stream(struct r600_shader_ctx *ctx,
488 unsigned char * bytes, unsigned bytes_read)
489 {
490 struct r600_bytecode_vtx vtx;
491
492 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
493 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
494 uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
495
496 memset(&vtx, 0, sizeof(vtx));
497
498 /* WORD0 */
499 vtx.inst = G_SQ_VTX_WORD0_VTX_INST(word0);
500 vtx.fetch_type = G_SQ_VTX_WORD0_FETCH_TYPE(word0);
501 vtx.buffer_id = G_SQ_VTX_WORD0_BUFFER_ID(word0);
502 vtx.src_gpr = G_SQ_VTX_WORD0_SRC_GPR(word0);
503 vtx.src_sel_x = G_SQ_VTX_WORD0_SRC_SEL_X(word0);
504 vtx.mega_fetch_count = G_SQ_VTX_WORD0_MEGA_FETCH_COUNT(word0);
505
506 /* WORD1 */
507 vtx.dst_gpr = G_SQ_VTX_WORD1_GPR_DST_GPR(word1);
508 vtx.dst_sel_x = G_SQ_VTX_WORD1_DST_SEL_X(word1);
509 vtx.dst_sel_y = G_SQ_VTX_WORD1_DST_SEL_Y(word1);
510 vtx.dst_sel_z = G_SQ_VTX_WORD1_DST_SEL_Z(word1);
511 vtx.dst_sel_w = G_SQ_VTX_WORD1_DST_SEL_W(word1);
512 vtx.use_const_fields = G_SQ_VTX_WORD1_USE_CONST_FIELDS(word1);
513 vtx.data_format = G_SQ_VTX_WORD1_DATA_FORMAT(word1);
514 vtx.num_format_all = G_SQ_VTX_WORD1_NUM_FORMAT_ALL(word1);
515 vtx.format_comp_all = G_SQ_VTX_WORD1_FORMAT_COMP_ALL(word1);
516 vtx.srf_mode_all = G_SQ_VTX_WORD1_SRF_MODE_ALL(word1);
517
518 /* WORD 2*/
519 vtx.offset = G_SQ_VTX_WORD2_OFFSET(word2);
520 vtx.endian = G_SQ_VTX_WORD2_ENDIAN_SWAP(word2);
521
522 if (r600_bytecode_add_vtx(ctx->bc, &vtx)) {
523 fprintf(stderr, "Error adding vtx\n");
524 }
525 /* Use the Texture Cache */
526 ctx->bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX;
527 return bytes_read;
528 }
529
530 static int r600_export_from_byte_stream(struct r600_shader_ctx *ctx,
531 unsigned char * bytes, unsigned bytes_read)
532 {
533 struct r600_bytecode_output output;
534 memset(&output, 0, sizeof(struct r600_bytecode_output));
535 uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
536 uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
537 if (ctx->bc->chip_class >= EVERGREEN)
538 eg_bytecode_export_read(&output, word0,word1);
539 else
540 r600_bytecode_export_read(&output, word0,word1);
541 r600_bytecode_add_output(ctx->bc, &output);
542 return bytes_read;
543 }
544
545 static void r600_bytecode_from_byte_stream(struct r600_shader_ctx *ctx,
546 unsigned char * bytes, unsigned num_bytes)
547 {
548 unsigned bytes_read = 0;
549 unsigned i, byte;
550 while (bytes_read < num_bytes) {
551 char inst_type = bytes[bytes_read++];
552 switch (inst_type) {
553 case 0:
554 bytes_read = r600_alu_from_byte_stream(ctx, bytes,
555 bytes_read);
556 break;
557 case 1:
558 bytes_read = r600_tex_from_byte_stream(ctx, bytes,
559 bytes_read);
560 break;
561 case 2:
562 bytes_read = r600_fc_from_byte_stream(ctx, bytes,
563 bytes_read);
564 break;
565 case 3:
566 r600_bytecode_add_cfinst(ctx->bc, CF_NATIVE);
567 for (i = 0; i < 2; i++) {
568 for (byte = 0 ; byte < 4; byte++) {
569 ctx->bc->cf_last->isa[i] |=
570 (bytes[bytes_read++] << (byte * 8));
571 }
572 }
573 break;
574
575 case 4:
576 bytes_read = r600_vtx_from_byte_stream(ctx, bytes,
577 bytes_read);
578 break;
579 case 5:
580 bytes_read = r600_export_from_byte_stream(ctx, bytes,
581 bytes_read);
582 break;
583 default:
584 /* XXX: Error here */
585 break;
586 }
587 }
588 }
589
590 /* End bytestream -> r600 shader functions*/
591
592 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
593 {
594 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
595 int j;
596
597 if (i->Instruction.NumDstRegs > 1) {
598 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
599 return -EINVAL;
600 }
601 if (i->Instruction.Predicate) {
602 R600_ERR("predicate unsupported\n");
603 return -EINVAL;
604 }
605 #if 0
606 if (i->Instruction.Label) {
607 R600_ERR("label unsupported\n");
608 return -EINVAL;
609 }
610 #endif
611 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
612 if (i->Src[j].Register.Dimension) {
613 R600_ERR("unsupported src %d (dimension %d)\n", j,
614 i->Src[j].Register.Dimension);
615 return -EINVAL;
616 }
617 }
618 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
619 if (i->Dst[j].Register.Dimension) {
620 R600_ERR("unsupported dst (dimension)\n");
621 return -EINVAL;
622 }
623 }
624 return 0;
625 }
626
627 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
628 {
629 int i, r;
630 struct r600_bytecode_alu alu;
631 int gpr = 0, base_chan = 0;
632 int ij_index = 0;
633
634 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
635 ij_index = 0;
636 if (ctx->shader->input[input].centroid)
637 ij_index++;
638 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
639 ij_index = 0;
640 /* if we have perspective add one */
641 if (ctx->input_perspective) {
642 ij_index++;
643 /* if we have perspective centroid */
644 if (ctx->input_centroid)
645 ij_index++;
646 }
647 if (ctx->shader->input[input].centroid)
648 ij_index++;
649 }
650
651 /* work out gpr and base_chan from index */
652 gpr = ij_index / 2;
653 base_chan = (2 * (ij_index % 2)) + 1;
654
655 for (i = 0; i < 8; i++) {
656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
657
658 if (i < 4)
659 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW;
660 else
661 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY;
662
663 if ((i > 1) && (i < 6)) {
664 alu.dst.sel = ctx->shader->input[input].gpr;
665 alu.dst.write = 1;
666 }
667
668 alu.dst.chan = i % 4;
669
670 alu.src[0].sel = gpr;
671 alu.src[0].chan = (base_chan - (i % 2));
672
673 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
674
675 alu.bank_swizzle_force = SQ_ALU_VEC_210;
676 if ((i % 4) == 3)
677 alu.last = 1;
678 r = r600_bytecode_add_alu(ctx->bc, &alu);
679 if (r)
680 return r;
681 }
682 return 0;
683 }
684
685 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
686 {
687 int i, r;
688 struct r600_bytecode_alu alu;
689
690 for (i = 0; i < 4; i++) {
691 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
692
693 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0;
694
695 alu.dst.sel = ctx->shader->input[input].gpr;
696 alu.dst.write = 1;
697
698 alu.dst.chan = i;
699
700 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
701 alu.src[0].chan = i;
702
703 if (i == 3)
704 alu.last = 1;
705 r = r600_bytecode_add_alu(ctx->bc, &alu);
706 if (r)
707 return r;
708 }
709 return 0;
710 }
711
712 /*
713 * Special export handling in shaders
714 *
715 * shader export ARRAY_BASE for EXPORT_POS:
716 * 60 is position
717 * 61 is misc vector
718 * 62, 63 are clip distance vectors
719 *
720 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
721 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
722 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
723 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
724 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
725 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
726 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
727 * exclusive from render target index)
728 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
729 *
730 *
731 * shader export ARRAY_BASE for EXPORT_PIXEL:
732 * 0-7 CB targets
733 * 61 computed Z vector
734 *
735 * The use of the values exported in the computed Z vector are controlled
736 * by DB_SHADER_CONTROL:
737 * Z_EXPORT_ENABLE - Z as a float in RED
738 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
739 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
740 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
741 * DB_SOURCE_FORMAT - export control restrictions
742 *
743 */
744
745
746 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
747 static int r600_spi_sid(struct r600_shader_io * io)
748 {
749 int index, name = io->name;
750
751 /* These params are handled differently, they don't need
752 * semantic indices, so we'll use 0 for them.
753 */
754 if (name == TGSI_SEMANTIC_POSITION ||
755 name == TGSI_SEMANTIC_PSIZE ||
756 name == TGSI_SEMANTIC_FACE)
757 index = 0;
758 else {
759 if (name == TGSI_SEMANTIC_GENERIC) {
760 /* For generic params simply use sid from tgsi */
761 index = io->sid;
762 } else {
763 /* For non-generic params - pack name and sid into 8 bits */
764 index = 0x80 | (name<<3) | (io->sid);
765 }
766
767 /* Make sure that all really used indices have nonzero value, so
768 * we can just compare it to 0 later instead of comparing the name
769 * with different values to detect special cases. */
770 index++;
771 }
772
773 return index;
774 };
775
776 /* turn input into interpolate on EG */
777 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
778 {
779 int r = 0;
780
781 if (ctx->shader->input[index].spi_sid) {
782 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
783 if (!ctx->use_llvm) {
784 if (ctx->shader->input[index].interpolate > 0) {
785 r = evergreen_interp_alu(ctx, index);
786 } else {
787 r = evergreen_interp_flat(ctx, index);
788 }
789 }
790 }
791 return r;
792 }
793
794 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
795 {
796 struct r600_bytecode_alu alu;
797 int i, r;
798 int gpr_front = ctx->shader->input[front].gpr;
799 int gpr_back = ctx->shader->input[back].gpr;
800
801 for (i = 0; i < 4; i++) {
802 memset(&alu, 0, sizeof(alu));
803 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
804 alu.is_op3 = 1;
805 alu.dst.write = 1;
806 alu.dst.sel = gpr_front;
807 alu.src[0].sel = ctx->face_gpr;
808 alu.src[1].sel = gpr_front;
809 alu.src[2].sel = gpr_back;
810
811 alu.dst.chan = i;
812 alu.src[1].chan = i;
813 alu.src[2].chan = i;
814 alu.last = (i==3);
815
816 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
817 return r;
818 }
819
820 return 0;
821 }
822
823 static int tgsi_declaration(struct r600_shader_ctx *ctx)
824 {
825 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
826 unsigned i;
827 int r;
828
829 switch (d->Declaration.File) {
830 case TGSI_FILE_INPUT:
831 i = ctx->shader->ninput++;
832 ctx->shader->input[i].name = d->Semantic.Name;
833 ctx->shader->input[i].sid = d->Semantic.Index;
834 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
835 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
836 ctx->shader->input[i].centroid = d->Interp.Centroid;
837 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
838 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
839 switch (ctx->shader->input[i].name) {
840 case TGSI_SEMANTIC_FACE:
841 ctx->face_gpr = ctx->shader->input[i].gpr;
842 break;
843 case TGSI_SEMANTIC_COLOR:
844 ctx->colors_used++;
845 break;
846 case TGSI_SEMANTIC_POSITION:
847 ctx->fragcoord_input = i;
848 break;
849 }
850 if (ctx->bc->chip_class >= EVERGREEN) {
851 if ((r = evergreen_interp_input(ctx, i)))
852 return r;
853 }
854 }
855 break;
856 case TGSI_FILE_OUTPUT:
857 i = ctx->shader->noutput++;
858 ctx->shader->output[i].name = d->Semantic.Name;
859 ctx->shader->output[i].sid = d->Semantic.Index;
860 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
861 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
862 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
863 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
864 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
865 switch (d->Semantic.Name) {
866 case TGSI_SEMANTIC_CLIPDIST:
867 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
868 break;
869 case TGSI_SEMANTIC_PSIZE:
870 ctx->shader->vs_out_misc_write = 1;
871 ctx->shader->vs_out_point_size = 1;
872 break;
873 case TGSI_SEMANTIC_CLIPVERTEX:
874 ctx->clip_vertex_write = TRUE;
875 ctx->cv_output = i;
876 break;
877 }
878 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
879 switch (d->Semantic.Name) {
880 case TGSI_SEMANTIC_COLOR:
881 ctx->shader->nr_ps_max_color_exports++;
882 break;
883 }
884 }
885 break;
886 case TGSI_FILE_CONSTANT:
887 case TGSI_FILE_TEMPORARY:
888 case TGSI_FILE_SAMPLER:
889 case TGSI_FILE_ADDRESS:
890 break;
891
892 case TGSI_FILE_SYSTEM_VALUE:
893 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
894 if (!ctx->native_integers) {
895 struct r600_bytecode_alu alu;
896 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
897
898 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
899 alu.src[0].sel = 0;
900 alu.src[0].chan = 3;
901
902 alu.dst.sel = 0;
903 alu.dst.chan = 3;
904 alu.dst.write = 1;
905 alu.last = 1;
906
907 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
908 return r;
909 }
910 break;
911 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
912 break;
913 default:
914 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
915 return -EINVAL;
916 }
917 return 0;
918 }
919
920 static int r600_get_temp(struct r600_shader_ctx *ctx)
921 {
922 return ctx->temp_reg + ctx->max_driver_temp_used++;
923 }
924
925 /*
926 * for evergreen we need to scan the shader to find the number of GPRs we need to
927 * reserve for interpolation.
928 *
929 * we need to know if we are going to emit
930 * any centroid inputs
931 * if perspective and linear are required
932 */
933 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
934 {
935 int i;
936 int num_baryc;
937
938 ctx->input_linear = FALSE;
939 ctx->input_perspective = FALSE;
940 ctx->input_centroid = FALSE;
941 ctx->num_interp_gpr = 1;
942
943 /* any centroid inputs */
944 for (i = 0; i < ctx->info.num_inputs; i++) {
945 /* skip position/face */
946 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
947 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
948 continue;
949 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
950 ctx->input_linear = TRUE;
951 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
952 ctx->input_perspective = TRUE;
953 if (ctx->info.input_centroid[i])
954 ctx->input_centroid = TRUE;
955 }
956
957 num_baryc = 0;
958 /* ignoring sample for now */
959 if (ctx->input_perspective)
960 num_baryc++;
961 if (ctx->input_linear)
962 num_baryc++;
963 if (ctx->input_centroid)
964 num_baryc *= 2;
965
966 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
967
968 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
969 return ctx->num_interp_gpr;
970 }
971
972 static void tgsi_src(struct r600_shader_ctx *ctx,
973 const struct tgsi_full_src_register *tgsi_src,
974 struct r600_shader_src *r600_src)
975 {
976 memset(r600_src, 0, sizeof(*r600_src));
977 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
978 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
979 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
980 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
981 r600_src->neg = tgsi_src->Register.Negate;
982 r600_src->abs = tgsi_src->Register.Absolute;
983
984 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
985 int index;
986 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
987 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
988 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
989
990 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
991 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
992 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
993 return;
994 }
995 index = tgsi_src->Register.Index;
996 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
997 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
998 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
999 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1000 r600_src->swizzle[0] = 3;
1001 r600_src->swizzle[1] = 3;
1002 r600_src->swizzle[2] = 3;
1003 r600_src->swizzle[3] = 3;
1004 r600_src->sel = 0;
1005 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1006 r600_src->swizzle[0] = 0;
1007 r600_src->swizzle[1] = 0;
1008 r600_src->swizzle[2] = 0;
1009 r600_src->swizzle[3] = 0;
1010 r600_src->sel = 0;
1011 }
1012 } else {
1013 if (tgsi_src->Register.Indirect)
1014 r600_src->rel = V_SQ_REL_RELATIVE;
1015 r600_src->sel = tgsi_src->Register.Index;
1016 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1017 }
1018 }
1019
1020 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg)
1021 {
1022 struct r600_bytecode_vtx vtx;
1023 unsigned int ar_reg;
1024 int r;
1025
1026 if (offset) {
1027 struct r600_bytecode_alu alu;
1028
1029 memset(&alu, 0, sizeof(alu));
1030
1031 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
1032 alu.src[0].sel = ctx->bc->ar_reg;
1033
1034 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1035 alu.src[1].value = offset;
1036
1037 alu.dst.sel = dst_reg;
1038 alu.dst.write = 1;
1039 alu.last = 1;
1040
1041 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1042 return r;
1043
1044 ar_reg = dst_reg;
1045 } else {
1046 ar_reg = ctx->bc->ar_reg;
1047 }
1048
1049 memset(&vtx, 0, sizeof(vtx));
1050 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
1051 vtx.src_gpr = ar_reg;
1052 vtx.mega_fetch_count = 16;
1053 vtx.dst_gpr = dst_reg;
1054 vtx.dst_sel_x = 0; /* SEL_X */
1055 vtx.dst_sel_y = 1; /* SEL_Y */
1056 vtx.dst_sel_z = 2; /* SEL_Z */
1057 vtx.dst_sel_w = 3; /* SEL_W */
1058 vtx.data_format = FMT_32_32_32_32_FLOAT;
1059 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1060 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1061 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1062 vtx.endian = r600_endian_swap(32);
1063
1064 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1065 return r;
1066
1067 return 0;
1068 }
1069
1070 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1071 {
1072 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1073 struct r600_bytecode_alu alu;
1074 int i, j, k, nconst, r;
1075
1076 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1077 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1078 nconst++;
1079 }
1080 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1081 }
1082 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1083 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1084 continue;
1085 }
1086
1087 if (ctx->src[i].rel) {
1088 int treg = r600_get_temp(ctx);
1089 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].sel - 512, treg)))
1090 return r;
1091
1092 ctx->src[i].sel = treg;
1093 ctx->src[i].rel = 0;
1094 j--;
1095 } else if (j > 0) {
1096 int treg = r600_get_temp(ctx);
1097 for (k = 0; k < 4; k++) {
1098 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1099 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1100 alu.src[0].sel = ctx->src[i].sel;
1101 alu.src[0].chan = k;
1102 alu.src[0].rel = ctx->src[i].rel;
1103 alu.dst.sel = treg;
1104 alu.dst.chan = k;
1105 alu.dst.write = 1;
1106 if (k == 3)
1107 alu.last = 1;
1108 r = r600_bytecode_add_alu(ctx->bc, &alu);
1109 if (r)
1110 return r;
1111 }
1112 ctx->src[i].sel = treg;
1113 ctx->src[i].rel =0;
1114 j--;
1115 }
1116 }
1117 return 0;
1118 }
1119
1120 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1121 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1122 {
1123 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1124 struct r600_bytecode_alu alu;
1125 int i, j, k, nliteral, r;
1126
1127 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1128 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1129 nliteral++;
1130 }
1131 }
1132 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1133 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1134 int treg = r600_get_temp(ctx);
1135 for (k = 0; k < 4; k++) {
1136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1137 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1138 alu.src[0].sel = ctx->src[i].sel;
1139 alu.src[0].chan = k;
1140 alu.src[0].value = ctx->src[i].value[k];
1141 alu.dst.sel = treg;
1142 alu.dst.chan = k;
1143 alu.dst.write = 1;
1144 if (k == 3)
1145 alu.last = 1;
1146 r = r600_bytecode_add_alu(ctx->bc, &alu);
1147 if (r)
1148 return r;
1149 }
1150 ctx->src[i].sel = treg;
1151 j--;
1152 }
1153 }
1154 return 0;
1155 }
1156
1157 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1158 {
1159 int i, r, count = ctx->shader->ninput;
1160
1161 for (i = 0; i < count; i++) {
1162 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1163 unsigned back_facing_reg = ctx->shader->input[i].potential_back_facing_reg;
1164 if (ctx->bc->chip_class >= EVERGREEN) {
1165 if ((r = evergreen_interp_input(ctx, back_facing_reg)))
1166 return r;
1167 }
1168
1169 if (!ctx->use_llvm) {
1170 r = select_twoside_color(ctx, i, back_facing_reg);
1171 if (r)
1172 return r;
1173 }
1174 }
1175 }
1176 return 0;
1177 }
1178
1179 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
1180 struct r600_pipe_shader *pipeshader,
1181 struct r600_shader_key key)
1182 {
1183 struct r600_shader *shader = &pipeshader->shader;
1184 struct tgsi_token *tokens = pipeshader->selector->tokens;
1185 struct pipe_stream_output_info so = pipeshader->selector->so;
1186 struct tgsi_full_immediate *immediate;
1187 struct tgsi_full_property *property;
1188 struct r600_shader_ctx ctx;
1189 struct r600_bytecode_output output[32];
1190 unsigned output_done, noutput;
1191 unsigned opcode;
1192 int i, j, k, r = 0;
1193 int next_pixel_base = 0, next_pos_base = 60, next_param_base = 0;
1194 /* Declarations used by llvm code */
1195 bool use_llvm = false;
1196 unsigned char * inst_bytes = NULL;
1197 unsigned inst_byte_count = 0;
1198
1199 #ifdef R600_USE_LLVM
1200 use_llvm = debug_get_bool_option("R600_LLVM", TRUE);
1201 #endif
1202 ctx.bc = &shader->bc;
1203 ctx.shader = shader;
1204 ctx.native_integers = true;
1205
1206 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
1207 rscreen->msaa_texture_support);
1208 ctx.tokens = tokens;
1209 tgsi_scan_shader(tokens, &ctx.info);
1210 tgsi_parse_init(&ctx.parse, tokens);
1211 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1212 shader->processor_type = ctx.type;
1213 ctx.bc->type = shader->processor_type;
1214
1215 ctx.face_gpr = -1;
1216 ctx.fragcoord_input = -1;
1217 ctx.colors_used = 0;
1218 ctx.clip_vertex_write = 0;
1219
1220 shader->nr_ps_color_exports = 0;
1221 shader->nr_ps_max_color_exports = 0;
1222
1223 shader->two_side = key.color_two_side;
1224
1225 /* register allocations */
1226 /* Values [0,127] correspond to GPR[0..127].
1227 * Values [128,159] correspond to constant buffer bank 0
1228 * Values [160,191] correspond to constant buffer bank 1
1229 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1230 * Values [256,287] correspond to constant buffer bank 2 (EG)
1231 * Values [288,319] correspond to constant buffer bank 3 (EG)
1232 * Other special values are shown in the list below.
1233 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1234 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1235 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1236 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1237 * 248 SQ_ALU_SRC_0: special constant 0.0.
1238 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1239 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1240 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1241 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1242 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1243 * 254 SQ_ALU_SRC_PV: previous vector result.
1244 * 255 SQ_ALU_SRC_PS: previous scalar result.
1245 */
1246 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1247 ctx.file_offset[i] = 0;
1248 }
1249 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1250 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1251 if (ctx.bc->chip_class >= EVERGREEN) {
1252 r600_bytecode_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
1253 } else {
1254 r600_bytecode_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
1255 }
1256 }
1257 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1258 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1259 }
1260
1261 #ifdef R600_USE_LLVM
1262 if (use_llvm && ctx.info.indirect_files) {
1263 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1264 "indirect adressing. Falling back to TGSI "
1265 "backend.\n");
1266 use_llvm = 0;
1267 }
1268 #endif
1269 ctx.use_llvm = use_llvm;
1270
1271 if (use_llvm) {
1272 ctx.file_offset[TGSI_FILE_OUTPUT] =
1273 ctx.file_offset[TGSI_FILE_INPUT];
1274 } else {
1275 ctx.file_offset[TGSI_FILE_OUTPUT] =
1276 ctx.file_offset[TGSI_FILE_INPUT] +
1277 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1278 }
1279 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1280 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1281
1282 /* Outside the GPR range. This will be translated to one of the
1283 * kcache banks later. */
1284 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1285
1286 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1287 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1288 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1289 ctx.temp_reg = ctx.bc->ar_reg + 1;
1290
1291 ctx.nliterals = 0;
1292 ctx.literals = NULL;
1293 shader->fs_write_all = FALSE;
1294 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1295 tgsi_parse_token(&ctx.parse);
1296 switch (ctx.parse.FullToken.Token.Type) {
1297 case TGSI_TOKEN_TYPE_IMMEDIATE:
1298 immediate = &ctx.parse.FullToken.FullImmediate;
1299 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1300 if(ctx.literals == NULL) {
1301 r = -ENOMEM;
1302 goto out_err;
1303 }
1304 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1305 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1306 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1307 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1308 ctx.nliterals++;
1309 break;
1310 case TGSI_TOKEN_TYPE_DECLARATION:
1311 r = tgsi_declaration(&ctx);
1312 if (r)
1313 goto out_err;
1314 break;
1315 case TGSI_TOKEN_TYPE_INSTRUCTION:
1316 break;
1317 case TGSI_TOKEN_TYPE_PROPERTY:
1318 property = &ctx.parse.FullToken.FullProperty;
1319 switch (property->Property.PropertyName) {
1320 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1321 if (property->u[0].Data == 1)
1322 shader->fs_write_all = TRUE;
1323 break;
1324 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1325 /* we don't need this one */
1326 break;
1327 }
1328 break;
1329 default:
1330 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1331 r = -EINVAL;
1332 goto out_err;
1333 }
1334 }
1335
1336 /* Process two side if needed */
1337 if (shader->two_side && ctx.colors_used) {
1338 int i, count = ctx.shader->ninput;
1339 unsigned next_lds_loc = ctx.shader->nlds;
1340
1341 /* additional inputs will be allocated right after the existing inputs,
1342 * we won't need them after the color selection, so we don't need to
1343 * reserve these gprs for the rest of the shader code and to adjust
1344 * output offsets etc. */
1345 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1346 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1347
1348 if (ctx.face_gpr == -1) {
1349 i = ctx.shader->ninput++;
1350 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1351 ctx.shader->input[i].spi_sid = 0;
1352 ctx.shader->input[i].gpr = gpr++;
1353 ctx.face_gpr = ctx.shader->input[i].gpr;
1354 }
1355
1356 for (i = 0; i < count; i++) {
1357 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1358 int ni = ctx.shader->ninput++;
1359 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1360 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1361 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1362 ctx.shader->input[ni].gpr = gpr++;
1363 // TGSI to LLVM needs to know the lds position of inputs.
1364 // Non LLVM path computes it later (in process_twoside_color)
1365 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1366 ctx.shader->input[i].potential_back_facing_reg = ni;
1367 }
1368 }
1369 }
1370
1371 /* LLVM backend setup */
1372 #ifdef R600_USE_LLVM
1373 if (use_llvm) {
1374 struct radeon_llvm_context radeon_llvm_ctx;
1375 LLVMModuleRef mod;
1376 unsigned dump = 0;
1377 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1378 radeon_llvm_ctx.reserved_reg_count = ctx.file_offset[TGSI_FILE_INPUT];
1379 radeon_llvm_ctx.type = ctx.type;
1380 radeon_llvm_ctx.two_side = shader->two_side;
1381 radeon_llvm_ctx.face_input = ctx.face_gpr;
1382 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1383 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1384 radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
1385 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1386 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1387 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1388 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
1389 dump = 1;
1390 }
1391 if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
1392 rscreen->family, dump)) {
1393 FREE(inst_bytes);
1394 radeon_llvm_dispose(&radeon_llvm_ctx);
1395 use_llvm = 0;
1396 fprintf(stderr, "R600 LLVM backend failed to compile "
1397 "shader. Falling back to TGSI\n");
1398 } else {
1399 ctx.file_offset[TGSI_FILE_OUTPUT] =
1400 ctx.file_offset[TGSI_FILE_INPUT];
1401 }
1402 radeon_llvm_dispose(&radeon_llvm_ctx);
1403 }
1404 #endif
1405 /* End of LLVM backend setup */
1406
1407 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1408 shader->nr_ps_max_color_exports = 8;
1409
1410 if (ctx.fragcoord_input >= 0 && !use_llvm) {
1411 if (ctx.bc->chip_class == CAYMAN) {
1412 for (j = 0 ; j < 4; j++) {
1413 struct r600_bytecode_alu alu;
1414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1415 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1416 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1417 alu.src[0].chan = 3;
1418
1419 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1420 alu.dst.chan = j;
1421 alu.dst.write = (j == 3);
1422 alu.last = 1;
1423 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1424 return r;
1425 }
1426 } else {
1427 struct r600_bytecode_alu alu;
1428 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1429 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1430 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1431 alu.src[0].chan = 3;
1432
1433 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1434 alu.dst.chan = 3;
1435 alu.dst.write = 1;
1436 alu.last = 1;
1437 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1438 return r;
1439 }
1440 }
1441
1442 if (shader->two_side && ctx.colors_used) {
1443 if ((r = process_twoside_color_inputs(&ctx)))
1444 return r;
1445 }
1446
1447 tgsi_parse_init(&ctx.parse, tokens);
1448 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1449 tgsi_parse_token(&ctx.parse);
1450 switch (ctx.parse.FullToken.Token.Type) {
1451 case TGSI_TOKEN_TYPE_INSTRUCTION:
1452 if (use_llvm) {
1453 continue;
1454 }
1455 r = tgsi_is_supported(&ctx);
1456 if (r)
1457 goto out_err;
1458 ctx.max_driver_temp_used = 0;
1459 /* reserve first tmp for everyone */
1460 r600_get_temp(&ctx);
1461
1462 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1463 if ((r = tgsi_split_constant(&ctx)))
1464 goto out_err;
1465 if ((r = tgsi_split_literal_constant(&ctx)))
1466 goto out_err;
1467 if (ctx.bc->chip_class == CAYMAN)
1468 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1469 else if (ctx.bc->chip_class >= EVERGREEN)
1470 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1471 else
1472 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1473 r = ctx.inst_info->process(&ctx);
1474 if (r)
1475 goto out_err;
1476 break;
1477 default:
1478 break;
1479 }
1480 }
1481
1482 /* Get instructions if we are using the LLVM backend. */
1483 if (use_llvm) {
1484 r600_bytecode_from_byte_stream(&ctx, inst_bytes, inst_byte_count);
1485 FREE(inst_bytes);
1486 }
1487
1488 noutput = shader->noutput;
1489
1490 if (ctx.clip_vertex_write) {
1491 /* need to convert a clipvertex write into clipdistance writes and not export
1492 the clip vertex anymore */
1493
1494 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1495 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1496 shader->output[noutput].gpr = ctx.temp_reg;
1497 noutput++;
1498 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1499 shader->output[noutput].gpr = ctx.temp_reg+1;
1500 noutput++;
1501
1502 /* reset spi_sid for clipvertex output to avoid confusing spi */
1503 shader->output[ctx.cv_output].spi_sid = 0;
1504
1505 shader->clip_dist_write = 0xFF;
1506
1507 for (i = 0; i < 8; i++) {
1508 int oreg = i >> 2;
1509 int ochan = i & 3;
1510
1511 for (j = 0; j < 4; j++) {
1512 struct r600_bytecode_alu alu;
1513 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1514 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4);
1515 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1516 alu.src[0].chan = j;
1517
1518 alu.src[1].sel = 512 + i;
1519 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1520 alu.src[1].chan = j;
1521
1522 alu.dst.sel = ctx.temp_reg + oreg;
1523 alu.dst.chan = j;
1524 alu.dst.write = (j == ochan);
1525 if (j == 3)
1526 alu.last = 1;
1527 r = r600_bytecode_add_alu(ctx.bc, &alu);
1528 if (r)
1529 return r;
1530 }
1531 }
1532 }
1533
1534 /* Add stream outputs. */
1535 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs) {
1536 for (i = 0; i < so.num_outputs; i++) {
1537 struct r600_bytecode_output output;
1538
1539 if (so.output[i].output_buffer >= 4) {
1540 R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1541 so.output[i].output_buffer);
1542 r = -EINVAL;
1543 goto out_err;
1544 }
1545 if (so.output[i].dst_offset < so.output[i].start_component) {
1546 R600_ERR("stream_output - dst_offset cannot be less than start_component\n");
1547 r = -EINVAL;
1548 goto out_err;
1549 }
1550
1551 memset(&output, 0, sizeof(struct r600_bytecode_output));
1552 output.gpr = shader->output[so.output[i].register_index].gpr;
1553 output.elem_size = 0;
1554 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1555 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1556 output.burst_count = 1;
1557 output.barrier = 1;
1558 /* array_size is an upper limit for the burst_count
1559 * with MEM_STREAM instructions */
1560 output.array_size = 0xFFF;
1561 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1562 if (ctx.bc->chip_class >= EVERGREEN) {
1563 switch (so.output[i].output_buffer) {
1564 case 0:
1565 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0;
1566 break;
1567 case 1:
1568 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1;
1569 break;
1570 case 2:
1571 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2;
1572 break;
1573 case 3:
1574 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3;
1575 break;
1576 }
1577 } else {
1578 switch (so.output[i].output_buffer) {
1579 case 0:
1580 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0;
1581 break;
1582 case 1:
1583 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1;
1584 break;
1585 case 2:
1586 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2;
1587 break;
1588 case 3:
1589 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3;
1590 break;
1591 }
1592 }
1593 r = r600_bytecode_add_output(ctx.bc, &output);
1594 if (r)
1595 goto out_err;
1596 }
1597 }
1598
1599 /* export output */
1600 for (i = 0, j = 0; i < noutput; i++, j++) {
1601 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1602 output[j].gpr = shader->output[i].gpr;
1603 output[j].elem_size = 3;
1604 output[j].swizzle_x = 0;
1605 output[j].swizzle_y = 1;
1606 output[j].swizzle_z = 2;
1607 output[j].swizzle_w = 3;
1608 output[j].burst_count = 1;
1609 output[j].barrier = 1;
1610 output[j].type = -1;
1611 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1612 switch (ctx.type) {
1613 case TGSI_PROCESSOR_VERTEX:
1614 switch (shader->output[i].name) {
1615 case TGSI_SEMANTIC_POSITION:
1616 output[j].array_base = next_pos_base++;
1617 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1618 break;
1619
1620 case TGSI_SEMANTIC_PSIZE:
1621 output[j].array_base = next_pos_base++;
1622 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1623 break;
1624 case TGSI_SEMANTIC_CLIPVERTEX:
1625 j--;
1626 break;
1627 case TGSI_SEMANTIC_CLIPDIST:
1628 output[j].array_base = next_pos_base++;
1629 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1630 /* spi_sid is 0 for clipdistance outputs that were generated
1631 * for clipvertex - we don't need to pass them to PS */
1632 if (shader->output[i].spi_sid) {
1633 j++;
1634 /* duplicate it as PARAM to pass to the pixel shader */
1635 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1636 output[j].array_base = next_param_base++;
1637 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1638 }
1639 break;
1640 case TGSI_SEMANTIC_FOG:
1641 output[j].swizzle_y = 4; /* 0 */
1642 output[j].swizzle_z = 4; /* 0 */
1643 output[j].swizzle_w = 5; /* 1 */
1644 break;
1645 }
1646 break;
1647 case TGSI_PROCESSOR_FRAGMENT:
1648 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1649 /* never export more colors than the number of CBs */
1650 if (next_pixel_base && next_pixel_base >= key.nr_cbufs) {
1651 /* skip export */
1652 j--;
1653 continue;
1654 }
1655 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1656 output[j].array_base = next_pixel_base++;
1657 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1658 shader->nr_ps_color_exports++;
1659 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1660 for (k = 1; k < key.nr_cbufs; k++) {
1661 j++;
1662 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1663 output[j].gpr = shader->output[i].gpr;
1664 output[j].elem_size = 3;
1665 output[j].swizzle_x = 0;
1666 output[j].swizzle_y = 1;
1667 output[j].swizzle_z = 2;
1668 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1669 output[j].burst_count = 1;
1670 output[j].barrier = 1;
1671 output[j].array_base = next_pixel_base++;
1672 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1673 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1674 shader->nr_ps_color_exports++;
1675 }
1676 }
1677 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1678 output[j].array_base = 61;
1679 output[j].swizzle_x = 2;
1680 output[j].swizzle_y = 7;
1681 output[j].swizzle_z = output[j].swizzle_w = 7;
1682 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1683 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1684 output[j].array_base = 61;
1685 output[j].swizzle_x = 7;
1686 output[j].swizzle_y = 1;
1687 output[j].swizzle_z = output[j].swizzle_w = 7;
1688 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1689 } else {
1690 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1691 r = -EINVAL;
1692 goto out_err;
1693 }
1694 break;
1695 default:
1696 R600_ERR("unsupported processor type %d\n", ctx.type);
1697 r = -EINVAL;
1698 goto out_err;
1699 }
1700
1701 if (output[j].type==-1) {
1702 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1703 output[j].array_base = next_param_base++;
1704 }
1705 }
1706
1707 /* add fake param output for vertex shader if no param is exported */
1708 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1709 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1710 output[j].gpr = 0;
1711 output[j].elem_size = 3;
1712 output[j].swizzle_x = 7;
1713 output[j].swizzle_y = 7;
1714 output[j].swizzle_z = 7;
1715 output[j].swizzle_w = 7;
1716 output[j].burst_count = 1;
1717 output[j].barrier = 1;
1718 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1719 output[j].array_base = 0;
1720 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1721 j++;
1722 }
1723
1724 /* add fake pixel export */
1725 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && next_pixel_base == 0) {
1726 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1727 output[j].gpr = 0;
1728 output[j].elem_size = 3;
1729 output[j].swizzle_x = 7;
1730 output[j].swizzle_y = 7;
1731 output[j].swizzle_z = 7;
1732 output[j].swizzle_w = 7;
1733 output[j].burst_count = 1;
1734 output[j].barrier = 1;
1735 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1736 output[j].array_base = 0;
1737 output[j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1738 j++;
1739 }
1740
1741 noutput = j;
1742
1743 /* set export done on last export of each type */
1744 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1745 if (ctx.bc->chip_class < CAYMAN) {
1746 if (i == (noutput - 1)) {
1747 output[i].end_of_program = 1;
1748 }
1749 }
1750 if (!(output_done & (1 << output[i].type))) {
1751 output_done |= (1 << output[i].type);
1752 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
1753 }
1754 }
1755 /* add output to bytecode */
1756 if (!use_llvm || ctx.type != TGSI_PROCESSOR_FRAGMENT) {
1757 for (i = 0; i < noutput; i++) {
1758 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1759 if (r)
1760 goto out_err;
1761 }
1762 }
1763 /* add program end */
1764 if (ctx.bc->chip_class == CAYMAN)
1765 cm_bytecode_add_cf_end(ctx.bc);
1766
1767 /* check GPR limit - we have 124 = 128 - 4
1768 * (4 are reserved as alu clause temporary registers) */
1769 if (ctx.bc->ngpr > 124) {
1770 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1771 r = -ENOMEM;
1772 goto out_err;
1773 }
1774
1775 free(ctx.literals);
1776 tgsi_parse_free(&ctx.parse);
1777 return 0;
1778 out_err:
1779 free(ctx.literals);
1780 tgsi_parse_free(&ctx.parse);
1781 return r;
1782 }
1783
1784 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1785 {
1786 R600_ERR("%s tgsi opcode unsupported\n",
1787 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1788 return -EINVAL;
1789 }
1790
1791 static int tgsi_end(struct r600_shader_ctx *ctx)
1792 {
1793 return 0;
1794 }
1795
1796 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1797 const struct r600_shader_src *shader_src,
1798 unsigned chan)
1799 {
1800 bc_src->sel = shader_src->sel;
1801 bc_src->chan = shader_src->swizzle[chan];
1802 bc_src->neg = shader_src->neg;
1803 bc_src->abs = shader_src->abs;
1804 bc_src->rel = shader_src->rel;
1805 bc_src->value = shader_src->value[bc_src->chan];
1806 }
1807
1808 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1809 {
1810 bc_src->abs = 1;
1811 bc_src->neg = 0;
1812 }
1813
1814 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1815 {
1816 bc_src->neg = !bc_src->neg;
1817 }
1818
1819 static void tgsi_dst(struct r600_shader_ctx *ctx,
1820 const struct tgsi_full_dst_register *tgsi_dst,
1821 unsigned swizzle,
1822 struct r600_bytecode_alu_dst *r600_dst)
1823 {
1824 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1825
1826 r600_dst->sel = tgsi_dst->Register.Index;
1827 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1828 r600_dst->chan = swizzle;
1829 r600_dst->write = 1;
1830 if (tgsi_dst->Register.Indirect)
1831 r600_dst->rel = V_SQ_REL_RELATIVE;
1832 if (inst->Instruction.Saturate) {
1833 r600_dst->clamp = 1;
1834 }
1835 }
1836
1837 static int tgsi_last_instruction(unsigned writemask)
1838 {
1839 int i, lasti = 0;
1840
1841 for (i = 0; i < 4; i++) {
1842 if (writemask & (1 << i)) {
1843 lasti = i;
1844 }
1845 }
1846 return lasti;
1847 }
1848
1849 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1850 {
1851 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1852 struct r600_bytecode_alu alu;
1853 int i, j, r;
1854 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1855
1856 for (i = 0; i < lasti + 1; i++) {
1857 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1858 continue;
1859
1860 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1861 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1862
1863 alu.inst = ctx->inst_info->r600_opcode;
1864 if (!swap) {
1865 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1866 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1867 }
1868 } else {
1869 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1870 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1871 }
1872 /* handle some special cases */
1873 switch (ctx->inst_info->tgsi_opcode) {
1874 case TGSI_OPCODE_SUB:
1875 r600_bytecode_src_toggle_neg(&alu.src[1]);
1876 break;
1877 case TGSI_OPCODE_ABS:
1878 r600_bytecode_src_set_abs(&alu.src[0]);
1879 break;
1880 default:
1881 break;
1882 }
1883 if (i == lasti || trans_only) {
1884 alu.last = 1;
1885 }
1886 r = r600_bytecode_add_alu(ctx->bc, &alu);
1887 if (r)
1888 return r;
1889 }
1890 return 0;
1891 }
1892
1893 static int tgsi_op2(struct r600_shader_ctx *ctx)
1894 {
1895 return tgsi_op2_s(ctx, 0, 0);
1896 }
1897
1898 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1899 {
1900 return tgsi_op2_s(ctx, 1, 0);
1901 }
1902
1903 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1904 {
1905 return tgsi_op2_s(ctx, 0, 1);
1906 }
1907
1908 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1909 {
1910 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1911 struct r600_bytecode_alu alu;
1912 int i, r;
1913 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1914
1915 for (i = 0; i < lasti + 1; i++) {
1916
1917 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1918 continue;
1919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1920 alu.inst = ctx->inst_info->r600_opcode;
1921
1922 alu.src[0].sel = V_SQ_ALU_SRC_0;
1923
1924 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1925
1926 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1927
1928 if (i == lasti) {
1929 alu.last = 1;
1930 }
1931 r = r600_bytecode_add_alu(ctx->bc, &alu);
1932 if (r)
1933 return r;
1934 }
1935 return 0;
1936
1937 }
1938
1939 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1940 {
1941 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1942 int i, j, r;
1943 struct r600_bytecode_alu alu;
1944 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1945
1946 for (i = 0 ; i < last_slot; i++) {
1947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1948 alu.inst = ctx->inst_info->r600_opcode;
1949 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1950 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1951
1952 /* RSQ should take the absolute value of src */
1953 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
1954 r600_bytecode_src_set_abs(&alu.src[j]);
1955 }
1956 }
1957 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1958 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1959
1960 if (i == last_slot - 1)
1961 alu.last = 1;
1962 r = r600_bytecode_add_alu(ctx->bc, &alu);
1963 if (r)
1964 return r;
1965 }
1966 return 0;
1967 }
1968
1969 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1970 {
1971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1972 int i, j, k, r;
1973 struct r600_bytecode_alu alu;
1974 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1975 for (k = 0; k < last_slot; k++) {
1976 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1977 continue;
1978
1979 for (i = 0 ; i < 4; i++) {
1980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1981 alu.inst = ctx->inst_info->r600_opcode;
1982 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1983 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1984 }
1985 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1986 alu.dst.write = (i == k);
1987 if (i == 3)
1988 alu.last = 1;
1989 r = r600_bytecode_add_alu(ctx->bc, &alu);
1990 if (r)
1991 return r;
1992 }
1993 }
1994 return 0;
1995 }
1996
1997 /*
1998 * r600 - trunc to -PI..PI range
1999 * r700 - normalize by dividing by 2PI
2000 * see fdo bug 27901
2001 */
2002 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2003 {
2004 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2005 static float double_pi = 3.1415926535 * 2;
2006 static float neg_pi = -3.1415926535;
2007
2008 int r;
2009 struct r600_bytecode_alu alu;
2010
2011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2012 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2013 alu.is_op3 = 1;
2014
2015 alu.dst.chan = 0;
2016 alu.dst.sel = ctx->temp_reg;
2017 alu.dst.write = 1;
2018
2019 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2020
2021 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2022 alu.src[1].chan = 0;
2023 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2024 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2025 alu.src[2].chan = 0;
2026 alu.last = 1;
2027 r = r600_bytecode_add_alu(ctx->bc, &alu);
2028 if (r)
2029 return r;
2030
2031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2032 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2033
2034 alu.dst.chan = 0;
2035 alu.dst.sel = ctx->temp_reg;
2036 alu.dst.write = 1;
2037
2038 alu.src[0].sel = ctx->temp_reg;
2039 alu.src[0].chan = 0;
2040 alu.last = 1;
2041 r = r600_bytecode_add_alu(ctx->bc, &alu);
2042 if (r)
2043 return r;
2044
2045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2046 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2047 alu.is_op3 = 1;
2048
2049 alu.dst.chan = 0;
2050 alu.dst.sel = ctx->temp_reg;
2051 alu.dst.write = 1;
2052
2053 alu.src[0].sel = ctx->temp_reg;
2054 alu.src[0].chan = 0;
2055
2056 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2057 alu.src[1].chan = 0;
2058 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2059 alu.src[2].chan = 0;
2060
2061 if (ctx->bc->chip_class == R600) {
2062 alu.src[1].value = *(uint32_t *)&double_pi;
2063 alu.src[2].value = *(uint32_t *)&neg_pi;
2064 } else {
2065 alu.src[1].sel = V_SQ_ALU_SRC_1;
2066 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2067 alu.src[2].neg = 1;
2068 }
2069
2070 alu.last = 1;
2071 r = r600_bytecode_add_alu(ctx->bc, &alu);
2072 if (r)
2073 return r;
2074 return 0;
2075 }
2076
2077 static int cayman_trig(struct r600_shader_ctx *ctx)
2078 {
2079 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2080 struct r600_bytecode_alu alu;
2081 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2082 int i, r;
2083
2084 r = tgsi_setup_trig(ctx);
2085 if (r)
2086 return r;
2087
2088
2089 for (i = 0; i < last_slot; i++) {
2090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2091 alu.inst = ctx->inst_info->r600_opcode;
2092 alu.dst.chan = i;
2093
2094 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2095 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2096
2097 alu.src[0].sel = ctx->temp_reg;
2098 alu.src[0].chan = 0;
2099 if (i == last_slot - 1)
2100 alu.last = 1;
2101 r = r600_bytecode_add_alu(ctx->bc, &alu);
2102 if (r)
2103 return r;
2104 }
2105 return 0;
2106 }
2107
2108 static int tgsi_trig(struct r600_shader_ctx *ctx)
2109 {
2110 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2111 struct r600_bytecode_alu alu;
2112 int i, r;
2113 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2114
2115 r = tgsi_setup_trig(ctx);
2116 if (r)
2117 return r;
2118
2119 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2120 alu.inst = ctx->inst_info->r600_opcode;
2121 alu.dst.chan = 0;
2122 alu.dst.sel = ctx->temp_reg;
2123 alu.dst.write = 1;
2124
2125 alu.src[0].sel = ctx->temp_reg;
2126 alu.src[0].chan = 0;
2127 alu.last = 1;
2128 r = r600_bytecode_add_alu(ctx->bc, &alu);
2129 if (r)
2130 return r;
2131
2132 /* replicate result */
2133 for (i = 0; i < lasti + 1; i++) {
2134 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2135 continue;
2136
2137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2138 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2139
2140 alu.src[0].sel = ctx->temp_reg;
2141 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2142 if (i == lasti)
2143 alu.last = 1;
2144 r = r600_bytecode_add_alu(ctx->bc, &alu);
2145 if (r)
2146 return r;
2147 }
2148 return 0;
2149 }
2150
2151 static int tgsi_scs(struct r600_shader_ctx *ctx)
2152 {
2153 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2154 struct r600_bytecode_alu alu;
2155 int i, r;
2156
2157 /* We'll only need the trig stuff if we are going to write to the
2158 * X or Y components of the destination vector.
2159 */
2160 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2161 r = tgsi_setup_trig(ctx);
2162 if (r)
2163 return r;
2164 }
2165
2166 /* dst.x = COS */
2167 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2168 if (ctx->bc->chip_class == CAYMAN) {
2169 for (i = 0 ; i < 3; i++) {
2170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2171 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
2172 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2173
2174 if (i == 0)
2175 alu.dst.write = 1;
2176 else
2177 alu.dst.write = 0;
2178 alu.src[0].sel = ctx->temp_reg;
2179 alu.src[0].chan = 0;
2180 if (i == 2)
2181 alu.last = 1;
2182 r = r600_bytecode_add_alu(ctx->bc, &alu);
2183 if (r)
2184 return r;
2185 }
2186 } else {
2187 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2188 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
2189 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2190
2191 alu.src[0].sel = ctx->temp_reg;
2192 alu.src[0].chan = 0;
2193 alu.last = 1;
2194 r = r600_bytecode_add_alu(ctx->bc, &alu);
2195 if (r)
2196 return r;
2197 }
2198 }
2199
2200 /* dst.y = SIN */
2201 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2202 if (ctx->bc->chip_class == CAYMAN) {
2203 for (i = 0 ; i < 3; i++) {
2204 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2205 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
2206 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2207 if (i == 1)
2208 alu.dst.write = 1;
2209 else
2210 alu.dst.write = 0;
2211 alu.src[0].sel = ctx->temp_reg;
2212 alu.src[0].chan = 0;
2213 if (i == 2)
2214 alu.last = 1;
2215 r = r600_bytecode_add_alu(ctx->bc, &alu);
2216 if (r)
2217 return r;
2218 }
2219 } else {
2220 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2221 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
2222 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2223
2224 alu.src[0].sel = ctx->temp_reg;
2225 alu.src[0].chan = 0;
2226 alu.last = 1;
2227 r = r600_bytecode_add_alu(ctx->bc, &alu);
2228 if (r)
2229 return r;
2230 }
2231 }
2232
2233 /* dst.z = 0.0; */
2234 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2235 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2236
2237 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2238
2239 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2240
2241 alu.src[0].sel = V_SQ_ALU_SRC_0;
2242 alu.src[0].chan = 0;
2243
2244 alu.last = 1;
2245
2246 r = r600_bytecode_add_alu(ctx->bc, &alu);
2247 if (r)
2248 return r;
2249 }
2250
2251 /* dst.w = 1.0; */
2252 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2254
2255 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2256
2257 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2258
2259 alu.src[0].sel = V_SQ_ALU_SRC_1;
2260 alu.src[0].chan = 0;
2261
2262 alu.last = 1;
2263
2264 r = r600_bytecode_add_alu(ctx->bc, &alu);
2265 if (r)
2266 return r;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static int tgsi_kill(struct r600_shader_ctx *ctx)
2273 {
2274 struct r600_bytecode_alu alu;
2275 int i, r;
2276
2277 for (i = 0; i < 4; i++) {
2278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2279 alu.inst = ctx->inst_info->r600_opcode;
2280
2281 alu.dst.chan = i;
2282
2283 alu.src[0].sel = V_SQ_ALU_SRC_0;
2284
2285 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
2286 alu.src[1].sel = V_SQ_ALU_SRC_1;
2287 alu.src[1].neg = 1;
2288 } else {
2289 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2290 }
2291 if (i == 3) {
2292 alu.last = 1;
2293 }
2294 r = r600_bytecode_add_alu(ctx->bc, &alu);
2295 if (r)
2296 return r;
2297 }
2298
2299 /* kill must be last in ALU */
2300 ctx->bc->force_add_cf = 1;
2301 ctx->shader->uses_kill = TRUE;
2302 return 0;
2303 }
2304
2305 static int tgsi_lit(struct r600_shader_ctx *ctx)
2306 {
2307 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2308 struct r600_bytecode_alu alu;
2309 int r;
2310
2311 /* tmp.x = max(src.y, 0.0) */
2312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2313 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
2314 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2315 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2316 alu.src[1].chan = 1;
2317
2318 alu.dst.sel = ctx->temp_reg;
2319 alu.dst.chan = 0;
2320 alu.dst.write = 1;
2321
2322 alu.last = 1;
2323 r = r600_bytecode_add_alu(ctx->bc, &alu);
2324 if (r)
2325 return r;
2326
2327 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2328 {
2329 int chan;
2330 int sel;
2331 int i;
2332
2333 if (ctx->bc->chip_class == CAYMAN) {
2334 for (i = 0; i < 3; i++) {
2335 /* tmp.z = log(tmp.x) */
2336 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2337 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
2338 alu.src[0].sel = ctx->temp_reg;
2339 alu.src[0].chan = 0;
2340 alu.dst.sel = ctx->temp_reg;
2341 alu.dst.chan = i;
2342 if (i == 2) {
2343 alu.dst.write = 1;
2344 alu.last = 1;
2345 } else
2346 alu.dst.write = 0;
2347
2348 r = r600_bytecode_add_alu(ctx->bc, &alu);
2349 if (r)
2350 return r;
2351 }
2352 } else {
2353 /* tmp.z = log(tmp.x) */
2354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2355 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
2356 alu.src[0].sel = ctx->temp_reg;
2357 alu.src[0].chan = 0;
2358 alu.dst.sel = ctx->temp_reg;
2359 alu.dst.chan = 2;
2360 alu.dst.write = 1;
2361 alu.last = 1;
2362 r = r600_bytecode_add_alu(ctx->bc, &alu);
2363 if (r)
2364 return r;
2365 }
2366
2367 chan = alu.dst.chan;
2368 sel = alu.dst.sel;
2369
2370 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2371 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2372 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
2373 alu.src[0].sel = sel;
2374 alu.src[0].chan = chan;
2375 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2376 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2377 alu.dst.sel = ctx->temp_reg;
2378 alu.dst.chan = 0;
2379 alu.dst.write = 1;
2380 alu.is_op3 = 1;
2381 alu.last = 1;
2382 r = r600_bytecode_add_alu(ctx->bc, &alu);
2383 if (r)
2384 return r;
2385
2386 if (ctx->bc->chip_class == CAYMAN) {
2387 for (i = 0; i < 3; i++) {
2388 /* dst.z = exp(tmp.x) */
2389 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2390 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2391 alu.src[0].sel = ctx->temp_reg;
2392 alu.src[0].chan = 0;
2393 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2394 if (i == 2) {
2395 alu.dst.write = 1;
2396 alu.last = 1;
2397 } else
2398 alu.dst.write = 0;
2399 r = r600_bytecode_add_alu(ctx->bc, &alu);
2400 if (r)
2401 return r;
2402 }
2403 } else {
2404 /* dst.z = exp(tmp.x) */
2405 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2406 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2407 alu.src[0].sel = ctx->temp_reg;
2408 alu.src[0].chan = 0;
2409 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2410 alu.last = 1;
2411 r = r600_bytecode_add_alu(ctx->bc, &alu);
2412 if (r)
2413 return r;
2414 }
2415 }
2416
2417 /* dst.x, <- 1.0 */
2418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2419 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2420 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2421 alu.src[0].chan = 0;
2422 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2423 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2424 r = r600_bytecode_add_alu(ctx->bc, &alu);
2425 if (r)
2426 return r;
2427
2428 /* dst.y = max(src.x, 0.0) */
2429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2430 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
2431 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2432 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2433 alu.src[1].chan = 0;
2434 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2435 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2436 r = r600_bytecode_add_alu(ctx->bc, &alu);
2437 if (r)
2438 return r;
2439
2440 /* dst.w, <- 1.0 */
2441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2442 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2443 alu.src[0].sel = V_SQ_ALU_SRC_1;
2444 alu.src[0].chan = 0;
2445 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2446 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2447 alu.last = 1;
2448 r = r600_bytecode_add_alu(ctx->bc, &alu);
2449 if (r)
2450 return r;
2451
2452 return 0;
2453 }
2454
2455 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2456 {
2457 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2458 struct r600_bytecode_alu alu;
2459 int i, r;
2460
2461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2462
2463 /* XXX:
2464 * For state trackers other than OpenGL, we'll want to use
2465 * _RECIPSQRT_IEEE instead.
2466 */
2467 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
2468
2469 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2470 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2471 r600_bytecode_src_set_abs(&alu.src[i]);
2472 }
2473 alu.dst.sel = ctx->temp_reg;
2474 alu.dst.write = 1;
2475 alu.last = 1;
2476 r = r600_bytecode_add_alu(ctx->bc, &alu);
2477 if (r)
2478 return r;
2479 /* replicate result */
2480 return tgsi_helper_tempx_replicate(ctx);
2481 }
2482
2483 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2484 {
2485 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2486 struct r600_bytecode_alu alu;
2487 int i, r;
2488
2489 for (i = 0; i < 4; i++) {
2490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2491 alu.src[0].sel = ctx->temp_reg;
2492 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2493 alu.dst.chan = i;
2494 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2495 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2496 if (i == 3)
2497 alu.last = 1;
2498 r = r600_bytecode_add_alu(ctx->bc, &alu);
2499 if (r)
2500 return r;
2501 }
2502 return 0;
2503 }
2504
2505 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2506 {
2507 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2508 struct r600_bytecode_alu alu;
2509 int i, r;
2510
2511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2512 alu.inst = ctx->inst_info->r600_opcode;
2513 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2514 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2515 }
2516 alu.dst.sel = ctx->temp_reg;
2517 alu.dst.write = 1;
2518 alu.last = 1;
2519 r = r600_bytecode_add_alu(ctx->bc, &alu);
2520 if (r)
2521 return r;
2522 /* replicate result */
2523 return tgsi_helper_tempx_replicate(ctx);
2524 }
2525
2526 static int cayman_pow(struct r600_shader_ctx *ctx)
2527 {
2528 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2529 int i, r;
2530 struct r600_bytecode_alu alu;
2531 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2532
2533 for (i = 0; i < 3; i++) {
2534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2535 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2536 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2537 alu.dst.sel = ctx->temp_reg;
2538 alu.dst.chan = i;
2539 alu.dst.write = 1;
2540 if (i == 2)
2541 alu.last = 1;
2542 r = r600_bytecode_add_alu(ctx->bc, &alu);
2543 if (r)
2544 return r;
2545 }
2546
2547 /* b * LOG2(a) */
2548 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2549 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2550 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2551 alu.src[1].sel = ctx->temp_reg;
2552 alu.dst.sel = ctx->temp_reg;
2553 alu.dst.write = 1;
2554 alu.last = 1;
2555 r = r600_bytecode_add_alu(ctx->bc, &alu);
2556 if (r)
2557 return r;
2558
2559 for (i = 0; i < last_slot; i++) {
2560 /* POW(a,b) = EXP2(b * LOG2(a))*/
2561 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2562 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2563 alu.src[0].sel = ctx->temp_reg;
2564
2565 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2566 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2567 if (i == last_slot - 1)
2568 alu.last = 1;
2569 r = r600_bytecode_add_alu(ctx->bc, &alu);
2570 if (r)
2571 return r;
2572 }
2573 return 0;
2574 }
2575
2576 static int tgsi_pow(struct r600_shader_ctx *ctx)
2577 {
2578 struct r600_bytecode_alu alu;
2579 int r;
2580
2581 /* LOG2(a) */
2582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2583 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2584 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2585 alu.dst.sel = ctx->temp_reg;
2586 alu.dst.write = 1;
2587 alu.last = 1;
2588 r = r600_bytecode_add_alu(ctx->bc, &alu);
2589 if (r)
2590 return r;
2591 /* b * LOG2(a) */
2592 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2593 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2594 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2595 alu.src[1].sel = ctx->temp_reg;
2596 alu.dst.sel = ctx->temp_reg;
2597 alu.dst.write = 1;
2598 alu.last = 1;
2599 r = r600_bytecode_add_alu(ctx->bc, &alu);
2600 if (r)
2601 return r;
2602 /* POW(a,b) = EXP2(b * LOG2(a))*/
2603 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2604 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2605 alu.src[0].sel = ctx->temp_reg;
2606 alu.dst.sel = ctx->temp_reg;
2607 alu.dst.write = 1;
2608 alu.last = 1;
2609 r = r600_bytecode_add_alu(ctx->bc, &alu);
2610 if (r)
2611 return r;
2612 return tgsi_helper_tempx_replicate(ctx);
2613 }
2614
2615 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2616 {
2617 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2618 struct r600_bytecode_alu alu;
2619 int i, r, j;
2620 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2621 int tmp0 = ctx->temp_reg;
2622 int tmp1 = r600_get_temp(ctx);
2623 int tmp2 = r600_get_temp(ctx);
2624 int tmp3 = r600_get_temp(ctx);
2625 /* Unsigned path:
2626 *
2627 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2628 *
2629 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2630 * 2. tmp0.z = lo (tmp0.x * src2)
2631 * 3. tmp0.w = -tmp0.z
2632 * 4. tmp0.y = hi (tmp0.x * src2)
2633 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2634 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2635 * 7. tmp1.x = tmp0.x - tmp0.w
2636 * 8. tmp1.y = tmp0.x + tmp0.w
2637 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2638 * 10. tmp0.z = hi(tmp0.x * src1) = q
2639 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2640 *
2641 * 12. tmp0.w = src1 - tmp0.y = r
2642 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2643 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2644 *
2645 * if DIV
2646 *
2647 * 15. tmp1.z = tmp0.z + 1 = q + 1
2648 * 16. tmp1.w = tmp0.z - 1 = q - 1
2649 *
2650 * else MOD
2651 *
2652 * 15. tmp1.z = tmp0.w - src2 = r - src2
2653 * 16. tmp1.w = tmp0.w + src2 = r + src2
2654 *
2655 * endif
2656 *
2657 * 17. tmp1.x = tmp1.x & tmp1.y
2658 *
2659 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2660 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2661 *
2662 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2663 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2664 *
2665 * Signed path:
2666 *
2667 * Same as unsigned, using abs values of the operands,
2668 * and fixing the sign of the result in the end.
2669 */
2670
2671 for (i = 0; i < 4; i++) {
2672 if (!(write_mask & (1<<i)))
2673 continue;
2674
2675 if (signed_op) {
2676
2677 /* tmp2.x = -src0 */
2678 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2679 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2680
2681 alu.dst.sel = tmp2;
2682 alu.dst.chan = 0;
2683 alu.dst.write = 1;
2684
2685 alu.src[0].sel = V_SQ_ALU_SRC_0;
2686
2687 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2688
2689 alu.last = 1;
2690 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2691 return r;
2692
2693 /* tmp2.y = -src1 */
2694 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2695 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2696
2697 alu.dst.sel = tmp2;
2698 alu.dst.chan = 1;
2699 alu.dst.write = 1;
2700
2701 alu.src[0].sel = V_SQ_ALU_SRC_0;
2702
2703 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2704
2705 alu.last = 1;
2706 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2707 return r;
2708
2709 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2710 /* it will be a sign of the quotient */
2711 if (!mod) {
2712
2713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2714 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT);
2715
2716 alu.dst.sel = tmp2;
2717 alu.dst.chan = 2;
2718 alu.dst.write = 1;
2719
2720 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2721 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2722
2723 alu.last = 1;
2724 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2725 return r;
2726 }
2727
2728 /* tmp2.x = |src0| */
2729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2730 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2731 alu.is_op3 = 1;
2732
2733 alu.dst.sel = tmp2;
2734 alu.dst.chan = 0;
2735 alu.dst.write = 1;
2736
2737 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2738 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2739 alu.src[2].sel = tmp2;
2740 alu.src[2].chan = 0;
2741
2742 alu.last = 1;
2743 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2744 return r;
2745
2746 /* tmp2.y = |src1| */
2747 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2748 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2749 alu.is_op3 = 1;
2750
2751 alu.dst.sel = tmp2;
2752 alu.dst.chan = 1;
2753 alu.dst.write = 1;
2754
2755 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2756 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2757 alu.src[2].sel = tmp2;
2758 alu.src[2].chan = 1;
2759
2760 alu.last = 1;
2761 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2762 return r;
2763
2764 }
2765
2766 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2767 if (ctx->bc->chip_class == CAYMAN) {
2768 /* tmp3.x = u2f(src2) */
2769 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2770 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
2771
2772 alu.dst.sel = tmp3;
2773 alu.dst.chan = 0;
2774 alu.dst.write = 1;
2775
2776 if (signed_op) {
2777 alu.src[0].sel = tmp2;
2778 alu.src[0].chan = 1;
2779 } else {
2780 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2781 }
2782
2783 alu.last = 1;
2784 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2785 return r;
2786
2787 /* tmp0.x = recip(tmp3.x) */
2788 for (j = 0 ; j < 3; j++) {
2789 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2790 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
2791
2792 alu.dst.sel = tmp0;
2793 alu.dst.chan = j;
2794 alu.dst.write = (j == 0);
2795
2796 alu.src[0].sel = tmp3;
2797 alu.src[0].chan = 0;
2798
2799 if (j == 2)
2800 alu.last = 1;
2801 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2802 return r;
2803 }
2804
2805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2806 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2807
2808 alu.src[0].sel = tmp0;
2809 alu.src[0].chan = 0;
2810
2811 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2812 alu.src[1].value = 0x4f800000;
2813
2814 alu.dst.sel = tmp3;
2815 alu.dst.write = 1;
2816 alu.last = 1;
2817 r = r600_bytecode_add_alu(ctx->bc, &alu);
2818 if (r)
2819 return r;
2820
2821 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2822 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
2823
2824 alu.dst.sel = tmp0;
2825 alu.dst.chan = 0;
2826 alu.dst.write = 1;
2827
2828 alu.src[0].sel = tmp3;
2829 alu.src[0].chan = 0;
2830
2831 alu.last = 1;
2832 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2833 return r;
2834
2835 } else {
2836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2837 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT);
2838
2839 alu.dst.sel = tmp0;
2840 alu.dst.chan = 0;
2841 alu.dst.write = 1;
2842
2843 if (signed_op) {
2844 alu.src[0].sel = tmp2;
2845 alu.src[0].chan = 1;
2846 } else {
2847 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2848 }
2849
2850 alu.last = 1;
2851 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2852 return r;
2853 }
2854
2855 /* 2. tmp0.z = lo (tmp0.x * src2) */
2856 if (ctx->bc->chip_class == CAYMAN) {
2857 for (j = 0 ; j < 4; j++) {
2858 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2859 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
2860
2861 alu.dst.sel = tmp0;
2862 alu.dst.chan = j;
2863 alu.dst.write = (j == 2);
2864
2865 alu.src[0].sel = tmp0;
2866 alu.src[0].chan = 0;
2867 if (signed_op) {
2868 alu.src[1].sel = tmp2;
2869 alu.src[1].chan = 1;
2870 } else {
2871 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2872 }
2873
2874 alu.last = (j == 3);
2875 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2876 return r;
2877 }
2878 } else {
2879 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2880 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
2881
2882 alu.dst.sel = tmp0;
2883 alu.dst.chan = 2;
2884 alu.dst.write = 1;
2885
2886 alu.src[0].sel = tmp0;
2887 alu.src[0].chan = 0;
2888 if (signed_op) {
2889 alu.src[1].sel = tmp2;
2890 alu.src[1].chan = 1;
2891 } else {
2892 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2893 }
2894
2895 alu.last = 1;
2896 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2897 return r;
2898 }
2899
2900 /* 3. tmp0.w = -tmp0.z */
2901 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2902 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2903
2904 alu.dst.sel = tmp0;
2905 alu.dst.chan = 3;
2906 alu.dst.write = 1;
2907
2908 alu.src[0].sel = V_SQ_ALU_SRC_0;
2909 alu.src[1].sel = tmp0;
2910 alu.src[1].chan = 2;
2911
2912 alu.last = 1;
2913 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2914 return r;
2915
2916 /* 4. tmp0.y = hi (tmp0.x * src2) */
2917 if (ctx->bc->chip_class == CAYMAN) {
2918 for (j = 0 ; j < 4; j++) {
2919 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2920 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2921
2922 alu.dst.sel = tmp0;
2923 alu.dst.chan = j;
2924 alu.dst.write = (j == 1);
2925
2926 alu.src[0].sel = tmp0;
2927 alu.src[0].chan = 0;
2928
2929 if (signed_op) {
2930 alu.src[1].sel = tmp2;
2931 alu.src[1].chan = 1;
2932 } else {
2933 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2934 }
2935 alu.last = (j == 3);
2936 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2937 return r;
2938 }
2939 } else {
2940 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2941 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2942
2943 alu.dst.sel = tmp0;
2944 alu.dst.chan = 1;
2945 alu.dst.write = 1;
2946
2947 alu.src[0].sel = tmp0;
2948 alu.src[0].chan = 0;
2949
2950 if (signed_op) {
2951 alu.src[1].sel = tmp2;
2952 alu.src[1].chan = 1;
2953 } else {
2954 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2955 }
2956
2957 alu.last = 1;
2958 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2959 return r;
2960 }
2961
2962 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2963 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2964 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
2965 alu.is_op3 = 1;
2966
2967 alu.dst.sel = tmp0;
2968 alu.dst.chan = 2;
2969 alu.dst.write = 1;
2970
2971 alu.src[0].sel = tmp0;
2972 alu.src[0].chan = 1;
2973 alu.src[1].sel = tmp0;
2974 alu.src[1].chan = 3;
2975 alu.src[2].sel = tmp0;
2976 alu.src[2].chan = 2;
2977
2978 alu.last = 1;
2979 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2980 return r;
2981
2982 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2983 if (ctx->bc->chip_class == CAYMAN) {
2984 for (j = 0 ; j < 4; j++) {
2985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2986 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
2987
2988 alu.dst.sel = tmp0;
2989 alu.dst.chan = j;
2990 alu.dst.write = (j == 3);
2991
2992 alu.src[0].sel = tmp0;
2993 alu.src[0].chan = 2;
2994
2995 alu.src[1].sel = tmp0;
2996 alu.src[1].chan = 0;
2997
2998 alu.last = (j == 3);
2999 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3000 return r;
3001 }
3002 } else {
3003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3004 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
3005
3006 alu.dst.sel = tmp0;
3007 alu.dst.chan = 3;
3008 alu.dst.write = 1;
3009
3010 alu.src[0].sel = tmp0;
3011 alu.src[0].chan = 2;
3012
3013 alu.src[1].sel = tmp0;
3014 alu.src[1].chan = 0;
3015
3016 alu.last = 1;
3017 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3018 return r;
3019 }
3020
3021 /* 7. tmp1.x = tmp0.x - tmp0.w */
3022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3023 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3024
3025 alu.dst.sel = tmp1;
3026 alu.dst.chan = 0;
3027 alu.dst.write = 1;
3028
3029 alu.src[0].sel = tmp0;
3030 alu.src[0].chan = 0;
3031 alu.src[1].sel = tmp0;
3032 alu.src[1].chan = 3;
3033
3034 alu.last = 1;
3035 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3036 return r;
3037
3038 /* 8. tmp1.y = tmp0.x + tmp0.w */
3039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3040 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3041
3042 alu.dst.sel = tmp1;
3043 alu.dst.chan = 1;
3044 alu.dst.write = 1;
3045
3046 alu.src[0].sel = tmp0;
3047 alu.src[0].chan = 0;
3048 alu.src[1].sel = tmp0;
3049 alu.src[1].chan = 3;
3050
3051 alu.last = 1;
3052 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3053 return r;
3054
3055 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3057 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
3058 alu.is_op3 = 1;
3059
3060 alu.dst.sel = tmp0;
3061 alu.dst.chan = 0;
3062 alu.dst.write = 1;
3063
3064 alu.src[0].sel = tmp0;
3065 alu.src[0].chan = 1;
3066 alu.src[1].sel = tmp1;
3067 alu.src[1].chan = 1;
3068 alu.src[2].sel = tmp1;
3069 alu.src[2].chan = 0;
3070
3071 alu.last = 1;
3072 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3073 return r;
3074
3075 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3076 if (ctx->bc->chip_class == CAYMAN) {
3077 for (j = 0 ; j < 4; j++) {
3078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3079 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
3080
3081 alu.dst.sel = tmp0;
3082 alu.dst.chan = j;
3083 alu.dst.write = (j == 2);
3084
3085 alu.src[0].sel = tmp0;
3086 alu.src[0].chan = 0;
3087
3088 if (signed_op) {
3089 alu.src[1].sel = tmp2;
3090 alu.src[1].chan = 0;
3091 } else {
3092 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3093 }
3094
3095 alu.last = (j == 3);
3096 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3097 return r;
3098 }
3099 } else {
3100 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3101 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT);
3102
3103 alu.dst.sel = tmp0;
3104 alu.dst.chan = 2;
3105 alu.dst.write = 1;
3106
3107 alu.src[0].sel = tmp0;
3108 alu.src[0].chan = 0;
3109
3110 if (signed_op) {
3111 alu.src[1].sel = tmp2;
3112 alu.src[1].chan = 0;
3113 } else {
3114 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3115 }
3116
3117 alu.last = 1;
3118 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3119 return r;
3120 }
3121
3122 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3123 if (ctx->bc->chip_class == CAYMAN) {
3124 for (j = 0 ; j < 4; j++) {
3125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3126 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
3127
3128 alu.dst.sel = tmp0;
3129 alu.dst.chan = j;
3130 alu.dst.write = (j == 1);
3131
3132 if (signed_op) {
3133 alu.src[0].sel = tmp2;
3134 alu.src[0].chan = 1;
3135 } else {
3136 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3137 }
3138
3139 alu.src[1].sel = tmp0;
3140 alu.src[1].chan = 2;
3141
3142 alu.last = (j == 3);
3143 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3144 return r;
3145 }
3146 } else {
3147 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3148 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
3149
3150 alu.dst.sel = tmp0;
3151 alu.dst.chan = 1;
3152 alu.dst.write = 1;
3153
3154 if (signed_op) {
3155 alu.src[0].sel = tmp2;
3156 alu.src[0].chan = 1;
3157 } else {
3158 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3159 }
3160
3161 alu.src[1].sel = tmp0;
3162 alu.src[1].chan = 2;
3163
3164 alu.last = 1;
3165 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3166 return r;
3167 }
3168
3169 /* 12. tmp0.w = src1 - tmp0.y = r */
3170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3171 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3172
3173 alu.dst.sel = tmp0;
3174 alu.dst.chan = 3;
3175 alu.dst.write = 1;
3176
3177 if (signed_op) {
3178 alu.src[0].sel = tmp2;
3179 alu.src[0].chan = 0;
3180 } else {
3181 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3182 }
3183
3184 alu.src[1].sel = tmp0;
3185 alu.src[1].chan = 1;
3186
3187 alu.last = 1;
3188 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3189 return r;
3190
3191 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3193 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
3194
3195 alu.dst.sel = tmp1;
3196 alu.dst.chan = 0;
3197 alu.dst.write = 1;
3198
3199 alu.src[0].sel = tmp0;
3200 alu.src[0].chan = 3;
3201 if (signed_op) {
3202 alu.src[1].sel = tmp2;
3203 alu.src[1].chan = 1;
3204 } else {
3205 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3206 }
3207
3208 alu.last = 1;
3209 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3210 return r;
3211
3212 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3214 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT);
3215
3216 alu.dst.sel = tmp1;
3217 alu.dst.chan = 1;
3218 alu.dst.write = 1;
3219
3220 if (signed_op) {
3221 alu.src[0].sel = tmp2;
3222 alu.src[0].chan = 0;
3223 } else {
3224 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3225 }
3226
3227 alu.src[1].sel = tmp0;
3228 alu.src[1].chan = 1;
3229
3230 alu.last = 1;
3231 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3232 return r;
3233
3234 if (mod) { /* UMOD */
3235
3236 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3238 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3239
3240 alu.dst.sel = tmp1;
3241 alu.dst.chan = 2;
3242 alu.dst.write = 1;
3243
3244 alu.src[0].sel = tmp0;
3245 alu.src[0].chan = 3;
3246
3247 if (signed_op) {
3248 alu.src[1].sel = tmp2;
3249 alu.src[1].chan = 1;
3250 } else {
3251 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3252 }
3253
3254 alu.last = 1;
3255 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3256 return r;
3257
3258 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3260 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3261
3262 alu.dst.sel = tmp1;
3263 alu.dst.chan = 3;
3264 alu.dst.write = 1;
3265
3266 alu.src[0].sel = tmp0;
3267 alu.src[0].chan = 3;
3268 if (signed_op) {
3269 alu.src[1].sel = tmp2;
3270 alu.src[1].chan = 1;
3271 } else {
3272 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3273 }
3274
3275 alu.last = 1;
3276 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3277 return r;
3278
3279 } else { /* UDIV */
3280
3281 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3283 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3284
3285 alu.dst.sel = tmp1;
3286 alu.dst.chan = 2;
3287 alu.dst.write = 1;
3288
3289 alu.src[0].sel = tmp0;
3290 alu.src[0].chan = 2;
3291 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3292
3293 alu.last = 1;
3294 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3295 return r;
3296
3297 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3298 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3299 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
3300
3301 alu.dst.sel = tmp1;
3302 alu.dst.chan = 3;
3303 alu.dst.write = 1;
3304
3305 alu.src[0].sel = tmp0;
3306 alu.src[0].chan = 2;
3307 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3308
3309 alu.last = 1;
3310 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3311 return r;
3312
3313 }
3314
3315 /* 17. tmp1.x = tmp1.x & tmp1.y */
3316 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3317 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
3318
3319 alu.dst.sel = tmp1;
3320 alu.dst.chan = 0;
3321 alu.dst.write = 1;
3322
3323 alu.src[0].sel = tmp1;
3324 alu.src[0].chan = 0;
3325 alu.src[1].sel = tmp1;
3326 alu.src[1].chan = 1;
3327
3328 alu.last = 1;
3329 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3330 return r;
3331
3332 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3333 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3334 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3335 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
3336 alu.is_op3 = 1;
3337
3338 alu.dst.sel = tmp0;
3339 alu.dst.chan = 2;
3340 alu.dst.write = 1;
3341
3342 alu.src[0].sel = tmp1;
3343 alu.src[0].chan = 0;
3344 alu.src[1].sel = tmp0;
3345 alu.src[1].chan = mod ? 3 : 2;
3346 alu.src[2].sel = tmp1;
3347 alu.src[2].chan = 2;
3348
3349 alu.last = 1;
3350 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3351 return r;
3352
3353 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3355 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDE_INT);
3356 alu.is_op3 = 1;
3357
3358 if (signed_op) {
3359 alu.dst.sel = tmp0;
3360 alu.dst.chan = 2;
3361 alu.dst.write = 1;
3362 } else {
3363 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3364 }
3365
3366 alu.src[0].sel = tmp1;
3367 alu.src[0].chan = 1;
3368 alu.src[1].sel = tmp1;
3369 alu.src[1].chan = 3;
3370 alu.src[2].sel = tmp0;
3371 alu.src[2].chan = 2;
3372
3373 alu.last = 1;
3374 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3375 return r;
3376
3377 if (signed_op) {
3378
3379 /* fix the sign of the result */
3380
3381 if (mod) {
3382
3383 /* tmp0.x = -tmp0.z */
3384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3385 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3386
3387 alu.dst.sel = tmp0;
3388 alu.dst.chan = 0;
3389 alu.dst.write = 1;
3390
3391 alu.src[0].sel = V_SQ_ALU_SRC_0;
3392 alu.src[1].sel = tmp0;
3393 alu.src[1].chan = 2;
3394
3395 alu.last = 1;
3396 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3397 return r;
3398
3399 /* sign of the remainder is the same as the sign of src0 */
3400 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3402 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3403 alu.is_op3 = 1;
3404
3405 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3406
3407 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3408 alu.src[1].sel = tmp0;
3409 alu.src[1].chan = 2;
3410 alu.src[2].sel = tmp0;
3411 alu.src[2].chan = 0;
3412
3413 alu.last = 1;
3414 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3415 return r;
3416
3417 } else {
3418
3419 /* tmp0.x = -tmp0.z */
3420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3421 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3422
3423 alu.dst.sel = tmp0;
3424 alu.dst.chan = 0;
3425 alu.dst.write = 1;
3426
3427 alu.src[0].sel = V_SQ_ALU_SRC_0;
3428 alu.src[1].sel = tmp0;
3429 alu.src[1].chan = 2;
3430
3431 alu.last = 1;
3432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3433 return r;
3434
3435 /* fix the quotient sign (same as the sign of src0*src1) */
3436 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3437 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3438 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3439 alu.is_op3 = 1;
3440
3441 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3442
3443 alu.src[0].sel = tmp2;
3444 alu.src[0].chan = 2;
3445 alu.src[1].sel = tmp0;
3446 alu.src[1].chan = 2;
3447 alu.src[2].sel = tmp0;
3448 alu.src[2].chan = 0;
3449
3450 alu.last = 1;
3451 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3452 return r;
3453 }
3454 }
3455 }
3456 return 0;
3457 }
3458
3459 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3460 {
3461 return tgsi_divmod(ctx, 0, 0);
3462 }
3463
3464 static int tgsi_umod(struct r600_shader_ctx *ctx)
3465 {
3466 return tgsi_divmod(ctx, 1, 0);
3467 }
3468
3469 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3470 {
3471 return tgsi_divmod(ctx, 0, 1);
3472 }
3473
3474 static int tgsi_imod(struct r600_shader_ctx *ctx)
3475 {
3476 return tgsi_divmod(ctx, 1, 1);
3477 }
3478
3479
3480 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3481 {
3482 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3483 struct r600_bytecode_alu alu;
3484 int i, r;
3485 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3486 int last_inst = tgsi_last_instruction(write_mask);
3487
3488 for (i = 0; i < 4; i++) {
3489 if (!(write_mask & (1<<i)))
3490 continue;
3491
3492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3493 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
3494
3495 alu.dst.sel = ctx->temp_reg;
3496 alu.dst.chan = i;
3497 alu.dst.write = 1;
3498
3499 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3500 if (i == last_inst)
3501 alu.last = 1;
3502 r = r600_bytecode_add_alu(ctx->bc, &alu);
3503 if (r)
3504 return r;
3505 }
3506
3507 for (i = 0; i < 4; i++) {
3508 if (!(write_mask & (1<<i)))
3509 continue;
3510
3511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3512 alu.inst = ctx->inst_info->r600_opcode;
3513
3514 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3515
3516 alu.src[0].sel = ctx->temp_reg;
3517 alu.src[0].chan = i;
3518
3519 if (i == last_inst || alu.inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT)
3520 alu.last = 1;
3521 r = r600_bytecode_add_alu(ctx->bc, &alu);
3522 if (r)
3523 return r;
3524 }
3525
3526 return 0;
3527 }
3528
3529 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3530 {
3531 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3532 struct r600_bytecode_alu alu;
3533 int i, r;
3534 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3535 int last_inst = tgsi_last_instruction(write_mask);
3536
3537 /* tmp = -src */
3538 for (i = 0; i < 4; i++) {
3539 if (!(write_mask & (1<<i)))
3540 continue;
3541
3542 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3543 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
3544
3545 alu.dst.sel = ctx->temp_reg;
3546 alu.dst.chan = i;
3547 alu.dst.write = 1;
3548
3549 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3550 alu.src[0].sel = V_SQ_ALU_SRC_0;
3551
3552 if (i == last_inst)
3553 alu.last = 1;
3554 r = r600_bytecode_add_alu(ctx->bc, &alu);
3555 if (r)
3556 return r;
3557 }
3558
3559 /* dst = (src >= 0 ? src : tmp) */
3560 for (i = 0; i < 4; i++) {
3561 if (!(write_mask & (1<<i)))
3562 continue;
3563
3564 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3565 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3566 alu.is_op3 = 1;
3567 alu.dst.write = 1;
3568
3569 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3570
3571 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3572 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3573 alu.src[2].sel = ctx->temp_reg;
3574 alu.src[2].chan = i;
3575
3576 if (i == last_inst)
3577 alu.last = 1;
3578 r = r600_bytecode_add_alu(ctx->bc, &alu);
3579 if (r)
3580 return r;
3581 }
3582 return 0;
3583 }
3584
3585 static int tgsi_issg(struct r600_shader_ctx *ctx)
3586 {
3587 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3588 struct r600_bytecode_alu alu;
3589 int i, r;
3590 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3591 int last_inst = tgsi_last_instruction(write_mask);
3592
3593 /* tmp = (src >= 0 ? src : -1) */
3594 for (i = 0; i < 4; i++) {
3595 if (!(write_mask & (1<<i)))
3596 continue;
3597
3598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3599 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
3600 alu.is_op3 = 1;
3601
3602 alu.dst.sel = ctx->temp_reg;
3603 alu.dst.chan = i;
3604 alu.dst.write = 1;
3605
3606 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3607 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3608 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3609
3610 if (i == last_inst)
3611 alu.last = 1;
3612 r = r600_bytecode_add_alu(ctx->bc, &alu);
3613 if (r)
3614 return r;
3615 }
3616
3617 /* dst = (tmp > 0 ? 1 : tmp) */
3618 for (i = 0; i < 4; i++) {
3619 if (!(write_mask & (1<<i)))
3620 continue;
3621
3622 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3623 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT);
3624 alu.is_op3 = 1;
3625 alu.dst.write = 1;
3626
3627 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3628
3629 alu.src[0].sel = ctx->temp_reg;
3630 alu.src[0].chan = i;
3631
3632 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3633
3634 alu.src[2].sel = ctx->temp_reg;
3635 alu.src[2].chan = i;
3636
3637 if (i == last_inst)
3638 alu.last = 1;
3639 r = r600_bytecode_add_alu(ctx->bc, &alu);
3640 if (r)
3641 return r;
3642 }
3643 return 0;
3644 }
3645
3646
3647
3648 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3649 {
3650 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3651 struct r600_bytecode_alu alu;
3652 int i, r;
3653
3654 /* tmp = (src > 0 ? 1 : src) */
3655 for (i = 0; i < 4; i++) {
3656 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3657 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
3658 alu.is_op3 = 1;
3659
3660 alu.dst.sel = ctx->temp_reg;
3661 alu.dst.chan = i;
3662
3663 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3664 alu.src[1].sel = V_SQ_ALU_SRC_1;
3665 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3666
3667 if (i == 3)
3668 alu.last = 1;
3669 r = r600_bytecode_add_alu(ctx->bc, &alu);
3670 if (r)
3671 return r;
3672 }
3673
3674 /* dst = (-tmp > 0 ? -1 : tmp) */
3675 for (i = 0; i < 4; i++) {
3676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3677 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
3678 alu.is_op3 = 1;
3679 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3680
3681 alu.src[0].sel = ctx->temp_reg;
3682 alu.src[0].chan = i;
3683 alu.src[0].neg = 1;
3684
3685 alu.src[1].sel = V_SQ_ALU_SRC_1;
3686 alu.src[1].neg = 1;
3687
3688 alu.src[2].sel = ctx->temp_reg;
3689 alu.src[2].chan = i;
3690
3691 if (i == 3)
3692 alu.last = 1;
3693 r = r600_bytecode_add_alu(ctx->bc, &alu);
3694 if (r)
3695 return r;
3696 }
3697 return 0;
3698 }
3699
3700 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3701 {
3702 struct r600_bytecode_alu alu;
3703 int i, r;
3704
3705 for (i = 0; i < 4; i++) {
3706 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3707 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3708 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
3709 alu.dst.chan = i;
3710 } else {
3711 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3712 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3713 alu.src[0].sel = ctx->temp_reg;
3714 alu.src[0].chan = i;
3715 }
3716 if (i == 3) {
3717 alu.last = 1;
3718 }
3719 r = r600_bytecode_add_alu(ctx->bc, &alu);
3720 if (r)
3721 return r;
3722 }
3723 return 0;
3724 }
3725
3726 static int tgsi_op3(struct r600_shader_ctx *ctx)
3727 {
3728 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3729 struct r600_bytecode_alu alu;
3730 int i, j, r;
3731 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3732
3733 for (i = 0; i < lasti + 1; i++) {
3734 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3735 continue;
3736
3737 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3738 alu.inst = ctx->inst_info->r600_opcode;
3739 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3740 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3741 }
3742
3743 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3744 alu.dst.chan = i;
3745 alu.dst.write = 1;
3746 alu.is_op3 = 1;
3747 if (i == lasti) {
3748 alu.last = 1;
3749 }
3750 r = r600_bytecode_add_alu(ctx->bc, &alu);
3751 if (r)
3752 return r;
3753 }
3754 return 0;
3755 }
3756
3757 static int tgsi_dp(struct r600_shader_ctx *ctx)
3758 {
3759 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3760 struct r600_bytecode_alu alu;
3761 int i, j, r;
3762
3763 for (i = 0; i < 4; i++) {
3764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3765 alu.inst = ctx->inst_info->r600_opcode;
3766 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3767 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3768 }
3769
3770 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3771 alu.dst.chan = i;
3772 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3773 /* handle some special cases */
3774 switch (ctx->inst_info->tgsi_opcode) {
3775 case TGSI_OPCODE_DP2:
3776 if (i > 1) {
3777 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3778 alu.src[0].chan = alu.src[1].chan = 0;
3779 }
3780 break;
3781 case TGSI_OPCODE_DP3:
3782 if (i > 2) {
3783 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3784 alu.src[0].chan = alu.src[1].chan = 0;
3785 }
3786 break;
3787 case TGSI_OPCODE_DPH:
3788 if (i == 3) {
3789 alu.src[0].sel = V_SQ_ALU_SRC_1;
3790 alu.src[0].chan = 0;
3791 alu.src[0].neg = 0;
3792 }
3793 break;
3794 default:
3795 break;
3796 }
3797 if (i == 3) {
3798 alu.last = 1;
3799 }
3800 r = r600_bytecode_add_alu(ctx->bc, &alu);
3801 if (r)
3802 return r;
3803 }
3804 return 0;
3805 }
3806
3807 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3808 unsigned index)
3809 {
3810 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3811 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3812 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3813 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3814 ctx->src[index].neg || ctx->src[index].abs;
3815 }
3816
3817 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3818 unsigned index)
3819 {
3820 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3821 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3822 }
3823
3824 static int tgsi_tex(struct r600_shader_ctx *ctx)
3825 {
3826 static float one_point_five = 1.5f;
3827 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3828 struct r600_bytecode_tex tex;
3829 struct r600_bytecode_alu alu;
3830 unsigned src_gpr;
3831 int r, i, j;
3832 int opcode;
3833 bool read_compressed_msaa = ctx->bc->msaa_texture_mode == MSAA_TEXTURE_COMPRESSED &&
3834 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
3835 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
3836 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
3837 /* Texture fetch instructions can only use gprs as source.
3838 * Also they cannot negate the source or take the absolute value */
3839 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3840 tgsi_tex_src_requires_loading(ctx, 0)) ||
3841 read_compressed_msaa;
3842 boolean src_loaded = FALSE;
3843 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3844 uint8_t offset_x = 0, offset_y = 0, offset_z = 0;
3845 boolean has_txq_cube_array_z = false;
3846
3847 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
3848 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3849 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
3850 if (inst->Dst[0].Register.WriteMask & 4) {
3851 ctx->shader->has_txq_cube_array_z_comp = true;
3852 has_txq_cube_array_z = true;
3853 }
3854
3855 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
3856 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
3857 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
3858 sampler_src_reg = 2;
3859
3860 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3861
3862 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3863 /* get offset values */
3864 if (inst->Texture.NumOffsets) {
3865 assert(inst->Texture.NumOffsets == 1);
3866
3867 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3868 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3869 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3870 }
3871 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3872 /* TGSI moves the sampler to src reg 3 for TXD */
3873 sampler_src_reg = 3;
3874
3875 for (i = 1; i < 3; i++) {
3876 /* set gradients h/v */
3877 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3878 tex.inst = (i == 1) ? SQ_TEX_INST_SET_GRADIENTS_H :
3879 SQ_TEX_INST_SET_GRADIENTS_V;
3880 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3881 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3882
3883 if (tgsi_tex_src_requires_loading(ctx, i)) {
3884 tex.src_gpr = r600_get_temp(ctx);
3885 tex.src_sel_x = 0;
3886 tex.src_sel_y = 1;
3887 tex.src_sel_z = 2;
3888 tex.src_sel_w = 3;
3889
3890 for (j = 0; j < 4; j++) {
3891 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3892 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3893 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3894 alu.dst.sel = tex.src_gpr;
3895 alu.dst.chan = j;
3896 if (j == 3)
3897 alu.last = 1;
3898 alu.dst.write = 1;
3899 r = r600_bytecode_add_alu(ctx->bc, &alu);
3900 if (r)
3901 return r;
3902 }
3903
3904 } else {
3905 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3906 tex.src_sel_x = ctx->src[i].swizzle[0];
3907 tex.src_sel_y = ctx->src[i].swizzle[1];
3908 tex.src_sel_z = ctx->src[i].swizzle[2];
3909 tex.src_sel_w = ctx->src[i].swizzle[3];
3910 tex.src_rel = ctx->src[i].rel;
3911 }
3912 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3913 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3914 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3915 tex.coord_type_x = 1;
3916 tex.coord_type_y = 1;
3917 tex.coord_type_z = 1;
3918 tex.coord_type_w = 1;
3919 }
3920 r = r600_bytecode_add_tex(ctx->bc, &tex);
3921 if (r)
3922 return r;
3923 }
3924 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3925 int out_chan;
3926 /* Add perspective divide */
3927 if (ctx->bc->chip_class == CAYMAN) {
3928 out_chan = 2;
3929 for (i = 0; i < 3; i++) {
3930 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3931 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3932 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3933
3934 alu.dst.sel = ctx->temp_reg;
3935 alu.dst.chan = i;
3936 if (i == 2)
3937 alu.last = 1;
3938 if (out_chan == i)
3939 alu.dst.write = 1;
3940 r = r600_bytecode_add_alu(ctx->bc, &alu);
3941 if (r)
3942 return r;
3943 }
3944
3945 } else {
3946 out_chan = 3;
3947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3948 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3949 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3950
3951 alu.dst.sel = ctx->temp_reg;
3952 alu.dst.chan = out_chan;
3953 alu.last = 1;
3954 alu.dst.write = 1;
3955 r = r600_bytecode_add_alu(ctx->bc, &alu);
3956 if (r)
3957 return r;
3958 }
3959
3960 for (i = 0; i < 3; i++) {
3961 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3962 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3963 alu.src[0].sel = ctx->temp_reg;
3964 alu.src[0].chan = out_chan;
3965 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3966 alu.dst.sel = ctx->temp_reg;
3967 alu.dst.chan = i;
3968 alu.dst.write = 1;
3969 r = r600_bytecode_add_alu(ctx->bc, &alu);
3970 if (r)
3971 return r;
3972 }
3973 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3974 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3975 alu.src[0].sel = V_SQ_ALU_SRC_1;
3976 alu.src[0].chan = 0;
3977 alu.dst.sel = ctx->temp_reg;
3978 alu.dst.chan = 3;
3979 alu.last = 1;
3980 alu.dst.write = 1;
3981 r = r600_bytecode_add_alu(ctx->bc, &alu);
3982 if (r)
3983 return r;
3984 src_loaded = TRUE;
3985 src_gpr = ctx->temp_reg;
3986 }
3987
3988 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3989 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3990 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
3991 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
3992 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3993 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
3994
3995 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3996 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3997
3998 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3999 for (i = 0; i < 4; i++) {
4000 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4001 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
4002 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4003 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4004 alu.dst.sel = ctx->temp_reg;
4005 alu.dst.chan = i;
4006 if (i == 3)
4007 alu.last = 1;
4008 alu.dst.write = 1;
4009 r = r600_bytecode_add_alu(ctx->bc, &alu);
4010 if (r)
4011 return r;
4012 }
4013
4014 /* tmp1.z = RCP_e(|tmp1.z|) */
4015 if (ctx->bc->chip_class == CAYMAN) {
4016 for (i = 0; i < 3; i++) {
4017 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4018 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
4019 alu.src[0].sel = ctx->temp_reg;
4020 alu.src[0].chan = 2;
4021 alu.src[0].abs = 1;
4022 alu.dst.sel = ctx->temp_reg;
4023 alu.dst.chan = i;
4024 if (i == 2)
4025 alu.dst.write = 1;
4026 if (i == 2)
4027 alu.last = 1;
4028 r = r600_bytecode_add_alu(ctx->bc, &alu);
4029 if (r)
4030 return r;
4031 }
4032 } else {
4033 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4034 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
4035 alu.src[0].sel = ctx->temp_reg;
4036 alu.src[0].chan = 2;
4037 alu.src[0].abs = 1;
4038 alu.dst.sel = ctx->temp_reg;
4039 alu.dst.chan = 2;
4040 alu.dst.write = 1;
4041 alu.last = 1;
4042 r = r600_bytecode_add_alu(ctx->bc, &alu);
4043 if (r)
4044 return r;
4045 }
4046
4047 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4048 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4049 * muladd has no writemask, have to use another temp
4050 */
4051 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4052 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
4053 alu.is_op3 = 1;
4054
4055 alu.src[0].sel = ctx->temp_reg;
4056 alu.src[0].chan = 0;
4057 alu.src[1].sel = ctx->temp_reg;
4058 alu.src[1].chan = 2;
4059
4060 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4061 alu.src[2].chan = 0;
4062 alu.src[2].value = *(uint32_t *)&one_point_five;
4063
4064 alu.dst.sel = ctx->temp_reg;
4065 alu.dst.chan = 0;
4066 alu.dst.write = 1;
4067
4068 r = r600_bytecode_add_alu(ctx->bc, &alu);
4069 if (r)
4070 return r;
4071
4072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4073 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
4074 alu.is_op3 = 1;
4075
4076 alu.src[0].sel = ctx->temp_reg;
4077 alu.src[0].chan = 1;
4078 alu.src[1].sel = ctx->temp_reg;
4079 alu.src[1].chan = 2;
4080
4081 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4082 alu.src[2].chan = 0;
4083 alu.src[2].value = *(uint32_t *)&one_point_five;
4084
4085 alu.dst.sel = ctx->temp_reg;
4086 alu.dst.chan = 1;
4087 alu.dst.write = 1;
4088
4089 alu.last = 1;
4090 r = r600_bytecode_add_alu(ctx->bc, &alu);
4091 if (r)
4092 return r;
4093 /* write initial compare value into Z component
4094 - W src 0 for shadow cube
4095 - X src 1 for shadow cube array */
4096 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4097 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4098 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4099 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4100 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4101 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4102 else
4103 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4104 alu.dst.sel = ctx->temp_reg;
4105 alu.dst.chan = 2;
4106 alu.dst.write = 1;
4107 alu.last = 1;
4108 r = r600_bytecode_add_alu(ctx->bc, &alu);
4109 if (r)
4110 return r;
4111 }
4112
4113 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4114 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4115 if (ctx->bc->chip_class >= EVERGREEN) {
4116 int mytmp = r600_get_temp(ctx);
4117 static const float eight = 8.0f;
4118 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4119 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4120 alu.src[0].sel = ctx->temp_reg;
4121 alu.src[0].chan = 3;
4122 alu.dst.sel = mytmp;
4123 alu.dst.chan = 0;
4124 alu.dst.write = 1;
4125 alu.last = 1;
4126 r = r600_bytecode_add_alu(ctx->bc, &alu);
4127 if (r)
4128 return r;
4129
4130 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4131 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4132 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
4133 alu.is_op3 = 1;
4134 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4135 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4136 alu.src[1].chan = 0;
4137 alu.src[1].value = *(uint32_t *)&eight;
4138 alu.src[2].sel = mytmp;
4139 alu.src[2].chan = 0;
4140 alu.dst.sel = ctx->temp_reg;
4141 alu.dst.chan = 3;
4142 alu.dst.write = 1;
4143 alu.last = 1;
4144 r = r600_bytecode_add_alu(ctx->bc, &alu);
4145 if (r)
4146 return r;
4147 } else if (ctx->bc->chip_class < EVERGREEN) {
4148 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4149 tex.inst = SQ_TEX_INST_SET_CUBEMAP_INDEX;
4150 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4151 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4152 tex.src_gpr = r600_get_temp(ctx);
4153 tex.src_sel_x = 0;
4154 tex.src_sel_y = 0;
4155 tex.src_sel_z = 0;
4156 tex.src_sel_w = 0;
4157 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4158 tex.coord_type_x = 1;
4159 tex.coord_type_y = 1;
4160 tex.coord_type_z = 1;
4161 tex.coord_type_w = 1;
4162 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4163 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4164 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4165 alu.dst.sel = tex.src_gpr;
4166 alu.dst.chan = 0;
4167 alu.last = 1;
4168 alu.dst.write = 1;
4169 r = r600_bytecode_add_alu(ctx->bc, &alu);
4170 if (r)
4171 return r;
4172
4173 r = r600_bytecode_add_tex(ctx->bc, &tex);
4174 if (r)
4175 return r;
4176 }
4177
4178 }
4179
4180 /* for cube forms of lod and bias we need to route things */
4181 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4182 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4183 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4184 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4185 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4186 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4187 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4188 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4189 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4190 else
4191 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4192 alu.dst.sel = ctx->temp_reg;
4193 alu.dst.chan = 2;
4194 alu.last = 1;
4195 alu.dst.write = 1;
4196 r = r600_bytecode_add_alu(ctx->bc, &alu);
4197 if (r)
4198 return r;
4199 }
4200
4201 src_loaded = TRUE;
4202 src_gpr = ctx->temp_reg;
4203 }
4204
4205 if (src_requires_loading && !src_loaded) {
4206 for (i = 0; i < 4; i++) {
4207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4208 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4209 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4210 alu.dst.sel = ctx->temp_reg;
4211 alu.dst.chan = i;
4212 if (i == 3)
4213 alu.last = 1;
4214 alu.dst.write = 1;
4215 r = r600_bytecode_add_alu(ctx->bc, &alu);
4216 if (r)
4217 return r;
4218 }
4219 src_loaded = TRUE;
4220 src_gpr = ctx->temp_reg;
4221 }
4222
4223 /* Obtain the sample index for reading a compressed MSAA color texture.
4224 * To read the FMASK, we use the ldfptr instruction, which tells us
4225 * where the samples are stored.
4226 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4227 * which is the identity mapping. Each nibble says which physical sample
4228 * should be fetched to get that sample.
4229 *
4230 * Assume src.z contains the sample index. It should be modified like this:
4231 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4232 * Then fetch the texel with src.
4233 */
4234 if (read_compressed_msaa) {
4235 unsigned sample_chan = inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ? 3 : 4;
4236 unsigned temp = r600_get_temp(ctx);
4237 assert(src_loaded);
4238
4239 /* temp.w = ldfptr() */
4240 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4241 tex.inst = SQ_TEX_INST_LD;
4242 tex.inst_mod = 1; /* to indicate this is ldfptr */
4243 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4244 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4245 tex.src_gpr = src_gpr;
4246 tex.dst_gpr = temp;
4247 tex.dst_sel_x = 7; /* mask out these components */
4248 tex.dst_sel_y = 7;
4249 tex.dst_sel_z = 7;
4250 tex.dst_sel_w = 0; /* store X */
4251 tex.src_sel_x = 0;
4252 tex.src_sel_y = 1;
4253 tex.src_sel_z = 2;
4254 tex.src_sel_w = 3;
4255 tex.offset_x = offset_x;
4256 tex.offset_y = offset_y;
4257 tex.offset_z = offset_z;
4258 r = r600_bytecode_add_tex(ctx->bc, &tex);
4259 if (r)
4260 return r;
4261
4262 /* temp.x = sample_index*4 */
4263 if (ctx->bc->chip_class == CAYMAN) {
4264 for (i = 0 ; i < 4; i++) {
4265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4266 alu.inst = ctx->inst_info->r600_opcode;
4267 alu.src[0].sel = src_gpr;
4268 alu.src[0].chan = sample_chan;
4269 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4270 alu.src[1].value = 4;
4271 alu.dst.sel = temp;
4272 alu.dst.chan = i;
4273 alu.dst.write = i == 0;
4274 if (i == 3)
4275 alu.last = 1;
4276 r = r600_bytecode_add_alu(ctx->bc, &alu);
4277 if (r)
4278 return r;
4279 }
4280 } else {
4281 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4282 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT);
4283 alu.src[0].sel = src_gpr;
4284 alu.src[0].chan = sample_chan;
4285 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4286 alu.src[1].value = 4;
4287 alu.dst.sel = temp;
4288 alu.dst.chan = 0;
4289 alu.dst.write = 1;
4290 alu.last = 1;
4291 r = r600_bytecode_add_alu(ctx->bc, &alu);
4292 if (r)
4293 return r;
4294 }
4295
4296 /* sample_index = temp.w >> temp.x */
4297 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4298 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT);
4299 alu.src[0].sel = temp;
4300 alu.src[0].chan = 3;
4301 alu.src[1].sel = temp;
4302 alu.src[1].chan = 0;
4303 alu.dst.sel = src_gpr;
4304 alu.dst.chan = sample_chan;
4305 alu.dst.write = 1;
4306 alu.last = 1;
4307 r = r600_bytecode_add_alu(ctx->bc, &alu);
4308 if (r)
4309 return r;
4310
4311 /* sample_index & 0xF */
4312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4313 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
4314 alu.src[0].sel = src_gpr;
4315 alu.src[0].chan = sample_chan;
4316 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4317 alu.src[1].value = 0xF;
4318 alu.dst.sel = src_gpr;
4319 alu.dst.chan = sample_chan;
4320 alu.dst.write = 1;
4321 alu.last = 1;
4322 r = r600_bytecode_add_alu(ctx->bc, &alu);
4323 if (r)
4324 return r;
4325 #if 0
4326 /* visualize the FMASK */
4327 for (i = 0; i < 4; i++) {
4328 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4329 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
4330 alu.src[0].sel = src_gpr;
4331 alu.src[0].chan = sample_chan;
4332 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4333 alu.dst.chan = i;
4334 alu.dst.write = 1;
4335 alu.last = 1;
4336 r = r600_bytecode_add_alu(ctx->bc, &alu);
4337 if (r)
4338 return r;
4339 }
4340 return 0;
4341 #endif
4342 }
4343
4344 /* does this shader want a num layers from TXQ for a cube array? */
4345 if (has_txq_cube_array_z) {
4346 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4347
4348 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4349 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4350
4351 alu.src[0].sel = 512 + (id / 4);
4352 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4353 alu.src[0].chan = id % 4;
4354 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4355 alu.last = 1;
4356 r = r600_bytecode_add_alu(ctx->bc, &alu);
4357 if (r)
4358 return r;
4359 /* disable writemask from texture instruction */
4360 inst->Dst[0].Register.WriteMask &= ~4;
4361 }
4362
4363 opcode = ctx->inst_info->r600_opcode;
4364 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4365 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4366 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4367 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4368 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4369 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4370 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4371 switch (opcode) {
4372 case SQ_TEX_INST_SAMPLE:
4373 opcode = SQ_TEX_INST_SAMPLE_C;
4374 break;
4375 case SQ_TEX_INST_SAMPLE_L:
4376 opcode = SQ_TEX_INST_SAMPLE_C_L;
4377 break;
4378 case SQ_TEX_INST_SAMPLE_LB:
4379 opcode = SQ_TEX_INST_SAMPLE_C_LB;
4380 break;
4381 case SQ_TEX_INST_SAMPLE_G:
4382 opcode = SQ_TEX_INST_SAMPLE_C_G;
4383 break;
4384 }
4385 }
4386
4387 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4388 tex.inst = opcode;
4389
4390 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4391 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4392 tex.src_gpr = src_gpr;
4393 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4394 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4395 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4396 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4397 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4398
4399 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4400 tex.src_sel_x = 4;
4401 tex.src_sel_y = 4;
4402 tex.src_sel_z = 4;
4403 tex.src_sel_w = 4;
4404 } else if (src_loaded) {
4405 tex.src_sel_x = 0;
4406 tex.src_sel_y = 1;
4407 tex.src_sel_z = 2;
4408 tex.src_sel_w = 3;
4409 } else {
4410 tex.src_sel_x = ctx->src[0].swizzle[0];
4411 tex.src_sel_y = ctx->src[0].swizzle[1];
4412 tex.src_sel_z = ctx->src[0].swizzle[2];
4413 tex.src_sel_w = ctx->src[0].swizzle[3];
4414 tex.src_rel = ctx->src[0].rel;
4415 }
4416
4417 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4418 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4419 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4420 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4421 tex.src_sel_x = 1;
4422 tex.src_sel_y = 0;
4423 tex.src_sel_z = 3;
4424 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4425 }
4426
4427 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4428 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4429 tex.coord_type_x = 1;
4430 tex.coord_type_y = 1;
4431 }
4432 tex.coord_type_z = 1;
4433 tex.coord_type_w = 1;
4434
4435 tex.offset_x = offset_x;
4436 tex.offset_y = offset_y;
4437 tex.offset_z = offset_z;
4438
4439 /* Put the depth for comparison in W.
4440 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4441 * Some instructions expect the depth in Z. */
4442 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4443 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4444 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4445 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4446 opcode != SQ_TEX_INST_SAMPLE_C_L &&
4447 opcode != SQ_TEX_INST_SAMPLE_C_LB) {
4448 tex.src_sel_w = tex.src_sel_z;
4449 }
4450
4451 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4452 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4453 if (opcode == SQ_TEX_INST_SAMPLE_C_L ||
4454 opcode == SQ_TEX_INST_SAMPLE_C_LB) {
4455 /* the array index is read from Y */
4456 tex.coord_type_y = 0;
4457 } else {
4458 /* the array index is read from Z */
4459 tex.coord_type_z = 0;
4460 tex.src_sel_z = tex.src_sel_y;
4461 }
4462 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4463 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4464 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4465 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4466 (ctx->bc->chip_class >= EVERGREEN)))
4467 /* the array index is read from Z */
4468 tex.coord_type_z = 0;
4469
4470 r = r600_bytecode_add_tex(ctx->bc, &tex);
4471 if (r)
4472 return r;
4473
4474 /* add shadow ambient support - gallium doesn't do it yet */
4475 return 0;
4476 }
4477
4478 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4479 {
4480 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4481 struct r600_bytecode_alu alu;
4482 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4483 unsigned i;
4484 int r;
4485
4486 /* optimize if it's just an equal balance */
4487 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4488 for (i = 0; i < lasti + 1; i++) {
4489 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4490 continue;
4491
4492 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4493 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
4494 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4495 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4496 alu.omod = 3;
4497 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4498 alu.dst.chan = i;
4499 if (i == lasti) {
4500 alu.last = 1;
4501 }
4502 r = r600_bytecode_add_alu(ctx->bc, &alu);
4503 if (r)
4504 return r;
4505 }
4506 return 0;
4507 }
4508
4509 /* 1 - src0 */
4510 for (i = 0; i < lasti + 1; i++) {
4511 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4512 continue;
4513
4514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4515 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
4516 alu.src[0].sel = V_SQ_ALU_SRC_1;
4517 alu.src[0].chan = 0;
4518 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4519 r600_bytecode_src_toggle_neg(&alu.src[1]);
4520 alu.dst.sel = ctx->temp_reg;
4521 alu.dst.chan = i;
4522 if (i == lasti) {
4523 alu.last = 1;
4524 }
4525 alu.dst.write = 1;
4526 r = r600_bytecode_add_alu(ctx->bc, &alu);
4527 if (r)
4528 return r;
4529 }
4530
4531 /* (1 - src0) * src2 */
4532 for (i = 0; i < lasti + 1; i++) {
4533 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4534 continue;
4535
4536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4537 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4538 alu.src[0].sel = ctx->temp_reg;
4539 alu.src[0].chan = i;
4540 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4541 alu.dst.sel = ctx->temp_reg;
4542 alu.dst.chan = i;
4543 if (i == lasti) {
4544 alu.last = 1;
4545 }
4546 alu.dst.write = 1;
4547 r = r600_bytecode_add_alu(ctx->bc, &alu);
4548 if (r)
4549 return r;
4550 }
4551
4552 /* src0 * src1 + (1 - src0) * src2 */
4553 for (i = 0; i < lasti + 1; i++) {
4554 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4555 continue;
4556
4557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4558 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
4559 alu.is_op3 = 1;
4560 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4561 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4562 alu.src[2].sel = ctx->temp_reg;
4563 alu.src[2].chan = i;
4564
4565 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4566 alu.dst.chan = i;
4567 if (i == lasti) {
4568 alu.last = 1;
4569 }
4570 r = r600_bytecode_add_alu(ctx->bc, &alu);
4571 if (r)
4572 return r;
4573 }
4574 return 0;
4575 }
4576
4577 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4578 {
4579 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4580 struct r600_bytecode_alu alu;
4581 int i, r;
4582 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4583
4584 for (i = 0; i < lasti + 1; i++) {
4585 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4586 continue;
4587
4588 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4589 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
4590 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4591 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4592 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4593 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4594 alu.dst.chan = i;
4595 alu.dst.write = 1;
4596 alu.is_op3 = 1;
4597 if (i == lasti)
4598 alu.last = 1;
4599 r = r600_bytecode_add_alu(ctx->bc, &alu);
4600 if (r)
4601 return r;
4602 }
4603 return 0;
4604 }
4605
4606 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4607 {
4608 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4609 static const unsigned int src0_swizzle[] = {2, 0, 1};
4610 static const unsigned int src1_swizzle[] = {1, 2, 0};
4611 struct r600_bytecode_alu alu;
4612 uint32_t use_temp = 0;
4613 int i, r;
4614
4615 if (inst->Dst[0].Register.WriteMask != 0xf)
4616 use_temp = 1;
4617
4618 for (i = 0; i < 4; i++) {
4619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4620 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4621 if (i < 3) {
4622 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4623 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4624 } else {
4625 alu.src[0].sel = V_SQ_ALU_SRC_0;
4626 alu.src[0].chan = i;
4627 alu.src[1].sel = V_SQ_ALU_SRC_0;
4628 alu.src[1].chan = i;
4629 }
4630
4631 alu.dst.sel = ctx->temp_reg;
4632 alu.dst.chan = i;
4633 alu.dst.write = 1;
4634
4635 if (i == 3)
4636 alu.last = 1;
4637 r = r600_bytecode_add_alu(ctx->bc, &alu);
4638 if (r)
4639 return r;
4640 }
4641
4642 for (i = 0; i < 4; i++) {
4643 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4644 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
4645
4646 if (i < 3) {
4647 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4648 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4649 } else {
4650 alu.src[0].sel = V_SQ_ALU_SRC_0;
4651 alu.src[0].chan = i;
4652 alu.src[1].sel = V_SQ_ALU_SRC_0;
4653 alu.src[1].chan = i;
4654 }
4655
4656 alu.src[2].sel = ctx->temp_reg;
4657 alu.src[2].neg = 1;
4658 alu.src[2].chan = i;
4659
4660 if (use_temp)
4661 alu.dst.sel = ctx->temp_reg;
4662 else
4663 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4664 alu.dst.chan = i;
4665 alu.dst.write = 1;
4666 alu.is_op3 = 1;
4667 if (i == 3)
4668 alu.last = 1;
4669 r = r600_bytecode_add_alu(ctx->bc, &alu);
4670 if (r)
4671 return r;
4672 }
4673 if (use_temp)
4674 return tgsi_helper_copy(ctx, inst);
4675 return 0;
4676 }
4677
4678 static int tgsi_exp(struct r600_shader_ctx *ctx)
4679 {
4680 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4681 struct r600_bytecode_alu alu;
4682 int r;
4683 int i;
4684
4685 /* result.x = 2^floor(src); */
4686 if (inst->Dst[0].Register.WriteMask & 1) {
4687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4688
4689 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
4690 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4691
4692 alu.dst.sel = ctx->temp_reg;
4693 alu.dst.chan = 0;
4694 alu.dst.write = 1;
4695 alu.last = 1;
4696 r = r600_bytecode_add_alu(ctx->bc, &alu);
4697 if (r)
4698 return r;
4699
4700 if (ctx->bc->chip_class == CAYMAN) {
4701 for (i = 0; i < 3; i++) {
4702 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4703 alu.src[0].sel = ctx->temp_reg;
4704 alu.src[0].chan = 0;
4705
4706 alu.dst.sel = ctx->temp_reg;
4707 alu.dst.chan = i;
4708 alu.dst.write = i == 0;
4709 alu.last = i == 2;
4710 r = r600_bytecode_add_alu(ctx->bc, &alu);
4711 if (r)
4712 return r;
4713 }
4714 } else {
4715 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4716 alu.src[0].sel = ctx->temp_reg;
4717 alu.src[0].chan = 0;
4718
4719 alu.dst.sel = ctx->temp_reg;
4720 alu.dst.chan = 0;
4721 alu.dst.write = 1;
4722 alu.last = 1;
4723 r = r600_bytecode_add_alu(ctx->bc, &alu);
4724 if (r)
4725 return r;
4726 }
4727 }
4728
4729 /* result.y = tmp - floor(tmp); */
4730 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4732
4733 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
4734 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4735
4736 alu.dst.sel = ctx->temp_reg;
4737 #if 0
4738 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4739 if (r)
4740 return r;
4741 #endif
4742 alu.dst.write = 1;
4743 alu.dst.chan = 1;
4744
4745 alu.last = 1;
4746
4747 r = r600_bytecode_add_alu(ctx->bc, &alu);
4748 if (r)
4749 return r;
4750 }
4751
4752 /* result.z = RoughApprox2ToX(tmp);*/
4753 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4754 if (ctx->bc->chip_class == CAYMAN) {
4755 for (i = 0; i < 3; i++) {
4756 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4757 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4758 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4759
4760 alu.dst.sel = ctx->temp_reg;
4761 alu.dst.chan = i;
4762 if (i == 2) {
4763 alu.dst.write = 1;
4764 alu.last = 1;
4765 }
4766
4767 r = r600_bytecode_add_alu(ctx->bc, &alu);
4768 if (r)
4769 return r;
4770 }
4771 } else {
4772 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4773 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4774 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4775
4776 alu.dst.sel = ctx->temp_reg;
4777 alu.dst.write = 1;
4778 alu.dst.chan = 2;
4779
4780 alu.last = 1;
4781
4782 r = r600_bytecode_add_alu(ctx->bc, &alu);
4783 if (r)
4784 return r;
4785 }
4786 }
4787
4788 /* result.w = 1.0;*/
4789 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4790 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4791
4792 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
4793 alu.src[0].sel = V_SQ_ALU_SRC_1;
4794 alu.src[0].chan = 0;
4795
4796 alu.dst.sel = ctx->temp_reg;
4797 alu.dst.chan = 3;
4798 alu.dst.write = 1;
4799 alu.last = 1;
4800 r = r600_bytecode_add_alu(ctx->bc, &alu);
4801 if (r)
4802 return r;
4803 }
4804 return tgsi_helper_copy(ctx, inst);
4805 }
4806
4807 static int tgsi_log(struct r600_shader_ctx *ctx)
4808 {
4809 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4810 struct r600_bytecode_alu alu;
4811 int r;
4812 int i;
4813
4814 /* result.x = floor(log2(|src|)); */
4815 if (inst->Dst[0].Register.WriteMask & 1) {
4816 if (ctx->bc->chip_class == CAYMAN) {
4817 for (i = 0; i < 3; i++) {
4818 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4819
4820 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4821 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4822 r600_bytecode_src_set_abs(&alu.src[0]);
4823
4824 alu.dst.sel = ctx->temp_reg;
4825 alu.dst.chan = i;
4826 if (i == 0)
4827 alu.dst.write = 1;
4828 if (i == 2)
4829 alu.last = 1;
4830 r = r600_bytecode_add_alu(ctx->bc, &alu);
4831 if (r)
4832 return r;
4833 }
4834
4835 } else {
4836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4837
4838 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4839 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4840 r600_bytecode_src_set_abs(&alu.src[0]);
4841
4842 alu.dst.sel = ctx->temp_reg;
4843 alu.dst.chan = 0;
4844 alu.dst.write = 1;
4845 alu.last = 1;
4846 r = r600_bytecode_add_alu(ctx->bc, &alu);
4847 if (r)
4848 return r;
4849 }
4850
4851 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
4852 alu.src[0].sel = ctx->temp_reg;
4853 alu.src[0].chan = 0;
4854
4855 alu.dst.sel = ctx->temp_reg;
4856 alu.dst.chan = 0;
4857 alu.dst.write = 1;
4858 alu.last = 1;
4859
4860 r = r600_bytecode_add_alu(ctx->bc, &alu);
4861 if (r)
4862 return r;
4863 }
4864
4865 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4866 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4867
4868 if (ctx->bc->chip_class == CAYMAN) {
4869 for (i = 0; i < 3; i++) {
4870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4871
4872 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4873 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4874 r600_bytecode_src_set_abs(&alu.src[0]);
4875
4876 alu.dst.sel = ctx->temp_reg;
4877 alu.dst.chan = i;
4878 if (i == 1)
4879 alu.dst.write = 1;
4880 if (i == 2)
4881 alu.last = 1;
4882
4883 r = r600_bytecode_add_alu(ctx->bc, &alu);
4884 if (r)
4885 return r;
4886 }
4887 } else {
4888 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4889
4890 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
4891 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4892 r600_bytecode_src_set_abs(&alu.src[0]);
4893
4894 alu.dst.sel = ctx->temp_reg;
4895 alu.dst.chan = 1;
4896 alu.dst.write = 1;
4897 alu.last = 1;
4898
4899 r = r600_bytecode_add_alu(ctx->bc, &alu);
4900 if (r)
4901 return r;
4902 }
4903
4904 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4905
4906 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
4907 alu.src[0].sel = ctx->temp_reg;
4908 alu.src[0].chan = 1;
4909
4910 alu.dst.sel = ctx->temp_reg;
4911 alu.dst.chan = 1;
4912 alu.dst.write = 1;
4913 alu.last = 1;
4914
4915 r = r600_bytecode_add_alu(ctx->bc, &alu);
4916 if (r)
4917 return r;
4918
4919 if (ctx->bc->chip_class == CAYMAN) {
4920 for (i = 0; i < 3; i++) {
4921 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4922 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4923 alu.src[0].sel = ctx->temp_reg;
4924 alu.src[0].chan = 1;
4925
4926 alu.dst.sel = ctx->temp_reg;
4927 alu.dst.chan = i;
4928 if (i == 1)
4929 alu.dst.write = 1;
4930 if (i == 2)
4931 alu.last = 1;
4932
4933 r = r600_bytecode_add_alu(ctx->bc, &alu);
4934 if (r)
4935 return r;
4936 }
4937 } else {
4938 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4939 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
4940 alu.src[0].sel = ctx->temp_reg;
4941 alu.src[0].chan = 1;
4942
4943 alu.dst.sel = ctx->temp_reg;
4944 alu.dst.chan = 1;
4945 alu.dst.write = 1;
4946 alu.last = 1;
4947
4948 r = r600_bytecode_add_alu(ctx->bc, &alu);
4949 if (r)
4950 return r;
4951 }
4952
4953 if (ctx->bc->chip_class == CAYMAN) {
4954 for (i = 0; i < 3; i++) {
4955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4956 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
4957 alu.src[0].sel = ctx->temp_reg;
4958 alu.src[0].chan = 1;
4959
4960 alu.dst.sel = ctx->temp_reg;
4961 alu.dst.chan = i;
4962 if (i == 1)
4963 alu.dst.write = 1;
4964 if (i == 2)
4965 alu.last = 1;
4966
4967 r = r600_bytecode_add_alu(ctx->bc, &alu);
4968 if (r)
4969 return r;
4970 }
4971 } else {
4972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4973 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
4974 alu.src[0].sel = ctx->temp_reg;
4975 alu.src[0].chan = 1;
4976
4977 alu.dst.sel = ctx->temp_reg;
4978 alu.dst.chan = 1;
4979 alu.dst.write = 1;
4980 alu.last = 1;
4981
4982 r = r600_bytecode_add_alu(ctx->bc, &alu);
4983 if (r)
4984 return r;
4985 }
4986
4987 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4988
4989 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
4990
4991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4992 r600_bytecode_src_set_abs(&alu.src[0]);
4993
4994 alu.src[1].sel = ctx->temp_reg;
4995 alu.src[1].chan = 1;
4996
4997 alu.dst.sel = ctx->temp_reg;
4998 alu.dst.chan = 1;
4999 alu.dst.write = 1;
5000 alu.last = 1;
5001
5002 r = r600_bytecode_add_alu(ctx->bc, &alu);
5003 if (r)
5004 return r;
5005 }
5006
5007 /* result.z = log2(|src|);*/
5008 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5009 if (ctx->bc->chip_class == CAYMAN) {
5010 for (i = 0; i < 3; i++) {
5011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5012
5013 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
5014 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5015 r600_bytecode_src_set_abs(&alu.src[0]);
5016
5017 alu.dst.sel = ctx->temp_reg;
5018 if (i == 2)
5019 alu.dst.write = 1;
5020 alu.dst.chan = i;
5021 if (i == 2)
5022 alu.last = 1;
5023
5024 r = r600_bytecode_add_alu(ctx->bc, &alu);
5025 if (r)
5026 return r;
5027 }
5028 } else {
5029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5030
5031 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
5032 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5033 r600_bytecode_src_set_abs(&alu.src[0]);
5034
5035 alu.dst.sel = ctx->temp_reg;
5036 alu.dst.write = 1;
5037 alu.dst.chan = 2;
5038 alu.last = 1;
5039
5040 r = r600_bytecode_add_alu(ctx->bc, &alu);
5041 if (r)
5042 return r;
5043 }
5044 }
5045
5046 /* result.w = 1.0; */
5047 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5048 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5049
5050 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
5051 alu.src[0].sel = V_SQ_ALU_SRC_1;
5052 alu.src[0].chan = 0;
5053
5054 alu.dst.sel = ctx->temp_reg;
5055 alu.dst.chan = 3;
5056 alu.dst.write = 1;
5057 alu.last = 1;
5058
5059 r = r600_bytecode_add_alu(ctx->bc, &alu);
5060 if (r)
5061 return r;
5062 }
5063
5064 return tgsi_helper_copy(ctx, inst);
5065 }
5066
5067 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5068 {
5069 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5070 struct r600_bytecode_alu alu;
5071 int r;
5072
5073 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5074
5075 switch (inst->Instruction.Opcode) {
5076 case TGSI_OPCODE_ARL:
5077 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
5078 break;
5079 case TGSI_OPCODE_ARR:
5080 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
5081 break;
5082 case TGSI_OPCODE_UARL:
5083 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
5084 break;
5085 default:
5086 assert(0);
5087 return -1;
5088 }
5089
5090 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5091 alu.last = 1;
5092 alu.dst.sel = ctx->bc->ar_reg;
5093 alu.dst.write = 1;
5094 r = r600_bytecode_add_alu(ctx->bc, &alu);
5095 if (r)
5096 return r;
5097
5098 ctx->bc->ar_loaded = 0;
5099 return 0;
5100 }
5101 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5102 {
5103 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5104 struct r600_bytecode_alu alu;
5105 int r;
5106
5107 switch (inst->Instruction.Opcode) {
5108 case TGSI_OPCODE_ARL:
5109 memset(&alu, 0, sizeof(alu));
5110 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
5111 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5112 alu.dst.sel = ctx->bc->ar_reg;
5113 alu.dst.write = 1;
5114 alu.last = 1;
5115
5116 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5117 return r;
5118
5119 memset(&alu, 0, sizeof(alu));
5120 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
5121 alu.src[0].sel = ctx->bc->ar_reg;
5122 alu.dst.sel = ctx->bc->ar_reg;
5123 alu.dst.write = 1;
5124 alu.last = 1;
5125
5126 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5127 return r;
5128 break;
5129 case TGSI_OPCODE_ARR:
5130 memset(&alu, 0, sizeof(alu));
5131 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
5132 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5133 alu.dst.sel = ctx->bc->ar_reg;
5134 alu.dst.write = 1;
5135 alu.last = 1;
5136
5137 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5138 return r;
5139 break;
5140 case TGSI_OPCODE_UARL:
5141 memset(&alu, 0, sizeof(alu));
5142 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
5143 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5144 alu.dst.sel = ctx->bc->ar_reg;
5145 alu.dst.write = 1;
5146 alu.last = 1;
5147
5148 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5149 return r;
5150 break;
5151 default:
5152 assert(0);
5153 return -1;
5154 }
5155
5156 ctx->bc->ar_loaded = 0;
5157 return 0;
5158 }
5159
5160 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5161 {
5162 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5163 struct r600_bytecode_alu alu;
5164 int i, r = 0;
5165
5166 for (i = 0; i < 4; i++) {
5167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5168
5169 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
5170 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5171
5172 if (i == 0 || i == 3) {
5173 alu.src[0].sel = V_SQ_ALU_SRC_1;
5174 } else {
5175 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5176 }
5177
5178 if (i == 0 || i == 2) {
5179 alu.src[1].sel = V_SQ_ALU_SRC_1;
5180 } else {
5181 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5182 }
5183 if (i == 3)
5184 alu.last = 1;
5185 r = r600_bytecode_add_alu(ctx->bc, &alu);
5186 if (r)
5187 return r;
5188 }
5189 return 0;
5190 }
5191
5192 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
5193 {
5194 struct r600_bytecode_alu alu;
5195 int r;
5196
5197 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5198 alu.inst = opcode;
5199 alu.execute_mask = 1;
5200 alu.update_pred = 1;
5201
5202 alu.dst.sel = ctx->temp_reg;
5203 alu.dst.write = 1;
5204 alu.dst.chan = 0;
5205
5206 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5207 alu.src[1].sel = V_SQ_ALU_SRC_0;
5208 alu.src[1].chan = 0;
5209
5210 alu.last = 1;
5211
5212 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
5213 if (r)
5214 return r;
5215 return 0;
5216 }
5217
5218 static int pops(struct r600_shader_ctx *ctx, int pops)
5219 {
5220 unsigned force_pop = ctx->bc->force_add_cf;
5221
5222 if (!force_pop) {
5223 int alu_pop = 3;
5224 if (ctx->bc->cf_last) {
5225 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU))
5226 alu_pop = 0;
5227 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER))
5228 alu_pop = 1;
5229 }
5230 alu_pop += pops;
5231 if (alu_pop == 1) {
5232 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER);
5233 ctx->bc->force_add_cf = 1;
5234 } else if (alu_pop == 2) {
5235 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER);
5236 ctx->bc->force_add_cf = 1;
5237 } else {
5238 force_pop = 1;
5239 }
5240 }
5241
5242 if (force_pop) {
5243 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
5244 ctx->bc->cf_last->pop_count = pops;
5245 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5246 }
5247
5248 return 0;
5249 }
5250
5251 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
5252 {
5253 switch(reason) {
5254 case FC_PUSH_VPM:
5255 ctx->bc->callstack[ctx->bc->call_sp].current--;
5256 break;
5257 case FC_PUSH_WQM:
5258 case FC_LOOP:
5259 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
5260 break;
5261 case FC_REP:
5262 /* TOODO : for 16 vp asic should -= 2; */
5263 ctx->bc->callstack[ctx->bc->call_sp].current --;
5264 break;
5265 }
5266 }
5267
5268 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
5269 {
5270 if (check_max_only) {
5271 int diff;
5272 switch (reason) {
5273 case FC_PUSH_VPM:
5274 diff = 1;
5275 break;
5276 case FC_PUSH_WQM:
5277 diff = 4;
5278 break;
5279 default:
5280 assert(0);
5281 diff = 0;
5282 }
5283 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
5284 ctx->bc->callstack[ctx->bc->call_sp].max) {
5285 ctx->bc->callstack[ctx->bc->call_sp].max =
5286 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
5287 }
5288 return;
5289 }
5290 switch (reason) {
5291 case FC_PUSH_VPM:
5292 ctx->bc->callstack[ctx->bc->call_sp].current++;
5293 break;
5294 case FC_PUSH_WQM:
5295 case FC_LOOP:
5296 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
5297 break;
5298 case FC_REP:
5299 ctx->bc->callstack[ctx->bc->call_sp].current++;
5300 break;
5301 }
5302
5303 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
5304 ctx->bc->callstack[ctx->bc->call_sp].max) {
5305 ctx->bc->callstack[ctx->bc->call_sp].max =
5306 ctx->bc->callstack[ctx->bc->call_sp].current;
5307 }
5308 }
5309
5310 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5311 {
5312 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5313
5314 sp->mid = realloc((void *)sp->mid,
5315 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5316 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5317 sp->num_mid++;
5318 }
5319
5320 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5321 {
5322 ctx->bc->fc_sp++;
5323 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5324 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5325 }
5326
5327 static void fc_poplevel(struct r600_shader_ctx *ctx)
5328 {
5329 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5330 free(sp->mid);
5331 sp->mid = NULL;
5332 sp->num_mid = 0;
5333 sp->start = NULL;
5334 sp->type = 0;
5335 ctx->bc->fc_sp--;
5336 }
5337
5338 #if 0
5339 static int emit_return(struct r600_shader_ctx *ctx)
5340 {
5341 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
5342 return 0;
5343 }
5344
5345 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5346 {
5347
5348 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
5349 ctx->bc->cf_last->pop_count = pops;
5350 /* XXX work out offset */
5351 return 0;
5352 }
5353
5354 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5355 {
5356 return 0;
5357 }
5358
5359 static void emit_testflag(struct r600_shader_ctx *ctx)
5360 {
5361
5362 }
5363
5364 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5365 {
5366 emit_testflag(ctx);
5367 emit_jump_to_offset(ctx, 1, 4);
5368 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5369 pops(ctx, ifidx + 1);
5370 emit_return(ctx);
5371 }
5372
5373 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5374 {
5375 emit_testflag(ctx);
5376
5377 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
5378 ctx->bc->cf_last->pop_count = 1;
5379
5380 fc_set_mid(ctx, fc_sp);
5381
5382 pops(ctx, 1);
5383 }
5384 #endif
5385
5386 static int tgsi_if(struct r600_shader_ctx *ctx)
5387 {
5388 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
5389
5390 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
5391
5392 fc_pushlevel(ctx, FC_IF);
5393
5394 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
5395 return 0;
5396 }
5397
5398 static int tgsi_else(struct r600_shader_ctx *ctx)
5399 {
5400 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
5401 ctx->bc->cf_last->pop_count = 1;
5402
5403 fc_set_mid(ctx, ctx->bc->fc_sp);
5404 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5405 return 0;
5406 }
5407
5408 static int tgsi_endif(struct r600_shader_ctx *ctx)
5409 {
5410 pops(ctx, 1);
5411 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5412 R600_ERR("if/endif unbalanced in shader\n");
5413 return -1;
5414 }
5415
5416 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5417 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5418 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5419 } else {
5420 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5421 }
5422 fc_poplevel(ctx);
5423
5424 callstack_decrease_current(ctx, FC_PUSH_VPM);
5425 return 0;
5426 }
5427
5428 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5429 {
5430 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5431 * limited to 4096 iterations, like the other LOOP_* instructions. */
5432 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_DX10));
5433
5434 fc_pushlevel(ctx, FC_LOOP);
5435
5436 /* check stack depth */
5437 callstack_check_depth(ctx, FC_LOOP, 0);
5438 return 0;
5439 }
5440
5441 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5442 {
5443 int i;
5444
5445 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
5446
5447 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5448 R600_ERR("loop/endloop in shader code are not paired.\n");
5449 return -EINVAL;
5450 }
5451
5452 /* fixup loop pointers - from r600isa
5453 LOOP END points to CF after LOOP START,
5454 LOOP START point to CF after LOOP END
5455 BRK/CONT point to LOOP END CF
5456 */
5457 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5458
5459 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5460
5461 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5462 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5463 }
5464 /* XXX add LOOPRET support */
5465 fc_poplevel(ctx);
5466 callstack_decrease_current(ctx, FC_LOOP);
5467 return 0;
5468 }
5469
5470 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5471 {
5472 unsigned int fscp;
5473
5474 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5475 {
5476 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5477 break;
5478 }
5479
5480 if (fscp == 0) {
5481 R600_ERR("Break not inside loop/endloop pair\n");
5482 return -EINVAL;
5483 }
5484
5485 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
5486
5487 fc_set_mid(ctx, fscp);
5488
5489 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
5490 return 0;
5491 }
5492
5493 static int tgsi_umad(struct r600_shader_ctx *ctx)
5494 {
5495 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5496 struct r600_bytecode_alu alu;
5497 int i, j, r;
5498 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5499
5500 /* src0 * src1 */
5501 for (i = 0; i < lasti + 1; i++) {
5502 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5503 continue;
5504
5505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5506
5507 alu.dst.chan = i;
5508 alu.dst.sel = ctx->temp_reg;
5509 alu.dst.write = 1;
5510
5511 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
5512 for (j = 0; j < 2; j++) {
5513 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5514 }
5515
5516 alu.last = 1;
5517 r = r600_bytecode_add_alu(ctx->bc, &alu);
5518 if (r)
5519 return r;
5520 }
5521
5522
5523 for (i = 0; i < lasti + 1; i++) {
5524 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5525 continue;
5526
5527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5528 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5529
5530 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
5531
5532 alu.src[0].sel = ctx->temp_reg;
5533 alu.src[0].chan = i;
5534
5535 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5536 if (i == lasti) {
5537 alu.last = 1;
5538 }
5539 r = r600_bytecode_add_alu(ctx->bc, &alu);
5540 if (r)
5541 return r;
5542 }
5543 return 0;
5544 }
5545
5546 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5547 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
5548 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5549 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
5550
5551 /* XXX:
5552 * For state trackers other than OpenGL, we'll want to use
5553 * _RECIP_IEEE instead.
5554 */
5555 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5556
5557 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
5558 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
5559 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
5560 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
5561 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5562 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5563 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5564 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
5565 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
5566 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
5567 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
5568 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
5569 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
5570 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5571 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
5572 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5573 /* gap */
5574 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5575 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5576 /* gap */
5577 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5578 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5579 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
5580 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5581 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
5582 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
5583 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
5584 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
5585 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
5586 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
5587 /* gap */
5588 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5589 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5590 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5591 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5592 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
5593 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5594 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
5595 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
5596 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5597 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5598 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5599 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5600 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5601 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
5602 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5603 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
5604 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
5605 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
5606 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
5607 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5608 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5609 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
5610 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5611 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5612 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5613 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5614 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5615 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5616 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5617 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
5618 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5619 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5620 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5621 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
5622 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
5623 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
5624 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
5625 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5626 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5627 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5628 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
5629 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
5630 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
5631 /* gap */
5632 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5633 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5634 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
5635 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
5636 /* gap */
5637 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5638 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5639 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5640 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5641 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
5642 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
5643 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
5644 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
5645 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2_trans},
5646 /* gap */
5647 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5648 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
5649 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
5650 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
5651 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
5652 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5653 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
5654 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
5655 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
5656 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5657 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5658 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
5659 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5660 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
5661 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5662 {TGSI_OPCODE_TXQ_LZ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
5663 /* gap */
5664 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5665 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5666 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5667 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5668 /* gap */
5669 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5670 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5671 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5672 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5673 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5674 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5675 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5676 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5677 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
5678 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
5679 /* gap */
5680 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5681 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2_trans},
5682 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
5683 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
5684 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
5685 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
5686 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
5687 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2_trans},
5688 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
5689 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2_trans},
5690 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
5691 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
5692 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
5693 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
5694 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
5695 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
5696 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
5697 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
5698 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
5699 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
5700 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2_trans},
5701 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
5702 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2_swap},
5703 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5704 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5705 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5706 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5707 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5708 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5709 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5710 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5711 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5712 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5713 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5714 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5715 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5716 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5717 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5718 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5719 {TGSI_OPCODE_UARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
5720 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
5721 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5722 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5723 {TGSI_OPCODE_LOAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5724 {TGSI_OPCODE_STORE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5725 {TGSI_OPCODE_MFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5726 {TGSI_OPCODE_LFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5727 {TGSI_OPCODE_SFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5728 {TGSI_OPCODE_BARRIER, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5729 {TGSI_OPCODE_ATOMUADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5730 {TGSI_OPCODE_ATOMXCHG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5731 {TGSI_OPCODE_ATOMCAS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5732 {TGSI_OPCODE_ATOMAND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5733 {TGSI_OPCODE_ATOMOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5734 {TGSI_OPCODE_ATOMXOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5735 {TGSI_OPCODE_ATOMUMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5736 {TGSI_OPCODE_ATOMUMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5737 {TGSI_OPCODE_ATOMIMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5738 {TGSI_OPCODE_ATOMIMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5739 {TGSI_OPCODE_TEX2, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5740 {TGSI_OPCODE_TXB2, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
5741 {TGSI_OPCODE_TXL2, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
5742 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5743 };
5744
5745 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5746 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5747 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5748 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
5749 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
5750 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_rsq},
5751 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
5752 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
5753 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
5754 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5755 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5756 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5757 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
5758 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
5759 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
5760 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
5761 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
5762 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
5763 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5764 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
5765 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5766 /* gap */
5767 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5768 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5769 /* gap */
5770 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5771 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5772 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
5773 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5774 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
5775 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
5776 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
5777 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
5778 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
5779 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
5780 /* gap */
5781 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5782 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5783 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5784 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5785 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
5786 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5787 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
5788 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
5789 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5790 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5791 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5792 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5793 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5794 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
5795 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5796 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
5797 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
5798 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
5799 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
5800 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5801 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5802 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
5803 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5804 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5805 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5806 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5807 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5808 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5809 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5810 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5811 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5812 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5813 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5814 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
5815 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
5816 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
5817 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
5818 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5819 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5820 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5821 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
5822 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
5823 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
5824 /* gap */
5825 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5826 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5827 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
5828 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
5829 /* gap */
5830 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5831 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5832 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5833 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5834 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
5835 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
5836 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
5837 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
5838 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
5839 /* gap */
5840 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5841 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
5842 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
5843 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
5844 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
5845 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5846 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
5847 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
5848 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
5849 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5850 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5851 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
5852 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5853 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
5854 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5855 {TGSI_OPCODE_TXQ_LZ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
5856 /* gap */
5857 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5858 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5859 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5860 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5861 /* gap */
5862 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5863 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5864 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5865 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5866 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5867 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5868 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5869 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5870 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
5871 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
5872 /* gap */
5873 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5874 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_f2i},
5875 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
5876 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
5877 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
5878 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
5879 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
5880 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
5881 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
5882 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_f2i},
5883 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
5884 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
5885 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
5886 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
5887 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
5888 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
5889 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
5890 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
5891 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
5892 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
5893 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
5894 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
5895 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
5896 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5897 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5898 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5899 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5900 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5901 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5902 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5903 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5904 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5905 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5906 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5907 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5908 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5909 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5910 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5911 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5912 {TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
5913 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
5914 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5915 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5916 {TGSI_OPCODE_LOAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5917 {TGSI_OPCODE_STORE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5918 {TGSI_OPCODE_MFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5919 {TGSI_OPCODE_LFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5920 {TGSI_OPCODE_SFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5921 {TGSI_OPCODE_BARRIER, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5922 {TGSI_OPCODE_ATOMUADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5923 {TGSI_OPCODE_ATOMXCHG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5924 {TGSI_OPCODE_ATOMCAS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5925 {TGSI_OPCODE_ATOMAND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5926 {TGSI_OPCODE_ATOMOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5927 {TGSI_OPCODE_ATOMXOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5928 {TGSI_OPCODE_ATOMUMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5929 {TGSI_OPCODE_ATOMUMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5930 {TGSI_OPCODE_ATOMIMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5931 {TGSI_OPCODE_ATOMIMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5932 {TGSI_OPCODE_TEX2, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5933 {TGSI_OPCODE_TXB2, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
5934 {TGSI_OPCODE_TXL2, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
5935 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5936 };
5937
5938 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
5939 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
5940 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5941 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
5942 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, cayman_emit_float_instr},
5943 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, cayman_emit_float_instr},
5944 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
5945 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
5946 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
5947 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5948 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5949 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5950 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
5951 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
5952 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
5953 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
5954 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
5955 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
5956 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
5957 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
5958 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5959 /* gap */
5960 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5961 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5962 /* gap */
5963 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5964 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5965 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
5966 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5967 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
5968 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
5969 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, cayman_emit_float_instr},
5970 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, cayman_emit_float_instr},
5971 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, cayman_pow},
5972 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
5973 /* gap */
5974 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5975 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
5976 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5977 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
5978 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, cayman_trig},
5979 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
5980 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
5981 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
5982 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5983 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5984 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5985 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5986 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5987 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
5988 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5989 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
5990 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, cayman_trig},
5991 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
5992 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
5993 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5994 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5995 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
5996 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
5997 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5998 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
5999 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6000 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6001 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6002 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6003 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
6004 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6005 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6006 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6007 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
6008 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
6009 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
6010 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
6011 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6012 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6013 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
6014 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
6015 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
6016 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
6017 /* gap */
6018 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6019 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6020 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
6021 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
6022 /* gap */
6023 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6024 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6025 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6026 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6027 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
6028 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2},
6029 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
6030 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
6031 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
6032 /* gap */
6033 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6034 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
6035 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
6036 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_imod},
6037 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
6038 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6039 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
6040 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
6041 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
6042 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6043 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6044 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
6045 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6046 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
6047 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6048 {TGSI_OPCODE_TXQ_LZ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
6049 /* gap */
6050 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6051 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6052 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6053 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6054 /* gap */
6055 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6056 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6057 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6058 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6059 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6060 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6061 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6062 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6063 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
6064 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
6065 /* gap */
6066 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6067 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2},
6068 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
6069 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
6070 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
6071 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
6072 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
6073 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
6074 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
6075 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
6076 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
6077 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
6078 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
6079 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
6080 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
6081 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
6082 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umod},
6083 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT, cayman_mul_int_instr},
6084 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
6085 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
6086 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
6087 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT, tgsi_op2_swap},
6088 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
6089 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6090 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6091 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6092 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6093 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6094 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6095 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6096 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6097 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6098 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6099 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6100 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6101 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6102 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6103 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6104 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6105 {TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
6106 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
6107 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6108 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6109 {TGSI_OPCODE_LOAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6110 {TGSI_OPCODE_STORE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_MFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6112 {TGSI_OPCODE_LFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6113 {TGSI_OPCODE_SFENCE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6114 {TGSI_OPCODE_BARRIER, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6115 {TGSI_OPCODE_ATOMUADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6116 {TGSI_OPCODE_ATOMXCHG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6117 {TGSI_OPCODE_ATOMCAS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6118 {TGSI_OPCODE_ATOMAND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6119 {TGSI_OPCODE_ATOMOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6120 {TGSI_OPCODE_ATOMXOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6121 {TGSI_OPCODE_ATOMUMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6122 {TGSI_OPCODE_ATOMUMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6123 {TGSI_OPCODE_ATOMIMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6124 {TGSI_OPCODE_ATOMIMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6125 {TGSI_OPCODE_TEX2, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
6126 {TGSI_OPCODE_TXB2, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
6127 {TGSI_OPCODE_TXL2, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
6128 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
6129 };