2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
29 #include "sb/sb_public.h"
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
43 Why CAYMAN got loops for lots of instructions is explained here.
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
63 /* Contents of r0 on entry to various shaders
69 GS - r0.xyw, r1.xyz = per-vertex offsets
75 .w = tess factor base.
77 TES - .x = TessCoord.x
79 - .z = RelPatchID (??)
82 PS - face_gpr.z = SampleMask
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
87 struct r600_pipe_shader
*pipeshader
,
88 union r600_shader_key key
);
90 static void r600_add_gpr_array(struct r600_shader
*ps
, int start_gpr
,
91 int size
, unsigned comp_mask
) {
96 if (ps
->num_arrays
== ps
->max_arrays
) {
98 ps
->arrays
= realloc(ps
->arrays
, ps
->max_arrays
*
99 sizeof(struct r600_shader_array
));
102 int n
= ps
->num_arrays
;
105 ps
->arrays
[n
].comp_mask
= comp_mask
;
106 ps
->arrays
[n
].gpr_start
= start_gpr
;
107 ps
->arrays
[n
].gpr_count
= size
;
110 static void r600_dump_streamout(struct pipe_stream_output_info
*so
)
114 fprintf(stderr
, "STREAMOUT\n");
115 for (i
= 0; i
< so
->num_outputs
; i
++) {
116 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
117 so
->output
[i
].start_component
;
118 fprintf(stderr
, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
120 so
->output
[i
].stream
,
121 so
->output
[i
].output_buffer
,
122 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
123 so
->output
[i
].register_index
,
128 so
->output
[i
].dst_offset
< so
->output
[i
].start_component
? " (will lower)" : "");
132 static int store_shader(struct pipe_context
*ctx
,
133 struct r600_pipe_shader
*shader
)
135 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
138 if (shader
->bo
== NULL
) {
139 shader
->bo
= (struct r600_resource
*)
140 pipe_buffer_create(ctx
->screen
, 0, PIPE_USAGE_IMMUTABLE
, shader
->shader
.bc
.ndw
* 4);
141 if (shader
->bo
== NULL
) {
144 ptr
= r600_buffer_map_sync_with_rings(&rctx
->b
, shader
->bo
, PIPE_TRANSFER_WRITE
);
145 if (R600_BIG_ENDIAN
) {
146 for (i
= 0; i
< shader
->shader
.bc
.ndw
; ++i
) {
147 ptr
[i
] = util_cpu_to_le32(shader
->shader
.bc
.bytecode
[i
]);
150 memcpy(ptr
, shader
->shader
.bc
.bytecode
, shader
->shader
.bc
.ndw
* sizeof(*ptr
));
152 rctx
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
158 int r600_pipe_shader_create(struct pipe_context
*ctx
,
159 struct r600_pipe_shader
*shader
,
160 union r600_shader_key key
)
162 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
163 struct r600_pipe_shader_selector
*sel
= shader
->selector
;
165 bool dump
= r600_can_dump_shader(&rctx
->screen
->b
,
166 tgsi_get_processor_type(sel
->tokens
));
167 unsigned use_sb
= !(rctx
->screen
->b
.debug_flags
& DBG_NO_SB
);
168 unsigned sb_disasm
= use_sb
|| (rctx
->screen
->b
.debug_flags
& DBG_SB_DISASM
);
169 unsigned export_shader
;
171 shader
->shader
.bc
.isa
= rctx
->isa
;
174 fprintf(stderr
, "--------------------------------------------------------------\n");
175 tgsi_dump(sel
->tokens
, 0);
177 if (sel
->so
.num_outputs
) {
178 r600_dump_streamout(&sel
->so
);
181 r
= r600_shader_from_tgsi(rctx
, shader
, key
);
183 R600_ERR("translation from TGSI failed !\n");
186 if (shader
->shader
.processor_type
== PIPE_SHADER_VERTEX
) {
187 /* only disable for vertex shaders in tess paths */
191 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_CTRL
);
192 use_sb
&= (shader
->shader
.processor_type
!= PIPE_SHADER_TESS_EVAL
);
194 /* disable SB for shaders using doubles */
195 use_sb
&= !shader
->shader
.uses_doubles
;
197 use_sb
&= !shader
->shader
.uses_atomics
;
198 use_sb
&= !shader
->shader
.uses_images
;
200 /* Check if the bytecode has already been built. */
201 if (!shader
->shader
.bc
.bytecode
) {
202 r
= r600_bytecode_build(&shader
->shader
.bc
);
204 R600_ERR("building bytecode failed !\n");
209 if (dump
&& !sb_disasm
) {
210 fprintf(stderr
, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader
->shader
.bc
);
212 fprintf(stderr
, "______________________________________________________________\n");
213 } else if ((dump
&& sb_disasm
) || use_sb
) {
214 r
= r600_sb_bytecode_process(rctx
, &shader
->shader
.bc
, &shader
->shader
,
217 R600_ERR("r600_sb_bytecode_process failed !\n");
222 if (shader
->gs_copy_shader
) {
225 r
= r600_sb_bytecode_process(rctx
, &shader
->gs_copy_shader
->shader
.bc
,
226 &shader
->gs_copy_shader
->shader
, dump
, 0);
231 if ((r
= store_shader(ctx
, shader
->gs_copy_shader
)))
235 /* Store the shader in a buffer. */
236 if ((r
= store_shader(ctx
, shader
)))
240 switch (shader
->shader
.processor_type
) {
241 case PIPE_SHADER_TESS_CTRL
:
242 evergreen_update_hs_state(ctx
, shader
);
244 case PIPE_SHADER_TESS_EVAL
:
246 evergreen_update_es_state(ctx
, shader
);
248 evergreen_update_vs_state(ctx
, shader
);
250 case PIPE_SHADER_GEOMETRY
:
251 if (rctx
->b
.chip_class
>= EVERGREEN
) {
252 evergreen_update_gs_state(ctx
, shader
);
253 evergreen_update_vs_state(ctx
, shader
->gs_copy_shader
);
255 r600_update_gs_state(ctx
, shader
);
256 r600_update_vs_state(ctx
, shader
->gs_copy_shader
);
259 case PIPE_SHADER_VERTEX
:
260 export_shader
= key
.vs
.as_es
;
261 if (rctx
->b
.chip_class
>= EVERGREEN
) {
263 evergreen_update_ls_state(ctx
, shader
);
264 else if (key
.vs
.as_es
)
265 evergreen_update_es_state(ctx
, shader
);
267 evergreen_update_vs_state(ctx
, shader
);
270 r600_update_es_state(ctx
, shader
);
272 r600_update_vs_state(ctx
, shader
);
275 case PIPE_SHADER_FRAGMENT
:
276 if (rctx
->b
.chip_class
>= EVERGREEN
) {
277 evergreen_update_ps_state(ctx
, shader
);
279 r600_update_ps_state(ctx
, shader
);
289 r600_pipe_shader_destroy(ctx
, shader
);
293 void r600_pipe_shader_destroy(struct pipe_context
*ctx UNUSED
, struct r600_pipe_shader
*shader
)
295 r600_resource_reference(&shader
->bo
, NULL
);
296 r600_bytecode_clear(&shader
->shader
.bc
);
297 r600_release_command_buffer(&shader
->command_buffer
);
301 * tgsi -> r600 shader
303 struct r600_shader_tgsi_instruction
;
305 struct r600_shader_src
{
312 boolean kc_rel
; /* true if cache bank is indexed */
321 struct r600_shader_ctx
{
322 struct tgsi_shader_info info
;
323 struct tgsi_parse_context parse
;
324 const struct tgsi_token
*tokens
;
326 unsigned file_offset
[TGSI_FILE_COUNT
];
328 const struct r600_shader_tgsi_instruction
*inst_info
;
329 struct r600_bytecode
*bc
;
330 struct r600_shader
*shader
;
331 struct r600_shader_src src
[4];
334 uint32_t max_driver_temp_used
;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators
[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr
;
342 boolean clip_vertex_write
;
344 unsigned edgeflag_output
;
347 int next_ring_offset
;
348 int gs_out_ring_offset
;
350 struct r600_shader
*gs_for_vs
;
351 int gs_export_gpr_tregs
[4];
352 int gs_rotated_input
[2];
353 const struct pipe_stream_output_info
*gs_stream_output_info
;
354 unsigned enabled_stream_buffers_mask
;
355 unsigned tess_input_info
; /* temp with tess input offsets */
356 unsigned tess_output_info
; /* temp with tess input offsets */
357 unsigned thread_id_gpr
; /* temp with thread id calculated for images */
358 bool thread_id_gpr_loaded
;
361 struct r600_shader_tgsi_instruction
{
363 int (*process
)(struct r600_shader_ctx
*ctx
);
366 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so
, int stream
, bool ind
);
367 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[], cm_shader_tgsi_instruction
[];
368 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
369 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
);
370 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
);
371 static int tgsi_else(struct r600_shader_ctx
*ctx
);
372 static int tgsi_endif(struct r600_shader_ctx
*ctx
);
373 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
);
374 static int tgsi_endloop(struct r600_shader_ctx
*ctx
);
375 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
);
376 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
377 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
378 unsigned int dst_reg
);
379 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
380 const struct r600_shader_src
*shader_src
,
382 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
383 unsigned dst_reg
, unsigned mask
);
385 static int tgsi_last_instruction(unsigned writemask
)
389 for (i
= 0; i
< 4; i
++) {
390 if (writemask
& (1 << i
)) {
397 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
399 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
402 if (i
->Instruction
.NumDstRegs
> 1 && i
->Instruction
.Opcode
!= TGSI_OPCODE_DFRACEXP
) {
403 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
407 if (i
->Instruction
.Label
) {
408 R600_ERR("label unsupported\n");
412 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
413 if (i
->Src
[j
].Register
.Dimension
) {
414 switch (i
->Src
[j
].Register
.File
) {
415 case TGSI_FILE_CONSTANT
:
416 case TGSI_FILE_HW_ATOMIC
:
418 case TGSI_FILE_INPUT
:
419 if (ctx
->type
== PIPE_SHADER_GEOMETRY
||
420 ctx
->type
== PIPE_SHADER_TESS_CTRL
||
421 ctx
->type
== PIPE_SHADER_TESS_EVAL
)
423 case TGSI_FILE_OUTPUT
:
424 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
427 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j
,
428 i
->Src
[j
].Register
.File
,
429 i
->Src
[j
].Register
.Dimension
);
434 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
435 if (i
->Dst
[j
].Register
.Dimension
) {
436 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
)
438 R600_ERR("unsupported dst (dimension)\n");
445 int eg_get_interpolator_index(unsigned interpolate
, unsigned location
)
447 if (interpolate
== TGSI_INTERPOLATE_COLOR
||
448 interpolate
== TGSI_INTERPOLATE_LINEAR
||
449 interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
)
451 int is_linear
= interpolate
== TGSI_INTERPOLATE_LINEAR
;
455 case TGSI_INTERPOLATE_LOC_CENTER
:
458 case TGSI_INTERPOLATE_LOC_CENTROID
:
461 case TGSI_INTERPOLATE_LOC_SAMPLE
:
466 return is_linear
* 3 + loc
;
472 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx
*ctx
,
475 int i
= eg_get_interpolator_index(
476 ctx
->shader
->input
[input
].interpolate
,
477 ctx
->shader
->input
[input
].interpolate_location
);
479 ctx
->shader
->input
[input
].ij_index
= ctx
->eg_interpolators
[i
].ij_index
;
482 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
485 struct r600_bytecode_alu alu
;
486 int gpr
= 0, base_chan
= 0;
487 int ij_index
= ctx
->shader
->input
[input
].ij_index
;
489 /* work out gpr and base_chan from index */
491 base_chan
= (2 * (ij_index
% 2)) + 1;
493 for (i
= 0; i
< 8; i
++) {
494 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
497 alu
.op
= ALU_OP2_INTERP_ZW
;
499 alu
.op
= ALU_OP2_INTERP_XY
;
501 if ((i
> 1) && (i
< 6)) {
502 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
506 alu
.dst
.chan
= i
% 4;
508 alu
.src
[0].sel
= gpr
;
509 alu
.src
[0].chan
= (base_chan
- (i
% 2));
511 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
513 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
516 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
523 static int evergreen_interp_flat(struct r600_shader_ctx
*ctx
, int input
)
526 struct r600_bytecode_alu alu
;
528 for (i
= 0; i
< 4; i
++) {
529 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
531 alu
.op
= ALU_OP1_INTERP_LOAD_P0
;
533 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
538 alu
.src
[0].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
543 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
551 * Special export handling in shaders
553 * shader export ARRAY_BASE for EXPORT_POS:
556 * 62, 63 are clip distance vectors
558 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
559 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
560 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
561 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
562 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
563 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
564 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
565 * exclusive from render target index)
566 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
569 * shader export ARRAY_BASE for EXPORT_PIXEL:
571 * 61 computed Z vector
573 * The use of the values exported in the computed Z vector are controlled
574 * by DB_SHADER_CONTROL:
575 * Z_EXPORT_ENABLE - Z as a float in RED
576 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
577 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
578 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
579 * DB_SOURCE_FORMAT - export control restrictions
584 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
585 static int r600_spi_sid(struct r600_shader_io
* io
)
587 int index
, name
= io
->name
;
589 /* These params are handled differently, they don't need
590 * semantic indices, so we'll use 0 for them.
592 if (name
== TGSI_SEMANTIC_POSITION
||
593 name
== TGSI_SEMANTIC_PSIZE
||
594 name
== TGSI_SEMANTIC_EDGEFLAG
||
595 name
== TGSI_SEMANTIC_FACE
||
596 name
== TGSI_SEMANTIC_SAMPLEMASK
)
599 if (name
== TGSI_SEMANTIC_GENERIC
) {
600 /* For generic params simply use sid from tgsi */
603 /* For non-generic params - pack name and sid into 8 bits */
604 index
= 0x80 | (name
<<3) | (io
->sid
);
607 /* Make sure that all really used indices have nonzero value, so
608 * we can just compare it to 0 later instead of comparing the name
609 * with different values to detect special cases. */
616 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
617 int r600_get_lds_unique_index(unsigned semantic_name
, unsigned index
)
619 switch (semantic_name
) {
620 case TGSI_SEMANTIC_POSITION
:
622 case TGSI_SEMANTIC_PSIZE
:
624 case TGSI_SEMANTIC_CLIPDIST
:
627 case TGSI_SEMANTIC_GENERIC
:
629 return 4 + index
- 9;
631 /* same explanation as in the default statement,
632 * the only user hitting this is st/nine.
636 /* patch indices are completely separate and thus start from 0 */
637 case TGSI_SEMANTIC_TESSOUTER
:
639 case TGSI_SEMANTIC_TESSINNER
:
641 case TGSI_SEMANTIC_PATCH
:
645 /* Don't fail here. The result of this function is only used
646 * for LS, TCS, TES, and GS, where legacy GL semantics can't
647 * occur, but this function is called for all vertex shaders
648 * before it's known whether LS will be compiled or not.
654 /* turn input into interpolate on EG */
655 static int evergreen_interp_input(struct r600_shader_ctx
*ctx
, int index
)
659 if (ctx
->shader
->input
[index
].spi_sid
) {
660 ctx
->shader
->input
[index
].lds_pos
= ctx
->shader
->nlds
++;
661 if (ctx
->shader
->input
[index
].interpolate
> 0) {
662 evergreen_interp_assign_ij_index(ctx
, index
);
663 r
= evergreen_interp_alu(ctx
, index
);
665 r
= evergreen_interp_flat(ctx
, index
);
671 static int select_twoside_color(struct r600_shader_ctx
*ctx
, int front
, int back
)
673 struct r600_bytecode_alu alu
;
675 int gpr_front
= ctx
->shader
->input
[front
].gpr
;
676 int gpr_back
= ctx
->shader
->input
[back
].gpr
;
678 for (i
= 0; i
< 4; i
++) {
679 memset(&alu
, 0, sizeof(alu
));
680 alu
.op
= ALU_OP3_CNDGT
;
683 alu
.dst
.sel
= gpr_front
;
684 alu
.src
[0].sel
= ctx
->face_gpr
;
685 alu
.src
[1].sel
= gpr_front
;
686 alu
.src
[2].sel
= gpr_back
;
693 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
700 /* execute a single slot ALU calculation */
701 static int single_alu_op2(struct r600_shader_ctx
*ctx
, int op
,
702 int dst_sel
, int dst_chan
,
703 int src0_sel
, unsigned src0_chan_val
,
704 int src1_sel
, unsigned src1_chan_val
)
706 struct r600_bytecode_alu alu
;
709 if (ctx
->bc
->chip_class
== CAYMAN
&& op
== ALU_OP2_MULLO_INT
) {
710 for (i
= 0; i
< 4; i
++) {
711 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
713 alu
.src
[0].sel
= src0_sel
;
714 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
715 alu
.src
[0].value
= src0_chan_val
;
717 alu
.src
[0].chan
= src0_chan_val
;
718 alu
.src
[1].sel
= src1_sel
;
719 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
720 alu
.src
[1].value
= src1_chan_val
;
722 alu
.src
[1].chan
= src1_chan_val
;
723 alu
.dst
.sel
= dst_sel
;
725 alu
.dst
.write
= i
== dst_chan
;
727 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
734 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
736 alu
.src
[0].sel
= src0_sel
;
737 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
738 alu
.src
[0].value
= src0_chan_val
;
740 alu
.src
[0].chan
= src0_chan_val
;
741 alu
.src
[1].sel
= src1_sel
;
742 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
743 alu
.src
[1].value
= src1_chan_val
;
745 alu
.src
[1].chan
= src1_chan_val
;
746 alu
.dst
.sel
= dst_sel
;
747 alu
.dst
.chan
= dst_chan
;
750 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
756 /* execute a single slot ALU calculation */
757 static int single_alu_op3(struct r600_shader_ctx
*ctx
, int op
,
758 int dst_sel
, int dst_chan
,
759 int src0_sel
, unsigned src0_chan_val
,
760 int src1_sel
, unsigned src1_chan_val
,
761 int src2_sel
, unsigned src2_chan_val
)
763 struct r600_bytecode_alu alu
;
766 /* validate this for other ops */
767 assert(op
== ALU_OP3_MULADD_UINT24
|| op
== ALU_OP3_CNDE_INT
);
768 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
770 alu
.src
[0].sel
= src0_sel
;
771 if (src0_sel
== V_SQ_ALU_SRC_LITERAL
)
772 alu
.src
[0].value
= src0_chan_val
;
774 alu
.src
[0].chan
= src0_chan_val
;
775 alu
.src
[1].sel
= src1_sel
;
776 if (src1_sel
== V_SQ_ALU_SRC_LITERAL
)
777 alu
.src
[1].value
= src1_chan_val
;
779 alu
.src
[1].chan
= src1_chan_val
;
780 alu
.src
[2].sel
= src2_sel
;
781 if (src2_sel
== V_SQ_ALU_SRC_LITERAL
)
782 alu
.src
[2].value
= src2_chan_val
;
784 alu
.src
[2].chan
= src2_chan_val
;
785 alu
.dst
.sel
= dst_sel
;
786 alu
.dst
.chan
= dst_chan
;
789 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
795 /* put it in temp_reg.x */
796 static int get_lds_offset0(struct r600_shader_ctx
*ctx
,
798 int temp_reg
, bool is_patch_var
)
802 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
804 Dimension - patch0_offset (input_vals.z),
805 Non-dim - patch0_data_offset (input_vals.w)
807 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
809 ctx
->tess_output_info
, 0,
811 ctx
->tess_output_info
, is_patch_var
? 3 : 2);
817 static inline int get_address_file_reg(struct r600_shader_ctx
*ctx
, int index
)
819 return index
> 0 ? ctx
->bc
->index_reg
[index
- 1] : ctx
->bc
->ar_reg
;
822 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
824 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
827 static int vs_add_primid_output(struct r600_shader_ctx
*ctx
, int prim_id_sid
)
830 i
= ctx
->shader
->noutput
++;
831 ctx
->shader
->output
[i
].name
= TGSI_SEMANTIC_PRIMID
;
832 ctx
->shader
->output
[i
].sid
= 0;
833 ctx
->shader
->output
[i
].gpr
= 0;
834 ctx
->shader
->output
[i
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
835 ctx
->shader
->output
[i
].write_mask
= 0x4;
836 ctx
->shader
->output
[i
].spi_sid
= prim_id_sid
;
841 static int tgsi_barrier(struct r600_shader_ctx
*ctx
)
843 struct r600_bytecode_alu alu
;
846 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
847 alu
.op
= ctx
->inst_info
->op
;
850 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
856 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
858 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
859 int r
, i
, j
, count
= d
->Range
.Last
- d
->Range
.First
+ 1;
861 switch (d
->Declaration
.File
) {
862 case TGSI_FILE_INPUT
:
863 for (j
= 0; j
< count
; j
++) {
864 i
= ctx
->shader
->ninput
+ j
;
865 assert(i
< ARRAY_SIZE(ctx
->shader
->input
));
866 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
867 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
+ j
;
868 ctx
->shader
->input
[i
].interpolate
= d
->Interp
.Interpolate
;
869 ctx
->shader
->input
[i
].interpolate_location
= d
->Interp
.Location
;
870 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + d
->Range
.First
+ j
;
871 if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
872 ctx
->shader
->input
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->input
[i
]);
873 switch (ctx
->shader
->input
[i
].name
) {
874 case TGSI_SEMANTIC_FACE
:
875 if (ctx
->face_gpr
!= -1)
876 ctx
->shader
->input
[i
].gpr
= ctx
->face_gpr
; /* already allocated by allocate_system_value_inputs */
878 ctx
->face_gpr
= ctx
->shader
->input
[i
].gpr
;
880 case TGSI_SEMANTIC_COLOR
:
883 case TGSI_SEMANTIC_POSITION
:
884 ctx
->fragcoord_input
= i
;
886 case TGSI_SEMANTIC_PRIMID
:
887 /* set this for now */
888 ctx
->shader
->gs_prim_id_input
= true;
889 ctx
->shader
->ps_prim_id_input
= i
;
892 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
893 if ((r
= evergreen_interp_input(ctx
, i
)))
896 } else if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
897 /* FIXME probably skip inputs if they aren't passed in the ring */
898 ctx
->shader
->input
[i
].ring_offset
= ctx
->next_ring_offset
;
899 ctx
->next_ring_offset
+= 16;
900 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_PRIMID
)
901 ctx
->shader
->gs_prim_id_input
= true;
904 ctx
->shader
->ninput
+= count
;
906 case TGSI_FILE_OUTPUT
:
907 for (j
= 0; j
< count
; j
++) {
908 i
= ctx
->shader
->noutput
+ j
;
909 assert(i
< ARRAY_SIZE(ctx
->shader
->output
));
910 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
911 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
+ j
;
912 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + d
->Range
.First
+ j
;
913 ctx
->shader
->output
[i
].interpolate
= d
->Interp
.Interpolate
;
914 ctx
->shader
->output
[i
].write_mask
= d
->Declaration
.UsageMask
;
915 if (ctx
->type
== PIPE_SHADER_VERTEX
||
916 ctx
->type
== PIPE_SHADER_GEOMETRY
||
917 ctx
->type
== PIPE_SHADER_TESS_EVAL
) {
918 ctx
->shader
->output
[i
].spi_sid
= r600_spi_sid(&ctx
->shader
->output
[i
]);
919 switch (d
->Semantic
.Name
) {
920 case TGSI_SEMANTIC_CLIPDIST
:
922 case TGSI_SEMANTIC_PSIZE
:
923 ctx
->shader
->vs_out_misc_write
= 1;
924 ctx
->shader
->vs_out_point_size
= 1;
926 case TGSI_SEMANTIC_EDGEFLAG
:
927 ctx
->shader
->vs_out_misc_write
= 1;
928 ctx
->shader
->vs_out_edgeflag
= 1;
929 ctx
->edgeflag_output
= i
;
931 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
932 ctx
->shader
->vs_out_misc_write
= 1;
933 ctx
->shader
->vs_out_viewport
= 1;
935 case TGSI_SEMANTIC_LAYER
:
936 ctx
->shader
->vs_out_misc_write
= 1;
937 ctx
->shader
->vs_out_layer
= 1;
939 case TGSI_SEMANTIC_CLIPVERTEX
:
940 ctx
->clip_vertex_write
= TRUE
;
944 if (ctx
->type
== PIPE_SHADER_GEOMETRY
) {
945 ctx
->gs_out_ring_offset
+= 16;
947 } else if (ctx
->type
== PIPE_SHADER_FRAGMENT
) {
948 switch (d
->Semantic
.Name
) {
949 case TGSI_SEMANTIC_COLOR
:
950 ctx
->shader
->nr_ps_max_color_exports
++;
955 ctx
->shader
->noutput
+= count
;
957 case TGSI_FILE_TEMPORARY
:
958 if (ctx
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) {
959 if (d
->Array
.ArrayID
) {
960 r600_add_gpr_array(ctx
->shader
,
961 ctx
->file_offset
[TGSI_FILE_TEMPORARY
] +
963 d
->Range
.Last
- d
->Range
.First
+ 1, 0x0F);
968 case TGSI_FILE_CONSTANT
:
969 case TGSI_FILE_SAMPLER
:
970 case TGSI_FILE_SAMPLER_VIEW
:
971 case TGSI_FILE_ADDRESS
:
972 case TGSI_FILE_BUFFER
:
973 case TGSI_FILE_IMAGE
:
976 case TGSI_FILE_HW_ATOMIC
:
977 i
= ctx
->shader
->nhwatomic_ranges
;
978 ctx
->shader
->atomics
[i
].start
= d
->Range
.First
;
979 ctx
->shader
->atomics
[i
].end
= d
->Range
.Last
;
980 ctx
->shader
->atomics
[i
].hw_idx
= ctx
->shader
->atomic_base
+ ctx
->shader
->nhwatomic
;
981 ctx
->shader
->atomics
[i
].array_id
= d
->Array
.ArrayID
;
982 ctx
->shader
->atomics
[i
].buffer_id
= d
->Dim
.Index2D
;
983 ctx
->shader
->nhwatomic_ranges
++;
984 ctx
->shader
->nhwatomic
+= count
;
987 case TGSI_FILE_SYSTEM_VALUE
:
988 if (d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEMASK
||
989 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEID
||
990 d
->Semantic
.Name
== TGSI_SEMANTIC_SAMPLEPOS
) {
991 break; /* Already handled from allocate_system_value_inputs */
992 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INSTANCEID
) {
993 if (!ctx
->native_integers
) {
994 struct r600_bytecode_alu alu
;
995 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
997 alu
.op
= ALU_OP1_INT_TO_FLT
;
1006 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1010 } else if (d
->Semantic
.Name
== TGSI_SEMANTIC_VERTEXID
)
1012 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_INVOCATIONID
)
1014 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
||
1015 d
->Semantic
.Name
== TGSI_SEMANTIC_TESSOUTER
) {
1016 int param
= r600_get_lds_unique_index(d
->Semantic
.Name
, 0);
1017 int dreg
= d
->Semantic
.Name
== TGSI_SEMANTIC_TESSINNER
? 3 : 2;
1018 unsigned temp_reg
= r600_get_temp(ctx
);
1020 r
= get_lds_offset0(ctx
, 2, temp_reg
, true);
1024 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1027 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1031 do_lds_fetch_values(ctx
, temp_reg
, dreg
, 0xf);
1033 else if (d
->Semantic
.Name
== TGSI_SEMANTIC_TESSCOORD
) {
1037 for (i
= 0; i
< 2; i
++) {
1038 struct r600_bytecode_alu alu
;
1039 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1040 alu
.op
= ALU_OP1_MOV
;
1042 alu
.src
[0].chan
= 0 + i
;
1044 alu
.dst
.chan
= 0 + i
;
1046 alu
.last
= (i
== 1) ? 1 : 0;
1047 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1050 /* ADD r1.z, 1.0f, -r0.x */
1051 struct r600_bytecode_alu alu
;
1052 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1053 alu
.op
= ALU_OP2_ADD
;
1054 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1056 alu
.src
[1].chan
= 0;
1062 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1065 /* ADD r1.z, r1.z, -r1.y */
1066 alu
.op
= ALU_OP2_ADD
;
1068 alu
.src
[0].chan
= 2;
1070 alu
.src
[1].chan
= 1;
1076 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1082 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
1088 static int allocate_system_value_inputs(struct r600_shader_ctx
*ctx
, int gpr_offset
)
1090 struct tgsi_parse_context parse
;
1094 unsigned name
, alternate_name
;
1096 { false, &ctx
->face_gpr
, TGSI_SEMANTIC_SAMPLEMASK
, ~0u }, /* lives in Front Face GPR.z */
1098 { false, &ctx
->fixed_pt_position_gpr
, TGSI_SEMANTIC_SAMPLEID
, TGSI_SEMANTIC_SAMPLEPOS
} /* SAMPLEID is in Fixed Point Position GPR.w */
1103 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1107 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1108 while (!tgsi_parse_end_of_tokens(&parse
)) {
1109 tgsi_parse_token(&parse
);
1111 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1112 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1113 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1114 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1115 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1117 int interpolate
, location
, k
;
1119 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1120 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1121 inputs
[1].enabled
= true; /* needs SAMPLEID */
1122 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1123 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1124 /* Needs sample positions, currently those are always available */
1126 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1129 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1130 k
= eg_get_interpolator_index(interpolate
, location
);
1132 ctx
->eg_interpolators
[k
].enabled
= true;
1134 } else if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_DECLARATION
) {
1135 struct tgsi_full_declaration
*d
= &parse
.FullToken
.FullDeclaration
;
1136 if (d
->Declaration
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1137 for (k
= 0; k
< ARRAY_SIZE(inputs
); k
++) {
1138 if (d
->Semantic
.Name
== inputs
[k
].name
||
1139 d
->Semantic
.Name
== inputs
[k
].alternate_name
) {
1140 inputs
[k
].enabled
= true;
1147 tgsi_parse_free(&parse
);
1149 for (i
= 0; i
< ARRAY_SIZE(inputs
); i
++) {
1150 boolean enabled
= inputs
[i
].enabled
;
1151 int *reg
= inputs
[i
].reg
;
1152 unsigned name
= inputs
[i
].name
;
1155 int gpr
= gpr_offset
+ num_regs
++;
1156 ctx
->shader
->nsys_inputs
++;
1158 // add to inputs, allocate a gpr
1159 k
= ctx
->shader
->ninput
++;
1160 ctx
->shader
->input
[k
].name
= name
;
1161 ctx
->shader
->input
[k
].sid
= 0;
1162 ctx
->shader
->input
[k
].interpolate
= TGSI_INTERPOLATE_CONSTANT
;
1163 ctx
->shader
->input
[k
].interpolate_location
= TGSI_INTERPOLATE_LOC_CENTER
;
1164 *reg
= ctx
->shader
->input
[k
].gpr
= gpr
;
1168 return gpr_offset
+ num_regs
;
1172 * for evergreen we need to scan the shader to find the number of GPRs we need to
1173 * reserve for interpolation and system values
1175 * we need to know if we are going to emit
1176 * any sample or centroid inputs
1177 * if perspective and linear are required
1179 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
1183 struct tgsi_parse_context parse
;
1185 memset(&ctx
->eg_interpolators
, 0, sizeof(ctx
->eg_interpolators
));
1187 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
1189 /* skip position/face/mask/sampleid */
1190 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
1191 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
||
1192 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEMASK
||
1193 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_SAMPLEID
)
1196 k
= eg_get_interpolator_index(
1197 ctx
->info
.input_interpolate
[i
],
1198 ctx
->info
.input_interpolate_loc
[i
]);
1200 ctx
->eg_interpolators
[k
].enabled
= TRUE
;
1203 if (tgsi_parse_init(&parse
, ctx
->tokens
) != TGSI_PARSE_OK
) {
1207 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1208 while (!tgsi_parse_end_of_tokens(&parse
)) {
1209 tgsi_parse_token(&parse
);
1211 if (parse
.FullToken
.Token
.Type
== TGSI_TOKEN_TYPE_INSTRUCTION
) {
1212 const struct tgsi_full_instruction
*inst
= &parse
.FullToken
.FullInstruction
;
1213 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
||
1214 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
1215 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_CENTROID
)
1217 int interpolate
, location
, k
;
1219 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
1220 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1221 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
1222 location
= TGSI_INTERPOLATE_LOC_CENTER
;
1224 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
1227 interpolate
= ctx
->info
.input_interpolate
[inst
->Src
[0].Register
.Index
];
1228 k
= eg_get_interpolator_index(interpolate
, location
);
1230 ctx
->eg_interpolators
[k
].enabled
= true;
1235 tgsi_parse_free(&parse
);
1237 /* assign gpr to each interpolator according to priority */
1239 for (i
= 0; i
< ARRAY_SIZE(ctx
->eg_interpolators
); i
++) {
1240 if (ctx
->eg_interpolators
[i
].enabled
) {
1241 ctx
->eg_interpolators
[i
].ij_index
= num_baryc
;
1246 /* XXX PULL MODEL and LINE STIPPLE */
1248 num_baryc
= (num_baryc
+ 1) >> 1;
1249 return allocate_system_value_inputs(ctx
, num_baryc
);
1252 /* sample_id_sel == NULL means fetch for current sample */
1253 static int load_sample_position(struct r600_shader_ctx
*ctx
, struct r600_shader_src
*sample_id
, int chan_sel
)
1255 struct r600_bytecode_vtx vtx
;
1258 assert(ctx
->fixed_pt_position_gpr
!= -1);
1260 t1
= r600_get_temp(ctx
);
1262 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
1263 vtx
.op
= FETCH_OP_VFETCH
;
1264 vtx
.buffer_id
= R600_BUFFER_INFO_CONST_BUFFER
;
1265 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1266 if (sample_id
== NULL
) {
1267 vtx
.src_gpr
= ctx
->fixed_pt_position_gpr
; // SAMPLEID is in .w;
1271 struct r600_bytecode_alu alu
;
1273 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1274 alu
.op
= ALU_OP1_MOV
;
1275 r600_bytecode_src(&alu
.src
[0], sample_id
, chan_sel
);
1279 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1286 vtx
.mega_fetch_count
= 16;
1292 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1293 vtx
.num_format_all
= 2;
1294 vtx
.format_comp_all
= 1;
1295 vtx
.use_const_fields
= 0;
1296 vtx
.offset
= 1; // first element is size of buffer
1297 vtx
.endian
= r600_endian_swap(32);
1298 vtx
.srf_mode_all
= 1; /* SRF_MODE_NO_ZERO */
1300 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
1307 static void tgsi_src(struct r600_shader_ctx
*ctx
,
1308 const struct tgsi_full_src_register
*tgsi_src
,
1309 struct r600_shader_src
*r600_src
)
1311 memset(r600_src
, 0, sizeof(*r600_src
));
1312 r600_src
->swizzle
[0] = tgsi_src
->Register
.SwizzleX
;
1313 r600_src
->swizzle
[1] = tgsi_src
->Register
.SwizzleY
;
1314 r600_src
->swizzle
[2] = tgsi_src
->Register
.SwizzleZ
;
1315 r600_src
->swizzle
[3] = tgsi_src
->Register
.SwizzleW
;
1316 r600_src
->neg
= tgsi_src
->Register
.Negate
;
1317 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
1319 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
1321 if ((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
1322 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
1323 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
1325 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
1326 r600_bytecode_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
, r600_src
->abs
);
1327 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
1330 index
= tgsi_src
->Register
.Index
;
1331 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
1332 memcpy(r600_src
->value
, ctx
->literals
+ index
* 4, sizeof(r600_src
->value
));
1333 } else if (tgsi_src
->Register
.File
== TGSI_FILE_SYSTEM_VALUE
) {
1334 if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEMASK
) {
1335 r600_src
->swizzle
[0] = 2; // Z value
1336 r600_src
->swizzle
[1] = 2;
1337 r600_src
->swizzle
[2] = 2;
1338 r600_src
->swizzle
[3] = 2;
1339 r600_src
->sel
= ctx
->face_gpr
;
1340 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEID
) {
1341 r600_src
->swizzle
[0] = 3; // W value
1342 r600_src
->swizzle
[1] = 3;
1343 r600_src
->swizzle
[2] = 3;
1344 r600_src
->swizzle
[3] = 3;
1345 r600_src
->sel
= ctx
->fixed_pt_position_gpr
;
1346 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_SAMPLEPOS
) {
1347 r600_src
->swizzle
[0] = 0;
1348 r600_src
->swizzle
[1] = 1;
1349 r600_src
->swizzle
[2] = 4;
1350 r600_src
->swizzle
[3] = 4;
1351 r600_src
->sel
= load_sample_position(ctx
, NULL
, -1);
1352 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INSTANCEID
) {
1353 r600_src
->swizzle
[0] = 3;
1354 r600_src
->swizzle
[1] = 3;
1355 r600_src
->swizzle
[2] = 3;
1356 r600_src
->swizzle
[3] = 3;
1358 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTEXID
) {
1359 r600_src
->swizzle
[0] = 0;
1360 r600_src
->swizzle
[1] = 0;
1361 r600_src
->swizzle
[2] = 0;
1362 r600_src
->swizzle
[3] = 0;
1364 } else if (ctx
->type
!= PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1365 r600_src
->swizzle
[0] = 3;
1366 r600_src
->swizzle
[1] = 3;
1367 r600_src
->swizzle
[2] = 3;
1368 r600_src
->swizzle
[3] = 3;
1370 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_INVOCATIONID
) {
1371 r600_src
->swizzle
[0] = 2;
1372 r600_src
->swizzle
[1] = 2;
1373 r600_src
->swizzle
[2] = 2;
1374 r600_src
->swizzle
[3] = 2;
1376 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSCOORD
) {
1378 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSINNER
) {
1380 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_TESSOUTER
) {
1382 } else if (ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_VERTICESIN
) {
1383 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
1384 r600_src
->sel
= ctx
->tess_input_info
;
1385 r600_src
->swizzle
[0] = 2;
1386 r600_src
->swizzle
[1] = 2;
1387 r600_src
->swizzle
[2] = 2;
1388 r600_src
->swizzle
[3] = 2;
1390 r600_src
->sel
= ctx
->tess_input_info
;
1391 r600_src
->swizzle
[0] = 3;
1392 r600_src
->swizzle
[1] = 3;
1393 r600_src
->swizzle
[2] = 3;
1394 r600_src
->swizzle
[3] = 3;
1396 } else if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1398 r600_src
->swizzle
[0] = 0;
1399 r600_src
->swizzle
[1] = 0;
1400 r600_src
->swizzle
[2] = 0;
1401 r600_src
->swizzle
[3] = 0;
1402 } else if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& ctx
->info
.system_value_semantic_name
[tgsi_src
->Register
.Index
] == TGSI_SEMANTIC_PRIMID
) {
1404 r600_src
->swizzle
[0] = 3;
1405 r600_src
->swizzle
[1] = 3;
1406 r600_src
->swizzle
[2] = 3;
1407 r600_src
->swizzle
[3] = 3;
1410 if (tgsi_src
->Register
.Indirect
)
1411 r600_src
->rel
= V_SQ_REL_RELATIVE
;
1412 r600_src
->sel
= tgsi_src
->Register
.Index
;
1413 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
1415 if (tgsi_src
->Register
.File
== TGSI_FILE_CONSTANT
) {
1416 if (tgsi_src
->Register
.Dimension
) {
1417 r600_src
->kc_bank
= tgsi_src
->Dimension
.Index
;
1418 if (tgsi_src
->Dimension
.Indirect
) {
1419 r600_src
->kc_rel
= 1;
1425 static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx
,
1426 unsigned int cb_idx
, unsigned cb_rel
, unsigned int offset
, unsigned ar_chan
,
1427 unsigned int dst_reg
)
1429 struct r600_bytecode_vtx vtx
;
1430 unsigned int ar_reg
;
1434 struct r600_bytecode_alu alu
;
1436 memset(&alu
, 0, sizeof(alu
));
1438 alu
.op
= ALU_OP2_ADD_INT
;
1439 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
1440 alu
.src
[0].chan
= ar_chan
;
1442 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1443 alu
.src
[1].value
= offset
;
1445 alu
.dst
.sel
= dst_reg
;
1446 alu
.dst
.chan
= ar_chan
;
1450 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
1455 ar_reg
= ctx
->bc
->ar_reg
;
1458 memset(&vtx
, 0, sizeof(vtx
));
1459 vtx
.buffer_id
= cb_idx
;
1460 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1461 vtx
.src_gpr
= ar_reg
;
1462 vtx
.src_sel_x
= ar_chan
;
1463 vtx
.mega_fetch_count
= 16;
1464 vtx
.dst_gpr
= dst_reg
;
1465 vtx
.dst_sel_x
= 0; /* SEL_X */
1466 vtx
.dst_sel_y
= 1; /* SEL_Y */
1467 vtx
.dst_sel_z
= 2; /* SEL_Z */
1468 vtx
.dst_sel_w
= 3; /* SEL_W */
1469 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1470 vtx
.num_format_all
= 2; /* NUM_FORMAT_SCALED */
1471 vtx
.format_comp_all
= 1; /* FORMAT_COMP_SIGNED */
1472 vtx
.endian
= r600_endian_swap(32);
1473 vtx
.buffer_index_mode
= cb_rel
; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1475 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1481 static int fetch_gs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1483 struct r600_bytecode_vtx vtx
;
1485 unsigned index
= src
->Register
.Index
;
1486 unsigned vtx_id
= src
->Dimension
.Index
;
1487 int offset_reg
= ctx
->gs_rotated_input
[vtx_id
/ 3];
1488 int offset_chan
= vtx_id
% 3;
1491 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1492 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1494 if (offset_reg
== ctx
->gs_rotated_input
[0] && offset_chan
== 2)
1497 if (src
->Dimension
.Indirect
|| src
->Register
.Indirect
)
1498 t2
= r600_get_temp(ctx
);
1500 if (src
->Dimension
.Indirect
) {
1502 struct r600_bytecode_alu alu
;
1505 addr_reg
= get_address_file_reg(ctx
, src
->DimIndirect
.Index
);
1506 if (src
->DimIndirect
.Index
> 0) {
1507 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
1515 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1516 at least this is what fglrx seems to do. */
1517 for (i
= 0; i
< 3; i
++) {
1518 treg
[i
] = r600_get_temp(ctx
);
1520 r600_add_gpr_array(ctx
->shader
, treg
[0], 3, 0x0F);
1522 for (i
= 0; i
< 3; i
++) {
1523 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1524 alu
.op
= ALU_OP1_MOV
;
1525 alu
.src
[0].sel
= ctx
->gs_rotated_input
[0];
1526 alu
.src
[0].chan
= i
== 2 ? 3 : i
;
1527 alu
.dst
.sel
= treg
[i
];
1531 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1535 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1536 alu
.op
= ALU_OP1_MOV
;
1537 alu
.src
[0].sel
= treg
[0];
1542 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1549 if (src
->Register
.Indirect
) {
1551 unsigned first
= ctx
->info
.input_array_first
[src
->Indirect
.ArrayID
];
1553 addr_reg
= get_address_file_reg(ctx
, src
->Indirect
.Index
);
1555 /* pull the value from index_reg */
1556 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1559 V_SQ_ALU_SRC_LITERAL
, first
);
1562 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1565 V_SQ_ALU_SRC_LITERAL
, 4,
1566 offset_reg
, offset_chan
);
1571 index
= src
->Register
.Index
- first
;
1574 memset(&vtx
, 0, sizeof(vtx
));
1575 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
1576 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
1577 vtx
.src_gpr
= offset_reg
;
1578 vtx
.src_sel_x
= offset_chan
;
1579 vtx
.offset
= index
* 16; /*bytes*/
1580 vtx
.mega_fetch_count
= 16;
1581 vtx
.dst_gpr
= dst_reg
;
1582 vtx
.dst_sel_x
= 0; /* SEL_X */
1583 vtx
.dst_sel_y
= 1; /* SEL_Y */
1584 vtx
.dst_sel_z
= 2; /* SEL_Z */
1585 vtx
.dst_sel_w
= 3; /* SEL_W */
1586 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
1587 vtx
.use_const_fields
= 1;
1589 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
1592 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
1598 static int tgsi_split_gs_inputs(struct r600_shader_ctx
*ctx
)
1600 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1603 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1604 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1606 if (src
->Register
.File
== TGSI_FILE_INPUT
) {
1607 if (ctx
->shader
->input
[src
->Register
.Index
].name
== TGSI_SEMANTIC_PRIMID
) {
1608 /* primitive id is in R0.z */
1609 ctx
->src
[i
].sel
= 0;
1610 ctx
->src
[i
].swizzle
[0] = 2;
1613 if (src
->Register
.File
== TGSI_FILE_INPUT
&& src
->Register
.Dimension
) {
1614 int treg
= r600_get_temp(ctx
);
1616 fetch_gs_input(ctx
, src
, treg
);
1617 ctx
->src
[i
].sel
= treg
;
1618 ctx
->src
[i
].rel
= 0;
1625 /* Tessellation shaders pass outputs to the next shader using LDS.
1627 * LS outputs = TCS(HS) inputs
1628 * TCS(HS) outputs = TES(DS) inputs
1630 * The LDS layout is:
1631 * - TCS inputs for patch 0
1632 * - TCS inputs for patch 1
1633 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1635 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1636 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1637 * - TCS outputs for patch 1
1638 * - Per-patch TCS outputs for patch 1
1639 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1640 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1643 * All three shaders VS(LS), TCS, TES share the same LDS space.
1645 /* this will return with the dw address in temp_reg.x */
1646 static int r600_get_byte_address(struct r600_shader_ctx
*ctx
, int temp_reg
,
1647 const struct tgsi_full_dst_register
*dst
,
1648 const struct tgsi_full_src_register
*src
,
1649 int stride_bytes_reg
, int stride_bytes_chan
)
1651 struct tgsi_full_dst_register reg
;
1652 ubyte
*name
, *index
, *array_first
;
1655 struct tgsi_shader_info
*info
= &ctx
->info
;
1656 /* Set the register description. The address computation is the same
1657 * for sources and destinations. */
1659 reg
.Register
.File
= src
->Register
.File
;
1660 reg
.Register
.Index
= src
->Register
.Index
;
1661 reg
.Register
.Indirect
= src
->Register
.Indirect
;
1662 reg
.Register
.Dimension
= src
->Register
.Dimension
;
1663 reg
.Indirect
= src
->Indirect
;
1664 reg
.Dimension
= src
->Dimension
;
1665 reg
.DimIndirect
= src
->DimIndirect
;
1669 /* If the register is 2-dimensional (e.g. an array of vertices
1670 * in a primitive), calculate the base address of the vertex. */
1671 if (reg
.Register
.Dimension
) {
1673 if (reg
.Dimension
.Indirect
) {
1675 assert (reg
.DimIndirect
.File
== TGSI_FILE_ADDRESS
);
1677 addr_reg
= get_address_file_reg(ctx
, reg
.DimIndirect
.Index
);
1678 /* pull the value from index_reg */
1682 sel
= V_SQ_ALU_SRC_LITERAL
;
1683 chan
= reg
.Dimension
.Index
;
1686 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1688 stride_bytes_reg
, stride_bytes_chan
,
1695 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
1696 name
= info
->input_semantic_name
;
1697 index
= info
->input_semantic_index
;
1698 array_first
= info
->input_array_first
;
1699 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
1700 name
= info
->output_semantic_name
;
1701 index
= info
->output_semantic_index
;
1702 array_first
= info
->output_array_first
;
1707 if (reg
.Register
.Indirect
) {
1710 /* Add the relative address of the element. */
1711 if (reg
.Indirect
.ArrayID
)
1712 first
= array_first
[reg
.Indirect
.ArrayID
];
1714 first
= reg
.Register
.Index
;
1716 addr_reg
= get_address_file_reg(ctx
, reg
.Indirect
.Index
);
1718 /* pull the value from index_reg */
1719 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
1721 V_SQ_ALU_SRC_LITERAL
, 16,
1727 param
= r600_get_lds_unique_index(name
[first
],
1731 param
= r600_get_lds_unique_index(name
[reg
.Register
.Index
],
1732 index
[reg
.Register
.Index
]);
1735 /* add to base_addr - passed in temp_reg.x */
1737 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1740 V_SQ_ALU_SRC_LITERAL
, param
* 16);
1748 static int do_lds_fetch_values(struct r600_shader_ctx
*ctx
, unsigned temp_reg
,
1749 unsigned dst_reg
, unsigned mask
)
1751 struct r600_bytecode_alu alu
;
1754 if ((ctx
->bc
->cf_last
->ndw
>>1) >= 0x60)
1755 ctx
->bc
->force_add_cf
= 1;
1757 lasti
= tgsi_last_instruction(mask
);
1758 for (i
= 1; i
<= lasti
; i
++) {
1759 if (!(mask
& (1 << i
)))
1762 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
1765 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
1769 for (i
= 0; i
<= lasti
; i
++) {
1770 if (!(mask
& (1 << i
)))
1773 /* emit an LDS_READ_RET */
1774 memset(&alu
, 0, sizeof(alu
));
1775 alu
.op
= LDS_OP1_LDS_READ_RET
;
1776 alu
.src
[0].sel
= temp_reg
;
1777 alu
.src
[0].chan
= i
;
1778 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1779 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
1781 alu
.is_lds_idx_op
= true;
1783 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1787 for (i
= 0; i
<= lasti
; i
++) {
1788 if (!(mask
& (1 << i
)))
1791 /* then read from LDS_OQ_A_POP */
1792 memset(&alu
, 0, sizeof(alu
));
1794 alu
.op
= ALU_OP1_MOV
;
1795 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_LDS_OQ_A_POP
;
1796 alu
.src
[0].chan
= 0;
1797 alu
.dst
.sel
= dst_reg
;
1801 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1808 static int fetch_mask(struct tgsi_src_register
*reg
)
1811 mask
|= 1 << reg
->SwizzleX
;
1812 mask
|= 1 << reg
->SwizzleY
;
1813 mask
|= 1 << reg
->SwizzleZ
;
1814 mask
|= 1 << reg
->SwizzleW
;
1818 static int fetch_tes_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1821 unsigned temp_reg
= r600_get_temp(ctx
);
1823 r
= get_lds_offset0(ctx
, 2, temp_reg
,
1824 src
->Register
.Dimension
? false : true);
1828 /* the base address is now in temp.x */
1829 r
= r600_get_byte_address(ctx
, temp_reg
,
1830 NULL
, src
, ctx
->tess_output_info
, 1);
1834 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
, fetch_mask(&src
->Register
));
1840 static int fetch_tcs_input(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1843 unsigned temp_reg
= r600_get_temp(ctx
);
1845 /* t.x = ips * r0.y */
1846 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
1848 ctx
->tess_input_info
, 0,
1854 /* the base address is now in temp.x */
1855 r
= r600_get_byte_address(ctx
, temp_reg
,
1856 NULL
, src
, ctx
->tess_input_info
, 1);
1860 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
, fetch_mask(&src
->Register
));
1866 static int fetch_tcs_output(struct r600_shader_ctx
*ctx
, struct tgsi_full_src_register
*src
, unsigned int dst_reg
)
1869 unsigned temp_reg
= r600_get_temp(ctx
);
1871 r
= get_lds_offset0(ctx
, 1, temp_reg
,
1872 src
->Register
.Dimension
? false : true);
1875 /* the base address is now in temp.x */
1876 r
= r600_get_byte_address(ctx
, temp_reg
,
1878 ctx
->tess_output_info
, 1);
1882 r
= do_lds_fetch_values(ctx
, temp_reg
, dst_reg
, fetch_mask(&src
->Register
));
1888 static int tgsi_split_lds_inputs(struct r600_shader_ctx
*ctx
)
1890 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1893 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1894 struct tgsi_full_src_register
*src
= &inst
->Src
[i
];
1896 if (ctx
->type
== PIPE_SHADER_TESS_EVAL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1897 int treg
= r600_get_temp(ctx
);
1898 fetch_tes_input(ctx
, src
, treg
);
1899 ctx
->src
[i
].sel
= treg
;
1900 ctx
->src
[i
].rel
= 0;
1902 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_INPUT
) {
1903 int treg
= r600_get_temp(ctx
);
1904 fetch_tcs_input(ctx
, src
, treg
);
1905 ctx
->src
[i
].sel
= treg
;
1906 ctx
->src
[i
].rel
= 0;
1908 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
&& src
->Register
.File
== TGSI_FILE_OUTPUT
) {
1909 int treg
= r600_get_temp(ctx
);
1910 fetch_tcs_output(ctx
, src
, treg
);
1911 ctx
->src
[i
].sel
= treg
;
1912 ctx
->src
[i
].rel
= 0;
1918 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
)
1920 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1921 struct r600_bytecode_alu alu
;
1922 int i
, j
, k
, nconst
, r
;
1924 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1925 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
1928 tgsi_src(ctx
, &inst
->Src
[i
], &ctx
->src
[i
]);
1930 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1931 if (inst
->Src
[i
].Register
.File
!= TGSI_FILE_CONSTANT
) {
1935 if (ctx
->src
[i
].rel
) {
1936 int chan
= inst
->Src
[i
].Indirect
.Swizzle
;
1937 int treg
= r600_get_temp(ctx
);
1938 if ((r
= tgsi_fetch_rel_const(ctx
, ctx
->src
[i
].kc_bank
, ctx
->src
[i
].kc_rel
, ctx
->src
[i
].sel
- 512, chan
, treg
)))
1941 ctx
->src
[i
].kc_bank
= 0;
1942 ctx
->src
[i
].kc_rel
= 0;
1943 ctx
->src
[i
].sel
= treg
;
1944 ctx
->src
[i
].rel
= 0;
1947 int treg
= r600_get_temp(ctx
);
1948 for (k
= 0; k
< 4; k
++) {
1949 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1950 alu
.op
= ALU_OP1_MOV
;
1951 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1952 alu
.src
[0].chan
= k
;
1953 alu
.src
[0].rel
= ctx
->src
[i
].rel
;
1954 alu
.src
[0].kc_bank
= ctx
->src
[i
].kc_bank
;
1955 alu
.src
[0].kc_rel
= ctx
->src
[i
].kc_rel
;
1961 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
1965 ctx
->src
[i
].sel
= treg
;
1973 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1974 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
)
1976 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1977 struct r600_bytecode_alu alu
;
1978 int i
, j
, k
, nliteral
, r
;
1980 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1981 if (ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1985 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1986 if (j
> 0 && ctx
->src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
1987 int treg
= r600_get_temp(ctx
);
1988 for (k
= 0; k
< 4; k
++) {
1989 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
1990 alu
.op
= ALU_OP1_MOV
;
1991 alu
.src
[0].sel
= ctx
->src
[i
].sel
;
1992 alu
.src
[0].chan
= k
;
1993 alu
.src
[0].value
= ctx
->src
[i
].value
[k
];
1999 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2003 ctx
->src
[i
].sel
= treg
;
2010 static int process_twoside_color_inputs(struct r600_shader_ctx
*ctx
)
2012 int i
, r
, count
= ctx
->shader
->ninput
;
2014 for (i
= 0; i
< count
; i
++) {
2015 if (ctx
->shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
2016 r
= select_twoside_color(ctx
, i
, ctx
->shader
->input
[i
].back_color_input
);
2024 static int emit_streamout(struct r600_shader_ctx
*ctx
, struct pipe_stream_output_info
*so
,
2025 int stream
, unsigned *stream_item_size UNUSED
)
2027 unsigned so_gpr
[PIPE_MAX_SHADER_OUTPUTS
];
2028 unsigned start_comp
[PIPE_MAX_SHADER_OUTPUTS
];
2032 /* Sanity checking. */
2033 if (so
->num_outputs
> PIPE_MAX_SO_OUTPUTS
) {
2034 R600_ERR("Too many stream outputs: %d\n", so
->num_outputs
);
2038 for (i
= 0; i
< so
->num_outputs
; i
++) {
2039 if (so
->output
[i
].output_buffer
>= 4) {
2040 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2041 so
->output
[i
].output_buffer
);
2047 /* Initialize locations where the outputs are stored. */
2048 for (i
= 0; i
< so
->num_outputs
; i
++) {
2050 so_gpr
[i
] = ctx
->shader
->output
[so
->output
[i
].register_index
].gpr
;
2051 start_comp
[i
] = so
->output
[i
].start_component
;
2052 /* Lower outputs with dst_offset < start_component.
2054 * We can only output 4D vectors with a write mask, e.g. we can
2055 * only output the W component at offset 3, etc. If we want
2056 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2057 * to move it to X and output X. */
2058 if (so
->output
[i
].dst_offset
< so
->output
[i
].start_component
) {
2059 unsigned tmp
= r600_get_temp(ctx
);
2061 for (j
= 0; j
< so
->output
[i
].num_components
; j
++) {
2062 struct r600_bytecode_alu alu
;
2063 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2064 alu
.op
= ALU_OP1_MOV
;
2065 alu
.src
[0].sel
= so_gpr
[i
];
2066 alu
.src
[0].chan
= so
->output
[i
].start_component
+ j
;
2071 if (j
== so
->output
[i
].num_components
- 1)
2073 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2082 /* Write outputs to buffers. */
2083 for (i
= 0; i
< so
->num_outputs
; i
++) {
2084 struct r600_bytecode_output output
;
2086 if (stream
!= -1 && stream
!= so
->output
[i
].output_buffer
)
2089 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2090 output
.gpr
= so_gpr
[i
];
2091 output
.elem_size
= so
->output
[i
].num_components
- 1;
2092 if (output
.elem_size
== 2)
2093 output
.elem_size
= 3; // 3 not supported, write 4 with junk at end
2094 output
.array_base
= so
->output
[i
].dst_offset
- start_comp
[i
];
2095 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2096 output
.burst_count
= 1;
2097 /* array_size is an upper limit for the burst_count
2098 * with MEM_STREAM instructions */
2099 output
.array_size
= 0xFFF;
2100 output
.comp_mask
= ((1 << so
->output
[i
].num_components
) - 1) << start_comp
[i
];
2102 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
2103 switch (so
->output
[i
].output_buffer
) {
2105 output
.op
= CF_OP_MEM_STREAM0_BUF0
;
2108 output
.op
= CF_OP_MEM_STREAM0_BUF1
;
2111 output
.op
= CF_OP_MEM_STREAM0_BUF2
;
2114 output
.op
= CF_OP_MEM_STREAM0_BUF3
;
2117 output
.op
+= so
->output
[i
].stream
* 4;
2118 assert(output
.op
>= CF_OP_MEM_STREAM0_BUF0
&& output
.op
<= CF_OP_MEM_STREAM3_BUF3
);
2119 ctx
->enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << so
->output
[i
].stream
* 4;
2121 switch (so
->output
[i
].output_buffer
) {
2123 output
.op
= CF_OP_MEM_STREAM0
;
2126 output
.op
= CF_OP_MEM_STREAM1
;
2129 output
.op
= CF_OP_MEM_STREAM2
;
2132 output
.op
= CF_OP_MEM_STREAM3
;
2135 ctx
->enabled_stream_buffers_mask
|= 1 << so
->output
[i
].output_buffer
;
2137 r
= r600_bytecode_add_output(ctx
->bc
, &output
);
2146 static void convert_edgeflag_to_int(struct r600_shader_ctx
*ctx
)
2148 struct r600_bytecode_alu alu
;
2151 if (!ctx
->shader
->vs_out_edgeflag
)
2154 reg
= ctx
->shader
->output
[ctx
->edgeflag_output
].gpr
;
2156 /* clamp(x, 0, 1) */
2157 memset(&alu
, 0, sizeof(alu
));
2158 alu
.op
= ALU_OP1_MOV
;
2159 alu
.src
[0].sel
= reg
;
2164 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2166 memset(&alu
, 0, sizeof(alu
));
2167 alu
.op
= ALU_OP1_FLT_TO_INT
;
2168 alu
.src
[0].sel
= reg
;
2172 r600_bytecode_add_alu(ctx
->bc
, &alu
);
2175 static int generate_gs_copy_shader(struct r600_context
*rctx
,
2176 struct r600_pipe_shader
*gs
,
2177 struct pipe_stream_output_info
*so
)
2179 struct r600_shader_ctx ctx
= {};
2180 struct r600_shader
*gs_shader
= &gs
->shader
;
2181 struct r600_pipe_shader
*cshader
;
2182 unsigned ocnt
= gs_shader
->noutput
;
2183 struct r600_bytecode_alu alu
;
2184 struct r600_bytecode_vtx vtx
;
2185 struct r600_bytecode_output output
;
2186 struct r600_bytecode_cf
*cf_jump
, *cf_pop
,
2187 *last_exp_pos
= NULL
, *last_exp_param
= NULL
;
2188 int next_clip_pos
= 61, next_param
= 0;
2191 bool only_ring_0
= true;
2192 cshader
= calloc(1, sizeof(struct r600_pipe_shader
));
2196 memcpy(cshader
->shader
.output
, gs_shader
->output
, ocnt
*
2197 sizeof(struct r600_shader_io
));
2199 cshader
->shader
.noutput
= ocnt
;
2201 ctx
.shader
= &cshader
->shader
;
2202 ctx
.bc
= &ctx
.shader
->bc
;
2203 ctx
.type
= ctx
.bc
->type
= PIPE_SHADER_VERTEX
;
2205 r600_bytecode_init(ctx
.bc
, rctx
->b
.chip_class
, rctx
->b
.family
,
2206 rctx
->screen
->has_compressed_msaa_texturing
);
2208 ctx
.bc
->isa
= rctx
->isa
;
2211 memset(cshader
->shader
.ring_item_sizes
, 0, sizeof(cshader
->shader
.ring_item_sizes
));
2213 /* R0.x = R0.x & 0x3fffffff */
2214 memset(&alu
, 0, sizeof(alu
));
2215 alu
.op
= ALU_OP2_AND_INT
;
2216 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2217 alu
.src
[1].value
= 0x3fffffff;
2219 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2221 /* R0.y = R0.x >> 30 */
2222 memset(&alu
, 0, sizeof(alu
));
2223 alu
.op
= ALU_OP2_LSHR_INT
;
2224 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2225 alu
.src
[1].value
= 0x1e;
2229 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2231 /* fetch vertex data from GSVS ring */
2232 for (i
= 0; i
< ocnt
; ++i
) {
2233 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2236 out
->ring_offset
= i
* 16;
2238 memset(&vtx
, 0, sizeof(vtx
));
2239 vtx
.op
= FETCH_OP_VFETCH
;
2240 vtx
.buffer_id
= R600_GS_RING_CONST_BUFFER
;
2241 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2242 vtx
.mega_fetch_count
= 16;
2243 vtx
.offset
= out
->ring_offset
;
2244 vtx
.dst_gpr
= out
->gpr
;
2250 if (rctx
->b
.chip_class
>= EVERGREEN
) {
2251 vtx
.use_const_fields
= 1;
2253 vtx
.data_format
= FMT_32_32_32_32_FLOAT
;
2256 r600_bytecode_add_vtx(ctx
.bc
, &vtx
);
2258 ctx
.temp_reg
= i
+ 1;
2259 for (ring
= 3; ring
>= 0; --ring
) {
2260 bool enabled
= false;
2261 for (i
= 0; i
< so
->num_outputs
; i
++) {
2262 if (so
->output
[i
].stream
== ring
) {
2265 only_ring_0
= false;
2269 if (ring
!= 0 && !enabled
) {
2270 cshader
->shader
.ring_item_sizes
[ring
] = 0;
2275 // Patch up jump label
2276 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2277 cf_pop
= ctx
.bc
->cf_last
;
2279 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2280 cf_jump
->pop_count
= 1;
2281 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2282 cf_pop
->pop_count
= 1;
2285 /* PRED_SETE_INT __, R0.y, ring */
2286 memset(&alu
, 0, sizeof(alu
));
2287 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2288 alu
.src
[0].chan
= 1;
2289 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2290 alu
.src
[1].value
= ring
;
2291 alu
.execute_mask
= 1;
2292 alu
.update_pred
= 1;
2294 r600_bytecode_add_alu_type(ctx
.bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2296 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_JUMP
);
2297 cf_jump
= ctx
.bc
->cf_last
;
2300 emit_streamout(&ctx
, so
, only_ring_0
? -1 : ring
, &cshader
->shader
.ring_item_sizes
[ring
]);
2301 cshader
->shader
.ring_item_sizes
[ring
] = ocnt
* 16;
2304 /* bc adds nops - copy it */
2305 if (ctx
.bc
->chip_class
== R600
) {
2306 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2307 alu
.op
= ALU_OP0_NOP
;
2309 r600_bytecode_add_alu(ctx
.bc
, &alu
);
2311 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2314 /* export vertex data */
2315 /* XXX factor out common code with r600_shader_from_tgsi ? */
2316 for (i
= 0; i
< ocnt
; ++i
) {
2317 struct r600_shader_io
*out
= &ctx
.shader
->output
[i
];
2318 bool instream0
= true;
2319 if (out
->name
== TGSI_SEMANTIC_CLIPVERTEX
)
2322 for (j
= 0; j
< so
->num_outputs
; j
++) {
2323 if (so
->output
[j
].register_index
== i
) {
2324 if (so
->output
[j
].stream
== 0)
2326 if (so
->output
[j
].stream
> 0)
2332 memset(&output
, 0, sizeof(output
));
2333 output
.gpr
= out
->gpr
;
2334 output
.elem_size
= 3;
2335 output
.swizzle_x
= 0;
2336 output
.swizzle_y
= 1;
2337 output
.swizzle_z
= 2;
2338 output
.swizzle_w
= 3;
2339 output
.burst_count
= 1;
2340 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2341 output
.op
= CF_OP_EXPORT
;
2342 switch (out
->name
) {
2343 case TGSI_SEMANTIC_POSITION
:
2344 output
.array_base
= 60;
2345 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2348 case TGSI_SEMANTIC_PSIZE
:
2349 output
.array_base
= 61;
2350 if (next_clip_pos
== 61)
2352 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2353 output
.swizzle_y
= 7;
2354 output
.swizzle_z
= 7;
2355 output
.swizzle_w
= 7;
2356 ctx
.shader
->vs_out_misc_write
= 1;
2357 ctx
.shader
->vs_out_point_size
= 1;
2359 case TGSI_SEMANTIC_LAYER
:
2361 /* duplicate it as PARAM to pass to the pixel shader */
2362 output
.array_base
= next_param
++;
2363 r600_bytecode_add_output(ctx
.bc
, &output
);
2364 last_exp_param
= ctx
.bc
->cf_last
;
2366 output
.array_base
= 61;
2367 if (next_clip_pos
== 61)
2369 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2370 output
.swizzle_x
= 7;
2371 output
.swizzle_y
= 7;
2372 output
.swizzle_z
= 0;
2373 output
.swizzle_w
= 7;
2374 ctx
.shader
->vs_out_misc_write
= 1;
2375 ctx
.shader
->vs_out_layer
= 1;
2377 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
2379 /* duplicate it as PARAM to pass to the pixel shader */
2380 output
.array_base
= next_param
++;
2381 r600_bytecode_add_output(ctx
.bc
, &output
);
2382 last_exp_param
= ctx
.bc
->cf_last
;
2384 output
.array_base
= 61;
2385 if (next_clip_pos
== 61)
2387 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2388 ctx
.shader
->vs_out_misc_write
= 1;
2389 ctx
.shader
->vs_out_viewport
= 1;
2390 output
.swizzle_x
= 7;
2391 output
.swizzle_y
= 7;
2392 output
.swizzle_z
= 7;
2393 output
.swizzle_w
= 0;
2395 case TGSI_SEMANTIC_CLIPDIST
:
2396 /* spi_sid is 0 for clipdistance outputs that were generated
2397 * for clipvertex - we don't need to pass them to PS */
2398 ctx
.shader
->clip_dist_write
= gs
->shader
.clip_dist_write
;
2399 ctx
.shader
->cull_dist_write
= gs
->shader
.cull_dist_write
;
2400 ctx
.shader
->cc_dist_mask
= gs
->shader
.cc_dist_mask
;
2402 /* duplicate it as PARAM to pass to the pixel shader */
2403 output
.array_base
= next_param
++;
2404 r600_bytecode_add_output(ctx
.bc
, &output
);
2405 last_exp_param
= ctx
.bc
->cf_last
;
2407 output
.array_base
= next_clip_pos
++;
2408 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2410 case TGSI_SEMANTIC_FOG
:
2411 output
.swizzle_y
= 4; /* 0 */
2412 output
.swizzle_z
= 4; /* 0 */
2413 output
.swizzle_w
= 5; /* 1 */
2416 output
.array_base
= next_param
++;
2419 r600_bytecode_add_output(ctx
.bc
, &output
);
2420 if (output
.type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
)
2421 last_exp_param
= ctx
.bc
->cf_last
;
2423 last_exp_pos
= ctx
.bc
->cf_last
;
2426 if (!last_exp_pos
) {
2427 memset(&output
, 0, sizeof(output
));
2429 output
.elem_size
= 3;
2430 output
.swizzle_x
= 7;
2431 output
.swizzle_y
= 7;
2432 output
.swizzle_z
= 7;
2433 output
.swizzle_w
= 7;
2434 output
.burst_count
= 1;
2436 output
.op
= CF_OP_EXPORT
;
2437 output
.array_base
= 60;
2438 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
2439 r600_bytecode_add_output(ctx
.bc
, &output
);
2440 last_exp_pos
= ctx
.bc
->cf_last
;
2443 if (!last_exp_param
) {
2444 memset(&output
, 0, sizeof(output
));
2446 output
.elem_size
= 3;
2447 output
.swizzle_x
= 7;
2448 output
.swizzle_y
= 7;
2449 output
.swizzle_z
= 7;
2450 output
.swizzle_w
= 7;
2451 output
.burst_count
= 1;
2453 output
.op
= CF_OP_EXPORT
;
2454 output
.array_base
= next_param
++;
2455 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
2456 r600_bytecode_add_output(ctx
.bc
, &output
);
2457 last_exp_param
= ctx
.bc
->cf_last
;
2460 last_exp_pos
->op
= CF_OP_EXPORT_DONE
;
2461 last_exp_param
->op
= CF_OP_EXPORT_DONE
;
2463 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_POP
);
2464 cf_pop
= ctx
.bc
->cf_last
;
2466 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2467 cf_jump
->pop_count
= 1;
2468 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2469 cf_pop
->pop_count
= 1;
2471 if (ctx
.bc
->chip_class
== CAYMAN
)
2472 cm_bytecode_add_cf_end(ctx
.bc
);
2474 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
2475 ctx
.bc
->cf_last
->end_of_program
= 1;
2478 gs
->gs_copy_shader
= cshader
;
2479 cshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
2483 return r600_bytecode_build(ctx
.bc
);
2486 static int emit_inc_ring_offset(struct r600_shader_ctx
*ctx
, int idx
, bool ind
)
2489 struct r600_bytecode_alu alu
;
2492 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2493 alu
.op
= ALU_OP2_ADD_INT
;
2494 alu
.src
[0].sel
= ctx
->gs_export_gpr_tregs
[idx
];
2495 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2496 alu
.src
[1].value
= ctx
->gs_out_ring_offset
>> 4;
2497 alu
.dst
.sel
= ctx
->gs_export_gpr_tregs
[idx
];
2500 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2507 static int emit_gs_ring_writes(struct r600_shader_ctx
*ctx
, const struct pipe_stream_output_info
*so UNUSED
, int stream
, bool ind
)
2509 struct r600_bytecode_output output
;
2512 int effective_stream
= stream
== -1 ? 0 : stream
;
2515 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2516 if (ctx
->gs_for_vs
) {
2517 /* for ES we need to lookup corresponding ring offset expected by GS
2518 * (map this output to GS input by name and sid) */
2519 /* FIXME precompute offsets */
2521 for(k
= 0; k
< ctx
->gs_for_vs
->ninput
; ++k
) {
2522 struct r600_shader_io
*in
= &ctx
->gs_for_vs
->input
[k
];
2523 struct r600_shader_io
*out
= &ctx
->shader
->output
[i
];
2524 if (in
->name
== out
->name
&& in
->sid
== out
->sid
)
2525 ring_offset
= in
->ring_offset
;
2528 if (ring_offset
== -1)
2531 ring_offset
= idx
* 16;
2535 if (stream
> 0 && ctx
->shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
2537 /* next_ring_offset after parsing input decls contains total size of
2538 * single vertex data, gs_next_vertex - current vertex index */
2540 ring_offset
+= ctx
->gs_out_ring_offset
* ctx
->gs_next_vertex
;
2542 memset(&output
, 0, sizeof(struct r600_bytecode_output
));
2543 output
.gpr
= ctx
->shader
->output
[i
].gpr
;
2544 output
.elem_size
= 3;
2545 output
.comp_mask
= 0xF;
2546 output
.burst_count
= 1;
2549 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
2551 output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE
;
2556 output
.op
= CF_OP_MEM_RING
; break;
2558 output
.op
= CF_OP_MEM_RING1
; break;
2560 output
.op
= CF_OP_MEM_RING2
; break;
2562 output
.op
= CF_OP_MEM_RING3
; break;
2566 output
.array_base
= ring_offset
>> 2; /* in dwords */
2567 output
.array_size
= 0xfff;
2568 output
.index_gpr
= ctx
->gs_export_gpr_tregs
[effective_stream
];
2570 output
.array_base
= ring_offset
>> 2; /* in dwords */
2571 r600_bytecode_add_output(ctx
->bc
, &output
);
2574 ++ctx
->gs_next_vertex
;
2579 static int r600_fetch_tess_io_info(struct r600_shader_ctx
*ctx
)
2582 struct r600_bytecode_vtx vtx
;
2583 int temp_val
= ctx
->temp_reg
;
2584 /* need to store the TCS output somewhere */
2585 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2587 V_SQ_ALU_SRC_LITERAL
, 0,
2592 /* used by VS/TCS */
2593 if (ctx
->tess_input_info
) {
2594 /* fetch tcs input values into resv space */
2595 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2596 vtx
.op
= FETCH_OP_VFETCH
;
2597 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2598 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2599 vtx
.mega_fetch_count
= 16;
2600 vtx
.data_format
= FMT_32_32_32_32
;
2601 vtx
.num_format_all
= 2;
2602 vtx
.format_comp_all
= 1;
2603 vtx
.use_const_fields
= 0;
2604 vtx
.endian
= r600_endian_swap(32);
2605 vtx
.srf_mode_all
= 1;
2607 vtx
.dst_gpr
= ctx
->tess_input_info
;
2612 vtx
.src_gpr
= temp_val
;
2615 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2620 /* used by TCS/TES */
2621 if (ctx
->tess_output_info
) {
2622 /* fetch tcs output values into resv space */
2623 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
2624 vtx
.op
= FETCH_OP_VFETCH
;
2625 vtx
.buffer_id
= R600_LDS_INFO_CONST_BUFFER
;
2626 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
2627 vtx
.mega_fetch_count
= 16;
2628 vtx
.data_format
= FMT_32_32_32_32
;
2629 vtx
.num_format_all
= 2;
2630 vtx
.format_comp_all
= 1;
2631 vtx
.use_const_fields
= 0;
2632 vtx
.endian
= r600_endian_swap(32);
2633 vtx
.srf_mode_all
= 1;
2635 vtx
.dst_gpr
= ctx
->tess_output_info
;
2640 vtx
.src_gpr
= temp_val
;
2643 r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
);
2650 static int emit_lds_vs_writes(struct r600_shader_ctx
*ctx
)
2656 /* fetch tcs input values into input_vals */
2657 ctx
->tess_input_info
= r600_get_temp(ctx
);
2658 ctx
->tess_output_info
= 0;
2659 r
= r600_fetch_tess_io_info(ctx
);
2663 temp_reg
= r600_get_temp(ctx
);
2664 /* dst reg contains LDS address stride * idx */
2665 /* MUL vertexID, vertex_dw_stride */
2666 r
= single_alu_op2(ctx
, ALU_OP2_MUL_UINT24
,
2668 ctx
->tess_input_info
, 1,
2669 0, 1); /* rel id in r0.y? */
2673 for (i
= 0; i
< ctx
->shader
->noutput
; i
++) {
2674 struct r600_bytecode_alu alu
;
2675 int param
= r600_get_lds_unique_index(ctx
->shader
->output
[i
].name
, ctx
->shader
->output
[i
].sid
);
2678 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2681 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2686 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2688 temp_reg
, param
? 1 : 0,
2689 V_SQ_ALU_SRC_LITERAL
, 8);
2694 for (j
= 0; j
< 2; j
++) {
2695 int chan
= (j
== 1) ? 2 : (param
? 1 : 0);
2696 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2697 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2698 alu
.src
[0].sel
= temp_reg
;
2699 alu
.src
[0].chan
= chan
;
2700 alu
.src
[1].sel
= ctx
->shader
->output
[i
].gpr
;
2701 alu
.src
[1].chan
= j
* 2;
2702 alu
.src
[2].sel
= ctx
->shader
->output
[i
].gpr
;
2703 alu
.src
[2].chan
= (j
* 2) + 1;
2707 alu
.is_lds_idx_op
= true;
2708 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2716 static int r600_store_tcs_output(struct r600_shader_ctx
*ctx
)
2718 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2719 const struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
2721 int temp_reg
= r600_get_temp(ctx
);
2722 struct r600_bytecode_alu alu
;
2723 unsigned write_mask
= dst
->Register
.WriteMask
;
2725 if (inst
->Dst
[0].Register
.File
!= TGSI_FILE_OUTPUT
)
2728 r
= get_lds_offset0(ctx
, 1, temp_reg
, dst
->Register
.Dimension
? false : true);
2732 /* the base address is now in temp.x */
2733 r
= r600_get_byte_address(ctx
, temp_reg
,
2734 &inst
->Dst
[0], NULL
, ctx
->tess_output_info
, 1);
2739 lasti
= tgsi_last_instruction(write_mask
);
2740 for (i
= 1; i
<= lasti
; i
++) {
2742 if (!(write_mask
& (1 << i
)))
2744 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2747 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2752 for (i
= 0; i
<= lasti
; i
++) {
2753 if (!(write_mask
& (1 << i
)))
2756 if ((i
== 0 && ((write_mask
& 3) == 3)) ||
2757 (i
== 2 && ((write_mask
& 0xc) == 0xc))) {
2758 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2759 alu
.op
= LDS_OP3_LDS_WRITE_REL
;
2760 alu
.src
[0].sel
= temp_reg
;
2761 alu
.src
[0].chan
= i
;
2763 alu
.src
[1].sel
= dst
->Register
.Index
;
2764 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2765 alu
.src
[1].chan
= i
;
2767 alu
.src
[2].sel
= dst
->Register
.Index
;
2768 alu
.src
[2].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2769 alu
.src
[2].chan
= i
+ 1;
2773 alu
.is_lds_idx_op
= true;
2774 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2780 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2781 alu
.op
= LDS_OP2_LDS_WRITE
;
2782 alu
.src
[0].sel
= temp_reg
;
2783 alu
.src
[0].chan
= i
;
2785 alu
.src
[1].sel
= dst
->Register
.Index
;
2786 alu
.src
[1].sel
+= ctx
->file_offset
[dst
->Register
.File
];
2787 alu
.src
[1].chan
= i
;
2789 alu
.src
[2].sel
= V_SQ_ALU_SRC_0
;
2792 alu
.is_lds_idx_op
= true;
2793 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2800 static int r600_tess_factor_read(struct r600_shader_ctx
*ctx
,
2804 unsigned temp_reg
= r600_get_temp(ctx
);
2805 unsigned name
= ctx
->shader
->output
[output_idx
].name
;
2806 int dreg
= ctx
->shader
->output
[output_idx
].gpr
;
2809 param
= r600_get_lds_unique_index(name
, 0);
2810 r
= get_lds_offset0(ctx
, 1, temp_reg
, true);
2814 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2817 V_SQ_ALU_SRC_LITERAL
, param
* 16);
2821 do_lds_fetch_values(ctx
, temp_reg
, dreg
, 0xf);
2825 static int r600_emit_tess_factor(struct r600_shader_ctx
*ctx
)
2827 int stride
, outer_comps
, inner_comps
;
2828 int tessinner_idx
= -1, tessouter_idx
= -1;
2831 int temp_reg
= r600_get_temp(ctx
);
2832 int treg
[3] = {-1, -1, -1};
2833 struct r600_bytecode_alu alu
;
2834 struct r600_bytecode_cf
*cf_jump
, *cf_pop
;
2836 /* only execute factor emission for invocation 0 */
2837 /* PRED_SETE_INT __, R0.x, 0 */
2838 memset(&alu
, 0, sizeof(alu
));
2839 alu
.op
= ALU_OP2_PRED_SETE_INT
;
2840 alu
.src
[0].chan
= 2;
2841 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
2842 alu
.execute_mask
= 1;
2843 alu
.update_pred
= 1;
2845 r600_bytecode_add_alu_type(ctx
->bc
, &alu
, CF_OP_ALU_PUSH_BEFORE
);
2847 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
2848 cf_jump
= ctx
->bc
->cf_last
;
2850 treg
[0] = r600_get_temp(ctx
);
2851 switch (ctx
->shader
->tcs_prim_mode
) {
2852 case PIPE_PRIM_LINES
:
2853 stride
= 8; /* 2 dwords, 1 vec2 store */
2857 case PIPE_PRIM_TRIANGLES
:
2858 stride
= 16; /* 4 dwords, 1 vec4 store */
2861 treg
[1] = r600_get_temp(ctx
);
2863 case PIPE_PRIM_QUADS
:
2864 stride
= 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2867 treg
[1] = r600_get_temp(ctx
);
2868 treg
[2] = r600_get_temp(ctx
);
2875 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2876 /* TF_WRITE takes index in R.x, value in R.y */
2877 for (j
= 0; j
< ctx
->shader
->noutput
; j
++) {
2878 if (ctx
->shader
->output
[j
].name
== TGSI_SEMANTIC_TESSINNER
)
2880 if (ctx
->shader
->output
[j
].name
== TGSI_SEMANTIC_TESSOUTER
)
2884 if (tessouter_idx
== -1)
2887 if (tessinner_idx
== -1 && inner_comps
)
2890 if (tessouter_idx
!= -1) {
2891 r
= r600_tess_factor_read(ctx
, tessouter_idx
);
2896 if (tessinner_idx
!= -1) {
2897 r
= r600_tess_factor_read(ctx
, tessinner_idx
);
2902 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2903 /* r.x = relpatchid(r0.y) * tf_stride */
2905 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2906 /* add incoming r0.w to it: t.x = t.x + r0.w */
2907 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
2910 V_SQ_ALU_SRC_LITERAL
, stride
,
2915 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2916 int out_idx
= i
>= outer_comps
? tessinner_idx
: tessouter_idx
;
2917 int out_comp
= i
>= outer_comps
? i
- outer_comps
: i
;
2919 if (ctx
->shader
->tcs_prim_mode
== PIPE_PRIM_LINES
) {
2922 else if (out_comp
== 0)
2926 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
2927 treg
[i
/ 2], (2 * (i
% 2)),
2929 V_SQ_ALU_SRC_LITERAL
, 4 * i
);
2932 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
2933 treg
[i
/ 2], 1 + (2 * (i
%2)),
2934 ctx
->shader
->output
[out_idx
].gpr
, out_comp
,
2939 for (i
= 0; i
< outer_comps
+ inner_comps
; i
++) {
2940 struct r600_bytecode_gds gds
;
2942 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
2943 gds
.src_gpr
= treg
[i
/ 2];
2944 gds
.src_sel_x
= 2 * (i
% 2);
2945 gds
.src_sel_y
= 1 + (2 * (i
% 2));
2951 gds
.op
= FETCH_OP_TF_WRITE
;
2952 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
2957 // Patch up jump label
2958 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
2959 cf_pop
= ctx
->bc
->cf_last
;
2961 cf_jump
->cf_addr
= cf_pop
->id
+ 2;
2962 cf_jump
->pop_count
= 1;
2963 cf_pop
->cf_addr
= cf_pop
->id
+ 2;
2964 cf_pop
->pop_count
= 1;
2970 * We have to work out the thread ID for load and atomic
2971 * operations, which store the returned value to an index
2972 * in an intermediate buffer.
2973 * The index is calculated by taking the thread id,
2974 * calculated from the MBCNT instructions.
2975 * Then the shader engine ID is multiplied by 256,
2976 * and the wave id is added.
2977 * Then the result is multipled by 64 and thread id is
2980 static int load_thread_id_gpr(struct r600_shader_ctx
*ctx
)
2982 struct r600_bytecode_alu alu
;
2985 if (ctx
->thread_id_gpr_loaded
)
2988 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
2989 alu
.op
= ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT
;
2990 alu
.dst
.sel
= ctx
->temp_reg
;
2992 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
2993 alu
.src
[0].value
= 0xffffffff;
2995 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
2999 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3000 alu
.op
= ALU_OP1_MBCNT_32HI_INT
;
3001 alu
.dst
.sel
= ctx
->temp_reg
;
3003 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3004 alu
.src
[0].value
= 0xffffffff;
3006 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3010 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3011 alu
.op
= ALU_OP3_MULADD_UINT24
;
3012 alu
.dst
.sel
= ctx
->temp_reg
;
3014 alu
.src
[0].sel
= EG_V_SQ_ALU_SRC_SE_ID
;
3015 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
3016 alu
.src
[1].value
= 256;
3017 alu
.src
[2].sel
= EG_V_SQ_ALU_SRC_HW_WAVE_ID
;
3021 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
3025 r
= single_alu_op3(ctx
, ALU_OP3_MULADD_UINT24
,
3026 ctx
->thread_id_gpr
, 1,
3028 V_SQ_ALU_SRC_LITERAL
, 0x40,
3032 ctx
->thread_id_gpr_loaded
= true;
3036 static int r600_shader_from_tgsi(struct r600_context
*rctx
,
3037 struct r600_pipe_shader
*pipeshader
,
3038 union r600_shader_key key
)
3040 struct r600_screen
*rscreen
= rctx
->screen
;
3041 struct r600_shader
*shader
= &pipeshader
->shader
;
3042 struct tgsi_token
*tokens
= pipeshader
->selector
->tokens
;
3043 struct pipe_stream_output_info so
= pipeshader
->selector
->so
;
3044 struct tgsi_full_immediate
*immediate
;
3045 struct r600_shader_ctx ctx
;
3046 struct r600_bytecode_output output
[ARRAY_SIZE(shader
->output
)];
3047 unsigned output_done
, noutput
;
3051 int next_param_base
= 0, next_clip_base
;
3052 int max_color_exports
= MAX2(key
.ps
.nr_cbufs
, 1);
3054 bool ring_outputs
= false;
3055 bool lds_outputs
= false;
3056 bool lds_inputs
= false;
3057 bool pos_emitted
= false;
3059 ctx
.bc
= &shader
->bc
;
3060 ctx
.shader
= shader
;
3061 ctx
.native_integers
= true;
3063 r600_bytecode_init(ctx
.bc
, rscreen
->b
.chip_class
, rscreen
->b
.family
,
3064 rscreen
->has_compressed_msaa_texturing
);
3065 ctx
.tokens
= tokens
;
3066 tgsi_scan_shader(tokens
, &ctx
.info
);
3067 shader
->indirect_files
= ctx
.info
.indirect_files
;
3069 shader
->uses_doubles
= ctx
.info
.uses_doubles
;
3070 shader
->uses_atomics
= ctx
.info
.file_mask
[TGSI_FILE_HW_ATOMIC
];
3071 shader
->nsys_inputs
= 0;
3073 shader
->uses_images
= ctx
.info
.file_count
[TGSI_FILE_IMAGE
] > 0 ||
3074 ctx
.info
.file_count
[TGSI_FILE_BUFFER
] > 0;
3075 indirect_gprs
= ctx
.info
.indirect_files
& ~((1 << TGSI_FILE_CONSTANT
) | (1 << TGSI_FILE_SAMPLER
));
3076 tgsi_parse_init(&ctx
.parse
, tokens
);
3077 ctx
.type
= ctx
.info
.processor
;
3078 shader
->processor_type
= ctx
.type
;
3079 ctx
.bc
->type
= shader
->processor_type
;
3082 case PIPE_SHADER_VERTEX
:
3083 shader
->vs_as_gs_a
= key
.vs
.as_gs_a
;
3084 shader
->vs_as_es
= key
.vs
.as_es
;
3085 shader
->vs_as_ls
= key
.vs
.as_ls
;
3086 shader
->atomic_base
= key
.vs
.first_atomic_counter
;
3087 if (shader
->vs_as_es
)
3088 ring_outputs
= true;
3089 if (shader
->vs_as_ls
)
3092 case PIPE_SHADER_GEOMETRY
:
3093 ring_outputs
= true;
3094 shader
->atomic_base
= key
.gs
.first_atomic_counter
;
3095 shader
->gs_tri_strip_adj_fix
= key
.gs
.tri_strip_adj_fix
;
3097 case PIPE_SHADER_TESS_CTRL
:
3098 shader
->tcs_prim_mode
= key
.tcs
.prim_mode
;
3099 shader
->atomic_base
= key
.tcs
.first_atomic_counter
;
3103 case PIPE_SHADER_TESS_EVAL
:
3104 shader
->tes_as_es
= key
.tes
.as_es
;
3105 shader
->atomic_base
= key
.tes
.first_atomic_counter
;
3107 if (shader
->tes_as_es
)
3108 ring_outputs
= true;
3110 case PIPE_SHADER_FRAGMENT
:
3111 shader
->two_side
= key
.ps
.color_two_side
;
3112 shader
->atomic_base
= key
.ps
.first_atomic_counter
;
3113 shader
->rat_base
= key
.ps
.nr_cbufs
;
3114 shader
->image_size_const_offset
= key
.ps
.image_size_const_offset
;
3120 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3121 ctx
.gs_for_vs
= &rctx
->gs_shader
->current
->shader
;
3123 ctx
.gs_for_vs
= NULL
;
3126 ctx
.next_ring_offset
= 0;
3127 ctx
.gs_out_ring_offset
= 0;
3128 ctx
.gs_next_vertex
= 0;
3129 ctx
.gs_stream_output_info
= &so
;
3132 ctx
.fixed_pt_position_gpr
= -1;
3133 ctx
.fragcoord_input
= -1;
3134 ctx
.colors_used
= 0;
3135 ctx
.clip_vertex_write
= 0;
3136 ctx
.thread_id_gpr_loaded
= false;
3138 shader
->nr_ps_color_exports
= 0;
3139 shader
->nr_ps_max_color_exports
= 0;
3142 /* register allocations */
3143 /* Values [0,127] correspond to GPR[0..127].
3144 * Values [128,159] correspond to constant buffer bank 0
3145 * Values [160,191] correspond to constant buffer bank 1
3146 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3147 * Values [256,287] correspond to constant buffer bank 2 (EG)
3148 * Values [288,319] correspond to constant buffer bank 3 (EG)
3149 * Other special values are shown in the list below.
3150 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3151 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3152 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3153 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3154 * 248 SQ_ALU_SRC_0: special constant 0.0.
3155 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3156 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3157 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3158 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3159 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3160 * 254 SQ_ALU_SRC_PV: previous vector result.
3161 * 255 SQ_ALU_SRC_PS: previous scalar result.
3163 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
3164 ctx
.file_offset
[i
] = 0;
3167 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3169 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3170 if (ctx
.info
.num_inputs
)
3171 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CALL_FS
);
3173 if (ctx
.type
== PIPE_SHADER_FRAGMENT
) {
3174 if (ctx
.bc
->chip_class
>= EVERGREEN
)
3175 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
3177 ctx
.file_offset
[TGSI_FILE_INPUT
] = allocate_system_value_inputs(&ctx
, ctx
.file_offset
[TGSI_FILE_INPUT
]);
3179 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3180 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3181 ctx
.file_offset
[TGSI_FILE_INPUT
] = 2;
3183 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3184 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3185 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3186 bool add_tesscoord
= false, add_tess_inout
= false;
3187 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
3188 for (i
= 0; i
< PIPE_MAX_SHADER_INPUTS
; i
++) {
3189 /* if we have tesscoord save one reg */
3190 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSCOORD
)
3191 add_tesscoord
= true;
3192 if (ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSINNER
||
3193 ctx
.info
.system_value_semantic_name
[i
] == TGSI_SEMANTIC_TESSOUTER
)
3194 add_tess_inout
= true;
3196 if (add_tesscoord
|| add_tess_inout
)
3197 ctx
.file_offset
[TGSI_FILE_INPUT
]++;
3199 ctx
.file_offset
[TGSI_FILE_INPUT
]+=2;
3202 ctx
.file_offset
[TGSI_FILE_OUTPUT
] =
3203 ctx
.file_offset
[TGSI_FILE_INPUT
] +
3204 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3205 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
3206 ctx
.info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3208 /* Outside the GPR range. This will be translated to one of the
3209 * kcache banks later. */
3210 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
3212 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
3213 ctx
.bc
->ar_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
3214 ctx
.info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3215 ctx
.bc
->index_reg
[0] = ctx
.bc
->ar_reg
+ 1;
3216 ctx
.bc
->index_reg
[1] = ctx
.bc
->ar_reg
+ 2;
3218 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3219 ctx
.tess_input_info
= ctx
.bc
->ar_reg
+ 3;
3220 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 4;
3221 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 5;
3222 } else if (ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3223 ctx
.tess_input_info
= 0;
3224 ctx
.tess_output_info
= ctx
.bc
->ar_reg
+ 3;
3225 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 4;
3226 } else if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3227 ctx
.gs_export_gpr_tregs
[0] = ctx
.bc
->ar_reg
+ 3;
3228 ctx
.gs_export_gpr_tregs
[1] = ctx
.bc
->ar_reg
+ 4;
3229 ctx
.gs_export_gpr_tregs
[2] = ctx
.bc
->ar_reg
+ 5;
3230 ctx
.gs_export_gpr_tregs
[3] = ctx
.bc
->ar_reg
+ 6;
3231 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 7;
3232 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3233 ctx
.gs_rotated_input
[0] = ctx
.bc
->ar_reg
+ 7;
3234 ctx
.gs_rotated_input
[1] = ctx
.bc
->ar_reg
+ 8;
3237 ctx
.gs_rotated_input
[0] = 0;
3238 ctx
.gs_rotated_input
[1] = 1;
3241 ctx
.temp_reg
= ctx
.bc
->ar_reg
+ 3;
3244 if (shader
->uses_images
) {
3245 ctx
.thread_id_gpr
= ctx
.temp_reg
++;
3246 ctx
.thread_id_gpr_loaded
= false;
3249 shader
->max_arrays
= 0;
3250 shader
->num_arrays
= 0;
3251 if (indirect_gprs
) {
3253 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_INPUT
)) {
3254 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_INPUT
],
3255 ctx
.file_offset
[TGSI_FILE_OUTPUT
] -
3256 ctx
.file_offset
[TGSI_FILE_INPUT
],
3259 if (ctx
.info
.indirect_files
& (1 << TGSI_FILE_OUTPUT
)) {
3260 r600_add_gpr_array(shader
, ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3261 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] -
3262 ctx
.file_offset
[TGSI_FILE_OUTPUT
],
3268 ctx
.literals
= NULL
;
3270 shader
->fs_write_all
= ctx
.info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
3271 ctx
.info
.colors_written
== 1;
3272 shader
->vs_position_window_space
= ctx
.info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
3273 shader
->ps_conservative_z
= (uint8_t)ctx
.info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
];
3275 if (ctx
.type
== PIPE_SHADER_VERTEX
||
3276 ctx
.type
== PIPE_SHADER_GEOMETRY
||
3277 ctx
.type
== PIPE_SHADER_TESS_EVAL
) {
3278 shader
->cc_dist_mask
= (1 << (ctx
.info
.properties
[TGSI_PROPERTY_NUM_CULLDIST_ENABLED
] +
3279 ctx
.info
.properties
[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
])) - 1;
3280 shader
->clip_dist_write
= (1 << ctx
.info
.properties
[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
]) - 1;
3281 shader
->cull_dist_write
= ((1 << ctx
.info
.properties
[TGSI_PROPERTY_NUM_CULLDIST_ENABLED
]) - 1) << ctx
.info
.properties
[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED
];
3284 if (shader
->vs_as_gs_a
)
3285 vs_add_primid_output(&ctx
, key
.vs
.prim_id_out
);
3287 if (ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3288 r600_fetch_tess_io_info(&ctx
);
3290 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3291 tgsi_parse_token(&ctx
.parse
);
3292 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3293 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3294 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
3295 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
3296 if(ctx
.literals
== NULL
) {
3300 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
3301 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
3302 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
3303 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
3306 case TGSI_TOKEN_TYPE_DECLARATION
:
3307 r
= tgsi_declaration(&ctx
);
3311 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3312 case TGSI_TOKEN_TYPE_PROPERTY
:
3315 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
3321 shader
->ring_item_sizes
[0] = ctx
.next_ring_offset
;
3322 shader
->ring_item_sizes
[1] = 0;
3323 shader
->ring_item_sizes
[2] = 0;
3324 shader
->ring_item_sizes
[3] = 0;
3326 /* Process two side if needed */
3327 if (shader
->two_side
&& ctx
.colors_used
) {
3328 int i
, count
= ctx
.shader
->ninput
;
3329 unsigned next_lds_loc
= ctx
.shader
->nlds
;
3331 /* additional inputs will be allocated right after the existing inputs,
3332 * we won't need them after the color selection, so we don't need to
3333 * reserve these gprs for the rest of the shader code and to adjust
3334 * output offsets etc. */
3335 int gpr
= ctx
.file_offset
[TGSI_FILE_INPUT
] +
3336 ctx
.info
.file_max
[TGSI_FILE_INPUT
] + 1;
3338 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3339 if (ctx
.face_gpr
== -1) {
3340 i
= ctx
.shader
->ninput
++;
3341 ctx
.shader
->input
[i
].name
= TGSI_SEMANTIC_FACE
;
3342 ctx
.shader
->input
[i
].spi_sid
= 0;
3343 ctx
.shader
->input
[i
].gpr
= gpr
++;
3344 ctx
.face_gpr
= ctx
.shader
->input
[i
].gpr
;
3347 for (i
= 0; i
< count
; i
++) {
3348 if (ctx
.shader
->input
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3349 int ni
= ctx
.shader
->ninput
++;
3350 memcpy(&ctx
.shader
->input
[ni
],&ctx
.shader
->input
[i
], sizeof(struct r600_shader_io
));
3351 ctx
.shader
->input
[ni
].name
= TGSI_SEMANTIC_BCOLOR
;
3352 ctx
.shader
->input
[ni
].spi_sid
= r600_spi_sid(&ctx
.shader
->input
[ni
]);
3353 ctx
.shader
->input
[ni
].gpr
= gpr
++;
3354 // TGSI to LLVM needs to know the lds position of inputs.
3355 // Non LLVM path computes it later (in process_twoside_color)
3356 ctx
.shader
->input
[ni
].lds_pos
= next_lds_loc
++;
3357 ctx
.shader
->input
[i
].back_color_input
= ni
;
3358 if (ctx
.bc
->chip_class
>= EVERGREEN
) {
3359 if ((r
= evergreen_interp_input(&ctx
, ni
)))
3366 if (shader
->fs_write_all
&& rscreen
->b
.chip_class
>= EVERGREEN
)
3367 shader
->nr_ps_max_color_exports
= 8;
3369 if (ctx
.fragcoord_input
>= 0) {
3370 if (ctx
.bc
->chip_class
== CAYMAN
) {
3371 for (j
= 0 ; j
< 4; j
++) {
3372 struct r600_bytecode_alu alu
;
3373 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3374 alu
.op
= ALU_OP1_RECIP_IEEE
;
3375 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3376 alu
.src
[0].chan
= 3;
3378 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3380 alu
.dst
.write
= (j
== 3);
3382 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3386 struct r600_bytecode_alu alu
;
3387 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3388 alu
.op
= ALU_OP1_RECIP_IEEE
;
3389 alu
.src
[0].sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3390 alu
.src
[0].chan
= 3;
3392 alu
.dst
.sel
= shader
->input
[ctx
.fragcoord_input
].gpr
;
3396 if ((r
= r600_bytecode_add_alu(ctx
.bc
, &alu
)))
3401 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3402 struct r600_bytecode_alu alu
;
3405 /* GS thread with no output workaround - emit a cut at start of GS */
3406 if (ctx
.bc
->chip_class
== R600
)
3407 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_CUT_VERTEX
);
3409 for (j
= 0; j
< 4; j
++) {
3410 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3411 alu
.op
= ALU_OP1_MOV
;
3412 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
3413 alu
.src
[0].value
= 0;
3414 alu
.dst
.sel
= ctx
.gs_export_gpr_tregs
[j
];
3417 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3422 if (ctx
.shader
->gs_tri_strip_adj_fix
) {
3423 r
= single_alu_op2(&ctx
, ALU_OP2_AND_INT
,
3424 ctx
.gs_rotated_input
[0], 2,
3426 V_SQ_ALU_SRC_LITERAL
, 1);
3430 for (i
= 0; i
< 6; i
++) {
3431 int rotated
= (i
+ 4) % 6;
3432 int offset_reg
= i
/ 3;
3433 int offset_chan
= i
% 3;
3434 int rotated_offset_reg
= rotated
/ 3;
3435 int rotated_offset_chan
= rotated
% 3;
3437 if (offset_reg
== 0 && offset_chan
== 2)
3439 if (rotated_offset_reg
== 0 && rotated_offset_chan
== 2)
3440 rotated_offset_chan
= 3;
3442 r
= single_alu_op3(&ctx
, ALU_OP3_CNDE_INT
,
3443 ctx
.gs_rotated_input
[offset_reg
], offset_chan
,
3444 ctx
.gs_rotated_input
[0], 2,
3445 offset_reg
, offset_chan
,
3446 rotated_offset_reg
, rotated_offset_chan
);
3453 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3454 r600_fetch_tess_io_info(&ctx
);
3456 if (shader
->two_side
&& ctx
.colors_used
) {
3457 if ((r
= process_twoside_color_inputs(&ctx
)))
3461 tgsi_parse_init(&ctx
.parse
, tokens
);
3462 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
3463 tgsi_parse_token(&ctx
.parse
);
3464 switch (ctx
.parse
.FullToken
.Token
.Type
) {
3465 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3466 r
= tgsi_is_supported(&ctx
);
3469 ctx
.max_driver_temp_used
= 0;
3470 /* reserve first tmp for everyone */
3471 r600_get_temp(&ctx
);
3473 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3474 if ((r
= tgsi_split_constant(&ctx
)))
3476 if ((r
= tgsi_split_literal_constant(&ctx
)))
3478 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3479 if ((r
= tgsi_split_gs_inputs(&ctx
)))
3481 } else if (lds_inputs
) {
3482 if ((r
= tgsi_split_lds_inputs(&ctx
)))
3485 if (ctx
.bc
->chip_class
== CAYMAN
)
3486 ctx
.inst_info
= &cm_shader_tgsi_instruction
[opcode
];
3487 else if (ctx
.bc
->chip_class
>= EVERGREEN
)
3488 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
3490 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
3491 r
= ctx
.inst_info
->process(&ctx
);
3495 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
) {
3496 r
= r600_store_tcs_output(&ctx
);
3506 /* Reset the temporary register counter. */
3507 ctx
.max_driver_temp_used
= 0;
3509 noutput
= shader
->noutput
;
3511 if (!ring_outputs
&& ctx
.clip_vertex_write
) {
3512 unsigned clipdist_temp
[2];
3514 clipdist_temp
[0] = r600_get_temp(&ctx
);
3515 clipdist_temp
[1] = r600_get_temp(&ctx
);
3517 /* need to convert a clipvertex write into clipdistance writes and not export
3518 the clip vertex anymore */
3520 memset(&shader
->output
[noutput
], 0, 2*sizeof(struct r600_shader_io
));
3521 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3522 shader
->output
[noutput
].gpr
= clipdist_temp
[0];
3524 shader
->output
[noutput
].name
= TGSI_SEMANTIC_CLIPDIST
;
3525 shader
->output
[noutput
].gpr
= clipdist_temp
[1];
3528 /* reset spi_sid for clipvertex output to avoid confusing spi */
3529 shader
->output
[ctx
.cv_output
].spi_sid
= 0;
3531 shader
->clip_dist_write
= 0xFF;
3532 shader
->cc_dist_mask
= 0xFF;
3534 for (i
= 0; i
< 8; i
++) {
3538 for (j
= 0; j
< 4; j
++) {
3539 struct r600_bytecode_alu alu
;
3540 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3541 alu
.op
= ALU_OP2_DOT4
;
3542 alu
.src
[0].sel
= shader
->output
[ctx
.cv_output
].gpr
;
3543 alu
.src
[0].chan
= j
;
3545 alu
.src
[1].sel
= 512 + i
;
3546 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
3547 alu
.src
[1].chan
= j
;
3549 alu
.dst
.sel
= clipdist_temp
[oreg
];
3551 alu
.dst
.write
= (j
== ochan
);
3554 r
= r600_bytecode_add_alu(ctx
.bc
, &alu
);
3561 /* Add stream outputs. */
3562 if (so
.num_outputs
) {
3564 if (!lds_outputs
&& !ring_outputs
&& ctx
.type
== PIPE_SHADER_VERTEX
)
3566 if (!ring_outputs
&& ctx
.type
== PIPE_SHADER_TESS_EVAL
)
3569 emit_streamout(&ctx
, &so
, -1, NULL
);
3571 pipeshader
->enabled_stream_buffers_mask
= ctx
.enabled_stream_buffers_mask
;
3572 convert_edgeflag_to_int(&ctx
);
3574 if (ctx
.type
== PIPE_SHADER_TESS_CTRL
)
3575 r600_emit_tess_factor(&ctx
);
3578 if (ctx
.type
== PIPE_SHADER_VERTEX
) {
3579 if (ctx
.shader
->noutput
)
3580 emit_lds_vs_writes(&ctx
);
3582 } else if (ring_outputs
) {
3583 if (shader
->vs_as_es
|| shader
->tes_as_es
) {
3584 ctx
.gs_export_gpr_tregs
[0] = r600_get_temp(&ctx
);
3585 ctx
.gs_export_gpr_tregs
[1] = -1;
3586 ctx
.gs_export_gpr_tregs
[2] = -1;
3587 ctx
.gs_export_gpr_tregs
[3] = -1;
3589 emit_gs_ring_writes(&ctx
, &so
, -1, FALSE
);
3593 next_clip_base
= shader
->vs_out_misc_write
? 62 : 61;
3595 for (i
= 0, j
= 0; i
< noutput
; i
++, j
++) {
3596 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3597 output
[j
].gpr
= shader
->output
[i
].gpr
;
3598 output
[j
].elem_size
= 3;
3599 output
[j
].swizzle_x
= 0;
3600 output
[j
].swizzle_y
= 1;
3601 output
[j
].swizzle_z
= 2;
3602 output
[j
].swizzle_w
= 3;
3603 output
[j
].burst_count
= 1;
3604 output
[j
].type
= 0xffffffff;
3605 output
[j
].op
= CF_OP_EXPORT
;
3607 case PIPE_SHADER_VERTEX
:
3608 case PIPE_SHADER_TESS_EVAL
:
3609 switch (shader
->output
[i
].name
) {
3610 case TGSI_SEMANTIC_POSITION
:
3611 output
[j
].array_base
= 60;
3612 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3616 case TGSI_SEMANTIC_PSIZE
:
3617 output
[j
].array_base
= 61;
3618 output
[j
].swizzle_y
= 7;
3619 output
[j
].swizzle_z
= 7;
3620 output
[j
].swizzle_w
= 7;
3621 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3624 case TGSI_SEMANTIC_EDGEFLAG
:
3625 output
[j
].array_base
= 61;
3626 output
[j
].swizzle_x
= 7;
3627 output
[j
].swizzle_y
= 0;
3628 output
[j
].swizzle_z
= 7;
3629 output
[j
].swizzle_w
= 7;
3630 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3633 case TGSI_SEMANTIC_LAYER
:
3634 /* spi_sid is 0 for outputs that are
3635 * not consumed by PS */
3636 if (shader
->output
[i
].spi_sid
) {
3637 output
[j
].array_base
= next_param_base
++;
3638 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3640 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3642 output
[j
].array_base
= 61;
3643 output
[j
].swizzle_x
= 7;
3644 output
[j
].swizzle_y
= 7;
3645 output
[j
].swizzle_z
= 0;
3646 output
[j
].swizzle_w
= 7;
3647 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3650 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
3651 /* spi_sid is 0 for outputs that are
3652 * not consumed by PS */
3653 if (shader
->output
[i
].spi_sid
) {
3654 output
[j
].array_base
= next_param_base
++;
3655 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3657 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3659 output
[j
].array_base
= 61;
3660 output
[j
].swizzle_x
= 7;
3661 output
[j
].swizzle_y
= 7;
3662 output
[j
].swizzle_z
= 7;
3663 output
[j
].swizzle_w
= 0;
3664 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3667 case TGSI_SEMANTIC_CLIPVERTEX
:
3670 case TGSI_SEMANTIC_CLIPDIST
:
3671 output
[j
].array_base
= next_clip_base
++;
3672 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3674 /* spi_sid is 0 for clipdistance outputs that were generated
3675 * for clipvertex - we don't need to pass them to PS */
3676 if (shader
->output
[i
].spi_sid
) {
3678 /* duplicate it as PARAM to pass to the pixel shader */
3679 memcpy(&output
[j
], &output
[j
-1], sizeof(struct r600_bytecode_output
));
3680 output
[j
].array_base
= next_param_base
++;
3681 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3684 case TGSI_SEMANTIC_FOG
:
3685 output
[j
].swizzle_y
= 4; /* 0 */
3686 output
[j
].swizzle_z
= 4; /* 0 */
3687 output
[j
].swizzle_w
= 5; /* 1 */
3689 case TGSI_SEMANTIC_PRIMID
:
3690 output
[j
].swizzle_x
= 2;
3691 output
[j
].swizzle_y
= 4; /* 0 */
3692 output
[j
].swizzle_z
= 4; /* 0 */
3693 output
[j
].swizzle_w
= 4; /* 0 */
3698 case PIPE_SHADER_FRAGMENT
:
3699 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
3700 /* never export more colors than the number of CBs */
3701 if (shader
->output
[i
].sid
>= max_color_exports
) {
3706 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3707 output
[j
].array_base
= shader
->output
[i
].sid
;
3708 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3709 shader
->nr_ps_color_exports
++;
3710 if (shader
->fs_write_all
&& (rscreen
->b
.chip_class
>= EVERGREEN
)) {
3711 for (k
= 1; k
< max_color_exports
; k
++) {
3713 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3714 output
[j
].gpr
= shader
->output
[i
].gpr
;
3715 output
[j
].elem_size
= 3;
3716 output
[j
].swizzle_x
= 0;
3717 output
[j
].swizzle_y
= 1;
3718 output
[j
].swizzle_z
= 2;
3719 output
[j
].swizzle_w
= key
.ps
.alpha_to_one
? 5 : 3;
3720 output
[j
].burst_count
= 1;
3721 output
[j
].array_base
= k
;
3722 output
[j
].op
= CF_OP_EXPORT
;
3723 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3724 shader
->nr_ps_color_exports
++;
3727 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
3728 output
[j
].array_base
= 61;
3729 output
[j
].swizzle_x
= 2;
3730 output
[j
].swizzle_y
= 7;
3731 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3732 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3733 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
3734 output
[j
].array_base
= 61;
3735 output
[j
].swizzle_x
= 7;
3736 output
[j
].swizzle_y
= 1;
3737 output
[j
].swizzle_z
= output
[j
].swizzle_w
= 7;
3738 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3739 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_SAMPLEMASK
) {
3740 output
[j
].array_base
= 61;
3741 output
[j
].swizzle_x
= 7;
3742 output
[j
].swizzle_y
= 7;
3743 output
[j
].swizzle_z
= 0;
3744 output
[j
].swizzle_w
= 7;
3745 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3747 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
3752 case PIPE_SHADER_TESS_CTRL
:
3755 R600_ERR("unsupported processor type %d\n", ctx
.type
);
3760 if (output
[j
].type
== 0xffffffff) {
3761 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3762 output
[j
].array_base
= next_param_base
++;
3766 /* add fake position export */
3767 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && pos_emitted
== false) {
3768 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3770 output
[j
].elem_size
= 3;
3771 output
[j
].swizzle_x
= 7;
3772 output
[j
].swizzle_y
= 7;
3773 output
[j
].swizzle_z
= 7;
3774 output
[j
].swizzle_w
= 7;
3775 output
[j
].burst_count
= 1;
3776 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
3777 output
[j
].array_base
= 60;
3778 output
[j
].op
= CF_OP_EXPORT
;
3782 /* add fake param output for vertex shader if no param is exported */
3783 if ((ctx
.type
== PIPE_SHADER_VERTEX
|| ctx
.type
== PIPE_SHADER_TESS_EVAL
) && next_param_base
== 0) {
3784 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3786 output
[j
].elem_size
= 3;
3787 output
[j
].swizzle_x
= 7;
3788 output
[j
].swizzle_y
= 7;
3789 output
[j
].swizzle_z
= 7;
3790 output
[j
].swizzle_w
= 7;
3791 output
[j
].burst_count
= 1;
3792 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
3793 output
[j
].array_base
= 0;
3794 output
[j
].op
= CF_OP_EXPORT
;
3798 /* add fake pixel export */
3799 if (ctx
.type
== PIPE_SHADER_FRAGMENT
&& shader
->nr_ps_color_exports
== 0) {
3800 memset(&output
[j
], 0, sizeof(struct r600_bytecode_output
));
3802 output
[j
].elem_size
= 3;
3803 output
[j
].swizzle_x
= 7;
3804 output
[j
].swizzle_y
= 7;
3805 output
[j
].swizzle_z
= 7;
3806 output
[j
].swizzle_w
= 7;
3807 output
[j
].burst_count
= 1;
3808 output
[j
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
3809 output
[j
].array_base
= 0;
3810 output
[j
].op
= CF_OP_EXPORT
;
3812 shader
->nr_ps_color_exports
++;
3817 /* set export done on last export of each type */
3818 for (k
= noutput
- 1, output_done
= 0; k
>= 0; k
--) {
3819 if (!(output_done
& (1 << output
[k
].type
))) {
3820 output_done
|= (1 << output
[k
].type
);
3821 output
[k
].op
= CF_OP_EXPORT_DONE
;
3824 /* add output to bytecode */
3825 for (i
= 0; i
< noutput
; i
++) {
3826 r
= r600_bytecode_add_output(ctx
.bc
, &output
[i
]);
3832 /* add program end */
3833 if (ctx
.bc
->chip_class
== CAYMAN
)
3834 cm_bytecode_add_cf_end(ctx
.bc
);
3836 const struct cf_op_info
*last
= NULL
;
3838 if (ctx
.bc
->cf_last
)
3839 last
= r600_isa_cf(ctx
.bc
->cf_last
->op
);
3841 /* alu clause instructions don't have EOP bit, so add NOP */
3842 if (!last
|| last
->flags
& CF_ALU
)
3843 r600_bytecode_add_cfinst(ctx
.bc
, CF_OP_NOP
);
3845 ctx
.bc
->cf_last
->end_of_program
= 1;
3848 /* check GPR limit - we have 124 = 128 - 4
3849 * (4 are reserved as alu clause temporary registers) */
3850 if (ctx
.bc
->ngpr
> 124) {
3851 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx
.bc
->ngpr
);
3856 if (ctx
.type
== PIPE_SHADER_GEOMETRY
) {
3857 if ((r
= generate_gs_copy_shader(rctx
, pipeshader
, &so
)))
3862 tgsi_parse_free(&ctx
.parse
);
3866 tgsi_parse_free(&ctx
.parse
);
3870 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
3872 const unsigned tgsi_opcode
=
3873 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
3874 R600_ERR("%s tgsi opcode unsupported\n",
3875 tgsi_get_opcode_name(tgsi_opcode
));
3879 static int tgsi_end(struct r600_shader_ctx
*ctx UNUSED
)
3884 static void r600_bytecode_src(struct r600_bytecode_alu_src
*bc_src
,
3885 const struct r600_shader_src
*shader_src
,
3888 bc_src
->sel
= shader_src
->sel
;
3889 bc_src
->chan
= shader_src
->swizzle
[chan
];
3890 bc_src
->neg
= shader_src
->neg
;
3891 bc_src
->abs
= shader_src
->abs
;
3892 bc_src
->rel
= shader_src
->rel
;
3893 bc_src
->value
= shader_src
->value
[bc_src
->chan
];
3894 bc_src
->kc_bank
= shader_src
->kc_bank
;
3895 bc_src
->kc_rel
= shader_src
->kc_rel
;
3898 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src
*bc_src
)
3904 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src
*bc_src
)
3906 bc_src
->neg
= !bc_src
->neg
;
3909 static void tgsi_dst(struct r600_shader_ctx
*ctx
,
3910 const struct tgsi_full_dst_register
*tgsi_dst
,
3912 struct r600_bytecode_alu_dst
*r600_dst
)
3914 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3916 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
3917 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
3918 r600_dst
->chan
= swizzle
;
3919 r600_dst
->write
= 1;
3920 if (inst
->Instruction
.Saturate
) {
3921 r600_dst
->clamp
= 1;
3923 if (ctx
->type
== PIPE_SHADER_TESS_CTRL
) {
3924 if (tgsi_dst
->Register
.File
== TGSI_FILE_OUTPUT
) {
3928 if (tgsi_dst
->Register
.Indirect
)
3929 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
3933 static int tgsi_op2_64_params(struct r600_shader_ctx
*ctx
, bool singledest
, bool swap
, int dest_temp
, int op_override
)
3935 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
3936 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
3937 struct r600_bytecode_alu alu
;
3938 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
3940 int swizzle_x
= inst
->Src
[0].Register
.SwizzleX
;
3943 switch (write_mask
) {
3945 if (swizzle_x
== 2) {
3952 if (swizzle_x
== 2) {
3961 if (swizzle_x
== 0) {
3968 if (swizzle_x
== 0) {
3979 lasti
= tgsi_last_instruction(write_mask
);
3980 for (i
= 0; i
<= lasti
; i
++) {
3982 if (!(write_mask
& (1 << i
)))
3985 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
3988 if (use_tmp
|| dest_temp
) {
3989 alu
.dst
.sel
= use_tmp
? ctx
->temp_reg
: dest_temp
;
3993 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
3995 if (i
== 1 || i
== 3)
3998 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4000 alu
.op
= op_override
? op_override
: ctx
->inst_info
->op
;
4001 if (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DABS
) {
4002 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4004 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4005 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4008 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], fp64_switch(i
));
4009 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], fp64_switch(i
));
4012 /* handle some special cases */
4013 if (i
== 1 || i
== 3) {
4014 switch (ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
) {
4015 case TGSI_OPCODE_DABS
:
4016 r600_bytecode_src_set_abs(&alu
.src
[0]);
4025 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4031 write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4033 lasti
= tgsi_last_instruction(write_mask
);
4034 /* move result from temp to dst */
4035 for (i
= 0; i
<= lasti
; i
++) {
4036 if (!(write_mask
& (1 << i
)))
4039 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4040 alu
.op
= ALU_OP1_MOV
;
4043 alu
.dst
.sel
= dest_temp
;
4047 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4048 alu
.src
[0].sel
= ctx
->temp_reg
;
4049 alu
.src
[0].chan
= use_tmp
- 1;
4050 alu
.last
= (i
== lasti
);
4052 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4060 static int tgsi_op2_64(struct r600_shader_ctx
*ctx
)
4062 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4063 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4064 /* confirm writemasking */
4065 if ((write_mask
& 0x3) != 0x3 &&
4066 (write_mask
& 0xc) != 0xc) {
4067 fprintf(stderr
, "illegal writemask for 64-bit: 0x%x\n", write_mask
);
4070 return tgsi_op2_64_params(ctx
, false, false, 0, 0);
4073 static int tgsi_op2_64_single_dest(struct r600_shader_ctx
*ctx
)
4075 return tgsi_op2_64_params(ctx
, true, false, 0, 0);
4078 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx
*ctx
)
4080 return tgsi_op2_64_params(ctx
, true, true, 0, 0);
4083 static int tgsi_op3_64(struct r600_shader_ctx
*ctx
)
4085 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4086 struct r600_bytecode_alu alu
;
4089 int tmp
= r600_get_temp(ctx
);
4091 for (i
= 0; i
< lasti
+ 1; i
++) {
4093 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4094 alu
.op
= ctx
->inst_info
->op
;
4095 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4096 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
== 3 ? 0 : 1);
4099 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
))
4100 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4109 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4116 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
, int trans_only
)
4118 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4119 struct r600_bytecode_alu alu
;
4120 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4121 int i
, j
, r
, lasti
= tgsi_last_instruction(write_mask
);
4122 /* use temp register if trans_only and more than one dst component */
4123 int use_tmp
= trans_only
&& (write_mask
^ (1 << lasti
));
4124 unsigned op
= ctx
->inst_info
->op
;
4126 if (op
== ALU_OP2_MUL_IEEE
&&
4127 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
4130 for (i
= 0; i
<= lasti
; i
++) {
4131 if (!(write_mask
& (1 << i
)))
4134 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4136 alu
.dst
.sel
= ctx
->temp_reg
;
4140 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4144 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4145 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
4148 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
4149 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4151 if (i
== lasti
|| trans_only
) {
4154 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4160 /* move result from temp to dst */
4161 for (i
= 0; i
<= lasti
; i
++) {
4162 if (!(write_mask
& (1 << i
)))
4165 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4166 alu
.op
= ALU_OP1_MOV
;
4167 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4168 alu
.src
[0].sel
= ctx
->temp_reg
;
4169 alu
.src
[0].chan
= i
;
4170 alu
.last
= (i
== lasti
);
4172 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4180 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
4182 return tgsi_op2_s(ctx
, 0, 0);
4185 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
4187 return tgsi_op2_s(ctx
, 1, 0);
4190 static int tgsi_op2_trans(struct r600_shader_ctx
*ctx
)
4192 return tgsi_op2_s(ctx
, 0, 1);
4195 static int tgsi_ineg(struct r600_shader_ctx
*ctx
)
4197 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4198 struct r600_bytecode_alu alu
;
4200 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4202 for (i
= 0; i
< lasti
+ 1; i
++) {
4204 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4206 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4207 alu
.op
= ctx
->inst_info
->op
;
4209 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4211 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4213 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4218 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4226 static int tgsi_dneg(struct r600_shader_ctx
*ctx
)
4228 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4229 struct r600_bytecode_alu alu
;
4231 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4233 for (i
= 0; i
< lasti
+ 1; i
++) {
4235 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4237 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4238 alu
.op
= ALU_OP1_MOV
;
4240 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4242 if (i
== 1 || i
== 3)
4243 r600_bytecode_src_toggle_neg(&alu
.src
[0]);
4244 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4249 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4257 static int tgsi_dfracexp(struct r600_shader_ctx
*ctx
)
4259 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4260 struct r600_bytecode_alu alu
;
4261 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
4264 for (i
= 0; i
<= 3; i
++) {
4265 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4266 alu
.op
= ctx
->inst_info
->op
;
4268 alu
.dst
.sel
= ctx
->temp_reg
;
4271 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4272 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], fp64_switch(i
));
4278 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4283 /* Replicate significand result across channels. */
4284 for (i
= 0; i
<= 3; i
++) {
4285 if (!(write_mask
& (1 << i
)))
4288 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4289 alu
.op
= ALU_OP1_MOV
;
4290 alu
.src
[0].chan
= (i
& 1) + 2;
4291 alu
.src
[0].sel
= ctx
->temp_reg
;
4293 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4296 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4301 for (i
= 0; i
<= 3; i
++) {
4302 if (inst
->Dst
[1].Register
.WriteMask
& (1 << i
)) {
4303 /* MOV third channels to writemask dst1 */
4304 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4305 alu
.op
= ALU_OP1_MOV
;
4306 alu
.src
[0].chan
= 1;
4307 alu
.src
[0].sel
= ctx
->temp_reg
;
4309 tgsi_dst(ctx
, &inst
->Dst
[1], i
, &alu
.dst
);
4311 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4321 static int egcm_int_to_double(struct r600_shader_ctx
*ctx
)
4323 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4324 struct r600_bytecode_alu alu
;
4326 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4328 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_I2D
||
4329 inst
->Instruction
.Opcode
== TGSI_OPCODE_U2D
);
4331 for (i
= 0; i
<= (lasti
+1)/2; i
++) {
4332 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4333 alu
.op
= ctx
->inst_info
->op
;
4335 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
4336 alu
.dst
.sel
= ctx
->temp_reg
;
4341 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4346 for (i
= 0; i
<= lasti
; i
++) {
4347 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4348 alu
.op
= ALU_OP1_FLT32_TO_FLT64
;
4350 alu
.src
[0].chan
= i
/2;
4352 alu
.src
[0].sel
= ctx
->temp_reg
;
4354 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
4355 alu
.src
[0].value
= 0x0;
4357 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4358 alu
.last
= i
== lasti
;
4360 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4368 static int egcm_double_to_int(struct r600_shader_ctx
*ctx
)
4370 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4371 struct r600_bytecode_alu alu
;
4373 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4374 int treg
= r600_get_temp(ctx
);
4375 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_D2I
||
4376 inst
->Instruction
.Opcode
== TGSI_OPCODE_D2U
);
4378 /* do a 64->32 into a temp register */
4379 r
= tgsi_op2_64_params(ctx
, true, false, treg
, ALU_OP1_FLT64_TO_FLT32
);
4383 for (i
= 0; i
<= lasti
; i
++) {
4384 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4386 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4387 alu
.op
= ctx
->inst_info
->op
;
4389 alu
.src
[0].chan
= i
;
4390 alu
.src
[0].sel
= treg
;
4391 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4392 alu
.last
= (i
== lasti
);
4394 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4402 static int cayman_emit_unary_double_raw(struct r600_bytecode
*bc
,
4405 struct r600_shader_src
*src
,
4408 struct r600_bytecode_alu alu
;
4409 const int last_slot
= 3;
4412 /* these have to write the result to X/Y by the looks of it */
4413 for (int i
= 0 ; i
< last_slot
; i
++) {
4414 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4417 r600_bytecode_src(&alu
.src
[0], src
, 1);
4418 r600_bytecode_src(&alu
.src
[1], src
, 0);
4421 r600_bytecode_src_set_abs(&alu
.src
[1]);
4423 alu
.dst
.sel
= dst_reg
;
4425 alu
.dst
.write
= (i
== 0 || i
== 1);
4427 if (bc
->chip_class
!= CAYMAN
|| i
== last_slot
- 1)
4429 r
= r600_bytecode_add_alu(bc
, &alu
);
4437 static int cayman_emit_double_instr(struct r600_shader_ctx
*ctx
)
4439 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4441 struct r600_bytecode_alu alu
;
4442 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4443 int t1
= ctx
->temp_reg
;
4445 /* should only be one src regs */
4446 assert(inst
->Instruction
.NumSrcRegs
== 1);
4448 /* only support one double at a time */
4449 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4450 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4452 r
= cayman_emit_unary_double_raw(
4453 ctx
->bc
, ctx
->inst_info
->op
, t1
,
4455 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DRSQ
||
4456 ctx
->parse
.FullToken
.FullInstruction
.Instruction
.Opcode
== TGSI_OPCODE_DSQRT
);
4460 for (i
= 0 ; i
<= lasti
; i
++) {
4461 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4463 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4464 alu
.op
= ALU_OP1_MOV
;
4465 alu
.src
[0].sel
= t1
;
4466 alu
.src
[0].chan
= (i
== 0 || i
== 2) ? 0 : 1;
4467 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4471 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4478 static int cayman_emit_float_instr(struct r600_shader_ctx
*ctx
)
4480 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4482 struct r600_bytecode_alu alu
;
4483 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4485 for (i
= 0 ; i
< last_slot
; i
++) {
4486 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4487 alu
.op
= ctx
->inst_info
->op
;
4488 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4489 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], 0);
4491 /* RSQ should take the absolute value of src */
4492 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RSQ
) {
4493 r600_bytecode_src_set_abs(&alu
.src
[j
]);
4496 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4497 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4499 if (i
== last_slot
- 1)
4501 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4508 static int cayman_mul_int_instr(struct r600_shader_ctx
*ctx
)
4510 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4512 struct r600_bytecode_alu alu
;
4513 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4514 int t1
= ctx
->temp_reg
;
4516 for (k
= 0; k
<= lasti
; k
++) {
4517 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << k
)))
4520 for (i
= 0 ; i
< 4; i
++) {
4521 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4522 alu
.op
= ctx
->inst_info
->op
;
4523 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4524 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
);
4528 alu
.dst
.write
= (i
== k
);
4531 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4537 for (i
= 0 ; i
<= lasti
; i
++) {
4538 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4540 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4541 alu
.op
= ALU_OP1_MOV
;
4542 alu
.src
[0].sel
= t1
;
4543 alu
.src
[0].chan
= i
;
4544 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4548 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4557 static int cayman_mul_double_instr(struct r600_shader_ctx
*ctx
)
4559 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4561 struct r600_bytecode_alu alu
;
4562 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4563 int t1
= ctx
->temp_reg
;
4565 /* t1 would get overwritten below if we actually tried to
4566 * multiply two pairs of doubles at a time. */
4567 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4568 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4570 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4572 for (i
= 0; i
< 4; i
++) {
4573 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4574 alu
.op
= ctx
->inst_info
->op
;
4575 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
4576 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], k
* 2 + ((i
== 3) ? 0 : 1));
4583 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4588 for (i
= 0; i
<= lasti
; i
++) {
4589 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4591 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4592 alu
.op
= ALU_OP1_MOV
;
4593 alu
.src
[0].sel
= t1
;
4594 alu
.src
[0].chan
= i
;
4595 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4599 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4608 * Emit RECIP_64 + MUL_64 to implement division.
4610 static int cayman_ddiv_instr(struct r600_shader_ctx
*ctx
)
4612 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4614 struct r600_bytecode_alu alu
;
4615 int t1
= ctx
->temp_reg
;
4618 /* Only support one double at a time. This is the same constraint as
4619 * in DMUL lowering. */
4620 assert(inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
||
4621 inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_ZW
);
4623 k
= inst
->Dst
[0].Register
.WriteMask
== TGSI_WRITEMASK_XY
? 0 : 1;
4625 r
= cayman_emit_unary_double_raw(ctx
->bc
, ALU_OP2_RECIP_64
, t1
, &ctx
->src
[1], false);
4629 for (int i
= 0; i
< 4; i
++) {
4630 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4631 alu
.op
= ALU_OP2_MUL_64
;
4633 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], k
* 2 + ((i
== 3) ? 0 : 1));
4635 alu
.src
[1].sel
= t1
;
4636 alu
.src
[1].chan
= (i
== 3) ? 0 : 1;
4643 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4648 for (int i
= 0; i
< 2; i
++) {
4649 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4650 alu
.op
= ALU_OP1_MOV
;
4651 alu
.src
[0].sel
= t1
;
4652 alu
.src
[0].chan
= i
;
4653 tgsi_dst(ctx
, &inst
->Dst
[0], k
* 2 + i
, &alu
.dst
);
4657 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4665 * r600 - trunc to -PI..PI range
4666 * r700 - normalize by dividing by 2PI
4669 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
)
4672 struct r600_bytecode_alu alu
;
4674 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4675 alu
.op
= ALU_OP3_MULADD
;
4679 alu
.dst
.sel
= ctx
->temp_reg
;
4682 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4684 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4685 alu
.src
[1].chan
= 0;
4686 alu
.src
[1].value
= u_bitcast_f2u(0.5f
* M_1_PI
);
4687 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4688 alu
.src
[2].chan
= 0;
4690 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4694 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4695 alu
.op
= ALU_OP1_FRACT
;
4698 alu
.dst
.sel
= ctx
->temp_reg
;
4701 alu
.src
[0].sel
= ctx
->temp_reg
;
4702 alu
.src
[0].chan
= 0;
4704 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4708 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4709 alu
.op
= ALU_OP3_MULADD
;
4713 alu
.dst
.sel
= ctx
->temp_reg
;
4716 alu
.src
[0].sel
= ctx
->temp_reg
;
4717 alu
.src
[0].chan
= 0;
4719 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
4720 alu
.src
[1].chan
= 0;
4721 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
4722 alu
.src
[2].chan
= 0;
4724 if (ctx
->bc
->chip_class
== R600
) {
4725 alu
.src
[1].value
= u_bitcast_f2u(2.0f
* M_PI
);
4726 alu
.src
[2].value
= u_bitcast_f2u(-M_PI
);
4728 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4729 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
4734 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4740 static int cayman_trig(struct r600_shader_ctx
*ctx
)
4742 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4743 struct r600_bytecode_alu alu
;
4744 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
4747 r
= tgsi_setup_trig(ctx
);
4752 for (i
= 0; i
< last_slot
; i
++) {
4753 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4754 alu
.op
= ctx
->inst_info
->op
;
4757 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4758 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
4760 alu
.src
[0].sel
= ctx
->temp_reg
;
4761 alu
.src
[0].chan
= 0;
4762 if (i
== last_slot
- 1)
4764 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4771 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
4773 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4774 struct r600_bytecode_alu alu
;
4776 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
4778 r
= tgsi_setup_trig(ctx
);
4782 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4783 alu
.op
= ctx
->inst_info
->op
;
4785 alu
.dst
.sel
= ctx
->temp_reg
;
4788 alu
.src
[0].sel
= ctx
->temp_reg
;
4789 alu
.src
[0].chan
= 0;
4791 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4795 /* replicate result */
4796 for (i
= 0; i
< lasti
+ 1; i
++) {
4797 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
4800 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4801 alu
.op
= ALU_OP1_MOV
;
4803 alu
.src
[0].sel
= ctx
->temp_reg
;
4804 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4807 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4814 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
4816 const struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4817 struct r600_bytecode_alu alu
;
4820 for (i
= 0; i
< 4; i
++) {
4821 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4822 alu
.op
= ctx
->inst_info
->op
;
4826 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
4828 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_KILL
) {
4829 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
4832 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
4837 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4842 /* kill must be last in ALU */
4843 ctx
->bc
->force_add_cf
= 1;
4844 ctx
->shader
->uses_kill
= TRUE
;
4848 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
4850 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
4851 struct r600_bytecode_alu alu
;
4854 /* tmp.x = max(src.y, 0.0) */
4855 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4856 alu
.op
= ALU_OP2_MAX
;
4857 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
4858 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4859 alu
.src
[1].chan
= 1;
4861 alu
.dst
.sel
= ctx
->temp_reg
;
4866 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4870 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
4876 if (ctx
->bc
->chip_class
== CAYMAN
) {
4877 for (i
= 0; i
< 3; i
++) {
4878 /* tmp.z = log(tmp.x) */
4879 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4880 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4881 alu
.src
[0].sel
= ctx
->temp_reg
;
4882 alu
.src
[0].chan
= 0;
4883 alu
.dst
.sel
= ctx
->temp_reg
;
4891 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4896 /* tmp.z = log(tmp.x) */
4897 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4898 alu
.op
= ALU_OP1_LOG_CLAMPED
;
4899 alu
.src
[0].sel
= ctx
->temp_reg
;
4900 alu
.src
[0].chan
= 0;
4901 alu
.dst
.sel
= ctx
->temp_reg
;
4905 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4910 chan
= alu
.dst
.chan
;
4913 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4914 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4915 alu
.op
= ALU_OP3_MUL_LIT
;
4916 alu
.src
[0].sel
= sel
;
4917 alu
.src
[0].chan
= chan
;
4918 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], 3);
4919 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], 0);
4920 alu
.dst
.sel
= ctx
->temp_reg
;
4925 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4929 if (ctx
->bc
->chip_class
== CAYMAN
) {
4930 for (i
= 0; i
< 3; i
++) {
4931 /* dst.z = exp(tmp.x) */
4932 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4933 alu
.op
= ALU_OP1_EXP_IEEE
;
4934 alu
.src
[0].sel
= ctx
->temp_reg
;
4935 alu
.src
[0].chan
= 0;
4936 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
4942 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4947 /* dst.z = exp(tmp.x) */
4948 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4949 alu
.op
= ALU_OP1_EXP_IEEE
;
4950 alu
.src
[0].sel
= ctx
->temp_reg
;
4951 alu
.src
[0].chan
= 0;
4952 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
4954 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4961 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4962 alu
.op
= ALU_OP1_MOV
;
4963 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
4964 alu
.src
[0].chan
= 0;
4965 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
4966 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
4967 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4971 /* dst.y = max(src.x, 0.0) */
4972 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4973 alu
.op
= ALU_OP2_MAX
;
4974 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
4975 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
4976 alu
.src
[1].chan
= 0;
4977 tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
4978 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
4979 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4984 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
4985 alu
.op
= ALU_OP1_MOV
;
4986 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
4987 alu
.src
[0].chan
= 0;
4988 tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
4989 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
4991 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
4998 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
5000 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5001 struct r600_bytecode_alu alu
;
5004 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5006 alu
.op
= ALU_OP1_RECIPSQRT_IEEE
;
5008 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
5009 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
5010 r600_bytecode_src_set_abs(&alu
.src
[i
]);
5012 alu
.dst
.sel
= ctx
->temp_reg
;
5015 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5018 /* replicate result */
5019 return tgsi_helper_tempx_replicate(ctx
);
5022 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
5024 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5025 struct r600_bytecode_alu alu
;
5028 for (i
= 0; i
< 4; i
++) {
5029 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5030 alu
.src
[0].sel
= ctx
->temp_reg
;
5031 alu
.op
= ALU_OP1_MOV
;
5033 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5034 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
5037 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5044 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
5046 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5047 struct r600_bytecode_alu alu
;
5050 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5051 alu
.op
= ctx
->inst_info
->op
;
5052 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
5053 r600_bytecode_src(&alu
.src
[i
], &ctx
->src
[i
], 0);
5055 alu
.dst
.sel
= ctx
->temp_reg
;
5058 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5061 /* replicate result */
5062 return tgsi_helper_tempx_replicate(ctx
);
5065 static int cayman_pow(struct r600_shader_ctx
*ctx
)
5067 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5069 struct r600_bytecode_alu alu
;
5070 int last_slot
= (inst
->Dst
[0].Register
.WriteMask
& 0x8) ? 4 : 3;
5072 for (i
= 0; i
< 3; i
++) {
5073 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5074 alu
.op
= ALU_OP1_LOG_IEEE
;
5075 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5076 alu
.dst
.sel
= ctx
->temp_reg
;
5081 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5087 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5088 alu
.op
= ALU_OP2_MUL
;
5089 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5090 alu
.src
[1].sel
= ctx
->temp_reg
;
5091 alu
.dst
.sel
= ctx
->temp_reg
;
5094 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5098 for (i
= 0; i
< last_slot
; i
++) {
5099 /* POW(a,b) = EXP2(b * LOG2(a))*/
5100 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5101 alu
.op
= ALU_OP1_EXP_IEEE
;
5102 alu
.src
[0].sel
= ctx
->temp_reg
;
5104 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5105 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
5106 if (i
== last_slot
- 1)
5108 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5115 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
5117 struct r600_bytecode_alu alu
;
5121 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5122 alu
.op
= ALU_OP1_LOG_IEEE
;
5123 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
5124 alu
.dst
.sel
= ctx
->temp_reg
;
5127 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5131 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5132 alu
.op
= ALU_OP2_MUL
;
5133 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
5134 alu
.src
[1].sel
= ctx
->temp_reg
;
5135 alu
.dst
.sel
= ctx
->temp_reg
;
5138 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5141 /* POW(a,b) = EXP2(b * LOG2(a))*/
5142 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5143 alu
.op
= ALU_OP1_EXP_IEEE
;
5144 alu
.src
[0].sel
= ctx
->temp_reg
;
5145 alu
.dst
.sel
= ctx
->temp_reg
;
5148 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5151 return tgsi_helper_tempx_replicate(ctx
);
5154 static int tgsi_divmod(struct r600_shader_ctx
*ctx
, int mod
, int signed_op
)
5156 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
5157 struct r600_bytecode_alu alu
;
5159 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
5160 int tmp0
= ctx
->temp_reg
;
5161 int tmp1
= r600_get_temp(ctx
);
5162 int tmp2
= r600_get_temp(ctx
);
5163 int tmp3
= r600_get_temp(ctx
);
5166 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5168 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5169 * 2. tmp0.z = lo (tmp0.x * src2)
5170 * 3. tmp0.w = -tmp0.z
5171 * 4. tmp0.y = hi (tmp0.x * src2)
5172 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5173 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5174 * 7. tmp1.x = tmp0.x - tmp0.w
5175 * 8. tmp1.y = tmp0.x + tmp0.w
5176 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5177 * 10. tmp0.z = hi(tmp0.x * src1) = q
5178 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5180 * 12. tmp0.w = src1 - tmp0.y = r
5181 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5182 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5186 * 15. tmp1.z = tmp0.z + 1 = q + 1
5187 * 16. tmp1.w = tmp0.z - 1 = q - 1
5191 * 15. tmp1.z = tmp0.w - src2 = r - src2
5192 * 16. tmp1.w = tmp0.w + src2 = r + src2
5196 * 17. tmp1.x = tmp1.x & tmp1.y
5198 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5199 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5201 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5202 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5206 * Same as unsigned, using abs values of the operands,
5207 * and fixing the sign of the result in the end.
5210 for (i
= 0; i
< 4; i
++) {
5211 if (!(write_mask
& (1<<i
)))
5216 /* tmp2.x = -src0 */
5217 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5218 alu
.op
= ALU_OP2_SUB_INT
;
5224 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5226 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5229 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5232 /* tmp2.y = -src1 */
5233 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5234 alu
.op
= ALU_OP2_SUB_INT
;
5240 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5242 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5245 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5248 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5249 /* it will be a sign of the quotient */
5252 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5253 alu
.op
= ALU_OP2_XOR_INT
;
5259 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5260 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5263 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5267 /* tmp2.x = |src0| */
5268 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5269 alu
.op
= ALU_OP3_CNDGE_INT
;
5276 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5277 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5278 alu
.src
[2].sel
= tmp2
;
5279 alu
.src
[2].chan
= 0;
5282 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5285 /* tmp2.y = |src1| */
5286 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5287 alu
.op
= ALU_OP3_CNDGE_INT
;
5294 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5295 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5296 alu
.src
[2].sel
= tmp2
;
5297 alu
.src
[2].chan
= 1;
5300 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5305 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5306 if (ctx
->bc
->chip_class
== CAYMAN
) {
5307 /* tmp3.x = u2f(src2) */
5308 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5309 alu
.op
= ALU_OP1_UINT_TO_FLT
;
5316 alu
.src
[0].sel
= tmp2
;
5317 alu
.src
[0].chan
= 1;
5319 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5323 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5326 /* tmp0.x = recip(tmp3.x) */
5327 for (j
= 0 ; j
< 3; j
++) {
5328 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5329 alu
.op
= ALU_OP1_RECIP_IEEE
;
5333 alu
.dst
.write
= (j
== 0);
5335 alu
.src
[0].sel
= tmp3
;
5336 alu
.src
[0].chan
= 0;
5340 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5344 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5345 alu
.op
= ALU_OP2_MUL
;
5347 alu
.src
[0].sel
= tmp0
;
5348 alu
.src
[0].chan
= 0;
5350 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
5351 alu
.src
[1].value
= 0x4f800000;
5356 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
5360 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5361 alu
.op
= ALU_OP1_FLT_TO_UINT
;
5367 alu
.src
[0].sel
= tmp3
;
5368 alu
.src
[0].chan
= 0;
5371 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5375 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5376 alu
.op
= ALU_OP1_RECIP_UINT
;
5383 alu
.src
[0].sel
= tmp2
;
5384 alu
.src
[0].chan
= 1;
5386 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5390 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5394 /* 2. tmp0.z = lo (tmp0.x * src2) */
5395 if (ctx
->bc
->chip_class
== CAYMAN
) {
5396 for (j
= 0 ; j
< 4; j
++) {
5397 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5398 alu
.op
= ALU_OP2_MULLO_UINT
;
5402 alu
.dst
.write
= (j
== 2);
5404 alu
.src
[0].sel
= tmp0
;
5405 alu
.src
[0].chan
= 0;
5407 alu
.src
[1].sel
= tmp2
;
5408 alu
.src
[1].chan
= 1;
5410 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5413 alu
.last
= (j
== 3);
5414 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5418 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5419 alu
.op
= ALU_OP2_MULLO_UINT
;
5425 alu
.src
[0].sel
= tmp0
;
5426 alu
.src
[0].chan
= 0;
5428 alu
.src
[1].sel
= tmp2
;
5429 alu
.src
[1].chan
= 1;
5431 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5435 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5439 /* 3. tmp0.w = -tmp0.z */
5440 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5441 alu
.op
= ALU_OP2_SUB_INT
;
5447 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5448 alu
.src
[1].sel
= tmp0
;
5449 alu
.src
[1].chan
= 2;
5452 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5455 /* 4. tmp0.y = hi (tmp0.x * src2) */
5456 if (ctx
->bc
->chip_class
== CAYMAN
) {
5457 for (j
= 0 ; j
< 4; j
++) {
5458 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5459 alu
.op
= ALU_OP2_MULHI_UINT
;
5463 alu
.dst
.write
= (j
== 1);
5465 alu
.src
[0].sel
= tmp0
;
5466 alu
.src
[0].chan
= 0;
5469 alu
.src
[1].sel
= tmp2
;
5470 alu
.src
[1].chan
= 1;
5472 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5474 alu
.last
= (j
== 3);
5475 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5479 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5480 alu
.op
= ALU_OP2_MULHI_UINT
;
5486 alu
.src
[0].sel
= tmp0
;
5487 alu
.src
[0].chan
= 0;
5490 alu
.src
[1].sel
= tmp2
;
5491 alu
.src
[1].chan
= 1;
5493 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5497 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5501 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5502 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5503 alu
.op
= ALU_OP3_CNDE_INT
;
5510 alu
.src
[0].sel
= tmp0
;
5511 alu
.src
[0].chan
= 1;
5512 alu
.src
[1].sel
= tmp0
;
5513 alu
.src
[1].chan
= 3;
5514 alu
.src
[2].sel
= tmp0
;
5515 alu
.src
[2].chan
= 2;
5518 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5521 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5522 if (ctx
->bc
->chip_class
== CAYMAN
) {
5523 for (j
= 0 ; j
< 4; j
++) {
5524 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5525 alu
.op
= ALU_OP2_MULHI_UINT
;
5529 alu
.dst
.write
= (j
== 3);
5531 alu
.src
[0].sel
= tmp0
;
5532 alu
.src
[0].chan
= 2;
5534 alu
.src
[1].sel
= tmp0
;
5535 alu
.src
[1].chan
= 0;
5537 alu
.last
= (j
== 3);
5538 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5542 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5543 alu
.op
= ALU_OP2_MULHI_UINT
;
5549 alu
.src
[0].sel
= tmp0
;
5550 alu
.src
[0].chan
= 2;
5552 alu
.src
[1].sel
= tmp0
;
5553 alu
.src
[1].chan
= 0;
5556 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5560 /* 7. tmp1.x = tmp0.x - tmp0.w */
5561 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5562 alu
.op
= ALU_OP2_SUB_INT
;
5568 alu
.src
[0].sel
= tmp0
;
5569 alu
.src
[0].chan
= 0;
5570 alu
.src
[1].sel
= tmp0
;
5571 alu
.src
[1].chan
= 3;
5574 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5577 /* 8. tmp1.y = tmp0.x + tmp0.w */
5578 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5579 alu
.op
= ALU_OP2_ADD_INT
;
5585 alu
.src
[0].sel
= tmp0
;
5586 alu
.src
[0].chan
= 0;
5587 alu
.src
[1].sel
= tmp0
;
5588 alu
.src
[1].chan
= 3;
5591 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5594 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5595 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5596 alu
.op
= ALU_OP3_CNDE_INT
;
5603 alu
.src
[0].sel
= tmp0
;
5604 alu
.src
[0].chan
= 1;
5605 alu
.src
[1].sel
= tmp1
;
5606 alu
.src
[1].chan
= 1;
5607 alu
.src
[2].sel
= tmp1
;
5608 alu
.src
[2].chan
= 0;
5611 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5614 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5615 if (ctx
->bc
->chip_class
== CAYMAN
) {
5616 for (j
= 0 ; j
< 4; j
++) {
5617 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5618 alu
.op
= ALU_OP2_MULHI_UINT
;
5622 alu
.dst
.write
= (j
== 2);
5624 alu
.src
[0].sel
= tmp0
;
5625 alu
.src
[0].chan
= 0;
5628 alu
.src
[1].sel
= tmp2
;
5629 alu
.src
[1].chan
= 0;
5631 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5634 alu
.last
= (j
== 3);
5635 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5639 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5640 alu
.op
= ALU_OP2_MULHI_UINT
;
5646 alu
.src
[0].sel
= tmp0
;
5647 alu
.src
[0].chan
= 0;
5650 alu
.src
[1].sel
= tmp2
;
5651 alu
.src
[1].chan
= 0;
5653 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
5657 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5661 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5662 if (ctx
->bc
->chip_class
== CAYMAN
) {
5663 for (j
= 0 ; j
< 4; j
++) {
5664 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5665 alu
.op
= ALU_OP2_MULLO_UINT
;
5669 alu
.dst
.write
= (j
== 1);
5672 alu
.src
[0].sel
= tmp2
;
5673 alu
.src
[0].chan
= 1;
5675 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5678 alu
.src
[1].sel
= tmp0
;
5679 alu
.src
[1].chan
= 2;
5681 alu
.last
= (j
== 3);
5682 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5686 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5687 alu
.op
= ALU_OP2_MULLO_UINT
;
5694 alu
.src
[0].sel
= tmp2
;
5695 alu
.src
[0].chan
= 1;
5697 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
5700 alu
.src
[1].sel
= tmp0
;
5701 alu
.src
[1].chan
= 2;
5704 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5708 /* 12. tmp0.w = src1 - tmp0.y = r */
5709 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5710 alu
.op
= ALU_OP2_SUB_INT
;
5717 alu
.src
[0].sel
= tmp2
;
5718 alu
.src
[0].chan
= 0;
5720 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5723 alu
.src
[1].sel
= tmp0
;
5724 alu
.src
[1].chan
= 1;
5727 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5730 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5731 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5732 alu
.op
= ALU_OP2_SETGE_UINT
;
5738 alu
.src
[0].sel
= tmp0
;
5739 alu
.src
[0].chan
= 3;
5741 alu
.src
[1].sel
= tmp2
;
5742 alu
.src
[1].chan
= 1;
5744 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5748 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5751 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5752 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5753 alu
.op
= ALU_OP2_SETGE_UINT
;
5760 alu
.src
[0].sel
= tmp2
;
5761 alu
.src
[0].chan
= 0;
5763 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5766 alu
.src
[1].sel
= tmp0
;
5767 alu
.src
[1].chan
= 1;
5770 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5773 if (mod
) { /* UMOD */
5775 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5776 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5777 alu
.op
= ALU_OP2_SUB_INT
;
5783 alu
.src
[0].sel
= tmp0
;
5784 alu
.src
[0].chan
= 3;
5787 alu
.src
[1].sel
= tmp2
;
5788 alu
.src
[1].chan
= 1;
5790 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5794 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5797 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5798 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5799 alu
.op
= ALU_OP2_ADD_INT
;
5805 alu
.src
[0].sel
= tmp0
;
5806 alu
.src
[0].chan
= 3;
5808 alu
.src
[1].sel
= tmp2
;
5809 alu
.src
[1].chan
= 1;
5811 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
5815 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5820 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5821 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5822 alu
.op
= ALU_OP2_ADD_INT
;
5828 alu
.src
[0].sel
= tmp0
;
5829 alu
.src
[0].chan
= 2;
5830 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
5833 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5836 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5837 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5838 alu
.op
= ALU_OP2_ADD_INT
;
5844 alu
.src
[0].sel
= tmp0
;
5845 alu
.src
[0].chan
= 2;
5846 alu
.src
[1].sel
= V_SQ_ALU_SRC_M_1_INT
;
5849 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5854 /* 17. tmp1.x = tmp1.x & tmp1.y */
5855 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5856 alu
.op
= ALU_OP2_AND_INT
;
5862 alu
.src
[0].sel
= tmp1
;
5863 alu
.src
[0].chan
= 0;
5864 alu
.src
[1].sel
= tmp1
;
5865 alu
.src
[1].chan
= 1;
5868 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5871 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5872 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5873 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5874 alu
.op
= ALU_OP3_CNDE_INT
;
5881 alu
.src
[0].sel
= tmp1
;
5882 alu
.src
[0].chan
= 0;
5883 alu
.src
[1].sel
= tmp0
;
5884 alu
.src
[1].chan
= mod
? 3 : 2;
5885 alu
.src
[2].sel
= tmp1
;
5886 alu
.src
[2].chan
= 2;
5889 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5892 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5893 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5894 alu
.op
= ALU_OP3_CNDE_INT
;
5902 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5905 alu
.src
[0].sel
= tmp1
;
5906 alu
.src
[0].chan
= 1;
5907 alu
.src
[1].sel
= tmp1
;
5908 alu
.src
[1].chan
= 3;
5909 alu
.src
[2].sel
= tmp0
;
5910 alu
.src
[2].chan
= 2;
5913 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5918 /* fix the sign of the result */
5922 /* tmp0.x = -tmp0.z */
5923 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5924 alu
.op
= ALU_OP2_SUB_INT
;
5930 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5931 alu
.src
[1].sel
= tmp0
;
5932 alu
.src
[1].chan
= 2;
5935 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5938 /* sign of the remainder is the same as the sign of src0 */
5939 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5940 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5941 alu
.op
= ALU_OP3_CNDGE_INT
;
5944 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5946 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
5947 alu
.src
[1].sel
= tmp0
;
5948 alu
.src
[1].chan
= 2;
5949 alu
.src
[2].sel
= tmp0
;
5950 alu
.src
[2].chan
= 0;
5953 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5958 /* tmp0.x = -tmp0.z */
5959 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5960 alu
.op
= ALU_OP2_SUB_INT
;
5966 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
5967 alu
.src
[1].sel
= tmp0
;
5968 alu
.src
[1].chan
= 2;
5971 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5974 /* fix the quotient sign (same as the sign of src0*src1) */
5975 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5976 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
5977 alu
.op
= ALU_OP3_CNDGE_INT
;
5980 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
5982 alu
.src
[0].sel
= tmp2
;
5983 alu
.src
[0].chan
= 2;
5984 alu
.src
[1].sel
= tmp0
;
5985 alu
.src
[1].chan
= 2;
5986 alu
.src
[2].sel
= tmp0
;
5987 alu
.src
[2].chan
= 0;
5990 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
5998 static int tgsi_udiv(struct r600_shader_ctx
*ctx
)
6000 return tgsi_divmod(ctx
, 0, 0);
6003 static int tgsi_umod(struct r600_shader_ctx
*ctx
)
6005 return tgsi_divmod(ctx
, 1, 0);
6008 static int tgsi_idiv(struct r600_shader_ctx
*ctx
)
6010 return tgsi_divmod(ctx
, 0, 1);
6013 static int tgsi_imod(struct r600_shader_ctx
*ctx
)
6015 return tgsi_divmod(ctx
, 1, 1);
6019 static int tgsi_f2i(struct r600_shader_ctx
*ctx
)
6021 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6022 struct r600_bytecode_alu alu
;
6024 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6025 int last_inst
= tgsi_last_instruction(write_mask
);
6027 for (i
= 0; i
< 4; i
++) {
6028 if (!(write_mask
& (1<<i
)))
6031 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6032 alu
.op
= ALU_OP1_TRUNC
;
6034 alu
.dst
.sel
= ctx
->temp_reg
;
6038 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6041 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6046 for (i
= 0; i
< 4; i
++) {
6047 if (!(write_mask
& (1<<i
)))
6050 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6051 alu
.op
= ctx
->inst_info
->op
;
6053 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6055 alu
.src
[0].sel
= ctx
->temp_reg
;
6056 alu
.src
[0].chan
= i
;
6058 if (i
== last_inst
|| alu
.op
== ALU_OP1_FLT_TO_UINT
)
6060 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6068 static int tgsi_iabs(struct r600_shader_ctx
*ctx
)
6070 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6071 struct r600_bytecode_alu alu
;
6073 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6074 int last_inst
= tgsi_last_instruction(write_mask
);
6077 for (i
= 0; i
< 4; i
++) {
6078 if (!(write_mask
& (1<<i
)))
6081 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6082 alu
.op
= ALU_OP2_SUB_INT
;
6084 alu
.dst
.sel
= ctx
->temp_reg
;
6088 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6089 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
6093 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6098 /* dst = (src >= 0 ? src : tmp) */
6099 for (i
= 0; i
< 4; i
++) {
6100 if (!(write_mask
& (1<<i
)))
6103 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6104 alu
.op
= ALU_OP3_CNDGE_INT
;
6108 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6110 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6111 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6112 alu
.src
[2].sel
= ctx
->temp_reg
;
6113 alu
.src
[2].chan
= i
;
6117 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6124 static int tgsi_issg(struct r600_shader_ctx
*ctx
)
6126 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6127 struct r600_bytecode_alu alu
;
6129 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6130 int last_inst
= tgsi_last_instruction(write_mask
);
6132 /* tmp = (src >= 0 ? src : -1) */
6133 for (i
= 0; i
< 4; i
++) {
6134 if (!(write_mask
& (1<<i
)))
6137 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6138 alu
.op
= ALU_OP3_CNDGE_INT
;
6141 alu
.dst
.sel
= ctx
->temp_reg
;
6145 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6146 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
6147 alu
.src
[2].sel
= V_SQ_ALU_SRC_M_1_INT
;
6151 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6156 /* dst = (tmp > 0 ? 1 : tmp) */
6157 for (i
= 0; i
< 4; i
++) {
6158 if (!(write_mask
& (1<<i
)))
6161 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6162 alu
.op
= ALU_OP3_CNDGT_INT
;
6166 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6168 alu
.src
[0].sel
= ctx
->temp_reg
;
6169 alu
.src
[0].chan
= i
;
6171 alu
.src
[1].sel
= V_SQ_ALU_SRC_1_INT
;
6173 alu
.src
[2].sel
= ctx
->temp_reg
;
6174 alu
.src
[2].chan
= i
;
6178 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6187 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
6189 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6190 struct r600_bytecode_alu alu
;
6193 /* tmp = (src > 0 ? 1 : src) */
6194 for (i
= 0; i
< 4; i
++) {
6195 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6196 alu
.op
= ALU_OP3_CNDGT
;
6199 alu
.dst
.sel
= ctx
->temp_reg
;
6202 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6203 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6204 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6208 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6213 /* dst = (-tmp > 0 ? -1 : tmp) */
6214 for (i
= 0; i
< 4; i
++) {
6215 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6216 alu
.op
= ALU_OP3_CNDGT
;
6218 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6220 alu
.src
[0].sel
= ctx
->temp_reg
;
6221 alu
.src
[0].chan
= i
;
6224 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
6227 alu
.src
[2].sel
= ctx
->temp_reg
;
6228 alu
.src
[2].chan
= i
;
6232 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6239 static int tgsi_bfi(struct r600_shader_ctx
*ctx
)
6241 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6242 struct r600_bytecode_alu alu
;
6245 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6246 int last_inst
= tgsi_last_instruction(write_mask
);
6248 t1
= r600_get_temp(ctx
);
6250 for (i
= 0; i
< 4; i
++) {
6251 if (!(write_mask
& (1<<i
)))
6254 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6255 alu
.op
= ALU_OP2_SETGE_INT
;
6256 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6257 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
6258 alu
.src
[1].value
= 32;
6259 alu
.dst
.sel
= ctx
->temp_reg
;
6262 alu
.last
= i
== last_inst
;
6263 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6268 for (i
= 0; i
< 4; i
++) {
6269 if (!(write_mask
& (1<<i
)))
6272 /* create mask tmp */
6273 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6274 alu
.op
= ALU_OP2_BFM_INT
;
6278 alu
.last
= i
== last_inst
;
6280 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], i
);
6281 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6283 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6288 t2
= r600_get_temp(ctx
);
6290 for (i
= 0; i
< 4; i
++) {
6291 if (!(write_mask
& (1<<i
)))
6294 /* shift insert left */
6295 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6296 alu
.op
= ALU_OP2_LSHL_INT
;
6300 alu
.last
= i
== last_inst
;
6302 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
6303 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
6305 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6310 for (i
= 0; i
< 4; i
++) {
6311 if (!(write_mask
& (1<<i
)))
6314 /* actual bitfield insert */
6315 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6316 alu
.op
= ALU_OP3_BFI_INT
;
6318 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6321 alu
.last
= i
== last_inst
;
6323 alu
.src
[0].sel
= t1
;
6324 alu
.src
[0].chan
= i
;
6325 alu
.src
[1].sel
= t2
;
6326 alu
.src
[1].chan
= i
;
6327 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
6329 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6334 for (i
= 0; i
< 4; i
++) {
6335 if (!(write_mask
& (1<<i
)))
6337 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6338 alu
.op
= ALU_OP3_CNDE_INT
;
6340 alu
.src
[0].sel
= ctx
->temp_reg
;
6341 alu
.src
[0].chan
= i
;
6342 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
6344 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6346 alu
.src
[1].sel
= alu
.dst
.sel
;
6347 alu
.src
[1].chan
= i
;
6349 alu
.last
= i
== last_inst
;
6350 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6357 static int tgsi_msb(struct r600_shader_ctx
*ctx
)
6359 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6360 struct r600_bytecode_alu alu
;
6363 unsigned write_mask
= inst
->Dst
[0].Register
.WriteMask
;
6364 int last_inst
= tgsi_last_instruction(write_mask
);
6366 assert(ctx
->inst_info
->op
== ALU_OP1_FFBH_INT
||
6367 ctx
->inst_info
->op
== ALU_OP1_FFBH_UINT
);
6371 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6372 for (i
= 0; i
< 4; i
++) {
6373 if (!(write_mask
& (1<<i
)))
6376 /* t1 = FFBH_INT / FFBH_UINT */
6377 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6378 alu
.op
= ctx
->inst_info
->op
;
6382 alu
.last
= i
== last_inst
;
6384 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6386 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6391 t2
= r600_get_temp(ctx
);
6393 for (i
= 0; i
< 4; i
++) {
6394 if (!(write_mask
& (1<<i
)))
6398 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6399 alu
.op
= ALU_OP2_SUB_INT
;
6403 alu
.last
= i
== last_inst
;
6405 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
6406 alu
.src
[0].value
= 31;
6407 alu
.src
[1].sel
= t1
;
6408 alu
.src
[1].chan
= i
;
6410 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6415 for (i
= 0; i
< 4; i
++) {
6416 if (!(write_mask
& (1<<i
)))
6419 /* result = t1 >= 0 ? t2 : t1 */
6420 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6421 alu
.op
= ALU_OP3_CNDGE_INT
;
6423 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6426 alu
.last
= i
== last_inst
;
6428 alu
.src
[0].sel
= t1
;
6429 alu
.src
[0].chan
= i
;
6430 alu
.src
[1].sel
= t2
;
6431 alu
.src
[1].chan
= i
;
6432 alu
.src
[2].sel
= t1
;
6433 alu
.src
[2].chan
= i
;
6435 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6443 static int tgsi_interp_egcm(struct r600_shader_ctx
*ctx
)
6445 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6446 struct r600_bytecode_alu alu
;
6447 int r
, i
= 0, k
, interp_gpr
, interp_base_chan
, tmp
, lasti
;
6449 const int input
= inst
->Src
[0].Register
.Index
+ ctx
->shader
->nsys_inputs
;
6451 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
6453 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6454 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6455 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6456 location
= TGSI_INTERPOLATE_LOC_CENTER
; /* sample offset will be added explicitly */
6459 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
6462 k
= eg_get_interpolator_index(ctx
->shader
->input
[input
].interpolate
, location
);
6465 interp_gpr
= ctx
->eg_interpolators
[k
].ij_index
/ 2;
6466 interp_base_chan
= 2 * (ctx
->eg_interpolators
[k
].ij_index
% 2);
6468 /* NOTE: currently offset is not perspective correct */
6469 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6470 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6471 int sample_gpr
= -1;
6472 int gradientsH
, gradientsV
;
6473 struct r600_bytecode_tex tex
;
6475 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6476 sample_gpr
= load_sample_position(ctx
, &ctx
->src
[1], ctx
->src
[1].swizzle
[0]);
6479 gradientsH
= r600_get_temp(ctx
);
6480 gradientsV
= r600_get_temp(ctx
);
6481 for (i
= 0; i
< 2; i
++) {
6482 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
6483 tex
.op
= i
== 0 ? FETCH_OP_GET_GRADIENTS_H
: FETCH_OP_GET_GRADIENTS_V
;
6484 tex
.src_gpr
= interp_gpr
;
6485 tex
.src_sel_x
= interp_base_chan
+ 0;
6486 tex
.src_sel_y
= interp_base_chan
+ 1;
6489 tex
.dst_gpr
= i
== 0 ? gradientsH
: gradientsV
;
6494 tex
.inst_mod
= 1; // Use per pixel gradient calculation
6496 tex
.resource_id
= tex
.sampler_id
;
6497 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
6502 for (i
= 0; i
< 2; i
++) {
6503 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6504 alu
.op
= ALU_OP3_MULADD
;
6506 alu
.src
[0].sel
= gradientsH
;
6507 alu
.src
[0].chan
= i
;
6508 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6509 alu
.src
[1].sel
= sample_gpr
;
6510 alu
.src
[1].chan
= 2;
6513 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 0);
6515 alu
.src
[2].sel
= interp_gpr
;
6516 alu
.src
[2].chan
= interp_base_chan
+ i
;
6517 alu
.dst
.sel
= ctx
->temp_reg
;
6521 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6526 for (i
= 0; i
< 2; i
++) {
6527 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6528 alu
.op
= ALU_OP3_MULADD
;
6530 alu
.src
[0].sel
= gradientsV
;
6531 alu
.src
[0].chan
= i
;
6532 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6533 alu
.src
[1].sel
= sample_gpr
;
6534 alu
.src
[1].chan
= 3;
6537 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], 1);
6539 alu
.src
[2].sel
= ctx
->temp_reg
;
6540 alu
.src
[2].chan
= i
;
6541 alu
.dst
.sel
= ctx
->temp_reg
;
6545 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6551 tmp
= r600_get_temp(ctx
);
6552 for (i
= 0; i
< 8; i
++) {
6553 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6554 alu
.op
= i
< 4 ? ALU_OP2_INTERP_ZW
: ALU_OP2_INTERP_XY
;
6557 if ((i
> 1 && i
< 6)) {
6563 alu
.dst
.chan
= i
% 4;
6565 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
6566 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
6567 alu
.src
[0].sel
= ctx
->temp_reg
;
6568 alu
.src
[0].chan
= 1 - (i
% 2);
6570 alu
.src
[0].sel
= interp_gpr
;
6571 alu
.src
[0].chan
= interp_base_chan
+ 1 - (i
% 2);
6573 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
6574 alu
.src
[1].chan
= 0;
6576 alu
.last
= i
% 4 == 3;
6577 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
6579 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6584 // INTERP can't swizzle dst
6585 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6586 for (i
= 0; i
<= lasti
; i
++) {
6587 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6590 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6591 alu
.op
= ALU_OP1_MOV
;
6592 alu
.src
[0].sel
= tmp
;
6593 alu
.src
[0].chan
= ctx
->src
[0].swizzle
[i
];
6594 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6596 alu
.last
= i
== lasti
;
6597 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6606 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
6608 struct r600_bytecode_alu alu
;
6611 for (i
= 0; i
< 4; i
++) {
6612 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6613 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
6614 alu
.op
= ALU_OP0_NOP
;
6617 alu
.op
= ALU_OP1_MOV
;
6618 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6619 alu
.src
[0].sel
= ctx
->temp_reg
;
6620 alu
.src
[0].chan
= i
;
6625 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6632 static int tgsi_make_src_for_op3(struct r600_shader_ctx
*ctx
,
6633 unsigned temp
, int chan
,
6634 struct r600_bytecode_alu_src
*bc_src
,
6635 const struct r600_shader_src
*shader_src
)
6637 struct r600_bytecode_alu alu
;
6640 r600_bytecode_src(bc_src
, shader_src
, chan
);
6642 /* op3 operands don't support abs modifier */
6644 assert(temp
!=0); /* we actually need the extra register, make sure it is allocated. */
6645 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6646 alu
.op
= ALU_OP1_MOV
;
6648 alu
.dst
.chan
= chan
;
6651 alu
.src
[0] = *bc_src
;
6652 alu
.last
= true; // sufficient?
6653 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6657 memset(bc_src
, 0, sizeof(*bc_src
));
6659 bc_src
->chan
= chan
;
6664 static int tgsi_op3_dst(struct r600_shader_ctx
*ctx
, int dst
)
6666 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6667 struct r600_bytecode_alu alu
;
6669 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6671 unsigned op
= ctx
->inst_info
->op
;
6673 if (op
== ALU_OP3_MULADD_IEEE
&&
6674 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6675 op
= ALU_OP3_MULADD
;
6677 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6679 if (ctx
->src
[j
].abs
)
6680 temp_regs
[j
] = r600_get_temp(ctx
);
6682 for (i
= 0; i
< lasti
+ 1; i
++) {
6683 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6686 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6688 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6689 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[j
], i
, &alu
.src
[j
], &ctx
->src
[j
]);
6695 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6705 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6712 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
6714 return tgsi_op3_dst(ctx
, -1);
6717 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
6719 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6720 struct r600_bytecode_alu alu
;
6722 unsigned op
= ctx
->inst_info
->op
;
6723 if (op
== ALU_OP2_DOT4_IEEE
&&
6724 ctx
->info
.properties
[TGSI_PROPERTY_MUL_ZERO_WINS
])
6727 for (i
= 0; i
< 4; i
++) {
6728 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6730 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
6731 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
6734 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
6736 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
6737 /* handle some special cases */
6738 switch (inst
->Instruction
.Opcode
) {
6739 case TGSI_OPCODE_DP2
:
6741 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6742 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6745 case TGSI_OPCODE_DP3
:
6747 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
6748 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
6757 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6764 static inline boolean
tgsi_tex_src_requires_loading(struct r600_shader_ctx
*ctx
,
6767 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6768 return (inst
->Src
[index
].Register
.File
!= TGSI_FILE_TEMPORARY
&&
6769 inst
->Src
[index
].Register
.File
!= TGSI_FILE_INPUT
&&
6770 inst
->Src
[index
].Register
.File
!= TGSI_FILE_OUTPUT
) ||
6771 ctx
->src
[index
].neg
|| ctx
->src
[index
].abs
||
6772 (inst
->Src
[index
].Register
.File
== TGSI_FILE_INPUT
&& ctx
->type
== PIPE_SHADER_GEOMETRY
);
6775 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx
*ctx
,
6778 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6779 return ctx
->file_offset
[inst
->Src
[index
].Register
.File
] + inst
->Src
[index
].Register
.Index
;
6782 static int do_vtx_fetch_inst(struct r600_shader_ctx
*ctx
, boolean src_requires_loading
)
6784 struct r600_bytecode_vtx vtx
;
6785 struct r600_bytecode_alu alu
;
6786 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6788 int id
= tgsi_tex_get_src_gpr(ctx
, 1);
6790 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6791 if (src_requires_loading
) {
6792 for (i
= 0; i
< 4; i
++) {
6793 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6794 alu
.op
= ALU_OP1_MOV
;
6795 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
6796 alu
.dst
.sel
= ctx
->temp_reg
;
6801 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6805 src_gpr
= ctx
->temp_reg
;
6808 memset(&vtx
, 0, sizeof(vtx
));
6809 vtx
.op
= FETCH_OP_VFETCH
;
6810 vtx
.buffer_id
= id
+ R600_MAX_CONST_BUFFERS
;
6811 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
6812 vtx
.src_gpr
= src_gpr
;
6813 vtx
.mega_fetch_count
= 16;
6814 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
6815 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
6816 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
6817 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
6818 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
6819 vtx
.use_const_fields
= 1;
6821 if ((r
= r600_bytecode_add_vtx(ctx
->bc
, &vtx
)))
6824 if (ctx
->bc
->chip_class
>= EVERGREEN
)
6827 for (i
= 0; i
< 4; i
++) {
6828 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
6829 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
6832 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6833 alu
.op
= ALU_OP2_AND_INT
;
6836 alu
.dst
.sel
= vtx
.dst_gpr
;
6839 alu
.src
[0].sel
= vtx
.dst_gpr
;
6840 alu
.src
[0].chan
= i
;
6842 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6843 alu
.src
[1].sel
+= (id
* 2);
6844 alu
.src
[1].chan
= i
% 4;
6845 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6849 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6854 if (inst
->Dst
[0].Register
.WriteMask
& 3) {
6855 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6856 alu
.op
= ALU_OP2_OR_INT
;
6859 alu
.dst
.sel
= vtx
.dst_gpr
;
6862 alu
.src
[0].sel
= vtx
.dst_gpr
;
6863 alu
.src
[0].chan
= 3;
6865 alu
.src
[1].sel
= R600_SHADER_BUFFER_INFO_SEL
+ (id
* 2) + 1;
6866 alu
.src
[1].chan
= 0;
6867 alu
.src
[1].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6870 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6877 static int r600_do_buffer_txq(struct r600_shader_ctx
*ctx
, int reg_idx
, int offset
)
6879 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6880 struct r600_bytecode_alu alu
;
6882 int id
= tgsi_tex_get_src_gpr(ctx
, reg_idx
) + offset
;
6884 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6885 alu
.op
= ALU_OP1_MOV
;
6886 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
6887 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
6888 /* channel 0 or 2 of each word */
6889 alu
.src
[0].sel
+= (id
/ 2);
6890 alu
.src
[0].chan
= (id
% 2) * 2;
6892 /* r600 we have them at channel 2 of the second dword */
6893 alu
.src
[0].sel
+= (id
* 2) + 1;
6894 alu
.src
[0].chan
= 1;
6896 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
6897 tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
6899 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6905 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
6907 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
6908 struct r600_bytecode_tex tex
;
6909 struct r600_bytecode_alu alu
;
6913 bool read_compressed_msaa
= ctx
->bc
->has_compressed_msaa_texturing
&&
6914 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6915 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_MSAA
||
6916 inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
6918 bool txf_add_offsets
= inst
->Texture
.NumOffsets
&&
6919 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
&&
6920 inst
->Texture
.Texture
!= TGSI_TEXTURE_BUFFER
;
6922 /* Texture fetch instructions can only use gprs as source.
6923 * Also they cannot negate the source or take the absolute value */
6924 const boolean src_requires_loading
= (inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQS
&&
6925 tgsi_tex_src_requires_loading(ctx
, 0)) ||
6926 read_compressed_msaa
|| txf_add_offsets
;
6928 boolean src_loaded
= FALSE
;
6929 unsigned sampler_src_reg
= 1;
6930 int8_t offset_x
= 0, offset_y
= 0, offset_z
= 0;
6931 boolean has_txq_cube_array_z
= false;
6932 unsigned sampler_index_mode
;
6934 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
6935 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
6936 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)))
6937 if (inst
->Dst
[0].Register
.WriteMask
& 4) {
6938 ctx
->shader
->has_txq_cube_array_z_comp
= true;
6939 has_txq_cube_array_z
= true;
6942 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TEX2
||
6943 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
6944 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
||
6945 inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
)
6946 sampler_src_reg
= 2;
6948 /* TGSI moves the sampler to src reg 3 for TXD */
6949 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
)
6950 sampler_src_reg
= 3;
6952 sampler_index_mode
= inst
->Src
[sampler_src_reg
].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6954 src_gpr
= tgsi_tex_get_src_gpr(ctx
, 0);
6956 if (inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
6957 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
6958 ctx
->shader
->uses_tex_buffers
= true;
6959 return r600_do_buffer_txq(ctx
, 1, 0);
6961 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXF
) {
6962 if (ctx
->bc
->chip_class
< EVERGREEN
)
6963 ctx
->shader
->uses_tex_buffers
= true;
6964 return do_vtx_fetch_inst(ctx
, src_requires_loading
);
6968 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
6970 /* Add perspective divide */
6971 if (ctx
->bc
->chip_class
== CAYMAN
) {
6973 for (i
= 0; i
< 3; i
++) {
6974 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6975 alu
.op
= ALU_OP1_RECIP_IEEE
;
6976 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6978 alu
.dst
.sel
= ctx
->temp_reg
;
6984 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
6991 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
6992 alu
.op
= ALU_OP1_RECIP_IEEE
;
6993 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
6995 alu
.dst
.sel
= ctx
->temp_reg
;
6996 alu
.dst
.chan
= out_chan
;
6999 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7004 for (i
= 0; i
< 3; i
++) {
7005 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7006 alu
.op
= ALU_OP2_MUL
;
7007 alu
.src
[0].sel
= ctx
->temp_reg
;
7008 alu
.src
[0].chan
= out_chan
;
7009 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
7010 alu
.dst
.sel
= ctx
->temp_reg
;
7013 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7017 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7018 alu
.op
= ALU_OP1_MOV
;
7019 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
7020 alu
.src
[0].chan
= 0;
7021 alu
.dst
.sel
= ctx
->temp_reg
;
7025 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7029 src_gpr
= ctx
->temp_reg
;
7033 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7034 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7035 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7036 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7037 inst
->Instruction
.Opcode
!= TGSI_OPCODE_TXQ
) {
7039 static const unsigned src0_swizzle
[] = {2, 2, 0, 1};
7040 static const unsigned src1_swizzle
[] = {1, 0, 2, 2};
7042 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7043 for (i
= 0; i
< 4; i
++) {
7044 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7045 alu
.op
= ALU_OP2_CUBE
;
7046 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], src0_swizzle
[i
]);
7047 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], src1_swizzle
[i
]);
7048 alu
.dst
.sel
= ctx
->temp_reg
;
7053 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7058 /* tmp1.z = RCP_e(|tmp1.z|) */
7059 if (ctx
->bc
->chip_class
== CAYMAN
) {
7060 for (i
= 0; i
< 3; i
++) {
7061 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7062 alu
.op
= ALU_OP1_RECIP_IEEE
;
7063 alu
.src
[0].sel
= ctx
->temp_reg
;
7064 alu
.src
[0].chan
= 2;
7066 alu
.dst
.sel
= ctx
->temp_reg
;
7072 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7077 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7078 alu
.op
= ALU_OP1_RECIP_IEEE
;
7079 alu
.src
[0].sel
= ctx
->temp_reg
;
7080 alu
.src
[0].chan
= 2;
7082 alu
.dst
.sel
= ctx
->temp_reg
;
7086 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7091 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7092 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7093 * muladd has no writemask, have to use another temp
7095 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7096 alu
.op
= ALU_OP3_MULADD
;
7099 alu
.src
[0].sel
= ctx
->temp_reg
;
7100 alu
.src
[0].chan
= 0;
7101 alu
.src
[1].sel
= ctx
->temp_reg
;
7102 alu
.src
[1].chan
= 2;
7104 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7105 alu
.src
[2].chan
= 0;
7106 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
7108 alu
.dst
.sel
= ctx
->temp_reg
;
7112 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7116 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7117 alu
.op
= ALU_OP3_MULADD
;
7120 alu
.src
[0].sel
= ctx
->temp_reg
;
7121 alu
.src
[0].chan
= 1;
7122 alu
.src
[1].sel
= ctx
->temp_reg
;
7123 alu
.src
[1].chan
= 2;
7125 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
7126 alu
.src
[2].chan
= 0;
7127 alu
.src
[2].value
= u_bitcast_f2u(1.5f
);
7129 alu
.dst
.sel
= ctx
->temp_reg
;
7134 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7137 /* write initial compare value into Z component
7138 - W src 0 for shadow cube
7139 - X src 1 for shadow cube array */
7140 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7141 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7142 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7143 alu
.op
= ALU_OP1_MOV
;
7144 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
7145 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7147 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7148 alu
.dst
.sel
= ctx
->temp_reg
;
7152 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7157 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7158 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7159 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7160 int mytmp
= r600_get_temp(ctx
);
7161 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7162 alu
.op
= ALU_OP1_MOV
;
7163 alu
.src
[0].sel
= ctx
->temp_reg
;
7164 alu
.src
[0].chan
= 3;
7165 alu
.dst
.sel
= mytmp
;
7169 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7173 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7174 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7175 alu
.op
= ALU_OP3_MULADD
;
7177 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7178 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7179 alu
.src
[1].chan
= 0;
7180 alu
.src
[1].value
= u_bitcast_f2u(8.0f
);
7181 alu
.src
[2].sel
= mytmp
;
7182 alu
.src
[2].chan
= 0;
7183 alu
.dst
.sel
= ctx
->temp_reg
;
7187 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7190 } else if (ctx
->bc
->chip_class
< EVERGREEN
) {
7191 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7192 tex
.op
= FETCH_OP_SET_CUBEMAP_INDEX
;
7193 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7194 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7195 tex
.src_gpr
= r600_get_temp(ctx
);
7200 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7201 tex
.coord_type_x
= 1;
7202 tex
.coord_type_y
= 1;
7203 tex
.coord_type_z
= 1;
7204 tex
.coord_type_w
= 1;
7205 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7206 alu
.op
= ALU_OP1_MOV
;
7207 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7208 alu
.dst
.sel
= tex
.src_gpr
;
7212 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7216 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7223 /* for cube forms of lod and bias we need to route things */
7224 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
7225 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
7226 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7227 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
) {
7228 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7229 alu
.op
= ALU_OP1_MOV
;
7230 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
||
7231 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL2
)
7232 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7234 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 3);
7235 alu
.dst
.sel
= ctx
->temp_reg
;
7239 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7245 src_gpr
= ctx
->temp_reg
;
7248 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXD
) {
7249 int temp_h
= 0, temp_v
= 0;
7252 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7253 if (src_loaded
== TRUE
)
7257 for (i
= start_val
; i
< 3; i
++) {
7258 int treg
= r600_get_temp(ctx
);
7267 for (j
= 0; j
< 4; j
++) {
7268 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7269 alu
.op
= ALU_OP1_MOV
;
7270 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[i
], j
);
7276 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7281 for (i
= 1; i
< 3; i
++) {
7282 /* set gradients h/v */
7283 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7284 tex
.op
= (i
== 1) ? FETCH_OP_SET_GRADIENTS_H
:
7285 FETCH_OP_SET_GRADIENTS_V
;
7286 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7287 tex
.sampler_index_mode
= sampler_index_mode
;
7288 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7289 tex
.resource_index_mode
= sampler_index_mode
;
7291 tex
.src_gpr
= (i
== 1) ? temp_h
: temp_v
;
7297 tex
.dst_gpr
= r600_get_temp(ctx
); /* just to avoid confusing the asm scheduler */
7298 tex
.dst_sel_x
= tex
.dst_sel_y
= tex
.dst_sel_z
= tex
.dst_sel_w
= 7;
7299 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
7300 tex
.coord_type_x
= 1;
7301 tex
.coord_type_y
= 1;
7302 tex
.coord_type_z
= 1;
7303 tex
.coord_type_w
= 1;
7305 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7311 if (src_requires_loading
&& !src_loaded
) {
7312 for (i
= 0; i
< 4; i
++) {
7313 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7314 alu
.op
= ALU_OP1_MOV
;
7315 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
7316 alu
.dst
.sel
= ctx
->temp_reg
;
7321 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7326 src_gpr
= ctx
->temp_reg
;
7329 /* get offset values */
7330 if (inst
->Texture
.NumOffsets
) {
7331 assert(inst
->Texture
.NumOffsets
== 1);
7333 /* The texture offset feature doesn't work with the TXF instruction
7334 * and must be emulated by adding the offset to the texture coordinates. */
7335 if (txf_add_offsets
) {
7336 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
7338 switch (inst
->Texture
.Texture
) {
7339 case TGSI_TEXTURE_3D
:
7340 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7341 alu
.op
= ALU_OP2_ADD_INT
;
7342 alu
.src
[0].sel
= src_gpr
;
7343 alu
.src
[0].chan
= 2;
7344 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7345 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleZ
];
7346 alu
.dst
.sel
= src_gpr
;
7350 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7355 case TGSI_TEXTURE_2D
:
7356 case TGSI_TEXTURE_SHADOW2D
:
7357 case TGSI_TEXTURE_RECT
:
7358 case TGSI_TEXTURE_SHADOWRECT
:
7359 case TGSI_TEXTURE_2D_ARRAY
:
7360 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7361 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7362 alu
.op
= ALU_OP2_ADD_INT
;
7363 alu
.src
[0].sel
= src_gpr
;
7364 alu
.src
[0].chan
= 1;
7365 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7366 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleY
];
7367 alu
.dst
.sel
= src_gpr
;
7371 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7376 case TGSI_TEXTURE_1D
:
7377 case TGSI_TEXTURE_SHADOW1D
:
7378 case TGSI_TEXTURE_1D_ARRAY
:
7379 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7380 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7381 alu
.op
= ALU_OP2_ADD_INT
;
7382 alu
.src
[0].sel
= src_gpr
;
7383 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7384 alu
.src
[1].value
= ctx
->literals
[4 * off
[0].Index
+ off
[0].SwizzleX
];
7385 alu
.dst
.sel
= src_gpr
;
7388 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7392 /* texture offsets do not apply to other texture targets */
7395 switch (inst
->Texture
.Texture
) {
7396 case TGSI_TEXTURE_3D
:
7397 offset_z
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleZ
] << 1;
7399 case TGSI_TEXTURE_2D
:
7400 case TGSI_TEXTURE_SHADOW2D
:
7401 case TGSI_TEXTURE_RECT
:
7402 case TGSI_TEXTURE_SHADOWRECT
:
7403 case TGSI_TEXTURE_2D_ARRAY
:
7404 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
7405 offset_y
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleY
] << 1;
7407 case TGSI_TEXTURE_1D
:
7408 case TGSI_TEXTURE_SHADOW1D
:
7409 case TGSI_TEXTURE_1D_ARRAY
:
7410 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
7411 offset_x
= ctx
->literals
[4 * inst
->TexOffsets
[0].Index
+ inst
->TexOffsets
[0].SwizzleX
] << 1;
7416 /* Obtain the sample index for reading a compressed MSAA color texture.
7417 * To read the FMASK, we use the ldfptr instruction, which tells us
7418 * where the samples are stored.
7419 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7420 * which is the identity mapping. Each nibble says which physical sample
7421 * should be fetched to get that sample.
7423 * Assume src.z contains the sample index. It should be modified like this:
7424 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7425 * Then fetch the texel with src.
7427 if (read_compressed_msaa
) {
7428 unsigned sample_chan
= 3;
7429 unsigned temp
= r600_get_temp(ctx
);
7432 /* temp.w = ldfptr() */
7433 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7434 tex
.op
= FETCH_OP_LD
;
7435 tex
.inst_mod
= 1; /* to indicate this is ldfptr */
7436 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7437 tex
.sampler_index_mode
= sampler_index_mode
;
7438 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7439 tex
.resource_index_mode
= sampler_index_mode
;
7440 tex
.src_gpr
= src_gpr
;
7442 tex
.dst_sel_x
= 7; /* mask out these components */
7445 tex
.dst_sel_w
= 0; /* store X */
7450 tex
.offset_x
= offset_x
;
7451 tex
.offset_y
= offset_y
;
7452 tex
.offset_z
= offset_z
;
7453 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7457 /* temp.x = sample_index*4 */
7458 if (ctx
->bc
->chip_class
== CAYMAN
) {
7459 for (i
= 0 ; i
< 4; i
++) {
7460 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7461 alu
.op
= ALU_OP2_MULLO_INT
;
7462 alu
.src
[0].sel
= src_gpr
;
7463 alu
.src
[0].chan
= sample_chan
;
7464 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7465 alu
.src
[1].value
= 4;
7468 alu
.dst
.write
= i
== 0;
7471 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7476 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7477 alu
.op
= ALU_OP2_MULLO_INT
;
7478 alu
.src
[0].sel
= src_gpr
;
7479 alu
.src
[0].chan
= sample_chan
;
7480 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7481 alu
.src
[1].value
= 4;
7486 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7491 /* sample_index = temp.w >> temp.x */
7492 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7493 alu
.op
= ALU_OP2_LSHR_INT
;
7494 alu
.src
[0].sel
= temp
;
7495 alu
.src
[0].chan
= 3;
7496 alu
.src
[1].sel
= temp
;
7497 alu
.src
[1].chan
= 0;
7498 alu
.dst
.sel
= src_gpr
;
7499 alu
.dst
.chan
= sample_chan
;
7502 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7506 /* sample_index & 0xF */
7507 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7508 alu
.op
= ALU_OP2_AND_INT
;
7509 alu
.src
[0].sel
= src_gpr
;
7510 alu
.src
[0].chan
= sample_chan
;
7511 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7512 alu
.src
[1].value
= 0xF;
7513 alu
.dst
.sel
= src_gpr
;
7514 alu
.dst
.chan
= sample_chan
;
7517 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7521 /* visualize the FMASK */
7522 for (i
= 0; i
< 4; i
++) {
7523 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7524 alu
.op
= ALU_OP1_INT_TO_FLT
;
7525 alu
.src
[0].sel
= src_gpr
;
7526 alu
.src
[0].chan
= sample_chan
;
7527 alu
.dst
.sel
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7531 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7539 /* does this shader want a num layers from TXQ for a cube array? */
7540 if (has_txq_cube_array_z
) {
7541 int id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7543 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7544 alu
.op
= ALU_OP1_MOV
;
7546 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
7547 if (ctx
->bc
->chip_class
>= EVERGREEN
) {
7548 /* channel 1 or 3 of each word */
7549 alu
.src
[0].sel
+= (id
/ 2);
7550 alu
.src
[0].chan
= ((id
% 2) * 2) + 1;
7552 /* r600 we have them at channel 2 of the second dword */
7553 alu
.src
[0].sel
+= (id
* 2) + 1;
7554 alu
.src
[0].chan
= 2;
7556 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
7557 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
7559 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7562 /* disable writemask from texture instruction */
7563 inst
->Dst
[0].Register
.WriteMask
&= ~4;
7566 opcode
= ctx
->inst_info
->op
;
7567 if (opcode
== FETCH_OP_GATHER4
&&
7568 inst
->TexOffsets
[0].File
!= TGSI_FILE_NULL
&&
7569 inst
->TexOffsets
[0].File
!= TGSI_FILE_IMMEDIATE
) {
7570 opcode
= FETCH_OP_GATHER4_O
;
7572 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7573 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7574 encoded in the instruction are ignored. */
7575 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7576 tex
.op
= FETCH_OP_SET_TEXTURE_OFFSETS
;
7577 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7578 tex
.sampler_index_mode
= sampler_index_mode
;
7579 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7580 tex
.resource_index_mode
= sampler_index_mode
;
7582 tex
.src_gpr
= ctx
->file_offset
[inst
->TexOffsets
[0].File
] + inst
->TexOffsets
[0].Index
;
7583 tex
.src_sel_x
= inst
->TexOffsets
[0].SwizzleX
;
7584 tex
.src_sel_y
= inst
->TexOffsets
[0].SwizzleY
;
7585 tex
.src_sel_z
= inst
->TexOffsets
[0].SwizzleZ
;
7593 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7598 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7599 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7600 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7601 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7602 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
7603 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7604 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7606 case FETCH_OP_SAMPLE
:
7607 opcode
= FETCH_OP_SAMPLE_C
;
7609 case FETCH_OP_SAMPLE_L
:
7610 opcode
= FETCH_OP_SAMPLE_C_L
;
7612 case FETCH_OP_SAMPLE_LB
:
7613 opcode
= FETCH_OP_SAMPLE_C_LB
;
7615 case FETCH_OP_SAMPLE_G
:
7616 opcode
= FETCH_OP_SAMPLE_C_G
;
7618 /* Texture gather variants */
7619 case FETCH_OP_GATHER4
:
7620 opcode
= FETCH_OP_GATHER4_C
;
7622 case FETCH_OP_GATHER4_O
:
7623 opcode
= FETCH_OP_GATHER4_C_O
;
7628 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
7631 tex
.sampler_id
= tgsi_tex_get_src_gpr(ctx
, sampler_src_reg
);
7632 tex
.sampler_index_mode
= sampler_index_mode
;
7633 tex
.resource_id
= tex
.sampler_id
+ R600_MAX_CONST_BUFFERS
;
7634 tex
.resource_index_mode
= sampler_index_mode
;
7635 tex
.src_gpr
= src_gpr
;
7636 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7638 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_DDX_FINE
||
7639 inst
->Instruction
.Opcode
== TGSI_OPCODE_DDY_FINE
) {
7640 tex
.inst_mod
= 1; /* per pixel gradient calculation instead of per 2x2 quad */
7643 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
) {
7644 int8_t texture_component_select
= ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
];
7645 tex
.inst_mod
= texture_component_select
;
7647 if (ctx
->bc
->chip_class
== CAYMAN
) {
7648 /* GATHER4 result order is different from TGSI TG4 */
7649 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 0 : 7;
7650 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 1 : 7;
7651 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 2 : 7;
7652 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7654 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7655 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7656 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7657 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7660 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_LODQ
) {
7661 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7662 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7666 else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7673 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
7674 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
7675 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
7676 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
7680 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQS
) {
7685 } else if (src_loaded
) {
7691 tex
.src_sel_x
= ctx
->src
[0].swizzle
[0];
7692 tex
.src_sel_y
= ctx
->src
[0].swizzle
[1];
7693 tex
.src_sel_z
= ctx
->src
[0].swizzle
[2];
7694 tex
.src_sel_w
= ctx
->src
[0].swizzle
[3];
7695 tex
.src_rel
= ctx
->src
[0].rel
;
7698 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
||
7699 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE
||
7700 inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7701 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
7705 tex
.src_sel_w
= 2; /* route Z compare or Lod value into W */
7708 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
&&
7709 inst
->Texture
.Texture
!= TGSI_TEXTURE_SHADOWRECT
) {
7710 tex
.coord_type_x
= 1;
7711 tex
.coord_type_y
= 1;
7713 tex
.coord_type_z
= 1;
7714 tex
.coord_type_w
= 1;
7716 tex
.offset_x
= offset_x
;
7717 tex
.offset_y
= offset_y
;
7718 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TG4
&&
7719 (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7720 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
)) {
7724 tex
.offset_z
= offset_z
;
7727 /* Put the depth for comparison in W.
7728 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7729 * Some instructions expect the depth in Z. */
7730 if ((inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
||
7731 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
||
7732 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWRECT
||
7733 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) &&
7734 opcode
!= FETCH_OP_SAMPLE_C_L
&&
7735 opcode
!= FETCH_OP_SAMPLE_C_LB
) {
7736 tex
.src_sel_w
= tex
.src_sel_z
;
7739 if (inst
->Texture
.Texture
== TGSI_TEXTURE_1D_ARRAY
||
7740 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
7741 if (opcode
== FETCH_OP_SAMPLE_C_L
||
7742 opcode
== FETCH_OP_SAMPLE_C_LB
) {
7743 /* the array index is read from Y */
7744 tex
.coord_type_y
= 0;
7746 /* the array index is read from Z */
7747 tex
.coord_type_z
= 0;
7748 tex
.src_sel_z
= tex
.src_sel_y
;
7750 } else if (inst
->Texture
.Texture
== TGSI_TEXTURE_2D_ARRAY
||
7751 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
7752 ((inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
||
7753 inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) &&
7754 (ctx
->bc
->chip_class
>= EVERGREEN
)))
7755 /* the array index is read from Z */
7756 tex
.coord_type_z
= 0;
7758 /* mask unused source components */
7759 if (opcode
== FETCH_OP_SAMPLE
|| opcode
== FETCH_OP_GATHER4
) {
7760 switch (inst
->Texture
.Texture
) {
7761 case TGSI_TEXTURE_2D
:
7762 case TGSI_TEXTURE_RECT
:
7766 case TGSI_TEXTURE_1D_ARRAY
:
7770 case TGSI_TEXTURE_1D
:
7778 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
7782 /* add shadow ambient support - gallium doesn't do it yet */
7786 static int find_hw_atomic_counter(struct r600_shader_ctx
*ctx
,
7787 struct tgsi_full_src_register
*src
)
7791 if (src
->Register
.Indirect
) {
7792 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7793 if (src
->Indirect
.ArrayID
== ctx
->shader
->atomics
[i
].array_id
)
7794 return ctx
->shader
->atomics
[i
].hw_idx
;
7797 uint32_t index
= src
->Register
.Index
;
7798 for (i
= 0; i
< ctx
->shader
->nhwatomic_ranges
; i
++) {
7799 if (ctx
->shader
->atomics
[i
].buffer_id
!= (unsigned)src
->Dimension
.Index
)
7801 if (index
> ctx
->shader
->atomics
[i
].end
)
7803 if (index
< ctx
->shader
->atomics
[i
].start
)
7805 uint32_t offset
= (index
- ctx
->shader
->atomics
[i
].start
);
7806 return ctx
->shader
->atomics
[i
].hw_idx
+ offset
;
7813 static int tgsi_set_gds_temp(struct r600_shader_ctx
*ctx
,
7814 int *uav_id_p
, int *uav_index_mode_p
)
7816 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7817 int uav_id
, uav_index_mode
;
7819 bool is_cm
= (ctx
->bc
->chip_class
== CAYMAN
);
7821 uav_id
= find_hw_atomic_counter(ctx
, &inst
->Src
[0]);
7823 if (inst
->Src
[0].Register
.Indirect
) {
7825 struct r600_bytecode_alu alu
;
7826 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7827 alu
.op
= ALU_OP2_LSHL_INT
;
7828 alu
.src
[0].sel
= get_address_file_reg(ctx
, inst
->Src
[0].Indirect
.Index
);
7829 alu
.src
[0].chan
= 0;
7830 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7831 alu
.src
[1].value
= 2;
7832 alu
.dst
.sel
= ctx
->temp_reg
;
7836 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7840 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
7843 V_SQ_ALU_SRC_LITERAL
, uav_id
* 4);
7849 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
7851 V_SQ_ALU_SRC_LITERAL
, uav_id
* 4,
7857 *uav_index_mode_p
= uav_index_mode
;
7861 static int tgsi_load_gds(struct r600_shader_ctx
*ctx
)
7863 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7865 struct r600_bytecode_gds gds
;
7867 int uav_index_mode
= 0;
7868 bool is_cm
= (ctx
->bc
->chip_class
== CAYMAN
);
7870 r
= tgsi_set_gds_temp(ctx
, &uav_id
, &uav_index_mode
);
7874 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
7875 gds
.op
= FETCH_OP_GDS_READ_RET
;
7876 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
7877 gds
.uav_id
= is_cm
? 0 : uav_id
;
7878 gds
.uav_index_mode
= is_cm
? 0 : uav_index_mode
;
7879 gds
.src_gpr
= ctx
->temp_reg
;
7880 gds
.src_sel_x
= (is_cm
) ? 0 : 4;
7888 gds
.alloc_consume
= !is_cm
;
7889 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
7893 ctx
->bc
->cf_last
->vpm
= 1;
7897 /* this fixes up 1D arrays properly */
7898 static int load_index_src(struct r600_shader_ctx
*ctx
, int src_index
, int *idx_gpr
)
7900 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7902 struct r600_bytecode_alu alu
;
7903 int temp_reg
= r600_get_temp(ctx
);
7905 for (i
= 0; i
< 4; i
++) {
7906 bool def_val
= true, write_zero
= false;
7907 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7908 alu
.op
= ALU_OP1_MOV
;
7909 alu
.dst
.sel
= temp_reg
;
7912 switch (inst
->Memory
.Texture
) {
7913 case TGSI_TEXTURE_BUFFER
:
7914 case TGSI_TEXTURE_1D
:
7915 if (i
== 1 || i
== 2 || i
== 3) {
7919 case TGSI_TEXTURE_1D_ARRAY
:
7920 if (i
== 1 || i
== 3)
7923 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[src_index
], 1);
7927 case TGSI_TEXTURE_2D
:
7928 if (i
== 2 || i
== 3)
7938 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
7939 alu
.src
[0].value
= 0;
7940 } else if (def_val
) {
7941 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[src_index
], i
);
7947 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7951 *idx_gpr
= temp_reg
;
7955 static int tgsi_load_buffer(struct r600_shader_ctx
*ctx
)
7957 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
7958 /* have to work out the offset into the RAT immediate return buffer */
7959 struct r600_bytecode_vtx vtx
;
7960 struct r600_bytecode_cf
*cf
;
7962 int temp_reg
= r600_get_temp(ctx
);
7963 unsigned rat_index_mode
;
7966 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7967 base
= R600_IMAGE_REAL_RESOURCE_OFFSET
+ ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
7969 if (inst
->Src
[1].Register
.File
== TGSI_FILE_IMMEDIATE
) {
7970 int value
= (ctx
->literals
[4 * inst
->Src
[1].Register
.Index
+ inst
->Src
[1].Register
.SwizzleX
]);
7971 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
7973 V_SQ_ALU_SRC_LITERAL
, value
>> 2,
7978 struct r600_bytecode_alu alu
;
7979 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
7980 alu
.op
= ALU_OP2_LSHR_INT
;
7981 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], 0);
7982 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
7983 alu
.src
[1].value
= 2;
7984 alu
.dst
.sel
= temp_reg
;
7987 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
7991 ctx
->bc
->cf_last
->barrier
= 1;
7992 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
7993 vtx
.op
= FETCH_OP_VFETCH
;
7994 vtx
.buffer_id
= inst
->Src
[0].Register
.Index
+ base
;
7995 vtx
.buffer_index_mode
= rat_index_mode
;
7996 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
7997 vtx
.src_gpr
= temp_reg
;
7999 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8000 vtx
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7; /* SEL_X */
8001 vtx
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7; /* SEL_Y */
8002 vtx
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7; /* SEL_Z */
8003 vtx
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7; /* SEL_W */
8004 vtx
.num_format_all
= 1;
8005 vtx
.format_comp_all
= 1;
8006 vtx
.srf_mode_all
= 0;
8008 if (inst
->Dst
[0].Register
.WriteMask
== 0xf) {
8009 vtx
.data_format
= FMT_32_32_32_32
;
8010 vtx
.use_const_fields
= 0;
8011 } else if (inst
->Dst
[0].Register
.WriteMask
== 0x7) {
8012 vtx
.data_format
= FMT_32_32_32
;
8013 vtx
.use_const_fields
= 0;
8014 } else if (inst
->Dst
[0].Register
.WriteMask
== 0x3) {
8015 vtx
.data_format
= FMT_32_32
;
8016 vtx
.use_const_fields
= 0;
8018 vtx
.use_const_fields
= 1;
8020 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
8023 cf
= ctx
->bc
->cf_last
;
8028 static int tgsi_load_rat(struct r600_shader_ctx
*ctx
)
8030 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8031 /* have to work out the offset into the RAT immediate return buffer */
8032 struct r600_bytecode_vtx vtx
;
8033 struct r600_bytecode_cf
*cf
;
8036 unsigned format
, num_format
, format_comp
, endian
;
8037 const struct util_format_description
*desc
;
8038 unsigned rat_index_mode
;
8039 unsigned immed_base
;
8041 r
= load_thread_id_gpr(ctx
);
8045 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8047 immed_base
= R600_IMAGE_IMMED_RESOURCE_OFFSET
;
8048 r
= load_index_src(ctx
, 1, &idx_gpr
);
8053 egcm_load_index_reg(ctx
->bc
, 1, false);
8055 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8056 cf
= ctx
->bc
->cf_last
;
8058 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Src
[0].Register
.Index
;
8059 cf
->rat
.inst
= V_RAT_INST_NOP_RTN
;
8060 cf
->rat
.index_mode
= rat_index_mode
;
8061 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND
;
8062 cf
->output
.gpr
= ctx
->thread_id_gpr
;
8063 cf
->output
.index_gpr
= idx_gpr
;
8064 cf
->output
.comp_mask
= 0xf;
8065 cf
->output
.burst_count
= 1;
8069 cf
->output
.elem_size
= 0;
8071 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_WAIT_ACK
);
8072 cf
= ctx
->bc
->cf_last
;
8075 desc
= util_format_description(inst
->Memory
.Format
);
8076 r600_vertex_data_type(inst
->Memory
.Format
,
8077 &format
, &num_format
, &format_comp
, &endian
);
8078 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
8079 vtx
.op
= FETCH_OP_VFETCH
;
8080 vtx
.buffer_id
= immed_base
+ inst
->Src
[0].Register
.Index
;
8081 vtx
.buffer_index_mode
= rat_index_mode
;
8082 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
8083 vtx
.src_gpr
= ctx
->thread_id_gpr
;
8085 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8086 vtx
.dst_sel_x
= desc
->swizzle
[0];
8087 vtx
.dst_sel_y
= desc
->swizzle
[1];
8088 vtx
.dst_sel_z
= desc
->swizzle
[2];
8089 vtx
.dst_sel_w
= desc
->swizzle
[3];
8090 vtx
.srf_mode_all
= 1;
8091 vtx
.data_format
= format
;
8092 vtx
.num_format_all
= num_format
;
8093 vtx
.format_comp_all
= format_comp
;
8094 vtx
.endian
= endian
;
8096 vtx
.mega_fetch_count
= 3;
8097 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
8100 cf
= ctx
->bc
->cf_last
;
8105 static int tgsi_load(struct r600_shader_ctx
*ctx
)
8107 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8108 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
8109 return tgsi_load_rat(ctx
);
8110 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
8111 return tgsi_load_gds(ctx
);
8112 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
8113 return tgsi_load_buffer(ctx
);
8117 static int tgsi_store_buffer_rat(struct r600_shader_ctx
*ctx
)
8119 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8120 struct r600_bytecode_cf
*cf
;
8122 unsigned rat_index_mode
;
8124 int temp_reg
= r600_get_temp(ctx
), treg2
= r600_get_temp(ctx
);
8126 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMMEDIATE
) {
8127 int value
= (ctx
->literals
[4 * inst
->Src
[0].Register
.Index
+ inst
->Src
[0].Register
.SwizzleX
]);
8128 r
= single_alu_op2(ctx
, ALU_OP1_MOV
,
8130 V_SQ_ALU_SRC_LITERAL
, value
>> 2,
8135 r
= single_alu_op2(ctx
, ALU_OP2_LSHR_INT
,
8137 ctx
->src
[0].sel
, ctx
->src
[0].swizzle
[0],
8138 V_SQ_ALU_SRC_LITERAL
, 2);
8143 rat_index_mode
= inst
->Dst
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8145 egcm_load_index_reg(ctx
->bc
, 1, false);
8147 for (i
= 0; i
<= 3; i
++) {
8148 struct r600_bytecode_alu alu
;
8149 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8150 alu
.op
= ALU_OP1_MOV
;
8151 alu
.dst
.sel
= temp_reg
;
8153 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
8154 alu
.last
= (i
== 3);
8156 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8161 lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8162 for (i
= 0; i
<= lasti
; i
++) {
8163 struct r600_bytecode_alu alu
;
8164 if (!((1 << i
) & inst
->Dst
[0].Register
.WriteMask
))
8167 r
= single_alu_op2(ctx
, ALU_OP2_ADD_INT
,
8170 V_SQ_ALU_SRC_LITERAL
, i
);
8174 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8175 alu
.op
= ALU_OP1_MOV
;
8176 alu
.dst
.sel
= ctx
->temp_reg
;
8179 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
8182 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8186 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8187 cf
= ctx
->bc
->cf_last
;
8189 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Dst
[0].Register
.Index
+ ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
8190 cf
->rat
.inst
= V_RAT_INST_STORE_TYPED
;
8191 cf
->rat
.index_mode
= rat_index_mode
;
8192 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
8193 cf
->output
.gpr
= ctx
->temp_reg
;
8194 cf
->output
.index_gpr
= temp_reg
;
8195 cf
->output
.comp_mask
= 1;
8196 cf
->output
.burst_count
= 1;
8199 cf
->output
.elem_size
= 0;
8204 static int tgsi_store_rat(struct r600_shader_ctx
*ctx
)
8206 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8207 struct r600_bytecode_cf
*cf
;
8208 bool src_requires_loading
= false;
8209 int val_gpr
, idx_gpr
;
8211 unsigned rat_index_mode
;
8213 rat_index_mode
= inst
->Dst
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8215 r
= load_index_src(ctx
, 0, &idx_gpr
);
8219 if (inst
->Src
[1].Register
.File
!= TGSI_FILE_TEMPORARY
)
8220 src_requires_loading
= true;
8222 if (src_requires_loading
) {
8223 struct r600_bytecode_alu alu
;
8224 for (i
= 0; i
< 4; i
++) {
8225 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8226 alu
.op
= ALU_OP1_MOV
;
8227 alu
.dst
.sel
= ctx
->temp_reg
;
8230 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
8234 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8238 val_gpr
= ctx
->temp_reg
;
8240 val_gpr
= tgsi_tex_get_src_gpr(ctx
, 1);
8242 egcm_load_index_reg(ctx
->bc
, 1, false);
8244 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8245 cf
= ctx
->bc
->cf_last
;
8247 cf
->rat
.id
= ctx
->shader
->rat_base
+ inst
->Dst
[0].Register
.Index
;
8248 cf
->rat
.inst
= V_RAT_INST_STORE_TYPED
;
8249 cf
->rat
.index_mode
= rat_index_mode
;
8250 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND
;
8251 cf
->output
.gpr
= val_gpr
;
8252 cf
->output
.index_gpr
= idx_gpr
;
8253 cf
->output
.comp_mask
= 0xf;
8254 cf
->output
.burst_count
= 1;
8257 cf
->output
.elem_size
= 0;
8261 static int tgsi_store(struct r600_shader_ctx
*ctx
)
8263 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8264 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
)
8265 return tgsi_store_buffer_rat(ctx
);
8267 return tgsi_store_rat(ctx
);
8270 static int tgsi_atomic_op_rat(struct r600_shader_ctx
*ctx
)
8272 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8273 /* have to work out the offset into the RAT immediate return buffer */
8274 struct r600_bytecode_alu alu
;
8275 struct r600_bytecode_vtx vtx
;
8276 struct r600_bytecode_cf
*cf
;
8279 unsigned format
, num_format
, format_comp
, endian
;
8280 const struct util_format_description
*desc
;
8281 unsigned rat_index_mode
;
8282 unsigned immed_base
;
8285 immed_base
= R600_IMAGE_IMMED_RESOURCE_OFFSET
;
8286 rat_base
= ctx
->shader
->rat_base
;
8288 r
= load_thread_id_gpr(ctx
);
8292 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
8293 immed_base
+= ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
8294 rat_base
+= ctx
->info
.file_count
[TGSI_FILE_IMAGE
];
8297 rat_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8299 r
= load_index_src(ctx
, 1, &idx_gpr
);
8303 if (ctx
->inst_info
->op
== V_RAT_INST_CMPXCHG_INT_RTN
) {
8304 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8305 alu
.op
= ALU_OP1_MOV
;
8306 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8309 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[3], 0);
8311 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8315 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8316 alu
.op
= ALU_OP1_MOV
;
8317 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8318 if (ctx
->bc
->chip_class
== CAYMAN
)
8323 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8325 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8329 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8330 alu
.op
= ALU_OP1_MOV
;
8331 alu
.dst
.sel
= ctx
->thread_id_gpr
;
8334 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8336 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8342 egcm_load_index_reg(ctx
->bc
, 1, false);
8343 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_MEM_RAT
);
8344 cf
= ctx
->bc
->cf_last
;
8346 cf
->rat
.id
= rat_base
+ inst
->Src
[0].Register
.Index
;
8347 cf
->rat
.inst
= ctx
->inst_info
->op
;
8348 cf
->rat
.index_mode
= rat_index_mode
;
8349 cf
->output
.type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND
;
8350 cf
->output
.gpr
= ctx
->thread_id_gpr
;
8351 cf
->output
.index_gpr
= idx_gpr
;
8352 cf
->output
.comp_mask
= 0xf;
8353 cf
->output
.burst_count
= 1;
8357 cf
->output
.elem_size
= 0;
8358 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_WAIT_ACK
);
8359 cf
= ctx
->bc
->cf_last
;
8363 memset(&vtx
, 0, sizeof(struct r600_bytecode_vtx
));
8364 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
) {
8365 desc
= util_format_description(inst
->Memory
.Format
);
8366 r600_vertex_data_type(inst
->Memory
.Format
,
8367 &format
, &num_format
, &format_comp
, &endian
);
8368 vtx
.dst_sel_x
= desc
->swizzle
[0];
8376 vtx
.op
= FETCH_OP_VFETCH
;
8377 vtx
.buffer_id
= immed_base
+ inst
->Src
[0].Register
.Index
;
8378 vtx
.buffer_index_mode
= rat_index_mode
;
8379 vtx
.fetch_type
= SQ_VTX_FETCH_NO_INDEX_OFFSET
;
8380 vtx
.src_gpr
= ctx
->thread_id_gpr
;
8382 vtx
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8386 vtx
.use_const_fields
= 0;
8387 vtx
.srf_mode_all
= 1;
8388 vtx
.data_format
= format
;
8389 vtx
.num_format_all
= num_format
;
8390 vtx
.format_comp_all
= format_comp
;
8391 vtx
.endian
= endian
;
8393 vtx
.mega_fetch_count
= 0xf;
8394 r
= r600_bytecode_add_vtx_tc(ctx
->bc
, &vtx
);
8397 cf
= ctx
->bc
->cf_last
;
8403 static int get_gds_op(int opcode
)
8406 case TGSI_OPCODE_ATOMUADD
:
8407 return FETCH_OP_GDS_ADD_RET
;
8408 case TGSI_OPCODE_ATOMAND
:
8409 return FETCH_OP_GDS_AND_RET
;
8410 case TGSI_OPCODE_ATOMOR
:
8411 return FETCH_OP_GDS_OR_RET
;
8412 case TGSI_OPCODE_ATOMXOR
:
8413 return FETCH_OP_GDS_XOR_RET
;
8414 case TGSI_OPCODE_ATOMUMIN
:
8415 return FETCH_OP_GDS_MIN_UINT_RET
;
8416 case TGSI_OPCODE_ATOMUMAX
:
8417 return FETCH_OP_GDS_MAX_UINT_RET
;
8418 case TGSI_OPCODE_ATOMXCHG
:
8419 return FETCH_OP_GDS_XCHG_RET
;
8420 case TGSI_OPCODE_ATOMCAS
:
8421 return FETCH_OP_GDS_CMP_XCHG_RET
;
8427 static int tgsi_atomic_op_gds(struct r600_shader_ctx
*ctx
)
8429 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8430 struct r600_bytecode_gds gds
;
8431 struct r600_bytecode_alu alu
;
8432 int gds_op
= get_gds_op(inst
->Instruction
.Opcode
);
8435 int uav_index_mode
= 0;
8436 bool is_cm
= (ctx
->bc
->chip_class
== CAYMAN
);
8439 fprintf(stderr
, "unknown GDS op for opcode %d\n", inst
->Instruction
.Opcode
);
8443 r
= tgsi_set_gds_temp(ctx
, &uav_id
, &uav_index_mode
);
8447 if (inst
->Src
[2].Register
.File
== TGSI_FILE_IMMEDIATE
) {
8448 int value
= (ctx
->literals
[4 * inst
->Src
[2].Register
.Index
+ inst
->Src
[2].Register
.SwizzleX
]);
8449 int abs_value
= abs(value
);
8450 if (abs_value
!= value
&& gds_op
== FETCH_OP_GDS_ADD_RET
)
8451 gds_op
= FETCH_OP_GDS_SUB_RET
;
8452 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8453 alu
.op
= ALU_OP1_MOV
;
8454 alu
.dst
.sel
= ctx
->temp_reg
;
8455 alu
.dst
.chan
= is_cm
? 1 : 0;
8456 alu
.src
[0].sel
= V_SQ_ALU_SRC_LITERAL
;
8457 alu
.src
[0].value
= abs_value
;
8460 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8464 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8465 alu
.op
= ALU_OP1_MOV
;
8466 alu
.dst
.sel
= ctx
->temp_reg
;
8467 alu
.dst
.chan
= is_cm
? 1 : 0;
8468 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], 0);
8471 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8477 memset(&gds
, 0, sizeof(struct r600_bytecode_gds
));
8479 gds
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8480 gds
.uav_id
= is_cm
? 0 : uav_id
;
8481 gds
.uav_index_mode
= is_cm
? 0 : uav_index_mode
;
8482 gds
.src_gpr
= ctx
->temp_reg
;
8484 gds
.src_sel_x
= is_cm
? 0 : 4;
8485 gds
.src_sel_y
= is_cm
? 1 : 0;
8491 gds
.alloc_consume
= !is_cm
;
8493 r
= r600_bytecode_add_gds(ctx
->bc
, &gds
);
8496 ctx
->bc
->cf_last
->vpm
= 1;
8500 static int tgsi_atomic_op(struct r600_shader_ctx
*ctx
)
8502 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8503 if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
)
8504 return tgsi_atomic_op_rat(ctx
);
8505 if (inst
->Src
[0].Register
.File
== TGSI_FILE_HW_ATOMIC
)
8506 return tgsi_atomic_op_gds(ctx
);
8507 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
)
8508 return tgsi_atomic_op_rat(ctx
);
8512 static int tgsi_resq(struct r600_shader_ctx
*ctx
)
8514 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8515 unsigned sampler_index_mode
;
8516 struct r600_bytecode_tex tex
;
8518 boolean has_txq_cube_array_z
= false;
8520 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
8521 (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
&& inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
)) {
8522 ctx
->shader
->uses_tex_buffers
= true;
8523 return r600_do_buffer_txq(ctx
, 0, ctx
->shader
->image_size_const_offset
);
8526 if (inst
->Memory
.Texture
== TGSI_TEXTURE_CUBE_ARRAY
&&
8527 inst
->Dst
[0].Register
.WriteMask
& 4) {
8528 ctx
->shader
->has_txq_cube_array_z_comp
= true;
8529 has_txq_cube_array_z
= true;
8532 sampler_index_mode
= inst
->Src
[0].Indirect
.Index
== 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8533 if (sampler_index_mode
)
8534 egcm_load_index_reg(ctx
->bc
, 1, false);
8537 /* does this shader want a num layers from TXQ for a cube array? */
8538 if (has_txq_cube_array_z
) {
8539 int id
= tgsi_tex_get_src_gpr(ctx
, 0) + ctx
->shader
->image_size_const_offset
;
8540 struct r600_bytecode_alu alu
;
8542 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8543 alu
.op
= ALU_OP1_MOV
;
8545 alu
.src
[0].sel
= R600_SHADER_BUFFER_INFO_SEL
;
8546 /* channel 1 or 3 of each word */
8547 alu
.src
[0].sel
+= (id
/ 2);
8548 alu
.src
[0].chan
= ((id
% 2) * 2) + 1;
8549 alu
.src
[0].kc_bank
= R600_BUFFER_INFO_CONST_BUFFER
;
8550 tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
8552 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8555 /* disable writemask from texture instruction */
8556 inst
->Dst
[0].Register
.WriteMask
&= ~4;
8558 memset(&tex
, 0, sizeof(struct r600_bytecode_tex
));
8559 tex
.op
= ctx
->inst_info
->op
;
8560 tex
.sampler_id
= R600_IMAGE_REAL_RESOURCE_OFFSET
+ inst
->Src
[0].Register
.Index
;
8561 tex
.sampler_index_mode
= sampler_index_mode
;
8562 tex
.resource_id
= tex
.sampler_id
;
8563 tex
.resource_index_mode
= sampler_index_mode
;
8568 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
8569 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
8570 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
8571 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
8572 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
8573 r
= r600_bytecode_add_tex(ctx
->bc
, &tex
);
8580 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
8582 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8583 struct r600_bytecode_alu alu
;
8584 unsigned lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8585 unsigned i
, temp_regs
[2];
8588 /* optimize if it's just an equal balance */
8589 if (ctx
->src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
8590 for (i
= 0; i
< lasti
+ 1; i
++) {
8591 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8594 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8595 alu
.op
= ALU_OP2_ADD
;
8596 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[1], i
);
8597 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8599 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8604 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8612 for (i
= 0; i
< lasti
+ 1; i
++) {
8613 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8616 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8617 alu
.op
= ALU_OP2_ADD
;
8618 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8619 alu
.src
[0].chan
= 0;
8620 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[0], i
);
8621 r600_bytecode_src_toggle_neg(&alu
.src
[1]);
8622 alu
.dst
.sel
= ctx
->temp_reg
;
8628 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8633 /* (1 - src0) * src2 */
8634 for (i
= 0; i
< lasti
+ 1; i
++) {
8635 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8638 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8639 alu
.op
= ALU_OP2_MUL
;
8640 alu
.src
[0].sel
= ctx
->temp_reg
;
8641 alu
.src
[0].chan
= i
;
8642 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8643 alu
.dst
.sel
= ctx
->temp_reg
;
8649 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8654 /* src0 * src1 + (1 - src0) * src2 */
8655 if (ctx
->src
[0].abs
)
8656 temp_regs
[0] = r600_get_temp(ctx
);
8659 if (ctx
->src
[1].abs
)
8660 temp_regs
[1] = r600_get_temp(ctx
);
8664 for (i
= 0; i
< lasti
+ 1; i
++) {
8665 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8668 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8669 alu
.op
= ALU_OP3_MULADD
;
8671 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
8674 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[1], &ctx
->src
[1]);
8677 alu
.src
[2].sel
= ctx
->temp_reg
;
8678 alu
.src
[2].chan
= i
;
8680 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8685 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8692 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
8694 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8695 struct r600_bytecode_alu alu
;
8697 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8701 if (ctx
->src
[0].abs
&& ctx
->src
[0].neg
) {
8703 ctx
->src
[0].abs
= 0;
8704 ctx
->src
[0].neg
= 0;
8709 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
8711 if (ctx
->src
[j
].abs
)
8712 temp_regs
[j
] = r600_get_temp(ctx
);
8715 for (i
= 0; i
< lasti
+ 1; i
++) {
8716 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8719 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8721 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[0], i
, &alu
.src
[0], &ctx
->src
[0]);
8724 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[2], i
, &alu
.src
[1], &ctx
->src
[2]);
8727 r
= tgsi_make_src_for_op3(ctx
, temp_regs
[1], i
, &alu
.src
[2], &ctx
->src
[1]);
8730 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8736 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8743 static int tgsi_ucmp(struct r600_shader_ctx
*ctx
)
8745 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8746 struct r600_bytecode_alu alu
;
8748 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
8750 for (i
= 0; i
< lasti
+ 1; i
++) {
8751 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
8754 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8755 alu
.op
= ALU_OP3_CNDE_INT
;
8756 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
8757 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
8758 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[1], i
);
8759 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8765 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8772 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
8774 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8775 struct r600_bytecode_alu alu
;
8779 /* result.x = 2^floor(src); */
8780 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8781 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8783 alu
.op
= ALU_OP1_FLOOR
;
8784 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8786 alu
.dst
.sel
= ctx
->temp_reg
;
8790 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8794 if (ctx
->bc
->chip_class
== CAYMAN
) {
8795 for (i
= 0; i
< 3; i
++) {
8796 alu
.op
= ALU_OP1_EXP_IEEE
;
8797 alu
.src
[0].sel
= ctx
->temp_reg
;
8798 alu
.src
[0].chan
= 0;
8800 alu
.dst
.sel
= ctx
->temp_reg
;
8802 alu
.dst
.write
= i
== 0;
8804 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8809 alu
.op
= ALU_OP1_EXP_IEEE
;
8810 alu
.src
[0].sel
= ctx
->temp_reg
;
8811 alu
.src
[0].chan
= 0;
8813 alu
.dst
.sel
= ctx
->temp_reg
;
8817 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8823 /* result.y = tmp - floor(tmp); */
8824 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8825 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8827 alu
.op
= ALU_OP1_FRACT
;
8828 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8830 alu
.dst
.sel
= ctx
->temp_reg
;
8832 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
8841 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8846 /* result.z = RoughApprox2ToX(tmp);*/
8847 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
8848 if (ctx
->bc
->chip_class
== CAYMAN
) {
8849 for (i
= 0; i
< 3; i
++) {
8850 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8851 alu
.op
= ALU_OP1_EXP_IEEE
;
8852 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8854 alu
.dst
.sel
= ctx
->temp_reg
;
8861 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8866 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8867 alu
.op
= ALU_OP1_EXP_IEEE
;
8868 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8870 alu
.dst
.sel
= ctx
->temp_reg
;
8876 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8882 /* result.w = 1.0;*/
8883 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
8884 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8886 alu
.op
= ALU_OP1_MOV
;
8887 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
8888 alu
.src
[0].chan
= 0;
8890 alu
.dst
.sel
= ctx
->temp_reg
;
8894 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8898 return tgsi_helper_copy(ctx
, inst
);
8901 static int tgsi_log(struct r600_shader_ctx
*ctx
)
8903 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
8904 struct r600_bytecode_alu alu
;
8908 /* result.x = floor(log2(|src|)); */
8909 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
8910 if (ctx
->bc
->chip_class
== CAYMAN
) {
8911 for (i
= 0; i
< 3; i
++) {
8912 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8914 alu
.op
= ALU_OP1_LOG_IEEE
;
8915 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8916 r600_bytecode_src_set_abs(&alu
.src
[0]);
8918 alu
.dst
.sel
= ctx
->temp_reg
;
8924 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8930 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8932 alu
.op
= ALU_OP1_LOG_IEEE
;
8933 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8934 r600_bytecode_src_set_abs(&alu
.src
[0]);
8936 alu
.dst
.sel
= ctx
->temp_reg
;
8940 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8945 alu
.op
= ALU_OP1_FLOOR
;
8946 alu
.src
[0].sel
= ctx
->temp_reg
;
8947 alu
.src
[0].chan
= 0;
8949 alu
.dst
.sel
= ctx
->temp_reg
;
8954 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8959 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8960 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
8962 if (ctx
->bc
->chip_class
== CAYMAN
) {
8963 for (i
= 0; i
< 3; i
++) {
8964 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8966 alu
.op
= ALU_OP1_LOG_IEEE
;
8967 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8968 r600_bytecode_src_set_abs(&alu
.src
[0]);
8970 alu
.dst
.sel
= ctx
->temp_reg
;
8977 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8982 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
8984 alu
.op
= ALU_OP1_LOG_IEEE
;
8985 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
8986 r600_bytecode_src_set_abs(&alu
.src
[0]);
8988 alu
.dst
.sel
= ctx
->temp_reg
;
8993 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
8998 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9000 alu
.op
= ALU_OP1_FLOOR
;
9001 alu
.src
[0].sel
= ctx
->temp_reg
;
9002 alu
.src
[0].chan
= 1;
9004 alu
.dst
.sel
= ctx
->temp_reg
;
9009 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9013 if (ctx
->bc
->chip_class
== CAYMAN
) {
9014 for (i
= 0; i
< 3; i
++) {
9015 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9016 alu
.op
= ALU_OP1_EXP_IEEE
;
9017 alu
.src
[0].sel
= ctx
->temp_reg
;
9018 alu
.src
[0].chan
= 1;
9020 alu
.dst
.sel
= ctx
->temp_reg
;
9027 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9032 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9033 alu
.op
= ALU_OP1_EXP_IEEE
;
9034 alu
.src
[0].sel
= ctx
->temp_reg
;
9035 alu
.src
[0].chan
= 1;
9037 alu
.dst
.sel
= ctx
->temp_reg
;
9042 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9047 if (ctx
->bc
->chip_class
== CAYMAN
) {
9048 for (i
= 0; i
< 3; i
++) {
9049 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9050 alu
.op
= ALU_OP1_RECIP_IEEE
;
9051 alu
.src
[0].sel
= ctx
->temp_reg
;
9052 alu
.src
[0].chan
= 1;
9054 alu
.dst
.sel
= ctx
->temp_reg
;
9061 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9066 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9067 alu
.op
= ALU_OP1_RECIP_IEEE
;
9068 alu
.src
[0].sel
= ctx
->temp_reg
;
9069 alu
.src
[0].chan
= 1;
9071 alu
.dst
.sel
= ctx
->temp_reg
;
9076 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9081 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9083 alu
.op
= ALU_OP2_MUL
;
9085 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9086 r600_bytecode_src_set_abs(&alu
.src
[0]);
9088 alu
.src
[1].sel
= ctx
->temp_reg
;
9089 alu
.src
[1].chan
= 1;
9091 alu
.dst
.sel
= ctx
->temp_reg
;
9096 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9101 /* result.z = log2(|src|);*/
9102 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
9103 if (ctx
->bc
->chip_class
== CAYMAN
) {
9104 for (i
= 0; i
< 3; i
++) {
9105 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9107 alu
.op
= ALU_OP1_LOG_IEEE
;
9108 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9109 r600_bytecode_src_set_abs(&alu
.src
[0]);
9111 alu
.dst
.sel
= ctx
->temp_reg
;
9118 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9123 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9125 alu
.op
= ALU_OP1_LOG_IEEE
;
9126 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9127 r600_bytecode_src_set_abs(&alu
.src
[0]);
9129 alu
.dst
.sel
= ctx
->temp_reg
;
9134 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9140 /* result.w = 1.0; */
9141 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
9142 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9144 alu
.op
= ALU_OP1_MOV
;
9145 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
9146 alu
.src
[0].chan
= 0;
9148 alu
.dst
.sel
= ctx
->temp_reg
;
9153 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9158 return tgsi_helper_copy(ctx
, inst
);
9161 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
9163 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9164 struct r600_bytecode_alu alu
;
9166 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9167 unsigned reg
= get_address_file_reg(ctx
, inst
->Dst
[0].Register
.Index
);
9169 assert(inst
->Dst
[0].Register
.Index
< 3);
9170 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9172 switch (inst
->Instruction
.Opcode
) {
9173 case TGSI_OPCODE_ARL
:
9174 alu
.op
= ALU_OP1_FLT_TO_INT_FLOOR
;
9176 case TGSI_OPCODE_ARR
:
9177 alu
.op
= ALU_OP1_FLT_TO_INT
;
9179 case TGSI_OPCODE_UARL
:
9180 alu
.op
= ALU_OP1_MOV
;
9187 for (i
= 0; i
<= lasti
; ++i
) {
9188 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9190 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9191 alu
.last
= i
== lasti
;
9195 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9200 if (inst
->Dst
[0].Register
.Index
> 0)
9201 ctx
->bc
->index_loaded
[inst
->Dst
[0].Register
.Index
- 1] = 0;
9203 ctx
->bc
->ar_loaded
= 0;
9207 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
9209 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9210 struct r600_bytecode_alu alu
;
9212 int i
, lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9214 switch (inst
->Instruction
.Opcode
) {
9215 case TGSI_OPCODE_ARL
:
9216 memset(&alu
, 0, sizeof(alu
));
9217 alu
.op
= ALU_OP1_FLOOR
;
9218 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9220 for (i
= 0; i
<= lasti
; ++i
) {
9221 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
9223 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9224 alu
.last
= i
== lasti
;
9225 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9230 memset(&alu
, 0, sizeof(alu
));
9231 alu
.op
= ALU_OP1_FLT_TO_INT
;
9232 alu
.src
[0].sel
= ctx
->bc
->ar_reg
;
9233 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9235 /* FLT_TO_INT is trans-only on r600/r700 */
9237 for (i
= 0; i
<= lasti
; ++i
) {
9239 alu
.src
[0].chan
= i
;
9240 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9244 case TGSI_OPCODE_ARR
:
9245 memset(&alu
, 0, sizeof(alu
));
9246 alu
.op
= ALU_OP1_FLT_TO_INT
;
9247 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9249 /* FLT_TO_INT is trans-only on r600/r700 */
9251 for (i
= 0; i
<= lasti
; ++i
) {
9252 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
9254 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9255 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9260 case TGSI_OPCODE_UARL
:
9261 memset(&alu
, 0, sizeof(alu
));
9262 alu
.op
= ALU_OP1_MOV
;
9263 alu
.dst
.sel
= ctx
->bc
->ar_reg
;
9265 for (i
= 0; i
<= lasti
; ++i
) {
9266 if (inst
->Dst
[0].Register
.WriteMask
& (1 << i
)) {
9268 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9269 alu
.last
= i
== lasti
;
9270 if ((r
= r600_bytecode_add_alu(ctx
->bc
, &alu
)))
9280 ctx
->bc
->ar_loaded
= 0;
9284 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
9286 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9287 struct r600_bytecode_alu alu
;
9290 for (i
= 0; i
< 4; i
++) {
9291 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9293 alu
.op
= ALU_OP2_MUL
;
9294 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9296 if (i
== 0 || i
== 3) {
9297 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
9299 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], i
);
9302 if (i
== 0 || i
== 2) {
9303 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
9305 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[1], i
);
9309 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9316 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
, int alu_type
)
9318 struct r600_bytecode_alu alu
;
9321 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9323 alu
.execute_mask
= 1;
9324 alu
.update_pred
= 1;
9326 alu
.dst
.sel
= ctx
->temp_reg
;
9330 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9331 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
9332 alu
.src
[1].chan
= 0;
9336 r
= r600_bytecode_add_alu_type(ctx
->bc
, &alu
, alu_type
);
9342 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
9344 unsigned force_pop
= ctx
->bc
->force_add_cf
;
9348 if (ctx
->bc
->cf_last
) {
9349 if (ctx
->bc
->cf_last
->op
== CF_OP_ALU
)
9351 else if (ctx
->bc
->cf_last
->op
== CF_OP_ALU_POP_AFTER
)
9356 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP_AFTER
;
9357 ctx
->bc
->force_add_cf
= 1;
9358 } else if (alu_pop
== 2) {
9359 ctx
->bc
->cf_last
->op
= CF_OP_ALU_POP2_AFTER
;
9360 ctx
->bc
->force_add_cf
= 1;
9367 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_POP
);
9368 ctx
->bc
->cf_last
->pop_count
= pops
;
9369 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9375 static inline void callstack_update_max_depth(struct r600_shader_ctx
*ctx
,
9378 struct r600_stack_info
*stack
= &ctx
->bc
->stack
;
9382 unsigned entry_size
= stack
->entry_size
;
9384 elements
= (stack
->loop
+ stack
->push_wqm
) * entry_size
;
9385 elements
+= stack
->push
;
9387 switch (ctx
->bc
->chip_class
) {
9390 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9391 * the stack must be reserved to hold the current active/continue
9393 if (reason
== FC_PUSH_VPM
) {
9399 /* r9xx: any stack operation on empty stack consumes 2 additional
9404 /* FIXME: do the two elements added above cover the cases for the
9408 /* r8xx+: 2 extra elements are not always required, but one extra
9409 * element must be added for each of the following cases:
9410 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9412 * (Currently we don't use ALU_ELSE_AFTER.)
9413 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9414 * PUSH instruction executed.
9416 * NOTE: it seems we also need to reserve additional element in some
9417 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9418 * then STACK_SIZE should be 2 instead of 1 */
9419 if (reason
== FC_PUSH_VPM
) {
9429 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9430 * for all chips, so we use 4 in the final formula, not the real entry_size
9434 entries
= (elements
+ (entry_size
- 1)) / entry_size
;
9436 if (entries
> stack
->max_entries
)
9437 stack
->max_entries
= entries
;
9440 static inline void callstack_pop(struct r600_shader_ctx
*ctx
, unsigned reason
)
9444 --ctx
->bc
->stack
.push
;
9445 assert(ctx
->bc
->stack
.push
>= 0);
9448 --ctx
->bc
->stack
.push_wqm
;
9449 assert(ctx
->bc
->stack
.push_wqm
>= 0);
9452 --ctx
->bc
->stack
.loop
;
9453 assert(ctx
->bc
->stack
.loop
>= 0);
9461 static inline void callstack_push(struct r600_shader_ctx
*ctx
, unsigned reason
)
9465 ++ctx
->bc
->stack
.push
;
9468 ++ctx
->bc
->stack
.push_wqm
;
9470 ++ctx
->bc
->stack
.loop
;
9476 callstack_update_max_depth(ctx
, reason
);
9479 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
9481 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
9483 sp
->mid
= realloc((void *)sp
->mid
,
9484 sizeof(struct r600_bytecode_cf
*) * (sp
->num_mid
+ 1));
9485 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
9489 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
9491 assert(ctx
->bc
->fc_sp
< ARRAY_SIZE(ctx
->bc
->fc_stack
));
9492 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
9493 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
9497 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
9499 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1];
9509 static int emit_return(struct r600_shader_ctx
*ctx
)
9511 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_RETURN
));
9515 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
9518 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
));
9519 ctx
->bc
->cf_last
->pop_count
= pops
;
9520 /* XXX work out offset */
9524 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
9529 static void emit_testflag(struct r600_shader_ctx
*ctx
)
9534 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
9537 emit_jump_to_offset(ctx
, 1, 4);
9538 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
9539 pops(ctx
, ifidx
+ 1);
9543 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
9547 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9548 ctx
->bc
->cf_last
->pop_count
= 1;
9550 fc_set_mid(ctx
, fc_sp
);
9556 static int emit_if(struct r600_shader_ctx
*ctx
, int opcode
)
9558 int alu_type
= CF_OP_ALU_PUSH_BEFORE
;
9560 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9561 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9562 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9563 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9564 if (ctx
->bc
->chip_class
== CAYMAN
&& ctx
->bc
->stack
.loop
> 1) {
9565 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_PUSH
);
9566 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9567 alu_type
= CF_OP_ALU
;
9570 emit_logic_pred(ctx
, opcode
, alu_type
);
9572 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_JUMP
);
9574 fc_pushlevel(ctx
, FC_IF
);
9576 callstack_push(ctx
, FC_PUSH_VPM
);
9580 static int tgsi_if(struct r600_shader_ctx
*ctx
)
9582 return emit_if(ctx
, ALU_OP2_PRED_SETNE
);
9585 static int tgsi_uif(struct r600_shader_ctx
*ctx
)
9587 return emit_if(ctx
, ALU_OP2_PRED_SETNE_INT
);
9590 static int tgsi_else(struct r600_shader_ctx
*ctx
)
9592 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_ELSE
);
9593 ctx
->bc
->cf_last
->pop_count
= 1;
9595 fc_set_mid(ctx
, ctx
->bc
->fc_sp
- 1);
9596 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
9600 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
9603 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_IF
) {
9604 R600_ERR("if/endif unbalanced in shader\n");
9608 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
== NULL
) {
9609 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9610 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->pop_count
= 1;
9612 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9616 callstack_pop(ctx
, FC_PUSH_VPM
);
9620 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
9622 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9623 * limited to 4096 iterations, like the other LOOP_* instructions. */
9624 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_START_DX10
);
9626 fc_pushlevel(ctx
, FC_LOOP
);
9628 /* check stack depth */
9629 callstack_push(ctx
, FC_LOOP
);
9633 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
9637 r600_bytecode_add_cfinst(ctx
->bc
, CF_OP_LOOP_END
);
9639 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].type
!= FC_LOOP
) {
9640 R600_ERR("loop/endloop in shader code are not paired.\n");
9644 /* fixup loop pointers - from r600isa
9645 LOOP END points to CF after LOOP START,
9646 LOOP START point to CF after LOOP END
9647 BRK/CONT point to LOOP END CF
9649 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->id
+ 2;
9651 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
9653 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].num_mid
; i
++) {
9654 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
- 1].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
9656 /* XXX add LOOPRET support */
9658 callstack_pop(ctx
, FC_LOOP
);
9662 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
9666 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
9668 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
- 1].type
)
9673 R600_ERR("Break not inside loop/endloop pair\n");
9677 r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9679 fc_set_mid(ctx
, fscp
- 1);
9684 static int tgsi_gs_emit(struct r600_shader_ctx
*ctx
)
9686 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9687 int stream
= ctx
->literals
[inst
->Src
[0].Register
.Index
* 4 + inst
->Src
[0].Register
.SwizzleX
];
9690 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
9691 emit_gs_ring_writes(ctx
, ctx
->gs_stream_output_info
, stream
, TRUE
);
9693 r
= r600_bytecode_add_cfinst(ctx
->bc
, ctx
->inst_info
->op
);
9695 ctx
->bc
->cf_last
->count
= stream
; // Count field for CUT/EMIT_VERTEX indicates which stream
9696 if (ctx
->inst_info
->op
== CF_OP_EMIT_VERTEX
)
9697 return emit_inc_ring_offset(ctx
, stream
, TRUE
);
9702 static int tgsi_umad(struct r600_shader_ctx
*ctx
)
9704 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9705 struct r600_bytecode_alu alu
;
9707 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9710 for (i
= 0; i
< lasti
+ 1; i
++) {
9711 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9714 if (ctx
->bc
->chip_class
== CAYMAN
) {
9715 for (j
= 0 ; j
< 4; j
++) {
9716 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9718 alu
.op
= ALU_OP2_MULLO_UINT
;
9719 for (k
= 0; k
< inst
->Instruction
.NumSrcRegs
; k
++) {
9720 r600_bytecode_src(&alu
.src
[k
], &ctx
->src
[k
], i
);
9723 alu
.dst
.sel
= ctx
->temp_reg
;
9724 alu
.dst
.write
= (j
== i
);
9727 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9732 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9735 alu
.dst
.sel
= ctx
->temp_reg
;
9738 alu
.op
= ALU_OP2_MULLO_UINT
;
9739 for (j
= 0; j
< 2; j
++) {
9740 r600_bytecode_src(&alu
.src
[j
], &ctx
->src
[j
], i
);
9744 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9751 for (i
= 0; i
< lasti
+ 1; i
++) {
9752 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9755 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9756 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9758 alu
.op
= ALU_OP2_ADD_INT
;
9760 alu
.src
[0].sel
= ctx
->temp_reg
;
9761 alu
.src
[0].chan
= i
;
9763 r600_bytecode_src(&alu
.src
[1], &ctx
->src
[2], i
);
9767 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9774 static int tgsi_pk2h(struct r600_shader_ctx
*ctx
)
9776 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9777 struct r600_bytecode_alu alu
;
9779 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9781 /* temp.xy = f32_to_f16(src) */
9782 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9783 alu
.op
= ALU_OP1_FLT32_TO_FLT16
;
9785 alu
.dst
.sel
= ctx
->temp_reg
;
9787 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9788 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9792 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 1);
9794 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9798 /* dst.x = temp.y * 0x10000 + temp.x */
9799 for (i
= 0; i
< lasti
+ 1; i
++) {
9800 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9803 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9804 alu
.op
= ALU_OP3_MULADD_UINT24
;
9806 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9807 alu
.last
= i
== lasti
;
9808 alu
.src
[0].sel
= ctx
->temp_reg
;
9809 alu
.src
[0].chan
= 1;
9810 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9811 alu
.src
[1].value
= 0x10000;
9812 alu
.src
[2].sel
= ctx
->temp_reg
;
9813 alu
.src
[2].chan
= 0;
9814 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9822 static int tgsi_up2h(struct r600_shader_ctx
*ctx
)
9824 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9825 struct r600_bytecode_alu alu
;
9827 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9829 /* temp.x = src.x */
9830 /* note: no need to mask out the high bits */
9831 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9832 alu
.op
= ALU_OP1_MOV
;
9834 alu
.dst
.sel
= ctx
->temp_reg
;
9836 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9837 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9841 /* temp.y = src.x >> 16 */
9842 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9843 alu
.op
= ALU_OP2_LSHR_INT
;
9845 alu
.dst
.sel
= ctx
->temp_reg
;
9847 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[0], 0);
9848 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9849 alu
.src
[1].value
= 16;
9851 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9855 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9856 for (i
= 0; i
< lasti
+ 1; i
++) {
9857 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
9859 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9860 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9861 alu
.op
= ALU_OP1_FLT16_TO_FLT32
;
9862 alu
.src
[0].sel
= ctx
->temp_reg
;
9863 alu
.src
[0].chan
= i
% 2;
9864 alu
.last
= i
== lasti
;
9865 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9873 static int tgsi_bfe(struct r600_shader_ctx
*ctx
)
9875 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
9876 struct r600_bytecode_alu alu
;
9877 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
9881 if ((inst
->Src
[0].Register
.File
== inst
->Dst
[0].Register
.File
&&
9882 inst
->Src
[0].Register
.Index
== inst
->Dst
[0].Register
.Index
) ||
9883 (inst
->Src
[2].Register
.File
== inst
->Dst
[0].Register
.File
&&
9884 inst
->Src
[2].Register
.Index
== inst
->Dst
[0].Register
.Index
))
9885 dst
= r600_get_temp(ctx
);
9887 r
= tgsi_op3_dst(ctx
, dst
);
9891 for (i
= 0; i
< lasti
+ 1; i
++) {
9892 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9893 alu
.op
= ALU_OP2_SETGE_INT
;
9894 r600_bytecode_src(&alu
.src
[0], &ctx
->src
[2], i
);
9895 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
9896 alu
.src
[1].value
= 32;
9897 alu
.dst
.sel
= ctx
->temp_reg
;
9902 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9907 for (i
= 0; i
< lasti
+ 1; i
++) {
9908 memset(&alu
, 0, sizeof(struct r600_bytecode_alu
));
9909 alu
.op
= ALU_OP3_CNDE_INT
;
9911 alu
.src
[0].sel
= ctx
->temp_reg
;
9912 alu
.src
[0].chan
= i
;
9914 tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
9916 alu
.src
[1].sel
= dst
;
9918 alu
.src
[1].sel
= alu
.dst
.sel
;
9919 alu
.src
[1].chan
= i
;
9920 r600_bytecode_src(&alu
.src
[2], &ctx
->src
[0], i
);
9924 r
= r600_bytecode_add_alu(ctx
->bc
, &alu
);
9932 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
9933 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9934 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
9935 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
9937 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
9939 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
9940 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
9941 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
9942 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
9943 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
9944 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9945 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
9946 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
9947 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
9948 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
9949 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
9950 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
9951 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
9952 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
9953 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
9954 [TGSI_OPCODE_FMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9955 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
9956 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
9957 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
9958 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
9959 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
9960 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
9961 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
9962 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
9963 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
9964 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
9965 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
9966 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
9967 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
9968 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
9969 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
9970 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
9971 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
9972 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
9973 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
9974 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
9975 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9976 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9977 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9978 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9979 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
9980 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
9981 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
9982 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
9983 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
9984 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
9985 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
9986 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
9987 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9988 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
9989 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
9990 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9991 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9992 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9993 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9994 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
9995 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
9996 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_r600_arl
},
9997 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
9998 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
9999 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10000 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
10001 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
10002 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
10003 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10004 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
10005 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10006 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10007 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10008 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
10009 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
10010 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
10011 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
10012 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
10013 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
10014 [TGSI_OPCODE_DDX_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10015 [TGSI_OPCODE_DDY_FINE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10016 [81] = { ALU_OP0_NOP
, tgsi_unsupported
},
10017 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
10018 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
10019 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
10020 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
10021 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
10022 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2_trans
},
10023 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
10024 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
10025 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
10026 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
10027 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
10028 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
10029 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
10030 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10031 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
10032 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
10033 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
10034 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
10035 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10036 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
10037 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10038 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10039 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
10040 [TGSI_OPCODE_RESQ
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10041 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
10042 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10043 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
10044 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
10045 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
10046 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
10047 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10048 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
10049 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
10050 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
10051 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
10052 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
10053 [TGSI_OPCODE_DFMA
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10054 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2_trans
},
10055 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
10056 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
10057 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
10058 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
10059 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
10060 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2_trans
},
10061 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
10062 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2_trans
},
10063 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
10064 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
10065 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
10066 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
10067 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
10068 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
10069 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
10070 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
10071 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
10072 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
10073 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2_trans
},
10074 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
10075 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2_swap
},
10076 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10077 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10078 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10079 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10080 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
10081 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
10082 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
10083 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
10084 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
10085 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
10086 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
10087 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
10088 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
10089 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
10090 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
10091 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
10092 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_r600_arl
},
10093 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
10094 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
10095 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
10096 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10097 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10098 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
10099 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
10100 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
10101 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10102 [TGSI_OPCODE_ATOMUADD
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10103 [TGSI_OPCODE_ATOMXCHG
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10104 [TGSI_OPCODE_ATOMCAS
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10105 [TGSI_OPCODE_ATOMAND
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10106 [TGSI_OPCODE_ATOMOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10107 [TGSI_OPCODE_ATOMXOR
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10108 [TGSI_OPCODE_ATOMUMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10109 [TGSI_OPCODE_ATOMUMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10110 [TGSI_OPCODE_ATOMIMIN
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10111 [TGSI_OPCODE_ATOMIMAX
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10112 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10113 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10114 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10115 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
10116 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
10117 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_unsupported
},
10118 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_unsupported
},
10119 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_unsupported
},
10120 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_unsupported
},
10121 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10122 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_unsupported
},
10123 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_unsupported
},
10124 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_unsupported
},
10125 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_unsupported
},
10126 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_unsupported
},
10127 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10128 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10129 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10130 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10133 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
10134 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10135 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
10136 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
10137 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
10138 [TGSI_OPCODE_RSQ
] = { ALU_OP0_NOP
, tgsi_rsq
},
10139 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
10140 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
10141 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
10142 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
10143 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10144 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10145 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
10146 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
10147 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
10148 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
10149 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
10150 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
10151 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
10152 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
10153 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, tgsi_trans_srcx_replicate
},
10154 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
10155 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
10156 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
10157 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
10158 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
10159 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
10160 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
10161 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, tgsi_trans_srcx_replicate
},
10162 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, tgsi_trans_srcx_replicate
},
10163 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, tgsi_pow
},
10164 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
10165 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
10166 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
10167 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
10168 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
10169 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, tgsi_trig
},
10170 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10171 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10172 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
10173 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
10174 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10175 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10176 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10177 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
10178 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
10179 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
10180 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
10181 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, tgsi_trig
},
10182 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
10183 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
10184 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
10185 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10186 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
10187 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10188 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
10189 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10190 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10191 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10192 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
10193 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
10194 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10195 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
10196 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10197 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10198 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
10199 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
10200 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
10201 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10202 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
10203 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10204 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10205 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10206 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
10207 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
10208 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
10209 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
10210 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
10211 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
10212 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10213 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10214 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
10215 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
10216 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2_trans
},
10217 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
10218 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
10219 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
10220 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
10221 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
10222 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
10223 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
10224 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
10225 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
10226 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
10227 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10228 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
10229 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
10230 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
10231 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
10232 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10233 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
10234 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10235 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10236 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
10237 [TGSI_OPCODE_RESQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_resq
},
10238 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
10239 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10240 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
10241 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
10242 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
10243 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
10244 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10245 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
10246 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
10247 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
10248 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
10249 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
10250 /* Refer below for TGSI_OPCODE_DFMA */
10251 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_f2i
},
10252 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
10253 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
10254 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
10255 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
10256 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
10257 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
10258 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
10259 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_f2i
},
10260 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2_trans
},
10261 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
10262 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
10263 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
10264 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
10265 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
10266 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
10267 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_UINT
, tgsi_op2_trans
},
10268 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
10269 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
10270 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
10271 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
10272 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
10273 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10274 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10275 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10276 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10277 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
10278 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
10279 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
10280 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
10281 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
10282 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
10283 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
10284 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
10285 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
10286 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
10287 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
10288 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
10289 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
10290 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
10291 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
10292 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
10293 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
10294 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_store
},
10295 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
10296 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
10297 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
10298 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10299 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
10300 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
10301 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
10302 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
10303 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
10304 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
10305 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
10306 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
10307 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
10308 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
10309 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10310 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10311 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10312 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, tgsi_op2_trans
},
10313 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, tgsi_op2_trans
},
10314 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
10315 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
10316 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
10317 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
10318 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
10319 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
10320 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
10321 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
10322 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
10323 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
10324 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10325 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10326 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10327 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
10328 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
10329 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
10330 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
10331 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
10332 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
10333 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
10334 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
10335 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
10336 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
10337 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
10338 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
10339 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
10340 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
10341 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
10342 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10343 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10344 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
10345 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
10346 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
10347 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
10348 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
10349 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
10350 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
10351 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
10352 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10355 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction
[] = {
10356 [TGSI_OPCODE_ARL
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10357 [TGSI_OPCODE_MOV
] = { ALU_OP1_MOV
, tgsi_op2
},
10358 [TGSI_OPCODE_LIT
] = { ALU_OP0_NOP
, tgsi_lit
},
10359 [TGSI_OPCODE_RCP
] = { ALU_OP1_RECIP_IEEE
, cayman_emit_float_instr
},
10360 [TGSI_OPCODE_RSQ
] = { ALU_OP1_RECIPSQRT_IEEE
, cayman_emit_float_instr
},
10361 [TGSI_OPCODE_EXP
] = { ALU_OP0_NOP
, tgsi_exp
},
10362 [TGSI_OPCODE_LOG
] = { ALU_OP0_NOP
, tgsi_log
},
10363 [TGSI_OPCODE_MUL
] = { ALU_OP2_MUL_IEEE
, tgsi_op2
},
10364 [TGSI_OPCODE_ADD
] = { ALU_OP2_ADD
, tgsi_op2
},
10365 [TGSI_OPCODE_DP3
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10366 [TGSI_OPCODE_DP4
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10367 [TGSI_OPCODE_DST
] = { ALU_OP0_NOP
, tgsi_opdst
},
10368 [TGSI_OPCODE_MIN
] = { ALU_OP2_MIN_DX10
, tgsi_op2
},
10369 [TGSI_OPCODE_MAX
] = { ALU_OP2_MAX_DX10
, tgsi_op2
},
10370 [TGSI_OPCODE_SLT
] = { ALU_OP2_SETGT
, tgsi_op2_swap
},
10371 [TGSI_OPCODE_SGE
] = { ALU_OP2_SETGE
, tgsi_op2
},
10372 [TGSI_OPCODE_MAD
] = { ALU_OP3_MULADD_IEEE
, tgsi_op3
},
10373 [TGSI_OPCODE_LRP
] = { ALU_OP0_NOP
, tgsi_lrp
},
10374 [TGSI_OPCODE_FMA
] = { ALU_OP3_FMA
, tgsi_op3
},
10375 [TGSI_OPCODE_SQRT
] = { ALU_OP1_SQRT_IEEE
, cayman_emit_float_instr
},
10376 [21] = { ALU_OP0_NOP
, tgsi_unsupported
},
10377 [22] = { ALU_OP0_NOP
, tgsi_unsupported
},
10378 [23] = { ALU_OP0_NOP
, tgsi_unsupported
},
10379 [TGSI_OPCODE_FRC
] = { ALU_OP1_FRACT
, tgsi_op2
},
10380 [25] = { ALU_OP0_NOP
, tgsi_unsupported
},
10381 [TGSI_OPCODE_FLR
] = { ALU_OP1_FLOOR
, tgsi_op2
},
10382 [TGSI_OPCODE_ROUND
] = { ALU_OP1_RNDNE
, tgsi_op2
},
10383 [TGSI_OPCODE_EX2
] = { ALU_OP1_EXP_IEEE
, cayman_emit_float_instr
},
10384 [TGSI_OPCODE_LG2
] = { ALU_OP1_LOG_IEEE
, cayman_emit_float_instr
},
10385 [TGSI_OPCODE_POW
] = { ALU_OP0_NOP
, cayman_pow
},
10386 [31] = { ALU_OP0_NOP
, tgsi_unsupported
},
10387 [32] = { ALU_OP0_NOP
, tgsi_unsupported
},
10388 [33] = { ALU_OP0_NOP
, tgsi_unsupported
},
10389 [34] = { ALU_OP0_NOP
, tgsi_unsupported
},
10390 [35] = { ALU_OP0_NOP
, tgsi_unsupported
},
10391 [TGSI_OPCODE_COS
] = { ALU_OP1_COS
, cayman_trig
},
10392 [TGSI_OPCODE_DDX
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10393 [TGSI_OPCODE_DDY
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10394 [TGSI_OPCODE_KILL
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* unconditional kill */
10395 [TGSI_OPCODE_PK2H
] = { ALU_OP0_NOP
, tgsi_pk2h
},
10396 [TGSI_OPCODE_PK2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10397 [TGSI_OPCODE_PK4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10398 [TGSI_OPCODE_PK4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10399 [44] = { ALU_OP0_NOP
, tgsi_unsupported
},
10400 [TGSI_OPCODE_SEQ
] = { ALU_OP2_SETE
, tgsi_op2
},
10401 [46] = { ALU_OP0_NOP
, tgsi_unsupported
},
10402 [TGSI_OPCODE_SGT
] = { ALU_OP2_SETGT
, tgsi_op2
},
10403 [TGSI_OPCODE_SIN
] = { ALU_OP1_SIN
, cayman_trig
},
10404 [TGSI_OPCODE_SLE
] = { ALU_OP2_SETGE
, tgsi_op2_swap
},
10405 [TGSI_OPCODE_SNE
] = { ALU_OP2_SETNE
, tgsi_op2
},
10406 [51] = { ALU_OP0_NOP
, tgsi_unsupported
},
10407 [TGSI_OPCODE_TEX
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10408 [TGSI_OPCODE_TXD
] = { FETCH_OP_SAMPLE_G
, tgsi_tex
},
10409 [TGSI_OPCODE_TXP
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10410 [TGSI_OPCODE_UP2H
] = { ALU_OP0_NOP
, tgsi_up2h
},
10411 [TGSI_OPCODE_UP2US
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10412 [TGSI_OPCODE_UP4B
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10413 [TGSI_OPCODE_UP4UB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10414 [59] = { ALU_OP0_NOP
, tgsi_unsupported
},
10415 [60] = { ALU_OP0_NOP
, tgsi_unsupported
},
10416 [TGSI_OPCODE_ARR
] = { ALU_OP0_NOP
, tgsi_eg_arl
},
10417 [62] = { ALU_OP0_NOP
, tgsi_unsupported
},
10418 [TGSI_OPCODE_CAL
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10419 [TGSI_OPCODE_RET
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10420 [TGSI_OPCODE_SSG
] = { ALU_OP0_NOP
, tgsi_ssg
},
10421 [TGSI_OPCODE_CMP
] = { ALU_OP0_NOP
, tgsi_cmp
},
10422 [67] = { ALU_OP0_NOP
, tgsi_unsupported
},
10423 [TGSI_OPCODE_TXB
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10424 [69] = { ALU_OP0_NOP
, tgsi_unsupported
},
10425 [TGSI_OPCODE_DIV
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10426 [TGSI_OPCODE_DP2
] = { ALU_OP2_DOT4_IEEE
, tgsi_dp
},
10427 [TGSI_OPCODE_TXL
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10428 [TGSI_OPCODE_BRK
] = { CF_OP_LOOP_BREAK
, tgsi_loop_brk_cont
},
10429 [TGSI_OPCODE_IF
] = { ALU_OP0_NOP
, tgsi_if
},
10430 [TGSI_OPCODE_UIF
] = { ALU_OP0_NOP
, tgsi_uif
},
10431 [76] = { ALU_OP0_NOP
, tgsi_unsupported
},
10432 [TGSI_OPCODE_ELSE
] = { ALU_OP0_NOP
, tgsi_else
},
10433 [TGSI_OPCODE_ENDIF
] = { ALU_OP0_NOP
, tgsi_endif
},
10434 [TGSI_OPCODE_DDX_FINE
] = { FETCH_OP_GET_GRADIENTS_H
, tgsi_tex
},
10435 [TGSI_OPCODE_DDY_FINE
] = { FETCH_OP_GET_GRADIENTS_V
, tgsi_tex
},
10436 [82] = { ALU_OP0_NOP
, tgsi_unsupported
},
10437 [TGSI_OPCODE_CEIL
] = { ALU_OP1_CEIL
, tgsi_op2
},
10438 [TGSI_OPCODE_I2F
] = { ALU_OP1_INT_TO_FLT
, tgsi_op2
},
10439 [TGSI_OPCODE_NOT
] = { ALU_OP1_NOT_INT
, tgsi_op2
},
10440 [TGSI_OPCODE_TRUNC
] = { ALU_OP1_TRUNC
, tgsi_op2
},
10441 [TGSI_OPCODE_SHL
] = { ALU_OP2_LSHL_INT
, tgsi_op2
},
10442 [88] = { ALU_OP0_NOP
, tgsi_unsupported
},
10443 [TGSI_OPCODE_AND
] = { ALU_OP2_AND_INT
, tgsi_op2
},
10444 [TGSI_OPCODE_OR
] = { ALU_OP2_OR_INT
, tgsi_op2
},
10445 [TGSI_OPCODE_MOD
] = { ALU_OP0_NOP
, tgsi_imod
},
10446 [TGSI_OPCODE_XOR
] = { ALU_OP2_XOR_INT
, tgsi_op2
},
10447 [93] = { ALU_OP0_NOP
, tgsi_unsupported
},
10448 [TGSI_OPCODE_TXF
] = { FETCH_OP_LD
, tgsi_tex
},
10449 [TGSI_OPCODE_TXQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10450 [TGSI_OPCODE_CONT
] = { CF_OP_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
10451 [TGSI_OPCODE_EMIT
] = { CF_OP_EMIT_VERTEX
, tgsi_gs_emit
},
10452 [TGSI_OPCODE_ENDPRIM
] = { CF_OP_CUT_VERTEX
, tgsi_gs_emit
},
10453 [TGSI_OPCODE_BGNLOOP
] = { ALU_OP0_NOP
, tgsi_bgnloop
},
10454 [TGSI_OPCODE_BGNSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10455 [TGSI_OPCODE_ENDLOOP
] = { ALU_OP0_NOP
, tgsi_endloop
},
10456 [TGSI_OPCODE_ENDSUB
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10457 [103] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_tex
},
10458 [TGSI_OPCODE_TXQS
] = { FETCH_OP_GET_NUMBER_OF_SAMPLES
, tgsi_tex
},
10459 [TGSI_OPCODE_RESQ
] = { FETCH_OP_GET_TEXTURE_RESINFO
, tgsi_resq
},
10460 [106] = { ALU_OP0_NOP
, tgsi_unsupported
},
10461 [TGSI_OPCODE_NOP
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10462 [TGSI_OPCODE_FSEQ
] = { ALU_OP2_SETE_DX10
, tgsi_op2
},
10463 [TGSI_OPCODE_FSGE
] = { ALU_OP2_SETGE_DX10
, tgsi_op2
},
10464 [TGSI_OPCODE_FSLT
] = { ALU_OP2_SETGT_DX10
, tgsi_op2_swap
},
10465 [TGSI_OPCODE_FSNE
] = { ALU_OP2_SETNE_DX10
, tgsi_op2_swap
},
10466 [TGSI_OPCODE_MEMBAR
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10467 [113] = { ALU_OP0_NOP
, tgsi_unsupported
},
10468 [114] = { ALU_OP0_NOP
, tgsi_unsupported
},
10469 [115] = { ALU_OP0_NOP
, tgsi_unsupported
},
10470 [TGSI_OPCODE_KILL_IF
] = { ALU_OP2_KILLGT
, tgsi_kill
}, /* conditional kill */
10471 [TGSI_OPCODE_END
] = { ALU_OP0_NOP
, tgsi_end
}, /* aka HALT */
10472 /* Refer below for TGSI_OPCODE_DFMA */
10473 [TGSI_OPCODE_F2I
] = { ALU_OP1_FLT_TO_INT
, tgsi_op2
},
10474 [TGSI_OPCODE_IDIV
] = { ALU_OP0_NOP
, tgsi_idiv
},
10475 [TGSI_OPCODE_IMAX
] = { ALU_OP2_MAX_INT
, tgsi_op2
},
10476 [TGSI_OPCODE_IMIN
] = { ALU_OP2_MIN_INT
, tgsi_op2
},
10477 [TGSI_OPCODE_INEG
] = { ALU_OP2_SUB_INT
, tgsi_ineg
},
10478 [TGSI_OPCODE_ISGE
] = { ALU_OP2_SETGE_INT
, tgsi_op2
},
10479 [TGSI_OPCODE_ISHR
] = { ALU_OP2_ASHR_INT
, tgsi_op2
},
10480 [TGSI_OPCODE_ISLT
] = { ALU_OP2_SETGT_INT
, tgsi_op2_swap
},
10481 [TGSI_OPCODE_F2U
] = { ALU_OP1_FLT_TO_UINT
, tgsi_op2
},
10482 [TGSI_OPCODE_U2F
] = { ALU_OP1_UINT_TO_FLT
, tgsi_op2
},
10483 [TGSI_OPCODE_UADD
] = { ALU_OP2_ADD_INT
, tgsi_op2
},
10484 [TGSI_OPCODE_UDIV
] = { ALU_OP0_NOP
, tgsi_udiv
},
10485 [TGSI_OPCODE_UMAD
] = { ALU_OP0_NOP
, tgsi_umad
},
10486 [TGSI_OPCODE_UMAX
] = { ALU_OP2_MAX_UINT
, tgsi_op2
},
10487 [TGSI_OPCODE_UMIN
] = { ALU_OP2_MIN_UINT
, tgsi_op2
},
10488 [TGSI_OPCODE_UMOD
] = { ALU_OP0_NOP
, tgsi_umod
},
10489 [TGSI_OPCODE_UMUL
] = { ALU_OP2_MULLO_INT
, cayman_mul_int_instr
},
10490 [TGSI_OPCODE_USEQ
] = { ALU_OP2_SETE_INT
, tgsi_op2
},
10491 [TGSI_OPCODE_USGE
] = { ALU_OP2_SETGE_UINT
, tgsi_op2
},
10492 [TGSI_OPCODE_USHR
] = { ALU_OP2_LSHR_INT
, tgsi_op2
},
10493 [TGSI_OPCODE_USLT
] = { ALU_OP2_SETGT_UINT
, tgsi_op2_swap
},
10494 [TGSI_OPCODE_USNE
] = { ALU_OP2_SETNE_INT
, tgsi_op2
},
10495 [TGSI_OPCODE_SWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10496 [TGSI_OPCODE_CASE
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10497 [TGSI_OPCODE_DEFAULT
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10498 [TGSI_OPCODE_ENDSWITCH
] = { ALU_OP0_NOP
, tgsi_unsupported
},
10499 [TGSI_OPCODE_SAMPLE
] = { 0, tgsi_unsupported
},
10500 [TGSI_OPCODE_SAMPLE_I
] = { 0, tgsi_unsupported
},
10501 [TGSI_OPCODE_SAMPLE_I_MS
] = { 0, tgsi_unsupported
},
10502 [TGSI_OPCODE_SAMPLE_B
] = { 0, tgsi_unsupported
},
10503 [TGSI_OPCODE_SAMPLE_C
] = { 0, tgsi_unsupported
},
10504 [TGSI_OPCODE_SAMPLE_C_LZ
] = { 0, tgsi_unsupported
},
10505 [TGSI_OPCODE_SAMPLE_D
] = { 0, tgsi_unsupported
},
10506 [TGSI_OPCODE_SAMPLE_L
] = { 0, tgsi_unsupported
},
10507 [TGSI_OPCODE_GATHER4
] = { 0, tgsi_unsupported
},
10508 [TGSI_OPCODE_SVIEWINFO
] = { 0, tgsi_unsupported
},
10509 [TGSI_OPCODE_SAMPLE_POS
] = { 0, tgsi_unsupported
},
10510 [TGSI_OPCODE_SAMPLE_INFO
] = { 0, tgsi_unsupported
},
10511 [TGSI_OPCODE_UARL
] = { ALU_OP1_MOVA_INT
, tgsi_eg_arl
},
10512 [TGSI_OPCODE_UCMP
] = { ALU_OP0_NOP
, tgsi_ucmp
},
10513 [TGSI_OPCODE_IABS
] = { 0, tgsi_iabs
},
10514 [TGSI_OPCODE_ISSG
] = { 0, tgsi_issg
},
10515 [TGSI_OPCODE_LOAD
] = { ALU_OP0_NOP
, tgsi_load
},
10516 [TGSI_OPCODE_STORE
] = { ALU_OP0_NOP
, tgsi_store
},
10517 [163] = { ALU_OP0_NOP
, tgsi_unsupported
},
10518 [164] = { ALU_OP0_NOP
, tgsi_unsupported
},
10519 [165] = { ALU_OP0_NOP
, tgsi_unsupported
},
10520 [TGSI_OPCODE_BARRIER
] = { ALU_OP0_GROUP_BARRIER
, tgsi_barrier
},
10521 [TGSI_OPCODE_ATOMUADD
] = { V_RAT_INST_ADD_RTN
, tgsi_atomic_op
},
10522 [TGSI_OPCODE_ATOMXCHG
] = { V_RAT_INST_XCHG_RTN
, tgsi_atomic_op
},
10523 [TGSI_OPCODE_ATOMCAS
] = { V_RAT_INST_CMPXCHG_INT_RTN
, tgsi_atomic_op
},
10524 [TGSI_OPCODE_ATOMAND
] = { V_RAT_INST_AND_RTN
, tgsi_atomic_op
},
10525 [TGSI_OPCODE_ATOMOR
] = { V_RAT_INST_OR_RTN
, tgsi_atomic_op
},
10526 [TGSI_OPCODE_ATOMXOR
] = { V_RAT_INST_XOR_RTN
, tgsi_atomic_op
},
10527 [TGSI_OPCODE_ATOMUMIN
] = { V_RAT_INST_MIN_UINT_RTN
, tgsi_atomic_op
},
10528 [TGSI_OPCODE_ATOMUMAX
] = { V_RAT_INST_MAX_UINT_RTN
, tgsi_atomic_op
},
10529 [TGSI_OPCODE_ATOMIMIN
] = { V_RAT_INST_MIN_INT_RTN
, tgsi_atomic_op
},
10530 [TGSI_OPCODE_ATOMIMAX
] = { V_RAT_INST_MAX_INT_RTN
, tgsi_atomic_op
},
10531 [TGSI_OPCODE_TEX2
] = { FETCH_OP_SAMPLE
, tgsi_tex
},
10532 [TGSI_OPCODE_TXB2
] = { FETCH_OP_SAMPLE_LB
, tgsi_tex
},
10533 [TGSI_OPCODE_TXL2
] = { FETCH_OP_SAMPLE_L
, tgsi_tex
},
10534 [TGSI_OPCODE_IMUL_HI
] = { ALU_OP2_MULHI_INT
, cayman_mul_int_instr
},
10535 [TGSI_OPCODE_UMUL_HI
] = { ALU_OP2_MULHI_UINT
, cayman_mul_int_instr
},
10536 [TGSI_OPCODE_TG4
] = { FETCH_OP_GATHER4
, tgsi_tex
},
10537 [TGSI_OPCODE_LODQ
] = { FETCH_OP_GET_LOD
, tgsi_tex
},
10538 [TGSI_OPCODE_IBFE
] = { ALU_OP3_BFE_INT
, tgsi_bfe
},
10539 [TGSI_OPCODE_UBFE
] = { ALU_OP3_BFE_UINT
, tgsi_bfe
},
10540 [TGSI_OPCODE_BFI
] = { ALU_OP0_NOP
, tgsi_bfi
},
10541 [TGSI_OPCODE_BREV
] = { ALU_OP1_BFREV_INT
, tgsi_op2
},
10542 [TGSI_OPCODE_POPC
] = { ALU_OP1_BCNT_INT
, tgsi_op2
},
10543 [TGSI_OPCODE_LSB
] = { ALU_OP1_FFBL_INT
, tgsi_op2
},
10544 [TGSI_OPCODE_IMSB
] = { ALU_OP1_FFBH_INT
, tgsi_msb
},
10545 [TGSI_OPCODE_UMSB
] = { ALU_OP1_FFBH_UINT
, tgsi_msb
},
10546 [TGSI_OPCODE_INTERP_CENTROID
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10547 [TGSI_OPCODE_INTERP_SAMPLE
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10548 [TGSI_OPCODE_INTERP_OFFSET
] = { ALU_OP0_NOP
, tgsi_interp_egcm
},
10549 [TGSI_OPCODE_F2D
] = { ALU_OP1_FLT32_TO_FLT64
, tgsi_op2_64
},
10550 [TGSI_OPCODE_D2F
] = { ALU_OP1_FLT64_TO_FLT32
, tgsi_op2_64_single_dest
},
10551 [TGSI_OPCODE_DABS
] = { ALU_OP1_MOV
, tgsi_op2_64
},
10552 [TGSI_OPCODE_DNEG
] = { ALU_OP2_ADD_64
, tgsi_dneg
},
10553 [TGSI_OPCODE_DADD
] = { ALU_OP2_ADD_64
, tgsi_op2_64
},
10554 [TGSI_OPCODE_DMUL
] = { ALU_OP2_MUL_64
, cayman_mul_double_instr
},
10555 [TGSI_OPCODE_DDIV
] = { 0, cayman_ddiv_instr
},
10556 [TGSI_OPCODE_DMAX
] = { ALU_OP2_MAX_64
, tgsi_op2_64
},
10557 [TGSI_OPCODE_DMIN
] = { ALU_OP2_MIN_64
, tgsi_op2_64
},
10558 [TGSI_OPCODE_DSLT
] = { ALU_OP2_SETGT_64
, tgsi_op2_64_single_dest_s
},
10559 [TGSI_OPCODE_DSGE
] = { ALU_OP2_SETGE_64
, tgsi_op2_64_single_dest
},
10560 [TGSI_OPCODE_DSEQ
] = { ALU_OP2_SETE_64
, tgsi_op2_64_single_dest
},
10561 [TGSI_OPCODE_DSNE
] = { ALU_OP2_SETNE_64
, tgsi_op2_64_single_dest
},
10562 [TGSI_OPCODE_DRCP
] = { ALU_OP2_RECIP_64
, cayman_emit_double_instr
},
10563 [TGSI_OPCODE_DSQRT
] = { ALU_OP2_SQRT_64
, cayman_emit_double_instr
},
10564 [TGSI_OPCODE_DMAD
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10565 [TGSI_OPCODE_DFMA
] = { ALU_OP3_FMA_64
, tgsi_op3_64
},
10566 [TGSI_OPCODE_DFRAC
] = { ALU_OP1_FRACT_64
, tgsi_op2_64
},
10567 [TGSI_OPCODE_DLDEXP
] = { ALU_OP2_LDEXP_64
, tgsi_op2_64
},
10568 [TGSI_OPCODE_DFRACEXP
] = { ALU_OP1_FREXP_64
, tgsi_dfracexp
},
10569 [TGSI_OPCODE_D2I
] = { ALU_OP1_FLT_TO_INT
, egcm_double_to_int
},
10570 [TGSI_OPCODE_I2D
] = { ALU_OP1_INT_TO_FLT
, egcm_int_to_double
},
10571 [TGSI_OPCODE_D2U
] = { ALU_OP1_FLT_TO_UINT
, egcm_double_to_int
},
10572 [TGSI_OPCODE_U2D
] = { ALU_OP1_UINT_TO_FLT
, egcm_int_to_double
},
10573 [TGSI_OPCODE_DRSQ
] = { ALU_OP2_RECIPSQRT_64
, cayman_emit_double_instr
},
10574 [TGSI_OPCODE_LAST
] = { ALU_OP0_NOP
, tgsi_unsupported
},