projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: enable SB backend by default
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static unsigned tgsi_get_processor_type(const struct tgsi_token *tokens)
88 {
89 struct tgsi_parse_context parse;
90
91 if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
92 debug_printf("tgsi_parse_init() failed in %s:%i!\n", __func__, __LINE__);
93 return ~0;
94 }
95 return parse.FullHeader.Processor.Processor;
96 }
97
98 static bool r600_can_dump_shader(struct r600_screen *rscreen, unsigned processor_type)
99 {
100 switch (processor_type) {
101 case TGSI_PROCESSOR_VERTEX:
102 return (rscreen->debug_flags & DBG_VS) != 0;
103 case TGSI_PROCESSOR_GEOMETRY:
104 return (rscreen->debug_flags & DBG_GS) != 0;
105 case TGSI_PROCESSOR_FRAGMENT:
106 return (rscreen->debug_flags & DBG_PS) != 0;
107 case TGSI_PROCESSOR_COMPUTE:
108 return (rscreen->debug_flags & DBG_CS) != 0;
109 default:
110 return false;
111 }
112 }
113
114 static void r600_dump_streamout(struct pipe_stream_output_info *so)
115 {
116 unsigned i;
117
118 fprintf(stderr, "STREAMOUT\n");
119 for (i = 0; i < so->num_outputs; i++) {
120 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
121 so->output[i].start_component;
122 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
123 i, so->output[i].output_buffer,
124 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
125 so->output[i].register_index,
126 mask & 1 ? "x" : "",
127 mask & 2 ? "y" : "",
128 mask & 4 ? "z" : "",
129 mask & 8 ? "w" : "",
130 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
131 }
132 }
133
134 int r600_pipe_shader_create(struct pipe_context *ctx,
135 struct r600_pipe_shader *shader,
136 struct r600_shader_key key)
137 {
138 struct r600_context *rctx = (struct r600_context *)ctx;
139 struct r600_pipe_shader_selector *sel = shader->selector;
140 int r, i;
141 uint32_t *ptr;
142 bool dump = r600_can_dump_shader(rctx->screen, tgsi_get_processor_type(sel->tokens));
143 unsigned use_sb = !(rctx->screen->debug_flags & DBG_NO_SB);
144 unsigned sb_disasm = use_sb || (rctx->screen->debug_flags & DBG_SB_DISASM);
145
146 shader->shader.bc.isa = rctx->isa;
147
148 if (dump) {
149 fprintf(stderr, "--------------------------------------------------------------\n");
150 tgsi_dump(sel->tokens, 0);
151
152 if (sel->so.num_outputs) {
153 r600_dump_streamout(&sel->so);
154 }
155 }
156 r = r600_shader_from_tgsi(rctx->screen, shader, key);
157 if (r) {
158 R600_ERR("translation from TGSI failed !\n");
159 return r;
160 }
161
162 /* Check if the bytecode has already been built. When using the llvm
163 * backend, r600_shader_from_tgsi() will take care of building the
164 * bytecode.
165 */
166 if (!shader->shader.bc.bytecode) {
167 r = r600_bytecode_build(&shader->shader.bc);
168 if (r) {
169 R600_ERR("building bytecode failed !\n");
170 return r;
171 }
172 }
173
174 if (dump && !sb_disasm) {
175 fprintf(stderr, "--------------------------------------------------------------\n");
176 r600_bytecode_disasm(&shader->shader.bc);
177 fprintf(stderr, "______________________________________________________________\n");
178 } else if ((dump && sb_disasm) || use_sb) {
179 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
180 dump, use_sb);
181 if (r) {
182 R600_ERR("r600_sb_bytecode_process failed !\n");
183 return r;
184 }
185 }
186
187 /* Store the shader in a buffer. */
188 if (shader->bo == NULL) {
189 shader->bo = (struct r600_resource*)
190 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
191 if (shader->bo == NULL) {
192 return -ENOMEM;
193 }
194 ptr = r600_buffer_mmap_sync_with_rings(rctx, shader->bo, PIPE_TRANSFER_WRITE);
195 if (R600_BIG_ENDIAN) {
196 for (i = 0; i < shader->shader.bc.ndw; ++i) {
197 ptr[i] = util_bswap32(shader->shader.bc.bytecode[i]);
198 }
199 } else {
200 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
201 }
202 rctx->ws->buffer_unmap(shader->bo->cs_buf);
203 }
204
205 /* Build state. */
206 switch (shader->shader.processor_type) {
207 case TGSI_PROCESSOR_VERTEX:
208 if (rctx->chip_class >= EVERGREEN) {
209 evergreen_update_vs_state(ctx, shader);
210 } else {
211 r600_update_vs_state(ctx, shader);
212 }
213 break;
214 case TGSI_PROCESSOR_FRAGMENT:
215 if (rctx->chip_class >= EVERGREEN) {
216 evergreen_update_ps_state(ctx, shader);
217 } else {
218 r600_update_ps_state(ctx, shader);
219 }
220 break;
221 default:
222 return -EINVAL;
223 }
224 return 0;
225 }
226
227 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
228 {
229 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
230 r600_bytecode_clear(&shader->shader.bc);
231 r600_release_command_buffer(&shader->command_buffer);
232 }
233
234 /*
235 * tgsi -> r600 shader
236 */
237 struct r600_shader_tgsi_instruction;
238
239 struct r600_shader_src {
240 unsigned sel;
241 unsigned swizzle[4];
242 unsigned neg;
243 unsigned abs;
244 unsigned rel;
245 unsigned kc_bank;
246 uint32_t value[4];
247 };
248
249 struct r600_shader_ctx {
250 struct tgsi_shader_info info;
251 struct tgsi_parse_context parse;
252 const struct tgsi_token *tokens;
253 unsigned type;
254 unsigned file_offset[TGSI_FILE_COUNT];
255 unsigned temp_reg;
256 struct r600_shader_tgsi_instruction *inst_info;
257 struct r600_bytecode *bc;
258 struct r600_shader *shader;
259 struct r600_shader_src src[4];
260 uint32_t *literals;
261 uint32_t nliterals;
262 uint32_t max_driver_temp_used;
263 boolean use_llvm;
264 /* needed for evergreen interpolation */
265 boolean input_centroid;
266 boolean input_linear;
267 boolean input_perspective;
268 int num_interp_gpr;
269 int face_gpr;
270 int colors_used;
271 boolean clip_vertex_write;
272 unsigned cv_output;
273 int fragcoord_input;
274 int native_integers;
275 };
276
277 struct r600_shader_tgsi_instruction {
278 unsigned tgsi_opcode;
279 unsigned is_op3;
280 unsigned op;
281 int (*process)(struct r600_shader_ctx *ctx);
282 };
283
284 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
285 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
286 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
287 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
288 static int tgsi_else(struct r600_shader_ctx *ctx);
289 static int tgsi_endif(struct r600_shader_ctx *ctx);
290 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
291 static int tgsi_endloop(struct r600_shader_ctx *ctx);
292 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
293
294 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
295 {
296 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
297 int j;
298
299 if (i->Instruction.NumDstRegs > 1) {
300 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
301 return -EINVAL;
302 }
303 if (i->Instruction.Predicate) {
304 R600_ERR("predicate unsupported\n");
305 return -EINVAL;
306 }
307 #if 0
308 if (i->Instruction.Label) {
309 R600_ERR("label unsupported\n");
310 return -EINVAL;
311 }
312 #endif
313 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
314 if (i->Src[j].Register.Dimension) {
315 if (i->Src[j].Register.File != TGSI_FILE_CONSTANT) {
316 R600_ERR("unsupported src %d (dimension %d)\n", j,
317 i->Src[j].Register.Dimension);
318 return -EINVAL;
319 }
320 }
321 }
322 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
323 if (i->Dst[j].Register.Dimension) {
324 R600_ERR("unsupported dst (dimension)\n");
325 return -EINVAL;
326 }
327 }
328 return 0;
329 }
330
331 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
332 int input)
333 {
334 int ij_index = 0;
335
336 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
337 if (ctx->shader->input[input].centroid)
338 ij_index++;
339 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
340 /* if we have perspective add one */
341 if (ctx->input_perspective) {
342 ij_index++;
343 /* if we have perspective centroid */
344 if (ctx->input_centroid)
345 ij_index++;
346 }
347 if (ctx->shader->input[input].centroid)
348 ij_index++;
349 }
350
351 ctx->shader->input[input].ij_index = ij_index;
352 }
353
354 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
355 {
356 int i, r;
357 struct r600_bytecode_alu alu;
358 int gpr = 0, base_chan = 0;
359 int ij_index = ctx->shader->input[input].ij_index;
360
361 /* work out gpr and base_chan from index */
362 gpr = ij_index / 2;
363 base_chan = (2 * (ij_index % 2)) + 1;
364
365 for (i = 0; i < 8; i++) {
366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
367
368 if (i < 4)
369 alu.op = ALU_OP2_INTERP_ZW;
370 else
371 alu.op = ALU_OP2_INTERP_XY;
372
373 if ((i > 1) && (i < 6)) {
374 alu.dst.sel = ctx->shader->input[input].gpr;
375 alu.dst.write = 1;
376 }
377
378 alu.dst.chan = i % 4;
379
380 alu.src[0].sel = gpr;
381 alu.src[0].chan = (base_chan - (i % 2));
382
383 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
384
385 alu.bank_swizzle_force = SQ_ALU_VEC_210;
386 if ((i % 4) == 3)
387 alu.last = 1;
388 r = r600_bytecode_add_alu(ctx->bc, &alu);
389 if (r)
390 return r;
391 }
392 return 0;
393 }
394
395 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
396 {
397 int i, r;
398 struct r600_bytecode_alu alu;
399
400 for (i = 0; i < 4; i++) {
401 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
402
403 alu.op = ALU_OP1_INTERP_LOAD_P0;
404
405 alu.dst.sel = ctx->shader->input[input].gpr;
406 alu.dst.write = 1;
407
408 alu.dst.chan = i;
409
410 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
411 alu.src[0].chan = i;
412
413 if (i == 3)
414 alu.last = 1;
415 r = r600_bytecode_add_alu(ctx->bc, &alu);
416 if (r)
417 return r;
418 }
419 return 0;
420 }
421
422 /*
423 * Special export handling in shaders
424 *
425 * shader export ARRAY_BASE for EXPORT_POS:
426 * 60 is position
427 * 61 is misc vector
428 * 62, 63 are clip distance vectors
429 *
430 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
431 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
432 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
433 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
434 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
435 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
436 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
437 * exclusive from render target index)
438 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
439 *
440 *
441 * shader export ARRAY_BASE for EXPORT_PIXEL:
442 * 0-7 CB targets
443 * 61 computed Z vector
444 *
445 * The use of the values exported in the computed Z vector are controlled
446 * by DB_SHADER_CONTROL:
447 * Z_EXPORT_ENABLE - Z as a float in RED
448 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
449 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
450 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
451 * DB_SOURCE_FORMAT - export control restrictions
452 *
453 */
454
455
456 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
457 static int r600_spi_sid(struct r600_shader_io * io)
458 {
459 int index, name = io->name;
460
461 /* These params are handled differently, they don't need
462 * semantic indices, so we'll use 0 for them.
463 */
464 if (name == TGSI_SEMANTIC_POSITION ||
465 name == TGSI_SEMANTIC_PSIZE ||
466 name == TGSI_SEMANTIC_FACE)
467 index = 0;
468 else {
469 if (name == TGSI_SEMANTIC_GENERIC) {
470 /* For generic params simply use sid from tgsi */
471 index = io->sid;
472 } else {
473 /* For non-generic params - pack name and sid into 8 bits */
474 index = 0x80 | (name<<3) | (io->sid);
475 }
476
477 /* Make sure that all really used indices have nonzero value, so
478 * we can just compare it to 0 later instead of comparing the name
479 * with different values to detect special cases. */
480 index++;
481 }
482
483 return index;
484 };
485
486 /* turn input into interpolate on EG */
487 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
488 {
489 int r = 0;
490
491 if (ctx->shader->input[index].spi_sid) {
492 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
493 if (ctx->shader->input[index].interpolate > 0) {
494 evergreen_interp_assign_ij_index(ctx, index);
495 if (!ctx->use_llvm)
496 r = evergreen_interp_alu(ctx, index);
497 } else {
498 if (!ctx->use_llvm)
499 r = evergreen_interp_flat(ctx, index);
500 }
501 }
502 return r;
503 }
504
505 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
506 {
507 struct r600_bytecode_alu alu;
508 int i, r;
509 int gpr_front = ctx->shader->input[front].gpr;
510 int gpr_back = ctx->shader->input[back].gpr;
511
512 for (i = 0; i < 4; i++) {
513 memset(&alu, 0, sizeof(alu));
514 alu.op = ALU_OP3_CNDGT;
515 alu.is_op3 = 1;
516 alu.dst.write = 1;
517 alu.dst.sel = gpr_front;
518 alu.src[0].sel = ctx->face_gpr;
519 alu.src[1].sel = gpr_front;
520 alu.src[2].sel = gpr_back;
521
522 alu.dst.chan = i;
523 alu.src[1].chan = i;
524 alu.src[2].chan = i;
525 alu.last = (i==3);
526
527 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
528 return r;
529 }
530
531 return 0;
532 }
533
534 static int tgsi_declaration(struct r600_shader_ctx *ctx)
535 {
536 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
537 int r, i, j, count = d->Range.Last - d->Range.First + 1;
538
539 switch (d->Declaration.File) {
540 case TGSI_FILE_INPUT:
541 i = ctx->shader->ninput;
542 assert(i < Elements(ctx->shader->input));
543 ctx->shader->ninput += count;
544 ctx->shader->input[i].name = d->Semantic.Name;
545 ctx->shader->input[i].sid = d->Semantic.Index;
546 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
547 ctx->shader->input[i].centroid = d->Interp.Centroid;
548 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
549 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
550 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
551 switch (ctx->shader->input[i].name) {
552 case TGSI_SEMANTIC_FACE:
553 ctx->face_gpr = ctx->shader->input[i].gpr;
554 break;
555 case TGSI_SEMANTIC_COLOR:
556 ctx->colors_used++;
557 break;
558 case TGSI_SEMANTIC_POSITION:
559 ctx->fragcoord_input = i;
560 break;
561 }
562 if (ctx->bc->chip_class >= EVERGREEN) {
563 if ((r = evergreen_interp_input(ctx, i)))
564 return r;
565 }
566 }
567 for (j = 1; j < count; ++j) {
568 ctx->shader->input[i + j] = ctx->shader->input[i];
569 ctx->shader->input[i + j].gpr += j;
570 }
571 break;
572 case TGSI_FILE_OUTPUT:
573 i = ctx->shader->noutput++;
574 assert(i < Elements(ctx->shader->output));
575 ctx->shader->output[i].name = d->Semantic.Name;
576 ctx->shader->output[i].sid = d->Semantic.Index;
577 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
578 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
579 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
580 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
581 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
582 switch (d->Semantic.Name) {
583 case TGSI_SEMANTIC_CLIPDIST:
584 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
585 break;
586 case TGSI_SEMANTIC_PSIZE:
587 ctx->shader->vs_out_misc_write = 1;
588 ctx->shader->vs_out_point_size = 1;
589 break;
590 case TGSI_SEMANTIC_CLIPVERTEX:
591 ctx->clip_vertex_write = TRUE;
592 ctx->cv_output = i;
593 break;
594 }
595 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
596 switch (d->Semantic.Name) {
597 case TGSI_SEMANTIC_COLOR:
598 ctx->shader->nr_ps_max_color_exports++;
599 break;
600 }
601 }
602 break;
603 case TGSI_FILE_TEMPORARY:
604 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
605 if (d->Array.ArrayID) {
606 r600_add_gpr_array(ctx->shader,
607 ctx->file_offset[TGSI_FILE_TEMPORARY] +
608 d->Range.First,
609 d->Range.Last - d->Range.First + 1, 0x0F);
610 }
611 }
612 break;
613
614 case TGSI_FILE_CONSTANT:
615 case TGSI_FILE_SAMPLER:
616 case TGSI_FILE_ADDRESS:
617 break;
618
619 case TGSI_FILE_SYSTEM_VALUE:
620 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
621 if (!ctx->native_integers) {
622 struct r600_bytecode_alu alu;
623 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
624
625 alu.op = ALU_OP1_INT_TO_FLT;
626 alu.src[0].sel = 0;
627 alu.src[0].chan = 3;
628
629 alu.dst.sel = 0;
630 alu.dst.chan = 3;
631 alu.dst.write = 1;
632 alu.last = 1;
633
634 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
635 return r;
636 }
637 break;
638 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
639 break;
640 default:
641 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
642 return -EINVAL;
643 }
644 return 0;
645 }
646
647 static int r600_get_temp(struct r600_shader_ctx *ctx)
648 {
649 return ctx->temp_reg + ctx->max_driver_temp_used++;
650 }
651
652 /*
653 * for evergreen we need to scan the shader to find the number of GPRs we need to
654 * reserve for interpolation.
655 *
656 * we need to know if we are going to emit
657 * any centroid inputs
658 * if perspective and linear are required
659 */
660 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
661 {
662 int i;
663 int num_baryc;
664
665 ctx->input_linear = FALSE;
666 ctx->input_perspective = FALSE;
667 ctx->input_centroid = FALSE;
668 ctx->num_interp_gpr = 1;
669
670 /* any centroid inputs */
671 for (i = 0; i < ctx->info.num_inputs; i++) {
672 /* skip position/face */
673 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
674 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
675 continue;
676 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
677 ctx->input_linear = TRUE;
678 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
679 ctx->input_perspective = TRUE;
680 if (ctx->info.input_centroid[i])
681 ctx->input_centroid = TRUE;
682 }
683
684 num_baryc = 0;
685 /* ignoring sample for now */
686 if (ctx->input_perspective)
687 num_baryc++;
688 if (ctx->input_linear)
689 num_baryc++;
690 if (ctx->input_centroid)
691 num_baryc *= 2;
692
693 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
694
695 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
696 return ctx->num_interp_gpr;
697 }
698
699 static void tgsi_src(struct r600_shader_ctx *ctx,
700 const struct tgsi_full_src_register *tgsi_src,
701 struct r600_shader_src *r600_src)
702 {
703 memset(r600_src, 0, sizeof(*r600_src));
704 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
705 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
706 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
707 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
708 r600_src->neg = tgsi_src->Register.Negate;
709 r600_src->abs = tgsi_src->Register.Absolute;
710
711 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
712 int index;
713 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
714 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
715 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
716
717 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
718 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
719 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
720 return;
721 }
722 index = tgsi_src->Register.Index;
723 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
724 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
725 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
726 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
727 r600_src->swizzle[0] = 3;
728 r600_src->swizzle[1] = 3;
729 r600_src->swizzle[2] = 3;
730 r600_src->swizzle[3] = 3;
731 r600_src->sel = 0;
732 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
733 r600_src->swizzle[0] = 0;
734 r600_src->swizzle[1] = 0;
735 r600_src->swizzle[2] = 0;
736 r600_src->swizzle[3] = 0;
737 r600_src->sel = 0;
738 }
739 } else {
740 if (tgsi_src->Register.Indirect)
741 r600_src->rel = V_SQ_REL_RELATIVE;
742 r600_src->sel = tgsi_src->Register.Index;
743 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
744 }
745 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
746 if (tgsi_src->Register.Dimension) {
747 r600_src->kc_bank = tgsi_src->Dimension.Index;
748 }
749 }
750 }
751
752 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int cb_idx, unsigned int offset, unsigned int dst_reg)
753 {
754 struct r600_bytecode_vtx vtx;
755 unsigned int ar_reg;
756 int r;
757
758 if (offset) {
759 struct r600_bytecode_alu alu;
760
761 memset(&alu, 0, sizeof(alu));
762
763 alu.op = ALU_OP2_ADD_INT;
764 alu.src[0].sel = ctx->bc->ar_reg;
765
766 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
767 alu.src[1].value = offset;
768
769 alu.dst.sel = dst_reg;
770 alu.dst.write = 1;
771 alu.last = 1;
772
773 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
774 return r;
775
776 ar_reg = dst_reg;
777 } else {
778 ar_reg = ctx->bc->ar_reg;
779 }
780
781 memset(&vtx, 0, sizeof(vtx));
782 vtx.buffer_id = cb_idx;
783 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
784 vtx.src_gpr = ar_reg;
785 vtx.mega_fetch_count = 16;
786 vtx.dst_gpr = dst_reg;
787 vtx.dst_sel_x = 0; /* SEL_X */
788 vtx.dst_sel_y = 1; /* SEL_Y */
789 vtx.dst_sel_z = 2; /* SEL_Z */
790 vtx.dst_sel_w = 3; /* SEL_W */
791 vtx.data_format = FMT_32_32_32_32_FLOAT;
792 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
793 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
794 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
795 vtx.endian = r600_endian_swap(32);
796
797 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
798 return r;
799
800 return 0;
801 }
802
803 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
804 {
805 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
806 struct r600_bytecode_alu alu;
807 int i, j, k, nconst, r;
808
809 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
810 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
811 nconst++;
812 }
813 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
814 }
815 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
816 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
817 continue;
818 }
819
820 if (ctx->src[i].rel) {
821 int treg = r600_get_temp(ctx);
822 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, treg)))
823 return r;
824
825 ctx->src[i].kc_bank = 0;
826 ctx->src[i].sel = treg;
827 ctx->src[i].rel = 0;
828 j--;
829 } else if (j > 0) {
830 int treg = r600_get_temp(ctx);
831 for (k = 0; k < 4; k++) {
832 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
833 alu.op = ALU_OP1_MOV;
834 alu.src[0].sel = ctx->src[i].sel;
835 alu.src[0].chan = k;
836 alu.src[0].rel = ctx->src[i].rel;
837 alu.dst.sel = treg;
838 alu.dst.chan = k;
839 alu.dst.write = 1;
840 if (k == 3)
841 alu.last = 1;
842 r = r600_bytecode_add_alu(ctx->bc, &alu);
843 if (r)
844 return r;
845 }
846 ctx->src[i].sel = treg;
847 ctx->src[i].rel =0;
848 j--;
849 }
850 }
851 return 0;
852 }
853
854 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
855 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
856 {
857 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
858 struct r600_bytecode_alu alu;
859 int i, j, k, nliteral, r;
860
861 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
862 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
863 nliteral++;
864 }
865 }
866 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
867 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
868 int treg = r600_get_temp(ctx);
869 for (k = 0; k < 4; k++) {
870 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
871 alu.op = ALU_OP1_MOV;
872 alu.src[0].sel = ctx->src[i].sel;
873 alu.src[0].chan = k;
874 alu.src[0].value = ctx->src[i].value[k];
875 alu.dst.sel = treg;
876 alu.dst.chan = k;
877 alu.dst.write = 1;
878 if (k == 3)
879 alu.last = 1;
880 r = r600_bytecode_add_alu(ctx->bc, &alu);
881 if (r)
882 return r;
883 }
884 ctx->src[i].sel = treg;
885 j--;
886 }
887 }
888 return 0;
889 }
890
891 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
892 {
893 int i, r, count = ctx->shader->ninput;
894
895 for (i = 0; i < count; i++) {
896 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
897 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
898 if (r)
899 return r;
900 }
901 }
902 return 0;
903 }
904
905
906 static int r600_shader_from_tgsi(struct r600_screen *rscreen,
907 struct r600_pipe_shader *pipeshader,
908 struct r600_shader_key key)
909 {
910 struct r600_shader *shader = &pipeshader->shader;
911 struct tgsi_token *tokens = pipeshader->selector->tokens;
912 struct pipe_stream_output_info so = pipeshader->selector->so;
913 struct tgsi_full_immediate *immediate;
914 struct tgsi_full_property *property;
915 struct r600_shader_ctx ctx;
916 struct r600_bytecode_output output[32];
917 unsigned output_done, noutput;
918 unsigned opcode;
919 int i, j, k, r = 0;
920 int next_pos_base = 60, next_param_base = 0;
921 int max_color_exports = MAX2(key.nr_cbufs, 1);
922 /* Declarations used by llvm code */
923 bool use_llvm = false;
924 bool indirect_gprs;
925
926 #ifdef R600_USE_LLVM
927 use_llvm = !(rscreen->debug_flags & DBG_NO_LLVM);
928 #endif
929 ctx.bc = &shader->bc;
930 ctx.shader = shader;
931 ctx.native_integers = true;
932
933 r600_bytecode_init(ctx.bc, rscreen->chip_class, rscreen->family,
934 rscreen->has_compressed_msaa_texturing);
935 ctx.tokens = tokens;
936 tgsi_scan_shader(tokens, &ctx.info);
937 shader->indirect_files = ctx.info.indirect_files;
938 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
939 tgsi_parse_init(&ctx.parse, tokens);
940 ctx.type = ctx.parse.FullHeader.Processor.Processor;
941 shader->processor_type = ctx.type;
942 ctx.bc->type = shader->processor_type;
943
944 ctx.face_gpr = -1;
945 ctx.fragcoord_input = -1;
946 ctx.colors_used = 0;
947 ctx.clip_vertex_write = 0;
948
949 shader->nr_ps_color_exports = 0;
950 shader->nr_ps_max_color_exports = 0;
951
952 shader->two_side = key.color_two_side;
953
954 /* register allocations */
955 /* Values [0,127] correspond to GPR[0..127].
956 * Values [128,159] correspond to constant buffer bank 0
957 * Values [160,191] correspond to constant buffer bank 1
958 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
959 * Values [256,287] correspond to constant buffer bank 2 (EG)
960 * Values [288,319] correspond to constant buffer bank 3 (EG)
961 * Other special values are shown in the list below.
962 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
963 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
964 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
965 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
966 * 248 SQ_ALU_SRC_0: special constant 0.0.
967 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
968 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
969 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
970 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
971 * 253 SQ_ALU_SRC_LITERAL: literal constant.
972 * 254 SQ_ALU_SRC_PV: previous vector result.
973 * 255 SQ_ALU_SRC_PS: previous scalar result.
974 */
975 for (i = 0; i < TGSI_FILE_COUNT; i++) {
976 ctx.file_offset[i] = 0;
977 }
978
979 #ifdef R600_USE_LLVM
980 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
981 fprintf(stderr, "Warning: R600 LLVM backend does not support "
982 "indirect adressing. Falling back to TGSI "
983 "backend.\n");
984 use_llvm = 0;
985 }
986 #endif
987 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
988 ctx.file_offset[TGSI_FILE_INPUT] = 1;
989 if (!use_llvm) {
990 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
991 }
992 }
993 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
994 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
995 }
996 ctx.use_llvm = use_llvm;
997
998 if (use_llvm) {
999 ctx.file_offset[TGSI_FILE_OUTPUT] =
1000 ctx.file_offset[TGSI_FILE_INPUT];
1001 } else {
1002 ctx.file_offset[TGSI_FILE_OUTPUT] =
1003 ctx.file_offset[TGSI_FILE_INPUT] +
1004 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1005 }
1006 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1007 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1008
1009 /* Outside the GPR range. This will be translated to one of the
1010 * kcache banks later. */
1011 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1012
1013 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1014 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1015 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1016 ctx.temp_reg = ctx.bc->ar_reg + 1;
1017
1018 if (indirect_gprs) {
1019 shader->max_arrays = 0;
1020 shader->num_arrays = 0;
1021
1022 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1023 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1024 ctx.file_offset[TGSI_FILE_OUTPUT] -
1025 ctx.file_offset[TGSI_FILE_INPUT],
1026 0x0F);
1027 }
1028 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1029 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1030 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1031 ctx.file_offset[TGSI_FILE_OUTPUT],
1032 0x0F);
1033 }
1034 }
1035
1036 ctx.nliterals = 0;
1037 ctx.literals = NULL;
1038 shader->fs_write_all = FALSE;
1039 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1040 tgsi_parse_token(&ctx.parse);
1041 switch (ctx.parse.FullToken.Token.Type) {
1042 case TGSI_TOKEN_TYPE_IMMEDIATE:
1043 immediate = &ctx.parse.FullToken.FullImmediate;
1044 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1045 if(ctx.literals == NULL) {
1046 r = -ENOMEM;
1047 goto out_err;
1048 }
1049 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1050 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1051 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1052 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1053 ctx.nliterals++;
1054 break;
1055 case TGSI_TOKEN_TYPE_DECLARATION:
1056 r = tgsi_declaration(&ctx);
1057 if (r)
1058 goto out_err;
1059 break;
1060 case TGSI_TOKEN_TYPE_INSTRUCTION:
1061 break;
1062 case TGSI_TOKEN_TYPE_PROPERTY:
1063 property = &ctx.parse.FullToken.FullProperty;
1064 switch (property->Property.PropertyName) {
1065 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1066 if (property->u[0].Data == 1)
1067 shader->fs_write_all = TRUE;
1068 break;
1069 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1070 /* we don't need this one */
1071 break;
1072 }
1073 break;
1074 default:
1075 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1076 r = -EINVAL;
1077 goto out_err;
1078 }
1079 }
1080
1081 /* Process two side if needed */
1082 if (shader->two_side && ctx.colors_used) {
1083 int i, count = ctx.shader->ninput;
1084 unsigned next_lds_loc = ctx.shader->nlds;
1085
1086 /* additional inputs will be allocated right after the existing inputs,
1087 * we won't need them after the color selection, so we don't need to
1088 * reserve these gprs for the rest of the shader code and to adjust
1089 * output offsets etc. */
1090 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1091 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1092
1093 if (ctx.face_gpr == -1) {
1094 i = ctx.shader->ninput++;
1095 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1096 ctx.shader->input[i].spi_sid = 0;
1097 ctx.shader->input[i].gpr = gpr++;
1098 ctx.face_gpr = ctx.shader->input[i].gpr;
1099 }
1100
1101 for (i = 0; i < count; i++) {
1102 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1103 int ni = ctx.shader->ninput++;
1104 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1105 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1106 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1107 ctx.shader->input[ni].gpr = gpr++;
1108 // TGSI to LLVM needs to know the lds position of inputs.
1109 // Non LLVM path computes it later (in process_twoside_color)
1110 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1111 ctx.shader->input[i].back_color_input = ni;
1112 if (ctx.bc->chip_class >= EVERGREEN) {
1113 if ((r = evergreen_interp_input(&ctx, ni)))
1114 return r;
1115 }
1116 }
1117 }
1118 }
1119
1120 /* LLVM backend setup */
1121 #ifdef R600_USE_LLVM
1122 if (use_llvm) {
1123 struct radeon_llvm_context radeon_llvm_ctx;
1124 LLVMModuleRef mod;
1125 bool dump = r600_can_dump_shader(rscreen, ctx.type);
1126 boolean use_kill = false;
1127
1128 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1129 radeon_llvm_ctx.type = ctx.type;
1130 radeon_llvm_ctx.two_side = shader->two_side;
1131 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1132 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1133 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1134 radeon_llvm_ctx.color_buffer_count = max_color_exports;
1135 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1136 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
1137 radeon_llvm_ctx.stream_outputs = &so;
1138 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1139 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1140 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1141 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1142
1143 if (r600_llvm_compile(mod, rscreen->family, ctx.bc, &use_kill, dump)) {
1144 radeon_llvm_dispose(&radeon_llvm_ctx);
1145 use_llvm = 0;
1146 fprintf(stderr, "R600 LLVM backend failed to compile "
1147 "shader. Falling back to TGSI\n");
1148 } else {
1149 ctx.file_offset[TGSI_FILE_OUTPUT] =
1150 ctx.file_offset[TGSI_FILE_INPUT];
1151 }
1152 if (use_kill)
1153 ctx.shader->uses_kill = use_kill;
1154 radeon_llvm_dispose(&radeon_llvm_ctx);
1155 }
1156 #endif
1157 /* End of LLVM backend setup */
1158
1159 if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
1160 shader->nr_ps_max_color_exports = 8;
1161
1162 if (!use_llvm) {
1163 if (ctx.fragcoord_input >= 0) {
1164 if (ctx.bc->chip_class == CAYMAN) {
1165 for (j = 0 ; j < 4; j++) {
1166 struct r600_bytecode_alu alu;
1167 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1168 alu.op = ALU_OP1_RECIP_IEEE;
1169 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1170 alu.src[0].chan = 3;
1171
1172 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1173 alu.dst.chan = j;
1174 alu.dst.write = (j == 3);
1175 alu.last = 1;
1176 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1177 return r;
1178 }
1179 } else {
1180 struct r600_bytecode_alu alu;
1181 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1182 alu.op = ALU_OP1_RECIP_IEEE;
1183 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1184 alu.src[0].chan = 3;
1185
1186 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1187 alu.dst.chan = 3;
1188 alu.dst.write = 1;
1189 alu.last = 1;
1190 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1191 return r;
1192 }
1193 }
1194
1195 if (shader->two_side && ctx.colors_used) {
1196 if ((r = process_twoside_color_inputs(&ctx)))
1197 return r;
1198 }
1199
1200 tgsi_parse_init(&ctx.parse, tokens);
1201 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1202 tgsi_parse_token(&ctx.parse);
1203 switch (ctx.parse.FullToken.Token.Type) {
1204 case TGSI_TOKEN_TYPE_INSTRUCTION:
1205 r = tgsi_is_supported(&ctx);
1206 if (r)
1207 goto out_err;
1208 ctx.max_driver_temp_used = 0;
1209 /* reserve first tmp for everyone */
1210 r600_get_temp(&ctx);
1211
1212 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1213 if ((r = tgsi_split_constant(&ctx)))
1214 goto out_err;
1215 if ((r = tgsi_split_literal_constant(&ctx)))
1216 goto out_err;
1217 if (ctx.bc->chip_class == CAYMAN)
1218 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1219 else if (ctx.bc->chip_class >= EVERGREEN)
1220 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1221 else
1222 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1223 r = ctx.inst_info->process(&ctx);
1224 if (r)
1225 goto out_err;
1226 break;
1227 default:
1228 break;
1229 }
1230 }
1231 }
1232
1233 /* Reset the temporary register counter. */
1234 ctx.max_driver_temp_used = 0;
1235
1236 noutput = shader->noutput;
1237
1238 if (ctx.clip_vertex_write) {
1239 unsigned clipdist_temp[2];
1240
1241 clipdist_temp[0] = r600_get_temp(&ctx);
1242 clipdist_temp[1] = r600_get_temp(&ctx);
1243
1244 /* need to convert a clipvertex write into clipdistance writes and not export
1245 the clip vertex anymore */
1246
1247 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1248 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1249 shader->output[noutput].gpr = clipdist_temp[0];
1250 noutput++;
1251 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1252 shader->output[noutput].gpr = clipdist_temp[1];
1253 noutput++;
1254
1255 /* reset spi_sid for clipvertex output to avoid confusing spi */
1256 shader->output[ctx.cv_output].spi_sid = 0;
1257
1258 shader->clip_dist_write = 0xFF;
1259
1260 for (i = 0; i < 8; i++) {
1261 int oreg = i >> 2;
1262 int ochan = i & 3;
1263
1264 for (j = 0; j < 4; j++) {
1265 struct r600_bytecode_alu alu;
1266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1267 alu.op = ALU_OP2_DOT4;
1268 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1269 alu.src[0].chan = j;
1270
1271 alu.src[1].sel = 512 + i;
1272 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1273 alu.src[1].chan = j;
1274
1275 alu.dst.sel = clipdist_temp[oreg];
1276 alu.dst.chan = j;
1277 alu.dst.write = (j == ochan);
1278 if (j == 3)
1279 alu.last = 1;
1280 if (!use_llvm)
1281 r = r600_bytecode_add_alu(ctx.bc, &alu);
1282 if (r)
1283 return r;
1284 }
1285 }
1286 }
1287
1288 /* Add stream outputs. */
1289 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
1290 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1291
1292 /* Sanity checking. */
1293 if (so.num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1294 R600_ERR("Too many stream outputs: %d\n", so.num_outputs);
1295 r = -EINVAL;
1296 goto out_err;
1297 }
1298 for (i = 0; i < so.num_outputs; i++) {
1299 if (so.output[i].output_buffer >= 4) {
1300 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1301 so.output[i].output_buffer);
1302 r = -EINVAL;
1303 goto out_err;
1304 }
1305 }
1306
1307 /* Initialize locations where the outputs are stored. */
1308 for (i = 0; i < so.num_outputs; i++) {
1309 so_gpr[i] = shader->output[so.output[i].register_index].gpr;
1310
1311 /* Lower outputs with dst_offset < start_component.
1312 *
1313 * We can only output 4D vectors with a write mask, e.g. we can
1314 * only output the W component at offset 3, etc. If we want
1315 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1316 * to move it to X and output X. */
1317 if (so.output[i].dst_offset < so.output[i].start_component) {
1318 unsigned tmp = r600_get_temp(&ctx);
1319
1320 for (j = 0; j < so.output[i].num_components; j++) {
1321 struct r600_bytecode_alu alu;
1322 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1323 alu.op = ALU_OP1_MOV;
1324 alu.src[0].sel = so_gpr[i];
1325 alu.src[0].chan = so.output[i].start_component + j;
1326
1327 alu.dst.sel = tmp;
1328 alu.dst.chan = j;
1329 alu.dst.write = 1;
1330 if (j == so.output[i].num_components - 1)
1331 alu.last = 1;
1332 r = r600_bytecode_add_alu(ctx.bc, &alu);
1333 if (r)
1334 return r;
1335 }
1336 so.output[i].start_component = 0;
1337 so_gpr[i] = tmp;
1338 }
1339 }
1340
1341 /* Write outputs to buffers. */
1342 for (i = 0; i < so.num_outputs; i++) {
1343 struct r600_bytecode_output output;
1344
1345 memset(&output, 0, sizeof(struct r600_bytecode_output));
1346 output.gpr = so_gpr[i];
1347 output.elem_size = so.output[i].num_components;
1348 output.array_base = so.output[i].dst_offset - so.output[i].start_component;
1349 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1350 output.burst_count = 1;
1351 output.barrier = 1;
1352 /* array_size is an upper limit for the burst_count
1353 * with MEM_STREAM instructions */
1354 output.array_size = 0xFFF;
1355 output.comp_mask = ((1 << so.output[i].num_components) - 1) << so.output[i].start_component;
1356 if (ctx.bc->chip_class >= EVERGREEN) {
1357 switch (so.output[i].output_buffer) {
1358 case 0:
1359 output.op = CF_OP_MEM_STREAM0_BUF0;
1360 break;
1361 case 1:
1362 output.op = CF_OP_MEM_STREAM0_BUF1;
1363 break;
1364 case 2:
1365 output.op = CF_OP_MEM_STREAM0_BUF2;
1366 break;
1367 case 3:
1368 output.op = CF_OP_MEM_STREAM0_BUF3;
1369 break;
1370 }
1371 } else {
1372 switch (so.output[i].output_buffer) {
1373 case 0:
1374 output.op = CF_OP_MEM_STREAM0;
1375 break;
1376 case 1:
1377 output.op = CF_OP_MEM_STREAM1;
1378 break;
1379 case 2:
1380 output.op = CF_OP_MEM_STREAM2;
1381 break;
1382 case 3:
1383 output.op = CF_OP_MEM_STREAM3;
1384 break;
1385 }
1386 }
1387 r = r600_bytecode_add_output(ctx.bc, &output);
1388 if (r)
1389 goto out_err;
1390 }
1391 }
1392
1393 /* export output */
1394 for (i = 0, j = 0; i < noutput; i++, j++) {
1395 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1396 output[j].gpr = shader->output[i].gpr;
1397 output[j].elem_size = 3;
1398 output[j].swizzle_x = 0;
1399 output[j].swizzle_y = 1;
1400 output[j].swizzle_z = 2;
1401 output[j].swizzle_w = 3;
1402 output[j].burst_count = 1;
1403 output[j].barrier = 1;
1404 output[j].type = -1;
1405 output[j].op = CF_OP_EXPORT;
1406 switch (ctx.type) {
1407 case TGSI_PROCESSOR_VERTEX:
1408 switch (shader->output[i].name) {
1409 case TGSI_SEMANTIC_POSITION:
1410 output[j].array_base = next_pos_base++;
1411 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1412 break;
1413
1414 case TGSI_SEMANTIC_PSIZE:
1415 output[j].array_base = next_pos_base++;
1416 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1417 break;
1418 case TGSI_SEMANTIC_CLIPVERTEX:
1419 j--;
1420 break;
1421 case TGSI_SEMANTIC_CLIPDIST:
1422 output[j].array_base = next_pos_base++;
1423 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1424 /* spi_sid is 0 for clipdistance outputs that were generated
1425 * for clipvertex - we don't need to pass them to PS */
1426 if (shader->output[i].spi_sid) {
1427 j++;
1428 /* duplicate it as PARAM to pass to the pixel shader */
1429 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
1430 output[j].array_base = next_param_base++;
1431 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1432 }
1433 break;
1434 case TGSI_SEMANTIC_FOG:
1435 output[j].swizzle_y = 4; /* 0 */
1436 output[j].swizzle_z = 4; /* 0 */
1437 output[j].swizzle_w = 5; /* 1 */
1438 break;
1439 }
1440 break;
1441 case TGSI_PROCESSOR_FRAGMENT:
1442 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1443 /* never export more colors than the number of CBs */
1444 if (shader->output[i].sid >= max_color_exports) {
1445 /* skip export */
1446 j--;
1447 continue;
1448 }
1449 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1450 output[j].array_base = shader->output[i].sid;
1451 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1452 shader->nr_ps_color_exports++;
1453 if (shader->fs_write_all && (rscreen->chip_class >= EVERGREEN)) {
1454 for (k = 1; k < max_color_exports; k++) {
1455 j++;
1456 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1457 output[j].gpr = shader->output[i].gpr;
1458 output[j].elem_size = 3;
1459 output[j].swizzle_x = 0;
1460 output[j].swizzle_y = 1;
1461 output[j].swizzle_z = 2;
1462 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
1463 output[j].burst_count = 1;
1464 output[j].barrier = 1;
1465 output[j].array_base = k;
1466 output[j].op = CF_OP_EXPORT;
1467 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1468 shader->nr_ps_color_exports++;
1469 }
1470 }
1471 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1472 output[j].array_base = 61;
1473 output[j].swizzle_x = 2;
1474 output[j].swizzle_y = 7;
1475 output[j].swizzle_z = output[j].swizzle_w = 7;
1476 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1477 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1478 output[j].array_base = 61;
1479 output[j].swizzle_x = 7;
1480 output[j].swizzle_y = 1;
1481 output[j].swizzle_z = output[j].swizzle_w = 7;
1482 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1483 } else {
1484 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1485 r = -EINVAL;
1486 goto out_err;
1487 }
1488 break;
1489 default:
1490 R600_ERR("unsupported processor type %d\n", ctx.type);
1491 r = -EINVAL;
1492 goto out_err;
1493 }
1494
1495 if (output[j].type==-1) {
1496 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1497 output[j].array_base = next_param_base++;
1498 }
1499 }
1500
1501 /* add fake position export */
1502 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_pos_base == 60) {
1503 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1504 output[j].gpr = 0;
1505 output[j].elem_size = 3;
1506 output[j].swizzle_x = 7;
1507 output[j].swizzle_y = 7;
1508 output[j].swizzle_z = 7;
1509 output[j].swizzle_w = 7;
1510 output[j].burst_count = 1;
1511 output[j].barrier = 1;
1512 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1513 output[j].array_base = next_pos_base;
1514 output[j].op = CF_OP_EXPORT;
1515 j++;
1516 }
1517
1518 /* add fake param output for vertex shader if no param is exported */
1519 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
1520 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1521 output[j].gpr = 0;
1522 output[j].elem_size = 3;
1523 output[j].swizzle_x = 7;
1524 output[j].swizzle_y = 7;
1525 output[j].swizzle_z = 7;
1526 output[j].swizzle_w = 7;
1527 output[j].burst_count = 1;
1528 output[j].barrier = 1;
1529 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1530 output[j].array_base = 0;
1531 output[j].op = CF_OP_EXPORT;
1532 j++;
1533 }
1534
1535 /* add fake pixel export */
1536 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
1537 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1538 output[j].gpr = 0;
1539 output[j].elem_size = 3;
1540 output[j].swizzle_x = 7;
1541 output[j].swizzle_y = 7;
1542 output[j].swizzle_z = 7;
1543 output[j].swizzle_w = 7;
1544 output[j].burst_count = 1;
1545 output[j].barrier = 1;
1546 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1547 output[j].array_base = 0;
1548 output[j].op = CF_OP_EXPORT;
1549 j++;
1550 }
1551
1552 noutput = j;
1553
1554 /* set export done on last export of each type */
1555 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1556 if (ctx.bc->chip_class < CAYMAN) {
1557 if (i == (noutput - 1)) {
1558 output[i].end_of_program = 1;
1559 }
1560 }
1561 if (!(output_done & (1 << output[i].type))) {
1562 output_done |= (1 << output[i].type);
1563 output[i].op = CF_OP_EXPORT_DONE;
1564 }
1565 }
1566 /* add output to bytecode */
1567 if (!use_llvm) {
1568 for (i = 0; i < noutput; i++) {
1569 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1570 if (r)
1571 goto out_err;
1572 }
1573 }
1574 /* add program end */
1575 if (!use_llvm && ctx.bc->chip_class == CAYMAN)
1576 cm_bytecode_add_cf_end(ctx.bc);
1577
1578 /* check GPR limit - we have 124 = 128 - 4
1579 * (4 are reserved as alu clause temporary registers) */
1580 if (ctx.bc->ngpr > 124) {
1581 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
1582 r = -ENOMEM;
1583 goto out_err;
1584 }
1585
1586 free(ctx.literals);
1587 tgsi_parse_free(&ctx.parse);
1588 return 0;
1589 out_err:
1590 free(ctx.literals);
1591 tgsi_parse_free(&ctx.parse);
1592 return r;
1593 }
1594
1595 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1596 {
1597 R600_ERR("%s tgsi opcode unsupported\n",
1598 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1599 return -EINVAL;
1600 }
1601
1602 static int tgsi_end(struct r600_shader_ctx *ctx)
1603 {
1604 return 0;
1605 }
1606
1607 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1608 const struct r600_shader_src *shader_src,
1609 unsigned chan)
1610 {
1611 bc_src->sel = shader_src->sel;
1612 bc_src->chan = shader_src->swizzle[chan];
1613 bc_src->neg = shader_src->neg;
1614 bc_src->abs = shader_src->abs;
1615 bc_src->rel = shader_src->rel;
1616 bc_src->value = shader_src->value[bc_src->chan];
1617 bc_src->kc_bank = shader_src->kc_bank;
1618 }
1619
1620 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1621 {
1622 bc_src->abs = 1;
1623 bc_src->neg = 0;
1624 }
1625
1626 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1627 {
1628 bc_src->neg = !bc_src->neg;
1629 }
1630
1631 static void tgsi_dst(struct r600_shader_ctx *ctx,
1632 const struct tgsi_full_dst_register *tgsi_dst,
1633 unsigned swizzle,
1634 struct r600_bytecode_alu_dst *r600_dst)
1635 {
1636 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1637
1638 r600_dst->sel = tgsi_dst->Register.Index;
1639 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1640 r600_dst->chan = swizzle;
1641 r600_dst->write = 1;
1642 if (tgsi_dst->Register.Indirect)
1643 r600_dst->rel = V_SQ_REL_RELATIVE;
1644 if (inst->Instruction.Saturate) {
1645 r600_dst->clamp = 1;
1646 }
1647 }
1648
1649 static int tgsi_last_instruction(unsigned writemask)
1650 {
1651 int i, lasti = 0;
1652
1653 for (i = 0; i < 4; i++) {
1654 if (writemask & (1 << i)) {
1655 lasti = i;
1656 }
1657 }
1658 return lasti;
1659 }
1660
1661 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1662 {
1663 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1664 struct r600_bytecode_alu alu;
1665 int i, j, r;
1666 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1667
1668 for (i = 0; i < lasti + 1; i++) {
1669 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1670 continue;
1671
1672 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1673 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1674
1675 alu.op = ctx->inst_info->op;
1676 if (!swap) {
1677 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1678 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1679 }
1680 } else {
1681 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1682 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1683 }
1684 /* handle some special cases */
1685 switch (ctx->inst_info->tgsi_opcode) {
1686 case TGSI_OPCODE_SUB:
1687 r600_bytecode_src_toggle_neg(&alu.src[1]);
1688 break;
1689 case TGSI_OPCODE_ABS:
1690 r600_bytecode_src_set_abs(&alu.src[0]);
1691 break;
1692 default:
1693 break;
1694 }
1695 if (i == lasti || trans_only) {
1696 alu.last = 1;
1697 }
1698 r = r600_bytecode_add_alu(ctx->bc, &alu);
1699 if (r)
1700 return r;
1701 }
1702 return 0;
1703 }
1704
1705 static int tgsi_op2(struct r600_shader_ctx *ctx)
1706 {
1707 return tgsi_op2_s(ctx, 0, 0);
1708 }
1709
1710 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1711 {
1712 return tgsi_op2_s(ctx, 1, 0);
1713 }
1714
1715 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1716 {
1717 return tgsi_op2_s(ctx, 0, 1);
1718 }
1719
1720 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1721 {
1722 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1723 struct r600_bytecode_alu alu;
1724 int i, r;
1725 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1726
1727 for (i = 0; i < lasti + 1; i++) {
1728
1729 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1730 continue;
1731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1732 alu.op = ctx->inst_info->op;
1733
1734 alu.src[0].sel = V_SQ_ALU_SRC_0;
1735
1736 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1737
1738 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1739
1740 if (i == lasti) {
1741 alu.last = 1;
1742 }
1743 r = r600_bytecode_add_alu(ctx->bc, &alu);
1744 if (r)
1745 return r;
1746 }
1747 return 0;
1748
1749 }
1750
1751 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1752 {
1753 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1754 int i, j, r;
1755 struct r600_bytecode_alu alu;
1756 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1757
1758 for (i = 0 ; i < last_slot; i++) {
1759 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1760 alu.op = ctx->inst_info->op;
1761 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1762 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1763
1764 /* RSQ should take the absolute value of src */
1765 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
1766 r600_bytecode_src_set_abs(&alu.src[j]);
1767 }
1768 }
1769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1770 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1771
1772 if (i == last_slot - 1)
1773 alu.last = 1;
1774 r = r600_bytecode_add_alu(ctx->bc, &alu);
1775 if (r)
1776 return r;
1777 }
1778 return 0;
1779 }
1780
1781 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
1782 {
1783 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1784 int i, j, k, r;
1785 struct r600_bytecode_alu alu;
1786 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1787 for (k = 0; k < last_slot; k++) {
1788 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
1789 continue;
1790
1791 for (i = 0 ; i < 4; i++) {
1792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1793 alu.op = ctx->inst_info->op;
1794 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1795 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
1796 }
1797 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1798 alu.dst.write = (i == k);
1799 if (i == 3)
1800 alu.last = 1;
1801 r = r600_bytecode_add_alu(ctx->bc, &alu);
1802 if (r)
1803 return r;
1804 }
1805 }
1806 return 0;
1807 }
1808
1809 /*
1810 * r600 - trunc to -PI..PI range
1811 * r700 - normalize by dividing by 2PI
1812 * see fdo bug 27901
1813 */
1814 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1815 {
1816 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1817 static float double_pi = 3.1415926535 * 2;
1818 static float neg_pi = -3.1415926535;
1819
1820 int r;
1821 struct r600_bytecode_alu alu;
1822
1823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1824 alu.op = ALU_OP3_MULADD;
1825 alu.is_op3 = 1;
1826
1827 alu.dst.chan = 0;
1828 alu.dst.sel = ctx->temp_reg;
1829 alu.dst.write = 1;
1830
1831 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1832
1833 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1834 alu.src[1].chan = 0;
1835 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1836 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1837 alu.src[2].chan = 0;
1838 alu.last = 1;
1839 r = r600_bytecode_add_alu(ctx->bc, &alu);
1840 if (r)
1841 return r;
1842
1843 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1844 alu.op = ALU_OP1_FRACT;
1845
1846 alu.dst.chan = 0;
1847 alu.dst.sel = ctx->temp_reg;
1848 alu.dst.write = 1;
1849
1850 alu.src[0].sel = ctx->temp_reg;
1851 alu.src[0].chan = 0;
1852 alu.last = 1;
1853 r = r600_bytecode_add_alu(ctx->bc, &alu);
1854 if (r)
1855 return r;
1856
1857 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1858 alu.op = ALU_OP3_MULADD;
1859 alu.is_op3 = 1;
1860
1861 alu.dst.chan = 0;
1862 alu.dst.sel = ctx->temp_reg;
1863 alu.dst.write = 1;
1864
1865 alu.src[0].sel = ctx->temp_reg;
1866 alu.src[0].chan = 0;
1867
1868 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1869 alu.src[1].chan = 0;
1870 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1871 alu.src[2].chan = 0;
1872
1873 if (ctx->bc->chip_class == R600) {
1874 alu.src[1].value = *(uint32_t *)&double_pi;
1875 alu.src[2].value = *(uint32_t *)&neg_pi;
1876 } else {
1877 alu.src[1].sel = V_SQ_ALU_SRC_1;
1878 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1879 alu.src[2].neg = 1;
1880 }
1881
1882 alu.last = 1;
1883 r = r600_bytecode_add_alu(ctx->bc, &alu);
1884 if (r)
1885 return r;
1886 return 0;
1887 }
1888
1889 static int cayman_trig(struct r600_shader_ctx *ctx)
1890 {
1891 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1892 struct r600_bytecode_alu alu;
1893 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1894 int i, r;
1895
1896 r = tgsi_setup_trig(ctx);
1897 if (r)
1898 return r;
1899
1900
1901 for (i = 0; i < last_slot; i++) {
1902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1903 alu.op = ctx->inst_info->op;
1904 alu.dst.chan = i;
1905
1906 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1907 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1908
1909 alu.src[0].sel = ctx->temp_reg;
1910 alu.src[0].chan = 0;
1911 if (i == last_slot - 1)
1912 alu.last = 1;
1913 r = r600_bytecode_add_alu(ctx->bc, &alu);
1914 if (r)
1915 return r;
1916 }
1917 return 0;
1918 }
1919
1920 static int tgsi_trig(struct r600_shader_ctx *ctx)
1921 {
1922 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1923 struct r600_bytecode_alu alu;
1924 int i, r;
1925 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1926
1927 r = tgsi_setup_trig(ctx);
1928 if (r)
1929 return r;
1930
1931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1932 alu.op = ctx->inst_info->op;
1933 alu.dst.chan = 0;
1934 alu.dst.sel = ctx->temp_reg;
1935 alu.dst.write = 1;
1936
1937 alu.src[0].sel = ctx->temp_reg;
1938 alu.src[0].chan = 0;
1939 alu.last = 1;
1940 r = r600_bytecode_add_alu(ctx->bc, &alu);
1941 if (r)
1942 return r;
1943
1944 /* replicate result */
1945 for (i = 0; i < lasti + 1; i++) {
1946 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1947 continue;
1948
1949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1950 alu.op = ALU_OP1_MOV;
1951
1952 alu.src[0].sel = ctx->temp_reg;
1953 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1954 if (i == lasti)
1955 alu.last = 1;
1956 r = r600_bytecode_add_alu(ctx->bc, &alu);
1957 if (r)
1958 return r;
1959 }
1960 return 0;
1961 }
1962
1963 static int tgsi_scs(struct r600_shader_ctx *ctx)
1964 {
1965 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1966 struct r600_bytecode_alu alu;
1967 int i, r;
1968
1969 /* We'll only need the trig stuff if we are going to write to the
1970 * X or Y components of the destination vector.
1971 */
1972 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1973 r = tgsi_setup_trig(ctx);
1974 if (r)
1975 return r;
1976 }
1977
1978 /* dst.x = COS */
1979 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1980 if (ctx->bc->chip_class == CAYMAN) {
1981 for (i = 0 ; i < 3; i++) {
1982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1983 alu.op = ALU_OP1_COS;
1984 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1985
1986 if (i == 0)
1987 alu.dst.write = 1;
1988 else
1989 alu.dst.write = 0;
1990 alu.src[0].sel = ctx->temp_reg;
1991 alu.src[0].chan = 0;
1992 if (i == 2)
1993 alu.last = 1;
1994 r = r600_bytecode_add_alu(ctx->bc, &alu);
1995 if (r)
1996 return r;
1997 }
1998 } else {
1999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2000 alu.op = ALU_OP1_COS;
2001 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2002
2003 alu.src[0].sel = ctx->temp_reg;
2004 alu.src[0].chan = 0;
2005 alu.last = 1;
2006 r = r600_bytecode_add_alu(ctx->bc, &alu);
2007 if (r)
2008 return r;
2009 }
2010 }
2011
2012 /* dst.y = SIN */
2013 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2014 if (ctx->bc->chip_class == CAYMAN) {
2015 for (i = 0 ; i < 3; i++) {
2016 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2017 alu.op = ALU_OP1_SIN;
2018 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2019 if (i == 1)
2020 alu.dst.write = 1;
2021 else
2022 alu.dst.write = 0;
2023 alu.src[0].sel = ctx->temp_reg;
2024 alu.src[0].chan = 0;
2025 if (i == 2)
2026 alu.last = 1;
2027 r = r600_bytecode_add_alu(ctx->bc, &alu);
2028 if (r)
2029 return r;
2030 }
2031 } else {
2032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2033 alu.op = ALU_OP1_SIN;
2034 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2035
2036 alu.src[0].sel = ctx->temp_reg;
2037 alu.src[0].chan = 0;
2038 alu.last = 1;
2039 r = r600_bytecode_add_alu(ctx->bc, &alu);
2040 if (r)
2041 return r;
2042 }
2043 }
2044
2045 /* dst.z = 0.0; */
2046 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2048
2049 alu.op = ALU_OP1_MOV;
2050
2051 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2052
2053 alu.src[0].sel = V_SQ_ALU_SRC_0;
2054 alu.src[0].chan = 0;
2055
2056 alu.last = 1;
2057
2058 r = r600_bytecode_add_alu(ctx->bc, &alu);
2059 if (r)
2060 return r;
2061 }
2062
2063 /* dst.w = 1.0; */
2064 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2066
2067 alu.op = ALU_OP1_MOV;
2068
2069 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2070
2071 alu.src[0].sel = V_SQ_ALU_SRC_1;
2072 alu.src[0].chan = 0;
2073
2074 alu.last = 1;
2075
2076 r = r600_bytecode_add_alu(ctx->bc, &alu);
2077 if (r)
2078 return r;
2079 }
2080
2081 return 0;
2082 }
2083
2084 static int tgsi_kill(struct r600_shader_ctx *ctx)
2085 {
2086 struct r600_bytecode_alu alu;
2087 int i, r;
2088
2089 for (i = 0; i < 4; i++) {
2090 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2091 alu.op = ctx->inst_info->op;
2092
2093 alu.dst.chan = i;
2094
2095 alu.src[0].sel = V_SQ_ALU_SRC_0;
2096
2097 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILL) {
2098 alu.src[1].sel = V_SQ_ALU_SRC_1;
2099 alu.src[1].neg = 1;
2100 } else {
2101 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2102 }
2103 if (i == 3) {
2104 alu.last = 1;
2105 }
2106 r = r600_bytecode_add_alu(ctx->bc, &alu);
2107 if (r)
2108 return r;
2109 }
2110
2111 /* kill must be last in ALU */
2112 ctx->bc->force_add_cf = 1;
2113 ctx->shader->uses_kill = TRUE;
2114 return 0;
2115 }
2116
2117 static int tgsi_lit(struct r600_shader_ctx *ctx)
2118 {
2119 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2120 struct r600_bytecode_alu alu;
2121 int r;
2122
2123 /* tmp.x = max(src.y, 0.0) */
2124 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2125 alu.op = ALU_OP2_MAX;
2126 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2127 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2128 alu.src[1].chan = 1;
2129
2130 alu.dst.sel = ctx->temp_reg;
2131 alu.dst.chan = 0;
2132 alu.dst.write = 1;
2133
2134 alu.last = 1;
2135 r = r600_bytecode_add_alu(ctx->bc, &alu);
2136 if (r)
2137 return r;
2138
2139 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2140 {
2141 int chan;
2142 int sel;
2143 int i;
2144
2145 if (ctx->bc->chip_class == CAYMAN) {
2146 for (i = 0; i < 3; i++) {
2147 /* tmp.z = log(tmp.x) */
2148 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2149 alu.op = ALU_OP1_LOG_CLAMPED;
2150 alu.src[0].sel = ctx->temp_reg;
2151 alu.src[0].chan = 0;
2152 alu.dst.sel = ctx->temp_reg;
2153 alu.dst.chan = i;
2154 if (i == 2) {
2155 alu.dst.write = 1;
2156 alu.last = 1;
2157 } else
2158 alu.dst.write = 0;
2159
2160 r = r600_bytecode_add_alu(ctx->bc, &alu);
2161 if (r)
2162 return r;
2163 }
2164 } else {
2165 /* tmp.z = log(tmp.x) */
2166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2167 alu.op = ALU_OP1_LOG_CLAMPED;
2168 alu.src[0].sel = ctx->temp_reg;
2169 alu.src[0].chan = 0;
2170 alu.dst.sel = ctx->temp_reg;
2171 alu.dst.chan = 2;
2172 alu.dst.write = 1;
2173 alu.last = 1;
2174 r = r600_bytecode_add_alu(ctx->bc, &alu);
2175 if (r)
2176 return r;
2177 }
2178
2179 chan = alu.dst.chan;
2180 sel = alu.dst.sel;
2181
2182 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2183 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2184 alu.op = ALU_OP3_MUL_LIT;
2185 alu.src[0].sel = sel;
2186 alu.src[0].chan = chan;
2187 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2188 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2189 alu.dst.sel = ctx->temp_reg;
2190 alu.dst.chan = 0;
2191 alu.dst.write = 1;
2192 alu.is_op3 = 1;
2193 alu.last = 1;
2194 r = r600_bytecode_add_alu(ctx->bc, &alu);
2195 if (r)
2196 return r;
2197
2198 if (ctx->bc->chip_class == CAYMAN) {
2199 for (i = 0; i < 3; i++) {
2200 /* dst.z = exp(tmp.x) */
2201 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2202 alu.op = ALU_OP1_EXP_IEEE;
2203 alu.src[0].sel = ctx->temp_reg;
2204 alu.src[0].chan = 0;
2205 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2206 if (i == 2) {
2207 alu.dst.write = 1;
2208 alu.last = 1;
2209 } else
2210 alu.dst.write = 0;
2211 r = r600_bytecode_add_alu(ctx->bc, &alu);
2212 if (r)
2213 return r;
2214 }
2215 } else {
2216 /* dst.z = exp(tmp.x) */
2217 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2218 alu.op = ALU_OP1_EXP_IEEE;
2219 alu.src[0].sel = ctx->temp_reg;
2220 alu.src[0].chan = 0;
2221 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2222 alu.last = 1;
2223 r = r600_bytecode_add_alu(ctx->bc, &alu);
2224 if (r)
2225 return r;
2226 }
2227 }
2228
2229 /* dst.x, <- 1.0 */
2230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2231 alu.op = ALU_OP1_MOV;
2232 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2233 alu.src[0].chan = 0;
2234 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2235 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2236 r = r600_bytecode_add_alu(ctx->bc, &alu);
2237 if (r)
2238 return r;
2239
2240 /* dst.y = max(src.x, 0.0) */
2241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2242 alu.op = ALU_OP2_MAX;
2243 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2244 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2245 alu.src[1].chan = 0;
2246 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2247 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2248 r = r600_bytecode_add_alu(ctx->bc, &alu);
2249 if (r)
2250 return r;
2251
2252 /* dst.w, <- 1.0 */
2253 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2254 alu.op = ALU_OP1_MOV;
2255 alu.src[0].sel = V_SQ_ALU_SRC_1;
2256 alu.src[0].chan = 0;
2257 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2258 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2259 alu.last = 1;
2260 r = r600_bytecode_add_alu(ctx->bc, &alu);
2261 if (r)
2262 return r;
2263
2264 return 0;
2265 }
2266
2267 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2268 {
2269 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2270 struct r600_bytecode_alu alu;
2271 int i, r;
2272
2273 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2274
2275 /* XXX:
2276 * For state trackers other than OpenGL, we'll want to use
2277 * _RECIPSQRT_IEEE instead.
2278 */
2279 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2280
2281 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2282 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2283 r600_bytecode_src_set_abs(&alu.src[i]);
2284 }
2285 alu.dst.sel = ctx->temp_reg;
2286 alu.dst.write = 1;
2287 alu.last = 1;
2288 r = r600_bytecode_add_alu(ctx->bc, &alu);
2289 if (r)
2290 return r;
2291 /* replicate result */
2292 return tgsi_helper_tempx_replicate(ctx);
2293 }
2294
2295 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2296 {
2297 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2298 struct r600_bytecode_alu alu;
2299 int i, r;
2300
2301 for (i = 0; i < 4; i++) {
2302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2303 alu.src[0].sel = ctx->temp_reg;
2304 alu.op = ALU_OP1_MOV;
2305 alu.dst.chan = i;
2306 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2307 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2308 if (i == 3)
2309 alu.last = 1;
2310 r = r600_bytecode_add_alu(ctx->bc, &alu);
2311 if (r)
2312 return r;
2313 }
2314 return 0;
2315 }
2316
2317 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
2318 {
2319 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2320 struct r600_bytecode_alu alu;
2321 int i, r;
2322
2323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2324 alu.op = ctx->inst_info->op;
2325 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2326 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2327 }
2328 alu.dst.sel = ctx->temp_reg;
2329 alu.dst.write = 1;
2330 alu.last = 1;
2331 r = r600_bytecode_add_alu(ctx->bc, &alu);
2332 if (r)
2333 return r;
2334 /* replicate result */
2335 return tgsi_helper_tempx_replicate(ctx);
2336 }
2337
2338 static int cayman_pow(struct r600_shader_ctx *ctx)
2339 {
2340 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2341 int i, r;
2342 struct r600_bytecode_alu alu;
2343 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2344
2345 for (i = 0; i < 3; i++) {
2346 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2347 alu.op = ALU_OP1_LOG_IEEE;
2348 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2349 alu.dst.sel = ctx->temp_reg;
2350 alu.dst.chan = i;
2351 alu.dst.write = 1;
2352 if (i == 2)
2353 alu.last = 1;
2354 r = r600_bytecode_add_alu(ctx->bc, &alu);
2355 if (r)
2356 return r;
2357 }
2358
2359 /* b * LOG2(a) */
2360 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2361 alu.op = ALU_OP2_MUL;
2362 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2363 alu.src[1].sel = ctx->temp_reg;
2364 alu.dst.sel = ctx->temp_reg;
2365 alu.dst.write = 1;
2366 alu.last = 1;
2367 r = r600_bytecode_add_alu(ctx->bc, &alu);
2368 if (r)
2369 return r;
2370
2371 for (i = 0; i < last_slot; i++) {
2372 /* POW(a,b) = EXP2(b * LOG2(a))*/
2373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2374 alu.op = ALU_OP1_EXP_IEEE;
2375 alu.src[0].sel = ctx->temp_reg;
2376
2377 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2378 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2379 if (i == last_slot - 1)
2380 alu.last = 1;
2381 r = r600_bytecode_add_alu(ctx->bc, &alu);
2382 if (r)
2383 return r;
2384 }
2385 return 0;
2386 }
2387
2388 static int tgsi_pow(struct r600_shader_ctx *ctx)
2389 {
2390 struct r600_bytecode_alu alu;
2391 int r;
2392
2393 /* LOG2(a) */
2394 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2395 alu.op = ALU_OP1_LOG_IEEE;
2396 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2397 alu.dst.sel = ctx->temp_reg;
2398 alu.dst.write = 1;
2399 alu.last = 1;
2400 r = r600_bytecode_add_alu(ctx->bc, &alu);
2401 if (r)
2402 return r;
2403 /* b * LOG2(a) */
2404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2405 alu.op = ALU_OP2_MUL;
2406 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2407 alu.src[1].sel = ctx->temp_reg;
2408 alu.dst.sel = ctx->temp_reg;
2409 alu.dst.write = 1;
2410 alu.last = 1;
2411 r = r600_bytecode_add_alu(ctx->bc, &alu);
2412 if (r)
2413 return r;
2414 /* POW(a,b) = EXP2(b * LOG2(a))*/
2415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2416 alu.op = ALU_OP1_EXP_IEEE;
2417 alu.src[0].sel = ctx->temp_reg;
2418 alu.dst.sel = ctx->temp_reg;
2419 alu.dst.write = 1;
2420 alu.last = 1;
2421 r = r600_bytecode_add_alu(ctx->bc, &alu);
2422 if (r)
2423 return r;
2424 return tgsi_helper_tempx_replicate(ctx);
2425 }
2426
2427 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
2428 {
2429 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2430 struct r600_bytecode_alu alu;
2431 int i, r, j;
2432 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2433 int tmp0 = ctx->temp_reg;
2434 int tmp1 = r600_get_temp(ctx);
2435 int tmp2 = r600_get_temp(ctx);
2436 int tmp3 = r600_get_temp(ctx);
2437 /* Unsigned path:
2438 *
2439 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
2440 *
2441 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
2442 * 2. tmp0.z = lo (tmp0.x * src2)
2443 * 3. tmp0.w = -tmp0.z
2444 * 4. tmp0.y = hi (tmp0.x * src2)
2445 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
2446 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
2447 * 7. tmp1.x = tmp0.x - tmp0.w
2448 * 8. tmp1.y = tmp0.x + tmp0.w
2449 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
2450 * 10. tmp0.z = hi(tmp0.x * src1) = q
2451 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
2452 *
2453 * 12. tmp0.w = src1 - tmp0.y = r
2454 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
2455 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
2456 *
2457 * if DIV
2458 *
2459 * 15. tmp1.z = tmp0.z + 1 = q + 1
2460 * 16. tmp1.w = tmp0.z - 1 = q - 1
2461 *
2462 * else MOD
2463 *
2464 * 15. tmp1.z = tmp0.w - src2 = r - src2
2465 * 16. tmp1.w = tmp0.w + src2 = r + src2
2466 *
2467 * endif
2468 *
2469 * 17. tmp1.x = tmp1.x & tmp1.y
2470 *
2471 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
2472 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
2473 *
2474 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
2475 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
2476 *
2477 * Signed path:
2478 *
2479 * Same as unsigned, using abs values of the operands,
2480 * and fixing the sign of the result in the end.
2481 */
2482
2483 for (i = 0; i < 4; i++) {
2484 if (!(write_mask & (1<<i)))
2485 continue;
2486
2487 if (signed_op) {
2488
2489 /* tmp2.x = -src0 */
2490 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2491 alu.op = ALU_OP2_SUB_INT;
2492
2493 alu.dst.sel = tmp2;
2494 alu.dst.chan = 0;
2495 alu.dst.write = 1;
2496
2497 alu.src[0].sel = V_SQ_ALU_SRC_0;
2498
2499 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2500
2501 alu.last = 1;
2502 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2503 return r;
2504
2505 /* tmp2.y = -src1 */
2506 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2507 alu.op = ALU_OP2_SUB_INT;
2508
2509 alu.dst.sel = tmp2;
2510 alu.dst.chan = 1;
2511 alu.dst.write = 1;
2512
2513 alu.src[0].sel = V_SQ_ALU_SRC_0;
2514
2515 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2516
2517 alu.last = 1;
2518 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2519 return r;
2520
2521 /* tmp2.z sign bit is set if src0 and src2 signs are different */
2522 /* it will be a sign of the quotient */
2523 if (!mod) {
2524
2525 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2526 alu.op = ALU_OP2_XOR_INT;
2527
2528 alu.dst.sel = tmp2;
2529 alu.dst.chan = 2;
2530 alu.dst.write = 1;
2531
2532 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2533 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2534
2535 alu.last = 1;
2536 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2537 return r;
2538 }
2539
2540 /* tmp2.x = |src0| */
2541 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2542 alu.op = ALU_OP3_CNDGE_INT;
2543 alu.is_op3 = 1;
2544
2545 alu.dst.sel = tmp2;
2546 alu.dst.chan = 0;
2547 alu.dst.write = 1;
2548
2549 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2550 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2551 alu.src[2].sel = tmp2;
2552 alu.src[2].chan = 0;
2553
2554 alu.last = 1;
2555 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2556 return r;
2557
2558 /* tmp2.y = |src1| */
2559 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2560 alu.op = ALU_OP3_CNDGE_INT;
2561 alu.is_op3 = 1;
2562
2563 alu.dst.sel = tmp2;
2564 alu.dst.chan = 1;
2565 alu.dst.write = 1;
2566
2567 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2568 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2569 alu.src[2].sel = tmp2;
2570 alu.src[2].chan = 1;
2571
2572 alu.last = 1;
2573 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2574 return r;
2575
2576 }
2577
2578 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
2579 if (ctx->bc->chip_class == CAYMAN) {
2580 /* tmp3.x = u2f(src2) */
2581 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2582 alu.op = ALU_OP1_UINT_TO_FLT;
2583
2584 alu.dst.sel = tmp3;
2585 alu.dst.chan = 0;
2586 alu.dst.write = 1;
2587
2588 if (signed_op) {
2589 alu.src[0].sel = tmp2;
2590 alu.src[0].chan = 1;
2591 } else {
2592 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2593 }
2594
2595 alu.last = 1;
2596 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2597 return r;
2598
2599 /* tmp0.x = recip(tmp3.x) */
2600 for (j = 0 ; j < 3; j++) {
2601 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2602 alu.op = ALU_OP1_RECIP_IEEE;
2603
2604 alu.dst.sel = tmp0;
2605 alu.dst.chan = j;
2606 alu.dst.write = (j == 0);
2607
2608 alu.src[0].sel = tmp3;
2609 alu.src[0].chan = 0;
2610
2611 if (j == 2)
2612 alu.last = 1;
2613 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2614 return r;
2615 }
2616
2617 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2618 alu.op = ALU_OP2_MUL;
2619
2620 alu.src[0].sel = tmp0;
2621 alu.src[0].chan = 0;
2622
2623 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2624 alu.src[1].value = 0x4f800000;
2625
2626 alu.dst.sel = tmp3;
2627 alu.dst.write = 1;
2628 alu.last = 1;
2629 r = r600_bytecode_add_alu(ctx->bc, &alu);
2630 if (r)
2631 return r;
2632
2633 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2634 alu.op = ALU_OP1_FLT_TO_UINT;
2635
2636 alu.dst.sel = tmp0;
2637 alu.dst.chan = 0;
2638 alu.dst.write = 1;
2639
2640 alu.src[0].sel = tmp3;
2641 alu.src[0].chan = 0;
2642
2643 alu.last = 1;
2644 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2645 return r;
2646
2647 } else {
2648 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2649 alu.op = ALU_OP1_RECIP_UINT;
2650
2651 alu.dst.sel = tmp0;
2652 alu.dst.chan = 0;
2653 alu.dst.write = 1;
2654
2655 if (signed_op) {
2656 alu.src[0].sel = tmp2;
2657 alu.src[0].chan = 1;
2658 } else {
2659 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2660 }
2661
2662 alu.last = 1;
2663 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2664 return r;
2665 }
2666
2667 /* 2. tmp0.z = lo (tmp0.x * src2) */
2668 if (ctx->bc->chip_class == CAYMAN) {
2669 for (j = 0 ; j < 4; j++) {
2670 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2671 alu.op = ALU_OP2_MULLO_UINT;
2672
2673 alu.dst.sel = tmp0;
2674 alu.dst.chan = j;
2675 alu.dst.write = (j == 2);
2676
2677 alu.src[0].sel = tmp0;
2678 alu.src[0].chan = 0;
2679 if (signed_op) {
2680 alu.src[1].sel = tmp2;
2681 alu.src[1].chan = 1;
2682 } else {
2683 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2684 }
2685
2686 alu.last = (j == 3);
2687 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2688 return r;
2689 }
2690 } else {
2691 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2692 alu.op = ALU_OP2_MULLO_UINT;
2693
2694 alu.dst.sel = tmp0;
2695 alu.dst.chan = 2;
2696 alu.dst.write = 1;
2697
2698 alu.src[0].sel = tmp0;
2699 alu.src[0].chan = 0;
2700 if (signed_op) {
2701 alu.src[1].sel = tmp2;
2702 alu.src[1].chan = 1;
2703 } else {
2704 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2705 }
2706
2707 alu.last = 1;
2708 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2709 return r;
2710 }
2711
2712 /* 3. tmp0.w = -tmp0.z */
2713 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2714 alu.op = ALU_OP2_SUB_INT;
2715
2716 alu.dst.sel = tmp0;
2717 alu.dst.chan = 3;
2718 alu.dst.write = 1;
2719
2720 alu.src[0].sel = V_SQ_ALU_SRC_0;
2721 alu.src[1].sel = tmp0;
2722 alu.src[1].chan = 2;
2723
2724 alu.last = 1;
2725 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2726 return r;
2727
2728 /* 4. tmp0.y = hi (tmp0.x * src2) */
2729 if (ctx->bc->chip_class == CAYMAN) {
2730 for (j = 0 ; j < 4; j++) {
2731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2732 alu.op = ALU_OP2_MULHI_UINT;
2733
2734 alu.dst.sel = tmp0;
2735 alu.dst.chan = j;
2736 alu.dst.write = (j == 1);
2737
2738 alu.src[0].sel = tmp0;
2739 alu.src[0].chan = 0;
2740
2741 if (signed_op) {
2742 alu.src[1].sel = tmp2;
2743 alu.src[1].chan = 1;
2744 } else {
2745 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2746 }
2747 alu.last = (j == 3);
2748 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2749 return r;
2750 }
2751 } else {
2752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2753 alu.op = ALU_OP2_MULHI_UINT;
2754
2755 alu.dst.sel = tmp0;
2756 alu.dst.chan = 1;
2757 alu.dst.write = 1;
2758
2759 alu.src[0].sel = tmp0;
2760 alu.src[0].chan = 0;
2761
2762 if (signed_op) {
2763 alu.src[1].sel = tmp2;
2764 alu.src[1].chan = 1;
2765 } else {
2766 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
2767 }
2768
2769 alu.last = 1;
2770 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2771 return r;
2772 }
2773
2774 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
2775 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2776 alu.op = ALU_OP3_CNDE_INT;
2777 alu.is_op3 = 1;
2778
2779 alu.dst.sel = tmp0;
2780 alu.dst.chan = 2;
2781 alu.dst.write = 1;
2782
2783 alu.src[0].sel = tmp0;
2784 alu.src[0].chan = 1;
2785 alu.src[1].sel = tmp0;
2786 alu.src[1].chan = 3;
2787 alu.src[2].sel = tmp0;
2788 alu.src[2].chan = 2;
2789
2790 alu.last = 1;
2791 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2792 return r;
2793
2794 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
2795 if (ctx->bc->chip_class == CAYMAN) {
2796 for (j = 0 ; j < 4; j++) {
2797 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2798 alu.op = ALU_OP2_MULHI_UINT;
2799
2800 alu.dst.sel = tmp0;
2801 alu.dst.chan = j;
2802 alu.dst.write = (j == 3);
2803
2804 alu.src[0].sel = tmp0;
2805 alu.src[0].chan = 2;
2806
2807 alu.src[1].sel = tmp0;
2808 alu.src[1].chan = 0;
2809
2810 alu.last = (j == 3);
2811 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2812 return r;
2813 }
2814 } else {
2815 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2816 alu.op = ALU_OP2_MULHI_UINT;
2817
2818 alu.dst.sel = tmp0;
2819 alu.dst.chan = 3;
2820 alu.dst.write = 1;
2821
2822 alu.src[0].sel = tmp0;
2823 alu.src[0].chan = 2;
2824
2825 alu.src[1].sel = tmp0;
2826 alu.src[1].chan = 0;
2827
2828 alu.last = 1;
2829 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2830 return r;
2831 }
2832
2833 /* 7. tmp1.x = tmp0.x - tmp0.w */
2834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2835 alu.op = ALU_OP2_SUB_INT;
2836
2837 alu.dst.sel = tmp1;
2838 alu.dst.chan = 0;
2839 alu.dst.write = 1;
2840
2841 alu.src[0].sel = tmp0;
2842 alu.src[0].chan = 0;
2843 alu.src[1].sel = tmp0;
2844 alu.src[1].chan = 3;
2845
2846 alu.last = 1;
2847 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2848 return r;
2849
2850 /* 8. tmp1.y = tmp0.x + tmp0.w */
2851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2852 alu.op = ALU_OP2_ADD_INT;
2853
2854 alu.dst.sel = tmp1;
2855 alu.dst.chan = 1;
2856 alu.dst.write = 1;
2857
2858 alu.src[0].sel = tmp0;
2859 alu.src[0].chan = 0;
2860 alu.src[1].sel = tmp0;
2861 alu.src[1].chan = 3;
2862
2863 alu.last = 1;
2864 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2865 return r;
2866
2867 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
2868 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2869 alu.op = ALU_OP3_CNDE_INT;
2870 alu.is_op3 = 1;
2871
2872 alu.dst.sel = tmp0;
2873 alu.dst.chan = 0;
2874 alu.dst.write = 1;
2875
2876 alu.src[0].sel = tmp0;
2877 alu.src[0].chan = 1;
2878 alu.src[1].sel = tmp1;
2879 alu.src[1].chan = 1;
2880 alu.src[2].sel = tmp1;
2881 alu.src[2].chan = 0;
2882
2883 alu.last = 1;
2884 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2885 return r;
2886
2887 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
2888 if (ctx->bc->chip_class == CAYMAN) {
2889 for (j = 0 ; j < 4; j++) {
2890 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2891 alu.op = ALU_OP2_MULHI_UINT;
2892
2893 alu.dst.sel = tmp0;
2894 alu.dst.chan = j;
2895 alu.dst.write = (j == 2);
2896
2897 alu.src[0].sel = tmp0;
2898 alu.src[0].chan = 0;
2899
2900 if (signed_op) {
2901 alu.src[1].sel = tmp2;
2902 alu.src[1].chan = 0;
2903 } else {
2904 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2905 }
2906
2907 alu.last = (j == 3);
2908 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2909 return r;
2910 }
2911 } else {
2912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2913 alu.op = ALU_OP2_MULHI_UINT;
2914
2915 alu.dst.sel = tmp0;
2916 alu.dst.chan = 2;
2917 alu.dst.write = 1;
2918
2919 alu.src[0].sel = tmp0;
2920 alu.src[0].chan = 0;
2921
2922 if (signed_op) {
2923 alu.src[1].sel = tmp2;
2924 alu.src[1].chan = 0;
2925 } else {
2926 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2927 }
2928
2929 alu.last = 1;
2930 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2931 return r;
2932 }
2933
2934 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
2935 if (ctx->bc->chip_class == CAYMAN) {
2936 for (j = 0 ; j < 4; j++) {
2937 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2938 alu.op = ALU_OP2_MULLO_UINT;
2939
2940 alu.dst.sel = tmp0;
2941 alu.dst.chan = j;
2942 alu.dst.write = (j == 1);
2943
2944 if (signed_op) {
2945 alu.src[0].sel = tmp2;
2946 alu.src[0].chan = 1;
2947 } else {
2948 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2949 }
2950
2951 alu.src[1].sel = tmp0;
2952 alu.src[1].chan = 2;
2953
2954 alu.last = (j == 3);
2955 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2956 return r;
2957 }
2958 } else {
2959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2960 alu.op = ALU_OP2_MULLO_UINT;
2961
2962 alu.dst.sel = tmp0;
2963 alu.dst.chan = 1;
2964 alu.dst.write = 1;
2965
2966 if (signed_op) {
2967 alu.src[0].sel = tmp2;
2968 alu.src[0].chan = 1;
2969 } else {
2970 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2971 }
2972
2973 alu.src[1].sel = tmp0;
2974 alu.src[1].chan = 2;
2975
2976 alu.last = 1;
2977 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
2978 return r;
2979 }
2980
2981 /* 12. tmp0.w = src1 - tmp0.y = r */
2982 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2983 alu.op = ALU_OP2_SUB_INT;
2984
2985 alu.dst.sel = tmp0;
2986 alu.dst.chan = 3;
2987 alu.dst.write = 1;
2988
2989 if (signed_op) {
2990 alu.src[0].sel = tmp2;
2991 alu.src[0].chan = 0;
2992 } else {
2993 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2994 }
2995
2996 alu.src[1].sel = tmp0;
2997 alu.src[1].chan = 1;
2998
2999 alu.last = 1;
3000 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3001 return r;
3002
3003 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3004 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3005 alu.op = ALU_OP2_SETGE_UINT;
3006
3007 alu.dst.sel = tmp1;
3008 alu.dst.chan = 0;
3009 alu.dst.write = 1;
3010
3011 alu.src[0].sel = tmp0;
3012 alu.src[0].chan = 3;
3013 if (signed_op) {
3014 alu.src[1].sel = tmp2;
3015 alu.src[1].chan = 1;
3016 } else {
3017 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3018 }
3019
3020 alu.last = 1;
3021 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3022 return r;
3023
3024 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3026 alu.op = ALU_OP2_SETGE_UINT;
3027
3028 alu.dst.sel = tmp1;
3029 alu.dst.chan = 1;
3030 alu.dst.write = 1;
3031
3032 if (signed_op) {
3033 alu.src[0].sel = tmp2;
3034 alu.src[0].chan = 0;
3035 } else {
3036 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3037 }
3038
3039 alu.src[1].sel = tmp0;
3040 alu.src[1].chan = 1;
3041
3042 alu.last = 1;
3043 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3044 return r;
3045
3046 if (mod) { /* UMOD */
3047
3048 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3049 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3050 alu.op = ALU_OP2_SUB_INT;
3051
3052 alu.dst.sel = tmp1;
3053 alu.dst.chan = 2;
3054 alu.dst.write = 1;
3055
3056 alu.src[0].sel = tmp0;
3057 alu.src[0].chan = 3;
3058
3059 if (signed_op) {
3060 alu.src[1].sel = tmp2;
3061 alu.src[1].chan = 1;
3062 } else {
3063 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3064 }
3065
3066 alu.last = 1;
3067 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3068 return r;
3069
3070 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3071 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3072 alu.op = ALU_OP2_ADD_INT;
3073
3074 alu.dst.sel = tmp1;
3075 alu.dst.chan = 3;
3076 alu.dst.write = 1;
3077
3078 alu.src[0].sel = tmp0;
3079 alu.src[0].chan = 3;
3080 if (signed_op) {
3081 alu.src[1].sel = tmp2;
3082 alu.src[1].chan = 1;
3083 } else {
3084 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3085 }
3086
3087 alu.last = 1;
3088 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3089 return r;
3090
3091 } else { /* UDIV */
3092
3093 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3094 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3095 alu.op = ALU_OP2_ADD_INT;
3096
3097 alu.dst.sel = tmp1;
3098 alu.dst.chan = 2;
3099 alu.dst.write = 1;
3100
3101 alu.src[0].sel = tmp0;
3102 alu.src[0].chan = 2;
3103 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3104
3105 alu.last = 1;
3106 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3107 return r;
3108
3109 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3110 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3111 alu.op = ALU_OP2_ADD_INT;
3112
3113 alu.dst.sel = tmp1;
3114 alu.dst.chan = 3;
3115 alu.dst.write = 1;
3116
3117 alu.src[0].sel = tmp0;
3118 alu.src[0].chan = 2;
3119 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3120
3121 alu.last = 1;
3122 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3123 return r;
3124
3125 }
3126
3127 /* 17. tmp1.x = tmp1.x & tmp1.y */
3128 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3129 alu.op = ALU_OP2_AND_INT;
3130
3131 alu.dst.sel = tmp1;
3132 alu.dst.chan = 0;
3133 alu.dst.write = 1;
3134
3135 alu.src[0].sel = tmp1;
3136 alu.src[0].chan = 0;
3137 alu.src[1].sel = tmp1;
3138 alu.src[1].chan = 1;
3139
3140 alu.last = 1;
3141 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3142 return r;
3143
3144 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3145 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3147 alu.op = ALU_OP3_CNDE_INT;
3148 alu.is_op3 = 1;
3149
3150 alu.dst.sel = tmp0;
3151 alu.dst.chan = 2;
3152 alu.dst.write = 1;
3153
3154 alu.src[0].sel = tmp1;
3155 alu.src[0].chan = 0;
3156 alu.src[1].sel = tmp0;
3157 alu.src[1].chan = mod ? 3 : 2;
3158 alu.src[2].sel = tmp1;
3159 alu.src[2].chan = 2;
3160
3161 alu.last = 1;
3162 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3163 return r;
3164
3165 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3166 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3167 alu.op = ALU_OP3_CNDE_INT;
3168 alu.is_op3 = 1;
3169
3170 if (signed_op) {
3171 alu.dst.sel = tmp0;
3172 alu.dst.chan = 2;
3173 alu.dst.write = 1;
3174 } else {
3175 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3176 }
3177
3178 alu.src[0].sel = tmp1;
3179 alu.src[0].chan = 1;
3180 alu.src[1].sel = tmp1;
3181 alu.src[1].chan = 3;
3182 alu.src[2].sel = tmp0;
3183 alu.src[2].chan = 2;
3184
3185 alu.last = 1;
3186 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3187 return r;
3188
3189 if (signed_op) {
3190
3191 /* fix the sign of the result */
3192
3193 if (mod) {
3194
3195 /* tmp0.x = -tmp0.z */
3196 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3197 alu.op = ALU_OP2_SUB_INT;
3198
3199 alu.dst.sel = tmp0;
3200 alu.dst.chan = 0;
3201 alu.dst.write = 1;
3202
3203 alu.src[0].sel = V_SQ_ALU_SRC_0;
3204 alu.src[1].sel = tmp0;
3205 alu.src[1].chan = 2;
3206
3207 alu.last = 1;
3208 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3209 return r;
3210
3211 /* sign of the remainder is the same as the sign of src0 */
3212 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3214 alu.op = ALU_OP3_CNDGE_INT;
3215 alu.is_op3 = 1;
3216
3217 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3218
3219 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3220 alu.src[1].sel = tmp0;
3221 alu.src[1].chan = 2;
3222 alu.src[2].sel = tmp0;
3223 alu.src[2].chan = 0;
3224
3225 alu.last = 1;
3226 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3227 return r;
3228
3229 } else {
3230
3231 /* tmp0.x = -tmp0.z */
3232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3233 alu.op = ALU_OP2_SUB_INT;
3234
3235 alu.dst.sel = tmp0;
3236 alu.dst.chan = 0;
3237 alu.dst.write = 1;
3238
3239 alu.src[0].sel = V_SQ_ALU_SRC_0;
3240 alu.src[1].sel = tmp0;
3241 alu.src[1].chan = 2;
3242
3243 alu.last = 1;
3244 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3245 return r;
3246
3247 /* fix the quotient sign (same as the sign of src0*src1) */
3248 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3250 alu.op = ALU_OP3_CNDGE_INT;
3251 alu.is_op3 = 1;
3252
3253 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3254
3255 alu.src[0].sel = tmp2;
3256 alu.src[0].chan = 2;
3257 alu.src[1].sel = tmp0;
3258 alu.src[1].chan = 2;
3259 alu.src[2].sel = tmp0;
3260 alu.src[2].chan = 0;
3261
3262 alu.last = 1;
3263 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3264 return r;
3265 }
3266 }
3267 }
3268 return 0;
3269 }
3270
3271 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3272 {
3273 return tgsi_divmod(ctx, 0, 0);
3274 }
3275
3276 static int tgsi_umod(struct r600_shader_ctx *ctx)
3277 {
3278 return tgsi_divmod(ctx, 1, 0);
3279 }
3280
3281 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3282 {
3283 return tgsi_divmod(ctx, 0, 1);
3284 }
3285
3286 static int tgsi_imod(struct r600_shader_ctx *ctx)
3287 {
3288 return tgsi_divmod(ctx, 1, 1);
3289 }
3290
3291
3292 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3293 {
3294 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3295 struct r600_bytecode_alu alu;
3296 int i, r;
3297 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3298 int last_inst = tgsi_last_instruction(write_mask);
3299
3300 for (i = 0; i < 4; i++) {
3301 if (!(write_mask & (1<<i)))
3302 continue;
3303
3304 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3305 alu.op = ALU_OP1_TRUNC;
3306
3307 alu.dst.sel = ctx->temp_reg;
3308 alu.dst.chan = i;
3309 alu.dst.write = 1;
3310
3311 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3312 if (i == last_inst)
3313 alu.last = 1;
3314 r = r600_bytecode_add_alu(ctx->bc, &alu);
3315 if (r)
3316 return r;
3317 }
3318
3319 for (i = 0; i < 4; i++) {
3320 if (!(write_mask & (1<<i)))
3321 continue;
3322
3323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3324 alu.op = ctx->inst_info->op;
3325
3326 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3327
3328 alu.src[0].sel = ctx->temp_reg;
3329 alu.src[0].chan = i;
3330
3331 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
3332 alu.last = 1;
3333 r = r600_bytecode_add_alu(ctx->bc, &alu);
3334 if (r)
3335 return r;
3336 }
3337
3338 return 0;
3339 }
3340
3341 static int tgsi_iabs(struct r600_shader_ctx *ctx)
3342 {
3343 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3344 struct r600_bytecode_alu alu;
3345 int i, r;
3346 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3347 int last_inst = tgsi_last_instruction(write_mask);
3348
3349 /* tmp = -src */
3350 for (i = 0; i < 4; i++) {
3351 if (!(write_mask & (1<<i)))
3352 continue;
3353
3354 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3355 alu.op = ALU_OP2_SUB_INT;
3356
3357 alu.dst.sel = ctx->temp_reg;
3358 alu.dst.chan = i;
3359 alu.dst.write = 1;
3360
3361 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3362 alu.src[0].sel = V_SQ_ALU_SRC_0;
3363
3364 if (i == last_inst)
3365 alu.last = 1;
3366 r = r600_bytecode_add_alu(ctx->bc, &alu);
3367 if (r)
3368 return r;
3369 }
3370
3371 /* dst = (src >= 0 ? src : tmp) */
3372 for (i = 0; i < 4; i++) {
3373 if (!(write_mask & (1<<i)))
3374 continue;
3375
3376 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3377 alu.op = ALU_OP3_CNDGE_INT;
3378 alu.is_op3 = 1;
3379 alu.dst.write = 1;
3380
3381 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3382
3383 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3384 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3385 alu.src[2].sel = ctx->temp_reg;
3386 alu.src[2].chan = i;
3387
3388 if (i == last_inst)
3389 alu.last = 1;
3390 r = r600_bytecode_add_alu(ctx->bc, &alu);
3391 if (r)
3392 return r;
3393 }
3394 return 0;
3395 }
3396
3397 static int tgsi_issg(struct r600_shader_ctx *ctx)
3398 {
3399 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3400 struct r600_bytecode_alu alu;
3401 int i, r;
3402 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3403 int last_inst = tgsi_last_instruction(write_mask);
3404
3405 /* tmp = (src >= 0 ? src : -1) */
3406 for (i = 0; i < 4; i++) {
3407 if (!(write_mask & (1<<i)))
3408 continue;
3409
3410 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3411 alu.op = ALU_OP3_CNDGE_INT;
3412 alu.is_op3 = 1;
3413
3414 alu.dst.sel = ctx->temp_reg;
3415 alu.dst.chan = i;
3416 alu.dst.write = 1;
3417
3418 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3419 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3420 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
3421
3422 if (i == last_inst)
3423 alu.last = 1;
3424 r = r600_bytecode_add_alu(ctx->bc, &alu);
3425 if (r)
3426 return r;
3427 }
3428
3429 /* dst = (tmp > 0 ? 1 : tmp) */
3430 for (i = 0; i < 4; i++) {
3431 if (!(write_mask & (1<<i)))
3432 continue;
3433
3434 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3435 alu.op = ALU_OP3_CNDGT_INT;
3436 alu.is_op3 = 1;
3437 alu.dst.write = 1;
3438
3439 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3440
3441 alu.src[0].sel = ctx->temp_reg;
3442 alu.src[0].chan = i;
3443
3444 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3445
3446 alu.src[2].sel = ctx->temp_reg;
3447 alu.src[2].chan = i;
3448
3449 if (i == last_inst)
3450 alu.last = 1;
3451 r = r600_bytecode_add_alu(ctx->bc, &alu);
3452 if (r)
3453 return r;
3454 }
3455 return 0;
3456 }
3457
3458
3459
3460 static int tgsi_ssg(struct r600_shader_ctx *ctx)
3461 {
3462 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3463 struct r600_bytecode_alu alu;
3464 int i, r;
3465
3466 /* tmp = (src > 0 ? 1 : src) */
3467 for (i = 0; i < 4; i++) {
3468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3469 alu.op = ALU_OP3_CNDGT;
3470 alu.is_op3 = 1;
3471
3472 alu.dst.sel = ctx->temp_reg;
3473 alu.dst.chan = i;
3474
3475 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3476 alu.src[1].sel = V_SQ_ALU_SRC_1;
3477 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
3478
3479 if (i == 3)
3480 alu.last = 1;
3481 r = r600_bytecode_add_alu(ctx->bc, &alu);
3482 if (r)
3483 return r;
3484 }
3485
3486 /* dst = (-tmp > 0 ? -1 : tmp) */
3487 for (i = 0; i < 4; i++) {
3488 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3489 alu.op = ALU_OP3_CNDGT;
3490 alu.is_op3 = 1;
3491 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3492
3493 alu.src[0].sel = ctx->temp_reg;
3494 alu.src[0].chan = i;
3495 alu.src[0].neg = 1;
3496
3497 alu.src[1].sel = V_SQ_ALU_SRC_1;
3498 alu.src[1].neg = 1;
3499
3500 alu.src[2].sel = ctx->temp_reg;
3501 alu.src[2].chan = i;
3502
3503 if (i == 3)
3504 alu.last = 1;
3505 r = r600_bytecode_add_alu(ctx->bc, &alu);
3506 if (r)
3507 return r;
3508 }
3509 return 0;
3510 }
3511
3512 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
3513 {
3514 struct r600_bytecode_alu alu;
3515 int i, r;
3516
3517 for (i = 0; i < 4; i++) {
3518 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3519 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
3520 alu.op = ALU_OP0_NOP;
3521 alu.dst.chan = i;
3522 } else {
3523 alu.op = ALU_OP1_MOV;
3524 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3525 alu.src[0].sel = ctx->temp_reg;
3526 alu.src[0].chan = i;
3527 }
3528 if (i == 3) {
3529 alu.last = 1;
3530 }
3531 r = r600_bytecode_add_alu(ctx->bc, &alu);
3532 if (r)
3533 return r;
3534 }
3535 return 0;
3536 }
3537
3538 static int tgsi_op3(struct r600_shader_ctx *ctx)
3539 {
3540 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3541 struct r600_bytecode_alu alu;
3542 int i, j, r;
3543 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3544
3545 for (i = 0; i < lasti + 1; i++) {
3546 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3547 continue;
3548
3549 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3550 alu.op = ctx->inst_info->op;
3551 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3552 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3553 }
3554
3555 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3556 alu.dst.chan = i;
3557 alu.dst.write = 1;
3558 alu.is_op3 = 1;
3559 if (i == lasti) {
3560 alu.last = 1;
3561 }
3562 r = r600_bytecode_add_alu(ctx->bc, &alu);
3563 if (r)
3564 return r;
3565 }
3566 return 0;
3567 }
3568
3569 static int tgsi_dp(struct r600_shader_ctx *ctx)
3570 {
3571 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3572 struct r600_bytecode_alu alu;
3573 int i, j, r;
3574
3575 for (i = 0; i < 4; i++) {
3576 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3577 alu.op = ctx->inst_info->op;
3578 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3579 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3580 }
3581
3582 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3583 alu.dst.chan = i;
3584 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3585 /* handle some special cases */
3586 switch (ctx->inst_info->tgsi_opcode) {
3587 case TGSI_OPCODE_DP2:
3588 if (i > 1) {
3589 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3590 alu.src[0].chan = alu.src[1].chan = 0;
3591 }
3592 break;
3593 case TGSI_OPCODE_DP3:
3594 if (i > 2) {
3595 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
3596 alu.src[0].chan = alu.src[1].chan = 0;
3597 }
3598 break;
3599 case TGSI_OPCODE_DPH:
3600 if (i == 3) {
3601 alu.src[0].sel = V_SQ_ALU_SRC_1;
3602 alu.src[0].chan = 0;
3603 alu.src[0].neg = 0;
3604 }
3605 break;
3606 default:
3607 break;
3608 }
3609 if (i == 3) {
3610 alu.last = 1;
3611 }
3612 r = r600_bytecode_add_alu(ctx->bc, &alu);
3613 if (r)
3614 return r;
3615 }
3616 return 0;
3617 }
3618
3619 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
3620 unsigned index)
3621 {
3622 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3623 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
3624 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
3625 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
3626 ctx->src[index].neg || ctx->src[index].abs;
3627 }
3628
3629 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
3630 unsigned index)
3631 {
3632 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3633 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
3634 }
3635
3636 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
3637 {
3638 struct r600_bytecode_vtx vtx;
3639 struct r600_bytecode_alu alu;
3640 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3641 int src_gpr, r, i;
3642 int id = tgsi_tex_get_src_gpr(ctx, 1);
3643
3644 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3645 if (src_requires_loading) {
3646 for (i = 0; i < 4; i++) {
3647 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3648 alu.op = ALU_OP1_MOV;
3649 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3650 alu.dst.sel = ctx->temp_reg;
3651 alu.dst.chan = i;
3652 if (i == 3)
3653 alu.last = 1;
3654 alu.dst.write = 1;
3655 r = r600_bytecode_add_alu(ctx->bc, &alu);
3656 if (r)
3657 return r;
3658 }
3659 src_gpr = ctx->temp_reg;
3660 }
3661
3662 memset(&vtx, 0, sizeof(vtx));
3663 vtx.op = FETCH_OP_VFETCH;
3664 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
3665 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
3666 vtx.src_gpr = src_gpr;
3667 vtx.mega_fetch_count = 16;
3668 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
3669 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
3670 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
3671 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
3672 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
3673 vtx.use_const_fields = 1;
3674 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
3675
3676 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
3677 return r;
3678
3679 if (ctx->bc->chip_class >= EVERGREEN)
3680 return 0;
3681
3682 for (i = 0; i < 4; i++) {
3683 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3684 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3685 continue;
3686
3687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3688 alu.op = ALU_OP2_AND_INT;
3689
3690 alu.dst.chan = i;
3691 alu.dst.sel = vtx.dst_gpr;
3692 alu.dst.write = 1;
3693
3694 alu.src[0].sel = vtx.dst_gpr;
3695 alu.src[0].chan = i;
3696
3697 alu.src[1].sel = 512 + (id * 2);
3698 alu.src[1].chan = i % 4;
3699 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3700
3701 if (i == lasti)
3702 alu.last = 1;
3703 r = r600_bytecode_add_alu(ctx->bc, &alu);
3704 if (r)
3705 return r;
3706 }
3707
3708 if (inst->Dst[0].Register.WriteMask & 3) {
3709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3710 alu.op = ALU_OP2_OR_INT;
3711
3712 alu.dst.chan = 3;
3713 alu.dst.sel = vtx.dst_gpr;
3714 alu.dst.write = 1;
3715
3716 alu.src[0].sel = vtx.dst_gpr;
3717 alu.src[0].chan = 3;
3718
3719 alu.src[1].sel = 512 + (id * 2) + 1;
3720 alu.src[1].chan = 0;
3721 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3722
3723 alu.last = 1;
3724 r = r600_bytecode_add_alu(ctx->bc, &alu);
3725 if (r)
3726 return r;
3727 }
3728 return 0;
3729 }
3730
3731 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
3732 {
3733 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3734 struct r600_bytecode_alu alu;
3735 int r;
3736 int id = tgsi_tex_get_src_gpr(ctx, 1);
3737
3738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3739 alu.op = ALU_OP1_MOV;
3740
3741 if (ctx->bc->chip_class >= EVERGREEN) {
3742 alu.src[0].sel = 512 + (id / 4);
3743 alu.src[0].chan = id % 4;
3744 } else {
3745 /* r600 we have them at channel 2 of the second dword */
3746 alu.src[0].sel = 512 + (id * 2) + 1;
3747 alu.src[0].chan = 1;
3748 }
3749 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3750 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
3751 alu.last = 1;
3752 r = r600_bytecode_add_alu(ctx->bc, &alu);
3753 if (r)
3754 return r;
3755 return 0;
3756 }
3757
3758 static int tgsi_tex(struct r600_shader_ctx *ctx)
3759 {
3760 static float one_point_five = 1.5f;
3761 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3762 struct r600_bytecode_tex tex;
3763 struct r600_bytecode_alu alu;
3764 unsigned src_gpr;
3765 int r, i, j;
3766 int opcode;
3767 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
3768 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
3769 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
3770 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
3771
3772 /* Texture fetch instructions can only use gprs as source.
3773 * Also they cannot negate the source or take the absolute value */
3774 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3775 tgsi_tex_src_requires_loading(ctx, 0)) ||
3776 read_compressed_msaa;
3777 boolean src_loaded = FALSE;
3778 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3779 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
3780 boolean has_txq_cube_array_z = false;
3781
3782 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
3783 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3784 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
3785 if (inst->Dst[0].Register.WriteMask & 4) {
3786 ctx->shader->has_txq_cube_array_z_comp = true;
3787 has_txq_cube_array_z = true;
3788 }
3789
3790 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
3791 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
3792 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
3793 sampler_src_reg = 2;
3794
3795 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
3796
3797 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
3798 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
3799 ctx->shader->uses_tex_buffers = true;
3800 return r600_do_buffer_txq(ctx);
3801 }
3802 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3803 if (ctx->bc->chip_class < EVERGREEN)
3804 ctx->shader->uses_tex_buffers = true;
3805 return do_vtx_fetch_inst(ctx, src_requires_loading);
3806 }
3807 }
3808
3809 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3810 /* get offset values */
3811 if (inst->Texture.NumOffsets) {
3812 assert(inst->Texture.NumOffsets == 1);
3813
3814 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
3815 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
3816 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
3817 }
3818 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3819 /* TGSI moves the sampler to src reg 3 for TXD */
3820 sampler_src_reg = 3;
3821
3822 for (i = 1; i < 3; i++) {
3823 /* set gradients h/v */
3824 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
3825 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
3826 FETCH_OP_SET_GRADIENTS_V;
3827 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
3828 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
3829
3830 if (tgsi_tex_src_requires_loading(ctx, i)) {
3831 tex.src_gpr = r600_get_temp(ctx);
3832 tex.src_sel_x = 0;
3833 tex.src_sel_y = 1;
3834 tex.src_sel_z = 2;
3835 tex.src_sel_w = 3;
3836
3837 for (j = 0; j < 4; j++) {
3838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3839 alu.op = ALU_OP1_MOV;
3840 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
3841 alu.dst.sel = tex.src_gpr;
3842 alu.dst.chan = j;
3843 if (j == 3)
3844 alu.last = 1;
3845 alu.dst.write = 1;
3846 r = r600_bytecode_add_alu(ctx->bc, &alu);
3847 if (r)
3848 return r;
3849 }
3850
3851 } else {
3852 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
3853 tex.src_sel_x = ctx->src[i].swizzle[0];
3854 tex.src_sel_y = ctx->src[i].swizzle[1];
3855 tex.src_sel_z = ctx->src[i].swizzle[2];
3856 tex.src_sel_w = ctx->src[i].swizzle[3];
3857 tex.src_rel = ctx->src[i].rel;
3858 }
3859 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
3860 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
3861 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
3862 tex.coord_type_x = 1;
3863 tex.coord_type_y = 1;
3864 tex.coord_type_z = 1;
3865 tex.coord_type_w = 1;
3866 }
3867 r = r600_bytecode_add_tex(ctx->bc, &tex);
3868 if (r)
3869 return r;
3870 }
3871 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3872 int out_chan;
3873 /* Add perspective divide */
3874 if (ctx->bc->chip_class == CAYMAN) {
3875 out_chan = 2;
3876 for (i = 0; i < 3; i++) {
3877 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3878 alu.op = ALU_OP1_RECIP_IEEE;
3879 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3880
3881 alu.dst.sel = ctx->temp_reg;
3882 alu.dst.chan = i;
3883 if (i == 2)
3884 alu.last = 1;
3885 if (out_chan == i)
3886 alu.dst.write = 1;
3887 r = r600_bytecode_add_alu(ctx->bc, &alu);
3888 if (r)
3889 return r;
3890 }
3891
3892 } else {
3893 out_chan = 3;
3894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3895 alu.op = ALU_OP1_RECIP_IEEE;
3896 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
3897
3898 alu.dst.sel = ctx->temp_reg;
3899 alu.dst.chan = out_chan;
3900 alu.last = 1;
3901 alu.dst.write = 1;
3902 r = r600_bytecode_add_alu(ctx->bc, &alu);
3903 if (r)
3904 return r;
3905 }
3906
3907 for (i = 0; i < 3; i++) {
3908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3909 alu.op = ALU_OP2_MUL;
3910 alu.src[0].sel = ctx->temp_reg;
3911 alu.src[0].chan = out_chan;
3912 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3913 alu.dst.sel = ctx->temp_reg;
3914 alu.dst.chan = i;
3915 alu.dst.write = 1;
3916 r = r600_bytecode_add_alu(ctx->bc, &alu);
3917 if (r)
3918 return r;
3919 }
3920 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3921 alu.op = ALU_OP1_MOV;
3922 alu.src[0].sel = V_SQ_ALU_SRC_1;
3923 alu.src[0].chan = 0;
3924 alu.dst.sel = ctx->temp_reg;
3925 alu.dst.chan = 3;
3926 alu.last = 1;
3927 alu.dst.write = 1;
3928 r = r600_bytecode_add_alu(ctx->bc, &alu);
3929 if (r)
3930 return r;
3931 src_loaded = TRUE;
3932 src_gpr = ctx->temp_reg;
3933 }
3934
3935 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
3936 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
3937 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
3938 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
3939 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3940 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
3941
3942 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
3943 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
3944
3945 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
3946 for (i = 0; i < 4; i++) {
3947 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3948 alu.op = ALU_OP2_CUBE;
3949 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3950 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
3951 alu.dst.sel = ctx->temp_reg;
3952 alu.dst.chan = i;
3953 if (i == 3)
3954 alu.last = 1;
3955 alu.dst.write = 1;
3956 r = r600_bytecode_add_alu(ctx->bc, &alu);
3957 if (r)
3958 return r;
3959 }
3960
3961 /* tmp1.z = RCP_e(|tmp1.z|) */
3962 if (ctx->bc->chip_class == CAYMAN) {
3963 for (i = 0; i < 3; i++) {
3964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3965 alu.op = ALU_OP1_RECIP_IEEE;
3966 alu.src[0].sel = ctx->temp_reg;
3967 alu.src[0].chan = 2;
3968 alu.src[0].abs = 1;
3969 alu.dst.sel = ctx->temp_reg;
3970 alu.dst.chan = i;
3971 if (i == 2)
3972 alu.dst.write = 1;
3973 if (i == 2)
3974 alu.last = 1;
3975 r = r600_bytecode_add_alu(ctx->bc, &alu);
3976 if (r)
3977 return r;
3978 }
3979 } else {
3980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3981 alu.op = ALU_OP1_RECIP_IEEE;
3982 alu.src[0].sel = ctx->temp_reg;
3983 alu.src[0].chan = 2;
3984 alu.src[0].abs = 1;
3985 alu.dst.sel = ctx->temp_reg;
3986 alu.dst.chan = 2;
3987 alu.dst.write = 1;
3988 alu.last = 1;
3989 r = r600_bytecode_add_alu(ctx->bc, &alu);
3990 if (r)
3991 return r;
3992 }
3993
3994 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
3995 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
3996 * muladd has no writemask, have to use another temp
3997 */
3998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3999 alu.op = ALU_OP3_MULADD;
4000 alu.is_op3 = 1;
4001
4002 alu.src[0].sel = ctx->temp_reg;
4003 alu.src[0].chan = 0;
4004 alu.src[1].sel = ctx->temp_reg;
4005 alu.src[1].chan = 2;
4006
4007 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4008 alu.src[2].chan = 0;
4009 alu.src[2].value = *(uint32_t *)&one_point_five;
4010
4011 alu.dst.sel = ctx->temp_reg;
4012 alu.dst.chan = 0;
4013 alu.dst.write = 1;
4014
4015 r = r600_bytecode_add_alu(ctx->bc, &alu);
4016 if (r)
4017 return r;
4018
4019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4020 alu.op = ALU_OP3_MULADD;
4021 alu.is_op3 = 1;
4022
4023 alu.src[0].sel = ctx->temp_reg;
4024 alu.src[0].chan = 1;
4025 alu.src[1].sel = ctx->temp_reg;
4026 alu.src[1].chan = 2;
4027
4028 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4029 alu.src[2].chan = 0;
4030 alu.src[2].value = *(uint32_t *)&one_point_five;
4031
4032 alu.dst.sel = ctx->temp_reg;
4033 alu.dst.chan = 1;
4034 alu.dst.write = 1;
4035
4036 alu.last = 1;
4037 r = r600_bytecode_add_alu(ctx->bc, &alu);
4038 if (r)
4039 return r;
4040 /* write initial compare value into Z component
4041 - W src 0 for shadow cube
4042 - X src 1 for shadow cube array */
4043 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4044 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4046 alu.op = ALU_OP1_MOV;
4047 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4048 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4049 else
4050 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4051 alu.dst.sel = ctx->temp_reg;
4052 alu.dst.chan = 2;
4053 alu.dst.write = 1;
4054 alu.last = 1;
4055 r = r600_bytecode_add_alu(ctx->bc, &alu);
4056 if (r)
4057 return r;
4058 }
4059
4060 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4061 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4062 if (ctx->bc->chip_class >= EVERGREEN) {
4063 int mytmp = r600_get_temp(ctx);
4064 static const float eight = 8.0f;
4065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4066 alu.op = ALU_OP1_MOV;
4067 alu.src[0].sel = ctx->temp_reg;
4068 alu.src[0].chan = 3;
4069 alu.dst.sel = mytmp;
4070 alu.dst.chan = 0;
4071 alu.dst.write = 1;
4072 alu.last = 1;
4073 r = r600_bytecode_add_alu(ctx->bc, &alu);
4074 if (r)
4075 return r;
4076
4077 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4079 alu.op = ALU_OP3_MULADD;
4080 alu.is_op3 = 1;
4081 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4082 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4083 alu.src[1].chan = 0;
4084 alu.src[1].value = *(uint32_t *)&eight;
4085 alu.src[2].sel = mytmp;
4086 alu.src[2].chan = 0;
4087 alu.dst.sel = ctx->temp_reg;
4088 alu.dst.chan = 3;
4089 alu.dst.write = 1;
4090 alu.last = 1;
4091 r = r600_bytecode_add_alu(ctx->bc, &alu);
4092 if (r)
4093 return r;
4094 } else if (ctx->bc->chip_class < EVERGREEN) {
4095 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4096 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4097 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4098 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4099 tex.src_gpr = r600_get_temp(ctx);
4100 tex.src_sel_x = 0;
4101 tex.src_sel_y = 0;
4102 tex.src_sel_z = 0;
4103 tex.src_sel_w = 0;
4104 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4105 tex.coord_type_x = 1;
4106 tex.coord_type_y = 1;
4107 tex.coord_type_z = 1;
4108 tex.coord_type_w = 1;
4109 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4110 alu.op = ALU_OP1_MOV;
4111 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4112 alu.dst.sel = tex.src_gpr;
4113 alu.dst.chan = 0;
4114 alu.last = 1;
4115 alu.dst.write = 1;
4116 r = r600_bytecode_add_alu(ctx->bc, &alu);
4117 if (r)
4118 return r;
4119
4120 r = r600_bytecode_add_tex(ctx->bc, &tex);
4121 if (r)
4122 return r;
4123 }
4124
4125 }
4126
4127 /* for cube forms of lod and bias we need to route things */
4128 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4129 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4130 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4131 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4132 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4133 alu.op = ALU_OP1_MOV;
4134 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4135 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4136 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4137 else
4138 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4139 alu.dst.sel = ctx->temp_reg;
4140 alu.dst.chan = 2;
4141 alu.last = 1;
4142 alu.dst.write = 1;
4143 r = r600_bytecode_add_alu(ctx->bc, &alu);
4144 if (r)
4145 return r;
4146 }
4147
4148 src_loaded = TRUE;
4149 src_gpr = ctx->temp_reg;
4150 }
4151
4152 if (src_requires_loading && !src_loaded) {
4153 for (i = 0; i < 4; i++) {
4154 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4155 alu.op = ALU_OP1_MOV;
4156 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4157 alu.dst.sel = ctx->temp_reg;
4158 alu.dst.chan = i;
4159 if (i == 3)
4160 alu.last = 1;
4161 alu.dst.write = 1;
4162 r = r600_bytecode_add_alu(ctx->bc, &alu);
4163 if (r)
4164 return r;
4165 }
4166 src_loaded = TRUE;
4167 src_gpr = ctx->temp_reg;
4168 }
4169
4170 /* Obtain the sample index for reading a compressed MSAA color texture.
4171 * To read the FMASK, we use the ldfptr instruction, which tells us
4172 * where the samples are stored.
4173 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4174 * which is the identity mapping. Each nibble says which physical sample
4175 * should be fetched to get that sample.
4176 *
4177 * Assume src.z contains the sample index. It should be modified like this:
4178 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4179 * Then fetch the texel with src.
4180 */
4181 if (read_compressed_msaa) {
4182 unsigned sample_chan = 3;
4183 unsigned temp = r600_get_temp(ctx);
4184 assert(src_loaded);
4185
4186 /* temp.w = ldfptr() */
4187 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4188 tex.op = FETCH_OP_LD;
4189 tex.inst_mod = 1; /* to indicate this is ldfptr */
4190 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4191 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4192 tex.src_gpr = src_gpr;
4193 tex.dst_gpr = temp;
4194 tex.dst_sel_x = 7; /* mask out these components */
4195 tex.dst_sel_y = 7;
4196 tex.dst_sel_z = 7;
4197 tex.dst_sel_w = 0; /* store X */
4198 tex.src_sel_x = 0;
4199 tex.src_sel_y = 1;
4200 tex.src_sel_z = 2;
4201 tex.src_sel_w = 3;
4202 tex.offset_x = offset_x;
4203 tex.offset_y = offset_y;
4204 tex.offset_z = offset_z;
4205 r = r600_bytecode_add_tex(ctx->bc, &tex);
4206 if (r)
4207 return r;
4208
4209 /* temp.x = sample_index*4 */
4210 if (ctx->bc->chip_class == CAYMAN) {
4211 for (i = 0 ; i < 4; i++) {
4212 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4213 alu.op = ALU_OP2_MULLO_INT;
4214 alu.src[0].sel = src_gpr;
4215 alu.src[0].chan = sample_chan;
4216 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4217 alu.src[1].value = 4;
4218 alu.dst.sel = temp;
4219 alu.dst.chan = i;
4220 alu.dst.write = i == 0;
4221 if (i == 3)
4222 alu.last = 1;
4223 r = r600_bytecode_add_alu(ctx->bc, &alu);
4224 if (r)
4225 return r;
4226 }
4227 } else {
4228 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4229 alu.op = ALU_OP2_MULLO_INT;
4230 alu.src[0].sel = src_gpr;
4231 alu.src[0].chan = sample_chan;
4232 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4233 alu.src[1].value = 4;
4234 alu.dst.sel = temp;
4235 alu.dst.chan = 0;
4236 alu.dst.write = 1;
4237 alu.last = 1;
4238 r = r600_bytecode_add_alu(ctx->bc, &alu);
4239 if (r)
4240 return r;
4241 }
4242
4243 /* sample_index = temp.w >> temp.x */
4244 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4245 alu.op = ALU_OP2_LSHR_INT;
4246 alu.src[0].sel = temp;
4247 alu.src[0].chan = 3;
4248 alu.src[1].sel = temp;
4249 alu.src[1].chan = 0;
4250 alu.dst.sel = src_gpr;
4251 alu.dst.chan = sample_chan;
4252 alu.dst.write = 1;
4253 alu.last = 1;
4254 r = r600_bytecode_add_alu(ctx->bc, &alu);
4255 if (r)
4256 return r;
4257
4258 /* sample_index & 0xF */
4259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4260 alu.op = ALU_OP2_AND_INT;
4261 alu.src[0].sel = src_gpr;
4262 alu.src[0].chan = sample_chan;
4263 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4264 alu.src[1].value = 0xF;
4265 alu.dst.sel = src_gpr;
4266 alu.dst.chan = sample_chan;
4267 alu.dst.write = 1;
4268 alu.last = 1;
4269 r = r600_bytecode_add_alu(ctx->bc, &alu);
4270 if (r)
4271 return r;
4272 #if 0
4273 /* visualize the FMASK */
4274 for (i = 0; i < 4; i++) {
4275 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4276 alu.op = ALU_OP1_INT_TO_FLT;
4277 alu.src[0].sel = src_gpr;
4278 alu.src[0].chan = sample_chan;
4279 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4280 alu.dst.chan = i;
4281 alu.dst.write = 1;
4282 alu.last = 1;
4283 r = r600_bytecode_add_alu(ctx->bc, &alu);
4284 if (r)
4285 return r;
4286 }
4287 return 0;
4288 #endif
4289 }
4290
4291 /* does this shader want a num layers from TXQ for a cube array? */
4292 if (has_txq_cube_array_z) {
4293 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4294
4295 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4296 alu.op = ALU_OP1_MOV;
4297
4298 alu.src[0].sel = 512 + (id / 4);
4299 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
4300 alu.src[0].chan = id % 4;
4301 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4302 alu.last = 1;
4303 r = r600_bytecode_add_alu(ctx->bc, &alu);
4304 if (r)
4305 return r;
4306 /* disable writemask from texture instruction */
4307 inst->Dst[0].Register.WriteMask &= ~4;
4308 }
4309
4310 opcode = ctx->inst_info->op;
4311 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4312 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4313 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4314 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4315 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
4316 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4317 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4318 switch (opcode) {
4319 case FETCH_OP_SAMPLE:
4320 opcode = FETCH_OP_SAMPLE_C;
4321 break;
4322 case FETCH_OP_SAMPLE_L:
4323 opcode = FETCH_OP_SAMPLE_C_L;
4324 break;
4325 case FETCH_OP_SAMPLE_LB:
4326 opcode = FETCH_OP_SAMPLE_C_LB;
4327 break;
4328 case FETCH_OP_SAMPLE_G:
4329 opcode = FETCH_OP_SAMPLE_C_G;
4330 break;
4331 }
4332 }
4333
4334 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4335 tex.op = opcode;
4336
4337 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4338 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4339 tex.src_gpr = src_gpr;
4340 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4341 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
4342 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
4343 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
4344 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
4345
4346 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4347 tex.src_sel_x = 4;
4348 tex.src_sel_y = 4;
4349 tex.src_sel_z = 4;
4350 tex.src_sel_w = 4;
4351 } else if (src_loaded) {
4352 tex.src_sel_x = 0;
4353 tex.src_sel_y = 1;
4354 tex.src_sel_z = 2;
4355 tex.src_sel_w = 3;
4356 } else {
4357 tex.src_sel_x = ctx->src[0].swizzle[0];
4358 tex.src_sel_y = ctx->src[0].swizzle[1];
4359 tex.src_sel_z = ctx->src[0].swizzle[2];
4360 tex.src_sel_w = ctx->src[0].swizzle[3];
4361 tex.src_rel = ctx->src[0].rel;
4362 }
4363
4364 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4365 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4366 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4367 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4368 tex.src_sel_x = 1;
4369 tex.src_sel_y = 0;
4370 tex.src_sel_z = 3;
4371 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
4372 }
4373
4374 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
4375 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
4376 tex.coord_type_x = 1;
4377 tex.coord_type_y = 1;
4378 }
4379 tex.coord_type_z = 1;
4380 tex.coord_type_w = 1;
4381
4382 tex.offset_x = offset_x;
4383 tex.offset_y = offset_y;
4384 tex.offset_z = offset_z;
4385
4386 /* Put the depth for comparison in W.
4387 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
4388 * Some instructions expect the depth in Z. */
4389 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
4390 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
4391 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
4392 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
4393 opcode != FETCH_OP_SAMPLE_C_L &&
4394 opcode != FETCH_OP_SAMPLE_C_LB) {
4395 tex.src_sel_w = tex.src_sel_z;
4396 }
4397
4398 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
4399 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4400 if (opcode == FETCH_OP_SAMPLE_C_L ||
4401 opcode == FETCH_OP_SAMPLE_C_LB) {
4402 /* the array index is read from Y */
4403 tex.coord_type_y = 0;
4404 } else {
4405 /* the array index is read from Z */
4406 tex.coord_type_z = 0;
4407 tex.src_sel_z = tex.src_sel_y;
4408 }
4409 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
4410 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4411 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4412 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4413 (ctx->bc->chip_class >= EVERGREEN)))
4414 /* the array index is read from Z */
4415 tex.coord_type_z = 0;
4416
4417 /* mask unused source components */
4418 if (opcode == FETCH_OP_SAMPLE) {
4419 switch (inst->Texture.Texture) {
4420 case TGSI_TEXTURE_2D:
4421 case TGSI_TEXTURE_RECT:
4422 tex.src_sel_z = 7;
4423 tex.src_sel_w = 7;
4424 break;
4425 case TGSI_TEXTURE_1D_ARRAY:
4426 tex.src_sel_y = 7;
4427 tex.src_sel_w = 7;
4428 break;
4429 case TGSI_TEXTURE_1D:
4430 tex.src_sel_y = 7;
4431 tex.src_sel_z = 7;
4432 tex.src_sel_w = 7;
4433 break;
4434 }
4435 }
4436
4437 r = r600_bytecode_add_tex(ctx->bc, &tex);
4438 if (r)
4439 return r;
4440
4441 /* add shadow ambient support - gallium doesn't do it yet */
4442 return 0;
4443 }
4444
4445 static int tgsi_lrp(struct r600_shader_ctx *ctx)
4446 {
4447 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4448 struct r600_bytecode_alu alu;
4449 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4450 unsigned i;
4451 int r;
4452
4453 /* optimize if it's just an equal balance */
4454 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
4455 for (i = 0; i < lasti + 1; i++) {
4456 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4457 continue;
4458
4459 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4460 alu.op = ALU_OP2_ADD;
4461 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4462 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4463 alu.omod = 3;
4464 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4465 alu.dst.chan = i;
4466 if (i == lasti) {
4467 alu.last = 1;
4468 }
4469 r = r600_bytecode_add_alu(ctx->bc, &alu);
4470 if (r)
4471 return r;
4472 }
4473 return 0;
4474 }
4475
4476 /* 1 - src0 */
4477 for (i = 0; i < lasti + 1; i++) {
4478 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4479 continue;
4480
4481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4482 alu.op = ALU_OP2_ADD;
4483 alu.src[0].sel = V_SQ_ALU_SRC_1;
4484 alu.src[0].chan = 0;
4485 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4486 r600_bytecode_src_toggle_neg(&alu.src[1]);
4487 alu.dst.sel = ctx->temp_reg;
4488 alu.dst.chan = i;
4489 if (i == lasti) {
4490 alu.last = 1;
4491 }
4492 alu.dst.write = 1;
4493 r = r600_bytecode_add_alu(ctx->bc, &alu);
4494 if (r)
4495 return r;
4496 }
4497
4498 /* (1 - src0) * src2 */
4499 for (i = 0; i < lasti + 1; i++) {
4500 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4501 continue;
4502
4503 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4504 alu.op = ALU_OP2_MUL;
4505 alu.src[0].sel = ctx->temp_reg;
4506 alu.src[0].chan = i;
4507 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4508 alu.dst.sel = ctx->temp_reg;
4509 alu.dst.chan = i;
4510 if (i == lasti) {
4511 alu.last = 1;
4512 }
4513 alu.dst.write = 1;
4514 r = r600_bytecode_add_alu(ctx->bc, &alu);
4515 if (r)
4516 return r;
4517 }
4518
4519 /* src0 * src1 + (1 - src0) * src2 */
4520 for (i = 0; i < lasti + 1; i++) {
4521 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4522 continue;
4523
4524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4525 alu.op = ALU_OP3_MULADD;
4526 alu.is_op3 = 1;
4527 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4528 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
4529 alu.src[2].sel = ctx->temp_reg;
4530 alu.src[2].chan = i;
4531
4532 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4533 alu.dst.chan = i;
4534 if (i == lasti) {
4535 alu.last = 1;
4536 }
4537 r = r600_bytecode_add_alu(ctx->bc, &alu);
4538 if (r)
4539 return r;
4540 }
4541 return 0;
4542 }
4543
4544 static int tgsi_cmp(struct r600_shader_ctx *ctx)
4545 {
4546 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4547 struct r600_bytecode_alu alu;
4548 int i, r;
4549 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4550
4551 for (i = 0; i < lasti + 1; i++) {
4552 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4553 continue;
4554
4555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4556 alu.op = ALU_OP3_CNDGE;
4557 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4558 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4559 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4560 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4561 alu.dst.chan = i;
4562 alu.dst.write = 1;
4563 alu.is_op3 = 1;
4564 if (i == lasti)
4565 alu.last = 1;
4566 r = r600_bytecode_add_alu(ctx->bc, &alu);
4567 if (r)
4568 return r;
4569 }
4570 return 0;
4571 }
4572
4573 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
4574 {
4575 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4576 struct r600_bytecode_alu alu;
4577 int i, r;
4578 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4579
4580 for (i = 0; i < lasti + 1; i++) {
4581 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4582 continue;
4583
4584 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4585 alu.op = ALU_OP3_CNDGE_INT;
4586 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4587 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4588 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
4589 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4590 alu.dst.chan = i;
4591 alu.dst.write = 1;
4592 alu.is_op3 = 1;
4593 if (i == lasti)
4594 alu.last = 1;
4595 r = r600_bytecode_add_alu(ctx->bc, &alu);
4596 if (r)
4597 return r;
4598 }
4599 return 0;
4600 }
4601
4602 static int tgsi_xpd(struct r600_shader_ctx *ctx)
4603 {
4604 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4605 static const unsigned int src0_swizzle[] = {2, 0, 1};
4606 static const unsigned int src1_swizzle[] = {1, 2, 0};
4607 struct r600_bytecode_alu alu;
4608 uint32_t use_temp = 0;
4609 int i, r;
4610
4611 if (inst->Dst[0].Register.WriteMask != 0xf)
4612 use_temp = 1;
4613
4614 for (i = 0; i < 4; i++) {
4615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4616 alu.op = ALU_OP2_MUL;
4617 if (i < 3) {
4618 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4619 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
4620 } else {
4621 alu.src[0].sel = V_SQ_ALU_SRC_0;
4622 alu.src[0].chan = i;
4623 alu.src[1].sel = V_SQ_ALU_SRC_0;
4624 alu.src[1].chan = i;
4625 }
4626
4627 alu.dst.sel = ctx->temp_reg;
4628 alu.dst.chan = i;
4629 alu.dst.write = 1;
4630
4631 if (i == 3)
4632 alu.last = 1;
4633 r = r600_bytecode_add_alu(ctx->bc, &alu);
4634 if (r)
4635 return r;
4636 }
4637
4638 for (i = 0; i < 4; i++) {
4639 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4640 alu.op = ALU_OP3_MULADD;
4641
4642 if (i < 3) {
4643 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
4644 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
4645 } else {
4646 alu.src[0].sel = V_SQ_ALU_SRC_0;
4647 alu.src[0].chan = i;
4648 alu.src[1].sel = V_SQ_ALU_SRC_0;
4649 alu.src[1].chan = i;
4650 }
4651
4652 alu.src[2].sel = ctx->temp_reg;
4653 alu.src[2].neg = 1;
4654 alu.src[2].chan = i;
4655
4656 if (use_temp)
4657 alu.dst.sel = ctx->temp_reg;
4658 else
4659 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4660 alu.dst.chan = i;
4661 alu.dst.write = 1;
4662 alu.is_op3 = 1;
4663 if (i == 3)
4664 alu.last = 1;
4665 r = r600_bytecode_add_alu(ctx->bc, &alu);
4666 if (r)
4667 return r;
4668 }
4669 if (use_temp)
4670 return tgsi_helper_copy(ctx, inst);
4671 return 0;
4672 }
4673
4674 static int tgsi_exp(struct r600_shader_ctx *ctx)
4675 {
4676 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4677 struct r600_bytecode_alu alu;
4678 int r;
4679 int i;
4680
4681 /* result.x = 2^floor(src); */
4682 if (inst->Dst[0].Register.WriteMask & 1) {
4683 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4684
4685 alu.op = ALU_OP1_FLOOR;
4686 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4687
4688 alu.dst.sel = ctx->temp_reg;
4689 alu.dst.chan = 0;
4690 alu.dst.write = 1;
4691 alu.last = 1;
4692 r = r600_bytecode_add_alu(ctx->bc, &alu);
4693 if (r)
4694 return r;
4695
4696 if (ctx->bc->chip_class == CAYMAN) {
4697 for (i = 0; i < 3; i++) {
4698 alu.op = ALU_OP1_EXP_IEEE;
4699 alu.src[0].sel = ctx->temp_reg;
4700 alu.src[0].chan = 0;
4701
4702 alu.dst.sel = ctx->temp_reg;
4703 alu.dst.chan = i;
4704 alu.dst.write = i == 0;
4705 alu.last = i == 2;
4706 r = r600_bytecode_add_alu(ctx->bc, &alu);
4707 if (r)
4708 return r;
4709 }
4710 } else {
4711 alu.op = ALU_OP1_EXP_IEEE;
4712 alu.src[0].sel = ctx->temp_reg;
4713 alu.src[0].chan = 0;
4714
4715 alu.dst.sel = ctx->temp_reg;
4716 alu.dst.chan = 0;
4717 alu.dst.write = 1;
4718 alu.last = 1;
4719 r = r600_bytecode_add_alu(ctx->bc, &alu);
4720 if (r)
4721 return r;
4722 }
4723 }
4724
4725 /* result.y = tmp - floor(tmp); */
4726 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4727 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4728
4729 alu.op = ALU_OP1_FRACT;
4730 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4731
4732 alu.dst.sel = ctx->temp_reg;
4733 #if 0
4734 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4735 if (r)
4736 return r;
4737 #endif
4738 alu.dst.write = 1;
4739 alu.dst.chan = 1;
4740
4741 alu.last = 1;
4742
4743 r = r600_bytecode_add_alu(ctx->bc, &alu);
4744 if (r)
4745 return r;
4746 }
4747
4748 /* result.z = RoughApprox2ToX(tmp);*/
4749 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
4750 if (ctx->bc->chip_class == CAYMAN) {
4751 for (i = 0; i < 3; i++) {
4752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4753 alu.op = ALU_OP1_EXP_IEEE;
4754 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4755
4756 alu.dst.sel = ctx->temp_reg;
4757 alu.dst.chan = i;
4758 if (i == 2) {
4759 alu.dst.write = 1;
4760 alu.last = 1;
4761 }
4762
4763 r = r600_bytecode_add_alu(ctx->bc, &alu);
4764 if (r)
4765 return r;
4766 }
4767 } else {
4768 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4769 alu.op = ALU_OP1_EXP_IEEE;
4770 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4771
4772 alu.dst.sel = ctx->temp_reg;
4773 alu.dst.write = 1;
4774 alu.dst.chan = 2;
4775
4776 alu.last = 1;
4777
4778 r = r600_bytecode_add_alu(ctx->bc, &alu);
4779 if (r)
4780 return r;
4781 }
4782 }
4783
4784 /* result.w = 1.0;*/
4785 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
4786 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4787
4788 alu.op = ALU_OP1_MOV;
4789 alu.src[0].sel = V_SQ_ALU_SRC_1;
4790 alu.src[0].chan = 0;
4791
4792 alu.dst.sel = ctx->temp_reg;
4793 alu.dst.chan = 3;
4794 alu.dst.write = 1;
4795 alu.last = 1;
4796 r = r600_bytecode_add_alu(ctx->bc, &alu);
4797 if (r)
4798 return r;
4799 }
4800 return tgsi_helper_copy(ctx, inst);
4801 }
4802
4803 static int tgsi_log(struct r600_shader_ctx *ctx)
4804 {
4805 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4806 struct r600_bytecode_alu alu;
4807 int r;
4808 int i;
4809
4810 /* result.x = floor(log2(|src|)); */
4811 if (inst->Dst[0].Register.WriteMask & 1) {
4812 if (ctx->bc->chip_class == CAYMAN) {
4813 for (i = 0; i < 3; i++) {
4814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4815
4816 alu.op = ALU_OP1_LOG_IEEE;
4817 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4818 r600_bytecode_src_set_abs(&alu.src[0]);
4819
4820 alu.dst.sel = ctx->temp_reg;
4821 alu.dst.chan = i;
4822 if (i == 0)
4823 alu.dst.write = 1;
4824 if (i == 2)
4825 alu.last = 1;
4826 r = r600_bytecode_add_alu(ctx->bc, &alu);
4827 if (r)
4828 return r;
4829 }
4830
4831 } else {
4832 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4833
4834 alu.op = ALU_OP1_LOG_IEEE;
4835 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4836 r600_bytecode_src_set_abs(&alu.src[0]);
4837
4838 alu.dst.sel = ctx->temp_reg;
4839 alu.dst.chan = 0;
4840 alu.dst.write = 1;
4841 alu.last = 1;
4842 r = r600_bytecode_add_alu(ctx->bc, &alu);
4843 if (r)
4844 return r;
4845 }
4846
4847 alu.op = ALU_OP1_FLOOR;
4848 alu.src[0].sel = ctx->temp_reg;
4849 alu.src[0].chan = 0;
4850
4851 alu.dst.sel = ctx->temp_reg;
4852 alu.dst.chan = 0;
4853 alu.dst.write = 1;
4854 alu.last = 1;
4855
4856 r = r600_bytecode_add_alu(ctx->bc, &alu);
4857 if (r)
4858 return r;
4859 }
4860
4861 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
4862 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
4863
4864 if (ctx->bc->chip_class == CAYMAN) {
4865 for (i = 0; i < 3; i++) {
4866 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4867
4868 alu.op = ALU_OP1_LOG_IEEE;
4869 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4870 r600_bytecode_src_set_abs(&alu.src[0]);
4871
4872 alu.dst.sel = ctx->temp_reg;
4873 alu.dst.chan = i;
4874 if (i == 1)
4875 alu.dst.write = 1;
4876 if (i == 2)
4877 alu.last = 1;
4878
4879 r = r600_bytecode_add_alu(ctx->bc, &alu);
4880 if (r)
4881 return r;
4882 }
4883 } else {
4884 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4885
4886 alu.op = ALU_OP1_LOG_IEEE;
4887 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4888 r600_bytecode_src_set_abs(&alu.src[0]);
4889
4890 alu.dst.sel = ctx->temp_reg;
4891 alu.dst.chan = 1;
4892 alu.dst.write = 1;
4893 alu.last = 1;
4894
4895 r = r600_bytecode_add_alu(ctx->bc, &alu);
4896 if (r)
4897 return r;
4898 }
4899
4900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4901
4902 alu.op = ALU_OP1_FLOOR;
4903 alu.src[0].sel = ctx->temp_reg;
4904 alu.src[0].chan = 1;
4905
4906 alu.dst.sel = ctx->temp_reg;
4907 alu.dst.chan = 1;
4908 alu.dst.write = 1;
4909 alu.last = 1;
4910
4911 r = r600_bytecode_add_alu(ctx->bc, &alu);
4912 if (r)
4913 return r;
4914
4915 if (ctx->bc->chip_class == CAYMAN) {
4916 for (i = 0; i < 3; i++) {
4917 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4918 alu.op = ALU_OP1_EXP_IEEE;
4919 alu.src[0].sel = ctx->temp_reg;
4920 alu.src[0].chan = 1;
4921
4922 alu.dst.sel = ctx->temp_reg;
4923 alu.dst.chan = i;
4924 if (i == 1)
4925 alu.dst.write = 1;
4926 if (i == 2)
4927 alu.last = 1;
4928
4929 r = r600_bytecode_add_alu(ctx->bc, &alu);
4930 if (r)
4931 return r;
4932 }
4933 } else {
4934 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4935 alu.op = ALU_OP1_EXP_IEEE;
4936 alu.src[0].sel = ctx->temp_reg;
4937 alu.src[0].chan = 1;
4938
4939 alu.dst.sel = ctx->temp_reg;
4940 alu.dst.chan = 1;
4941 alu.dst.write = 1;
4942 alu.last = 1;
4943
4944 r = r600_bytecode_add_alu(ctx->bc, &alu);
4945 if (r)
4946 return r;
4947 }
4948
4949 if (ctx->bc->chip_class == CAYMAN) {
4950 for (i = 0; i < 3; i++) {
4951 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4952 alu.op = ALU_OP1_RECIP_IEEE;
4953 alu.src[0].sel = ctx->temp_reg;
4954 alu.src[0].chan = 1;
4955
4956 alu.dst.sel = ctx->temp_reg;
4957 alu.dst.chan = i;
4958 if (i == 1)
4959 alu.dst.write = 1;
4960 if (i == 2)
4961 alu.last = 1;
4962
4963 r = r600_bytecode_add_alu(ctx->bc, &alu);
4964 if (r)
4965 return r;
4966 }
4967 } else {
4968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4969 alu.op = ALU_OP1_RECIP_IEEE;
4970 alu.src[0].sel = ctx->temp_reg;
4971 alu.src[0].chan = 1;
4972
4973 alu.dst.sel = ctx->temp_reg;
4974 alu.dst.chan = 1;
4975 alu.dst.write = 1;
4976 alu.last = 1;
4977
4978 r = r600_bytecode_add_alu(ctx->bc, &alu);
4979 if (r)
4980 return r;
4981 }
4982
4983 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4984
4985 alu.op = ALU_OP2_MUL;
4986
4987 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4988 r600_bytecode_src_set_abs(&alu.src[0]);
4989
4990 alu.src[1].sel = ctx->temp_reg;
4991 alu.src[1].chan = 1;
4992
4993 alu.dst.sel = ctx->temp_reg;
4994 alu.dst.chan = 1;
4995 alu.dst.write = 1;
4996 alu.last = 1;
4997
4998 r = r600_bytecode_add_alu(ctx->bc, &alu);
4999 if (r)
5000 return r;
5001 }
5002
5003 /* result.z = log2(|src|);*/
5004 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5005 if (ctx->bc->chip_class == CAYMAN) {
5006 for (i = 0; i < 3; i++) {
5007 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5008
5009 alu.op = ALU_OP1_LOG_IEEE;
5010 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5011 r600_bytecode_src_set_abs(&alu.src[0]);
5012
5013 alu.dst.sel = ctx->temp_reg;
5014 if (i == 2)
5015 alu.dst.write = 1;
5016 alu.dst.chan = i;
5017 if (i == 2)
5018 alu.last = 1;
5019
5020 r = r600_bytecode_add_alu(ctx->bc, &alu);
5021 if (r)
5022 return r;
5023 }
5024 } else {
5025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5026
5027 alu.op = ALU_OP1_LOG_IEEE;
5028 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5029 r600_bytecode_src_set_abs(&alu.src[0]);
5030
5031 alu.dst.sel = ctx->temp_reg;
5032 alu.dst.write = 1;
5033 alu.dst.chan = 2;
5034 alu.last = 1;
5035
5036 r = r600_bytecode_add_alu(ctx->bc, &alu);
5037 if (r)
5038 return r;
5039 }
5040 }
5041
5042 /* result.w = 1.0; */
5043 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5045
5046 alu.op = ALU_OP1_MOV;
5047 alu.src[0].sel = V_SQ_ALU_SRC_1;
5048 alu.src[0].chan = 0;
5049
5050 alu.dst.sel = ctx->temp_reg;
5051 alu.dst.chan = 3;
5052 alu.dst.write = 1;
5053 alu.last = 1;
5054
5055 r = r600_bytecode_add_alu(ctx->bc, &alu);
5056 if (r)
5057 return r;
5058 }
5059
5060 return tgsi_helper_copy(ctx, inst);
5061 }
5062
5063 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5064 {
5065 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5066 struct r600_bytecode_alu alu;
5067 int r;
5068
5069 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5070
5071 switch (inst->Instruction.Opcode) {
5072 case TGSI_OPCODE_ARL:
5073 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5074 break;
5075 case TGSI_OPCODE_ARR:
5076 alu.op = ALU_OP1_FLT_TO_INT;
5077 break;
5078 case TGSI_OPCODE_UARL:
5079 alu.op = ALU_OP1_MOV;
5080 break;
5081 default:
5082 assert(0);
5083 return -1;
5084 }
5085
5086 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5087 alu.last = 1;
5088 alu.dst.sel = ctx->bc->ar_reg;
5089 alu.dst.write = 1;
5090 r = r600_bytecode_add_alu(ctx->bc, &alu);
5091 if (r)
5092 return r;
5093
5094 ctx->bc->ar_loaded = 0;
5095 return 0;
5096 }
5097 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5098 {
5099 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5100 struct r600_bytecode_alu alu;
5101 int r;
5102
5103 switch (inst->Instruction.Opcode) {
5104 case TGSI_OPCODE_ARL:
5105 memset(&alu, 0, sizeof(alu));
5106 alu.op = ALU_OP1_FLOOR;
5107 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5108 alu.dst.sel = ctx->bc->ar_reg;
5109 alu.dst.write = 1;
5110 alu.last = 1;
5111
5112 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5113 return r;
5114
5115 memset(&alu, 0, sizeof(alu));
5116 alu.op = ALU_OP1_FLT_TO_INT;
5117 alu.src[0].sel = ctx->bc->ar_reg;
5118 alu.dst.sel = ctx->bc->ar_reg;
5119 alu.dst.write = 1;
5120 alu.last = 1;
5121
5122 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5123 return r;
5124 break;
5125 case TGSI_OPCODE_ARR:
5126 memset(&alu, 0, sizeof(alu));
5127 alu.op = ALU_OP1_FLT_TO_INT;
5128 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5129 alu.dst.sel = ctx->bc->ar_reg;
5130 alu.dst.write = 1;
5131 alu.last = 1;
5132
5133 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5134 return r;
5135 break;
5136 case TGSI_OPCODE_UARL:
5137 memset(&alu, 0, sizeof(alu));
5138 alu.op = ALU_OP1_MOV;
5139 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5140 alu.dst.sel = ctx->bc->ar_reg;
5141 alu.dst.write = 1;
5142 alu.last = 1;
5143
5144 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5145 return r;
5146 break;
5147 default:
5148 assert(0);
5149 return -1;
5150 }
5151
5152 ctx->bc->ar_loaded = 0;
5153 return 0;
5154 }
5155
5156 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5157 {
5158 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5159 struct r600_bytecode_alu alu;
5160 int i, r = 0;
5161
5162 for (i = 0; i < 4; i++) {
5163 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5164
5165 alu.op = ALU_OP2_MUL;
5166 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5167
5168 if (i == 0 || i == 3) {
5169 alu.src[0].sel = V_SQ_ALU_SRC_1;
5170 } else {
5171 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5172 }
5173
5174 if (i == 0 || i == 2) {
5175 alu.src[1].sel = V_SQ_ALU_SRC_1;
5176 } else {
5177 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5178 }
5179 if (i == 3)
5180 alu.last = 1;
5181 r = r600_bytecode_add_alu(ctx->bc, &alu);
5182 if (r)
5183 return r;
5184 }
5185 return 0;
5186 }
5187
5188 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5189 {
5190 struct r600_bytecode_alu alu;
5191 int r;
5192
5193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5194 alu.op = opcode;
5195 alu.execute_mask = 1;
5196 alu.update_pred = 1;
5197
5198 alu.dst.sel = ctx->temp_reg;
5199 alu.dst.write = 1;
5200 alu.dst.chan = 0;
5201
5202 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5203 alu.src[1].sel = V_SQ_ALU_SRC_0;
5204 alu.src[1].chan = 0;
5205
5206 alu.last = 1;
5207
5208 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
5209 if (r)
5210 return r;
5211 return 0;
5212 }
5213
5214 static int pops(struct r600_shader_ctx *ctx, int pops)
5215 {
5216 unsigned force_pop = ctx->bc->force_add_cf;
5217
5218 if (!force_pop) {
5219 int alu_pop = 3;
5220 if (ctx->bc->cf_last) {
5221 if (ctx->bc->cf_last->op == CF_OP_ALU)
5222 alu_pop = 0;
5223 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
5224 alu_pop = 1;
5225 }
5226 alu_pop += pops;
5227 if (alu_pop == 1) {
5228 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
5229 ctx->bc->force_add_cf = 1;
5230 } else if (alu_pop == 2) {
5231 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
5232 ctx->bc->force_add_cf = 1;
5233 } else {
5234 force_pop = 1;
5235 }
5236 }
5237
5238 if (force_pop) {
5239 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
5240 ctx->bc->cf_last->pop_count = pops;
5241 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5242 }
5243
5244 return 0;
5245 }
5246
5247 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
5248 unsigned reason)
5249 {
5250 struct r600_stack_info *stack = &ctx->bc->stack;
5251 unsigned elements, entries;
5252
5253 unsigned entry_size = stack->entry_size;
5254
5255 elements = (stack->loop + stack->push_wqm ) * entry_size;
5256 elements += stack->push;
5257
5258 switch (ctx->bc->chip_class) {
5259 case R600:
5260 case R700:
5261 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
5262 * the stack must be reserved to hold the current active/continue
5263 * masks */
5264 if (reason == FC_PUSH_VPM) {
5265 elements += 2;
5266 }
5267 break;
5268
5269 case CAYMAN:
5270 /* r9xx: any stack operation on empty stack consumes 2 additional
5271 * elements */
5272 elements += 2;
5273
5274 /* fallthrough */
5275 /* FIXME: do the two elements added above cover the cases for the
5276 * r8xx+ below? */
5277
5278 case EVERGREEN:
5279 /* r8xx+: 2 extra elements are not always required, but one extra
5280 * element must be added for each of the following cases:
5281 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
5282 * stack usage.
5283 * (Currently we don't use ALU_ELSE_AFTER.)
5284 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
5285 * PUSH instruction executed.
5286 *
5287 * NOTE: it seems we also need to reserve additional element in some
5288 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
5289 * then STACK_SIZE should be 2 instead of 1 */
5290 if (reason == FC_PUSH_VPM) {
5291 elements += 1;
5292 }
5293 break;
5294
5295 default:
5296 assert(0);
5297 break;
5298 }
5299
5300 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
5301 * for all chips, so we use 4 in the final formula, not the real entry_size
5302 * for the chip */
5303 entry_size = 4;
5304
5305 entries = (elements + (entry_size - 1)) / entry_size;
5306
5307 if (entries > stack->max_entries)
5308 stack->max_entries = entries;
5309 }
5310
5311 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
5312 {
5313 switch(reason) {
5314 case FC_PUSH_VPM:
5315 --ctx->bc->stack.push;
5316 assert(ctx->bc->stack.push >= 0);
5317 break;
5318 case FC_PUSH_WQM:
5319 --ctx->bc->stack.push_wqm;
5320 assert(ctx->bc->stack.push_wqm >= 0);
5321 break;
5322 case FC_LOOP:
5323 --ctx->bc->stack.loop;
5324 assert(ctx->bc->stack.loop >= 0);
5325 break;
5326 default:
5327 assert(0);
5328 break;
5329 }
5330 }
5331
5332 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
5333 {
5334 switch (reason) {
5335 case FC_PUSH_VPM:
5336 ++ctx->bc->stack.push;
5337 break;
5338 case FC_PUSH_WQM:
5339 ++ctx->bc->stack.push_wqm;
5340 case FC_LOOP:
5341 ++ctx->bc->stack.loop;
5342 break;
5343 default:
5344 assert(0);
5345 }
5346
5347 callstack_update_max_depth(ctx, reason);
5348 }
5349
5350 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
5351 {
5352 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
5353
5354 sp->mid = realloc((void *)sp->mid,
5355 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
5356 sp->mid[sp->num_mid] = ctx->bc->cf_last;
5357 sp->num_mid++;
5358 }
5359
5360 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
5361 {
5362 ctx->bc->fc_sp++;
5363 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
5364 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
5365 }
5366
5367 static void fc_poplevel(struct r600_shader_ctx *ctx)
5368 {
5369 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
5370 free(sp->mid);
5371 sp->mid = NULL;
5372 sp->num_mid = 0;
5373 sp->start = NULL;
5374 sp->type = 0;
5375 ctx->bc->fc_sp--;
5376 }
5377
5378 #if 0
5379 static int emit_return(struct r600_shader_ctx *ctx)
5380 {
5381 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
5382 return 0;
5383 }
5384
5385 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
5386 {
5387
5388 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
5389 ctx->bc->cf_last->pop_count = pops;
5390 /* XXX work out offset */
5391 return 0;
5392 }
5393
5394 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
5395 {
5396 return 0;
5397 }
5398
5399 static void emit_testflag(struct r600_shader_ctx *ctx)
5400 {
5401
5402 }
5403
5404 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
5405 {
5406 emit_testflag(ctx);
5407 emit_jump_to_offset(ctx, 1, 4);
5408 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
5409 pops(ctx, ifidx + 1);
5410 emit_return(ctx);
5411 }
5412
5413 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
5414 {
5415 emit_testflag(ctx);
5416
5417 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5418 ctx->bc->cf_last->pop_count = 1;
5419
5420 fc_set_mid(ctx, fc_sp);
5421
5422 pops(ctx, 1);
5423 }
5424 #endif
5425
5426 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
5427 {
5428 int alu_type = CF_OP_ALU_PUSH_BEFORE;
5429
5430 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
5431 * LOOP_STARTxxx for nested loops may put the branch stack into a state
5432 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
5433 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
5434 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
5435 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
5436 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
5437 alu_type = CF_OP_ALU;
5438 }
5439
5440 emit_logic_pred(ctx, opcode, alu_type);
5441
5442 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
5443
5444 fc_pushlevel(ctx, FC_IF);
5445
5446 callstack_push(ctx, FC_PUSH_VPM);
5447 return 0;
5448 }
5449
5450 static int tgsi_if(struct r600_shader_ctx *ctx)
5451 {
5452 return emit_if(ctx, ALU_OP2_PRED_SETNE);
5453 }
5454
5455 static int tgsi_uif(struct r600_shader_ctx *ctx)
5456 {
5457 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
5458 }
5459
5460 static int tgsi_else(struct r600_shader_ctx *ctx)
5461 {
5462 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
5463 ctx->bc->cf_last->pop_count = 1;
5464
5465 fc_set_mid(ctx, ctx->bc->fc_sp);
5466 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
5467 return 0;
5468 }
5469
5470 static int tgsi_endif(struct r600_shader_ctx *ctx)
5471 {
5472 pops(ctx, 1);
5473 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
5474 R600_ERR("if/endif unbalanced in shader\n");
5475 return -1;
5476 }
5477
5478 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
5479 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5480 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
5481 } else {
5482 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
5483 }
5484 fc_poplevel(ctx);
5485
5486 callstack_pop(ctx, FC_PUSH_VPM);
5487 return 0;
5488 }
5489
5490 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
5491 {
5492 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
5493 * limited to 4096 iterations, like the other LOOP_* instructions. */
5494 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
5495
5496 fc_pushlevel(ctx, FC_LOOP);
5497
5498 /* check stack depth */
5499 callstack_push(ctx, FC_LOOP);
5500 return 0;
5501 }
5502
5503 static int tgsi_endloop(struct r600_shader_ctx *ctx)
5504 {
5505 int i;
5506
5507 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
5508
5509 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
5510 R600_ERR("loop/endloop in shader code are not paired.\n");
5511 return -EINVAL;
5512 }
5513
5514 /* fixup loop pointers - from r600isa
5515 LOOP END points to CF after LOOP START,
5516 LOOP START point to CF after LOOP END
5517 BRK/CONT point to LOOP END CF
5518 */
5519 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
5520
5521 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
5522
5523 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
5524 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
5525 }
5526 /* XXX add LOOPRET support */
5527 fc_poplevel(ctx);
5528 callstack_pop(ctx, FC_LOOP);
5529 return 0;
5530 }
5531
5532 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
5533 {
5534 unsigned int fscp;
5535
5536 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
5537 {
5538 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
5539 break;
5540 }
5541
5542 if (fscp == 0) {
5543 R600_ERR("Break not inside loop/endloop pair\n");
5544 return -EINVAL;
5545 }
5546
5547 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
5548
5549 fc_set_mid(ctx, fscp);
5550
5551 return 0;
5552 }
5553
5554 static int tgsi_umad(struct r600_shader_ctx *ctx)
5555 {
5556 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5557 struct r600_bytecode_alu alu;
5558 int i, j, k, r;
5559 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5560
5561 /* src0 * src1 */
5562 for (i = 0; i < lasti + 1; i++) {
5563 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5564 continue;
5565
5566 if (ctx->bc->chip_class == CAYMAN) {
5567 for (j = 0 ; j < 4; j++) {
5568 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5569
5570 alu.op = ALU_OP2_MULLO_UINT;
5571 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
5572 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
5573 }
5574 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
5575 alu.dst.sel = ctx->temp_reg;
5576 alu.dst.write = (j == i);
5577 if (j == 3)
5578 alu.last = 1;
5579 r = r600_bytecode_add_alu(ctx->bc, &alu);
5580 if (r)
5581 return r;
5582 }
5583 } else {
5584 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5585
5586 alu.dst.chan = i;
5587 alu.dst.sel = ctx->temp_reg;
5588 alu.dst.write = 1;
5589
5590 alu.op = ALU_OP2_MULLO_UINT;
5591 for (j = 0; j < 2; j++) {
5592 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
5593 }
5594
5595 alu.last = 1;
5596 r = r600_bytecode_add_alu(ctx->bc, &alu);
5597 if (r)
5598 return r;
5599 }
5600 }
5601
5602
5603 for (i = 0; i < lasti + 1; i++) {
5604 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5605 continue;
5606
5607 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5608 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5609
5610 alu.op = ALU_OP2_ADD_INT;
5611
5612 alu.src[0].sel = ctx->temp_reg;
5613 alu.src[0].chan = i;
5614
5615 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5616 if (i == lasti) {
5617 alu.last = 1;
5618 }
5619 r = r600_bytecode_add_alu(ctx->bc, &alu);
5620 if (r)
5621 return r;
5622 }
5623 return 0;
5624 }
5625
5626 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
5627 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
5628 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5629 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5630
5631 /* XXX:
5632 * For state trackers other than OpenGL, we'll want to use
5633 * _RECIP_IEEE instead.
5634 */
5635 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
5636
5637 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
5638 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5639 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5640 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5641 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5642 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5643 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5644 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5645 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5646 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5647 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5648 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5649 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5650 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5651 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5652 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5653 /* gap */
5654 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5655 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5656 /* gap */
5657 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5658 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5659 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5660 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5661 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5662 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5663 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5664 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5665 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5666 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5667 /* gap */
5668 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5669 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5670 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5671 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5672 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5673 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5674 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5675 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
5676 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5677 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5678 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5679 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5680 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5681 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5682 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5683 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5684 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5685 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5686 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5687 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5688 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5689 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5690 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5691 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5692 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5693 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5694 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5695 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5696 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5697 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
5698 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5699 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5700 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5701 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5702 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5703 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5704 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5705 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5706 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5707 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5708 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5709 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5710 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5711 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5712 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5713 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5714 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5715 /* gap */
5716 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5717 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5718 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5719 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5720 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5721 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5722 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5723 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5724 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
5725 /* gap */
5726 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5727 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5728 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5729 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5730 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5731 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5732 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5733 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5734 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5735 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5736 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5737 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5738 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5739 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5740 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5741 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5742 /* gap */
5743 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5744 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5745 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5746 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5747 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
5748 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
5749 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
5750 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
5751 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5752 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5753 /* gap */
5754 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5755 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5756 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5757 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5758 /* gap */
5759 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5760 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
5761 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5762 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5763 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5764 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5765 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5766 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
5767 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5768 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
5769 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5770 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5771 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5772 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5773 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5774 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5775 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5776 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5777 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5778 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5779 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
5780 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5781 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
5782 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5783 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5784 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5785 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5786 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5787 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5788 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5789 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5790 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5791 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5792 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5793 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5794 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5795 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5796 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5797 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5798 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
5799 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5800 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5801 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5802 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5803 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5804 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5805 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5806 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5807 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
5808 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
5809 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
5810 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
5811 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
5812 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5813 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
5814 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5815 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5816 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
5817 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
5818 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
5819 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5820 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5821 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
5822 };
5823
5824 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
5825 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
5826 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
5827 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
5828 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
5829 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
5830 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
5831 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
5832 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
5833 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
5834 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
5835 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
5836 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
5837 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
5838 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
5839 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
5840 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
5841 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
5842 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
5843 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
5844 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
5845 /* gap */
5846 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
5847 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
5848 /* gap */
5849 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
5850 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
5851 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
5852 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
5853 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
5854 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
5855 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
5856 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
5857 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
5858 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
5859 /* gap */
5860 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
5861 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
5862 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
5863 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
5864 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
5865 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
5866 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
5867 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
5868 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5869 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5870 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5871 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5872 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5873 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
5874 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
5875 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
5876 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
5877 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
5878 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
5879 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
5880 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
5881 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
5882 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
5883 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
5884 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
5885 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
5886 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
5887 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
5888 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
5889 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
5890 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
5891 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
5892 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
5893 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
5894 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
5895 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
5896 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
5897 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
5898 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
5899 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
5900 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
5901 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
5902 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
5903 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
5904 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
5905 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
5906 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
5907 /* gap */
5908 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
5909 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
5910 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
5911 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
5912 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
5913 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
5914 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
5915 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
5916 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
5917 /* gap */
5918 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
5919 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
5920 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
5921 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
5922 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
5923 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5924 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
5925 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5926 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
5927 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
5928 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
5929 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
5930 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5931 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
5932 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
5933 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
5934 /* gap */
5935 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
5936 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
5937 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
5938 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
5939 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
5940 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
5941 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
5942 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
5943 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
5944 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
5945 /* gap */
5946 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
5947 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
5948 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
5949 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
5950 /* gap */
5951 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
5952 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
5953 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
5954 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
5955 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
5956 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
5957 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
5958 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
5959 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
5960 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
5961 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
5962 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
5963 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
5964 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
5965 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
5966 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
5967 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
5968 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
5969 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
5970 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
5971 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
5972 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
5973 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
5974 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5975 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
5976 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
5977 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
5978 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
5979 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
5980 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
5981 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
5982 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
5983 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
5984 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
5985 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
5986 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
5987 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
5988 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
5989 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
5990 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
5991 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
5992 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
5993 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
5994 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
5995 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
5996 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5997 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5998 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
5999 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6000 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6001 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6002 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6003 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6004 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6005 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6006 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6007 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6008 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6009 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6010 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6011 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6012 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6013 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6014 };
6015
6016 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6017 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6018 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6019 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6020 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6021 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6022 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6023 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6024 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6025 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6026 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6027 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6028 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6029 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6030 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6031 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6032 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6033 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6034 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6035 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6036 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6037 /* gap */
6038 {20, 0, ALU_OP0_NOP, tgsi_unsupported},
6039 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6040 /* gap */
6041 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6042 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6043 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6044 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6045 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6046 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6047 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6048 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6049 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6050 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6051 /* gap */
6052 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6053 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6054 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6055 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6056 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6057 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6058 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6059 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6060 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6061 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6062 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6063 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6064 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6065 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6066 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6067 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6068 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6069 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6070 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6071 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6072 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6073 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6074 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6075 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6076 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6077 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6078 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6079 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6080 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6081 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6082 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6083 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6084 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6085 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6086 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6087 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6088 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6089 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6090 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6091 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6092 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6093 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6094 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6095 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6096 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6097 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6098 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6099 /* gap */
6100 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6101 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6102 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6103 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6104 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6105 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6106 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6107 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6108 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6109 /* gap */
6110 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6111 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6112 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6113 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6114 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6115 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6116 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6117 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6118 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6119 {TGSI_OPCODE_EMIT, 0, ALU_OP0_NOP, tgsi_unsupported},
6120 {TGSI_OPCODE_ENDPRIM, 0, ALU_OP0_NOP, tgsi_unsupported},
6121 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6122 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6123 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6124 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6125 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6126 /* gap */
6127 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6128 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6129 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6130 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6131 /* gap */
6132 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6133 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6134 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6135 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6136 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6137 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6138 /* gap */
6139 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6140 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6141 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6142 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6143 /* gap */
6144 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6145 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6146 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6147 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6148 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6149 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6150 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6151 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6152 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6153 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
6154 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
6155 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6156 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6157 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6158 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6159 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6160 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6161 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
6162 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6163 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6164 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6165 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6166 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6167 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6168 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6169 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6170 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6171 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6172 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6173 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6174 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6175 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6176 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6177 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6178 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6179 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6180 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6181 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6182 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6183 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6184 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6185 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6186 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6187 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6188 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6189 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6190 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6191 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6192 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6193 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6194 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6195 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6196 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6197 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6198 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6199 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6200 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6201 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6202 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6203 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6204 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6205 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6206 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6207 };