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broadcom/vc5: Increase simulator memory for tex-miplevel-selection.
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193
194 /* disable SB for shaders using doubles */
195 use_sb &= !shader->shader.uses_doubles;
196
197 use_sb &= !shader->shader.uses_atomics;
198 use_sb &= !shader->shader.uses_images;
199
200 /* Check if the bytecode has already been built. */
201 if (!shader->shader.bc.bytecode) {
202 r = r600_bytecode_build(&shader->shader.bc);
203 if (r) {
204 R600_ERR("building bytecode failed !\n");
205 goto error;
206 }
207 }
208
209 if (dump && !sb_disasm) {
210 fprintf(stderr, "--------------------------------------------------------------\n");
211 r600_bytecode_disasm(&shader->shader.bc);
212 fprintf(stderr, "______________________________________________________________\n");
213 } else if ((dump && sb_disasm) || use_sb) {
214 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
215 dump, use_sb);
216 if (r) {
217 R600_ERR("r600_sb_bytecode_process failed !\n");
218 goto error;
219 }
220 }
221
222 if (shader->gs_copy_shader) {
223 if (dump) {
224 // dump copy shader
225 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
226 &shader->gs_copy_shader->shader, dump, 0);
227 if (r)
228 goto error;
229 }
230
231 if ((r = store_shader(ctx, shader->gs_copy_shader)))
232 goto error;
233 }
234
235 /* Store the shader in a buffer. */
236 if ((r = store_shader(ctx, shader)))
237 goto error;
238
239 /* Build state. */
240 switch (shader->shader.processor_type) {
241 case PIPE_SHADER_TESS_CTRL:
242 evergreen_update_hs_state(ctx, shader);
243 break;
244 case PIPE_SHADER_TESS_EVAL:
245 if (key.tes.as_es)
246 evergreen_update_es_state(ctx, shader);
247 else
248 evergreen_update_vs_state(ctx, shader);
249 break;
250 case PIPE_SHADER_GEOMETRY:
251 if (rctx->b.chip_class >= EVERGREEN) {
252 evergreen_update_gs_state(ctx, shader);
253 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
254 } else {
255 r600_update_gs_state(ctx, shader);
256 r600_update_vs_state(ctx, shader->gs_copy_shader);
257 }
258 break;
259 case PIPE_SHADER_VERTEX:
260 export_shader = key.vs.as_es;
261 if (rctx->b.chip_class >= EVERGREEN) {
262 if (key.vs.as_ls)
263 evergreen_update_ls_state(ctx, shader);
264 else if (key.vs.as_es)
265 evergreen_update_es_state(ctx, shader);
266 else
267 evergreen_update_vs_state(ctx, shader);
268 } else {
269 if (export_shader)
270 r600_update_es_state(ctx, shader);
271 else
272 r600_update_vs_state(ctx, shader);
273 }
274 break;
275 case PIPE_SHADER_FRAGMENT:
276 if (rctx->b.chip_class >= EVERGREEN) {
277 evergreen_update_ps_state(ctx, shader);
278 } else {
279 r600_update_ps_state(ctx, shader);
280 }
281 break;
282 default:
283 r = -EINVAL;
284 goto error;
285 }
286 return 0;
287
288 error:
289 r600_pipe_shader_destroy(ctx, shader);
290 return r;
291 }
292
293 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
294 {
295 r600_resource_reference(&shader->bo, NULL);
296 r600_bytecode_clear(&shader->shader.bc);
297 r600_release_command_buffer(&shader->command_buffer);
298 }
299
300 /*
301 * tgsi -> r600 shader
302 */
303 struct r600_shader_tgsi_instruction;
304
305 struct r600_shader_src {
306 unsigned sel;
307 unsigned swizzle[4];
308 unsigned neg;
309 unsigned abs;
310 unsigned rel;
311 unsigned kc_bank;
312 boolean kc_rel; /* true if cache bank is indexed */
313 uint32_t value[4];
314 };
315
316 struct eg_interp {
317 boolean enabled;
318 unsigned ij_index;
319 };
320
321 struct r600_shader_ctx {
322 struct tgsi_shader_info info;
323 struct tgsi_parse_context parse;
324 const struct tgsi_token *tokens;
325 unsigned type;
326 unsigned file_offset[TGSI_FILE_COUNT];
327 unsigned temp_reg;
328 const struct r600_shader_tgsi_instruction *inst_info;
329 struct r600_bytecode *bc;
330 struct r600_shader *shader;
331 struct r600_shader_src src[4];
332 uint32_t *literals;
333 uint32_t nliterals;
334 uint32_t max_driver_temp_used;
335 /* needed for evergreen interpolation */
336 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
337 /* evergreen/cayman also store sample mask in face register */
338 int face_gpr;
339 /* sample id is .w component stored in fixed point position register */
340 int fixed_pt_position_gpr;
341 int colors_used;
342 boolean clip_vertex_write;
343 unsigned cv_output;
344 unsigned edgeflag_output;
345 int fragcoord_input;
346 int native_integers;
347 int next_ring_offset;
348 int gs_out_ring_offset;
349 int gs_next_vertex;
350 struct r600_shader *gs_for_vs;
351 int gs_export_gpr_tregs[4];
352 int gs_rotated_input[2];
353 const struct pipe_stream_output_info *gs_stream_output_info;
354 unsigned enabled_stream_buffers_mask;
355 unsigned tess_input_info; /* temp with tess input offsets */
356 unsigned tess_output_info; /* temp with tess input offsets */
357 unsigned thread_id_gpr; /* temp with thread id calculated for images */
358 };
359
360 struct r600_shader_tgsi_instruction {
361 unsigned op;
362 int (*process)(struct r600_shader_ctx *ctx);
363 };
364
365 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
366 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
367 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
368 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
369 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
370 static int tgsi_else(struct r600_shader_ctx *ctx);
371 static int tgsi_endif(struct r600_shader_ctx *ctx);
372 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
373 static int tgsi_endloop(struct r600_shader_ctx *ctx);
374 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
375 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
376 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
377 unsigned int dst_reg);
378 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
379 const struct r600_shader_src *shader_src,
380 unsigned chan);
381 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
382 unsigned dst_reg);
383
384 static int tgsi_last_instruction(unsigned writemask)
385 {
386 int i, lasti = 0;
387
388 for (i = 0; i < 4; i++) {
389 if (writemask & (1 << i)) {
390 lasti = i;
391 }
392 }
393 return lasti;
394 }
395
396 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
397 {
398 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
399 unsigned j;
400
401 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
402 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
403 return -EINVAL;
404 }
405 #if 0
406 if (i->Instruction.Label) {
407 R600_ERR("label unsupported\n");
408 return -EINVAL;
409 }
410 #endif
411 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
412 if (i->Src[j].Register.Dimension) {
413 switch (i->Src[j].Register.File) {
414 case TGSI_FILE_CONSTANT:
415 case TGSI_FILE_HW_ATOMIC:
416 break;
417 case TGSI_FILE_INPUT:
418 if (ctx->type == PIPE_SHADER_GEOMETRY ||
419 ctx->type == PIPE_SHADER_TESS_CTRL ||
420 ctx->type == PIPE_SHADER_TESS_EVAL)
421 break;
422 case TGSI_FILE_OUTPUT:
423 if (ctx->type == PIPE_SHADER_TESS_CTRL)
424 break;
425 default:
426 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
427 i->Src[j].Register.File,
428 i->Src[j].Register.Dimension);
429 return -EINVAL;
430 }
431 }
432 }
433 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
434 if (i->Dst[j].Register.Dimension) {
435 if (ctx->type == PIPE_SHADER_TESS_CTRL)
436 continue;
437 R600_ERR("unsupported dst (dimension)\n");
438 return -EINVAL;
439 }
440 }
441 return 0;
442 }
443
444 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
445 {
446 if (interpolate == TGSI_INTERPOLATE_COLOR ||
447 interpolate == TGSI_INTERPOLATE_LINEAR ||
448 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
449 {
450 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
451 int loc;
452
453 switch(location) {
454 case TGSI_INTERPOLATE_LOC_CENTER:
455 loc = 1;
456 break;
457 case TGSI_INTERPOLATE_LOC_CENTROID:
458 loc = 2;
459 break;
460 case TGSI_INTERPOLATE_LOC_SAMPLE:
461 default:
462 loc = 0; break;
463 }
464
465 return is_linear * 3 + loc;
466 }
467
468 return -1;
469 }
470
471 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
472 int input)
473 {
474 int i = eg_get_interpolator_index(
475 ctx->shader->input[input].interpolate,
476 ctx->shader->input[input].interpolate_location);
477 assert(i >= 0);
478 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
479 }
480
481 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
482 {
483 int i, r;
484 struct r600_bytecode_alu alu;
485 int gpr = 0, base_chan = 0;
486 int ij_index = ctx->shader->input[input].ij_index;
487
488 /* work out gpr and base_chan from index */
489 gpr = ij_index / 2;
490 base_chan = (2 * (ij_index % 2)) + 1;
491
492 for (i = 0; i < 8; i++) {
493 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
494
495 if (i < 4)
496 alu.op = ALU_OP2_INTERP_ZW;
497 else
498 alu.op = ALU_OP2_INTERP_XY;
499
500 if ((i > 1) && (i < 6)) {
501 alu.dst.sel = ctx->shader->input[input].gpr;
502 alu.dst.write = 1;
503 }
504
505 alu.dst.chan = i % 4;
506
507 alu.src[0].sel = gpr;
508 alu.src[0].chan = (base_chan - (i % 2));
509
510 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
511
512 alu.bank_swizzle_force = SQ_ALU_VEC_210;
513 if ((i % 4) == 3)
514 alu.last = 1;
515 r = r600_bytecode_add_alu(ctx->bc, &alu);
516 if (r)
517 return r;
518 }
519 return 0;
520 }
521
522 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
523 {
524 int i, r;
525 struct r600_bytecode_alu alu;
526
527 for (i = 0; i < 4; i++) {
528 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
529
530 alu.op = ALU_OP1_INTERP_LOAD_P0;
531
532 alu.dst.sel = ctx->shader->input[input].gpr;
533 alu.dst.write = 1;
534
535 alu.dst.chan = i;
536
537 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
538 alu.src[0].chan = i;
539
540 if (i == 3)
541 alu.last = 1;
542 r = r600_bytecode_add_alu(ctx->bc, &alu);
543 if (r)
544 return r;
545 }
546 return 0;
547 }
548
549 /*
550 * Special export handling in shaders
551 *
552 * shader export ARRAY_BASE for EXPORT_POS:
553 * 60 is position
554 * 61 is misc vector
555 * 62, 63 are clip distance vectors
556 *
557 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
558 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
559 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
560 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
561 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
562 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
563 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
564 * exclusive from render target index)
565 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
566 *
567 *
568 * shader export ARRAY_BASE for EXPORT_PIXEL:
569 * 0-7 CB targets
570 * 61 computed Z vector
571 *
572 * The use of the values exported in the computed Z vector are controlled
573 * by DB_SHADER_CONTROL:
574 * Z_EXPORT_ENABLE - Z as a float in RED
575 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
576 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
577 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
578 * DB_SOURCE_FORMAT - export control restrictions
579 *
580 */
581
582
583 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
584 static int r600_spi_sid(struct r600_shader_io * io)
585 {
586 int index, name = io->name;
587
588 /* These params are handled differently, they don't need
589 * semantic indices, so we'll use 0 for them.
590 */
591 if (name == TGSI_SEMANTIC_POSITION ||
592 name == TGSI_SEMANTIC_PSIZE ||
593 name == TGSI_SEMANTIC_EDGEFLAG ||
594 name == TGSI_SEMANTIC_FACE ||
595 name == TGSI_SEMANTIC_SAMPLEMASK)
596 index = 0;
597 else {
598 if (name == TGSI_SEMANTIC_GENERIC) {
599 /* For generic params simply use sid from tgsi */
600 index = io->sid;
601 } else {
602 /* For non-generic params - pack name and sid into 8 bits */
603 index = 0x80 | (name<<3) | (io->sid);
604 }
605
606 /* Make sure that all really used indices have nonzero value, so
607 * we can just compare it to 0 later instead of comparing the name
608 * with different values to detect special cases. */
609 index++;
610 }
611
612 return index;
613 };
614
615 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
616 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
617 {
618 switch (semantic_name) {
619 case TGSI_SEMANTIC_POSITION:
620 return 0;
621 case TGSI_SEMANTIC_PSIZE:
622 return 1;
623 case TGSI_SEMANTIC_CLIPDIST:
624 assert(index <= 1);
625 return 2 + index;
626 case TGSI_SEMANTIC_GENERIC:
627 if (index <= 63-4)
628 return 4 + index - 9;
629 else
630 /* same explanation as in the default statement,
631 * the only user hitting this is st/nine.
632 */
633 return 0;
634
635 /* patch indices are completely separate and thus start from 0 */
636 case TGSI_SEMANTIC_TESSOUTER:
637 return 0;
638 case TGSI_SEMANTIC_TESSINNER:
639 return 1;
640 case TGSI_SEMANTIC_PATCH:
641 return 2 + index;
642
643 default:
644 /* Don't fail here. The result of this function is only used
645 * for LS, TCS, TES, and GS, where legacy GL semantics can't
646 * occur, but this function is called for all vertex shaders
647 * before it's known whether LS will be compiled or not.
648 */
649 return 0;
650 }
651 }
652
653 /* turn input into interpolate on EG */
654 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
655 {
656 int r = 0;
657
658 if (ctx->shader->input[index].spi_sid) {
659 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
660 if (ctx->shader->input[index].interpolate > 0) {
661 evergreen_interp_assign_ij_index(ctx, index);
662 r = evergreen_interp_alu(ctx, index);
663 } else {
664 r = evergreen_interp_flat(ctx, index);
665 }
666 }
667 return r;
668 }
669
670 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
671 {
672 struct r600_bytecode_alu alu;
673 int i, r;
674 int gpr_front = ctx->shader->input[front].gpr;
675 int gpr_back = ctx->shader->input[back].gpr;
676
677 for (i = 0; i < 4; i++) {
678 memset(&alu, 0, sizeof(alu));
679 alu.op = ALU_OP3_CNDGT;
680 alu.is_op3 = 1;
681 alu.dst.write = 1;
682 alu.dst.sel = gpr_front;
683 alu.src[0].sel = ctx->face_gpr;
684 alu.src[1].sel = gpr_front;
685 alu.src[2].sel = gpr_back;
686
687 alu.dst.chan = i;
688 alu.src[1].chan = i;
689 alu.src[2].chan = i;
690 alu.last = (i==3);
691
692 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
693 return r;
694 }
695
696 return 0;
697 }
698
699 /* execute a single slot ALU calculation */
700 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
701 int dst_sel, int dst_chan,
702 int src0_sel, unsigned src0_chan_val,
703 int src1_sel, unsigned src1_chan_val)
704 {
705 struct r600_bytecode_alu alu;
706 int r, i;
707
708 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
709 for (i = 0; i < 4; i++) {
710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
711 alu.op = op;
712 alu.src[0].sel = src0_sel;
713 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
714 alu.src[0].value = src0_chan_val;
715 else
716 alu.src[0].chan = src0_chan_val;
717 alu.src[1].sel = src1_sel;
718 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
719 alu.src[1].value = src1_chan_val;
720 else
721 alu.src[1].chan = src1_chan_val;
722 alu.dst.sel = dst_sel;
723 alu.dst.chan = i;
724 alu.dst.write = i == dst_chan;
725 alu.last = (i == 3);
726 r = r600_bytecode_add_alu(ctx->bc, &alu);
727 if (r)
728 return r;
729 }
730 return 0;
731 }
732
733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
734 alu.op = op;
735 alu.src[0].sel = src0_sel;
736 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
737 alu.src[0].value = src0_chan_val;
738 else
739 alu.src[0].chan = src0_chan_val;
740 alu.src[1].sel = src1_sel;
741 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
742 alu.src[1].value = src1_chan_val;
743 else
744 alu.src[1].chan = src1_chan_val;
745 alu.dst.sel = dst_sel;
746 alu.dst.chan = dst_chan;
747 alu.dst.write = 1;
748 alu.last = 1;
749 r = r600_bytecode_add_alu(ctx->bc, &alu);
750 if (r)
751 return r;
752 return 0;
753 }
754
755 /* execute a single slot ALU calculation */
756 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
757 int dst_sel, int dst_chan,
758 int src0_sel, unsigned src0_chan_val,
759 int src1_sel, unsigned src1_chan_val,
760 int src2_sel, unsigned src2_chan_val)
761 {
762 struct r600_bytecode_alu alu;
763 int r;
764
765 /* validate this for other ops */
766 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
767 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
768 alu.op = op;
769 alu.src[0].sel = src0_sel;
770 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
771 alu.src[0].value = src0_chan_val;
772 else
773 alu.src[0].chan = src0_chan_val;
774 alu.src[1].sel = src1_sel;
775 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
776 alu.src[1].value = src1_chan_val;
777 else
778 alu.src[1].chan = src1_chan_val;
779 alu.src[2].sel = src2_sel;
780 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
781 alu.src[2].value = src2_chan_val;
782 else
783 alu.src[2].chan = src2_chan_val;
784 alu.dst.sel = dst_sel;
785 alu.dst.chan = dst_chan;
786 alu.is_op3 = 1;
787 alu.last = 1;
788 r = r600_bytecode_add_alu(ctx->bc, &alu);
789 if (r)
790 return r;
791 return 0;
792 }
793
794 /* put it in temp_reg.x */
795 static int get_lds_offset0(struct r600_shader_ctx *ctx,
796 int rel_patch_chan,
797 int temp_reg, bool is_patch_var)
798 {
799 int r;
800
801 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
802 /* ADD
803 Dimension - patch0_offset (input_vals.z),
804 Non-dim - patch0_data_offset (input_vals.w)
805 */
806 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
807 temp_reg, 0,
808 ctx->tess_output_info, 0,
809 0, rel_patch_chan,
810 ctx->tess_output_info, is_patch_var ? 3 : 2);
811 if (r)
812 return r;
813 return 0;
814 }
815
816 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
817 {
818 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
819 }
820
821 static int r600_get_temp(struct r600_shader_ctx *ctx)
822 {
823 return ctx->temp_reg + ctx->max_driver_temp_used++;
824 }
825
826 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
827 {
828 int i;
829 i = ctx->shader->noutput++;
830 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
831 ctx->shader->output[i].sid = 0;
832 ctx->shader->output[i].gpr = 0;
833 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
834 ctx->shader->output[i].write_mask = 0x4;
835 ctx->shader->output[i].spi_sid = prim_id_sid;
836
837 return 0;
838 }
839
840 static int tgsi_barrier(struct r600_shader_ctx *ctx)
841 {
842 struct r600_bytecode_alu alu;
843 int r;
844
845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
846 alu.op = ctx->inst_info->op;
847 alu.last = 1;
848
849 r = r600_bytecode_add_alu(ctx->bc, &alu);
850 if (r)
851 return r;
852 return 0;
853 }
854
855 static int tgsi_declaration(struct r600_shader_ctx *ctx)
856 {
857 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
858 int r, i, j, count = d->Range.Last - d->Range.First + 1;
859
860 switch (d->Declaration.File) {
861 case TGSI_FILE_INPUT:
862 for (j = 0; j < count; j++) {
863 i = ctx->shader->ninput + j;
864 assert(i < ARRAY_SIZE(ctx->shader->input));
865 ctx->shader->input[i].name = d->Semantic.Name;
866 ctx->shader->input[i].sid = d->Semantic.Index + j;
867 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
868 ctx->shader->input[i].interpolate_location = d->Interp.Location;
869 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
870 if (ctx->type == PIPE_SHADER_FRAGMENT) {
871 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
872 switch (ctx->shader->input[i].name) {
873 case TGSI_SEMANTIC_FACE:
874 if (ctx->face_gpr != -1)
875 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
876 else
877 ctx->face_gpr = ctx->shader->input[i].gpr;
878 break;
879 case TGSI_SEMANTIC_COLOR:
880 ctx->colors_used++;
881 break;
882 case TGSI_SEMANTIC_POSITION:
883 ctx->fragcoord_input = i;
884 break;
885 case TGSI_SEMANTIC_PRIMID:
886 /* set this for now */
887 ctx->shader->gs_prim_id_input = true;
888 ctx->shader->ps_prim_id_input = i;
889 break;
890 }
891 if (ctx->bc->chip_class >= EVERGREEN) {
892 if ((r = evergreen_interp_input(ctx, i)))
893 return r;
894 }
895 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
896 /* FIXME probably skip inputs if they aren't passed in the ring */
897 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
898 ctx->next_ring_offset += 16;
899 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
900 ctx->shader->gs_prim_id_input = true;
901 }
902 }
903 ctx->shader->ninput += count;
904 break;
905 case TGSI_FILE_OUTPUT:
906 for (j = 0; j < count; j++) {
907 i = ctx->shader->noutput + j;
908 assert(i < ARRAY_SIZE(ctx->shader->output));
909 ctx->shader->output[i].name = d->Semantic.Name;
910 ctx->shader->output[i].sid = d->Semantic.Index + j;
911 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
912 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
913 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
914 if (ctx->type == PIPE_SHADER_VERTEX ||
915 ctx->type == PIPE_SHADER_GEOMETRY ||
916 ctx->type == PIPE_SHADER_TESS_EVAL) {
917 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
918 switch (d->Semantic.Name) {
919 case TGSI_SEMANTIC_CLIPDIST:
920 ctx->shader->clip_dist_write |= d->Declaration.UsageMask <<
921 ((d->Semantic.Index + j) << 2);
922 break;
923 case TGSI_SEMANTIC_PSIZE:
924 ctx->shader->vs_out_misc_write = 1;
925 ctx->shader->vs_out_point_size = 1;
926 break;
927 case TGSI_SEMANTIC_EDGEFLAG:
928 ctx->shader->vs_out_misc_write = 1;
929 ctx->shader->vs_out_edgeflag = 1;
930 ctx->edgeflag_output = i;
931 break;
932 case TGSI_SEMANTIC_VIEWPORT_INDEX:
933 ctx->shader->vs_out_misc_write = 1;
934 ctx->shader->vs_out_viewport = 1;
935 break;
936 case TGSI_SEMANTIC_LAYER:
937 ctx->shader->vs_out_misc_write = 1;
938 ctx->shader->vs_out_layer = 1;
939 break;
940 case TGSI_SEMANTIC_CLIPVERTEX:
941 ctx->clip_vertex_write = TRUE;
942 ctx->cv_output = i;
943 break;
944 }
945 if (ctx->type == PIPE_SHADER_GEOMETRY) {
946 ctx->gs_out_ring_offset += 16;
947 }
948 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
949 switch (d->Semantic.Name) {
950 case TGSI_SEMANTIC_COLOR:
951 ctx->shader->nr_ps_max_color_exports++;
952 break;
953 }
954 }
955 }
956 ctx->shader->noutput += count;
957 break;
958 case TGSI_FILE_TEMPORARY:
959 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
960 if (d->Array.ArrayID) {
961 r600_add_gpr_array(ctx->shader,
962 ctx->file_offset[TGSI_FILE_TEMPORARY] +
963 d->Range.First,
964 d->Range.Last - d->Range.First + 1, 0x0F);
965 }
966 }
967 break;
968
969 case TGSI_FILE_CONSTANT:
970 case TGSI_FILE_SAMPLER:
971 case TGSI_FILE_SAMPLER_VIEW:
972 case TGSI_FILE_ADDRESS:
973 case TGSI_FILE_IMAGE:
974 break;
975
976 case TGSI_FILE_HW_ATOMIC:
977 i = ctx->shader->nhwatomic_ranges;
978 ctx->shader->atomics[i].start = d->Range.First;
979 ctx->shader->atomics[i].end = d->Range.Last;
980 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
981 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
982 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
983 ctx->shader->nhwatomic_ranges++;
984 ctx->shader->nhwatomic += count;
985 break;
986
987 case TGSI_FILE_SYSTEM_VALUE:
988 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
989 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
990 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
991 break; /* Already handled from allocate_system_value_inputs */
992 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
993 if (!ctx->native_integers) {
994 struct r600_bytecode_alu alu;
995 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
996
997 alu.op = ALU_OP1_INT_TO_FLT;
998 alu.src[0].sel = 0;
999 alu.src[0].chan = 3;
1000
1001 alu.dst.sel = 0;
1002 alu.dst.chan = 3;
1003 alu.dst.write = 1;
1004 alu.last = 1;
1005
1006 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1007 return r;
1008 }
1009 break;
1010 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1011 break;
1012 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1013 break;
1014 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1015 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1016 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1017 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1018 unsigned temp_reg = r600_get_temp(ctx);
1019
1020 r = get_lds_offset0(ctx, 2, temp_reg, true);
1021 if (r)
1022 return r;
1023
1024 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1025 temp_reg, 0,
1026 temp_reg, 0,
1027 V_SQ_ALU_SRC_LITERAL, param * 16);
1028 if (r)
1029 return r;
1030
1031 do_lds_fetch_values(ctx, temp_reg, dreg);
1032 }
1033 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1034 /* MOV r1.x, r0.x;
1035 MOV r1.y, r0.y;
1036 */
1037 for (i = 0; i < 2; i++) {
1038 struct r600_bytecode_alu alu;
1039 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1040 alu.op = ALU_OP1_MOV;
1041 alu.src[0].sel = 0;
1042 alu.src[0].chan = 0 + i;
1043 alu.dst.sel = 1;
1044 alu.dst.chan = 0 + i;
1045 alu.dst.write = 1;
1046 alu.last = (i == 1) ? 1 : 0;
1047 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1048 return r;
1049 }
1050 /* ADD r1.z, 1.0f, -r0.x */
1051 struct r600_bytecode_alu alu;
1052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1053 alu.op = ALU_OP2_ADD;
1054 alu.src[0].sel = V_SQ_ALU_SRC_1;
1055 alu.src[1].sel = 1;
1056 alu.src[1].chan = 0;
1057 alu.src[1].neg = 1;
1058 alu.dst.sel = 1;
1059 alu.dst.chan = 2;
1060 alu.dst.write = 1;
1061 alu.last = 1;
1062 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1063 return r;
1064
1065 /* ADD r1.z, r1.z, -r1.y */
1066 alu.op = ALU_OP2_ADD;
1067 alu.src[0].sel = 1;
1068 alu.src[0].chan = 2;
1069 alu.src[1].sel = 1;
1070 alu.src[1].chan = 1;
1071 alu.src[1].neg = 1;
1072 alu.dst.sel = 1;
1073 alu.dst.chan = 2;
1074 alu.dst.write = 1;
1075 alu.last = 1;
1076 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1077 return r;
1078 break;
1079 }
1080 break;
1081 default:
1082 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1083 return -EINVAL;
1084 }
1085 return 0;
1086 }
1087
1088 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1089 {
1090 struct tgsi_parse_context parse;
1091 struct {
1092 boolean enabled;
1093 int *reg;
1094 unsigned name, alternate_name;
1095 } inputs[2] = {
1096 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1097
1098 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1099 };
1100 int i, k, num_regs = 0;
1101
1102 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1103 return 0;
1104 }
1105
1106 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1107 while (!tgsi_parse_end_of_tokens(&parse)) {
1108 tgsi_parse_token(&parse);
1109
1110 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1111 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1112 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1113 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1114 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1115 {
1116 int interpolate, location, k;
1117
1118 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1119 location = TGSI_INTERPOLATE_LOC_CENTER;
1120 inputs[1].enabled = true; /* needs SAMPLEID */
1121 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1122 location = TGSI_INTERPOLATE_LOC_CENTER;
1123 /* Needs sample positions, currently those are always available */
1124 } else {
1125 location = TGSI_INTERPOLATE_LOC_CENTROID;
1126 }
1127
1128 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1129 k = eg_get_interpolator_index(interpolate, location);
1130 if (k >= 0)
1131 ctx->eg_interpolators[k].enabled = true;
1132 }
1133 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1134 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1135 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1136 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1137 if (d->Semantic.Name == inputs[k].name ||
1138 d->Semantic.Name == inputs[k].alternate_name) {
1139 inputs[k].enabled = true;
1140 }
1141 }
1142 }
1143 }
1144 }
1145
1146 tgsi_parse_free(&parse);
1147
1148 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1149 boolean enabled = inputs[i].enabled;
1150 int *reg = inputs[i].reg;
1151 unsigned name = inputs[i].name;
1152
1153 if (enabled) {
1154 int gpr = gpr_offset + num_regs++;
1155 ctx->shader->nsys_inputs++;
1156
1157 // add to inputs, allocate a gpr
1158 k = ctx->shader->ninput++;
1159 ctx->shader->input[k].name = name;
1160 ctx->shader->input[k].sid = 0;
1161 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1162 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1163 *reg = ctx->shader->input[k].gpr = gpr;
1164 }
1165 }
1166
1167 return gpr_offset + num_regs;
1168 }
1169
1170 /*
1171 * for evergreen we need to scan the shader to find the number of GPRs we need to
1172 * reserve for interpolation and system values
1173 *
1174 * we need to know if we are going to emit
1175 * any sample or centroid inputs
1176 * if perspective and linear are required
1177 */
1178 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1179 {
1180 unsigned i;
1181 int num_baryc;
1182 struct tgsi_parse_context parse;
1183
1184 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1185
1186 for (i = 0; i < ctx->info.num_inputs; i++) {
1187 int k;
1188 /* skip position/face/mask/sampleid */
1189 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1190 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1191 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1192 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1193 continue;
1194
1195 k = eg_get_interpolator_index(
1196 ctx->info.input_interpolate[i],
1197 ctx->info.input_interpolate_loc[i]);
1198 if (k >= 0)
1199 ctx->eg_interpolators[k].enabled = TRUE;
1200 }
1201
1202 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1203 return 0;
1204 }
1205
1206 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1207 while (!tgsi_parse_end_of_tokens(&parse)) {
1208 tgsi_parse_token(&parse);
1209
1210 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1211 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1212 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1213 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1214 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1215 {
1216 int interpolate, location, k;
1217
1218 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1219 location = TGSI_INTERPOLATE_LOC_CENTER;
1220 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1221 location = TGSI_INTERPOLATE_LOC_CENTER;
1222 } else {
1223 location = TGSI_INTERPOLATE_LOC_CENTROID;
1224 }
1225
1226 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1227 k = eg_get_interpolator_index(interpolate, location);
1228 if (k >= 0)
1229 ctx->eg_interpolators[k].enabled = true;
1230 }
1231 }
1232 }
1233
1234 tgsi_parse_free(&parse);
1235
1236 /* assign gpr to each interpolator according to priority */
1237 num_baryc = 0;
1238 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1239 if (ctx->eg_interpolators[i].enabled) {
1240 ctx->eg_interpolators[i].ij_index = num_baryc;
1241 num_baryc ++;
1242 }
1243 }
1244
1245 /* XXX PULL MODEL and LINE STIPPLE */
1246
1247 num_baryc = (num_baryc + 1) >> 1;
1248 return allocate_system_value_inputs(ctx, num_baryc);
1249 }
1250
1251 /* sample_id_sel == NULL means fetch for current sample */
1252 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1253 {
1254 struct r600_bytecode_vtx vtx;
1255 int r, t1;
1256
1257 assert(ctx->fixed_pt_position_gpr != -1);
1258
1259 t1 = r600_get_temp(ctx);
1260
1261 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1262 vtx.op = FETCH_OP_VFETCH;
1263 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1264 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1265 if (sample_id == NULL) {
1266 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1267 vtx.src_sel_x = 3;
1268 }
1269 else {
1270 struct r600_bytecode_alu alu;
1271
1272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1273 alu.op = ALU_OP1_MOV;
1274 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1275 alu.dst.sel = t1;
1276 alu.dst.write = 1;
1277 alu.last = 1;
1278 r = r600_bytecode_add_alu(ctx->bc, &alu);
1279 if (r)
1280 return r;
1281
1282 vtx.src_gpr = t1;
1283 vtx.src_sel_x = 0;
1284 }
1285 vtx.mega_fetch_count = 16;
1286 vtx.dst_gpr = t1;
1287 vtx.dst_sel_x = 0;
1288 vtx.dst_sel_y = 1;
1289 vtx.dst_sel_z = 2;
1290 vtx.dst_sel_w = 3;
1291 vtx.data_format = FMT_32_32_32_32_FLOAT;
1292 vtx.num_format_all = 2;
1293 vtx.format_comp_all = 1;
1294 vtx.use_const_fields = 0;
1295 vtx.offset = 1; // first element is size of buffer
1296 vtx.endian = r600_endian_swap(32);
1297 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1298
1299 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1300 if (r)
1301 return r;
1302
1303 return t1;
1304 }
1305
1306 static void tgsi_src(struct r600_shader_ctx *ctx,
1307 const struct tgsi_full_src_register *tgsi_src,
1308 struct r600_shader_src *r600_src)
1309 {
1310 memset(r600_src, 0, sizeof(*r600_src));
1311 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1312 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1313 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1314 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1315 r600_src->neg = tgsi_src->Register.Negate;
1316 r600_src->abs = tgsi_src->Register.Absolute;
1317
1318 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1319 int index;
1320 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1321 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1322 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1323
1324 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1325 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1326 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1327 return;
1328 }
1329 index = tgsi_src->Register.Index;
1330 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1331 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1332 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1333 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1334 r600_src->swizzle[0] = 2; // Z value
1335 r600_src->swizzle[1] = 2;
1336 r600_src->swizzle[2] = 2;
1337 r600_src->swizzle[3] = 2;
1338 r600_src->sel = ctx->face_gpr;
1339 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1340 r600_src->swizzle[0] = 3; // W value
1341 r600_src->swizzle[1] = 3;
1342 r600_src->swizzle[2] = 3;
1343 r600_src->swizzle[3] = 3;
1344 r600_src->sel = ctx->fixed_pt_position_gpr;
1345 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1346 r600_src->swizzle[0] = 0;
1347 r600_src->swizzle[1] = 1;
1348 r600_src->swizzle[2] = 4;
1349 r600_src->swizzle[3] = 4;
1350 r600_src->sel = load_sample_position(ctx, NULL, -1);
1351 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1352 r600_src->swizzle[0] = 3;
1353 r600_src->swizzle[1] = 3;
1354 r600_src->swizzle[2] = 3;
1355 r600_src->swizzle[3] = 3;
1356 r600_src->sel = 0;
1357 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1358 r600_src->swizzle[0] = 0;
1359 r600_src->swizzle[1] = 0;
1360 r600_src->swizzle[2] = 0;
1361 r600_src->swizzle[3] = 0;
1362 r600_src->sel = 0;
1363 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1364 r600_src->swizzle[0] = 3;
1365 r600_src->swizzle[1] = 3;
1366 r600_src->swizzle[2] = 3;
1367 r600_src->swizzle[3] = 3;
1368 r600_src->sel = 1;
1369 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1370 r600_src->swizzle[0] = 2;
1371 r600_src->swizzle[1] = 2;
1372 r600_src->swizzle[2] = 2;
1373 r600_src->swizzle[3] = 2;
1374 r600_src->sel = 0;
1375 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1376 r600_src->sel = 1;
1377 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1378 r600_src->sel = 3;
1379 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1380 r600_src->sel = 2;
1381 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1382 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1383 r600_src->sel = ctx->tess_input_info;
1384 r600_src->swizzle[0] = 2;
1385 r600_src->swizzle[1] = 2;
1386 r600_src->swizzle[2] = 2;
1387 r600_src->swizzle[3] = 2;
1388 } else {
1389 r600_src->sel = ctx->tess_input_info;
1390 r600_src->swizzle[0] = 3;
1391 r600_src->swizzle[1] = 3;
1392 r600_src->swizzle[2] = 3;
1393 r600_src->swizzle[3] = 3;
1394 }
1395 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1396 r600_src->sel = 0;
1397 r600_src->swizzle[0] = 0;
1398 r600_src->swizzle[1] = 0;
1399 r600_src->swizzle[2] = 0;
1400 r600_src->swizzle[3] = 0;
1401 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1402 r600_src->sel = 0;
1403 r600_src->swizzle[0] = 3;
1404 r600_src->swizzle[1] = 3;
1405 r600_src->swizzle[2] = 3;
1406 r600_src->swizzle[3] = 3;
1407 }
1408 } else {
1409 if (tgsi_src->Register.Indirect)
1410 r600_src->rel = V_SQ_REL_RELATIVE;
1411 r600_src->sel = tgsi_src->Register.Index;
1412 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1413 }
1414 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1415 if (tgsi_src->Register.Dimension) {
1416 r600_src->kc_bank = tgsi_src->Dimension.Index;
1417 if (tgsi_src->Dimension.Indirect) {
1418 r600_src->kc_rel = 1;
1419 }
1420 }
1421 }
1422 }
1423
1424 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1425 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1426 unsigned int dst_reg)
1427 {
1428 struct r600_bytecode_vtx vtx;
1429 unsigned int ar_reg;
1430 int r;
1431
1432 if (offset) {
1433 struct r600_bytecode_alu alu;
1434
1435 memset(&alu, 0, sizeof(alu));
1436
1437 alu.op = ALU_OP2_ADD_INT;
1438 alu.src[0].sel = ctx->bc->ar_reg;
1439 alu.src[0].chan = ar_chan;
1440
1441 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1442 alu.src[1].value = offset;
1443
1444 alu.dst.sel = dst_reg;
1445 alu.dst.chan = ar_chan;
1446 alu.dst.write = 1;
1447 alu.last = 1;
1448
1449 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1450 return r;
1451
1452 ar_reg = dst_reg;
1453 } else {
1454 ar_reg = ctx->bc->ar_reg;
1455 }
1456
1457 memset(&vtx, 0, sizeof(vtx));
1458 vtx.buffer_id = cb_idx;
1459 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1460 vtx.src_gpr = ar_reg;
1461 vtx.src_sel_x = ar_chan;
1462 vtx.mega_fetch_count = 16;
1463 vtx.dst_gpr = dst_reg;
1464 vtx.dst_sel_x = 0; /* SEL_X */
1465 vtx.dst_sel_y = 1; /* SEL_Y */
1466 vtx.dst_sel_z = 2; /* SEL_Z */
1467 vtx.dst_sel_w = 3; /* SEL_W */
1468 vtx.data_format = FMT_32_32_32_32_FLOAT;
1469 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1470 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1471 vtx.endian = r600_endian_swap(32);
1472 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1473
1474 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1475 return r;
1476
1477 return 0;
1478 }
1479
1480 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1481 {
1482 struct r600_bytecode_vtx vtx;
1483 int r;
1484 unsigned index = src->Register.Index;
1485 unsigned vtx_id = src->Dimension.Index;
1486 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1487 int offset_chan = vtx_id % 3;
1488 int t2 = 0;
1489
1490 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1491 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1492
1493 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1494 offset_chan = 3;
1495
1496 if (src->Dimension.Indirect || src->Register.Indirect)
1497 t2 = r600_get_temp(ctx);
1498
1499 if (src->Dimension.Indirect) {
1500 int treg[3];
1501 struct r600_bytecode_alu alu;
1502 int r, i;
1503 unsigned addr_reg;
1504 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1505 if (src->DimIndirect.Index > 0) {
1506 r = single_alu_op2(ctx, ALU_OP1_MOV,
1507 ctx->bc->ar_reg, 0,
1508 addr_reg, 0,
1509 0, 0);
1510 if (r)
1511 return r;
1512 }
1513 /*
1514 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1515 at least this is what fglrx seems to do. */
1516 for (i = 0; i < 3; i++) {
1517 treg[i] = r600_get_temp(ctx);
1518 }
1519 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1520
1521 for (i = 0; i < 3; i++) {
1522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1523 alu.op = ALU_OP1_MOV;
1524 alu.src[0].sel = ctx->gs_rotated_input[0];
1525 alu.src[0].chan = i == 2 ? 3 : i;
1526 alu.dst.sel = treg[i];
1527 alu.dst.chan = 0;
1528 alu.dst.write = 1;
1529 alu.last = 1;
1530 r = r600_bytecode_add_alu(ctx->bc, &alu);
1531 if (r)
1532 return r;
1533 }
1534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1535 alu.op = ALU_OP1_MOV;
1536 alu.src[0].sel = treg[0];
1537 alu.src[0].rel = 1;
1538 alu.dst.sel = t2;
1539 alu.dst.write = 1;
1540 alu.last = 1;
1541 r = r600_bytecode_add_alu(ctx->bc, &alu);
1542 if (r)
1543 return r;
1544 offset_reg = t2;
1545 offset_chan = 0;
1546 }
1547
1548 if (src->Register.Indirect) {
1549 int addr_reg;
1550 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1551
1552 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1553
1554 /* pull the value from index_reg */
1555 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1556 t2, 1,
1557 addr_reg, 0,
1558 V_SQ_ALU_SRC_LITERAL, first);
1559 if (r)
1560 return r;
1561 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1562 t2, 0,
1563 t2, 1,
1564 V_SQ_ALU_SRC_LITERAL, 4,
1565 offset_reg, offset_chan);
1566 if (r)
1567 return r;
1568 offset_reg = t2;
1569 offset_chan = 0;
1570 index = src->Register.Index - first;
1571 }
1572
1573 memset(&vtx, 0, sizeof(vtx));
1574 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1575 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1576 vtx.src_gpr = offset_reg;
1577 vtx.src_sel_x = offset_chan;
1578 vtx.offset = index * 16; /*bytes*/
1579 vtx.mega_fetch_count = 16;
1580 vtx.dst_gpr = dst_reg;
1581 vtx.dst_sel_x = 0; /* SEL_X */
1582 vtx.dst_sel_y = 1; /* SEL_Y */
1583 vtx.dst_sel_z = 2; /* SEL_Z */
1584 vtx.dst_sel_w = 3; /* SEL_W */
1585 if (ctx->bc->chip_class >= EVERGREEN) {
1586 vtx.use_const_fields = 1;
1587 } else {
1588 vtx.data_format = FMT_32_32_32_32_FLOAT;
1589 }
1590
1591 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1592 return r;
1593
1594 return 0;
1595 }
1596
1597 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1598 {
1599 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1600 unsigned i;
1601
1602 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1603 struct tgsi_full_src_register *src = &inst->Src[i];
1604
1605 if (src->Register.File == TGSI_FILE_INPUT) {
1606 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1607 /* primitive id is in R0.z */
1608 ctx->src[i].sel = 0;
1609 ctx->src[i].swizzle[0] = 2;
1610 }
1611 }
1612 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1613 int treg = r600_get_temp(ctx);
1614
1615 fetch_gs_input(ctx, src, treg);
1616 ctx->src[i].sel = treg;
1617 ctx->src[i].rel = 0;
1618 }
1619 }
1620 return 0;
1621 }
1622
1623
1624 /* Tessellation shaders pass outputs to the next shader using LDS.
1625 *
1626 * LS outputs = TCS(HS) inputs
1627 * TCS(HS) outputs = TES(DS) inputs
1628 *
1629 * The LDS layout is:
1630 * - TCS inputs for patch 0
1631 * - TCS inputs for patch 1
1632 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1633 * - ...
1634 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1635 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1636 * - TCS outputs for patch 1
1637 * - Per-patch TCS outputs for patch 1
1638 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1639 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1640 * - ...
1641 *
1642 * All three shaders VS(LS), TCS, TES share the same LDS space.
1643 */
1644 /* this will return with the dw address in temp_reg.x */
1645 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1646 const struct tgsi_full_dst_register *dst,
1647 const struct tgsi_full_src_register *src,
1648 int stride_bytes_reg, int stride_bytes_chan)
1649 {
1650 struct tgsi_full_dst_register reg;
1651 ubyte *name, *index, *array_first;
1652 int r;
1653 int param;
1654 struct tgsi_shader_info *info = &ctx->info;
1655 /* Set the register description. The address computation is the same
1656 * for sources and destinations. */
1657 if (src) {
1658 reg.Register.File = src->Register.File;
1659 reg.Register.Index = src->Register.Index;
1660 reg.Register.Indirect = src->Register.Indirect;
1661 reg.Register.Dimension = src->Register.Dimension;
1662 reg.Indirect = src->Indirect;
1663 reg.Dimension = src->Dimension;
1664 reg.DimIndirect = src->DimIndirect;
1665 } else
1666 reg = *dst;
1667
1668 /* If the register is 2-dimensional (e.g. an array of vertices
1669 * in a primitive), calculate the base address of the vertex. */
1670 if (reg.Register.Dimension) {
1671 int sel, chan;
1672 if (reg.Dimension.Indirect) {
1673 unsigned addr_reg;
1674 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1675
1676 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1677 /* pull the value from index_reg */
1678 sel = addr_reg;
1679 chan = 0;
1680 } else {
1681 sel = V_SQ_ALU_SRC_LITERAL;
1682 chan = reg.Dimension.Index;
1683 }
1684
1685 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1686 temp_reg, 0,
1687 stride_bytes_reg, stride_bytes_chan,
1688 sel, chan,
1689 temp_reg, 0);
1690 if (r)
1691 return r;
1692 }
1693
1694 if (reg.Register.File == TGSI_FILE_INPUT) {
1695 name = info->input_semantic_name;
1696 index = info->input_semantic_index;
1697 array_first = info->input_array_first;
1698 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1699 name = info->output_semantic_name;
1700 index = info->output_semantic_index;
1701 array_first = info->output_array_first;
1702 } else {
1703 assert(0);
1704 return -1;
1705 }
1706 if (reg.Register.Indirect) {
1707 int addr_reg;
1708 int first;
1709 /* Add the relative address of the element. */
1710 if (reg.Indirect.ArrayID)
1711 first = array_first[reg.Indirect.ArrayID];
1712 else
1713 first = reg.Register.Index;
1714
1715 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1716
1717 /* pull the value from index_reg */
1718 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1719 temp_reg, 0,
1720 V_SQ_ALU_SRC_LITERAL, 16,
1721 addr_reg, 0,
1722 temp_reg, 0);
1723 if (r)
1724 return r;
1725
1726 param = r600_get_lds_unique_index(name[first],
1727 index[first]);
1728
1729 } else {
1730 param = r600_get_lds_unique_index(name[reg.Register.Index],
1731 index[reg.Register.Index]);
1732 }
1733
1734 /* add to base_addr - passed in temp_reg.x */
1735 if (param) {
1736 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1737 temp_reg, 0,
1738 temp_reg, 0,
1739 V_SQ_ALU_SRC_LITERAL, param * 16);
1740 if (r)
1741 return r;
1742
1743 }
1744 return 0;
1745 }
1746
1747 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1748 unsigned dst_reg)
1749 {
1750 struct r600_bytecode_alu alu;
1751 int r, i;
1752
1753 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1754 ctx->bc->force_add_cf = 1;
1755 for (i = 1; i < 4; i++) {
1756 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1757 temp_reg, i,
1758 temp_reg, 0,
1759 V_SQ_ALU_SRC_LITERAL, 4 * i);
1760 if (r)
1761 return r;
1762 }
1763 for (i = 0; i < 4; i++) {
1764 /* emit an LDS_READ_RET */
1765 memset(&alu, 0, sizeof(alu));
1766 alu.op = LDS_OP1_LDS_READ_RET;
1767 alu.src[0].sel = temp_reg;
1768 alu.src[0].chan = i;
1769 alu.src[1].sel = V_SQ_ALU_SRC_0;
1770 alu.src[2].sel = V_SQ_ALU_SRC_0;
1771 alu.dst.chan = 0;
1772 alu.is_lds_idx_op = true;
1773 alu.last = 1;
1774 r = r600_bytecode_add_alu(ctx->bc, &alu);
1775 if (r)
1776 return r;
1777 }
1778 for (i = 0; i < 4; i++) {
1779 /* then read from LDS_OQ_A_POP */
1780 memset(&alu, 0, sizeof(alu));
1781
1782 alu.op = ALU_OP1_MOV;
1783 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1784 alu.src[0].chan = 0;
1785 alu.dst.sel = dst_reg;
1786 alu.dst.chan = i;
1787 alu.dst.write = 1;
1788 alu.last = 1;
1789 r = r600_bytecode_add_alu(ctx->bc, &alu);
1790 if (r)
1791 return r;
1792 }
1793 return 0;
1794 }
1795
1796 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1797 {
1798 int r;
1799 unsigned temp_reg = r600_get_temp(ctx);
1800
1801 r = get_lds_offset0(ctx, 2, temp_reg,
1802 src->Register.Dimension ? false : true);
1803 if (r)
1804 return r;
1805
1806 /* the base address is now in temp.x */
1807 r = r600_get_byte_address(ctx, temp_reg,
1808 NULL, src, ctx->tess_output_info, 1);
1809 if (r)
1810 return r;
1811
1812 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1813 if (r)
1814 return r;
1815 return 0;
1816 }
1817
1818 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1819 {
1820 int r;
1821 unsigned temp_reg = r600_get_temp(ctx);
1822
1823 /* t.x = ips * r0.y */
1824 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1825 temp_reg, 0,
1826 ctx->tess_input_info, 0,
1827 0, 1);
1828
1829 if (r)
1830 return r;
1831
1832 /* the base address is now in temp.x */
1833 r = r600_get_byte_address(ctx, temp_reg,
1834 NULL, src, ctx->tess_input_info, 1);
1835 if (r)
1836 return r;
1837
1838 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1839 if (r)
1840 return r;
1841 return 0;
1842 }
1843
1844 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1845 {
1846 int r;
1847 unsigned temp_reg = r600_get_temp(ctx);
1848
1849 r = get_lds_offset0(ctx, 1, temp_reg,
1850 src->Register.Dimension ? false : true);
1851 if (r)
1852 return r;
1853 /* the base address is now in temp.x */
1854 r = r600_get_byte_address(ctx, temp_reg,
1855 NULL, src,
1856 ctx->tess_output_info, 1);
1857 if (r)
1858 return r;
1859
1860 r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
1861 if (r)
1862 return r;
1863 return 0;
1864 }
1865
1866 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1867 {
1868 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1869 unsigned i;
1870
1871 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1872 struct tgsi_full_src_register *src = &inst->Src[i];
1873
1874 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1875 int treg = r600_get_temp(ctx);
1876 fetch_tes_input(ctx, src, treg);
1877 ctx->src[i].sel = treg;
1878 ctx->src[i].rel = 0;
1879 }
1880 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1881 int treg = r600_get_temp(ctx);
1882 fetch_tcs_input(ctx, src, treg);
1883 ctx->src[i].sel = treg;
1884 ctx->src[i].rel = 0;
1885 }
1886 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1887 int treg = r600_get_temp(ctx);
1888 fetch_tcs_output(ctx, src, treg);
1889 ctx->src[i].sel = treg;
1890 ctx->src[i].rel = 0;
1891 }
1892 }
1893 return 0;
1894 }
1895
1896 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1897 {
1898 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1899 struct r600_bytecode_alu alu;
1900 int i, j, k, nconst, r;
1901
1902 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1903 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1904 nconst++;
1905 }
1906 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1907 }
1908 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1909 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1910 continue;
1911 }
1912
1913 if (ctx->src[i].rel) {
1914 int chan = inst->Src[i].Indirect.Swizzle;
1915 int treg = r600_get_temp(ctx);
1916 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1917 return r;
1918
1919 ctx->src[i].kc_bank = 0;
1920 ctx->src[i].kc_rel = 0;
1921 ctx->src[i].sel = treg;
1922 ctx->src[i].rel = 0;
1923 j--;
1924 } else if (j > 0) {
1925 int treg = r600_get_temp(ctx);
1926 for (k = 0; k < 4; k++) {
1927 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1928 alu.op = ALU_OP1_MOV;
1929 alu.src[0].sel = ctx->src[i].sel;
1930 alu.src[0].chan = k;
1931 alu.src[0].rel = ctx->src[i].rel;
1932 alu.src[0].kc_bank = ctx->src[i].kc_bank;
1933 alu.src[0].kc_rel = ctx->src[i].kc_rel;
1934 alu.dst.sel = treg;
1935 alu.dst.chan = k;
1936 alu.dst.write = 1;
1937 if (k == 3)
1938 alu.last = 1;
1939 r = r600_bytecode_add_alu(ctx->bc, &alu);
1940 if (r)
1941 return r;
1942 }
1943 ctx->src[i].sel = treg;
1944 ctx->src[i].rel =0;
1945 j--;
1946 }
1947 }
1948 return 0;
1949 }
1950
1951 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1952 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1953 {
1954 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1955 struct r600_bytecode_alu alu;
1956 int i, j, k, nliteral, r;
1957
1958 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1959 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1960 nliteral++;
1961 }
1962 }
1963 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1964 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1965 int treg = r600_get_temp(ctx);
1966 for (k = 0; k < 4; k++) {
1967 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1968 alu.op = ALU_OP1_MOV;
1969 alu.src[0].sel = ctx->src[i].sel;
1970 alu.src[0].chan = k;
1971 alu.src[0].value = ctx->src[i].value[k];
1972 alu.dst.sel = treg;
1973 alu.dst.chan = k;
1974 alu.dst.write = 1;
1975 if (k == 3)
1976 alu.last = 1;
1977 r = r600_bytecode_add_alu(ctx->bc, &alu);
1978 if (r)
1979 return r;
1980 }
1981 ctx->src[i].sel = treg;
1982 j--;
1983 }
1984 }
1985 return 0;
1986 }
1987
1988 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1989 {
1990 int i, r, count = ctx->shader->ninput;
1991
1992 for (i = 0; i < count; i++) {
1993 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1994 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1995 if (r)
1996 return r;
1997 }
1998 }
1999 return 0;
2000 }
2001
2002 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2003 int stream, unsigned *stream_item_size)
2004 {
2005 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2006 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2007 int i, j, r;
2008
2009 /* Sanity checking. */
2010 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2011 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2012 r = -EINVAL;
2013 goto out_err;
2014 }
2015 for (i = 0; i < so->num_outputs; i++) {
2016 if (so->output[i].output_buffer >= 4) {
2017 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2018 so->output[i].output_buffer);
2019 r = -EINVAL;
2020 goto out_err;
2021 }
2022 }
2023
2024 /* Initialize locations where the outputs are stored. */
2025 for (i = 0; i < so->num_outputs; i++) {
2026
2027 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2028 start_comp[i] = so->output[i].start_component;
2029 /* Lower outputs with dst_offset < start_component.
2030 *
2031 * We can only output 4D vectors with a write mask, e.g. we can
2032 * only output the W component at offset 3, etc. If we want
2033 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2034 * to move it to X and output X. */
2035 if (so->output[i].dst_offset < so->output[i].start_component) {
2036 unsigned tmp = r600_get_temp(ctx);
2037
2038 for (j = 0; j < so->output[i].num_components; j++) {
2039 struct r600_bytecode_alu alu;
2040 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2041 alu.op = ALU_OP1_MOV;
2042 alu.src[0].sel = so_gpr[i];
2043 alu.src[0].chan = so->output[i].start_component + j;
2044
2045 alu.dst.sel = tmp;
2046 alu.dst.chan = j;
2047 alu.dst.write = 1;
2048 if (j == so->output[i].num_components - 1)
2049 alu.last = 1;
2050 r = r600_bytecode_add_alu(ctx->bc, &alu);
2051 if (r)
2052 return r;
2053 }
2054 start_comp[i] = 0;
2055 so_gpr[i] = tmp;
2056 }
2057 }
2058
2059 /* Write outputs to buffers. */
2060 for (i = 0; i < so->num_outputs; i++) {
2061 struct r600_bytecode_output output;
2062
2063 if (stream != -1 && stream != so->output[i].output_buffer)
2064 continue;
2065
2066 memset(&output, 0, sizeof(struct r600_bytecode_output));
2067 output.gpr = so_gpr[i];
2068 output.elem_size = so->output[i].num_components - 1;
2069 if (output.elem_size == 2)
2070 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2071 output.array_base = so->output[i].dst_offset - start_comp[i];
2072 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2073 output.burst_count = 1;
2074 /* array_size is an upper limit for the burst_count
2075 * with MEM_STREAM instructions */
2076 output.array_size = 0xFFF;
2077 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2078
2079 if (ctx->bc->chip_class >= EVERGREEN) {
2080 switch (so->output[i].output_buffer) {
2081 case 0:
2082 output.op = CF_OP_MEM_STREAM0_BUF0;
2083 break;
2084 case 1:
2085 output.op = CF_OP_MEM_STREAM0_BUF1;
2086 break;
2087 case 2:
2088 output.op = CF_OP_MEM_STREAM0_BUF2;
2089 break;
2090 case 3:
2091 output.op = CF_OP_MEM_STREAM0_BUF3;
2092 break;
2093 }
2094 output.op += so->output[i].stream * 4;
2095 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2096 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2097 } else {
2098 switch (so->output[i].output_buffer) {
2099 case 0:
2100 output.op = CF_OP_MEM_STREAM0;
2101 break;
2102 case 1:
2103 output.op = CF_OP_MEM_STREAM1;
2104 break;
2105 case 2:
2106 output.op = CF_OP_MEM_STREAM2;
2107 break;
2108 case 3:
2109 output.op = CF_OP_MEM_STREAM3;
2110 break;
2111 }
2112 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2113 }
2114 r = r600_bytecode_add_output(ctx->bc, &output);
2115 if (r)
2116 goto out_err;
2117 }
2118 return 0;
2119 out_err:
2120 return r;
2121 }
2122
2123 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2124 {
2125 struct r600_bytecode_alu alu;
2126 unsigned reg;
2127
2128 if (!ctx->shader->vs_out_edgeflag)
2129 return;
2130
2131 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2132
2133 /* clamp(x, 0, 1) */
2134 memset(&alu, 0, sizeof(alu));
2135 alu.op = ALU_OP1_MOV;
2136 alu.src[0].sel = reg;
2137 alu.dst.sel = reg;
2138 alu.dst.write = 1;
2139 alu.dst.clamp = 1;
2140 alu.last = 1;
2141 r600_bytecode_add_alu(ctx->bc, &alu);
2142
2143 memset(&alu, 0, sizeof(alu));
2144 alu.op = ALU_OP1_FLT_TO_INT;
2145 alu.src[0].sel = reg;
2146 alu.dst.sel = reg;
2147 alu.dst.write = 1;
2148 alu.last = 1;
2149 r600_bytecode_add_alu(ctx->bc, &alu);
2150 }
2151
2152 static int generate_gs_copy_shader(struct r600_context *rctx,
2153 struct r600_pipe_shader *gs,
2154 struct pipe_stream_output_info *so)
2155 {
2156 struct r600_shader_ctx ctx = {};
2157 struct r600_shader *gs_shader = &gs->shader;
2158 struct r600_pipe_shader *cshader;
2159 int ocnt = gs_shader->noutput;
2160 struct r600_bytecode_alu alu;
2161 struct r600_bytecode_vtx vtx;
2162 struct r600_bytecode_output output;
2163 struct r600_bytecode_cf *cf_jump, *cf_pop,
2164 *last_exp_pos = NULL, *last_exp_param = NULL;
2165 int i, j, next_clip_pos = 61, next_param = 0;
2166 int ring;
2167 bool only_ring_0 = true;
2168 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2169 if (!cshader)
2170 return 0;
2171
2172 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2173 sizeof(struct r600_shader_io));
2174
2175 cshader->shader.noutput = ocnt;
2176
2177 ctx.shader = &cshader->shader;
2178 ctx.bc = &ctx.shader->bc;
2179 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2180
2181 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2182 rctx->screen->has_compressed_msaa_texturing);
2183
2184 ctx.bc->isa = rctx->isa;
2185
2186 cf_jump = NULL;
2187 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2188
2189 /* R0.x = R0.x & 0x3fffffff */
2190 memset(&alu, 0, sizeof(alu));
2191 alu.op = ALU_OP2_AND_INT;
2192 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2193 alu.src[1].value = 0x3fffffff;
2194 alu.dst.write = 1;
2195 r600_bytecode_add_alu(ctx.bc, &alu);
2196
2197 /* R0.y = R0.x >> 30 */
2198 memset(&alu, 0, sizeof(alu));
2199 alu.op = ALU_OP2_LSHR_INT;
2200 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2201 alu.src[1].value = 0x1e;
2202 alu.dst.chan = 1;
2203 alu.dst.write = 1;
2204 alu.last = 1;
2205 r600_bytecode_add_alu(ctx.bc, &alu);
2206
2207 /* fetch vertex data from GSVS ring */
2208 for (i = 0; i < ocnt; ++i) {
2209 struct r600_shader_io *out = &ctx.shader->output[i];
2210
2211 out->gpr = i + 1;
2212 out->ring_offset = i * 16;
2213
2214 memset(&vtx, 0, sizeof(vtx));
2215 vtx.op = FETCH_OP_VFETCH;
2216 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2217 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2218 vtx.mega_fetch_count = 16;
2219 vtx.offset = out->ring_offset;
2220 vtx.dst_gpr = out->gpr;
2221 vtx.src_gpr = 0;
2222 vtx.dst_sel_x = 0;
2223 vtx.dst_sel_y = 1;
2224 vtx.dst_sel_z = 2;
2225 vtx.dst_sel_w = 3;
2226 if (rctx->b.chip_class >= EVERGREEN) {
2227 vtx.use_const_fields = 1;
2228 } else {
2229 vtx.data_format = FMT_32_32_32_32_FLOAT;
2230 }
2231
2232 r600_bytecode_add_vtx(ctx.bc, &vtx);
2233 }
2234 ctx.temp_reg = i + 1;
2235 for (ring = 3; ring >= 0; --ring) {
2236 bool enabled = false;
2237 for (i = 0; i < so->num_outputs; i++) {
2238 if (so->output[i].stream == ring) {
2239 enabled = true;
2240 if (ring > 0)
2241 only_ring_0 = false;
2242 break;
2243 }
2244 }
2245 if (ring != 0 && !enabled) {
2246 cshader->shader.ring_item_sizes[ring] = 0;
2247 continue;
2248 }
2249
2250 if (cf_jump) {
2251 // Patch up jump label
2252 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2253 cf_pop = ctx.bc->cf_last;
2254
2255 cf_jump->cf_addr = cf_pop->id + 2;
2256 cf_jump->pop_count = 1;
2257 cf_pop->cf_addr = cf_pop->id + 2;
2258 cf_pop->pop_count = 1;
2259 }
2260
2261 /* PRED_SETE_INT __, R0.y, ring */
2262 memset(&alu, 0, sizeof(alu));
2263 alu.op = ALU_OP2_PRED_SETE_INT;
2264 alu.src[0].chan = 1;
2265 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2266 alu.src[1].value = ring;
2267 alu.execute_mask = 1;
2268 alu.update_pred = 1;
2269 alu.last = 1;
2270 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2271
2272 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2273 cf_jump = ctx.bc->cf_last;
2274
2275 if (enabled)
2276 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2277 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2278 }
2279
2280 /* bc adds nops - copy it */
2281 if (ctx.bc->chip_class == R600) {
2282 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2283 alu.op = ALU_OP0_NOP;
2284 alu.last = 1;
2285 r600_bytecode_add_alu(ctx.bc, &alu);
2286
2287 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2288 }
2289
2290 /* export vertex data */
2291 /* XXX factor out common code with r600_shader_from_tgsi ? */
2292 for (i = 0; i < ocnt; ++i) {
2293 struct r600_shader_io *out = &ctx.shader->output[i];
2294 bool instream0 = true;
2295 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2296 continue;
2297
2298 for (j = 0; j < so->num_outputs; j++) {
2299 if (so->output[j].register_index == i) {
2300 if (so->output[j].stream == 0)
2301 break;
2302 if (so->output[j].stream > 0)
2303 instream0 = false;
2304 }
2305 }
2306 if (!instream0)
2307 continue;
2308 memset(&output, 0, sizeof(output));
2309 output.gpr = out->gpr;
2310 output.elem_size = 3;
2311 output.swizzle_x = 0;
2312 output.swizzle_y = 1;
2313 output.swizzle_z = 2;
2314 output.swizzle_w = 3;
2315 output.burst_count = 1;
2316 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2317 output.op = CF_OP_EXPORT;
2318 switch (out->name) {
2319 case TGSI_SEMANTIC_POSITION:
2320 output.array_base = 60;
2321 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2322 break;
2323
2324 case TGSI_SEMANTIC_PSIZE:
2325 output.array_base = 61;
2326 if (next_clip_pos == 61)
2327 next_clip_pos = 62;
2328 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2329 output.swizzle_y = 7;
2330 output.swizzle_z = 7;
2331 output.swizzle_w = 7;
2332 ctx.shader->vs_out_misc_write = 1;
2333 ctx.shader->vs_out_point_size = 1;
2334 break;
2335 case TGSI_SEMANTIC_LAYER:
2336 if (out->spi_sid) {
2337 /* duplicate it as PARAM to pass to the pixel shader */
2338 output.array_base = next_param++;
2339 r600_bytecode_add_output(ctx.bc, &output);
2340 last_exp_param = ctx.bc->cf_last;
2341 }
2342 output.array_base = 61;
2343 if (next_clip_pos == 61)
2344 next_clip_pos = 62;
2345 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2346 output.swizzle_x = 7;
2347 output.swizzle_y = 7;
2348 output.swizzle_z = 0;
2349 output.swizzle_w = 7;
2350 ctx.shader->vs_out_misc_write = 1;
2351 ctx.shader->vs_out_layer = 1;
2352 break;
2353 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2354 if (out->spi_sid) {
2355 /* duplicate it as PARAM to pass to the pixel shader */
2356 output.array_base = next_param++;
2357 r600_bytecode_add_output(ctx.bc, &output);
2358 last_exp_param = ctx.bc->cf_last;
2359 }
2360 output.array_base = 61;
2361 if (next_clip_pos == 61)
2362 next_clip_pos = 62;
2363 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2364 ctx.shader->vs_out_misc_write = 1;
2365 ctx.shader->vs_out_viewport = 1;
2366 output.swizzle_x = 7;
2367 output.swizzle_y = 7;
2368 output.swizzle_z = 7;
2369 output.swizzle_w = 0;
2370 break;
2371 case TGSI_SEMANTIC_CLIPDIST:
2372 /* spi_sid is 0 for clipdistance outputs that were generated
2373 * for clipvertex - we don't need to pass them to PS */
2374 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2375 if (out->spi_sid) {
2376 /* duplicate it as PARAM to pass to the pixel shader */
2377 output.array_base = next_param++;
2378 r600_bytecode_add_output(ctx.bc, &output);
2379 last_exp_param = ctx.bc->cf_last;
2380 }
2381 output.array_base = next_clip_pos++;
2382 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2383 break;
2384 case TGSI_SEMANTIC_FOG:
2385 output.swizzle_y = 4; /* 0 */
2386 output.swizzle_z = 4; /* 0 */
2387 output.swizzle_w = 5; /* 1 */
2388 break;
2389 default:
2390 output.array_base = next_param++;
2391 break;
2392 }
2393 r600_bytecode_add_output(ctx.bc, &output);
2394 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2395 last_exp_param = ctx.bc->cf_last;
2396 else
2397 last_exp_pos = ctx.bc->cf_last;
2398 }
2399
2400 if (!last_exp_pos) {
2401 memset(&output, 0, sizeof(output));
2402 output.gpr = 0;
2403 output.elem_size = 3;
2404 output.swizzle_x = 7;
2405 output.swizzle_y = 7;
2406 output.swizzle_z = 7;
2407 output.swizzle_w = 7;
2408 output.burst_count = 1;
2409 output.type = 2;
2410 output.op = CF_OP_EXPORT;
2411 output.array_base = 60;
2412 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2413 r600_bytecode_add_output(ctx.bc, &output);
2414 last_exp_pos = ctx.bc->cf_last;
2415 }
2416
2417 if (!last_exp_param) {
2418 memset(&output, 0, sizeof(output));
2419 output.gpr = 0;
2420 output.elem_size = 3;
2421 output.swizzle_x = 7;
2422 output.swizzle_y = 7;
2423 output.swizzle_z = 7;
2424 output.swizzle_w = 7;
2425 output.burst_count = 1;
2426 output.type = 2;
2427 output.op = CF_OP_EXPORT;
2428 output.array_base = next_param++;
2429 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2430 r600_bytecode_add_output(ctx.bc, &output);
2431 last_exp_param = ctx.bc->cf_last;
2432 }
2433
2434 last_exp_pos->op = CF_OP_EXPORT_DONE;
2435 last_exp_param->op = CF_OP_EXPORT_DONE;
2436
2437 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2438 cf_pop = ctx.bc->cf_last;
2439
2440 cf_jump->cf_addr = cf_pop->id + 2;
2441 cf_jump->pop_count = 1;
2442 cf_pop->cf_addr = cf_pop->id + 2;
2443 cf_pop->pop_count = 1;
2444
2445 if (ctx.bc->chip_class == CAYMAN)
2446 cm_bytecode_add_cf_end(ctx.bc);
2447 else {
2448 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2449 ctx.bc->cf_last->end_of_program = 1;
2450 }
2451
2452 gs->gs_copy_shader = cshader;
2453 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2454
2455 ctx.bc->nstack = 1;
2456
2457 return r600_bytecode_build(ctx.bc);
2458 }
2459
2460 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2461 {
2462 if (ind) {
2463 struct r600_bytecode_alu alu;
2464 int r;
2465
2466 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2467 alu.op = ALU_OP2_ADD_INT;
2468 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2469 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2470 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2471 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2472 alu.dst.write = 1;
2473 alu.last = 1;
2474 r = r600_bytecode_add_alu(ctx->bc, &alu);
2475 if (r)
2476 return r;
2477 }
2478 return 0;
2479 }
2480
2481 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind)
2482 {
2483 struct r600_bytecode_output output;
2484 int i, k, ring_offset;
2485 int effective_stream = stream == -1 ? 0 : stream;
2486 int idx = 0;
2487
2488 for (i = 0; i < ctx->shader->noutput; i++) {
2489 if (ctx->gs_for_vs) {
2490 /* for ES we need to lookup corresponding ring offset expected by GS
2491 * (map this output to GS input by name and sid) */
2492 /* FIXME precompute offsets */
2493 ring_offset = -1;
2494 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2495 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2496 struct r600_shader_io *out = &ctx->shader->output[i];
2497 if (in->name == out->name && in->sid == out->sid)
2498 ring_offset = in->ring_offset;
2499 }
2500
2501 if (ring_offset == -1)
2502 continue;
2503 } else {
2504 ring_offset = idx * 16;
2505 idx++;
2506 }
2507
2508 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2509 continue;
2510 /* next_ring_offset after parsing input decls contains total size of
2511 * single vertex data, gs_next_vertex - current vertex index */
2512 if (!ind)
2513 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2514
2515 memset(&output, 0, sizeof(struct r600_bytecode_output));
2516 output.gpr = ctx->shader->output[i].gpr;
2517 output.elem_size = 3;
2518 output.comp_mask = 0xF;
2519 output.burst_count = 1;
2520
2521 if (ind)
2522 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2523 else
2524 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2525
2526 switch (stream) {
2527 default:
2528 case 0:
2529 output.op = CF_OP_MEM_RING; break;
2530 case 1:
2531 output.op = CF_OP_MEM_RING1; break;
2532 case 2:
2533 output.op = CF_OP_MEM_RING2; break;
2534 case 3:
2535 output.op = CF_OP_MEM_RING3; break;
2536 }
2537
2538 if (ind) {
2539 output.array_base = ring_offset >> 2; /* in dwords */
2540 output.array_size = 0xfff;
2541 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2542 } else
2543 output.array_base = ring_offset >> 2; /* in dwords */
2544 r600_bytecode_add_output(ctx->bc, &output);
2545 }
2546
2547 ++ctx->gs_next_vertex;
2548 return 0;
2549 }
2550
2551
2552 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2553 {
2554 int r;
2555 struct r600_bytecode_vtx vtx;
2556 int temp_val = ctx->temp_reg;
2557 /* need to store the TCS output somewhere */
2558 r = single_alu_op2(ctx, ALU_OP1_MOV,
2559 temp_val, 0,
2560 V_SQ_ALU_SRC_LITERAL, 0,
2561 0, 0);
2562 if (r)
2563 return r;
2564
2565 /* used by VS/TCS */
2566 if (ctx->tess_input_info) {
2567 /* fetch tcs input values into resv space */
2568 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2569 vtx.op = FETCH_OP_VFETCH;
2570 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2571 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2572 vtx.mega_fetch_count = 16;
2573 vtx.data_format = FMT_32_32_32_32;
2574 vtx.num_format_all = 2;
2575 vtx.format_comp_all = 1;
2576 vtx.use_const_fields = 0;
2577 vtx.endian = r600_endian_swap(32);
2578 vtx.srf_mode_all = 1;
2579 vtx.offset = 0;
2580 vtx.dst_gpr = ctx->tess_input_info;
2581 vtx.dst_sel_x = 0;
2582 vtx.dst_sel_y = 1;
2583 vtx.dst_sel_z = 2;
2584 vtx.dst_sel_w = 3;
2585 vtx.src_gpr = temp_val;
2586 vtx.src_sel_x = 0;
2587
2588 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2589 if (r)
2590 return r;
2591 }
2592
2593 /* used by TCS/TES */
2594 if (ctx->tess_output_info) {
2595 /* fetch tcs output values into resv space */
2596 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2597 vtx.op = FETCH_OP_VFETCH;
2598 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2599 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2600 vtx.mega_fetch_count = 16;
2601 vtx.data_format = FMT_32_32_32_32;
2602 vtx.num_format_all = 2;
2603 vtx.format_comp_all = 1;
2604 vtx.use_const_fields = 0;
2605 vtx.endian = r600_endian_swap(32);
2606 vtx.srf_mode_all = 1;
2607 vtx.offset = 16;
2608 vtx.dst_gpr = ctx->tess_output_info;
2609 vtx.dst_sel_x = 0;
2610 vtx.dst_sel_y = 1;
2611 vtx.dst_sel_z = 2;
2612 vtx.dst_sel_w = 3;
2613 vtx.src_gpr = temp_val;
2614 vtx.src_sel_x = 0;
2615
2616 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2617 if (r)
2618 return r;
2619 }
2620 return 0;
2621 }
2622
2623 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2624 {
2625 int i, j, r;
2626 int temp_reg;
2627
2628 /* fetch tcs input values into input_vals */
2629 ctx->tess_input_info = r600_get_temp(ctx);
2630 ctx->tess_output_info = 0;
2631 r = r600_fetch_tess_io_info(ctx);
2632 if (r)
2633 return r;
2634
2635 temp_reg = r600_get_temp(ctx);
2636 /* dst reg contains LDS address stride * idx */
2637 /* MUL vertexID, vertex_dw_stride */
2638 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2639 temp_reg, 0,
2640 ctx->tess_input_info, 1,
2641 0, 1); /* rel id in r0.y? */
2642 if (r)
2643 return r;
2644
2645 for (i = 0; i < ctx->shader->noutput; i++) {
2646 struct r600_bytecode_alu alu;
2647 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2648
2649 if (param) {
2650 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2651 temp_reg, 1,
2652 temp_reg, 0,
2653 V_SQ_ALU_SRC_LITERAL, param * 16);
2654 if (r)
2655 return r;
2656 }
2657
2658 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2659 temp_reg, 2,
2660 temp_reg, param ? 1 : 0,
2661 V_SQ_ALU_SRC_LITERAL, 8);
2662 if (r)
2663 return r;
2664
2665
2666 for (j = 0; j < 2; j++) {
2667 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2668 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2669 alu.op = LDS_OP3_LDS_WRITE_REL;
2670 alu.src[0].sel = temp_reg;
2671 alu.src[0].chan = chan;
2672 alu.src[1].sel = ctx->shader->output[i].gpr;
2673 alu.src[1].chan = j * 2;
2674 alu.src[2].sel = ctx->shader->output[i].gpr;
2675 alu.src[2].chan = (j * 2) + 1;
2676 alu.last = 1;
2677 alu.dst.chan = 0;
2678 alu.lds_idx = 1;
2679 alu.is_lds_idx_op = true;
2680 r = r600_bytecode_add_alu(ctx->bc, &alu);
2681 if (r)
2682 return r;
2683 }
2684 }
2685 return 0;
2686 }
2687
2688 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2689 {
2690 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2691 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2692 int i, r, lasti;
2693 int temp_reg = r600_get_temp(ctx);
2694 struct r600_bytecode_alu alu;
2695 unsigned write_mask = dst->Register.WriteMask;
2696
2697 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2698 return 0;
2699
2700 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2701 if (r)
2702 return r;
2703
2704 /* the base address is now in temp.x */
2705 r = r600_get_byte_address(ctx, temp_reg,
2706 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2707 if (r)
2708 return r;
2709
2710 /* LDS write */
2711 lasti = tgsi_last_instruction(write_mask);
2712 for (i = 1; i <= lasti; i++) {
2713
2714 if (!(write_mask & (1 << i)))
2715 continue;
2716 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2717 temp_reg, i,
2718 temp_reg, 0,
2719 V_SQ_ALU_SRC_LITERAL, 4 * i);
2720 if (r)
2721 return r;
2722 }
2723
2724 for (i = 0; i <= lasti; i++) {
2725 if (!(write_mask & (1 << i)))
2726 continue;
2727
2728 if ((i == 0 && ((write_mask & 3) == 3)) ||
2729 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2730 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2731 alu.op = LDS_OP3_LDS_WRITE_REL;
2732 alu.src[0].sel = temp_reg;
2733 alu.src[0].chan = i;
2734
2735 alu.src[1].sel = dst->Register.Index;
2736 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2737 alu.src[1].chan = i;
2738
2739 alu.src[2].sel = dst->Register.Index;
2740 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2741 alu.src[2].chan = i + 1;
2742 alu.lds_idx = 1;
2743 alu.dst.chan = 0;
2744 alu.last = 1;
2745 alu.is_lds_idx_op = true;
2746 r = r600_bytecode_add_alu(ctx->bc, &alu);
2747 if (r)
2748 return r;
2749 i += 1;
2750 continue;
2751 }
2752 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2753 alu.op = LDS_OP2_LDS_WRITE;
2754 alu.src[0].sel = temp_reg;
2755 alu.src[0].chan = i;
2756
2757 alu.src[1].sel = dst->Register.Index;
2758 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2759 alu.src[1].chan = i;
2760
2761 alu.src[2].sel = V_SQ_ALU_SRC_0;
2762 alu.dst.chan = 0;
2763 alu.last = 1;
2764 alu.is_lds_idx_op = true;
2765 r = r600_bytecode_add_alu(ctx->bc, &alu);
2766 if (r)
2767 return r;
2768 }
2769 return 0;
2770 }
2771
2772 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2773 int output_idx)
2774 {
2775 int param;
2776 unsigned temp_reg = r600_get_temp(ctx);
2777 unsigned name = ctx->shader->output[output_idx].name;
2778 int dreg = ctx->shader->output[output_idx].gpr;
2779 int r;
2780
2781 param = r600_get_lds_unique_index(name, 0);
2782 r = get_lds_offset0(ctx, 1, temp_reg, true);
2783 if (r)
2784 return r;
2785
2786 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2787 temp_reg, 0,
2788 temp_reg, 0,
2789 V_SQ_ALU_SRC_LITERAL, param * 16);
2790 if (r)
2791 return r;
2792
2793 do_lds_fetch_values(ctx, temp_reg, dreg);
2794 return 0;
2795 }
2796
2797 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2798 {
2799 unsigned i;
2800 int stride, outer_comps, inner_comps;
2801 int tessinner_idx = -1, tessouter_idx = -1;
2802 int r;
2803 int temp_reg = r600_get_temp(ctx);
2804 int treg[3] = {-1, -1, -1};
2805 struct r600_bytecode_alu alu;
2806 struct r600_bytecode_cf *cf_jump, *cf_pop;
2807
2808 /* only execute factor emission for invocation 0 */
2809 /* PRED_SETE_INT __, R0.x, 0 */
2810 memset(&alu, 0, sizeof(alu));
2811 alu.op = ALU_OP2_PRED_SETE_INT;
2812 alu.src[0].chan = 2;
2813 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2814 alu.execute_mask = 1;
2815 alu.update_pred = 1;
2816 alu.last = 1;
2817 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2818
2819 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2820 cf_jump = ctx->bc->cf_last;
2821
2822 treg[0] = r600_get_temp(ctx);
2823 switch (ctx->shader->tcs_prim_mode) {
2824 case PIPE_PRIM_LINES:
2825 stride = 8; /* 2 dwords, 1 vec2 store */
2826 outer_comps = 2;
2827 inner_comps = 0;
2828 break;
2829 case PIPE_PRIM_TRIANGLES:
2830 stride = 16; /* 4 dwords, 1 vec4 store */
2831 outer_comps = 3;
2832 inner_comps = 1;
2833 treg[1] = r600_get_temp(ctx);
2834 break;
2835 case PIPE_PRIM_QUADS:
2836 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2837 outer_comps = 4;
2838 inner_comps = 2;
2839 treg[1] = r600_get_temp(ctx);
2840 treg[2] = r600_get_temp(ctx);
2841 break;
2842 default:
2843 assert(0);
2844 return -1;
2845 }
2846
2847 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2848 /* TF_WRITE takes index in R.x, value in R.y */
2849 for (i = 0; i < ctx->shader->noutput; i++) {
2850 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSINNER)
2851 tessinner_idx = i;
2852 if (ctx->shader->output[i].name == TGSI_SEMANTIC_TESSOUTER)
2853 tessouter_idx = i;
2854 }
2855
2856 if (tessouter_idx == -1)
2857 return -1;
2858
2859 if (tessinner_idx == -1 && inner_comps)
2860 return -1;
2861
2862 if (tessouter_idx != -1) {
2863 r = r600_tess_factor_read(ctx, tessouter_idx);
2864 if (r)
2865 return r;
2866 }
2867
2868 if (tessinner_idx != -1) {
2869 r = r600_tess_factor_read(ctx, tessinner_idx);
2870 if (r)
2871 return r;
2872 }
2873
2874 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2875 /* r.x = relpatchid(r0.y) * tf_stride */
2876
2877 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2878 /* add incoming r0.w to it: t.x = t.x + r0.w */
2879 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2880 temp_reg, 0,
2881 0, 1,
2882 V_SQ_ALU_SRC_LITERAL, stride,
2883 0, 3);
2884 if (r)
2885 return r;
2886
2887 for (i = 0; i < outer_comps + inner_comps; i++) {
2888 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2889 int out_comp = i >= outer_comps ? i - outer_comps : i;
2890
2891 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2892 if (out_comp == 1)
2893 out_comp = 0;
2894 else if (out_comp == 0)
2895 out_comp = 1;
2896 }
2897
2898 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2899 treg[i / 2], (2 * (i % 2)),
2900 temp_reg, 0,
2901 V_SQ_ALU_SRC_LITERAL, 4 * i);
2902 if (r)
2903 return r;
2904 r = single_alu_op2(ctx, ALU_OP1_MOV,
2905 treg[i / 2], 1 + (2 * (i%2)),
2906 ctx->shader->output[out_idx].gpr, out_comp,
2907 0, 0);
2908 if (r)
2909 return r;
2910 }
2911 for (i = 0; i < outer_comps + inner_comps; i++) {
2912 struct r600_bytecode_gds gds;
2913
2914 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2915 gds.src_gpr = treg[i / 2];
2916 gds.src_sel_x = 2 * (i % 2);
2917 gds.src_sel_y = 1 + (2 * (i % 2));
2918 gds.src_sel_z = 4;
2919 gds.dst_sel_x = 7;
2920 gds.dst_sel_y = 7;
2921 gds.dst_sel_z = 7;
2922 gds.dst_sel_w = 7;
2923 gds.op = FETCH_OP_TF_WRITE;
2924 r = r600_bytecode_add_gds(ctx->bc, &gds);
2925 if (r)
2926 return r;
2927 }
2928
2929 // Patch up jump label
2930 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
2931 cf_pop = ctx->bc->cf_last;
2932
2933 cf_jump->cf_addr = cf_pop->id + 2;
2934 cf_jump->pop_count = 1;
2935 cf_pop->cf_addr = cf_pop->id + 2;
2936 cf_pop->pop_count = 1;
2937
2938 return 0;
2939 }
2940
2941 /*
2942 * We have to work out the thread ID for load and atomic
2943 * operations, which store the returned value to an index
2944 * in an intermediate buffer.
2945 * The index is calculated by taking the thread id,
2946 * calculated from the MBCNT instructions.
2947 * Then the shader engine ID is multiplied by 256,
2948 * and the wave id is added.
2949 * Then the result is multipled by 64 and thread id is
2950 * added.
2951 */
2952 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
2953 {
2954 struct r600_bytecode_alu alu;
2955 int r;
2956
2957 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2958 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
2959 alu.dst.sel = ctx->temp_reg;
2960 alu.dst.chan = 0;
2961 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2962 alu.src[0].value = 0xffffffff;
2963 alu.dst.write = 1;
2964 r = r600_bytecode_add_alu(ctx->bc, &alu);
2965 if (r)
2966 return r;
2967
2968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2969 alu.op = ALU_OP1_MBCNT_32HI_INT;
2970 alu.dst.sel = ctx->temp_reg;
2971 alu.dst.chan = 1;
2972 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
2973 alu.src[0].value = 0xffffffff;
2974 alu.dst.write = 1;
2975 r = r600_bytecode_add_alu(ctx->bc, &alu);
2976 if (r)
2977 return r;
2978
2979 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2980 alu.op = ALU_OP3_MULADD_UINT24;
2981 alu.dst.sel = ctx->temp_reg;
2982 alu.dst.chan = 2;
2983 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
2984 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2985 alu.src[1].value = 256;
2986 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
2987 alu.dst.write = 1;
2988 alu.is_op3 = 1;
2989 alu.last = 1;
2990 r = r600_bytecode_add_alu(ctx->bc, &alu);
2991 if (r)
2992 return r;
2993
2994 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2995 ctx->thread_id_gpr, 1,
2996 ctx->temp_reg, 2,
2997 V_SQ_ALU_SRC_LITERAL, 0x40,
2998 ctx->temp_reg, 0);
2999 if (r)
3000 return r;
3001 return 0;
3002 }
3003
3004 static int r600_shader_from_tgsi(struct r600_context *rctx,
3005 struct r600_pipe_shader *pipeshader,
3006 union r600_shader_key key)
3007 {
3008 struct r600_screen *rscreen = rctx->screen;
3009 struct r600_shader *shader = &pipeshader->shader;
3010 struct tgsi_token *tokens = pipeshader->selector->tokens;
3011 struct pipe_stream_output_info so = pipeshader->selector->so;
3012 struct tgsi_full_immediate *immediate;
3013 struct r600_shader_ctx ctx;
3014 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3015 unsigned output_done, noutput;
3016 unsigned opcode;
3017 int i, j, k, r = 0;
3018 int next_param_base = 0, next_clip_base;
3019 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3020 bool indirect_gprs;
3021 bool ring_outputs = false;
3022 bool lds_outputs = false;
3023 bool lds_inputs = false;
3024 bool pos_emitted = false;
3025
3026 ctx.bc = &shader->bc;
3027 ctx.shader = shader;
3028 ctx.native_integers = true;
3029
3030 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3031 rscreen->has_compressed_msaa_texturing);
3032 ctx.tokens = tokens;
3033 tgsi_scan_shader(tokens, &ctx.info);
3034 shader->indirect_files = ctx.info.indirect_files;
3035
3036 shader->uses_doubles = ctx.info.uses_doubles;
3037 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3038 shader->nsys_inputs = 0;
3039
3040 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0;
3041 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3042 tgsi_parse_init(&ctx.parse, tokens);
3043 ctx.type = ctx.info.processor;
3044 shader->processor_type = ctx.type;
3045 ctx.bc->type = shader->processor_type;
3046
3047 switch (ctx.type) {
3048 case PIPE_SHADER_VERTEX:
3049 shader->vs_as_gs_a = key.vs.as_gs_a;
3050 shader->vs_as_es = key.vs.as_es;
3051 shader->vs_as_ls = key.vs.as_ls;
3052 shader->atomic_base = key.vs.first_atomic_counter;
3053 if (shader->vs_as_es)
3054 ring_outputs = true;
3055 if (shader->vs_as_ls)
3056 lds_outputs = true;
3057 break;
3058 case PIPE_SHADER_GEOMETRY:
3059 ring_outputs = true;
3060 shader->atomic_base = key.gs.first_atomic_counter;
3061 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3062 break;
3063 case PIPE_SHADER_TESS_CTRL:
3064 shader->tcs_prim_mode = key.tcs.prim_mode;
3065 shader->atomic_base = key.tcs.first_atomic_counter;
3066 lds_outputs = true;
3067 lds_inputs = true;
3068 break;
3069 case PIPE_SHADER_TESS_EVAL:
3070 shader->tes_as_es = key.tes.as_es;
3071 shader->atomic_base = key.tes.first_atomic_counter;
3072 lds_inputs = true;
3073 if (shader->tes_as_es)
3074 ring_outputs = true;
3075 break;
3076 case PIPE_SHADER_FRAGMENT:
3077 shader->two_side = key.ps.color_two_side;
3078 shader->atomic_base = key.ps.first_atomic_counter;
3079 shader->rat_base = key.ps.nr_cbufs;
3080 shader->image_size_const_offset = key.ps.image_size_const_offset;
3081 break;
3082 default:
3083 break;
3084 }
3085
3086 if (shader->vs_as_es || shader->tes_as_es) {
3087 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3088 } else {
3089 ctx.gs_for_vs = NULL;
3090 }
3091
3092 ctx.next_ring_offset = 0;
3093 ctx.gs_out_ring_offset = 0;
3094 ctx.gs_next_vertex = 0;
3095 ctx.gs_stream_output_info = &so;
3096
3097 ctx.face_gpr = -1;
3098 ctx.fixed_pt_position_gpr = -1;
3099 ctx.fragcoord_input = -1;
3100 ctx.colors_used = 0;
3101 ctx.clip_vertex_write = 0;
3102
3103 shader->nr_ps_color_exports = 0;
3104 shader->nr_ps_max_color_exports = 0;
3105
3106
3107 /* register allocations */
3108 /* Values [0,127] correspond to GPR[0..127].
3109 * Values [128,159] correspond to constant buffer bank 0
3110 * Values [160,191] correspond to constant buffer bank 1
3111 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3112 * Values [256,287] correspond to constant buffer bank 2 (EG)
3113 * Values [288,319] correspond to constant buffer bank 3 (EG)
3114 * Other special values are shown in the list below.
3115 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3116 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3117 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3118 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3119 * 248 SQ_ALU_SRC_0: special constant 0.0.
3120 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3121 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3122 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3123 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3124 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3125 * 254 SQ_ALU_SRC_PV: previous vector result.
3126 * 255 SQ_ALU_SRC_PS: previous scalar result.
3127 */
3128 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3129 ctx.file_offset[i] = 0;
3130 }
3131
3132 if (ctx.type == PIPE_SHADER_VERTEX) {
3133
3134 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3135 if (ctx.info.num_inputs)
3136 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3137 }
3138 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3139 if (ctx.bc->chip_class >= EVERGREEN)
3140 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3141 else
3142 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3143 }
3144 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3145 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3146 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3147 }
3148 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3149 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3150 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3151 bool add_tesscoord = false, add_tess_inout = false;
3152 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3153 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3154 /* if we have tesscoord save one reg */
3155 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3156 add_tesscoord = true;
3157 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3158 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3159 add_tess_inout = true;
3160 }
3161 if (add_tesscoord || add_tess_inout)
3162 ctx.file_offset[TGSI_FILE_INPUT]++;
3163 if (add_tess_inout)
3164 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3165 }
3166
3167 ctx.file_offset[TGSI_FILE_OUTPUT] =
3168 ctx.file_offset[TGSI_FILE_INPUT] +
3169 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3170 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3171 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3172
3173 /* Outside the GPR range. This will be translated to one of the
3174 * kcache banks later. */
3175 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3176
3177 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3178 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3179 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3180 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3181 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3182
3183 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3184 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3185 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3186 ctx.temp_reg = ctx.bc->ar_reg + 5;
3187 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3188 ctx.tess_input_info = 0;
3189 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3190 ctx.temp_reg = ctx.bc->ar_reg + 4;
3191 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3192 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3193 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3194 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3195 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3196 ctx.temp_reg = ctx.bc->ar_reg + 7;
3197 if (ctx.shader->gs_tri_strip_adj_fix) {
3198 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3199 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3200 ctx.temp_reg += 2;
3201 } else {
3202 ctx.gs_rotated_input[0] = 0;
3203 ctx.gs_rotated_input[1] = 1;
3204 }
3205 } else {
3206 ctx.temp_reg = ctx.bc->ar_reg + 3;
3207 }
3208
3209 if (shader->uses_images && ctx.type == PIPE_SHADER_FRAGMENT) {
3210 ctx.thread_id_gpr = ctx.temp_reg;
3211 ctx.temp_reg++;
3212 } else
3213 ctx.thread_id_gpr = 0;
3214
3215 shader->max_arrays = 0;
3216 shader->num_arrays = 0;
3217 if (indirect_gprs) {
3218
3219 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3220 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3221 ctx.file_offset[TGSI_FILE_OUTPUT] -
3222 ctx.file_offset[TGSI_FILE_INPUT],
3223 0x0F);
3224 }
3225 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3226 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3227 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3228 ctx.file_offset[TGSI_FILE_OUTPUT],
3229 0x0F);
3230 }
3231 }
3232
3233 ctx.nliterals = 0;
3234 ctx.literals = NULL;
3235
3236 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3237 ctx.info.colors_written == 1;
3238 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3239 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3240
3241 if (shader->vs_as_gs_a)
3242 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3243
3244 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3245 r600_fetch_tess_io_info(&ctx);
3246
3247 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3248 tgsi_parse_token(&ctx.parse);
3249 switch (ctx.parse.FullToken.Token.Type) {
3250 case TGSI_TOKEN_TYPE_IMMEDIATE:
3251 immediate = &ctx.parse.FullToken.FullImmediate;
3252 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3253 if(ctx.literals == NULL) {
3254 r = -ENOMEM;
3255 goto out_err;
3256 }
3257 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3258 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3259 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3260 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3261 ctx.nliterals++;
3262 break;
3263 case TGSI_TOKEN_TYPE_DECLARATION:
3264 r = tgsi_declaration(&ctx);
3265 if (r)
3266 goto out_err;
3267 break;
3268 case TGSI_TOKEN_TYPE_INSTRUCTION:
3269 case TGSI_TOKEN_TYPE_PROPERTY:
3270 break;
3271 default:
3272 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3273 r = -EINVAL;
3274 goto out_err;
3275 }
3276 }
3277
3278 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3279 shader->ring_item_sizes[1] = 0;
3280 shader->ring_item_sizes[2] = 0;
3281 shader->ring_item_sizes[3] = 0;
3282
3283 /* Process two side if needed */
3284 if (shader->two_side && ctx.colors_used) {
3285 int i, count = ctx.shader->ninput;
3286 unsigned next_lds_loc = ctx.shader->nlds;
3287
3288 /* additional inputs will be allocated right after the existing inputs,
3289 * we won't need them after the color selection, so we don't need to
3290 * reserve these gprs for the rest of the shader code and to adjust
3291 * output offsets etc. */
3292 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3293 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3294
3295 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3296 if (ctx.face_gpr == -1) {
3297 i = ctx.shader->ninput++;
3298 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3299 ctx.shader->input[i].spi_sid = 0;
3300 ctx.shader->input[i].gpr = gpr++;
3301 ctx.face_gpr = ctx.shader->input[i].gpr;
3302 }
3303
3304 for (i = 0; i < count; i++) {
3305 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3306 int ni = ctx.shader->ninput++;
3307 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3308 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3309 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3310 ctx.shader->input[ni].gpr = gpr++;
3311 // TGSI to LLVM needs to know the lds position of inputs.
3312 // Non LLVM path computes it later (in process_twoside_color)
3313 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3314 ctx.shader->input[i].back_color_input = ni;
3315 if (ctx.bc->chip_class >= EVERGREEN) {
3316 if ((r = evergreen_interp_input(&ctx, ni)))
3317 return r;
3318 }
3319 }
3320 }
3321 }
3322
3323 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3324 shader->nr_ps_max_color_exports = 8;
3325
3326 if (ctx.fragcoord_input >= 0) {
3327 if (ctx.bc->chip_class == CAYMAN) {
3328 for (j = 0 ; j < 4; j++) {
3329 struct r600_bytecode_alu alu;
3330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3331 alu.op = ALU_OP1_RECIP_IEEE;
3332 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3333 alu.src[0].chan = 3;
3334
3335 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3336 alu.dst.chan = j;
3337 alu.dst.write = (j == 3);
3338 alu.last = 1;
3339 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3340 return r;
3341 }
3342 } else {
3343 struct r600_bytecode_alu alu;
3344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3345 alu.op = ALU_OP1_RECIP_IEEE;
3346 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3347 alu.src[0].chan = 3;
3348
3349 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3350 alu.dst.chan = 3;
3351 alu.dst.write = 1;
3352 alu.last = 1;
3353 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3354 return r;
3355 }
3356 }
3357
3358 if (ctx.thread_id_gpr) {
3359 load_thread_id_gpr(&ctx);
3360 }
3361
3362 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3363 struct r600_bytecode_alu alu;
3364 int r;
3365
3366 /* GS thread with no output workaround - emit a cut at start of GS */
3367 if (ctx.bc->chip_class == R600)
3368 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3369
3370 for (j = 0; j < 4; j++) {
3371 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3372 alu.op = ALU_OP1_MOV;
3373 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3374 alu.src[0].value = 0;
3375 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3376 alu.dst.write = 1;
3377 alu.last = 1;
3378 r = r600_bytecode_add_alu(ctx.bc, &alu);
3379 if (r)
3380 return r;
3381 }
3382
3383 if (ctx.shader->gs_tri_strip_adj_fix) {
3384 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3385 ctx.gs_rotated_input[0], 2,
3386 0, 2,
3387 V_SQ_ALU_SRC_LITERAL, 1);
3388 if (r)
3389 return r;
3390
3391 for (i = 0; i < 6; i++) {
3392 int rotated = (i + 4) % 6;
3393 int offset_reg = i / 3;
3394 int offset_chan = i % 3;
3395 int rotated_offset_reg = rotated / 3;
3396 int rotated_offset_chan = rotated % 3;
3397
3398 if (offset_reg == 0 && offset_chan == 2)
3399 offset_chan = 3;
3400 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3401 rotated_offset_chan = 3;
3402
3403 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3404 ctx.gs_rotated_input[offset_reg], offset_chan,
3405 ctx.gs_rotated_input[0], 2,
3406 offset_reg, offset_chan,
3407 rotated_offset_reg, rotated_offset_chan);
3408 if (r)
3409 return r;
3410 }
3411 }
3412 }
3413
3414 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3415 r600_fetch_tess_io_info(&ctx);
3416
3417 if (shader->two_side && ctx.colors_used) {
3418 if ((r = process_twoside_color_inputs(&ctx)))
3419 return r;
3420 }
3421
3422 tgsi_parse_init(&ctx.parse, tokens);
3423 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3424 tgsi_parse_token(&ctx.parse);
3425 switch (ctx.parse.FullToken.Token.Type) {
3426 case TGSI_TOKEN_TYPE_INSTRUCTION:
3427 r = tgsi_is_supported(&ctx);
3428 if (r)
3429 goto out_err;
3430 ctx.max_driver_temp_used = 0;
3431 /* reserve first tmp for everyone */
3432 r600_get_temp(&ctx);
3433
3434 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3435 if ((r = tgsi_split_constant(&ctx)))
3436 goto out_err;
3437 if ((r = tgsi_split_literal_constant(&ctx)))
3438 goto out_err;
3439 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3440 if ((r = tgsi_split_gs_inputs(&ctx)))
3441 goto out_err;
3442 } else if (lds_inputs) {
3443 if ((r = tgsi_split_lds_inputs(&ctx)))
3444 goto out_err;
3445 }
3446 if (ctx.bc->chip_class == CAYMAN)
3447 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3448 else if (ctx.bc->chip_class >= EVERGREEN)
3449 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3450 else
3451 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3452 r = ctx.inst_info->process(&ctx);
3453 if (r)
3454 goto out_err;
3455
3456 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3457 r = r600_store_tcs_output(&ctx);
3458 if (r)
3459 goto out_err;
3460 }
3461 break;
3462 default:
3463 break;
3464 }
3465 }
3466
3467 /* Reset the temporary register counter. */
3468 ctx.max_driver_temp_used = 0;
3469
3470 noutput = shader->noutput;
3471
3472 if (!ring_outputs && ctx.clip_vertex_write) {
3473 unsigned clipdist_temp[2];
3474
3475 clipdist_temp[0] = r600_get_temp(&ctx);
3476 clipdist_temp[1] = r600_get_temp(&ctx);
3477
3478 /* need to convert a clipvertex write into clipdistance writes and not export
3479 the clip vertex anymore */
3480
3481 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3482 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3483 shader->output[noutput].gpr = clipdist_temp[0];
3484 noutput++;
3485 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3486 shader->output[noutput].gpr = clipdist_temp[1];
3487 noutput++;
3488
3489 /* reset spi_sid for clipvertex output to avoid confusing spi */
3490 shader->output[ctx.cv_output].spi_sid = 0;
3491
3492 shader->clip_dist_write = 0xFF;
3493
3494 for (i = 0; i < 8; i++) {
3495 int oreg = i >> 2;
3496 int ochan = i & 3;
3497
3498 for (j = 0; j < 4; j++) {
3499 struct r600_bytecode_alu alu;
3500 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3501 alu.op = ALU_OP2_DOT4;
3502 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3503 alu.src[0].chan = j;
3504
3505 alu.src[1].sel = 512 + i;
3506 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3507 alu.src[1].chan = j;
3508
3509 alu.dst.sel = clipdist_temp[oreg];
3510 alu.dst.chan = j;
3511 alu.dst.write = (j == ochan);
3512 if (j == 3)
3513 alu.last = 1;
3514 r = r600_bytecode_add_alu(ctx.bc, &alu);
3515 if (r)
3516 return r;
3517 }
3518 }
3519 }
3520
3521 /* Add stream outputs. */
3522 if (so.num_outputs) {
3523 bool emit = false;
3524 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3525 emit = true;
3526 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3527 emit = true;
3528 if (emit)
3529 emit_streamout(&ctx, &so, -1, NULL);
3530 }
3531 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3532 convert_edgeflag_to_int(&ctx);
3533
3534 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3535 r600_emit_tess_factor(&ctx);
3536
3537 if (lds_outputs) {
3538 if (ctx.type == PIPE_SHADER_VERTEX) {
3539 if (ctx.shader->noutput)
3540 emit_lds_vs_writes(&ctx);
3541 }
3542 } else if (ring_outputs) {
3543 if (shader->vs_as_es || shader->tes_as_es) {
3544 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3545 ctx.gs_export_gpr_tregs[1] = -1;
3546 ctx.gs_export_gpr_tregs[2] = -1;
3547 ctx.gs_export_gpr_tregs[3] = -1;
3548
3549 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3550 }
3551 } else {
3552 /* Export output */
3553 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3554
3555 for (i = 0, j = 0; i < noutput; i++, j++) {
3556 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3557 output[j].gpr = shader->output[i].gpr;
3558 output[j].elem_size = 3;
3559 output[j].swizzle_x = 0;
3560 output[j].swizzle_y = 1;
3561 output[j].swizzle_z = 2;
3562 output[j].swizzle_w = 3;
3563 output[j].burst_count = 1;
3564 output[j].type = -1;
3565 output[j].op = CF_OP_EXPORT;
3566 switch (ctx.type) {
3567 case PIPE_SHADER_VERTEX:
3568 case PIPE_SHADER_TESS_EVAL:
3569 switch (shader->output[i].name) {
3570 case TGSI_SEMANTIC_POSITION:
3571 output[j].array_base = 60;
3572 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3573 pos_emitted = true;
3574 break;
3575
3576 case TGSI_SEMANTIC_PSIZE:
3577 output[j].array_base = 61;
3578 output[j].swizzle_y = 7;
3579 output[j].swizzle_z = 7;
3580 output[j].swizzle_w = 7;
3581 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3582 pos_emitted = true;
3583 break;
3584 case TGSI_SEMANTIC_EDGEFLAG:
3585 output[j].array_base = 61;
3586 output[j].swizzle_x = 7;
3587 output[j].swizzle_y = 0;
3588 output[j].swizzle_z = 7;
3589 output[j].swizzle_w = 7;
3590 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3591 pos_emitted = true;
3592 break;
3593 case TGSI_SEMANTIC_LAYER:
3594 /* spi_sid is 0 for outputs that are
3595 * not consumed by PS */
3596 if (shader->output[i].spi_sid) {
3597 output[j].array_base = next_param_base++;
3598 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3599 j++;
3600 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3601 }
3602 output[j].array_base = 61;
3603 output[j].swizzle_x = 7;
3604 output[j].swizzle_y = 7;
3605 output[j].swizzle_z = 0;
3606 output[j].swizzle_w = 7;
3607 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3608 pos_emitted = true;
3609 break;
3610 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3611 /* spi_sid is 0 for outputs that are
3612 * not consumed by PS */
3613 if (shader->output[i].spi_sid) {
3614 output[j].array_base = next_param_base++;
3615 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3616 j++;
3617 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3618 }
3619 output[j].array_base = 61;
3620 output[j].swizzle_x = 7;
3621 output[j].swizzle_y = 7;
3622 output[j].swizzle_z = 7;
3623 output[j].swizzle_w = 0;
3624 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3625 pos_emitted = true;
3626 break;
3627 case TGSI_SEMANTIC_CLIPVERTEX:
3628 j--;
3629 break;
3630 case TGSI_SEMANTIC_CLIPDIST:
3631 output[j].array_base = next_clip_base++;
3632 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3633 pos_emitted = true;
3634 /* spi_sid is 0 for clipdistance outputs that were generated
3635 * for clipvertex - we don't need to pass them to PS */
3636 if (shader->output[i].spi_sid) {
3637 j++;
3638 /* duplicate it as PARAM to pass to the pixel shader */
3639 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3640 output[j].array_base = next_param_base++;
3641 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3642 }
3643 break;
3644 case TGSI_SEMANTIC_FOG:
3645 output[j].swizzle_y = 4; /* 0 */
3646 output[j].swizzle_z = 4; /* 0 */
3647 output[j].swizzle_w = 5; /* 1 */
3648 break;
3649 case TGSI_SEMANTIC_PRIMID:
3650 output[j].swizzle_x = 2;
3651 output[j].swizzle_y = 4; /* 0 */
3652 output[j].swizzle_z = 4; /* 0 */
3653 output[j].swizzle_w = 4; /* 0 */
3654 break;
3655 }
3656
3657 break;
3658 case PIPE_SHADER_FRAGMENT:
3659 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3660 /* never export more colors than the number of CBs */
3661 if (shader->output[i].sid >= max_color_exports) {
3662 /* skip export */
3663 j--;
3664 continue;
3665 }
3666 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3667 output[j].array_base = shader->output[i].sid;
3668 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3669 shader->nr_ps_color_exports++;
3670 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3671 for (k = 1; k < max_color_exports; k++) {
3672 j++;
3673 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3674 output[j].gpr = shader->output[i].gpr;
3675 output[j].elem_size = 3;
3676 output[j].swizzle_x = 0;
3677 output[j].swizzle_y = 1;
3678 output[j].swizzle_z = 2;
3679 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3680 output[j].burst_count = 1;
3681 output[j].array_base = k;
3682 output[j].op = CF_OP_EXPORT;
3683 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3684 shader->nr_ps_color_exports++;
3685 }
3686 }
3687 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3688 output[j].array_base = 61;
3689 output[j].swizzle_x = 2;
3690 output[j].swizzle_y = 7;
3691 output[j].swizzle_z = output[j].swizzle_w = 7;
3692 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3693 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3694 output[j].array_base = 61;
3695 output[j].swizzle_x = 7;
3696 output[j].swizzle_y = 1;
3697 output[j].swizzle_z = output[j].swizzle_w = 7;
3698 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3699 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3700 output[j].array_base = 61;
3701 output[j].swizzle_x = 7;
3702 output[j].swizzle_y = 7;
3703 output[j].swizzle_z = 0;
3704 output[j].swizzle_w = 7;
3705 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3706 } else {
3707 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3708 r = -EINVAL;
3709 goto out_err;
3710 }
3711 break;
3712 case PIPE_SHADER_TESS_CTRL:
3713 break;
3714 default:
3715 R600_ERR("unsupported processor type %d\n", ctx.type);
3716 r = -EINVAL;
3717 goto out_err;
3718 }
3719
3720 if (output[j].type==-1) {
3721 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3722 output[j].array_base = next_param_base++;
3723 }
3724 }
3725
3726 /* add fake position export */
3727 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3728 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3729 output[j].gpr = 0;
3730 output[j].elem_size = 3;
3731 output[j].swizzle_x = 7;
3732 output[j].swizzle_y = 7;
3733 output[j].swizzle_z = 7;
3734 output[j].swizzle_w = 7;
3735 output[j].burst_count = 1;
3736 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3737 output[j].array_base = 60;
3738 output[j].op = CF_OP_EXPORT;
3739 j++;
3740 }
3741
3742 /* add fake param output for vertex shader if no param is exported */
3743 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3744 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3745 output[j].gpr = 0;
3746 output[j].elem_size = 3;
3747 output[j].swizzle_x = 7;
3748 output[j].swizzle_y = 7;
3749 output[j].swizzle_z = 7;
3750 output[j].swizzle_w = 7;
3751 output[j].burst_count = 1;
3752 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3753 output[j].array_base = 0;
3754 output[j].op = CF_OP_EXPORT;
3755 j++;
3756 }
3757
3758 /* add fake pixel export */
3759 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3760 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3761 output[j].gpr = 0;
3762 output[j].elem_size = 3;
3763 output[j].swizzle_x = 7;
3764 output[j].swizzle_y = 7;
3765 output[j].swizzle_z = 7;
3766 output[j].swizzle_w = 7;
3767 output[j].burst_count = 1;
3768 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3769 output[j].array_base = 0;
3770 output[j].op = CF_OP_EXPORT;
3771 j++;
3772 shader->nr_ps_color_exports++;
3773 }
3774
3775 noutput = j;
3776
3777 /* set export done on last export of each type */
3778 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
3779 if (!(output_done & (1 << output[i].type))) {
3780 output_done |= (1 << output[i].type);
3781 output[i].op = CF_OP_EXPORT_DONE;
3782 }
3783 }
3784 /* add output to bytecode */
3785 for (i = 0; i < noutput; i++) {
3786 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3787 if (r)
3788 goto out_err;
3789 }
3790 }
3791
3792 /* add program end */
3793 if (ctx.bc->chip_class == CAYMAN)
3794 cm_bytecode_add_cf_end(ctx.bc);
3795 else {
3796 const struct cf_op_info *last = NULL;
3797
3798 if (ctx.bc->cf_last)
3799 last = r600_isa_cf(ctx.bc->cf_last->op);
3800
3801 /* alu clause instructions don't have EOP bit, so add NOP */
3802 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS || ctx.bc->cf_last->op == CF_OP_POP || ctx.bc->cf_last->op == CF_OP_GDS)
3803 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3804
3805 ctx.bc->cf_last->end_of_program = 1;
3806 }
3807
3808 /* check GPR limit - we have 124 = 128 - 4
3809 * (4 are reserved as alu clause temporary registers) */
3810 if (ctx.bc->ngpr > 124) {
3811 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3812 r = -ENOMEM;
3813 goto out_err;
3814 }
3815
3816 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3817 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3818 return r;
3819 }
3820
3821 free(ctx.literals);
3822 tgsi_parse_free(&ctx.parse);
3823 return 0;
3824 out_err:
3825 free(ctx.literals);
3826 tgsi_parse_free(&ctx.parse);
3827 return r;
3828 }
3829
3830 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3831 {
3832 const unsigned tgsi_opcode =
3833 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3834 R600_ERR("%s tgsi opcode unsupported\n",
3835 tgsi_get_opcode_name(tgsi_opcode));
3836 return -EINVAL;
3837 }
3838
3839 static int tgsi_end(struct r600_shader_ctx *ctx)
3840 {
3841 return 0;
3842 }
3843
3844 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3845 const struct r600_shader_src *shader_src,
3846 unsigned chan)
3847 {
3848 bc_src->sel = shader_src->sel;
3849 bc_src->chan = shader_src->swizzle[chan];
3850 bc_src->neg = shader_src->neg;
3851 bc_src->abs = shader_src->abs;
3852 bc_src->rel = shader_src->rel;
3853 bc_src->value = shader_src->value[bc_src->chan];
3854 bc_src->kc_bank = shader_src->kc_bank;
3855 bc_src->kc_rel = shader_src->kc_rel;
3856 }
3857
3858 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3859 {
3860 bc_src->abs = 1;
3861 bc_src->neg = 0;
3862 }
3863
3864 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3865 {
3866 bc_src->neg = !bc_src->neg;
3867 }
3868
3869 static void tgsi_dst(struct r600_shader_ctx *ctx,
3870 const struct tgsi_full_dst_register *tgsi_dst,
3871 unsigned swizzle,
3872 struct r600_bytecode_alu_dst *r600_dst)
3873 {
3874 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3875
3876 r600_dst->sel = tgsi_dst->Register.Index;
3877 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3878 r600_dst->chan = swizzle;
3879 r600_dst->write = 1;
3880 if (inst->Instruction.Saturate) {
3881 r600_dst->clamp = 1;
3882 }
3883 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3884 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3885 return;
3886 }
3887 }
3888 if (tgsi_dst->Register.Indirect)
3889 r600_dst->rel = V_SQ_REL_RELATIVE;
3890
3891 }
3892
3893 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap)
3894 {
3895 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3896 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3897 struct r600_bytecode_alu alu;
3898 int i, j, r, lasti = tgsi_last_instruction(write_mask);
3899 int use_tmp = 0;
3900
3901 if (singledest) {
3902 switch (write_mask) {
3903 case 0x1:
3904 write_mask = 0x3;
3905 break;
3906 case 0x2:
3907 use_tmp = 1;
3908 write_mask = 0x3;
3909 break;
3910 case 0x4:
3911 write_mask = 0xc;
3912 break;
3913 case 0x8:
3914 write_mask = 0xc;
3915 use_tmp = 3;
3916 break;
3917 }
3918 }
3919
3920 lasti = tgsi_last_instruction(write_mask);
3921 for (i = 0; i <= lasti; i++) {
3922
3923 if (!(write_mask & (1 << i)))
3924 continue;
3925
3926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3927
3928 if (singledest) {
3929 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3930 if (use_tmp) {
3931 alu.dst.sel = ctx->temp_reg;
3932 alu.dst.chan = i;
3933 alu.dst.write = 1;
3934 }
3935 if (i == 1 || i == 3)
3936 alu.dst.write = 0;
3937 } else
3938 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3939
3940 alu.op = ctx->inst_info->op;
3941 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
3942 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3943 } else if (!swap) {
3944 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
3945 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
3946 }
3947 } else {
3948 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
3949 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
3950 }
3951
3952 /* handle some special cases */
3953 if (i == 1 || i == 3) {
3954 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
3955 case TGSI_OPCODE_DABS:
3956 r600_bytecode_src_set_abs(&alu.src[0]);
3957 break;
3958 default:
3959 break;
3960 }
3961 }
3962 if (i == lasti) {
3963 alu.last = 1;
3964 }
3965 r = r600_bytecode_add_alu(ctx->bc, &alu);
3966 if (r)
3967 return r;
3968 }
3969
3970 if (use_tmp) {
3971 write_mask = inst->Dst[0].Register.WriteMask;
3972
3973 /* move result from temp to dst */
3974 for (i = 0; i <= lasti; i++) {
3975 if (!(write_mask & (1 << i)))
3976 continue;
3977
3978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3979 alu.op = ALU_OP1_MOV;
3980 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3981 alu.src[0].sel = ctx->temp_reg;
3982 alu.src[0].chan = use_tmp - 1;
3983 alu.last = (i == lasti);
3984
3985 r = r600_bytecode_add_alu(ctx->bc, &alu);
3986 if (r)
3987 return r;
3988 }
3989 }
3990 return 0;
3991 }
3992
3993 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
3994 {
3995 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3996 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3997 /* confirm writemasking */
3998 if ((write_mask & 0x3) != 0x3 &&
3999 (write_mask & 0xc) != 0xc) {
4000 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4001 return -1;
4002 }
4003 return tgsi_op2_64_params(ctx, false, false);
4004 }
4005
4006 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4007 {
4008 return tgsi_op2_64_params(ctx, true, false);
4009 }
4010
4011 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4012 {
4013 return tgsi_op2_64_params(ctx, true, true);
4014 }
4015
4016 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4017 {
4018 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4019 struct r600_bytecode_alu alu;
4020 int i, j, r;
4021 int lasti = 3;
4022 int tmp = r600_get_temp(ctx);
4023
4024 for (i = 0; i < lasti + 1; i++) {
4025
4026 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4027 alu.op = ctx->inst_info->op;
4028 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4029 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4030 }
4031
4032 if (inst->Dst[0].Register.WriteMask & (1 << i))
4033 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4034 else
4035 alu.dst.sel = tmp;
4036
4037 alu.dst.chan = i;
4038 alu.is_op3 = 1;
4039 if (i == lasti) {
4040 alu.last = 1;
4041 }
4042 r = r600_bytecode_add_alu(ctx->bc, &alu);
4043 if (r)
4044 return r;
4045 }
4046 return 0;
4047 }
4048
4049 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4050 {
4051 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4052 struct r600_bytecode_alu alu;
4053 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4054 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4055 /* use temp register if trans_only and more than one dst component */
4056 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4057 unsigned op = ctx->inst_info->op;
4058
4059 if (op == ALU_OP2_MUL_IEEE &&
4060 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4061 op = ALU_OP2_MUL;
4062
4063 for (i = 0; i <= lasti; i++) {
4064 if (!(write_mask & (1 << i)))
4065 continue;
4066
4067 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4068 if (use_tmp) {
4069 alu.dst.sel = ctx->temp_reg;
4070 alu.dst.chan = i;
4071 alu.dst.write = 1;
4072 } else
4073 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4074
4075 alu.op = op;
4076 if (!swap) {
4077 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4078 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4079 }
4080 } else {
4081 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4082 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4083 }
4084 if (i == lasti || trans_only) {
4085 alu.last = 1;
4086 }
4087 r = r600_bytecode_add_alu(ctx->bc, &alu);
4088 if (r)
4089 return r;
4090 }
4091
4092 if (use_tmp) {
4093 /* move result from temp to dst */
4094 for (i = 0; i <= lasti; i++) {
4095 if (!(write_mask & (1 << i)))
4096 continue;
4097
4098 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4099 alu.op = ALU_OP1_MOV;
4100 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4101 alu.src[0].sel = ctx->temp_reg;
4102 alu.src[0].chan = i;
4103 alu.last = (i == lasti);
4104
4105 r = r600_bytecode_add_alu(ctx->bc, &alu);
4106 if (r)
4107 return r;
4108 }
4109 }
4110 return 0;
4111 }
4112
4113 static int tgsi_op2(struct r600_shader_ctx *ctx)
4114 {
4115 return tgsi_op2_s(ctx, 0, 0);
4116 }
4117
4118 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4119 {
4120 return tgsi_op2_s(ctx, 1, 0);
4121 }
4122
4123 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4124 {
4125 return tgsi_op2_s(ctx, 0, 1);
4126 }
4127
4128 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4129 {
4130 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4131 struct r600_bytecode_alu alu;
4132 int i, r;
4133 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4134
4135 for (i = 0; i < lasti + 1; i++) {
4136
4137 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4138 continue;
4139 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4140 alu.op = ctx->inst_info->op;
4141
4142 alu.src[0].sel = V_SQ_ALU_SRC_0;
4143
4144 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4145
4146 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4147
4148 if (i == lasti) {
4149 alu.last = 1;
4150 }
4151 r = r600_bytecode_add_alu(ctx->bc, &alu);
4152 if (r)
4153 return r;
4154 }
4155 return 0;
4156
4157 }
4158
4159 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4160 {
4161 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4162 struct r600_bytecode_alu alu;
4163 int i, r;
4164 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4165
4166 for (i = 0; i < lasti + 1; i++) {
4167
4168 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4169 continue;
4170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4171 alu.op = ALU_OP1_MOV;
4172
4173 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4174
4175 if (i == 1 || i == 3)
4176 r600_bytecode_src_toggle_neg(&alu.src[0]);
4177 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4178
4179 if (i == lasti) {
4180 alu.last = 1;
4181 }
4182 r = r600_bytecode_add_alu(ctx->bc, &alu);
4183 if (r)
4184 return r;
4185 }
4186 return 0;
4187
4188 }
4189
4190 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4191 {
4192 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4193 struct r600_bytecode_alu alu;
4194 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4195 int i, j, r;
4196
4197 for (i = 0; i <= 3; i++) {
4198 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4199 alu.op = ctx->inst_info->op;
4200
4201 alu.dst.sel = ctx->temp_reg;
4202 alu.dst.chan = i;
4203 alu.dst.write = 1;
4204 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4205 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4206 }
4207
4208 if (i == 3)
4209 alu.last = 1;
4210
4211 r = r600_bytecode_add_alu(ctx->bc, &alu);
4212 if (r)
4213 return r;
4214 }
4215
4216 /* Replicate significand result across channels. */
4217 for (i = 0; i <= 3; i++) {
4218 if (!(write_mask & (1 << i)))
4219 continue;
4220
4221 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4222 alu.op = ALU_OP1_MOV;
4223 alu.src[0].chan = (i & 1) + 2;
4224 alu.src[0].sel = ctx->temp_reg;
4225
4226 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4227 alu.dst.write = 1;
4228 alu.last = 1;
4229 r = r600_bytecode_add_alu(ctx->bc, &alu);
4230 if (r)
4231 return r;
4232 }
4233
4234 for (i = 0; i <= 3; i++) {
4235 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4236 /* MOV third channels to writemask dst1 */
4237 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4238 alu.op = ALU_OP1_MOV;
4239 alu.src[0].chan = 1;
4240 alu.src[0].sel = ctx->temp_reg;
4241
4242 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4243 alu.last = 1;
4244 r = r600_bytecode_add_alu(ctx->bc, &alu);
4245 if (r)
4246 return r;
4247 break;
4248 }
4249 }
4250 return 0;
4251 }
4252
4253
4254 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4255 {
4256 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4257 struct r600_bytecode_alu alu;
4258 int i, r;
4259 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4260
4261 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4262 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4263
4264 for (i = 0; i <= (lasti+1)/2; i++) {
4265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4266 alu.op = ctx->inst_info->op;
4267
4268 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4269 alu.dst.sel = ctx->temp_reg;
4270 alu.dst.chan = i;
4271 alu.dst.write = 1;
4272 alu.last = 1;
4273
4274 r = r600_bytecode_add_alu(ctx->bc, &alu);
4275 if (r)
4276 return r;
4277 }
4278
4279 for (i = 0; i <= lasti; i++) {
4280 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4281 alu.op = ALU_OP1_FLT32_TO_FLT64;
4282
4283 alu.src[0].chan = i/2;
4284 if (i%2 == 0)
4285 alu.src[0].sel = ctx->temp_reg;
4286 else {
4287 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4288 alu.src[0].value = 0x0;
4289 }
4290 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4291 alu.last = i == lasti;
4292
4293 r = r600_bytecode_add_alu(ctx->bc, &alu);
4294 if (r)
4295 return r;
4296 }
4297
4298 return 0;
4299 }
4300
4301 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4302 {
4303 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4304 struct r600_bytecode_alu alu;
4305 int i, r;
4306 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4307
4308 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4309 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4310
4311 for (i = 0; i <= lasti; i++) {
4312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4313 alu.op = ALU_OP1_FLT64_TO_FLT32;
4314
4315 r600_bytecode_src(&alu.src[0], &ctx->src[0], fp64_switch(i));
4316 alu.dst.chan = i;
4317 alu.dst.sel = ctx->temp_reg;
4318 alu.dst.write = i%2 == 0;
4319 alu.last = i == lasti;
4320
4321 r = r600_bytecode_add_alu(ctx->bc, &alu);
4322 if (r)
4323 return r;
4324 }
4325
4326 for (i = 0; i <= (lasti+1)/2; i++) {
4327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4328 alu.op = ctx->inst_info->op;
4329
4330 alu.src[0].chan = i*2;
4331 alu.src[0].sel = ctx->temp_reg;
4332 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4333 alu.last = 1;
4334
4335 r = r600_bytecode_add_alu(ctx->bc, &alu);
4336 if (r)
4337 return r;
4338 }
4339
4340 return 0;
4341 }
4342
4343 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4344 unsigned op,
4345 int dst_reg,
4346 struct r600_shader_src *src,
4347 bool abs)
4348 {
4349 struct r600_bytecode_alu alu;
4350 const int last_slot = 3;
4351 int r;
4352
4353 /* these have to write the result to X/Y by the looks of it */
4354 for (int i = 0 ; i < last_slot; i++) {
4355 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4356 alu.op = op;
4357
4358 r600_bytecode_src(&alu.src[0], src, 1);
4359 r600_bytecode_src(&alu.src[1], src, 0);
4360
4361 if (abs)
4362 r600_bytecode_src_set_abs(&alu.src[1]);
4363
4364 alu.dst.sel = dst_reg;
4365 alu.dst.chan = i;
4366 alu.dst.write = (i == 0 || i == 1);
4367
4368 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4369 alu.last = 1;
4370 r = r600_bytecode_add_alu(bc, &alu);
4371 if (r)
4372 return r;
4373 }
4374
4375 return 0;
4376 }
4377
4378 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4379 {
4380 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4381 int i, r;
4382 struct r600_bytecode_alu alu;
4383 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4384 int t1 = ctx->temp_reg;
4385
4386 /* should only be one src regs */
4387 assert(inst->Instruction.NumSrcRegs == 1);
4388
4389 /* only support one double at a time */
4390 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4391 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4392
4393 r = cayman_emit_unary_double_raw(
4394 ctx->bc, ctx->inst_info->op, t1,
4395 &ctx->src[0],
4396 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4397 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4398 if (r)
4399 return r;
4400
4401 for (i = 0 ; i <= lasti; i++) {
4402 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4403 continue;
4404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4405 alu.op = ALU_OP1_MOV;
4406 alu.src[0].sel = t1;
4407 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4408 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4409 alu.dst.write = 1;
4410 if (i == lasti)
4411 alu.last = 1;
4412 r = r600_bytecode_add_alu(ctx->bc, &alu);
4413 if (r)
4414 return r;
4415 }
4416 return 0;
4417 }
4418
4419 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4420 {
4421 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4422 int i, j, r;
4423 struct r600_bytecode_alu alu;
4424 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4425
4426 for (i = 0 ; i < last_slot; i++) {
4427 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4428 alu.op = ctx->inst_info->op;
4429 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4430 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4431
4432 /* RSQ should take the absolute value of src */
4433 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4434 r600_bytecode_src_set_abs(&alu.src[j]);
4435 }
4436 }
4437 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4438 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4439
4440 if (i == last_slot - 1)
4441 alu.last = 1;
4442 r = r600_bytecode_add_alu(ctx->bc, &alu);
4443 if (r)
4444 return r;
4445 }
4446 return 0;
4447 }
4448
4449 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4450 {
4451 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4452 int i, j, k, r;
4453 struct r600_bytecode_alu alu;
4454 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4455 int t1 = ctx->temp_reg;
4456
4457 for (k = 0; k <= lasti; k++) {
4458 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4459 continue;
4460
4461 for (i = 0 ; i < 4; i++) {
4462 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4463 alu.op = ctx->inst_info->op;
4464 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4465 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4466 }
4467 alu.dst.sel = t1;
4468 alu.dst.chan = i;
4469 alu.dst.write = (i == k);
4470 if (i == 3)
4471 alu.last = 1;
4472 r = r600_bytecode_add_alu(ctx->bc, &alu);
4473 if (r)
4474 return r;
4475 }
4476 }
4477
4478 for (i = 0 ; i <= lasti; i++) {
4479 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4480 continue;
4481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4482 alu.op = ALU_OP1_MOV;
4483 alu.src[0].sel = t1;
4484 alu.src[0].chan = i;
4485 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4486 alu.dst.write = 1;
4487 if (i == lasti)
4488 alu.last = 1;
4489 r = r600_bytecode_add_alu(ctx->bc, &alu);
4490 if (r)
4491 return r;
4492 }
4493
4494 return 0;
4495 }
4496
4497
4498 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4499 {
4500 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4501 int i, j, k, r;
4502 struct r600_bytecode_alu alu;
4503 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4504 int t1 = ctx->temp_reg;
4505
4506 /* t1 would get overwritten below if we actually tried to
4507 * multiply two pairs of doubles at a time. */
4508 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4509 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4510
4511 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4512
4513 for (i = 0; i < 4; i++) {
4514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4515 alu.op = ctx->inst_info->op;
4516 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4517 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4518 }
4519 alu.dst.sel = t1;
4520 alu.dst.chan = i;
4521 alu.dst.write = 1;
4522 if (i == 3)
4523 alu.last = 1;
4524 r = r600_bytecode_add_alu(ctx->bc, &alu);
4525 if (r)
4526 return r;
4527 }
4528
4529 for (i = 0; i <= lasti; i++) {
4530 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4531 continue;
4532 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4533 alu.op = ALU_OP1_MOV;
4534 alu.src[0].sel = t1;
4535 alu.src[0].chan = i;
4536 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4537 alu.dst.write = 1;
4538 if (i == lasti)
4539 alu.last = 1;
4540 r = r600_bytecode_add_alu(ctx->bc, &alu);
4541 if (r)
4542 return r;
4543 }
4544
4545 return 0;
4546 }
4547
4548 /*
4549 * Emit RECIP_64 + MUL_64 to implement division.
4550 */
4551 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4552 {
4553 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4554 int r;
4555 struct r600_bytecode_alu alu;
4556 int t1 = ctx->temp_reg;
4557 int k;
4558
4559 /* Only support one double at a time. This is the same constraint as
4560 * in DMUL lowering. */
4561 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4562 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4563
4564 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4565
4566 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4567 if (r)
4568 return r;
4569
4570 for (int i = 0; i < 4; i++) {
4571 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4572 alu.op = ALU_OP2_MUL_64;
4573
4574 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4575
4576 alu.src[1].sel = t1;
4577 alu.src[1].chan = (i == 3) ? 0 : 1;
4578
4579 alu.dst.sel = t1;
4580 alu.dst.chan = i;
4581 alu.dst.write = 1;
4582 if (i == 3)
4583 alu.last = 1;
4584 r = r600_bytecode_add_alu(ctx->bc, &alu);
4585 if (r)
4586 return r;
4587 }
4588
4589 for (int i = 0; i < 2; i++) {
4590 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4591 alu.op = ALU_OP1_MOV;
4592 alu.src[0].sel = t1;
4593 alu.src[0].chan = i;
4594 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4595 alu.dst.write = 1;
4596 if (i == 1)
4597 alu.last = 1;
4598 r = r600_bytecode_add_alu(ctx->bc, &alu);
4599 if (r)
4600 return r;
4601 }
4602 return 0;
4603 }
4604
4605 /*
4606 * r600 - trunc to -PI..PI range
4607 * r700 - normalize by dividing by 2PI
4608 * see fdo bug 27901
4609 */
4610 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4611 {
4612 int r;
4613 struct r600_bytecode_alu alu;
4614
4615 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4616 alu.op = ALU_OP3_MULADD;
4617 alu.is_op3 = 1;
4618
4619 alu.dst.chan = 0;
4620 alu.dst.sel = ctx->temp_reg;
4621 alu.dst.write = 1;
4622
4623 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4624
4625 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4626 alu.src[1].chan = 0;
4627 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4628 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4629 alu.src[2].chan = 0;
4630 alu.last = 1;
4631 r = r600_bytecode_add_alu(ctx->bc, &alu);
4632 if (r)
4633 return r;
4634
4635 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4636 alu.op = ALU_OP1_FRACT;
4637
4638 alu.dst.chan = 0;
4639 alu.dst.sel = ctx->temp_reg;
4640 alu.dst.write = 1;
4641
4642 alu.src[0].sel = ctx->temp_reg;
4643 alu.src[0].chan = 0;
4644 alu.last = 1;
4645 r = r600_bytecode_add_alu(ctx->bc, &alu);
4646 if (r)
4647 return r;
4648
4649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4650 alu.op = ALU_OP3_MULADD;
4651 alu.is_op3 = 1;
4652
4653 alu.dst.chan = 0;
4654 alu.dst.sel = ctx->temp_reg;
4655 alu.dst.write = 1;
4656
4657 alu.src[0].sel = ctx->temp_reg;
4658 alu.src[0].chan = 0;
4659
4660 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4661 alu.src[1].chan = 0;
4662 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4663 alu.src[2].chan = 0;
4664
4665 if (ctx->bc->chip_class == R600) {
4666 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4667 alu.src[2].value = u_bitcast_f2u(-M_PI);
4668 } else {
4669 alu.src[1].sel = V_SQ_ALU_SRC_1;
4670 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4671 alu.src[2].neg = 1;
4672 }
4673
4674 alu.last = 1;
4675 r = r600_bytecode_add_alu(ctx->bc, &alu);
4676 if (r)
4677 return r;
4678 return 0;
4679 }
4680
4681 static int cayman_trig(struct r600_shader_ctx *ctx)
4682 {
4683 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4684 struct r600_bytecode_alu alu;
4685 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4686 int i, r;
4687
4688 r = tgsi_setup_trig(ctx);
4689 if (r)
4690 return r;
4691
4692
4693 for (i = 0; i < last_slot; i++) {
4694 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4695 alu.op = ctx->inst_info->op;
4696 alu.dst.chan = i;
4697
4698 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4699 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4700
4701 alu.src[0].sel = ctx->temp_reg;
4702 alu.src[0].chan = 0;
4703 if (i == last_slot - 1)
4704 alu.last = 1;
4705 r = r600_bytecode_add_alu(ctx->bc, &alu);
4706 if (r)
4707 return r;
4708 }
4709 return 0;
4710 }
4711
4712 static int tgsi_trig(struct r600_shader_ctx *ctx)
4713 {
4714 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4715 struct r600_bytecode_alu alu;
4716 int i, r;
4717 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4718
4719 r = tgsi_setup_trig(ctx);
4720 if (r)
4721 return r;
4722
4723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4724 alu.op = ctx->inst_info->op;
4725 alu.dst.chan = 0;
4726 alu.dst.sel = ctx->temp_reg;
4727 alu.dst.write = 1;
4728
4729 alu.src[0].sel = ctx->temp_reg;
4730 alu.src[0].chan = 0;
4731 alu.last = 1;
4732 r = r600_bytecode_add_alu(ctx->bc, &alu);
4733 if (r)
4734 return r;
4735
4736 /* replicate result */
4737 for (i = 0; i < lasti + 1; i++) {
4738 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4739 continue;
4740
4741 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4742 alu.op = ALU_OP1_MOV;
4743
4744 alu.src[0].sel = ctx->temp_reg;
4745 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4746 if (i == lasti)
4747 alu.last = 1;
4748 r = r600_bytecode_add_alu(ctx->bc, &alu);
4749 if (r)
4750 return r;
4751 }
4752 return 0;
4753 }
4754
4755 static int tgsi_kill(struct r600_shader_ctx *ctx)
4756 {
4757 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4758 struct r600_bytecode_alu alu;
4759 int i, r;
4760
4761 for (i = 0; i < 4; i++) {
4762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4763 alu.op = ctx->inst_info->op;
4764
4765 alu.dst.chan = i;
4766
4767 alu.src[0].sel = V_SQ_ALU_SRC_0;
4768
4769 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4770 alu.src[1].sel = V_SQ_ALU_SRC_1;
4771 alu.src[1].neg = 1;
4772 } else {
4773 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4774 }
4775 if (i == 3) {
4776 alu.last = 1;
4777 }
4778 r = r600_bytecode_add_alu(ctx->bc, &alu);
4779 if (r)
4780 return r;
4781 }
4782
4783 /* kill must be last in ALU */
4784 ctx->bc->force_add_cf = 1;
4785 ctx->shader->uses_kill = TRUE;
4786 return 0;
4787 }
4788
4789 static int tgsi_lit(struct r600_shader_ctx *ctx)
4790 {
4791 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4792 struct r600_bytecode_alu alu;
4793 int r;
4794
4795 /* tmp.x = max(src.y, 0.0) */
4796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4797 alu.op = ALU_OP2_MAX;
4798 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4799 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4800 alu.src[1].chan = 1;
4801
4802 alu.dst.sel = ctx->temp_reg;
4803 alu.dst.chan = 0;
4804 alu.dst.write = 1;
4805
4806 alu.last = 1;
4807 r = r600_bytecode_add_alu(ctx->bc, &alu);
4808 if (r)
4809 return r;
4810
4811 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4812 {
4813 int chan;
4814 int sel;
4815 unsigned i;
4816
4817 if (ctx->bc->chip_class == CAYMAN) {
4818 for (i = 0; i < 3; i++) {
4819 /* tmp.z = log(tmp.x) */
4820 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4821 alu.op = ALU_OP1_LOG_CLAMPED;
4822 alu.src[0].sel = ctx->temp_reg;
4823 alu.src[0].chan = 0;
4824 alu.dst.sel = ctx->temp_reg;
4825 alu.dst.chan = i;
4826 if (i == 2) {
4827 alu.dst.write = 1;
4828 alu.last = 1;
4829 } else
4830 alu.dst.write = 0;
4831
4832 r = r600_bytecode_add_alu(ctx->bc, &alu);
4833 if (r)
4834 return r;
4835 }
4836 } else {
4837 /* tmp.z = log(tmp.x) */
4838 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4839 alu.op = ALU_OP1_LOG_CLAMPED;
4840 alu.src[0].sel = ctx->temp_reg;
4841 alu.src[0].chan = 0;
4842 alu.dst.sel = ctx->temp_reg;
4843 alu.dst.chan = 2;
4844 alu.dst.write = 1;
4845 alu.last = 1;
4846 r = r600_bytecode_add_alu(ctx->bc, &alu);
4847 if (r)
4848 return r;
4849 }
4850
4851 chan = alu.dst.chan;
4852 sel = alu.dst.sel;
4853
4854 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4856 alu.op = ALU_OP3_MUL_LIT;
4857 alu.src[0].sel = sel;
4858 alu.src[0].chan = chan;
4859 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4860 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4861 alu.dst.sel = ctx->temp_reg;
4862 alu.dst.chan = 0;
4863 alu.dst.write = 1;
4864 alu.is_op3 = 1;
4865 alu.last = 1;
4866 r = r600_bytecode_add_alu(ctx->bc, &alu);
4867 if (r)
4868 return r;
4869
4870 if (ctx->bc->chip_class == CAYMAN) {
4871 for (i = 0; i < 3; i++) {
4872 /* dst.z = exp(tmp.x) */
4873 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4874 alu.op = ALU_OP1_EXP_IEEE;
4875 alu.src[0].sel = ctx->temp_reg;
4876 alu.src[0].chan = 0;
4877 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4878 if (i == 2) {
4879 alu.dst.write = 1;
4880 alu.last = 1;
4881 } else
4882 alu.dst.write = 0;
4883 r = r600_bytecode_add_alu(ctx->bc, &alu);
4884 if (r)
4885 return r;
4886 }
4887 } else {
4888 /* dst.z = exp(tmp.x) */
4889 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4890 alu.op = ALU_OP1_EXP_IEEE;
4891 alu.src[0].sel = ctx->temp_reg;
4892 alu.src[0].chan = 0;
4893 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
4894 alu.last = 1;
4895 r = r600_bytecode_add_alu(ctx->bc, &alu);
4896 if (r)
4897 return r;
4898 }
4899 }
4900
4901 /* dst.x, <- 1.0 */
4902 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4903 alu.op = ALU_OP1_MOV;
4904 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
4905 alu.src[0].chan = 0;
4906 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4907 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
4908 r = r600_bytecode_add_alu(ctx->bc, &alu);
4909 if (r)
4910 return r;
4911
4912 /* dst.y = max(src.x, 0.0) */
4913 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4914 alu.op = ALU_OP2_MAX;
4915 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4916 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4917 alu.src[1].chan = 0;
4918 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
4919 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
4920 r = r600_bytecode_add_alu(ctx->bc, &alu);
4921 if (r)
4922 return r;
4923
4924 /* dst.w, <- 1.0 */
4925 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4926 alu.op = ALU_OP1_MOV;
4927 alu.src[0].sel = V_SQ_ALU_SRC_1;
4928 alu.src[0].chan = 0;
4929 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
4930 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
4931 alu.last = 1;
4932 r = r600_bytecode_add_alu(ctx->bc, &alu);
4933 if (r)
4934 return r;
4935
4936 return 0;
4937 }
4938
4939 static int tgsi_rsq(struct r600_shader_ctx *ctx)
4940 {
4941 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4942 struct r600_bytecode_alu alu;
4943 int i, r;
4944
4945 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4946
4947 alu.op = ALU_OP1_RECIPSQRT_IEEE;
4948
4949 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4950 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4951 r600_bytecode_src_set_abs(&alu.src[i]);
4952 }
4953 alu.dst.sel = ctx->temp_reg;
4954 alu.dst.write = 1;
4955 alu.last = 1;
4956 r = r600_bytecode_add_alu(ctx->bc, &alu);
4957 if (r)
4958 return r;
4959 /* replicate result */
4960 return tgsi_helper_tempx_replicate(ctx);
4961 }
4962
4963 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
4964 {
4965 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4966 struct r600_bytecode_alu alu;
4967 int i, r;
4968
4969 for (i = 0; i < 4; i++) {
4970 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4971 alu.src[0].sel = ctx->temp_reg;
4972 alu.op = ALU_OP1_MOV;
4973 alu.dst.chan = i;
4974 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4975 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4976 if (i == 3)
4977 alu.last = 1;
4978 r = r600_bytecode_add_alu(ctx->bc, &alu);
4979 if (r)
4980 return r;
4981 }
4982 return 0;
4983 }
4984
4985 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
4986 {
4987 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4988 struct r600_bytecode_alu alu;
4989 int i, r;
4990
4991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4992 alu.op = ctx->inst_info->op;
4993 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
4994 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
4995 }
4996 alu.dst.sel = ctx->temp_reg;
4997 alu.dst.write = 1;
4998 alu.last = 1;
4999 r = r600_bytecode_add_alu(ctx->bc, &alu);
5000 if (r)
5001 return r;
5002 /* replicate result */
5003 return tgsi_helper_tempx_replicate(ctx);
5004 }
5005
5006 static int cayman_pow(struct r600_shader_ctx *ctx)
5007 {
5008 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5009 int i, r;
5010 struct r600_bytecode_alu alu;
5011 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5012
5013 for (i = 0; i < 3; i++) {
5014 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5015 alu.op = ALU_OP1_LOG_IEEE;
5016 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5017 alu.dst.sel = ctx->temp_reg;
5018 alu.dst.chan = i;
5019 alu.dst.write = 1;
5020 if (i == 2)
5021 alu.last = 1;
5022 r = r600_bytecode_add_alu(ctx->bc, &alu);
5023 if (r)
5024 return r;
5025 }
5026
5027 /* b * LOG2(a) */
5028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5029 alu.op = ALU_OP2_MUL;
5030 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5031 alu.src[1].sel = ctx->temp_reg;
5032 alu.dst.sel = ctx->temp_reg;
5033 alu.dst.write = 1;
5034 alu.last = 1;
5035 r = r600_bytecode_add_alu(ctx->bc, &alu);
5036 if (r)
5037 return r;
5038
5039 for (i = 0; i < last_slot; i++) {
5040 /* POW(a,b) = EXP2(b * LOG2(a))*/
5041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5042 alu.op = ALU_OP1_EXP_IEEE;
5043 alu.src[0].sel = ctx->temp_reg;
5044
5045 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5046 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5047 if (i == last_slot - 1)
5048 alu.last = 1;
5049 r = r600_bytecode_add_alu(ctx->bc, &alu);
5050 if (r)
5051 return r;
5052 }
5053 return 0;
5054 }
5055
5056 static int tgsi_pow(struct r600_shader_ctx *ctx)
5057 {
5058 struct r600_bytecode_alu alu;
5059 int r;
5060
5061 /* LOG2(a) */
5062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5063 alu.op = ALU_OP1_LOG_IEEE;
5064 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5065 alu.dst.sel = ctx->temp_reg;
5066 alu.dst.write = 1;
5067 alu.last = 1;
5068 r = r600_bytecode_add_alu(ctx->bc, &alu);
5069 if (r)
5070 return r;
5071 /* b * LOG2(a) */
5072 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5073 alu.op = ALU_OP2_MUL;
5074 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5075 alu.src[1].sel = ctx->temp_reg;
5076 alu.dst.sel = ctx->temp_reg;
5077 alu.dst.write = 1;
5078 alu.last = 1;
5079 r = r600_bytecode_add_alu(ctx->bc, &alu);
5080 if (r)
5081 return r;
5082 /* POW(a,b) = EXP2(b * LOG2(a))*/
5083 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5084 alu.op = ALU_OP1_EXP_IEEE;
5085 alu.src[0].sel = ctx->temp_reg;
5086 alu.dst.sel = ctx->temp_reg;
5087 alu.dst.write = 1;
5088 alu.last = 1;
5089 r = r600_bytecode_add_alu(ctx->bc, &alu);
5090 if (r)
5091 return r;
5092 return tgsi_helper_tempx_replicate(ctx);
5093 }
5094
5095 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5096 {
5097 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5098 struct r600_bytecode_alu alu;
5099 int i, r, j;
5100 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5101 int tmp0 = ctx->temp_reg;
5102 int tmp1 = r600_get_temp(ctx);
5103 int tmp2 = r600_get_temp(ctx);
5104 int tmp3 = r600_get_temp(ctx);
5105 /* Unsigned path:
5106 *
5107 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5108 *
5109 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5110 * 2. tmp0.z = lo (tmp0.x * src2)
5111 * 3. tmp0.w = -tmp0.z
5112 * 4. tmp0.y = hi (tmp0.x * src2)
5113 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5114 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5115 * 7. tmp1.x = tmp0.x - tmp0.w
5116 * 8. tmp1.y = tmp0.x + tmp0.w
5117 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5118 * 10. tmp0.z = hi(tmp0.x * src1) = q
5119 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5120 *
5121 * 12. tmp0.w = src1 - tmp0.y = r
5122 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5123 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5124 *
5125 * if DIV
5126 *
5127 * 15. tmp1.z = tmp0.z + 1 = q + 1
5128 * 16. tmp1.w = tmp0.z - 1 = q - 1
5129 *
5130 * else MOD
5131 *
5132 * 15. tmp1.z = tmp0.w - src2 = r - src2
5133 * 16. tmp1.w = tmp0.w + src2 = r + src2
5134 *
5135 * endif
5136 *
5137 * 17. tmp1.x = tmp1.x & tmp1.y
5138 *
5139 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5140 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5141 *
5142 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5143 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5144 *
5145 * Signed path:
5146 *
5147 * Same as unsigned, using abs values of the operands,
5148 * and fixing the sign of the result in the end.
5149 */
5150
5151 for (i = 0; i < 4; i++) {
5152 if (!(write_mask & (1<<i)))
5153 continue;
5154
5155 if (signed_op) {
5156
5157 /* tmp2.x = -src0 */
5158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5159 alu.op = ALU_OP2_SUB_INT;
5160
5161 alu.dst.sel = tmp2;
5162 alu.dst.chan = 0;
5163 alu.dst.write = 1;
5164
5165 alu.src[0].sel = V_SQ_ALU_SRC_0;
5166
5167 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5168
5169 alu.last = 1;
5170 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5171 return r;
5172
5173 /* tmp2.y = -src1 */
5174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5175 alu.op = ALU_OP2_SUB_INT;
5176
5177 alu.dst.sel = tmp2;
5178 alu.dst.chan = 1;
5179 alu.dst.write = 1;
5180
5181 alu.src[0].sel = V_SQ_ALU_SRC_0;
5182
5183 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5184
5185 alu.last = 1;
5186 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5187 return r;
5188
5189 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5190 /* it will be a sign of the quotient */
5191 if (!mod) {
5192
5193 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5194 alu.op = ALU_OP2_XOR_INT;
5195
5196 alu.dst.sel = tmp2;
5197 alu.dst.chan = 2;
5198 alu.dst.write = 1;
5199
5200 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5201 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5202
5203 alu.last = 1;
5204 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5205 return r;
5206 }
5207
5208 /* tmp2.x = |src0| */
5209 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5210 alu.op = ALU_OP3_CNDGE_INT;
5211 alu.is_op3 = 1;
5212
5213 alu.dst.sel = tmp2;
5214 alu.dst.chan = 0;
5215 alu.dst.write = 1;
5216
5217 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5218 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5219 alu.src[2].sel = tmp2;
5220 alu.src[2].chan = 0;
5221
5222 alu.last = 1;
5223 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5224 return r;
5225
5226 /* tmp2.y = |src1| */
5227 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5228 alu.op = ALU_OP3_CNDGE_INT;
5229 alu.is_op3 = 1;
5230
5231 alu.dst.sel = tmp2;
5232 alu.dst.chan = 1;
5233 alu.dst.write = 1;
5234
5235 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5236 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5237 alu.src[2].sel = tmp2;
5238 alu.src[2].chan = 1;
5239
5240 alu.last = 1;
5241 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5242 return r;
5243
5244 }
5245
5246 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5247 if (ctx->bc->chip_class == CAYMAN) {
5248 /* tmp3.x = u2f(src2) */
5249 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5250 alu.op = ALU_OP1_UINT_TO_FLT;
5251
5252 alu.dst.sel = tmp3;
5253 alu.dst.chan = 0;
5254 alu.dst.write = 1;
5255
5256 if (signed_op) {
5257 alu.src[0].sel = tmp2;
5258 alu.src[0].chan = 1;
5259 } else {
5260 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5261 }
5262
5263 alu.last = 1;
5264 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5265 return r;
5266
5267 /* tmp0.x = recip(tmp3.x) */
5268 for (j = 0 ; j < 3; j++) {
5269 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5270 alu.op = ALU_OP1_RECIP_IEEE;
5271
5272 alu.dst.sel = tmp0;
5273 alu.dst.chan = j;
5274 alu.dst.write = (j == 0);
5275
5276 alu.src[0].sel = tmp3;
5277 alu.src[0].chan = 0;
5278
5279 if (j == 2)
5280 alu.last = 1;
5281 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5282 return r;
5283 }
5284
5285 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5286 alu.op = ALU_OP2_MUL;
5287
5288 alu.src[0].sel = tmp0;
5289 alu.src[0].chan = 0;
5290
5291 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5292 alu.src[1].value = 0x4f800000;
5293
5294 alu.dst.sel = tmp3;
5295 alu.dst.write = 1;
5296 alu.last = 1;
5297 r = r600_bytecode_add_alu(ctx->bc, &alu);
5298 if (r)
5299 return r;
5300
5301 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5302 alu.op = ALU_OP1_FLT_TO_UINT;
5303
5304 alu.dst.sel = tmp0;
5305 alu.dst.chan = 0;
5306 alu.dst.write = 1;
5307
5308 alu.src[0].sel = tmp3;
5309 alu.src[0].chan = 0;
5310
5311 alu.last = 1;
5312 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5313 return r;
5314
5315 } else {
5316 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5317 alu.op = ALU_OP1_RECIP_UINT;
5318
5319 alu.dst.sel = tmp0;
5320 alu.dst.chan = 0;
5321 alu.dst.write = 1;
5322
5323 if (signed_op) {
5324 alu.src[0].sel = tmp2;
5325 alu.src[0].chan = 1;
5326 } else {
5327 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5328 }
5329
5330 alu.last = 1;
5331 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5332 return r;
5333 }
5334
5335 /* 2. tmp0.z = lo (tmp0.x * src2) */
5336 if (ctx->bc->chip_class == CAYMAN) {
5337 for (j = 0 ; j < 4; j++) {
5338 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5339 alu.op = ALU_OP2_MULLO_UINT;
5340
5341 alu.dst.sel = tmp0;
5342 alu.dst.chan = j;
5343 alu.dst.write = (j == 2);
5344
5345 alu.src[0].sel = tmp0;
5346 alu.src[0].chan = 0;
5347 if (signed_op) {
5348 alu.src[1].sel = tmp2;
5349 alu.src[1].chan = 1;
5350 } else {
5351 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5352 }
5353
5354 alu.last = (j == 3);
5355 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5356 return r;
5357 }
5358 } else {
5359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5360 alu.op = ALU_OP2_MULLO_UINT;
5361
5362 alu.dst.sel = tmp0;
5363 alu.dst.chan = 2;
5364 alu.dst.write = 1;
5365
5366 alu.src[0].sel = tmp0;
5367 alu.src[0].chan = 0;
5368 if (signed_op) {
5369 alu.src[1].sel = tmp2;
5370 alu.src[1].chan = 1;
5371 } else {
5372 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5373 }
5374
5375 alu.last = 1;
5376 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5377 return r;
5378 }
5379
5380 /* 3. tmp0.w = -tmp0.z */
5381 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5382 alu.op = ALU_OP2_SUB_INT;
5383
5384 alu.dst.sel = tmp0;
5385 alu.dst.chan = 3;
5386 alu.dst.write = 1;
5387
5388 alu.src[0].sel = V_SQ_ALU_SRC_0;
5389 alu.src[1].sel = tmp0;
5390 alu.src[1].chan = 2;
5391
5392 alu.last = 1;
5393 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5394 return r;
5395
5396 /* 4. tmp0.y = hi (tmp0.x * src2) */
5397 if (ctx->bc->chip_class == CAYMAN) {
5398 for (j = 0 ; j < 4; j++) {
5399 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5400 alu.op = ALU_OP2_MULHI_UINT;
5401
5402 alu.dst.sel = tmp0;
5403 alu.dst.chan = j;
5404 alu.dst.write = (j == 1);
5405
5406 alu.src[0].sel = tmp0;
5407 alu.src[0].chan = 0;
5408
5409 if (signed_op) {
5410 alu.src[1].sel = tmp2;
5411 alu.src[1].chan = 1;
5412 } else {
5413 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5414 }
5415 alu.last = (j == 3);
5416 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5417 return r;
5418 }
5419 } else {
5420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5421 alu.op = ALU_OP2_MULHI_UINT;
5422
5423 alu.dst.sel = tmp0;
5424 alu.dst.chan = 1;
5425 alu.dst.write = 1;
5426
5427 alu.src[0].sel = tmp0;
5428 alu.src[0].chan = 0;
5429
5430 if (signed_op) {
5431 alu.src[1].sel = tmp2;
5432 alu.src[1].chan = 1;
5433 } else {
5434 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5435 }
5436
5437 alu.last = 1;
5438 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5439 return r;
5440 }
5441
5442 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5444 alu.op = ALU_OP3_CNDE_INT;
5445 alu.is_op3 = 1;
5446
5447 alu.dst.sel = tmp0;
5448 alu.dst.chan = 2;
5449 alu.dst.write = 1;
5450
5451 alu.src[0].sel = tmp0;
5452 alu.src[0].chan = 1;
5453 alu.src[1].sel = tmp0;
5454 alu.src[1].chan = 3;
5455 alu.src[2].sel = tmp0;
5456 alu.src[2].chan = 2;
5457
5458 alu.last = 1;
5459 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5460 return r;
5461
5462 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5463 if (ctx->bc->chip_class == CAYMAN) {
5464 for (j = 0 ; j < 4; j++) {
5465 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5466 alu.op = ALU_OP2_MULHI_UINT;
5467
5468 alu.dst.sel = tmp0;
5469 alu.dst.chan = j;
5470 alu.dst.write = (j == 3);
5471
5472 alu.src[0].sel = tmp0;
5473 alu.src[0].chan = 2;
5474
5475 alu.src[1].sel = tmp0;
5476 alu.src[1].chan = 0;
5477
5478 alu.last = (j == 3);
5479 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5480 return r;
5481 }
5482 } else {
5483 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5484 alu.op = ALU_OP2_MULHI_UINT;
5485
5486 alu.dst.sel = tmp0;
5487 alu.dst.chan = 3;
5488 alu.dst.write = 1;
5489
5490 alu.src[0].sel = tmp0;
5491 alu.src[0].chan = 2;
5492
5493 alu.src[1].sel = tmp0;
5494 alu.src[1].chan = 0;
5495
5496 alu.last = 1;
5497 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5498 return r;
5499 }
5500
5501 /* 7. tmp1.x = tmp0.x - tmp0.w */
5502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5503 alu.op = ALU_OP2_SUB_INT;
5504
5505 alu.dst.sel = tmp1;
5506 alu.dst.chan = 0;
5507 alu.dst.write = 1;
5508
5509 alu.src[0].sel = tmp0;
5510 alu.src[0].chan = 0;
5511 alu.src[1].sel = tmp0;
5512 alu.src[1].chan = 3;
5513
5514 alu.last = 1;
5515 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5516 return r;
5517
5518 /* 8. tmp1.y = tmp0.x + tmp0.w */
5519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5520 alu.op = ALU_OP2_ADD_INT;
5521
5522 alu.dst.sel = tmp1;
5523 alu.dst.chan = 1;
5524 alu.dst.write = 1;
5525
5526 alu.src[0].sel = tmp0;
5527 alu.src[0].chan = 0;
5528 alu.src[1].sel = tmp0;
5529 alu.src[1].chan = 3;
5530
5531 alu.last = 1;
5532 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5533 return r;
5534
5535 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5536 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5537 alu.op = ALU_OP3_CNDE_INT;
5538 alu.is_op3 = 1;
5539
5540 alu.dst.sel = tmp0;
5541 alu.dst.chan = 0;
5542 alu.dst.write = 1;
5543
5544 alu.src[0].sel = tmp0;
5545 alu.src[0].chan = 1;
5546 alu.src[1].sel = tmp1;
5547 alu.src[1].chan = 1;
5548 alu.src[2].sel = tmp1;
5549 alu.src[2].chan = 0;
5550
5551 alu.last = 1;
5552 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5553 return r;
5554
5555 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5556 if (ctx->bc->chip_class == CAYMAN) {
5557 for (j = 0 ; j < 4; j++) {
5558 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5559 alu.op = ALU_OP2_MULHI_UINT;
5560
5561 alu.dst.sel = tmp0;
5562 alu.dst.chan = j;
5563 alu.dst.write = (j == 2);
5564
5565 alu.src[0].sel = tmp0;
5566 alu.src[0].chan = 0;
5567
5568 if (signed_op) {
5569 alu.src[1].sel = tmp2;
5570 alu.src[1].chan = 0;
5571 } else {
5572 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5573 }
5574
5575 alu.last = (j == 3);
5576 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5577 return r;
5578 }
5579 } else {
5580 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5581 alu.op = ALU_OP2_MULHI_UINT;
5582
5583 alu.dst.sel = tmp0;
5584 alu.dst.chan = 2;
5585 alu.dst.write = 1;
5586
5587 alu.src[0].sel = tmp0;
5588 alu.src[0].chan = 0;
5589
5590 if (signed_op) {
5591 alu.src[1].sel = tmp2;
5592 alu.src[1].chan = 0;
5593 } else {
5594 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5595 }
5596
5597 alu.last = 1;
5598 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5599 return r;
5600 }
5601
5602 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5603 if (ctx->bc->chip_class == CAYMAN) {
5604 for (j = 0 ; j < 4; j++) {
5605 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5606 alu.op = ALU_OP2_MULLO_UINT;
5607
5608 alu.dst.sel = tmp0;
5609 alu.dst.chan = j;
5610 alu.dst.write = (j == 1);
5611
5612 if (signed_op) {
5613 alu.src[0].sel = tmp2;
5614 alu.src[0].chan = 1;
5615 } else {
5616 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5617 }
5618
5619 alu.src[1].sel = tmp0;
5620 alu.src[1].chan = 2;
5621
5622 alu.last = (j == 3);
5623 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5624 return r;
5625 }
5626 } else {
5627 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5628 alu.op = ALU_OP2_MULLO_UINT;
5629
5630 alu.dst.sel = tmp0;
5631 alu.dst.chan = 1;
5632 alu.dst.write = 1;
5633
5634 if (signed_op) {
5635 alu.src[0].sel = tmp2;
5636 alu.src[0].chan = 1;
5637 } else {
5638 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5639 }
5640
5641 alu.src[1].sel = tmp0;
5642 alu.src[1].chan = 2;
5643
5644 alu.last = 1;
5645 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5646 return r;
5647 }
5648
5649 /* 12. tmp0.w = src1 - tmp0.y = r */
5650 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5651 alu.op = ALU_OP2_SUB_INT;
5652
5653 alu.dst.sel = tmp0;
5654 alu.dst.chan = 3;
5655 alu.dst.write = 1;
5656
5657 if (signed_op) {
5658 alu.src[0].sel = tmp2;
5659 alu.src[0].chan = 0;
5660 } else {
5661 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5662 }
5663
5664 alu.src[1].sel = tmp0;
5665 alu.src[1].chan = 1;
5666
5667 alu.last = 1;
5668 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5669 return r;
5670
5671 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5672 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5673 alu.op = ALU_OP2_SETGE_UINT;
5674
5675 alu.dst.sel = tmp1;
5676 alu.dst.chan = 0;
5677 alu.dst.write = 1;
5678
5679 alu.src[0].sel = tmp0;
5680 alu.src[0].chan = 3;
5681 if (signed_op) {
5682 alu.src[1].sel = tmp2;
5683 alu.src[1].chan = 1;
5684 } else {
5685 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5686 }
5687
5688 alu.last = 1;
5689 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5690 return r;
5691
5692 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5693 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5694 alu.op = ALU_OP2_SETGE_UINT;
5695
5696 alu.dst.sel = tmp1;
5697 alu.dst.chan = 1;
5698 alu.dst.write = 1;
5699
5700 if (signed_op) {
5701 alu.src[0].sel = tmp2;
5702 alu.src[0].chan = 0;
5703 } else {
5704 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5705 }
5706
5707 alu.src[1].sel = tmp0;
5708 alu.src[1].chan = 1;
5709
5710 alu.last = 1;
5711 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5712 return r;
5713
5714 if (mod) { /* UMOD */
5715
5716 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5718 alu.op = ALU_OP2_SUB_INT;
5719
5720 alu.dst.sel = tmp1;
5721 alu.dst.chan = 2;
5722 alu.dst.write = 1;
5723
5724 alu.src[0].sel = tmp0;
5725 alu.src[0].chan = 3;
5726
5727 if (signed_op) {
5728 alu.src[1].sel = tmp2;
5729 alu.src[1].chan = 1;
5730 } else {
5731 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5732 }
5733
5734 alu.last = 1;
5735 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5736 return r;
5737
5738 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5739 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5740 alu.op = ALU_OP2_ADD_INT;
5741
5742 alu.dst.sel = tmp1;
5743 alu.dst.chan = 3;
5744 alu.dst.write = 1;
5745
5746 alu.src[0].sel = tmp0;
5747 alu.src[0].chan = 3;
5748 if (signed_op) {
5749 alu.src[1].sel = tmp2;
5750 alu.src[1].chan = 1;
5751 } else {
5752 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5753 }
5754
5755 alu.last = 1;
5756 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5757 return r;
5758
5759 } else { /* UDIV */
5760
5761 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5762 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5763 alu.op = ALU_OP2_ADD_INT;
5764
5765 alu.dst.sel = tmp1;
5766 alu.dst.chan = 2;
5767 alu.dst.write = 1;
5768
5769 alu.src[0].sel = tmp0;
5770 alu.src[0].chan = 2;
5771 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5772
5773 alu.last = 1;
5774 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5775 return r;
5776
5777 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5779 alu.op = ALU_OP2_ADD_INT;
5780
5781 alu.dst.sel = tmp1;
5782 alu.dst.chan = 3;
5783 alu.dst.write = 1;
5784
5785 alu.src[0].sel = tmp0;
5786 alu.src[0].chan = 2;
5787 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5788
5789 alu.last = 1;
5790 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5791 return r;
5792
5793 }
5794
5795 /* 17. tmp1.x = tmp1.x & tmp1.y */
5796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5797 alu.op = ALU_OP2_AND_INT;
5798
5799 alu.dst.sel = tmp1;
5800 alu.dst.chan = 0;
5801 alu.dst.write = 1;
5802
5803 alu.src[0].sel = tmp1;
5804 alu.src[0].chan = 0;
5805 alu.src[1].sel = tmp1;
5806 alu.src[1].chan = 1;
5807
5808 alu.last = 1;
5809 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5810 return r;
5811
5812 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5813 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5814 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5815 alu.op = ALU_OP3_CNDE_INT;
5816 alu.is_op3 = 1;
5817
5818 alu.dst.sel = tmp0;
5819 alu.dst.chan = 2;
5820 alu.dst.write = 1;
5821
5822 alu.src[0].sel = tmp1;
5823 alu.src[0].chan = 0;
5824 alu.src[1].sel = tmp0;
5825 alu.src[1].chan = mod ? 3 : 2;
5826 alu.src[2].sel = tmp1;
5827 alu.src[2].chan = 2;
5828
5829 alu.last = 1;
5830 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5831 return r;
5832
5833 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5834 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5835 alu.op = ALU_OP3_CNDE_INT;
5836 alu.is_op3 = 1;
5837
5838 if (signed_op) {
5839 alu.dst.sel = tmp0;
5840 alu.dst.chan = 2;
5841 alu.dst.write = 1;
5842 } else {
5843 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5844 }
5845
5846 alu.src[0].sel = tmp1;
5847 alu.src[0].chan = 1;
5848 alu.src[1].sel = tmp1;
5849 alu.src[1].chan = 3;
5850 alu.src[2].sel = tmp0;
5851 alu.src[2].chan = 2;
5852
5853 alu.last = 1;
5854 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5855 return r;
5856
5857 if (signed_op) {
5858
5859 /* fix the sign of the result */
5860
5861 if (mod) {
5862
5863 /* tmp0.x = -tmp0.z */
5864 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5865 alu.op = ALU_OP2_SUB_INT;
5866
5867 alu.dst.sel = tmp0;
5868 alu.dst.chan = 0;
5869 alu.dst.write = 1;
5870
5871 alu.src[0].sel = V_SQ_ALU_SRC_0;
5872 alu.src[1].sel = tmp0;
5873 alu.src[1].chan = 2;
5874
5875 alu.last = 1;
5876 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5877 return r;
5878
5879 /* sign of the remainder is the same as the sign of src0 */
5880 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
5881 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5882 alu.op = ALU_OP3_CNDGE_INT;
5883 alu.is_op3 = 1;
5884
5885 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5886
5887 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5888 alu.src[1].sel = tmp0;
5889 alu.src[1].chan = 2;
5890 alu.src[2].sel = tmp0;
5891 alu.src[2].chan = 0;
5892
5893 alu.last = 1;
5894 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5895 return r;
5896
5897 } else {
5898
5899 /* tmp0.x = -tmp0.z */
5900 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5901 alu.op = ALU_OP2_SUB_INT;
5902
5903 alu.dst.sel = tmp0;
5904 alu.dst.chan = 0;
5905 alu.dst.write = 1;
5906
5907 alu.src[0].sel = V_SQ_ALU_SRC_0;
5908 alu.src[1].sel = tmp0;
5909 alu.src[1].chan = 2;
5910
5911 alu.last = 1;
5912 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5913 return r;
5914
5915 /* fix the quotient sign (same as the sign of src0*src1) */
5916 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
5917 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5918 alu.op = ALU_OP3_CNDGE_INT;
5919 alu.is_op3 = 1;
5920
5921 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5922
5923 alu.src[0].sel = tmp2;
5924 alu.src[0].chan = 2;
5925 alu.src[1].sel = tmp0;
5926 alu.src[1].chan = 2;
5927 alu.src[2].sel = tmp0;
5928 alu.src[2].chan = 0;
5929
5930 alu.last = 1;
5931 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5932 return r;
5933 }
5934 }
5935 }
5936 return 0;
5937 }
5938
5939 static int tgsi_udiv(struct r600_shader_ctx *ctx)
5940 {
5941 return tgsi_divmod(ctx, 0, 0);
5942 }
5943
5944 static int tgsi_umod(struct r600_shader_ctx *ctx)
5945 {
5946 return tgsi_divmod(ctx, 1, 0);
5947 }
5948
5949 static int tgsi_idiv(struct r600_shader_ctx *ctx)
5950 {
5951 return tgsi_divmod(ctx, 0, 1);
5952 }
5953
5954 static int tgsi_imod(struct r600_shader_ctx *ctx)
5955 {
5956 return tgsi_divmod(ctx, 1, 1);
5957 }
5958
5959
5960 static int tgsi_f2i(struct r600_shader_ctx *ctx)
5961 {
5962 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5963 struct r600_bytecode_alu alu;
5964 int i, r;
5965 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5966 int last_inst = tgsi_last_instruction(write_mask);
5967
5968 for (i = 0; i < 4; i++) {
5969 if (!(write_mask & (1<<i)))
5970 continue;
5971
5972 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5973 alu.op = ALU_OP1_TRUNC;
5974
5975 alu.dst.sel = ctx->temp_reg;
5976 alu.dst.chan = i;
5977 alu.dst.write = 1;
5978
5979 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5980 if (i == last_inst)
5981 alu.last = 1;
5982 r = r600_bytecode_add_alu(ctx->bc, &alu);
5983 if (r)
5984 return r;
5985 }
5986
5987 for (i = 0; i < 4; i++) {
5988 if (!(write_mask & (1<<i)))
5989 continue;
5990
5991 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5992 alu.op = ctx->inst_info->op;
5993
5994 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5995
5996 alu.src[0].sel = ctx->temp_reg;
5997 alu.src[0].chan = i;
5998
5999 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6000 alu.last = 1;
6001 r = r600_bytecode_add_alu(ctx->bc, &alu);
6002 if (r)
6003 return r;
6004 }
6005
6006 return 0;
6007 }
6008
6009 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6010 {
6011 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6012 struct r600_bytecode_alu alu;
6013 int i, r;
6014 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6015 int last_inst = tgsi_last_instruction(write_mask);
6016
6017 /* tmp = -src */
6018 for (i = 0; i < 4; i++) {
6019 if (!(write_mask & (1<<i)))
6020 continue;
6021
6022 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6023 alu.op = ALU_OP2_SUB_INT;
6024
6025 alu.dst.sel = ctx->temp_reg;
6026 alu.dst.chan = i;
6027 alu.dst.write = 1;
6028
6029 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6030 alu.src[0].sel = V_SQ_ALU_SRC_0;
6031
6032 if (i == last_inst)
6033 alu.last = 1;
6034 r = r600_bytecode_add_alu(ctx->bc, &alu);
6035 if (r)
6036 return r;
6037 }
6038
6039 /* dst = (src >= 0 ? src : tmp) */
6040 for (i = 0; i < 4; i++) {
6041 if (!(write_mask & (1<<i)))
6042 continue;
6043
6044 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6045 alu.op = ALU_OP3_CNDGE_INT;
6046 alu.is_op3 = 1;
6047 alu.dst.write = 1;
6048
6049 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6050
6051 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6052 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6053 alu.src[2].sel = ctx->temp_reg;
6054 alu.src[2].chan = i;
6055
6056 if (i == last_inst)
6057 alu.last = 1;
6058 r = r600_bytecode_add_alu(ctx->bc, &alu);
6059 if (r)
6060 return r;
6061 }
6062 return 0;
6063 }
6064
6065 static int tgsi_issg(struct r600_shader_ctx *ctx)
6066 {
6067 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6068 struct r600_bytecode_alu alu;
6069 int i, r;
6070 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6071 int last_inst = tgsi_last_instruction(write_mask);
6072
6073 /* tmp = (src >= 0 ? src : -1) */
6074 for (i = 0; i < 4; i++) {
6075 if (!(write_mask & (1<<i)))
6076 continue;
6077
6078 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6079 alu.op = ALU_OP3_CNDGE_INT;
6080 alu.is_op3 = 1;
6081
6082 alu.dst.sel = ctx->temp_reg;
6083 alu.dst.chan = i;
6084 alu.dst.write = 1;
6085
6086 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6087 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6088 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6089
6090 if (i == last_inst)
6091 alu.last = 1;
6092 r = r600_bytecode_add_alu(ctx->bc, &alu);
6093 if (r)
6094 return r;
6095 }
6096
6097 /* dst = (tmp > 0 ? 1 : tmp) */
6098 for (i = 0; i < 4; i++) {
6099 if (!(write_mask & (1<<i)))
6100 continue;
6101
6102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6103 alu.op = ALU_OP3_CNDGT_INT;
6104 alu.is_op3 = 1;
6105 alu.dst.write = 1;
6106
6107 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6108
6109 alu.src[0].sel = ctx->temp_reg;
6110 alu.src[0].chan = i;
6111
6112 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6113
6114 alu.src[2].sel = ctx->temp_reg;
6115 alu.src[2].chan = i;
6116
6117 if (i == last_inst)
6118 alu.last = 1;
6119 r = r600_bytecode_add_alu(ctx->bc, &alu);
6120 if (r)
6121 return r;
6122 }
6123 return 0;
6124 }
6125
6126
6127
6128 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6129 {
6130 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6131 struct r600_bytecode_alu alu;
6132 int i, r;
6133
6134 /* tmp = (src > 0 ? 1 : src) */
6135 for (i = 0; i < 4; i++) {
6136 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6137 alu.op = ALU_OP3_CNDGT;
6138 alu.is_op3 = 1;
6139
6140 alu.dst.sel = ctx->temp_reg;
6141 alu.dst.chan = i;
6142
6143 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6144 alu.src[1].sel = V_SQ_ALU_SRC_1;
6145 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6146
6147 if (i == 3)
6148 alu.last = 1;
6149 r = r600_bytecode_add_alu(ctx->bc, &alu);
6150 if (r)
6151 return r;
6152 }
6153
6154 /* dst = (-tmp > 0 ? -1 : tmp) */
6155 for (i = 0; i < 4; i++) {
6156 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6157 alu.op = ALU_OP3_CNDGT;
6158 alu.is_op3 = 1;
6159 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6160
6161 alu.src[0].sel = ctx->temp_reg;
6162 alu.src[0].chan = i;
6163 alu.src[0].neg = 1;
6164
6165 alu.src[1].sel = V_SQ_ALU_SRC_1;
6166 alu.src[1].neg = 1;
6167
6168 alu.src[2].sel = ctx->temp_reg;
6169 alu.src[2].chan = i;
6170
6171 if (i == 3)
6172 alu.last = 1;
6173 r = r600_bytecode_add_alu(ctx->bc, &alu);
6174 if (r)
6175 return r;
6176 }
6177 return 0;
6178 }
6179
6180 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6181 {
6182 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6183 struct r600_bytecode_alu alu;
6184 int i, r, t1, t2;
6185
6186 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6187 int last_inst = tgsi_last_instruction(write_mask);
6188
6189 t1 = r600_get_temp(ctx);
6190
6191 for (i = 0; i < 4; i++) {
6192 if (!(write_mask & (1<<i)))
6193 continue;
6194
6195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6196 alu.op = ALU_OP2_SETGE_INT;
6197 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6198 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6199 alu.src[1].value = 32;
6200 alu.dst.sel = ctx->temp_reg;
6201 alu.dst.chan = i;
6202 alu.dst.write = 1;
6203 alu.last = i == last_inst;
6204 r = r600_bytecode_add_alu(ctx->bc, &alu);
6205 if (r)
6206 return r;
6207 }
6208
6209 for (i = 0; i < 4; i++) {
6210 if (!(write_mask & (1<<i)))
6211 continue;
6212
6213 /* create mask tmp */
6214 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6215 alu.op = ALU_OP2_BFM_INT;
6216 alu.dst.sel = t1;
6217 alu.dst.chan = i;
6218 alu.dst.write = 1;
6219 alu.last = i == last_inst;
6220
6221 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6222 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6223
6224 r = r600_bytecode_add_alu(ctx->bc, &alu);
6225 if (r)
6226 return r;
6227 }
6228
6229 t2 = r600_get_temp(ctx);
6230
6231 for (i = 0; i < 4; i++) {
6232 if (!(write_mask & (1<<i)))
6233 continue;
6234
6235 /* shift insert left */
6236 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6237 alu.op = ALU_OP2_LSHL_INT;
6238 alu.dst.sel = t2;
6239 alu.dst.chan = i;
6240 alu.dst.write = 1;
6241 alu.last = i == last_inst;
6242
6243 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6244 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6245
6246 r = r600_bytecode_add_alu(ctx->bc, &alu);
6247 if (r)
6248 return r;
6249 }
6250
6251 for (i = 0; i < 4; i++) {
6252 if (!(write_mask & (1<<i)))
6253 continue;
6254
6255 /* actual bitfield insert */
6256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6257 alu.op = ALU_OP3_BFI_INT;
6258 alu.is_op3 = 1;
6259 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6260 alu.dst.chan = i;
6261 alu.dst.write = 1;
6262 alu.last = i == last_inst;
6263
6264 alu.src[0].sel = t1;
6265 alu.src[0].chan = i;
6266 alu.src[1].sel = t2;
6267 alu.src[1].chan = i;
6268 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6269
6270 r = r600_bytecode_add_alu(ctx->bc, &alu);
6271 if (r)
6272 return r;
6273 }
6274
6275 for (i = 0; i < 4; i++) {
6276 if (!(write_mask & (1<<i)))
6277 continue;
6278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6279 alu.op = ALU_OP3_CNDE_INT;
6280 alu.is_op3 = 1;
6281 alu.src[0].sel = ctx->temp_reg;
6282 alu.src[0].chan = i;
6283 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6284
6285 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6286
6287 alu.src[1].sel = alu.dst.sel;
6288 alu.src[1].chan = i;
6289
6290 alu.last = i == last_inst;
6291 r = r600_bytecode_add_alu(ctx->bc, &alu);
6292 if (r)
6293 return r;
6294 }
6295 return 0;
6296 }
6297
6298 static int tgsi_msb(struct r600_shader_ctx *ctx)
6299 {
6300 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6301 struct r600_bytecode_alu alu;
6302 int i, r, t1, t2;
6303
6304 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6305 int last_inst = tgsi_last_instruction(write_mask);
6306
6307 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6308 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6309
6310 t1 = ctx->temp_reg;
6311
6312 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6313 for (i = 0; i < 4; i++) {
6314 if (!(write_mask & (1<<i)))
6315 continue;
6316
6317 /* t1 = FFBH_INT / FFBH_UINT */
6318 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6319 alu.op = ctx->inst_info->op;
6320 alu.dst.sel = t1;
6321 alu.dst.chan = i;
6322 alu.dst.write = 1;
6323 alu.last = i == last_inst;
6324
6325 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6326
6327 r = r600_bytecode_add_alu(ctx->bc, &alu);
6328 if (r)
6329 return r;
6330 }
6331
6332 t2 = r600_get_temp(ctx);
6333
6334 for (i = 0; i < 4; i++) {
6335 if (!(write_mask & (1<<i)))
6336 continue;
6337
6338 /* t2 = 31 - t1 */
6339 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6340 alu.op = ALU_OP2_SUB_INT;
6341 alu.dst.sel = t2;
6342 alu.dst.chan = i;
6343 alu.dst.write = 1;
6344 alu.last = i == last_inst;
6345
6346 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6347 alu.src[0].value = 31;
6348 alu.src[1].sel = t1;
6349 alu.src[1].chan = i;
6350
6351 r = r600_bytecode_add_alu(ctx->bc, &alu);
6352 if (r)
6353 return r;
6354 }
6355
6356 for (i = 0; i < 4; i++) {
6357 if (!(write_mask & (1<<i)))
6358 continue;
6359
6360 /* result = t1 >= 0 ? t2 : t1 */
6361 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6362 alu.op = ALU_OP3_CNDGE_INT;
6363 alu.is_op3 = 1;
6364 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6365 alu.dst.chan = i;
6366 alu.dst.write = 1;
6367 alu.last = i == last_inst;
6368
6369 alu.src[0].sel = t1;
6370 alu.src[0].chan = i;
6371 alu.src[1].sel = t2;
6372 alu.src[1].chan = i;
6373 alu.src[2].sel = t1;
6374 alu.src[2].chan = i;
6375
6376 r = r600_bytecode_add_alu(ctx->bc, &alu);
6377 if (r)
6378 return r;
6379 }
6380
6381 return 0;
6382 }
6383
6384 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6385 {
6386 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6387 struct r600_bytecode_alu alu;
6388 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6389 unsigned location;
6390 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6391
6392 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6393
6394 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6395 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6396 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6397 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6398 }
6399 else {
6400 location = TGSI_INTERPOLATE_LOC_CENTROID;
6401 }
6402
6403 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6404 if (k < 0)
6405 k = 0;
6406 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6407 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6408
6409 /* NOTE: currently offset is not perspective correct */
6410 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6411 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6412 int sample_gpr = -1;
6413 int gradientsH, gradientsV;
6414 struct r600_bytecode_tex tex;
6415
6416 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6417 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6418 }
6419
6420 gradientsH = r600_get_temp(ctx);
6421 gradientsV = r600_get_temp(ctx);
6422 for (i = 0; i < 2; i++) {
6423 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6424 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6425 tex.src_gpr = interp_gpr;
6426 tex.src_sel_x = interp_base_chan + 0;
6427 tex.src_sel_y = interp_base_chan + 1;
6428 tex.src_sel_z = 0;
6429 tex.src_sel_w = 0;
6430 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6431 tex.dst_sel_x = 0;
6432 tex.dst_sel_y = 1;
6433 tex.dst_sel_z = 7;
6434 tex.dst_sel_w = 7;
6435 tex.inst_mod = 1; // Use per pixel gradient calculation
6436 tex.sampler_id = 0;
6437 tex.resource_id = tex.sampler_id;
6438 r = r600_bytecode_add_tex(ctx->bc, &tex);
6439 if (r)
6440 return r;
6441 }
6442
6443 for (i = 0; i < 2; i++) {
6444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6445 alu.op = ALU_OP3_MULADD;
6446 alu.is_op3 = 1;
6447 alu.src[0].sel = gradientsH;
6448 alu.src[0].chan = i;
6449 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6450 alu.src[1].sel = sample_gpr;
6451 alu.src[1].chan = 2;
6452 }
6453 else {
6454 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6455 }
6456 alu.src[2].sel = interp_gpr;
6457 alu.src[2].chan = interp_base_chan + i;
6458 alu.dst.sel = ctx->temp_reg;
6459 alu.dst.chan = i;
6460 alu.last = i == 1;
6461
6462 r = r600_bytecode_add_alu(ctx->bc, &alu);
6463 if (r)
6464 return r;
6465 }
6466
6467 for (i = 0; i < 2; i++) {
6468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6469 alu.op = ALU_OP3_MULADD;
6470 alu.is_op3 = 1;
6471 alu.src[0].sel = gradientsV;
6472 alu.src[0].chan = i;
6473 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6474 alu.src[1].sel = sample_gpr;
6475 alu.src[1].chan = 3;
6476 }
6477 else {
6478 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6479 }
6480 alu.src[2].sel = ctx->temp_reg;
6481 alu.src[2].chan = i;
6482 alu.dst.sel = ctx->temp_reg;
6483 alu.dst.chan = i;
6484 alu.last = i == 1;
6485
6486 r = r600_bytecode_add_alu(ctx->bc, &alu);
6487 if (r)
6488 return r;
6489 }
6490 }
6491
6492 tmp = r600_get_temp(ctx);
6493 for (i = 0; i < 8; i++) {
6494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6495 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6496
6497 alu.dst.sel = tmp;
6498 if ((i > 1 && i < 6)) {
6499 alu.dst.write = 1;
6500 }
6501 else {
6502 alu.dst.write = 0;
6503 }
6504 alu.dst.chan = i % 4;
6505
6506 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6507 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6508 alu.src[0].sel = ctx->temp_reg;
6509 alu.src[0].chan = 1 - (i % 2);
6510 } else {
6511 alu.src[0].sel = interp_gpr;
6512 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6513 }
6514 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6515 alu.src[1].chan = 0;
6516
6517 alu.last = i % 4 == 3;
6518 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6519
6520 r = r600_bytecode_add_alu(ctx->bc, &alu);
6521 if (r)
6522 return r;
6523 }
6524
6525 // INTERP can't swizzle dst
6526 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6527 for (i = 0; i <= lasti; i++) {
6528 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6529 continue;
6530
6531 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6532 alu.op = ALU_OP1_MOV;
6533 alu.src[0].sel = tmp;
6534 alu.src[0].chan = ctx->src[0].swizzle[i];
6535 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6536 alu.dst.write = 1;
6537 alu.last = i == lasti;
6538 r = r600_bytecode_add_alu(ctx->bc, &alu);
6539 if (r)
6540 return r;
6541 }
6542
6543 return 0;
6544 }
6545
6546
6547 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6548 {
6549 struct r600_bytecode_alu alu;
6550 int i, r;
6551
6552 for (i = 0; i < 4; i++) {
6553 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6554 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6555 alu.op = ALU_OP0_NOP;
6556 alu.dst.chan = i;
6557 } else {
6558 alu.op = ALU_OP1_MOV;
6559 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6560 alu.src[0].sel = ctx->temp_reg;
6561 alu.src[0].chan = i;
6562 }
6563 if (i == 3) {
6564 alu.last = 1;
6565 }
6566 r = r600_bytecode_add_alu(ctx->bc, &alu);
6567 if (r)
6568 return r;
6569 }
6570 return 0;
6571 }
6572
6573 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6574 unsigned temp, int chan,
6575 struct r600_bytecode_alu_src *bc_src,
6576 const struct r600_shader_src *shader_src)
6577 {
6578 struct r600_bytecode_alu alu;
6579 int r;
6580
6581 r600_bytecode_src(bc_src, shader_src, chan);
6582
6583 /* op3 operands don't support abs modifier */
6584 if (bc_src->abs) {
6585 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6587 alu.op = ALU_OP1_MOV;
6588 alu.dst.sel = temp;
6589 alu.dst.chan = chan;
6590 alu.dst.write = 1;
6591
6592 alu.src[0] = *bc_src;
6593 alu.last = true; // sufficient?
6594 r = r600_bytecode_add_alu(ctx->bc, &alu);
6595 if (r)
6596 return r;
6597
6598 memset(bc_src, 0, sizeof(*bc_src));
6599 bc_src->sel = temp;
6600 bc_src->chan = chan;
6601 }
6602 return 0;
6603 }
6604
6605 static int tgsi_op3(struct r600_shader_ctx *ctx)
6606 {
6607 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6608 struct r600_bytecode_alu alu;
6609 int i, j, r;
6610 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6611 int temp_regs[4];
6612 unsigned op = ctx->inst_info->op;
6613
6614 if (op == ALU_OP3_MULADD_IEEE &&
6615 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6616 op = ALU_OP3_MULADD;
6617
6618 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6619 temp_regs[j] = 0;
6620 if (ctx->src[j].abs)
6621 temp_regs[j] = r600_get_temp(ctx);
6622 }
6623 for (i = 0; i < lasti + 1; i++) {
6624 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6625 continue;
6626
6627 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6628 alu.op = op;
6629 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6630 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6631 if (r)
6632 return r;
6633 }
6634
6635 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6636 alu.dst.chan = i;
6637 alu.dst.write = 1;
6638 alu.is_op3 = 1;
6639 if (i == lasti) {
6640 alu.last = 1;
6641 }
6642 r = r600_bytecode_add_alu(ctx->bc, &alu);
6643 if (r)
6644 return r;
6645 }
6646 return 0;
6647 }
6648
6649 static int tgsi_dp(struct r600_shader_ctx *ctx)
6650 {
6651 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6652 struct r600_bytecode_alu alu;
6653 int i, j, r;
6654 unsigned op = ctx->inst_info->op;
6655 if (op == ALU_OP2_DOT4_IEEE &&
6656 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6657 op = ALU_OP2_DOT4;
6658
6659 for (i = 0; i < 4; i++) {
6660 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6661 alu.op = op;
6662 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6663 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6664 }
6665
6666 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6667 alu.dst.chan = i;
6668 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6669 /* handle some special cases */
6670 switch (inst->Instruction.Opcode) {
6671 case TGSI_OPCODE_DP2:
6672 if (i > 1) {
6673 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6674 alu.src[0].chan = alu.src[1].chan = 0;
6675 }
6676 break;
6677 case TGSI_OPCODE_DP3:
6678 if (i > 2) {
6679 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6680 alu.src[0].chan = alu.src[1].chan = 0;
6681 }
6682 break;
6683 default:
6684 break;
6685 }
6686 if (i == 3) {
6687 alu.last = 1;
6688 }
6689 r = r600_bytecode_add_alu(ctx->bc, &alu);
6690 if (r)
6691 return r;
6692 }
6693 return 0;
6694 }
6695
6696 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6697 unsigned index)
6698 {
6699 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6700 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6701 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6702 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6703 ctx->src[index].neg || ctx->src[index].abs ||
6704 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6705 }
6706
6707 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6708 unsigned index)
6709 {
6710 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6711 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6712 }
6713
6714 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6715 {
6716 struct r600_bytecode_vtx vtx;
6717 struct r600_bytecode_alu alu;
6718 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6719 int src_gpr, r, i;
6720 int id = tgsi_tex_get_src_gpr(ctx, 1);
6721
6722 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6723 if (src_requires_loading) {
6724 for (i = 0; i < 4; i++) {
6725 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6726 alu.op = ALU_OP1_MOV;
6727 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6728 alu.dst.sel = ctx->temp_reg;
6729 alu.dst.chan = i;
6730 if (i == 3)
6731 alu.last = 1;
6732 alu.dst.write = 1;
6733 r = r600_bytecode_add_alu(ctx->bc, &alu);
6734 if (r)
6735 return r;
6736 }
6737 src_gpr = ctx->temp_reg;
6738 }
6739
6740 memset(&vtx, 0, sizeof(vtx));
6741 vtx.op = FETCH_OP_VFETCH;
6742 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6743 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6744 vtx.src_gpr = src_gpr;
6745 vtx.mega_fetch_count = 16;
6746 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6747 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6748 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6749 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6750 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6751 vtx.use_const_fields = 1;
6752
6753 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6754 return r;
6755
6756 if (ctx->bc->chip_class >= EVERGREEN)
6757 return 0;
6758
6759 for (i = 0; i < 4; i++) {
6760 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6761 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6762 continue;
6763
6764 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6765 alu.op = ALU_OP2_AND_INT;
6766
6767 alu.dst.chan = i;
6768 alu.dst.sel = vtx.dst_gpr;
6769 alu.dst.write = 1;
6770
6771 alu.src[0].sel = vtx.dst_gpr;
6772 alu.src[0].chan = i;
6773
6774 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6775 alu.src[1].sel += (id * 2);
6776 alu.src[1].chan = i % 4;
6777 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6778
6779 if (i == lasti)
6780 alu.last = 1;
6781 r = r600_bytecode_add_alu(ctx->bc, &alu);
6782 if (r)
6783 return r;
6784 }
6785
6786 if (inst->Dst[0].Register.WriteMask & 3) {
6787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6788 alu.op = ALU_OP2_OR_INT;
6789
6790 alu.dst.chan = 3;
6791 alu.dst.sel = vtx.dst_gpr;
6792 alu.dst.write = 1;
6793
6794 alu.src[0].sel = vtx.dst_gpr;
6795 alu.src[0].chan = 3;
6796
6797 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6798 alu.src[1].chan = 0;
6799 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6800
6801 alu.last = 1;
6802 r = r600_bytecode_add_alu(ctx->bc, &alu);
6803 if (r)
6804 return r;
6805 }
6806 return 0;
6807 }
6808
6809 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset)
6810 {
6811 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6812 struct r600_bytecode_alu alu;
6813 int r;
6814 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
6815
6816 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6817 alu.op = ALU_OP1_MOV;
6818 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6819 if (ctx->bc->chip_class >= EVERGREEN) {
6820 /* channel 0 or 2 of each word */
6821 alu.src[0].sel += (id / 2);
6822 alu.src[0].chan = (id % 2) * 2;
6823 } else {
6824 /* r600 we have them at channel 2 of the second dword */
6825 alu.src[0].sel += (id * 2) + 1;
6826 alu.src[0].chan = 1;
6827 }
6828 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6829 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6830 alu.last = 1;
6831 r = r600_bytecode_add_alu(ctx->bc, &alu);
6832 if (r)
6833 return r;
6834 return 0;
6835 }
6836
6837 static int tgsi_tex(struct r600_shader_ctx *ctx)
6838 {
6839 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6840 struct r600_bytecode_tex tex;
6841 struct r600_bytecode_alu alu;
6842 unsigned src_gpr;
6843 int r, i, j;
6844 int opcode;
6845 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
6846 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6847 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
6848 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
6849
6850 bool txf_add_offsets = inst->Texture.NumOffsets &&
6851 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
6852 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
6853
6854 /* Texture fetch instructions can only use gprs as source.
6855 * Also they cannot negate the source or take the absolute value */
6856 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
6857 tgsi_tex_src_requires_loading(ctx, 0)) ||
6858 read_compressed_msaa || txf_add_offsets;
6859
6860 boolean src_loaded = FALSE;
6861 unsigned sampler_src_reg = 1;
6862 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
6863 boolean has_txq_cube_array_z = false;
6864 unsigned sampler_index_mode;
6865
6866 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
6867 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6868 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
6869 if (inst->Dst[0].Register.WriteMask & 4) {
6870 ctx->shader->has_txq_cube_array_z_comp = true;
6871 has_txq_cube_array_z = true;
6872 }
6873
6874 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
6875 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
6876 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
6877 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
6878 sampler_src_reg = 2;
6879
6880 /* TGSI moves the sampler to src reg 3 for TXD */
6881 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
6882 sampler_src_reg = 3;
6883
6884 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6885
6886 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6887
6888 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
6889 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
6890 ctx->shader->uses_tex_buffers = true;
6891 return r600_do_buffer_txq(ctx, 1, 0);
6892 }
6893 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
6894 if (ctx->bc->chip_class < EVERGREEN)
6895 ctx->shader->uses_tex_buffers = true;
6896 return do_vtx_fetch_inst(ctx, src_requires_loading);
6897 }
6898 }
6899
6900 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
6901 int out_chan;
6902 /* Add perspective divide */
6903 if (ctx->bc->chip_class == CAYMAN) {
6904 out_chan = 2;
6905 for (i = 0; i < 3; i++) {
6906 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6907 alu.op = ALU_OP1_RECIP_IEEE;
6908 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6909
6910 alu.dst.sel = ctx->temp_reg;
6911 alu.dst.chan = i;
6912 if (i == 2)
6913 alu.last = 1;
6914 if (out_chan == i)
6915 alu.dst.write = 1;
6916 r = r600_bytecode_add_alu(ctx->bc, &alu);
6917 if (r)
6918 return r;
6919 }
6920
6921 } else {
6922 out_chan = 3;
6923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6924 alu.op = ALU_OP1_RECIP_IEEE;
6925 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
6926
6927 alu.dst.sel = ctx->temp_reg;
6928 alu.dst.chan = out_chan;
6929 alu.last = 1;
6930 alu.dst.write = 1;
6931 r = r600_bytecode_add_alu(ctx->bc, &alu);
6932 if (r)
6933 return r;
6934 }
6935
6936 for (i = 0; i < 3; i++) {
6937 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6938 alu.op = ALU_OP2_MUL;
6939 alu.src[0].sel = ctx->temp_reg;
6940 alu.src[0].chan = out_chan;
6941 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6942 alu.dst.sel = ctx->temp_reg;
6943 alu.dst.chan = i;
6944 alu.dst.write = 1;
6945 r = r600_bytecode_add_alu(ctx->bc, &alu);
6946 if (r)
6947 return r;
6948 }
6949 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6950 alu.op = ALU_OP1_MOV;
6951 alu.src[0].sel = V_SQ_ALU_SRC_1;
6952 alu.src[0].chan = 0;
6953 alu.dst.sel = ctx->temp_reg;
6954 alu.dst.chan = 3;
6955 alu.last = 1;
6956 alu.dst.write = 1;
6957 r = r600_bytecode_add_alu(ctx->bc, &alu);
6958 if (r)
6959 return r;
6960 src_loaded = TRUE;
6961 src_gpr = ctx->temp_reg;
6962 }
6963
6964
6965 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
6966 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
6967 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
6968 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
6969 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
6970
6971 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
6972 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
6973
6974 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
6975 for (i = 0; i < 4; i++) {
6976 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6977 alu.op = ALU_OP2_CUBE;
6978 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
6979 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
6980 alu.dst.sel = ctx->temp_reg;
6981 alu.dst.chan = i;
6982 if (i == 3)
6983 alu.last = 1;
6984 alu.dst.write = 1;
6985 r = r600_bytecode_add_alu(ctx->bc, &alu);
6986 if (r)
6987 return r;
6988 }
6989
6990 /* tmp1.z = RCP_e(|tmp1.z|) */
6991 if (ctx->bc->chip_class == CAYMAN) {
6992 for (i = 0; i < 3; i++) {
6993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6994 alu.op = ALU_OP1_RECIP_IEEE;
6995 alu.src[0].sel = ctx->temp_reg;
6996 alu.src[0].chan = 2;
6997 alu.src[0].abs = 1;
6998 alu.dst.sel = ctx->temp_reg;
6999 alu.dst.chan = i;
7000 if (i == 2)
7001 alu.dst.write = 1;
7002 if (i == 2)
7003 alu.last = 1;
7004 r = r600_bytecode_add_alu(ctx->bc, &alu);
7005 if (r)
7006 return r;
7007 }
7008 } else {
7009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7010 alu.op = ALU_OP1_RECIP_IEEE;
7011 alu.src[0].sel = ctx->temp_reg;
7012 alu.src[0].chan = 2;
7013 alu.src[0].abs = 1;
7014 alu.dst.sel = ctx->temp_reg;
7015 alu.dst.chan = 2;
7016 alu.dst.write = 1;
7017 alu.last = 1;
7018 r = r600_bytecode_add_alu(ctx->bc, &alu);
7019 if (r)
7020 return r;
7021 }
7022
7023 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7024 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7025 * muladd has no writemask, have to use another temp
7026 */
7027 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7028 alu.op = ALU_OP3_MULADD;
7029 alu.is_op3 = 1;
7030
7031 alu.src[0].sel = ctx->temp_reg;
7032 alu.src[0].chan = 0;
7033 alu.src[1].sel = ctx->temp_reg;
7034 alu.src[1].chan = 2;
7035
7036 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7037 alu.src[2].chan = 0;
7038 alu.src[2].value = u_bitcast_f2u(1.5f);
7039
7040 alu.dst.sel = ctx->temp_reg;
7041 alu.dst.chan = 0;
7042 alu.dst.write = 1;
7043
7044 r = r600_bytecode_add_alu(ctx->bc, &alu);
7045 if (r)
7046 return r;
7047
7048 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7049 alu.op = ALU_OP3_MULADD;
7050 alu.is_op3 = 1;
7051
7052 alu.src[0].sel = ctx->temp_reg;
7053 alu.src[0].chan = 1;
7054 alu.src[1].sel = ctx->temp_reg;
7055 alu.src[1].chan = 2;
7056
7057 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7058 alu.src[2].chan = 0;
7059 alu.src[2].value = u_bitcast_f2u(1.5f);
7060
7061 alu.dst.sel = ctx->temp_reg;
7062 alu.dst.chan = 1;
7063 alu.dst.write = 1;
7064
7065 alu.last = 1;
7066 r = r600_bytecode_add_alu(ctx->bc, &alu);
7067 if (r)
7068 return r;
7069 /* write initial compare value into Z component
7070 - W src 0 for shadow cube
7071 - X src 1 for shadow cube array */
7072 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7073 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7074 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7075 alu.op = ALU_OP1_MOV;
7076 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7077 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7078 else
7079 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7080 alu.dst.sel = ctx->temp_reg;
7081 alu.dst.chan = 2;
7082 alu.dst.write = 1;
7083 alu.last = 1;
7084 r = r600_bytecode_add_alu(ctx->bc, &alu);
7085 if (r)
7086 return r;
7087 }
7088
7089 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7090 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7091 if (ctx->bc->chip_class >= EVERGREEN) {
7092 int mytmp = r600_get_temp(ctx);
7093 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7094 alu.op = ALU_OP1_MOV;
7095 alu.src[0].sel = ctx->temp_reg;
7096 alu.src[0].chan = 3;
7097 alu.dst.sel = mytmp;
7098 alu.dst.chan = 0;
7099 alu.dst.write = 1;
7100 alu.last = 1;
7101 r = r600_bytecode_add_alu(ctx->bc, &alu);
7102 if (r)
7103 return r;
7104
7105 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7106 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7107 alu.op = ALU_OP3_MULADD;
7108 alu.is_op3 = 1;
7109 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7110 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7111 alu.src[1].chan = 0;
7112 alu.src[1].value = u_bitcast_f2u(8.0f);
7113 alu.src[2].sel = mytmp;
7114 alu.src[2].chan = 0;
7115 alu.dst.sel = ctx->temp_reg;
7116 alu.dst.chan = 3;
7117 alu.dst.write = 1;
7118 alu.last = 1;
7119 r = r600_bytecode_add_alu(ctx->bc, &alu);
7120 if (r)
7121 return r;
7122 } else if (ctx->bc->chip_class < EVERGREEN) {
7123 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7124 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7125 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7126 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7127 tex.src_gpr = r600_get_temp(ctx);
7128 tex.src_sel_x = 0;
7129 tex.src_sel_y = 0;
7130 tex.src_sel_z = 0;
7131 tex.src_sel_w = 0;
7132 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7133 tex.coord_type_x = 1;
7134 tex.coord_type_y = 1;
7135 tex.coord_type_z = 1;
7136 tex.coord_type_w = 1;
7137 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7138 alu.op = ALU_OP1_MOV;
7139 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7140 alu.dst.sel = tex.src_gpr;
7141 alu.dst.chan = 0;
7142 alu.last = 1;
7143 alu.dst.write = 1;
7144 r = r600_bytecode_add_alu(ctx->bc, &alu);
7145 if (r)
7146 return r;
7147
7148 r = r600_bytecode_add_tex(ctx->bc, &tex);
7149 if (r)
7150 return r;
7151 }
7152
7153 }
7154
7155 /* for cube forms of lod and bias we need to route things */
7156 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7157 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7158 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7159 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7160 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7161 alu.op = ALU_OP1_MOV;
7162 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7163 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7164 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7165 else
7166 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7167 alu.dst.sel = ctx->temp_reg;
7168 alu.dst.chan = 2;
7169 alu.last = 1;
7170 alu.dst.write = 1;
7171 r = r600_bytecode_add_alu(ctx->bc, &alu);
7172 if (r)
7173 return r;
7174 }
7175
7176 src_loaded = TRUE;
7177 src_gpr = ctx->temp_reg;
7178 }
7179
7180 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7181 int temp_h = 0, temp_v = 0;
7182 int start_val = 0;
7183
7184 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7185 if (src_loaded == TRUE)
7186 start_val = 1;
7187 else
7188 src_loaded = TRUE;
7189 for (i = start_val; i < 3; i++) {
7190 int treg = r600_get_temp(ctx);
7191
7192 if (i == 0)
7193 src_gpr = treg;
7194 else if (i == 1)
7195 temp_h = treg;
7196 else
7197 temp_v = treg;
7198
7199 for (j = 0; j < 4; j++) {
7200 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7201 alu.op = ALU_OP1_MOV;
7202 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7203 alu.dst.sel = treg;
7204 alu.dst.chan = j;
7205 if (j == 3)
7206 alu.last = 1;
7207 alu.dst.write = 1;
7208 r = r600_bytecode_add_alu(ctx->bc, &alu);
7209 if (r)
7210 return r;
7211 }
7212 }
7213 for (i = 1; i < 3; i++) {
7214 /* set gradients h/v */
7215 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7216 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7217 FETCH_OP_SET_GRADIENTS_V;
7218 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7219 tex.sampler_index_mode = sampler_index_mode;
7220 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7221 tex.resource_index_mode = sampler_index_mode;
7222
7223 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7224 tex.src_sel_x = 0;
7225 tex.src_sel_y = 1;
7226 tex.src_sel_z = 2;
7227 tex.src_sel_w = 3;
7228
7229 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7230 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7231 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7232 tex.coord_type_x = 1;
7233 tex.coord_type_y = 1;
7234 tex.coord_type_z = 1;
7235 tex.coord_type_w = 1;
7236 }
7237 r = r600_bytecode_add_tex(ctx->bc, &tex);
7238 if (r)
7239 return r;
7240 }
7241 }
7242
7243 if (src_requires_loading && !src_loaded) {
7244 for (i = 0; i < 4; i++) {
7245 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7246 alu.op = ALU_OP1_MOV;
7247 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7248 alu.dst.sel = ctx->temp_reg;
7249 alu.dst.chan = i;
7250 if (i == 3)
7251 alu.last = 1;
7252 alu.dst.write = 1;
7253 r = r600_bytecode_add_alu(ctx->bc, &alu);
7254 if (r)
7255 return r;
7256 }
7257 src_loaded = TRUE;
7258 src_gpr = ctx->temp_reg;
7259 }
7260
7261 /* get offset values */
7262 if (inst->Texture.NumOffsets) {
7263 assert(inst->Texture.NumOffsets == 1);
7264
7265 /* The texture offset feature doesn't work with the TXF instruction
7266 * and must be emulated by adding the offset to the texture coordinates. */
7267 if (txf_add_offsets) {
7268 const struct tgsi_texture_offset *off = inst->TexOffsets;
7269
7270 switch (inst->Texture.Texture) {
7271 case TGSI_TEXTURE_3D:
7272 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7273 alu.op = ALU_OP2_ADD_INT;
7274 alu.src[0].sel = src_gpr;
7275 alu.src[0].chan = 2;
7276 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7277 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7278 alu.dst.sel = src_gpr;
7279 alu.dst.chan = 2;
7280 alu.dst.write = 1;
7281 alu.last = 1;
7282 r = r600_bytecode_add_alu(ctx->bc, &alu);
7283 if (r)
7284 return r;
7285 /* fall through */
7286
7287 case TGSI_TEXTURE_2D:
7288 case TGSI_TEXTURE_SHADOW2D:
7289 case TGSI_TEXTURE_RECT:
7290 case TGSI_TEXTURE_SHADOWRECT:
7291 case TGSI_TEXTURE_2D_ARRAY:
7292 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7294 alu.op = ALU_OP2_ADD_INT;
7295 alu.src[0].sel = src_gpr;
7296 alu.src[0].chan = 1;
7297 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7298 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7299 alu.dst.sel = src_gpr;
7300 alu.dst.chan = 1;
7301 alu.dst.write = 1;
7302 alu.last = 1;
7303 r = r600_bytecode_add_alu(ctx->bc, &alu);
7304 if (r)
7305 return r;
7306 /* fall through */
7307
7308 case TGSI_TEXTURE_1D:
7309 case TGSI_TEXTURE_SHADOW1D:
7310 case TGSI_TEXTURE_1D_ARRAY:
7311 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7312 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7313 alu.op = ALU_OP2_ADD_INT;
7314 alu.src[0].sel = src_gpr;
7315 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7316 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7317 alu.dst.sel = src_gpr;
7318 alu.dst.write = 1;
7319 alu.last = 1;
7320 r = r600_bytecode_add_alu(ctx->bc, &alu);
7321 if (r)
7322 return r;
7323 break;
7324 /* texture offsets do not apply to other texture targets */
7325 }
7326 } else {
7327 switch (inst->Texture.Texture) {
7328 case TGSI_TEXTURE_3D:
7329 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7330 /* fallthrough */
7331 case TGSI_TEXTURE_2D:
7332 case TGSI_TEXTURE_SHADOW2D:
7333 case TGSI_TEXTURE_RECT:
7334 case TGSI_TEXTURE_SHADOWRECT:
7335 case TGSI_TEXTURE_2D_ARRAY:
7336 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7337 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7338 /* fallthrough */
7339 case TGSI_TEXTURE_1D:
7340 case TGSI_TEXTURE_SHADOW1D:
7341 case TGSI_TEXTURE_1D_ARRAY:
7342 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7343 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7344 }
7345 }
7346 }
7347
7348 /* Obtain the sample index for reading a compressed MSAA color texture.
7349 * To read the FMASK, we use the ldfptr instruction, which tells us
7350 * where the samples are stored.
7351 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7352 * which is the identity mapping. Each nibble says which physical sample
7353 * should be fetched to get that sample.
7354 *
7355 * Assume src.z contains the sample index. It should be modified like this:
7356 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7357 * Then fetch the texel with src.
7358 */
7359 if (read_compressed_msaa) {
7360 unsigned sample_chan = 3;
7361 unsigned temp = r600_get_temp(ctx);
7362 assert(src_loaded);
7363
7364 /* temp.w = ldfptr() */
7365 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7366 tex.op = FETCH_OP_LD;
7367 tex.inst_mod = 1; /* to indicate this is ldfptr */
7368 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7369 tex.sampler_index_mode = sampler_index_mode;
7370 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7371 tex.resource_index_mode = sampler_index_mode;
7372 tex.src_gpr = src_gpr;
7373 tex.dst_gpr = temp;
7374 tex.dst_sel_x = 7; /* mask out these components */
7375 tex.dst_sel_y = 7;
7376 tex.dst_sel_z = 7;
7377 tex.dst_sel_w = 0; /* store X */
7378 tex.src_sel_x = 0;
7379 tex.src_sel_y = 1;
7380 tex.src_sel_z = 2;
7381 tex.src_sel_w = 3;
7382 tex.offset_x = offset_x;
7383 tex.offset_y = offset_y;
7384 tex.offset_z = offset_z;
7385 r = r600_bytecode_add_tex(ctx->bc, &tex);
7386 if (r)
7387 return r;
7388
7389 /* temp.x = sample_index*4 */
7390 if (ctx->bc->chip_class == CAYMAN) {
7391 for (i = 0 ; i < 4; i++) {
7392 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7393 alu.op = ALU_OP2_MULLO_INT;
7394 alu.src[0].sel = src_gpr;
7395 alu.src[0].chan = sample_chan;
7396 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7397 alu.src[1].value = 4;
7398 alu.dst.sel = temp;
7399 alu.dst.chan = i;
7400 alu.dst.write = i == 0;
7401 if (i == 3)
7402 alu.last = 1;
7403 r = r600_bytecode_add_alu(ctx->bc, &alu);
7404 if (r)
7405 return r;
7406 }
7407 } else {
7408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7409 alu.op = ALU_OP2_MULLO_INT;
7410 alu.src[0].sel = src_gpr;
7411 alu.src[0].chan = sample_chan;
7412 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7413 alu.src[1].value = 4;
7414 alu.dst.sel = temp;
7415 alu.dst.chan = 0;
7416 alu.dst.write = 1;
7417 alu.last = 1;
7418 r = r600_bytecode_add_alu(ctx->bc, &alu);
7419 if (r)
7420 return r;
7421 }
7422
7423 /* sample_index = temp.w >> temp.x */
7424 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7425 alu.op = ALU_OP2_LSHR_INT;
7426 alu.src[0].sel = temp;
7427 alu.src[0].chan = 3;
7428 alu.src[1].sel = temp;
7429 alu.src[1].chan = 0;
7430 alu.dst.sel = src_gpr;
7431 alu.dst.chan = sample_chan;
7432 alu.dst.write = 1;
7433 alu.last = 1;
7434 r = r600_bytecode_add_alu(ctx->bc, &alu);
7435 if (r)
7436 return r;
7437
7438 /* sample_index & 0xF */
7439 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7440 alu.op = ALU_OP2_AND_INT;
7441 alu.src[0].sel = src_gpr;
7442 alu.src[0].chan = sample_chan;
7443 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7444 alu.src[1].value = 0xF;
7445 alu.dst.sel = src_gpr;
7446 alu.dst.chan = sample_chan;
7447 alu.dst.write = 1;
7448 alu.last = 1;
7449 r = r600_bytecode_add_alu(ctx->bc, &alu);
7450 if (r)
7451 return r;
7452 #if 0
7453 /* visualize the FMASK */
7454 for (i = 0; i < 4; i++) {
7455 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7456 alu.op = ALU_OP1_INT_TO_FLT;
7457 alu.src[0].sel = src_gpr;
7458 alu.src[0].chan = sample_chan;
7459 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7460 alu.dst.chan = i;
7461 alu.dst.write = 1;
7462 alu.last = 1;
7463 r = r600_bytecode_add_alu(ctx->bc, &alu);
7464 if (r)
7465 return r;
7466 }
7467 return 0;
7468 #endif
7469 }
7470
7471 /* does this shader want a num layers from TXQ for a cube array? */
7472 if (has_txq_cube_array_z) {
7473 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7474
7475 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7476 alu.op = ALU_OP1_MOV;
7477
7478 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7479 if (ctx->bc->chip_class >= EVERGREEN) {
7480 /* channel 1 or 3 of each word */
7481 alu.src[0].sel += (id / 2);
7482 alu.src[0].chan = ((id % 2) * 2) + 1;
7483 } else {
7484 /* r600 we have them at channel 2 of the second dword */
7485 alu.src[0].sel += (id * 2) + 1;
7486 alu.src[0].chan = 2;
7487 }
7488 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7489 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7490 alu.last = 1;
7491 r = r600_bytecode_add_alu(ctx->bc, &alu);
7492 if (r)
7493 return r;
7494 /* disable writemask from texture instruction */
7495 inst->Dst[0].Register.WriteMask &= ~4;
7496 }
7497
7498 opcode = ctx->inst_info->op;
7499 if (opcode == FETCH_OP_GATHER4 &&
7500 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7501 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7502 opcode = FETCH_OP_GATHER4_O;
7503
7504 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7505 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7506 encoded in the instruction are ignored. */
7507 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7508 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7509 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7510 tex.sampler_index_mode = sampler_index_mode;
7511 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7512 tex.resource_index_mode = sampler_index_mode;
7513
7514 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7515 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7516 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7517 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7518 tex.src_sel_w = 4;
7519
7520 tex.dst_sel_x = 7;
7521 tex.dst_sel_y = 7;
7522 tex.dst_sel_z = 7;
7523 tex.dst_sel_w = 7;
7524
7525 r = r600_bytecode_add_tex(ctx->bc, &tex);
7526 if (r)
7527 return r;
7528 }
7529
7530 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7531 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7532 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7533 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7534 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7535 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7536 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7537 switch (opcode) {
7538 case FETCH_OP_SAMPLE:
7539 opcode = FETCH_OP_SAMPLE_C;
7540 break;
7541 case FETCH_OP_SAMPLE_L:
7542 opcode = FETCH_OP_SAMPLE_C_L;
7543 break;
7544 case FETCH_OP_SAMPLE_LB:
7545 opcode = FETCH_OP_SAMPLE_C_LB;
7546 break;
7547 case FETCH_OP_SAMPLE_G:
7548 opcode = FETCH_OP_SAMPLE_C_G;
7549 break;
7550 /* Texture gather variants */
7551 case FETCH_OP_GATHER4:
7552 opcode = FETCH_OP_GATHER4_C;
7553 break;
7554 case FETCH_OP_GATHER4_O:
7555 opcode = FETCH_OP_GATHER4_C_O;
7556 break;
7557 }
7558 }
7559
7560 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7561 tex.op = opcode;
7562
7563 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7564 tex.sampler_index_mode = sampler_index_mode;
7565 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7566 tex.resource_index_mode = sampler_index_mode;
7567 tex.src_gpr = src_gpr;
7568 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7569
7570 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7571 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7572 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7573 }
7574
7575 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7576 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7577 tex.inst_mod = texture_component_select;
7578
7579 if (ctx->bc->chip_class == CAYMAN) {
7580 /* GATHER4 result order is different from TGSI TG4 */
7581 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7582 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7583 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7584 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7585 } else {
7586 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7587 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7588 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7589 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7590 }
7591 }
7592 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7593 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7594 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7595 tex.dst_sel_z = 7;
7596 tex.dst_sel_w = 7;
7597 }
7598 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7599 tex.dst_sel_x = 3;
7600 tex.dst_sel_y = 7;
7601 tex.dst_sel_z = 7;
7602 tex.dst_sel_w = 7;
7603 }
7604 else {
7605 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7606 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7607 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7608 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7609 }
7610
7611
7612 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7613 tex.src_sel_x = 4;
7614 tex.src_sel_y = 4;
7615 tex.src_sel_z = 4;
7616 tex.src_sel_w = 4;
7617 } else if (src_loaded) {
7618 tex.src_sel_x = 0;
7619 tex.src_sel_y = 1;
7620 tex.src_sel_z = 2;
7621 tex.src_sel_w = 3;
7622 } else {
7623 tex.src_sel_x = ctx->src[0].swizzle[0];
7624 tex.src_sel_y = ctx->src[0].swizzle[1];
7625 tex.src_sel_z = ctx->src[0].swizzle[2];
7626 tex.src_sel_w = ctx->src[0].swizzle[3];
7627 tex.src_rel = ctx->src[0].rel;
7628 }
7629
7630 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7631 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7632 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7633 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7634 tex.src_sel_x = 1;
7635 tex.src_sel_y = 0;
7636 tex.src_sel_z = 3;
7637 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7638 }
7639
7640 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7641 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7642 tex.coord_type_x = 1;
7643 tex.coord_type_y = 1;
7644 }
7645 tex.coord_type_z = 1;
7646 tex.coord_type_w = 1;
7647
7648 tex.offset_x = offset_x;
7649 tex.offset_y = offset_y;
7650 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7651 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7652 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7653 tex.offset_z = 0;
7654 }
7655 else {
7656 tex.offset_z = offset_z;
7657 }
7658
7659 /* Put the depth for comparison in W.
7660 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7661 * Some instructions expect the depth in Z. */
7662 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7663 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7664 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7665 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7666 opcode != FETCH_OP_SAMPLE_C_L &&
7667 opcode != FETCH_OP_SAMPLE_C_LB) {
7668 tex.src_sel_w = tex.src_sel_z;
7669 }
7670
7671 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7672 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7673 if (opcode == FETCH_OP_SAMPLE_C_L ||
7674 opcode == FETCH_OP_SAMPLE_C_LB) {
7675 /* the array index is read from Y */
7676 tex.coord_type_y = 0;
7677 } else {
7678 /* the array index is read from Z */
7679 tex.coord_type_z = 0;
7680 tex.src_sel_z = tex.src_sel_y;
7681 }
7682 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7683 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7684 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7685 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7686 (ctx->bc->chip_class >= EVERGREEN)))
7687 /* the array index is read from Z */
7688 tex.coord_type_z = 0;
7689
7690 /* mask unused source components */
7691 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7692 switch (inst->Texture.Texture) {
7693 case TGSI_TEXTURE_2D:
7694 case TGSI_TEXTURE_RECT:
7695 tex.src_sel_z = 7;
7696 tex.src_sel_w = 7;
7697 break;
7698 case TGSI_TEXTURE_1D_ARRAY:
7699 tex.src_sel_y = 7;
7700 tex.src_sel_w = 7;
7701 break;
7702 case TGSI_TEXTURE_1D:
7703 tex.src_sel_y = 7;
7704 tex.src_sel_z = 7;
7705 tex.src_sel_w = 7;
7706 break;
7707 }
7708 }
7709
7710 r = r600_bytecode_add_tex(ctx->bc, &tex);
7711 if (r)
7712 return r;
7713
7714 /* add shadow ambient support - gallium doesn't do it yet */
7715 return 0;
7716 }
7717
7718 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7719 struct tgsi_full_src_register *src)
7720 {
7721 int i;
7722
7723 if (src->Register.Indirect) {
7724 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7725 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7726 return ctx->shader->atomics[i].hw_idx;
7727 }
7728 } else {
7729 uint32_t index = src->Register.Index;
7730 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7731 if (ctx->shader->atomics[i].buffer_id != src->Dimension.Index)
7732 continue;
7733 if (index > ctx->shader->atomics[i].end)
7734 continue;
7735 if (index < ctx->shader->atomics[i].start)
7736 continue;
7737 uint32_t offset = (index - ctx->shader->atomics[i].start);
7738 return ctx->shader->atomics[i].hw_idx + offset;
7739 }
7740 }
7741 assert(0);
7742 return -1;
7743 }
7744
7745
7746 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7747 {
7748 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7749 int r;
7750 struct r600_bytecode_gds gds;
7751 int uav_id = 0;
7752 int uav_index_mode = 0;
7753
7754 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7755
7756 if (inst->Src[0].Register.Indirect)
7757 uav_index_mode = 2;
7758
7759 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7760 gds.op = FETCH_OP_GDS_READ_RET;
7761 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7762 gds.uav_id = uav_id;
7763 gds.uav_index_mode = uav_index_mode;
7764 gds.src_gpr = ctx->temp_reg;
7765 gds.src_sel_x = 4;
7766 gds.src_sel_y = 4;
7767 gds.src_sel_z = 4;
7768 gds.dst_sel_x = 0;
7769 gds.dst_sel_y = 7;
7770 gds.dst_sel_z = 7;
7771 gds.dst_sel_w = 7;
7772 gds.src_gpr2 = ctx->temp_reg;
7773 gds.alloc_consume = 1;
7774 r = r600_bytecode_add_gds(ctx->bc, &gds);
7775 if (r)
7776 return r;
7777
7778 ctx->bc->cf_last->vpm = 1;
7779 return 0;
7780 }
7781
7782 /* this fixes up 1D arrays properly */
7783 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
7784 {
7785 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7786 int r, i;
7787 struct r600_bytecode_alu alu;
7788 int temp_reg = r600_get_temp(ctx);
7789
7790 for (i = 0; i < 4; i++) {
7791 bool def_val = true, write_zero = false;
7792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7793 alu.op = ALU_OP1_MOV;
7794 alu.dst.sel = temp_reg;
7795 alu.dst.chan = i;
7796
7797 switch (inst->Memory.Texture) {
7798 case TGSI_TEXTURE_BUFFER:
7799 case TGSI_TEXTURE_1D:
7800 if (i == 1 || i == 2 || i == 3) {
7801 write_zero = true;
7802 }
7803 break;
7804 case TGSI_TEXTURE_1D_ARRAY:
7805 if (i == 1 || i == 3)
7806 write_zero = true;
7807 else if (i == 2) {
7808 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
7809 def_val = false;
7810 }
7811 break;
7812 case TGSI_TEXTURE_2D:
7813 if (i == 2 || i == 3)
7814 write_zero = true;
7815 break;
7816 default:
7817 if (i == 3)
7818 write_zero = true;
7819 break;
7820 }
7821
7822 if (write_zero) {
7823 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
7824 alu.src[0].value = 0;
7825 } else if (def_val) {
7826 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
7827 }
7828
7829 if (i == 3)
7830 alu.last = 1;
7831 alu.dst.write = 1;
7832 r = r600_bytecode_add_alu(ctx->bc, &alu);
7833 if (r)
7834 return r;
7835 }
7836 *idx_gpr = temp_reg;
7837 return 0;
7838 }
7839
7840 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
7841 {
7842 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7843 /* have to work out the offset into the RAT immediate return buffer */
7844 struct r600_bytecode_vtx vtx;
7845 struct r600_bytecode_cf *cf;
7846 int r;
7847 int idx_gpr;
7848 unsigned format, num_format, format_comp, endian;
7849 const struct util_format_description *desc;
7850 unsigned rat_index_mode;
7851 unsigned immed_base;
7852
7853 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7854
7855 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
7856 r = load_index_src(ctx, 1, &idx_gpr);
7857 if (r)
7858 return r;
7859
7860 if (rat_index_mode)
7861 egcm_load_index_reg(ctx->bc, 1, false);
7862
7863 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
7864 cf = ctx->bc->cf_last;
7865
7866 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
7867 cf->rat.inst = V_RAT_INST_NOP_RTN;
7868 cf->rat.index_mode = rat_index_mode;
7869 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
7870 cf->output.gpr = ctx->thread_id_gpr;
7871 cf->output.index_gpr = idx_gpr;
7872 cf->output.comp_mask = 0xf;
7873 cf->output.burst_count = 1;
7874 cf->vpm = 1;
7875 cf->barrier = 1;
7876 cf->mark = 1;
7877 cf->output.elem_size = 0;
7878
7879 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
7880 cf = ctx->bc->cf_last;
7881 cf->barrier = 1;
7882
7883 desc = util_format_description(inst->Memory.Format);
7884 r600_vertex_data_type(inst->Memory.Format,
7885 &format, &num_format, &format_comp, &endian);
7886 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
7887 vtx.op = FETCH_OP_VFETCH;
7888 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
7889 vtx.buffer_index_mode = rat_index_mode;
7890 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
7891 vtx.src_gpr = ctx->thread_id_gpr;
7892 vtx.src_sel_x = 1;
7893 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7894 vtx.dst_sel_x = desc->swizzle[0];
7895 vtx.dst_sel_y = desc->swizzle[1];
7896 vtx.dst_sel_z = desc->swizzle[2];
7897 vtx.dst_sel_w = desc->swizzle[3];
7898 vtx.srf_mode_all = 1;
7899 vtx.data_format = format;
7900 vtx.num_format_all = num_format;
7901 vtx.format_comp_all = format_comp;
7902 vtx.endian = endian;
7903 vtx.offset = 0;
7904 vtx.mega_fetch_count = 3;
7905 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
7906 if (r)
7907 return r;
7908 cf = ctx->bc->cf_last;
7909 cf->barrier = 1;
7910 return 0;
7911 }
7912
7913 static int tgsi_load(struct r600_shader_ctx *ctx)
7914 {
7915 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7916 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
7917 return tgsi_load_rat(ctx);
7918 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
7919 return tgsi_load_gds(ctx);
7920 return 0;
7921 }
7922
7923 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
7924 {
7925 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7926 struct r600_bytecode_cf *cf;
7927 bool src_requires_loading = false;
7928 int val_gpr, idx_gpr;
7929 int r, i;
7930 unsigned rat_index_mode;
7931
7932 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7933
7934 r = load_index_src(ctx, 0, &idx_gpr);
7935 if (r)
7936 return r;
7937
7938 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
7939 src_requires_loading = true;
7940
7941 if (src_requires_loading) {
7942 struct r600_bytecode_alu alu;
7943 for (i = 0; i < 4; i++) {
7944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7945 alu.op = ALU_OP1_MOV;
7946 alu.dst.sel = ctx->temp_reg;
7947 alu.dst.chan = i;
7948
7949 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
7950 if (i == 3)
7951 alu.last = 1;
7952 alu.dst.write = 1;
7953 r = r600_bytecode_add_alu(ctx->bc, &alu);
7954 if (r)
7955 return r;
7956 }
7957 val_gpr = ctx->temp_reg;
7958 } else
7959 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
7960 if (rat_index_mode)
7961 egcm_load_index_reg(ctx->bc, 1, false);
7962
7963 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
7964 cf = ctx->bc->cf_last;
7965
7966 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
7967 cf->rat.inst = V_RAT_INST_STORE_TYPED;
7968 cf->rat.index_mode = rat_index_mode;
7969 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
7970 cf->output.gpr = val_gpr;
7971 cf->output.index_gpr = idx_gpr;
7972 cf->output.comp_mask = 0xf;
7973 cf->output.burst_count = 1;
7974 cf->vpm = 1;
7975 cf->barrier = 1;
7976 cf->output.elem_size = 0;
7977 return 0;
7978 }
7979
7980 static int tgsi_store(struct r600_shader_ctx *ctx)
7981 {
7982 return tgsi_store_rat(ctx);
7983 }
7984
7985 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
7986 {
7987 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7988 /* have to work out the offset into the RAT immediate return buffer */
7989 struct r600_bytecode_alu alu;
7990 struct r600_bytecode_vtx vtx;
7991 struct r600_bytecode_cf *cf;
7992 int r;
7993 int idx_gpr;
7994 unsigned format, num_format, format_comp, endian;
7995 const struct util_format_description *desc;
7996 unsigned rat_index_mode;
7997 unsigned immed_base;
7998
7999 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8000
8001 assert (inst->Src[0].Register.File == TGSI_FILE_IMAGE);
8002 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8003
8004 r = load_index_src(ctx, 1, &idx_gpr);
8005 if (r)
8006 return r;
8007
8008 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8010 alu.op = ALU_OP1_MOV;
8011 alu.dst.sel = ctx->thread_id_gpr;
8012 alu.dst.chan = 0;
8013 alu.dst.write = 1;
8014 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8015 alu.last = 1;
8016 r = r600_bytecode_add_alu(ctx->bc, &alu);
8017 if (r)
8018 return r;
8019
8020 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8021 alu.op = ALU_OP1_MOV;
8022 alu.dst.sel = ctx->thread_id_gpr;
8023 alu.dst.chan = 3;
8024 alu.dst.write = 1;
8025 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8026 alu.last = 1;
8027 r = r600_bytecode_add_alu(ctx->bc, &alu);
8028 if (r)
8029 return r;
8030 } else {
8031 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8032 alu.op = ALU_OP1_MOV;
8033 alu.dst.sel = ctx->thread_id_gpr;
8034 alu.dst.chan = 0;
8035 alu.dst.write = 1;
8036 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8037 alu.last = 1;
8038 r = r600_bytecode_add_alu(ctx->bc, &alu);
8039 if (r)
8040 return r;
8041 }
8042
8043 if (rat_index_mode)
8044 egcm_load_index_reg(ctx->bc, 1, false);
8045 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8046 cf = ctx->bc->cf_last;
8047
8048 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8049 cf->rat.inst = ctx->inst_info->op;
8050 cf->rat.index_mode = rat_index_mode;
8051 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8052 cf->output.gpr = ctx->thread_id_gpr;
8053 cf->output.index_gpr = idx_gpr;
8054 cf->output.comp_mask = 0xf;
8055 cf->output.burst_count = 1;
8056 cf->vpm = 1;
8057 cf->barrier = 1;
8058 cf->mark = 1;
8059 cf->output.elem_size = 0;
8060 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8061 cf = ctx->bc->cf_last;
8062 cf->barrier = 1;
8063 cf->cf_addr = 1;
8064
8065 desc = util_format_description(inst->Memory.Format);
8066 r600_vertex_data_type(inst->Memory.Format,
8067 &format, &num_format, &format_comp, &endian);
8068 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8069 vtx.op = FETCH_OP_VFETCH;
8070 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8071 vtx.buffer_index_mode = rat_index_mode;
8072 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8073 vtx.src_gpr = ctx->thread_id_gpr;
8074 vtx.src_sel_x = 1;
8075 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8076 vtx.dst_sel_x = desc->swizzle[0];
8077 vtx.dst_sel_y = 7;
8078 vtx.dst_sel_z = 7;
8079 vtx.dst_sel_w = 7;
8080 vtx.use_const_fields = 0;
8081 vtx.srf_mode_all = 1;
8082 vtx.data_format = format;
8083 vtx.num_format_all = num_format;
8084 vtx.format_comp_all = format_comp;
8085 vtx.endian = endian;
8086 vtx.offset = 0;
8087 vtx.mega_fetch_count = 0xf;
8088 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8089 if (r)
8090 return r;
8091 cf = ctx->bc->cf_last;
8092 cf->vpm = 1;
8093 cf->barrier = 1;
8094 return 0;
8095 }
8096
8097 static int get_gds_op(int opcode)
8098 {
8099 switch (opcode) {
8100 case TGSI_OPCODE_ATOMUADD:
8101 return FETCH_OP_GDS_ADD_RET;
8102 case TGSI_OPCODE_ATOMAND:
8103 return FETCH_OP_GDS_AND_RET;
8104 case TGSI_OPCODE_ATOMOR:
8105 return FETCH_OP_GDS_OR_RET;
8106 case TGSI_OPCODE_ATOMXOR:
8107 return FETCH_OP_GDS_XOR_RET;
8108 case TGSI_OPCODE_ATOMUMIN:
8109 return FETCH_OP_GDS_MIN_UINT_RET;
8110 case TGSI_OPCODE_ATOMUMAX:
8111 return FETCH_OP_GDS_MAX_UINT_RET;
8112 case TGSI_OPCODE_ATOMXCHG:
8113 return FETCH_OP_GDS_XCHG_RET;
8114 case TGSI_OPCODE_ATOMCAS:
8115 return FETCH_OP_GDS_CMP_XCHG_RET;
8116 default:
8117 return -1;
8118 }
8119 }
8120
8121 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8122 {
8123 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8124 struct r600_bytecode_gds gds;
8125 struct r600_bytecode_alu alu;
8126 int gds_op = get_gds_op(inst->Instruction.Opcode);
8127 int r;
8128 int uav_id = 0;
8129 int uav_index_mode = 0;
8130
8131 if (gds_op == -1) {
8132 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8133 return -1;
8134 }
8135
8136 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
8137
8138 if (inst->Src[0].Register.Indirect)
8139 uav_index_mode = 2;
8140
8141 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8142 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8143 int abs_value = abs(value);
8144 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8145 gds_op = FETCH_OP_GDS_SUB_RET;
8146 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8147 alu.op = ALU_OP1_MOV;
8148 alu.dst.sel = ctx->temp_reg;
8149 alu.dst.chan = 0;
8150 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8151 alu.src[0].value = abs_value;
8152 alu.last = 1;
8153 alu.dst.write = 1;
8154 r = r600_bytecode_add_alu(ctx->bc, &alu);
8155 if (r)
8156 return r;
8157 } else {
8158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8159 alu.op = ALU_OP1_MOV;
8160 alu.dst.sel = ctx->temp_reg;
8161 alu.dst.chan = 0;
8162 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8163 alu.last = 1;
8164 alu.dst.write = 1;
8165 r = r600_bytecode_add_alu(ctx->bc, &alu);
8166 if (r)
8167 return r;
8168 }
8169
8170 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8171 gds.op = gds_op;
8172 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8173 gds.uav_id = uav_id;
8174 gds.uav_index_mode = uav_index_mode;
8175 gds.src_gpr = ctx->temp_reg;
8176 gds.src_gpr2 = ctx->temp_reg;
8177 gds.src_sel_x = 4;
8178 gds.src_sel_y = 0;
8179 gds.src_sel_z = 4;
8180 gds.dst_sel_x = 0;
8181 gds.dst_sel_y = 7;
8182 gds.dst_sel_z = 7;
8183 gds.dst_sel_w = 7;
8184 gds.alloc_consume = 1;
8185 r = r600_bytecode_add_gds(ctx->bc, &gds);
8186 if (r)
8187 return r;
8188 ctx->bc->cf_last->vpm = 1;
8189 return 0;
8190 }
8191
8192 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8193 {
8194 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8195 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8196 return tgsi_atomic_op_rat(ctx);
8197 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8198 return tgsi_atomic_op_gds(ctx);
8199 return 0;
8200 }
8201
8202 static int tgsi_resq(struct r600_shader_ctx *ctx)
8203 {
8204 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8205 unsigned sampler_index_mode;
8206 struct r600_bytecode_tex tex;
8207 int r;
8208 boolean has_txq_cube_array_z = false;
8209
8210 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
8211 ctx->shader->uses_tex_buffers = true;
8212 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset);
8213 }
8214
8215 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
8216 inst->Dst[0].Register.WriteMask & 4) {
8217 ctx->shader->has_txq_cube_array_z_comp = true;
8218 has_txq_cube_array_z = true;
8219 }
8220
8221 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8222 if (sampler_index_mode)
8223 egcm_load_index_reg(ctx->bc, 1, false);
8224
8225
8226 /* does this shader want a num layers from TXQ for a cube array? */
8227 if (has_txq_cube_array_z) {
8228 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
8229 struct r600_bytecode_alu alu;
8230
8231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8232 alu.op = ALU_OP1_MOV;
8233
8234 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8235 /* channel 1 or 3 of each word */
8236 alu.src[0].sel += (id / 2);
8237 alu.src[0].chan = ((id % 2) * 2) + 1;
8238 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8239 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8240 alu.last = 1;
8241 r = r600_bytecode_add_alu(ctx->bc, &alu);
8242 if (r)
8243 return r;
8244 /* disable writemask from texture instruction */
8245 inst->Dst[0].Register.WriteMask &= ~4;
8246 }
8247 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8248 tex.op = ctx->inst_info->op;
8249 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
8250 tex.sampler_index_mode = sampler_index_mode;
8251 tex.resource_id = tex.sampler_id;
8252 tex.resource_index_mode = sampler_index_mode;
8253 tex.src_sel_x = 4;
8254 tex.src_sel_y = 4;
8255 tex.src_sel_z = 4;
8256 tex.src_sel_w = 4;
8257 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8258 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8259 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8260 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8261 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8262 r = r600_bytecode_add_tex(ctx->bc, &tex);
8263 if (r)
8264 return r;
8265
8266 return 0;
8267 }
8268
8269 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8270 {
8271 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8272 struct r600_bytecode_alu alu;
8273 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8274 unsigned i, temp_regs[2];
8275 int r;
8276
8277 /* optimize if it's just an equal balance */
8278 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8279 for (i = 0; i < lasti + 1; i++) {
8280 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8281 continue;
8282
8283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8284 alu.op = ALU_OP2_ADD;
8285 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8286 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8287 alu.omod = 3;
8288 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8289 alu.dst.chan = i;
8290 if (i == lasti) {
8291 alu.last = 1;
8292 }
8293 r = r600_bytecode_add_alu(ctx->bc, &alu);
8294 if (r)
8295 return r;
8296 }
8297 return 0;
8298 }
8299
8300 /* 1 - src0 */
8301 for (i = 0; i < lasti + 1; i++) {
8302 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8303 continue;
8304
8305 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8306 alu.op = ALU_OP2_ADD;
8307 alu.src[0].sel = V_SQ_ALU_SRC_1;
8308 alu.src[0].chan = 0;
8309 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8310 r600_bytecode_src_toggle_neg(&alu.src[1]);
8311 alu.dst.sel = ctx->temp_reg;
8312 alu.dst.chan = i;
8313 if (i == lasti) {
8314 alu.last = 1;
8315 }
8316 alu.dst.write = 1;
8317 r = r600_bytecode_add_alu(ctx->bc, &alu);
8318 if (r)
8319 return r;
8320 }
8321
8322 /* (1 - src0) * src2 */
8323 for (i = 0; i < lasti + 1; i++) {
8324 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8325 continue;
8326
8327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8328 alu.op = ALU_OP2_MUL;
8329 alu.src[0].sel = ctx->temp_reg;
8330 alu.src[0].chan = i;
8331 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8332 alu.dst.sel = ctx->temp_reg;
8333 alu.dst.chan = i;
8334 if (i == lasti) {
8335 alu.last = 1;
8336 }
8337 alu.dst.write = 1;
8338 r = r600_bytecode_add_alu(ctx->bc, &alu);
8339 if (r)
8340 return r;
8341 }
8342
8343 /* src0 * src1 + (1 - src0) * src2 */
8344 if (ctx->src[0].abs)
8345 temp_regs[0] = r600_get_temp(ctx);
8346 else
8347 temp_regs[0] = 0;
8348 if (ctx->src[1].abs)
8349 temp_regs[1] = r600_get_temp(ctx);
8350 else
8351 temp_regs[1] = 0;
8352
8353 for (i = 0; i < lasti + 1; i++) {
8354 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8355 continue;
8356
8357 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8358 alu.op = ALU_OP3_MULADD;
8359 alu.is_op3 = 1;
8360 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8361 if (r)
8362 return r;
8363 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
8364 if (r)
8365 return r;
8366 alu.src[2].sel = ctx->temp_reg;
8367 alu.src[2].chan = i;
8368
8369 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8370 alu.dst.chan = i;
8371 if (i == lasti) {
8372 alu.last = 1;
8373 }
8374 r = r600_bytecode_add_alu(ctx->bc, &alu);
8375 if (r)
8376 return r;
8377 }
8378 return 0;
8379 }
8380
8381 static int tgsi_cmp(struct r600_shader_ctx *ctx)
8382 {
8383 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8384 struct r600_bytecode_alu alu;
8385 int i, r, j;
8386 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8387 int temp_regs[3];
8388 unsigned op;
8389
8390 if (ctx->src[0].abs && ctx->src[0].neg) {
8391 op = ALU_OP3_CNDE;
8392 ctx->src[0].abs = 0;
8393 ctx->src[0].neg = 0;
8394 } else {
8395 op = ALU_OP3_CNDGE;
8396 }
8397
8398 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
8399 temp_regs[j] = 0;
8400 if (ctx->src[j].abs)
8401 temp_regs[j] = r600_get_temp(ctx);
8402 }
8403
8404 for (i = 0; i < lasti + 1; i++) {
8405 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8406 continue;
8407
8408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8409 alu.op = op;
8410 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8411 if (r)
8412 return r;
8413 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
8414 if (r)
8415 return r;
8416 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
8417 if (r)
8418 return r;
8419 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8420 alu.dst.chan = i;
8421 alu.dst.write = 1;
8422 alu.is_op3 = 1;
8423 if (i == lasti)
8424 alu.last = 1;
8425 r = r600_bytecode_add_alu(ctx->bc, &alu);
8426 if (r)
8427 return r;
8428 }
8429 return 0;
8430 }
8431
8432 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
8433 {
8434 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8435 struct r600_bytecode_alu alu;
8436 int i, r;
8437 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8438
8439 for (i = 0; i < lasti + 1; i++) {
8440 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8441 continue;
8442
8443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8444 alu.op = ALU_OP3_CNDE_INT;
8445 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8446 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8447 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
8448 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8449 alu.dst.chan = i;
8450 alu.dst.write = 1;
8451 alu.is_op3 = 1;
8452 if (i == lasti)
8453 alu.last = 1;
8454 r = r600_bytecode_add_alu(ctx->bc, &alu);
8455 if (r)
8456 return r;
8457 }
8458 return 0;
8459 }
8460
8461 static int tgsi_exp(struct r600_shader_ctx *ctx)
8462 {
8463 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8464 struct r600_bytecode_alu alu;
8465 int r;
8466 unsigned i;
8467
8468 /* result.x = 2^floor(src); */
8469 if (inst->Dst[0].Register.WriteMask & 1) {
8470 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8471
8472 alu.op = ALU_OP1_FLOOR;
8473 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8474
8475 alu.dst.sel = ctx->temp_reg;
8476 alu.dst.chan = 0;
8477 alu.dst.write = 1;
8478 alu.last = 1;
8479 r = r600_bytecode_add_alu(ctx->bc, &alu);
8480 if (r)
8481 return r;
8482
8483 if (ctx->bc->chip_class == CAYMAN) {
8484 for (i = 0; i < 3; i++) {
8485 alu.op = ALU_OP1_EXP_IEEE;
8486 alu.src[0].sel = ctx->temp_reg;
8487 alu.src[0].chan = 0;
8488
8489 alu.dst.sel = ctx->temp_reg;
8490 alu.dst.chan = i;
8491 alu.dst.write = i == 0;
8492 alu.last = i == 2;
8493 r = r600_bytecode_add_alu(ctx->bc, &alu);
8494 if (r)
8495 return r;
8496 }
8497 } else {
8498 alu.op = ALU_OP1_EXP_IEEE;
8499 alu.src[0].sel = ctx->temp_reg;
8500 alu.src[0].chan = 0;
8501
8502 alu.dst.sel = ctx->temp_reg;
8503 alu.dst.chan = 0;
8504 alu.dst.write = 1;
8505 alu.last = 1;
8506 r = r600_bytecode_add_alu(ctx->bc, &alu);
8507 if (r)
8508 return r;
8509 }
8510 }
8511
8512 /* result.y = tmp - floor(tmp); */
8513 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8514 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8515
8516 alu.op = ALU_OP1_FRACT;
8517 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8518
8519 alu.dst.sel = ctx->temp_reg;
8520 #if 0
8521 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8522 if (r)
8523 return r;
8524 #endif
8525 alu.dst.write = 1;
8526 alu.dst.chan = 1;
8527
8528 alu.last = 1;
8529
8530 r = r600_bytecode_add_alu(ctx->bc, &alu);
8531 if (r)
8532 return r;
8533 }
8534
8535 /* result.z = RoughApprox2ToX(tmp);*/
8536 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
8537 if (ctx->bc->chip_class == CAYMAN) {
8538 for (i = 0; i < 3; i++) {
8539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8540 alu.op = ALU_OP1_EXP_IEEE;
8541 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8542
8543 alu.dst.sel = ctx->temp_reg;
8544 alu.dst.chan = i;
8545 if (i == 2) {
8546 alu.dst.write = 1;
8547 alu.last = 1;
8548 }
8549
8550 r = r600_bytecode_add_alu(ctx->bc, &alu);
8551 if (r)
8552 return r;
8553 }
8554 } else {
8555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8556 alu.op = ALU_OP1_EXP_IEEE;
8557 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8558
8559 alu.dst.sel = ctx->temp_reg;
8560 alu.dst.write = 1;
8561 alu.dst.chan = 2;
8562
8563 alu.last = 1;
8564
8565 r = r600_bytecode_add_alu(ctx->bc, &alu);
8566 if (r)
8567 return r;
8568 }
8569 }
8570
8571 /* result.w = 1.0;*/
8572 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
8573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8574
8575 alu.op = ALU_OP1_MOV;
8576 alu.src[0].sel = V_SQ_ALU_SRC_1;
8577 alu.src[0].chan = 0;
8578
8579 alu.dst.sel = ctx->temp_reg;
8580 alu.dst.chan = 3;
8581 alu.dst.write = 1;
8582 alu.last = 1;
8583 r = r600_bytecode_add_alu(ctx->bc, &alu);
8584 if (r)
8585 return r;
8586 }
8587 return tgsi_helper_copy(ctx, inst);
8588 }
8589
8590 static int tgsi_log(struct r600_shader_ctx *ctx)
8591 {
8592 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8593 struct r600_bytecode_alu alu;
8594 int r;
8595 unsigned i;
8596
8597 /* result.x = floor(log2(|src|)); */
8598 if (inst->Dst[0].Register.WriteMask & 1) {
8599 if (ctx->bc->chip_class == CAYMAN) {
8600 for (i = 0; i < 3; i++) {
8601 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8602
8603 alu.op = ALU_OP1_LOG_IEEE;
8604 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8605 r600_bytecode_src_set_abs(&alu.src[0]);
8606
8607 alu.dst.sel = ctx->temp_reg;
8608 alu.dst.chan = i;
8609 if (i == 0)
8610 alu.dst.write = 1;
8611 if (i == 2)
8612 alu.last = 1;
8613 r = r600_bytecode_add_alu(ctx->bc, &alu);
8614 if (r)
8615 return r;
8616 }
8617
8618 } else {
8619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8620
8621 alu.op = ALU_OP1_LOG_IEEE;
8622 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8623 r600_bytecode_src_set_abs(&alu.src[0]);
8624
8625 alu.dst.sel = ctx->temp_reg;
8626 alu.dst.chan = 0;
8627 alu.dst.write = 1;
8628 alu.last = 1;
8629 r = r600_bytecode_add_alu(ctx->bc, &alu);
8630 if (r)
8631 return r;
8632 }
8633
8634 alu.op = ALU_OP1_FLOOR;
8635 alu.src[0].sel = ctx->temp_reg;
8636 alu.src[0].chan = 0;
8637
8638 alu.dst.sel = ctx->temp_reg;
8639 alu.dst.chan = 0;
8640 alu.dst.write = 1;
8641 alu.last = 1;
8642
8643 r = r600_bytecode_add_alu(ctx->bc, &alu);
8644 if (r)
8645 return r;
8646 }
8647
8648 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
8649 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
8650
8651 if (ctx->bc->chip_class == CAYMAN) {
8652 for (i = 0; i < 3; i++) {
8653 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8654
8655 alu.op = ALU_OP1_LOG_IEEE;
8656 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8657 r600_bytecode_src_set_abs(&alu.src[0]);
8658
8659 alu.dst.sel = ctx->temp_reg;
8660 alu.dst.chan = i;
8661 if (i == 1)
8662 alu.dst.write = 1;
8663 if (i == 2)
8664 alu.last = 1;
8665
8666 r = r600_bytecode_add_alu(ctx->bc, &alu);
8667 if (r)
8668 return r;
8669 }
8670 } else {
8671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8672
8673 alu.op = ALU_OP1_LOG_IEEE;
8674 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8675 r600_bytecode_src_set_abs(&alu.src[0]);
8676
8677 alu.dst.sel = ctx->temp_reg;
8678 alu.dst.chan = 1;
8679 alu.dst.write = 1;
8680 alu.last = 1;
8681
8682 r = r600_bytecode_add_alu(ctx->bc, &alu);
8683 if (r)
8684 return r;
8685 }
8686
8687 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8688
8689 alu.op = ALU_OP1_FLOOR;
8690 alu.src[0].sel = ctx->temp_reg;
8691 alu.src[0].chan = 1;
8692
8693 alu.dst.sel = ctx->temp_reg;
8694 alu.dst.chan = 1;
8695 alu.dst.write = 1;
8696 alu.last = 1;
8697
8698 r = r600_bytecode_add_alu(ctx->bc, &alu);
8699 if (r)
8700 return r;
8701
8702 if (ctx->bc->chip_class == CAYMAN) {
8703 for (i = 0; i < 3; i++) {
8704 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8705 alu.op = ALU_OP1_EXP_IEEE;
8706 alu.src[0].sel = ctx->temp_reg;
8707 alu.src[0].chan = 1;
8708
8709 alu.dst.sel = ctx->temp_reg;
8710 alu.dst.chan = i;
8711 if (i == 1)
8712 alu.dst.write = 1;
8713 if (i == 2)
8714 alu.last = 1;
8715
8716 r = r600_bytecode_add_alu(ctx->bc, &alu);
8717 if (r)
8718 return r;
8719 }
8720 } else {
8721 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8722 alu.op = ALU_OP1_EXP_IEEE;
8723 alu.src[0].sel = ctx->temp_reg;
8724 alu.src[0].chan = 1;
8725
8726 alu.dst.sel = ctx->temp_reg;
8727 alu.dst.chan = 1;
8728 alu.dst.write = 1;
8729 alu.last = 1;
8730
8731 r = r600_bytecode_add_alu(ctx->bc, &alu);
8732 if (r)
8733 return r;
8734 }
8735
8736 if (ctx->bc->chip_class == CAYMAN) {
8737 for (i = 0; i < 3; i++) {
8738 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8739 alu.op = ALU_OP1_RECIP_IEEE;
8740 alu.src[0].sel = ctx->temp_reg;
8741 alu.src[0].chan = 1;
8742
8743 alu.dst.sel = ctx->temp_reg;
8744 alu.dst.chan = i;
8745 if (i == 1)
8746 alu.dst.write = 1;
8747 if (i == 2)
8748 alu.last = 1;
8749
8750 r = r600_bytecode_add_alu(ctx->bc, &alu);
8751 if (r)
8752 return r;
8753 }
8754 } else {
8755 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8756 alu.op = ALU_OP1_RECIP_IEEE;
8757 alu.src[0].sel = ctx->temp_reg;
8758 alu.src[0].chan = 1;
8759
8760 alu.dst.sel = ctx->temp_reg;
8761 alu.dst.chan = 1;
8762 alu.dst.write = 1;
8763 alu.last = 1;
8764
8765 r = r600_bytecode_add_alu(ctx->bc, &alu);
8766 if (r)
8767 return r;
8768 }
8769
8770 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8771
8772 alu.op = ALU_OP2_MUL;
8773
8774 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8775 r600_bytecode_src_set_abs(&alu.src[0]);
8776
8777 alu.src[1].sel = ctx->temp_reg;
8778 alu.src[1].chan = 1;
8779
8780 alu.dst.sel = ctx->temp_reg;
8781 alu.dst.chan = 1;
8782 alu.dst.write = 1;
8783 alu.last = 1;
8784
8785 r = r600_bytecode_add_alu(ctx->bc, &alu);
8786 if (r)
8787 return r;
8788 }
8789
8790 /* result.z = log2(|src|);*/
8791 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
8792 if (ctx->bc->chip_class == CAYMAN) {
8793 for (i = 0; i < 3; i++) {
8794 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8795
8796 alu.op = ALU_OP1_LOG_IEEE;
8797 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8798 r600_bytecode_src_set_abs(&alu.src[0]);
8799
8800 alu.dst.sel = ctx->temp_reg;
8801 if (i == 2)
8802 alu.dst.write = 1;
8803 alu.dst.chan = i;
8804 if (i == 2)
8805 alu.last = 1;
8806
8807 r = r600_bytecode_add_alu(ctx->bc, &alu);
8808 if (r)
8809 return r;
8810 }
8811 } else {
8812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8813
8814 alu.op = ALU_OP1_LOG_IEEE;
8815 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8816 r600_bytecode_src_set_abs(&alu.src[0]);
8817
8818 alu.dst.sel = ctx->temp_reg;
8819 alu.dst.write = 1;
8820 alu.dst.chan = 2;
8821 alu.last = 1;
8822
8823 r = r600_bytecode_add_alu(ctx->bc, &alu);
8824 if (r)
8825 return r;
8826 }
8827 }
8828
8829 /* result.w = 1.0; */
8830 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
8831 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8832
8833 alu.op = ALU_OP1_MOV;
8834 alu.src[0].sel = V_SQ_ALU_SRC_1;
8835 alu.src[0].chan = 0;
8836
8837 alu.dst.sel = ctx->temp_reg;
8838 alu.dst.chan = 3;
8839 alu.dst.write = 1;
8840 alu.last = 1;
8841
8842 r = r600_bytecode_add_alu(ctx->bc, &alu);
8843 if (r)
8844 return r;
8845 }
8846
8847 return tgsi_helper_copy(ctx, inst);
8848 }
8849
8850 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
8851 {
8852 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8853 struct r600_bytecode_alu alu;
8854 int r;
8855 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8856 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
8857
8858 assert(inst->Dst[0].Register.Index < 3);
8859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8860
8861 switch (inst->Instruction.Opcode) {
8862 case TGSI_OPCODE_ARL:
8863 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
8864 break;
8865 case TGSI_OPCODE_ARR:
8866 alu.op = ALU_OP1_FLT_TO_INT;
8867 break;
8868 case TGSI_OPCODE_UARL:
8869 alu.op = ALU_OP1_MOV;
8870 break;
8871 default:
8872 assert(0);
8873 return -1;
8874 }
8875
8876 for (i = 0; i <= lasti; ++i) {
8877 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8878 continue;
8879 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8880 alu.last = i == lasti;
8881 alu.dst.sel = reg;
8882 alu.dst.chan = i;
8883 alu.dst.write = 1;
8884 r = r600_bytecode_add_alu(ctx->bc, &alu);
8885 if (r)
8886 return r;
8887 }
8888
8889 if (inst->Dst[0].Register.Index > 0)
8890 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
8891 else
8892 ctx->bc->ar_loaded = 0;
8893
8894 return 0;
8895 }
8896 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
8897 {
8898 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8899 struct r600_bytecode_alu alu;
8900 int r;
8901 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8902
8903 switch (inst->Instruction.Opcode) {
8904 case TGSI_OPCODE_ARL:
8905 memset(&alu, 0, sizeof(alu));
8906 alu.op = ALU_OP1_FLOOR;
8907 alu.dst.sel = ctx->bc->ar_reg;
8908 alu.dst.write = 1;
8909 for (i = 0; i <= lasti; ++i) {
8910 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8911 alu.dst.chan = i;
8912 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8913 alu.last = i == lasti;
8914 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8915 return r;
8916 }
8917 }
8918
8919 memset(&alu, 0, sizeof(alu));
8920 alu.op = ALU_OP1_FLT_TO_INT;
8921 alu.src[0].sel = ctx->bc->ar_reg;
8922 alu.dst.sel = ctx->bc->ar_reg;
8923 alu.dst.write = 1;
8924 /* FLT_TO_INT is trans-only on r600/r700 */
8925 alu.last = TRUE;
8926 for (i = 0; i <= lasti; ++i) {
8927 alu.dst.chan = i;
8928 alu.src[0].chan = i;
8929 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8930 return r;
8931 }
8932 break;
8933 case TGSI_OPCODE_ARR:
8934 memset(&alu, 0, sizeof(alu));
8935 alu.op = ALU_OP1_FLT_TO_INT;
8936 alu.dst.sel = ctx->bc->ar_reg;
8937 alu.dst.write = 1;
8938 /* FLT_TO_INT is trans-only on r600/r700 */
8939 alu.last = TRUE;
8940 for (i = 0; i <= lasti; ++i) {
8941 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8942 alu.dst.chan = i;
8943 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8944 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8945 return r;
8946 }
8947 }
8948 break;
8949 case TGSI_OPCODE_UARL:
8950 memset(&alu, 0, sizeof(alu));
8951 alu.op = ALU_OP1_MOV;
8952 alu.dst.sel = ctx->bc->ar_reg;
8953 alu.dst.write = 1;
8954 for (i = 0; i <= lasti; ++i) {
8955 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
8956 alu.dst.chan = i;
8957 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8958 alu.last = i == lasti;
8959 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
8960 return r;
8961 }
8962 }
8963 break;
8964 default:
8965 assert(0);
8966 return -1;
8967 }
8968
8969 ctx->bc->ar_loaded = 0;
8970 return 0;
8971 }
8972
8973 static int tgsi_opdst(struct r600_shader_ctx *ctx)
8974 {
8975 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8976 struct r600_bytecode_alu alu;
8977 int i, r = 0;
8978
8979 for (i = 0; i < 4; i++) {
8980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8981
8982 alu.op = ALU_OP2_MUL;
8983 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8984
8985 if (i == 0 || i == 3) {
8986 alu.src[0].sel = V_SQ_ALU_SRC_1;
8987 } else {
8988 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
8989 }
8990
8991 if (i == 0 || i == 2) {
8992 alu.src[1].sel = V_SQ_ALU_SRC_1;
8993 } else {
8994 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8995 }
8996 if (i == 3)
8997 alu.last = 1;
8998 r = r600_bytecode_add_alu(ctx->bc, &alu);
8999 if (r)
9000 return r;
9001 }
9002 return 0;
9003 }
9004
9005 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
9006 {
9007 struct r600_bytecode_alu alu;
9008 int r;
9009
9010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9011 alu.op = opcode;
9012 alu.execute_mask = 1;
9013 alu.update_pred = 1;
9014
9015 alu.dst.sel = ctx->temp_reg;
9016 alu.dst.write = 1;
9017 alu.dst.chan = 0;
9018
9019 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9020 alu.src[1].sel = V_SQ_ALU_SRC_0;
9021 alu.src[1].chan = 0;
9022
9023 alu.last = 1;
9024
9025 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
9026 if (r)
9027 return r;
9028 return 0;
9029 }
9030
9031 static int pops(struct r600_shader_ctx *ctx, int pops)
9032 {
9033 unsigned force_pop = ctx->bc->force_add_cf;
9034
9035 if (!force_pop) {
9036 int alu_pop = 3;
9037 if (ctx->bc->cf_last) {
9038 if (ctx->bc->cf_last->op == CF_OP_ALU)
9039 alu_pop = 0;
9040 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
9041 alu_pop = 1;
9042 }
9043 alu_pop += pops;
9044 if (alu_pop == 1) {
9045 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
9046 ctx->bc->force_add_cf = 1;
9047 } else if (alu_pop == 2) {
9048 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
9049 ctx->bc->force_add_cf = 1;
9050 } else {
9051 force_pop = 1;
9052 }
9053 }
9054
9055 if (force_pop) {
9056 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
9057 ctx->bc->cf_last->pop_count = pops;
9058 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9059 }
9060
9061 return 0;
9062 }
9063
9064 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
9065 unsigned reason)
9066 {
9067 struct r600_stack_info *stack = &ctx->bc->stack;
9068 unsigned elements, entries;
9069
9070 unsigned entry_size = stack->entry_size;
9071
9072 elements = (stack->loop + stack->push_wqm ) * entry_size;
9073 elements += stack->push;
9074
9075 switch (ctx->bc->chip_class) {
9076 case R600:
9077 case R700:
9078 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9079 * the stack must be reserved to hold the current active/continue
9080 * masks */
9081 if (reason == FC_PUSH_VPM) {
9082 elements += 2;
9083 }
9084 break;
9085
9086 case CAYMAN:
9087 /* r9xx: any stack operation on empty stack consumes 2 additional
9088 * elements */
9089 elements += 2;
9090
9091 /* fallthrough */
9092 /* FIXME: do the two elements added above cover the cases for the
9093 * r8xx+ below? */
9094
9095 case EVERGREEN:
9096 /* r8xx+: 2 extra elements are not always required, but one extra
9097 * element must be added for each of the following cases:
9098 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9099 * stack usage.
9100 * (Currently we don't use ALU_ELSE_AFTER.)
9101 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9102 * PUSH instruction executed.
9103 *
9104 * NOTE: it seems we also need to reserve additional element in some
9105 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9106 * then STACK_SIZE should be 2 instead of 1 */
9107 if (reason == FC_PUSH_VPM) {
9108 elements += 1;
9109 }
9110 break;
9111
9112 default:
9113 assert(0);
9114 break;
9115 }
9116
9117 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9118 * for all chips, so we use 4 in the final formula, not the real entry_size
9119 * for the chip */
9120 entry_size = 4;
9121
9122 entries = (elements + (entry_size - 1)) / entry_size;
9123
9124 if (entries > stack->max_entries)
9125 stack->max_entries = entries;
9126 }
9127
9128 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9129 {
9130 switch(reason) {
9131 case FC_PUSH_VPM:
9132 --ctx->bc->stack.push;
9133 assert(ctx->bc->stack.push >= 0);
9134 break;
9135 case FC_PUSH_WQM:
9136 --ctx->bc->stack.push_wqm;
9137 assert(ctx->bc->stack.push_wqm >= 0);
9138 break;
9139 case FC_LOOP:
9140 --ctx->bc->stack.loop;
9141 assert(ctx->bc->stack.loop >= 0);
9142 break;
9143 default:
9144 assert(0);
9145 break;
9146 }
9147 }
9148
9149 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9150 {
9151 switch (reason) {
9152 case FC_PUSH_VPM:
9153 ++ctx->bc->stack.push;
9154 break;
9155 case FC_PUSH_WQM:
9156 ++ctx->bc->stack.push_wqm;
9157 case FC_LOOP:
9158 ++ctx->bc->stack.loop;
9159 break;
9160 default:
9161 assert(0);
9162 }
9163
9164 callstack_update_max_depth(ctx, reason);
9165 }
9166
9167 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9168 {
9169 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9170
9171 sp->mid = realloc((void *)sp->mid,
9172 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9173 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9174 sp->num_mid++;
9175 }
9176
9177 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9178 {
9179 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9180 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9181 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9182 ctx->bc->fc_sp++;
9183 }
9184
9185 static void fc_poplevel(struct r600_shader_ctx *ctx)
9186 {
9187 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9188 free(sp->mid);
9189 sp->mid = NULL;
9190 sp->num_mid = 0;
9191 sp->start = NULL;
9192 sp->type = 0;
9193 ctx->bc->fc_sp--;
9194 }
9195
9196 #if 0
9197 static int emit_return(struct r600_shader_ctx *ctx)
9198 {
9199 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9200 return 0;
9201 }
9202
9203 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9204 {
9205
9206 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9207 ctx->bc->cf_last->pop_count = pops;
9208 /* XXX work out offset */
9209 return 0;
9210 }
9211
9212 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9213 {
9214 return 0;
9215 }
9216
9217 static void emit_testflag(struct r600_shader_ctx *ctx)
9218 {
9219
9220 }
9221
9222 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9223 {
9224 emit_testflag(ctx);
9225 emit_jump_to_offset(ctx, 1, 4);
9226 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9227 pops(ctx, ifidx + 1);
9228 emit_return(ctx);
9229 }
9230
9231 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9232 {
9233 emit_testflag(ctx);
9234
9235 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9236 ctx->bc->cf_last->pop_count = 1;
9237
9238 fc_set_mid(ctx, fc_sp);
9239
9240 pops(ctx, 1);
9241 }
9242 #endif
9243
9244 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
9245 {
9246 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9247
9248 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9249 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9250 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9251 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9252 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9253 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9254 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9255 alu_type = CF_OP_ALU;
9256 }
9257
9258 emit_logic_pred(ctx, opcode, alu_type);
9259
9260 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9261
9262 fc_pushlevel(ctx, FC_IF);
9263
9264 callstack_push(ctx, FC_PUSH_VPM);
9265 return 0;
9266 }
9267
9268 static int tgsi_if(struct r600_shader_ctx *ctx)
9269 {
9270 return emit_if(ctx, ALU_OP2_PRED_SETNE);
9271 }
9272
9273 static int tgsi_uif(struct r600_shader_ctx *ctx)
9274 {
9275 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
9276 }
9277
9278 static int tgsi_else(struct r600_shader_ctx *ctx)
9279 {
9280 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9281 ctx->bc->cf_last->pop_count = 1;
9282
9283 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9284 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9285 return 0;
9286 }
9287
9288 static int tgsi_endif(struct r600_shader_ctx *ctx)
9289 {
9290 pops(ctx, 1);
9291 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9292 R600_ERR("if/endif unbalanced in shader\n");
9293 return -1;
9294 }
9295
9296 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9297 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9298 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9299 } else {
9300 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9301 }
9302 fc_poplevel(ctx);
9303
9304 callstack_pop(ctx, FC_PUSH_VPM);
9305 return 0;
9306 }
9307
9308 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
9309 {
9310 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9311 * limited to 4096 iterations, like the other LOOP_* instructions. */
9312 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
9313
9314 fc_pushlevel(ctx, FC_LOOP);
9315
9316 /* check stack depth */
9317 callstack_push(ctx, FC_LOOP);
9318 return 0;
9319 }
9320
9321 static int tgsi_endloop(struct r600_shader_ctx *ctx)
9322 {
9323 unsigned i;
9324
9325 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
9326
9327 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
9328 R600_ERR("loop/endloop in shader code are not paired.\n");
9329 return -EINVAL;
9330 }
9331
9332 /* fixup loop pointers - from r600isa
9333 LOOP END points to CF after LOOP START,
9334 LOOP START point to CF after LOOP END
9335 BRK/CONT point to LOOP END CF
9336 */
9337 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
9338
9339 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9340
9341 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
9342 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
9343 }
9344 /* XXX add LOOPRET support */
9345 fc_poplevel(ctx);
9346 callstack_pop(ctx, FC_LOOP);
9347 return 0;
9348 }
9349
9350 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
9351 {
9352 unsigned int fscp;
9353
9354 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
9355 {
9356 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
9357 break;
9358 }
9359
9360 if (fscp == 0) {
9361 R600_ERR("Break not inside loop/endloop pair\n");
9362 return -EINVAL;
9363 }
9364
9365 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9366
9367 fc_set_mid(ctx, fscp - 1);
9368
9369 return 0;
9370 }
9371
9372 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
9373 {
9374 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9375 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
9376 int r;
9377
9378 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9379 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
9380
9381 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9382 if (!r) {
9383 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
9384 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9385 return emit_inc_ring_offset(ctx, stream, TRUE);
9386 }
9387 return r;
9388 }
9389
9390 static int tgsi_umad(struct r600_shader_ctx *ctx)
9391 {
9392 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9393 struct r600_bytecode_alu alu;
9394 int i, j, k, r;
9395 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9396
9397 /* src0 * src1 */
9398 for (i = 0; i < lasti + 1; i++) {
9399 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9400 continue;
9401
9402 if (ctx->bc->chip_class == CAYMAN) {
9403 for (j = 0 ; j < 4; j++) {
9404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9405
9406 alu.op = ALU_OP2_MULLO_UINT;
9407 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
9408 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
9409 }
9410 alu.dst.chan = j;
9411 alu.dst.sel = ctx->temp_reg;
9412 alu.dst.write = (j == i);
9413 if (j == 3)
9414 alu.last = 1;
9415 r = r600_bytecode_add_alu(ctx->bc, &alu);
9416 if (r)
9417 return r;
9418 }
9419 } else {
9420 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9421
9422 alu.dst.chan = i;
9423 alu.dst.sel = ctx->temp_reg;
9424 alu.dst.write = 1;
9425
9426 alu.op = ALU_OP2_MULLO_UINT;
9427 for (j = 0; j < 2; j++) {
9428 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
9429 }
9430
9431 alu.last = 1;
9432 r = r600_bytecode_add_alu(ctx->bc, &alu);
9433 if (r)
9434 return r;
9435 }
9436 }
9437
9438
9439 for (i = 0; i < lasti + 1; i++) {
9440 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9441 continue;
9442
9443 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9444 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9445
9446 alu.op = ALU_OP2_ADD_INT;
9447
9448 alu.src[0].sel = ctx->temp_reg;
9449 alu.src[0].chan = i;
9450
9451 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9452 if (i == lasti) {
9453 alu.last = 1;
9454 }
9455 r = r600_bytecode_add_alu(ctx->bc, &alu);
9456 if (r)
9457 return r;
9458 }
9459 return 0;
9460 }
9461
9462 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
9463 {
9464 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9465 struct r600_bytecode_alu alu;
9466 int r, i;
9467 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9468
9469 /* temp.xy = f32_to_f16(src) */
9470 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9471 alu.op = ALU_OP1_FLT32_TO_FLT16;
9472 alu.dst.chan = 0;
9473 alu.dst.sel = ctx->temp_reg;
9474 alu.dst.write = 1;
9475 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9476 r = r600_bytecode_add_alu(ctx->bc, &alu);
9477 if (r)
9478 return r;
9479 alu.dst.chan = 1;
9480 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
9481 alu.last = 1;
9482 r = r600_bytecode_add_alu(ctx->bc, &alu);
9483 if (r)
9484 return r;
9485
9486 /* dst.x = temp.y * 0x10000 + temp.x */
9487 for (i = 0; i < lasti + 1; i++) {
9488 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9489 continue;
9490
9491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9492 alu.op = ALU_OP3_MULADD_UINT24;
9493 alu.is_op3 = 1;
9494 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9495 alu.last = i == lasti;
9496 alu.src[0].sel = ctx->temp_reg;
9497 alu.src[0].chan = 1;
9498 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9499 alu.src[1].value = 0x10000;
9500 alu.src[2].sel = ctx->temp_reg;
9501 alu.src[2].chan = 0;
9502 r = r600_bytecode_add_alu(ctx->bc, &alu);
9503 if (r)
9504 return r;
9505 }
9506
9507 return 0;
9508 }
9509
9510 static int tgsi_up2h(struct r600_shader_ctx *ctx)
9511 {
9512 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9513 struct r600_bytecode_alu alu;
9514 int r, i;
9515 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9516
9517 /* temp.x = src.x */
9518 /* note: no need to mask out the high bits */
9519 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9520 alu.op = ALU_OP1_MOV;
9521 alu.dst.chan = 0;
9522 alu.dst.sel = ctx->temp_reg;
9523 alu.dst.write = 1;
9524 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9525 r = r600_bytecode_add_alu(ctx->bc, &alu);
9526 if (r)
9527 return r;
9528
9529 /* temp.y = src.x >> 16 */
9530 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9531 alu.op = ALU_OP2_LSHR_INT;
9532 alu.dst.chan = 1;
9533 alu.dst.sel = ctx->temp_reg;
9534 alu.dst.write = 1;
9535 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9536 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9537 alu.src[1].value = 16;
9538 alu.last = 1;
9539 r = r600_bytecode_add_alu(ctx->bc, &alu);
9540 if (r)
9541 return r;
9542
9543 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
9544 for (i = 0; i < lasti + 1; i++) {
9545 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9546 continue;
9547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9548 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9549 alu.op = ALU_OP1_FLT16_TO_FLT32;
9550 alu.src[0].sel = ctx->temp_reg;
9551 alu.src[0].chan = i % 2;
9552 alu.last = i == lasti;
9553 r = r600_bytecode_add_alu(ctx->bc, &alu);
9554 if (r)
9555 return r;
9556 }
9557
9558 return 0;
9559 }
9560
9561 static int tgsi_bfe(struct r600_shader_ctx *ctx)
9562 {
9563 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9564 struct r600_bytecode_alu alu;
9565 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9566 int r, i;
9567
9568 r = tgsi_op3(ctx);
9569 if (r)
9570 return r;
9571
9572 for (i = 0; i < lasti + 1; i++) {
9573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9574 alu.op = ALU_OP2_SETGE_INT;
9575 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
9576 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
9577 alu.src[1].value = 32;
9578 alu.dst.sel = ctx->temp_reg;
9579 alu.dst.chan = i;
9580 alu.dst.write = 1;
9581 if (i == lasti)
9582 alu.last = 1;
9583 r = r600_bytecode_add_alu(ctx->bc, &alu);
9584 if (r)
9585 return r;
9586 }
9587
9588 for (i = 0; i < lasti + 1; i++) {
9589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9590 alu.op = ALU_OP3_CNDE_INT;
9591 alu.is_op3 = 1;
9592 alu.src[0].sel = ctx->temp_reg;
9593 alu.src[1].chan = i;
9594
9595 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9596 alu.src[1].sel = alu.dst.sel;
9597 alu.src[1].chan = i;
9598 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
9599 alu.dst.write = 1;
9600 if (i == lasti)
9601 alu.last = 1;
9602 r = r600_bytecode_add_alu(ctx->bc, &alu);
9603 if (r)
9604 return r;
9605 }
9606
9607 return 0;
9608 }
9609
9610 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
9611 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
9612 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9613 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9614
9615 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9616
9617 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9618 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9619 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9620 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9621 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9622 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9623 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9624 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9625 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
9626 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9627 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9628 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9629 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9630 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9631 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9632 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
9633 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9634 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9635 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9636 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9637 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9638 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9639 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9640 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9641 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9642 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9643 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9644 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9645 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9646 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9647 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9648 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9649 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9650 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9651 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9652 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9653 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
9654 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9655 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9656 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9657 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9658 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9659 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9660 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9661 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9662 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9663 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9664 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9665 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9666 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9667 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9668 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
9669 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9670 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9671 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9672 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9673 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9674 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
9675 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9676 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9677 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9678 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9679 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9680 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9681 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9682 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9683 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9684 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9685 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9686 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9687 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9688 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9689 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9690 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9691 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9692 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9693 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
9694 [81] = { ALU_OP0_NOP, tgsi_unsupported},
9695 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9696 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9697 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9698 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9699 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9700 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
9701 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9702 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9703 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9704 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9705 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9706 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9707 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9708 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9709 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9710 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9711 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9712 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9713 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9714 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9715 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9716 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9717 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9718 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
9719 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9720 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9721 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9722 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9723 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9724 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9725 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
9726 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9727 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9728 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9729 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9730 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9731 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
9732 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
9733 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9734 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9735 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9736 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9737 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9738 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
9739 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9740 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
9741 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9742 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9743 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9744 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9745 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9746 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9747 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9748 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9749 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9750 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9751 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
9752 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9753 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
9754 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9755 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9756 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9757 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9758 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9759 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9760 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9761 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9762 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9763 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9764 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9765 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9766 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9767 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9768 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9769 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9770 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
9771 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9772 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9773 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9774 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
9775 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
9776 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9777 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9778 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9779 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
9780 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
9781 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
9782 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
9783 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
9784 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
9785 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
9786 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9787 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9788 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
9789 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
9790 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9791 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9792 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9793 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9794 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9795 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
9796 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
9797 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
9798 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
9799 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
9800 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
9801 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
9802 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
9803 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
9804 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
9805 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
9806 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
9807 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
9808 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
9809 };
9810
9811 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
9812 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
9813 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
9814 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
9815 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
9816 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
9817 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
9818 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
9819 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
9820 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
9821 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9822 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9823 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
9824 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
9825 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
9826 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
9827 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
9828 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
9829 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
9830 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
9831 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
9832 [21] = { ALU_OP0_NOP, tgsi_unsupported},
9833 [22] = { ALU_OP0_NOP, tgsi_unsupported},
9834 [23] = { ALU_OP0_NOP, tgsi_unsupported},
9835 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
9836 [25] = { ALU_OP0_NOP, tgsi_unsupported},
9837 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
9838 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
9839 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
9840 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
9841 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
9842 [31] = { ALU_OP0_NOP, tgsi_unsupported},
9843 [32] = { ALU_OP0_NOP, tgsi_unsupported},
9844 [33] = { ALU_OP0_NOP, tgsi_unsupported},
9845 [34] = { ALU_OP0_NOP, tgsi_unsupported},
9846 [35] = { ALU_OP0_NOP, tgsi_unsupported},
9847 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
9848 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9849 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9850 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
9851 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
9852 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
9853 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
9854 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9855 [44] = { ALU_OP0_NOP, tgsi_unsupported},
9856 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
9857 [46] = { ALU_OP0_NOP, tgsi_unsupported},
9858 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
9859 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
9860 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
9861 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
9862 [51] = { ALU_OP0_NOP, tgsi_unsupported},
9863 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
9864 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
9865 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
9866 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
9867 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
9868 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
9869 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
9870 [59] = { ALU_OP0_NOP, tgsi_unsupported},
9871 [60] = { ALU_OP0_NOP, tgsi_unsupported},
9872 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
9873 [62] = { ALU_OP0_NOP, tgsi_unsupported},
9874 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
9875 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
9876 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
9877 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
9878 [67] = { ALU_OP0_NOP, tgsi_unsupported},
9879 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9880 [69] = { ALU_OP0_NOP, tgsi_unsupported},
9881 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
9882 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
9883 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9884 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
9885 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
9886 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
9887 [76] = { ALU_OP0_NOP, tgsi_unsupported},
9888 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
9889 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
9890 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
9891 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
9892 [82] = { ALU_OP0_NOP, tgsi_unsupported},
9893 [83] = { ALU_OP0_NOP, tgsi_unsupported},
9894 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
9895 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
9896 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
9897 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
9898 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
9899 [88] = { ALU_OP0_NOP, tgsi_unsupported},
9900 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
9901 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
9902 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
9903 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
9904 [93] = { ALU_OP0_NOP, tgsi_unsupported},
9905 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
9906 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9907 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
9908 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
9909 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
9910 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
9911 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9912 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
9913 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
9914 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
9915 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
9916 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
9917 [106] = { ALU_OP0_NOP, tgsi_unsupported},
9918 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
9919 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
9920 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
9921 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
9922 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
9923 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9924 [113] = { ALU_OP0_NOP, tgsi_unsupported},
9925 [114] = { ALU_OP0_NOP, tgsi_unsupported},
9926 [115] = { ALU_OP0_NOP, tgsi_unsupported},
9927 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
9928 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
9929 /* Refer below for TGSI_OPCODE_DFMA */
9930 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
9931 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
9932 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
9933 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
9934 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
9935 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
9936 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
9937 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
9938 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
9939 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
9940 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
9941 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
9942 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
9943 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
9944 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
9945 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
9946 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
9947 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
9948 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
9949 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
9950 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
9951 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
9952 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9953 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
9954 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
9955 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
9956 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
9957 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
9958 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
9959 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
9960 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
9961 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
9962 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
9963 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
9964 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
9965 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
9966 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
9967 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
9968 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
9969 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
9970 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
9971 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
9972 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
9973 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
9974 [163] = { ALU_OP0_NOP, tgsi_unsupported},
9975 [164] = { ALU_OP0_NOP, tgsi_unsupported},
9976 [165] = { ALU_OP0_NOP, tgsi_unsupported},
9977 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
9978 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
9979 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
9980 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
9981 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
9982 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
9983 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
9984 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
9985 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
9986 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
9987 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
9988 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
9989 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
9990 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
9991 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
9992 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
9993 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
9994 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
9995 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
9996 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
9997 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
9998 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
9999 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10000 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10001 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10002 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10003 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10004 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10005 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10006 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10007 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10008 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10009 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10010 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10011 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10012 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10013 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10014 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10015 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10016 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10017 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10018 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10019 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10020 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10021 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10022 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10023 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10024 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10025 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10026 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10027 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10028 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10029 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10030 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10031 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10032 };
10033
10034 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
10035 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10036 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10037 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10038 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
10039 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
10040 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10041 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10042 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10043 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10044 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10045 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10046 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10047 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10048 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10049 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10050 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10051 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10052 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10053 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10054 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
10055 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10056 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10057 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10058 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10059 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10060 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10061 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10062 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
10063 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
10064 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
10065 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10066 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10067 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10068 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10069 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10070 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
10071 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10072 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10073 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10074 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10075 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10076 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10077 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10078 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10079 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10080 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10081 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10082 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
10083 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10084 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10085 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10086 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10087 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10088 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10089 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10090 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10091 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10092 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10093 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10094 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10095 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10096 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10097 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10098 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10099 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10100 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10101 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10102 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10103 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10104 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10105 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10106 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10107 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10108 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10109 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10110 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10111 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10112 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10113 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10114 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10115 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10116 [83] = { ALU_OP0_NOP, tgsi_unsupported},
10117 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10118 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
10119 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10120 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10121 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10122 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10123 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10124 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10125 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10126 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10127 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10128 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10129 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10130 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10131 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10132 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10133 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10134 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10135 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10136 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10137 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10138 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10139 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10140 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10141 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10142 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10143 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10144 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10145 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10146 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10147 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10148 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10149 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10150 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10151 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10152 /* Refer below for TGSI_OPCODE_DFMA */
10153 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
10154 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10155 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10156 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10157 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10158 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10159 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10160 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10161 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
10162 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
10163 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10164 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10165 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10166 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10167 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10168 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10169 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
10170 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10171 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10172 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10173 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10174 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10175 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10176 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10177 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10178 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10179 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10180 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10181 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10182 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10183 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10184 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10185 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10186 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10187 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10188 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10189 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10190 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10191 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10192 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10193 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10194 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10195 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10196 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10197 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10198 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10199 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10200 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10201 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10202 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10203 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10204 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10205 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10206 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10207 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10208 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10209 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10210 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10211 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10212 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10213 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10214 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
10215 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
10216 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10217 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10218 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10219 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10220 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10221 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10222 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10223 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10224 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10225 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10226 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10227 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10228 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10229 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10230 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10231 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10232 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10233 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10234 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10235 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10236 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10237 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10238 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10239 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10240 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10241 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10242 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10243 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10244 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10245 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10246 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10247 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10248 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10249 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10250 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10251 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10252 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10253 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10254 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10255 };