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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_info.h"
25 #include "tgsi/tgsi_parse.h"
26 #include "tgsi/tgsi_scan.h"
27 #include "tgsi/tgsi_dump.h"
28 #include "util/u_format.h"
29 #include "r600_pipe.h"
30 #include "r600_asm.h"
31 #include "r600_sq.h"
32 #include "r600_formats.h"
33 #include "r600_opcodes.h"
34 #include "r600d.h"
35 #include <stdio.h>
36 #include <errno.h>
37 #include <byteswap.h>
38
39 /* CAYMAN notes
40 Why CAYMAN got loops for lots of instructions is explained here.
41
42 -These 8xx t-slot only ops are implemented in all vector slots.
43 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
44 These 8xx t-slot only opcodes become vector ops, with all four
45 slots expecting the arguments on sources a and b. Result is
46 broadcast to all channels.
47 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
48 These 8xx t-slot only opcodes become vector ops in the z, y, and
49 x slots.
50 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
51 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
52 SQRT_IEEE/_64
53 SIN/COS
54 The w slot may have an independent co-issued operation, or if the
55 result is required to be in the w slot, the opcode above may be
56 issued in the w slot as well.
57 The compiler must issue the source argument to slots z, y, and x
58 */
59
60 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
61 {
62 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
63 struct r600_shader *rshader = &shader->shader;
64 uint32_t *ptr;
65 int i;
66
67 /* copy new shader */
68 if (shader->bo == NULL) {
69 shader->bo = (struct r600_resource*)
70 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, rshader->bc.ndw * 4);
71 if (shader->bo == NULL) {
72 return -ENOMEM;
73 }
74 ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
75 if (R600_BIG_ENDIAN) {
76 for (i = 0; i < rshader->bc.ndw; ++i) {
77 ptr[i] = bswap_32(rshader->bc.bytecode[i]);
78 }
79 } else {
80 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * sizeof(*ptr));
81 }
82 rctx->ws->buffer_unmap(shader->bo->buf);
83 }
84 /* build state */
85 switch (rshader->processor_type) {
86 case TGSI_PROCESSOR_VERTEX:
87 if (rctx->chip_class >= EVERGREEN) {
88 evergreen_pipe_shader_vs(ctx, shader);
89 } else {
90 r600_pipe_shader_vs(ctx, shader);
91 }
92 break;
93 case TGSI_PROCESSOR_FRAGMENT:
94 if (rctx->chip_class >= EVERGREEN) {
95 evergreen_pipe_shader_ps(ctx, shader);
96 } else {
97 r600_pipe_shader_ps(ctx, shader);
98 }
99 break;
100 default:
101 return -EINVAL;
102 }
103 return 0;
104 }
105
106 static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pipe_shader *pipeshader);
107
108 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader)
109 {
110 static int dump_shaders = -1;
111 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
112 int r;
113
114 /* Would like some magic "get_bool_option_once" routine.
115 */
116 if (dump_shaders == -1)
117 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
118
119 if (dump_shaders) {
120 fprintf(stderr, "--------------------------------------------------------------\n");
121 tgsi_dump(shader->tokens, 0);
122
123 if (shader->so.num_outputs) {
124 unsigned i;
125 fprintf(stderr, "STREAMOUT\n");
126 for (i = 0; i < shader->so.num_outputs; i++) {
127 unsigned mask = ((1 << shader->so.output[i].num_components) - 1) <<
128 shader->so.output[i].start_component;
129 fprintf(stderr, " %i: MEM_STREAM0_BUF%i OUT[%i].%s%s%s%s\n", i,
130 shader->so.output[i].output_buffer, shader->so.output[i].register_index,
131 mask & 1 ? "x" : "_",
132 (mask >> 1) & 1 ? "y" : "_",
133 (mask >> 2) & 1 ? "z" : "_",
134 (mask >> 3) & 1 ? "w" : "_");
135 }
136 }
137 }
138 r = r600_shader_from_tgsi(rctx, shader);
139 if (r) {
140 R600_ERR("translation from TGSI failed !\n");
141 return r;
142 }
143 r = r600_bytecode_build(&shader->shader.bc);
144 if (r) {
145 R600_ERR("building bytecode failed !\n");
146 return r;
147 }
148 if (dump_shaders) {
149 r600_bytecode_dump(&shader->shader.bc);
150 fprintf(stderr, "______________________________________________________________\n");
151 }
152 return r600_pipe_shader(ctx, shader);
153 }
154
155 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
156 {
157 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
158 r600_bytecode_clear(&shader->shader.bc);
159
160 memset(&shader->shader,0,sizeof(struct r600_shader));
161 }
162
163 /*
164 * tgsi -> r600 shader
165 */
166 struct r600_shader_tgsi_instruction;
167
168 struct r600_shader_src {
169 unsigned sel;
170 unsigned swizzle[4];
171 unsigned neg;
172 unsigned abs;
173 unsigned rel;
174 uint32_t value[4];
175 };
176
177 struct r600_shader_ctx {
178 struct tgsi_shader_info info;
179 struct tgsi_parse_context parse;
180 const struct tgsi_token *tokens;
181 unsigned type;
182 unsigned file_offset[TGSI_FILE_COUNT];
183 unsigned temp_reg;
184 struct r600_shader_tgsi_instruction *inst_info;
185 struct r600_bytecode *bc;
186 struct r600_shader *shader;
187 struct r600_shader_src src[4];
188 u32 *literals;
189 u32 nliterals;
190 u32 max_driver_temp_used;
191 /* needed for evergreen interpolation */
192 boolean input_centroid;
193 boolean input_linear;
194 boolean input_perspective;
195 int num_interp_gpr;
196 int face_gpr;
197 int colors_used;
198 };
199
200 struct r600_shader_tgsi_instruction {
201 unsigned tgsi_opcode;
202 unsigned is_op3;
203 unsigned r600_opcode;
204 int (*process)(struct r600_shader_ctx *ctx);
205 };
206
207 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
208 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
209
210 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
211 {
212 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
213 int j;
214
215 if (i->Instruction.NumDstRegs > 1) {
216 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
217 return -EINVAL;
218 }
219 if (i->Instruction.Predicate) {
220 R600_ERR("predicate unsupported\n");
221 return -EINVAL;
222 }
223 #if 0
224 if (i->Instruction.Label) {
225 R600_ERR("label unsupported\n");
226 return -EINVAL;
227 }
228 #endif
229 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
230 if (i->Src[j].Register.Dimension) {
231 R600_ERR("unsupported src %d (dimension %d)\n", j,
232 i->Src[j].Register.Dimension);
233 return -EINVAL;
234 }
235 }
236 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
237 if (i->Dst[j].Register.Dimension) {
238 R600_ERR("unsupported dst (dimension)\n");
239 return -EINVAL;
240 }
241 }
242 return 0;
243 }
244
245 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
246 {
247 int i, r;
248 struct r600_bytecode_alu alu;
249 int gpr = 0, base_chan = 0;
250 int ij_index = 0;
251
252 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
253 ij_index = 0;
254 if (ctx->shader->input[input].centroid)
255 ij_index++;
256 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
257 ij_index = 0;
258 /* if we have perspective add one */
259 if (ctx->input_perspective) {
260 ij_index++;
261 /* if we have perspective centroid */
262 if (ctx->input_centroid)
263 ij_index++;
264 }
265 if (ctx->shader->input[input].centroid)
266 ij_index++;
267 }
268
269 /* work out gpr and base_chan from index */
270 gpr = ij_index / 2;
271 base_chan = (2 * (ij_index % 2)) + 1;
272
273 for (i = 0; i < 8; i++) {
274 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
275
276 if (i < 4)
277 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
278 else
279 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
280
281 if ((i > 1) && (i < 6)) {
282 alu.dst.sel = ctx->shader->input[input].gpr;
283 alu.dst.write = 1;
284 }
285
286 alu.dst.chan = i % 4;
287
288 alu.src[0].sel = gpr;
289 alu.src[0].chan = (base_chan - (i % 2));
290
291 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
292
293 alu.bank_swizzle_force = SQ_ALU_VEC_210;
294 if ((i % 4) == 3)
295 alu.last = 1;
296 r = r600_bytecode_add_alu(ctx->bc, &alu);
297 if (r)
298 return r;
299 }
300 return 0;
301 }
302
303 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
304 {
305 int i, r;
306 struct r600_bytecode_alu alu;
307
308 for (i = 0; i < 4; i++) {
309 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
310
311 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0;
312
313 alu.dst.sel = ctx->shader->input[input].gpr;
314 alu.dst.write = 1;
315
316 alu.dst.chan = i;
317
318 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
319 alu.src[0].chan = i;
320
321 if (i == 3)
322 alu.last = 1;
323 r = r600_bytecode_add_alu(ctx->bc, &alu);
324 if (r)
325 return r;
326 }
327 return 0;
328 }
329
330 /*
331 * Special export handling in shaders
332 *
333 * shader export ARRAY_BASE for EXPORT_POS:
334 * 60 is position
335 * 61 is misc vector
336 * 62, 63 are clip distance vectors
337 *
338 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
339 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
340 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
341 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
342 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
343 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
344 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
345 * exclusive from render target index)
346 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
347 *
348 *
349 * shader export ARRAY_BASE for EXPORT_PIXEL:
350 * 0-7 CB targets
351 * 61 computed Z vector
352 *
353 * The use of the values exported in the computed Z vector are controlled
354 * by DB_SHADER_CONTROL:
355 * Z_EXPORT_ENABLE - Z as a float in RED
356 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
357 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
358 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
359 * DB_SOURCE_FORMAT - export control restrictions
360 *
361 */
362
363
364 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
365 static int r600_spi_sid(struct r600_shader_io * io)
366 {
367 int index, name = io->name;
368
369 /* These params are handled differently, they don't need
370 * semantic indices, so we'll use 0 for them.
371 */
372 if (name == TGSI_SEMANTIC_POSITION ||
373 name == TGSI_SEMANTIC_PSIZE ||
374 name == TGSI_SEMANTIC_FACE)
375 index = 0;
376 else {
377 if (name == TGSI_SEMANTIC_GENERIC) {
378 /* For generic params simply use sid from tgsi */
379 index = io->sid;
380 } else {
381 /* For non-generic params - pack name and sid into 8 bits */
382 index = 0x80 | (name<<3) | (io->sid);
383 }
384
385 /* Make sure that all really used indices have nonzero value, so
386 * we can just compare it to 0 later instead of comparing the name
387 * with different values to detect special cases. */
388 index++;
389 }
390
391 return index;
392 };
393
394 /* turn input into interpolate on EG */
395 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
396 {
397 int r = 0;
398
399 if (ctx->shader->input[index].spi_sid) {
400 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
401 if (ctx->shader->input[index].interpolate > 0) {
402 r = evergreen_interp_alu(ctx, index);
403 } else {
404 r = evergreen_interp_flat(ctx, index);
405 }
406 }
407 return r;
408 }
409
410 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
411 {
412 struct r600_bytecode_alu alu;
413 int i, r;
414 int gpr_front = ctx->shader->input[front].gpr;
415 int gpr_back = ctx->shader->input[back].gpr;
416
417 for (i = 0; i < 4; i++) {
418 memset(&alu, 0, sizeof(alu));
419 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
420 alu.is_op3 = 1;
421 alu.dst.write = 1;
422 alu.dst.sel = gpr_front;
423 alu.src[0].sel = ctx->face_gpr;
424 alu.src[1].sel = gpr_front;
425 alu.src[2].sel = gpr_back;
426
427 alu.dst.chan = i;
428 alu.src[1].chan = i;
429 alu.src[2].chan = i;
430 alu.last = (i==3);
431
432 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
433 return r;
434 }
435
436 return 0;
437 }
438
439 static int tgsi_declaration(struct r600_shader_ctx *ctx)
440 {
441 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
442 unsigned i;
443 int r;
444
445 switch (d->Declaration.File) {
446 case TGSI_FILE_INPUT:
447 i = ctx->shader->ninput++;
448 ctx->shader->input[i].name = d->Semantic.Name;
449 ctx->shader->input[i].sid = d->Semantic.Index;
450 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
451 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
452 ctx->shader->input[i].centroid = d->Declaration.Centroid;
453 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
454 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
455 if (ctx->shader->input[i].name == TGSI_SEMANTIC_FACE)
456 ctx->face_gpr = ctx->shader->input[i].gpr;
457 else if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR)
458 ctx->colors_used++;
459 if (ctx->bc->chip_class >= EVERGREEN) {
460 r = evergreen_interp_input(ctx, i);
461 if (r)
462 return r;
463 }
464 }
465 break;
466 case TGSI_FILE_OUTPUT:
467 i = ctx->shader->noutput++;
468 ctx->shader->output[i].name = d->Semantic.Name;
469 ctx->shader->output[i].sid = d->Semantic.Index;
470 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
471 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
472 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
473 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
474 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
475 switch (d->Semantic.Name) {
476 case TGSI_SEMANTIC_CLIPDIST:
477 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
478 break;
479 case TGSI_SEMANTIC_PSIZE:
480 ctx->shader->vs_out_misc_write = 1;
481 break;
482 }
483 }
484 break;
485 case TGSI_FILE_CONSTANT:
486 case TGSI_FILE_TEMPORARY:
487 case TGSI_FILE_SAMPLER:
488 case TGSI_FILE_ADDRESS:
489 break;
490
491 case TGSI_FILE_SYSTEM_VALUE:
492 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
493 struct r600_bytecode_alu alu;
494 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
495
496 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
497 alu.src[0].sel = 0;
498 alu.src[0].chan = 3;
499
500 alu.dst.sel = 0;
501 alu.dst.chan = 3;
502 alu.dst.write = 1;
503 alu.last = 1;
504
505 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
506 return r;
507 break;
508 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
509 break;
510 default:
511 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
512 return -EINVAL;
513 }
514 return 0;
515 }
516
517 static int r600_get_temp(struct r600_shader_ctx *ctx)
518 {
519 return ctx->temp_reg + ctx->max_driver_temp_used++;
520 }
521
522 /*
523 * for evergreen we need to scan the shader to find the number of GPRs we need to
524 * reserve for interpolation.
525 *
526 * we need to know if we are going to emit
527 * any centroid inputs
528 * if perspective and linear are required
529 */
530 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
531 {
532 int i;
533 int num_baryc;
534
535 ctx->input_linear = FALSE;
536 ctx->input_perspective = FALSE;
537 ctx->input_centroid = FALSE;
538 ctx->num_interp_gpr = 1;
539
540 /* any centroid inputs */
541 for (i = 0; i < ctx->info.num_inputs; i++) {
542 /* skip position/face */
543 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
544 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
545 continue;
546 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
547 ctx->input_linear = TRUE;
548 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
549 ctx->input_perspective = TRUE;
550 if (ctx->info.input_centroid[i])
551 ctx->input_centroid = TRUE;
552 }
553
554 num_baryc = 0;
555 /* ignoring sample for now */
556 if (ctx->input_perspective)
557 num_baryc++;
558 if (ctx->input_linear)
559 num_baryc++;
560 if (ctx->input_centroid)
561 num_baryc *= 2;
562
563 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
564
565 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
566 return ctx->num_interp_gpr;
567 }
568
569 static void tgsi_src(struct r600_shader_ctx *ctx,
570 const struct tgsi_full_src_register *tgsi_src,
571 struct r600_shader_src *r600_src)
572 {
573 memset(r600_src, 0, sizeof(*r600_src));
574 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
575 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
576 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
577 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
578 r600_src->neg = tgsi_src->Register.Negate;
579 r600_src->abs = tgsi_src->Register.Absolute;
580
581 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
582 int index;
583 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
584 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
585 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
586
587 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
588 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
589 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
590 return;
591 }
592 index = tgsi_src->Register.Index;
593 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
594 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
595 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
596 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
597 r600_src->swizzle[0] = 3;
598 r600_src->swizzle[1] = 3;
599 r600_src->swizzle[2] = 3;
600 r600_src->swizzle[3] = 3;
601 r600_src->sel = 0;
602 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
603 r600_src->swizzle[0] = 0;
604 r600_src->swizzle[1] = 0;
605 r600_src->swizzle[2] = 0;
606 r600_src->swizzle[3] = 0;
607 r600_src->sel = 0;
608 }
609 } else {
610 if (tgsi_src->Register.Indirect)
611 r600_src->rel = V_SQ_REL_RELATIVE;
612 r600_src->sel = tgsi_src->Register.Index;
613 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
614 }
615 }
616
617 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg)
618 {
619 struct r600_bytecode_vtx vtx;
620 unsigned int ar_reg;
621 int r;
622
623 if (offset) {
624 struct r600_bytecode_alu alu;
625
626 memset(&alu, 0, sizeof(alu));
627
628 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
629 alu.src[0].sel = ctx->bc->ar_reg;
630
631 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
632 alu.src[1].value = offset;
633
634 alu.dst.sel = dst_reg;
635 alu.dst.write = 1;
636 alu.last = 1;
637
638 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
639 return r;
640
641 ar_reg = dst_reg;
642 } else {
643 ar_reg = ctx->bc->ar_reg;
644 }
645
646 memset(&vtx, 0, sizeof(vtx));
647 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
648 vtx.src_gpr = ar_reg;
649 vtx.mega_fetch_count = 16;
650 vtx.dst_gpr = dst_reg;
651 vtx.dst_sel_x = 0; /* SEL_X */
652 vtx.dst_sel_y = 1; /* SEL_Y */
653 vtx.dst_sel_z = 2; /* SEL_Z */
654 vtx.dst_sel_w = 3; /* SEL_W */
655 vtx.data_format = FMT_32_32_32_32_FLOAT;
656 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
657 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
658 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
659 vtx.endian = r600_endian_swap(32);
660
661 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
662 return r;
663
664 return 0;
665 }
666
667 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
668 {
669 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
670 struct r600_bytecode_alu alu;
671 int i, j, k, nconst, r;
672
673 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
674 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
675 nconst++;
676 }
677 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
678 }
679 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
680 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
681 continue;
682 }
683
684 if (ctx->src[i].rel) {
685 int treg = r600_get_temp(ctx);
686 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].sel - 512, treg)))
687 return r;
688
689 ctx->src[i].sel = treg;
690 ctx->src[i].rel = 0;
691 j--;
692 } else if (j > 0) {
693 int treg = r600_get_temp(ctx);
694 for (k = 0; k < 4; k++) {
695 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
696 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
697 alu.src[0].sel = ctx->src[i].sel;
698 alu.src[0].chan = k;
699 alu.src[0].rel = ctx->src[i].rel;
700 alu.dst.sel = treg;
701 alu.dst.chan = k;
702 alu.dst.write = 1;
703 if (k == 3)
704 alu.last = 1;
705 r = r600_bytecode_add_alu(ctx->bc, &alu);
706 if (r)
707 return r;
708 }
709 ctx->src[i].sel = treg;
710 ctx->src[i].rel =0;
711 j--;
712 }
713 }
714 return 0;
715 }
716
717 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
718 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
719 {
720 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
721 struct r600_bytecode_alu alu;
722 int i, j, k, nliteral, r;
723
724 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
725 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
726 nliteral++;
727 }
728 }
729 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
730 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
731 int treg = r600_get_temp(ctx);
732 for (k = 0; k < 4; k++) {
733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
734 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
735 alu.src[0].sel = ctx->src[i].sel;
736 alu.src[0].chan = k;
737 alu.src[0].value = ctx->src[i].value[k];
738 alu.dst.sel = treg;
739 alu.dst.chan = k;
740 alu.dst.write = 1;
741 if (k == 3)
742 alu.last = 1;
743 r = r600_bytecode_add_alu(ctx->bc, &alu);
744 if (r)
745 return r;
746 }
747 ctx->src[i].sel = treg;
748 j--;
749 }
750 }
751 return 0;
752 }
753
754 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
755 {
756 int i, r, count = ctx->shader->ninput;
757
758 /* additional inputs will be allocated right after the existing inputs,
759 * we won't need them after the color selection, so we don't need to
760 * reserve these gprs for the rest of the shader code and to adjust
761 * output offsets etc. */
762 int gpr = ctx->file_offset[TGSI_FILE_INPUT] +
763 ctx->info.file_max[TGSI_FILE_INPUT] + 1;
764
765 if (ctx->face_gpr == -1) {
766 i = ctx->shader->ninput++;
767 ctx->shader->input[i].name = TGSI_SEMANTIC_FACE;
768 ctx->shader->input[i].spi_sid = 0;
769 ctx->shader->input[i].gpr = gpr++;
770 ctx->face_gpr = ctx->shader->input[i].gpr;
771 }
772
773 for (i = 0; i < count; i++) {
774 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
775 int ni = ctx->shader->ninput++;
776 memcpy(&ctx->shader->input[ni],&ctx->shader->input[i], sizeof(struct r600_shader_io));
777 ctx->shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
778 ctx->shader->input[ni].spi_sid = r600_spi_sid(&ctx->shader->input[ni]);
779 ctx->shader->input[ni].gpr = gpr++;
780
781 if (ctx->bc->chip_class >= EVERGREEN) {
782 r = evergreen_interp_input(ctx, ni);
783 if (r)
784 return r;
785 }
786
787 r = select_twoside_color(ctx, i, ni);
788 if (r)
789 return r;
790 }
791 }
792 return 0;
793 }
794
795 static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pipe_shader *pipeshader)
796 {
797 struct r600_shader *shader = &pipeshader->shader;
798 struct tgsi_token *tokens = pipeshader->tokens;
799 struct pipe_stream_output_info so = pipeshader->so;
800 struct tgsi_full_immediate *immediate;
801 struct tgsi_full_property *property;
802 struct r600_shader_ctx ctx;
803 struct r600_bytecode_output output[32];
804 unsigned output_done, noutput;
805 unsigned opcode;
806 int i, j, r = 0, pos0;
807
808 ctx.bc = &shader->bc;
809 ctx.shader = shader;
810 r600_bytecode_init(ctx.bc, rctx->chip_class);
811 ctx.tokens = tokens;
812 tgsi_scan_shader(tokens, &ctx.info);
813 tgsi_parse_init(&ctx.parse, tokens);
814 ctx.type = ctx.parse.FullHeader.Processor.Processor;
815 shader->processor_type = ctx.type;
816 ctx.bc->type = shader->processor_type;
817
818 ctx.face_gpr = -1;
819 ctx.colors_used = 0;
820
821 shader->two_side = (ctx.type == TGSI_PROCESSOR_FRAGMENT) && rctx->two_side;
822
823 shader->clamp_color = (((ctx.type == TGSI_PROCESSOR_FRAGMENT) && rctx->clamp_fragment_color) ||
824 ((ctx.type == TGSI_PROCESSOR_VERTEX) && rctx->clamp_vertex_color));
825
826 shader->nr_cbufs = rctx->nr_cbufs;
827
828 /* register allocations */
829 /* Values [0,127] correspond to GPR[0..127].
830 * Values [128,159] correspond to constant buffer bank 0
831 * Values [160,191] correspond to constant buffer bank 1
832 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
833 * Values [256,287] correspond to constant buffer bank 2 (EG)
834 * Values [288,319] correspond to constant buffer bank 3 (EG)
835 * Other special values are shown in the list below.
836 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
837 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
838 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
839 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
840 * 248 SQ_ALU_SRC_0: special constant 0.0.
841 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
842 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
843 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
844 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
845 * 253 SQ_ALU_SRC_LITERAL: literal constant.
846 * 254 SQ_ALU_SRC_PV: previous vector result.
847 * 255 SQ_ALU_SRC_PS: previous scalar result.
848 */
849 for (i = 0; i < TGSI_FILE_COUNT; i++) {
850 ctx.file_offset[i] = 0;
851 }
852 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
853 ctx.file_offset[TGSI_FILE_INPUT] = 1;
854 if (ctx.bc->chip_class >= EVERGREEN) {
855 r600_bytecode_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
856 } else {
857 r600_bytecode_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
858 }
859 }
860 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
861 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
862 }
863 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
864 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
865 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
866 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
867
868 /* Outside the GPR range. This will be translated to one of the
869 * kcache banks later. */
870 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
871
872 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
873 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
874 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
875 ctx.temp_reg = ctx.bc->ar_reg + 1;
876
877 ctx.nliterals = 0;
878 ctx.literals = NULL;
879 shader->fs_write_all = FALSE;
880 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
881 tgsi_parse_token(&ctx.parse);
882 switch (ctx.parse.FullToken.Token.Type) {
883 case TGSI_TOKEN_TYPE_IMMEDIATE:
884 immediate = &ctx.parse.FullToken.FullImmediate;
885 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
886 if(ctx.literals == NULL) {
887 r = -ENOMEM;
888 goto out_err;
889 }
890 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
891 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
892 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
893 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
894 ctx.nliterals++;
895 break;
896 case TGSI_TOKEN_TYPE_DECLARATION:
897 r = tgsi_declaration(&ctx);
898 if (r)
899 goto out_err;
900 break;
901 case TGSI_TOKEN_TYPE_INSTRUCTION:
902 break;
903 case TGSI_TOKEN_TYPE_PROPERTY:
904 property = &ctx.parse.FullToken.FullProperty;
905 switch (property->Property.PropertyName) {
906 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
907 if (property->u[0].Data == 1)
908 shader->fs_write_all = TRUE;
909 break;
910 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
911 if (property->u[0].Data == 1)
912 shader->vs_prohibit_ucps = TRUE;
913 break;
914 }
915 break;
916 default:
917 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
918 r = -EINVAL;
919 goto out_err;
920 }
921 }
922
923 if (shader->two_side && ctx.colors_used) {
924 if ((r = process_twoside_color_inputs(&ctx)))
925 return r;
926 }
927
928 tgsi_parse_init(&ctx.parse, tokens);
929 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
930 tgsi_parse_token(&ctx.parse);
931 switch (ctx.parse.FullToken.Token.Type) {
932 case TGSI_TOKEN_TYPE_INSTRUCTION:
933 r = tgsi_is_supported(&ctx);
934 if (r)
935 goto out_err;
936 ctx.max_driver_temp_used = 0;
937 /* reserve first tmp for everyone */
938 r600_get_temp(&ctx);
939
940 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
941 if ((r = tgsi_split_constant(&ctx)))
942 goto out_err;
943 if ((r = tgsi_split_literal_constant(&ctx)))
944 goto out_err;
945 if (ctx.bc->chip_class == CAYMAN)
946 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
947 else if (ctx.bc->chip_class >= EVERGREEN)
948 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
949 else
950 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
951 r = ctx.inst_info->process(&ctx);
952 if (r)
953 goto out_err;
954 break;
955 default:
956 break;
957 }
958 }
959
960 noutput = shader->noutput;
961
962 /* clamp color outputs */
963 if (shader->clamp_color) {
964 for (i = 0; i < noutput; i++) {
965 if (shader->output[i].name == TGSI_SEMANTIC_COLOR ||
966 shader->output[i].name == TGSI_SEMANTIC_BCOLOR) {
967
968 int j;
969 for (j = 0; j < 4; j++) {
970 struct r600_bytecode_alu alu;
971 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
972
973 /* MOV_SAT R, R */
974 alu.inst = BC_INST(ctx.bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
975 alu.dst.sel = shader->output[i].gpr;
976 alu.dst.chan = j;
977 alu.dst.write = 1;
978 alu.dst.clamp = 1;
979 alu.src[0].sel = alu.dst.sel;
980 alu.src[0].chan = j;
981
982 if (j == 3) {
983 alu.last = 1;
984 }
985 r = r600_bytecode_add_alu(ctx.bc, &alu);
986 if (r)
987 return r;
988 }
989 }
990 }
991 }
992
993 /* Add stream outputs. */
994 if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs) {
995 for (i = 0; i < so.num_outputs; i++) {
996 struct r600_bytecode_output output;
997
998 if (so.output[i].output_buffer >= 4) {
999 R600_ERR("exceeded the max number of stream output buffers, got: %d\n",
1000 so.output[i].output_buffer);
1001 r = -EINVAL;
1002 goto out_err;
1003 }
1004 if (so.output[i].start_component) {
1005 R600_ERR("stream_output - start_component cannot be non-zero\n");
1006 r = -EINVAL;
1007 goto out_err;
1008 }
1009
1010 memset(&output, 0, sizeof(struct r600_bytecode_output));
1011 output.gpr = shader->output[so.output[i].register_index].gpr;
1012 output.elem_size = 0;
1013 output.array_base = so.output[i].dst_offset;
1014 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1015 output.burst_count = 1;
1016 output.barrier = 1;
1017 output.array_size = 0;
1018 output.comp_mask = (1 << so.output[i].num_components) - 1;
1019 if (ctx.bc->chip_class >= EVERGREEN) {
1020 switch (so.output[i].output_buffer) {
1021 case 0:
1022 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0;
1023 break;
1024 case 1:
1025 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1;
1026 break;
1027 case 2:
1028 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2;
1029 break;
1030 case 3:
1031 output.inst = EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3;
1032 break;
1033 }
1034 } else {
1035 switch (so.output[i].output_buffer) {
1036 case 0:
1037 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0;
1038 break;
1039 case 1:
1040 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1;
1041 break;
1042 case 2:
1043 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2;
1044 break;
1045 case 3:
1046 output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3;
1047 break;
1048 }
1049 }
1050 r = r600_bytecode_add_output(ctx.bc, &output);
1051 if (r)
1052 goto out_err;
1053 }
1054 }
1055
1056 /* export output */
1057 j = 0;
1058
1059 for (i = 0, pos0 = 0; i < noutput; i++) {
1060 memset(&output[i+j], 0, sizeof(struct r600_bytecode_output));
1061 output[i + j].gpr = shader->output[i].gpr;
1062 output[i + j].elem_size = 3;
1063 output[i + j].swizzle_x = 0;
1064 output[i + j].swizzle_y = 1;
1065 output[i + j].swizzle_z = 2;
1066 output[i + j].swizzle_w = 3;
1067 output[i + j].burst_count = 1;
1068 output[i + j].barrier = 1;
1069 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1070 output[i + j].array_base = i+j - pos0;
1071 output[i + j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1072 switch (ctx.type) {
1073 case TGSI_PROCESSOR_VERTEX:
1074 switch (shader->output[i].name) {
1075 case TGSI_SEMANTIC_POSITION:
1076 output[i + j].array_base = 60;
1077 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1078 /* position doesn't count in array_base */
1079 pos0++;
1080 break;
1081
1082 case TGSI_SEMANTIC_PSIZE:
1083 output[i + j].array_base = 61;
1084 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1085 /* position doesn't count in array_base */
1086 pos0++;
1087 break;
1088
1089 case TGSI_SEMANTIC_CLIPDIST:
1090 /* array base for enabled OUT_MISC_VEC & CCDIST[0|1]_VEC
1091 * vectors is allocated sequentially, starting from 61 */
1092 output[i + j].array_base = 61 + shader->output[i].sid
1093 /* +1 if OUT_MISC_VEC is enabled */
1094 + shader->vs_out_misc_write
1095 /* -1 if OUT_CCDIST0_VEC is disabled */
1096 - (((shader->clip_dist_write & 0xF) == 0)? 1 : 0);
1097 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1098 j++;
1099 pos0++;
1100 /* duplicate it as PARAM to pass to the pixel shader */
1101 memcpy(&output[i+j], &output[i+j-1], sizeof(struct r600_bytecode_output));
1102 output[i + j].array_base = i+j-pos0;
1103 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1104 break;
1105 }
1106 break;
1107 case TGSI_PROCESSOR_FRAGMENT:
1108 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
1109 output[i + j].array_base = shader->output[i].sid;
1110 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1111 if (shader->fs_write_all && (rctx->chip_class >= EVERGREEN)) {
1112 for (j = 1; j < shader->nr_cbufs; j++) {
1113 memset(&output[i + j], 0, sizeof(struct r600_bytecode_output));
1114 output[i + j].gpr = shader->output[i].gpr;
1115 output[i + j].elem_size = 3;
1116 output[i + j].swizzle_x = 0;
1117 output[i + j].swizzle_y = 1;
1118 output[i + j].swizzle_z = 2;
1119 output[i + j].swizzle_w = 3;
1120 output[i + j].burst_count = 1;
1121 output[i + j].barrier = 1;
1122 output[i + j].array_base = shader->output[i].sid + j;
1123 output[i + j].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1124 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1125 }
1126 j = shader->nr_cbufs-1;
1127 }
1128 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
1129 output[i + j].array_base = 61;
1130 output[i + j].swizzle_x = 2;
1131 output[i + j].swizzle_y = 7;
1132 output[i + j].swizzle_z = output[i + j].swizzle_w = 7;
1133 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1134 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
1135 output[i + j].array_base = 61;
1136 output[i + j].swizzle_x = 7;
1137 output[i + j].swizzle_y = 1;
1138 output[i + j].swizzle_z = output[i + j].swizzle_w = 7;
1139 output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1140 } else {
1141 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
1142 r = -EINVAL;
1143 goto out_err;
1144 }
1145 break;
1146 default:
1147 R600_ERR("unsupported processor type %d\n", ctx.type);
1148 r = -EINVAL;
1149 goto out_err;
1150 }
1151 }
1152 noutput += j;
1153 /* add fake param output for vertex shader if no param is exported */
1154 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1155 for (i = 0, pos0 = 0; i < noutput; i++) {
1156 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
1157 pos0 = 1;
1158 break;
1159 }
1160 }
1161 if (!pos0) {
1162 memset(&output[i], 0, sizeof(struct r600_bytecode_output));
1163 output[i].gpr = 0;
1164 output[i].elem_size = 3;
1165 output[i].swizzle_x = 7;
1166 output[i].swizzle_y = 7;
1167 output[i].swizzle_z = 7;
1168 output[i].swizzle_w = 7;
1169 output[i].burst_count = 1;
1170 output[i].barrier = 1;
1171 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1172 output[i].array_base = 0;
1173 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1174 noutput++;
1175 }
1176 }
1177 /* add fake pixel export */
1178 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
1179 memset(&output[0], 0, sizeof(struct r600_bytecode_output));
1180 output[0].gpr = 0;
1181 output[0].elem_size = 3;
1182 output[0].swizzle_x = 7;
1183 output[0].swizzle_y = 7;
1184 output[0].swizzle_z = 7;
1185 output[0].swizzle_w = 7;
1186 output[0].burst_count = 1;
1187 output[0].barrier = 1;
1188 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
1189 output[0].array_base = 0;
1190 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
1191 noutput++;
1192 }
1193 /* set export done on last export of each type */
1194 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
1195 if (ctx.bc->chip_class < CAYMAN) {
1196 if (i == (noutput - 1)) {
1197 output[i].end_of_program = 1;
1198 }
1199 }
1200 if (!(output_done & (1 << output[i].type))) {
1201 output_done |= (1 << output[i].type);
1202 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
1203 }
1204 }
1205 /* add output to bytecode */
1206 for (i = 0; i < noutput; i++) {
1207 r = r600_bytecode_add_output(ctx.bc, &output[i]);
1208 if (r)
1209 goto out_err;
1210 }
1211 /* add program end */
1212 if (ctx.bc->chip_class == CAYMAN)
1213 cm_bytecode_add_cf_end(ctx.bc);
1214
1215 free(ctx.literals);
1216 tgsi_parse_free(&ctx.parse);
1217 return 0;
1218 out_err:
1219 free(ctx.literals);
1220 tgsi_parse_free(&ctx.parse);
1221 return r;
1222 }
1223
1224 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
1225 {
1226 R600_ERR("%s tgsi opcode unsupported\n",
1227 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
1228 return -EINVAL;
1229 }
1230
1231 static int tgsi_end(struct r600_shader_ctx *ctx)
1232 {
1233 return 0;
1234 }
1235
1236 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
1237 const struct r600_shader_src *shader_src,
1238 unsigned chan)
1239 {
1240 bc_src->sel = shader_src->sel;
1241 bc_src->chan = shader_src->swizzle[chan];
1242 bc_src->neg = shader_src->neg;
1243 bc_src->abs = shader_src->abs;
1244 bc_src->rel = shader_src->rel;
1245 bc_src->value = shader_src->value[bc_src->chan];
1246 }
1247
1248 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
1249 {
1250 bc_src->abs = 1;
1251 bc_src->neg = 0;
1252 }
1253
1254 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
1255 {
1256 bc_src->neg = !bc_src->neg;
1257 }
1258
1259 static void tgsi_dst(struct r600_shader_ctx *ctx,
1260 const struct tgsi_full_dst_register *tgsi_dst,
1261 unsigned swizzle,
1262 struct r600_bytecode_alu_dst *r600_dst)
1263 {
1264 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1265
1266 r600_dst->sel = tgsi_dst->Register.Index;
1267 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
1268 r600_dst->chan = swizzle;
1269 r600_dst->write = 1;
1270 if (tgsi_dst->Register.Indirect)
1271 r600_dst->rel = V_SQ_REL_RELATIVE;
1272 if (inst->Instruction.Saturate) {
1273 r600_dst->clamp = 1;
1274 }
1275 }
1276
1277 static int tgsi_last_instruction(unsigned writemask)
1278 {
1279 int i, lasti = 0;
1280
1281 for (i = 0; i < 4; i++) {
1282 if (writemask & (1 << i)) {
1283 lasti = i;
1284 }
1285 }
1286 return lasti;
1287 }
1288
1289 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
1290 {
1291 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1292 struct r600_bytecode_alu alu;
1293 int i, j, r;
1294 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1295
1296 for (i = 0; i < lasti + 1; i++) {
1297 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1298 continue;
1299
1300 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1301 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1302
1303 alu.inst = ctx->inst_info->r600_opcode;
1304 if (!swap) {
1305 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1306 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
1307 }
1308 } else {
1309 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
1310 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1311 }
1312 /* handle some special cases */
1313 switch (ctx->inst_info->tgsi_opcode) {
1314 case TGSI_OPCODE_SUB:
1315 r600_bytecode_src_toggle_neg(&alu.src[1]);
1316 break;
1317 case TGSI_OPCODE_ABS:
1318 r600_bytecode_src_set_abs(&alu.src[0]);
1319 break;
1320 default:
1321 break;
1322 }
1323 if (i == lasti || trans_only) {
1324 alu.last = 1;
1325 }
1326 r = r600_bytecode_add_alu(ctx->bc, &alu);
1327 if (r)
1328 return r;
1329 }
1330 return 0;
1331 }
1332
1333 static int tgsi_op2(struct r600_shader_ctx *ctx)
1334 {
1335 return tgsi_op2_s(ctx, 0, 0);
1336 }
1337
1338 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1339 {
1340 return tgsi_op2_s(ctx, 1, 0);
1341 }
1342
1343 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
1344 {
1345 return tgsi_op2_s(ctx, 0, 1);
1346 }
1347
1348 static int tgsi_ineg(struct r600_shader_ctx *ctx)
1349 {
1350 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1351 struct r600_bytecode_alu alu;
1352 int i, r;
1353 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1354
1355 for (i = 0; i < lasti + 1; i++) {
1356
1357 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1358 continue;
1359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1360 alu.inst = ctx->inst_info->r600_opcode;
1361
1362 alu.src[0].sel = V_SQ_ALU_SRC_0;
1363
1364 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1365
1366 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1367
1368 if (i == lasti) {
1369 alu.last = 1;
1370 }
1371 r = r600_bytecode_add_alu(ctx->bc, &alu);
1372 if (r)
1373 return r;
1374 }
1375 return 0;
1376
1377 }
1378
1379 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
1380 {
1381 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1382 int i, j, r;
1383 struct r600_bytecode_alu alu;
1384 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1385
1386 for (i = 0 ; i < last_slot; i++) {
1387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1388 alu.inst = ctx->inst_info->r600_opcode;
1389 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1390 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
1391 }
1392 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1393 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1394
1395 if (i == last_slot - 1)
1396 alu.last = 1;
1397 r = r600_bytecode_add_alu(ctx->bc, &alu);
1398 if (r)
1399 return r;
1400 }
1401 return 0;
1402 }
1403
1404 /*
1405 * r600 - trunc to -PI..PI range
1406 * r700 - normalize by dividing by 2PI
1407 * see fdo bug 27901
1408 */
1409 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1410 {
1411 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1412 static float double_pi = 3.1415926535 * 2;
1413 static float neg_pi = -3.1415926535;
1414
1415 int r;
1416 struct r600_bytecode_alu alu;
1417
1418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1419 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1420 alu.is_op3 = 1;
1421
1422 alu.dst.chan = 0;
1423 alu.dst.sel = ctx->temp_reg;
1424 alu.dst.write = 1;
1425
1426 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1427
1428 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1429 alu.src[1].chan = 0;
1430 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1431 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1432 alu.src[2].chan = 0;
1433 alu.last = 1;
1434 r = r600_bytecode_add_alu(ctx->bc, &alu);
1435 if (r)
1436 return r;
1437
1438 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1439 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1440
1441 alu.dst.chan = 0;
1442 alu.dst.sel = ctx->temp_reg;
1443 alu.dst.write = 1;
1444
1445 alu.src[0].sel = ctx->temp_reg;
1446 alu.src[0].chan = 0;
1447 alu.last = 1;
1448 r = r600_bytecode_add_alu(ctx->bc, &alu);
1449 if (r)
1450 return r;
1451
1452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1453 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1454 alu.is_op3 = 1;
1455
1456 alu.dst.chan = 0;
1457 alu.dst.sel = ctx->temp_reg;
1458 alu.dst.write = 1;
1459
1460 alu.src[0].sel = ctx->temp_reg;
1461 alu.src[0].chan = 0;
1462
1463 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1464 alu.src[1].chan = 0;
1465 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1466 alu.src[2].chan = 0;
1467
1468 if (ctx->bc->chip_class == R600) {
1469 alu.src[1].value = *(uint32_t *)&double_pi;
1470 alu.src[2].value = *(uint32_t *)&neg_pi;
1471 } else {
1472 alu.src[1].sel = V_SQ_ALU_SRC_1;
1473 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1474 alu.src[2].neg = 1;
1475 }
1476
1477 alu.last = 1;
1478 r = r600_bytecode_add_alu(ctx->bc, &alu);
1479 if (r)
1480 return r;
1481 return 0;
1482 }
1483
1484 static int cayman_trig(struct r600_shader_ctx *ctx)
1485 {
1486 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1487 struct r600_bytecode_alu alu;
1488 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1489 int i, r;
1490
1491 r = tgsi_setup_trig(ctx);
1492 if (r)
1493 return r;
1494
1495
1496 for (i = 0; i < last_slot; i++) {
1497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1498 alu.inst = ctx->inst_info->r600_opcode;
1499 alu.dst.chan = i;
1500
1501 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1502 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1503
1504 alu.src[0].sel = ctx->temp_reg;
1505 alu.src[0].chan = 0;
1506 if (i == last_slot - 1)
1507 alu.last = 1;
1508 r = r600_bytecode_add_alu(ctx->bc, &alu);
1509 if (r)
1510 return r;
1511 }
1512 return 0;
1513 }
1514
1515 static int tgsi_trig(struct r600_shader_ctx *ctx)
1516 {
1517 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1518 struct r600_bytecode_alu alu;
1519 int i, r;
1520 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1521
1522 r = tgsi_setup_trig(ctx);
1523 if (r)
1524 return r;
1525
1526 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1527 alu.inst = ctx->inst_info->r600_opcode;
1528 alu.dst.chan = 0;
1529 alu.dst.sel = ctx->temp_reg;
1530 alu.dst.write = 1;
1531
1532 alu.src[0].sel = ctx->temp_reg;
1533 alu.src[0].chan = 0;
1534 alu.last = 1;
1535 r = r600_bytecode_add_alu(ctx->bc, &alu);
1536 if (r)
1537 return r;
1538
1539 /* replicate result */
1540 for (i = 0; i < lasti + 1; i++) {
1541 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1542 continue;
1543
1544 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1545 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1546
1547 alu.src[0].sel = ctx->temp_reg;
1548 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1549 if (i == lasti)
1550 alu.last = 1;
1551 r = r600_bytecode_add_alu(ctx->bc, &alu);
1552 if (r)
1553 return r;
1554 }
1555 return 0;
1556 }
1557
1558 static int tgsi_scs(struct r600_shader_ctx *ctx)
1559 {
1560 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1561 struct r600_bytecode_alu alu;
1562 int i, r;
1563
1564 /* We'll only need the trig stuff if we are going to write to the
1565 * X or Y components of the destination vector.
1566 */
1567 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1568 r = tgsi_setup_trig(ctx);
1569 if (r)
1570 return r;
1571 }
1572
1573 /* dst.x = COS */
1574 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1575 if (ctx->bc->chip_class == CAYMAN) {
1576 for (i = 0 ; i < 3; i++) {
1577 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1578 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1579 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1580
1581 if (i == 0)
1582 alu.dst.write = 1;
1583 else
1584 alu.dst.write = 0;
1585 alu.src[0].sel = ctx->temp_reg;
1586 alu.src[0].chan = 0;
1587 if (i == 2)
1588 alu.last = 1;
1589 r = r600_bytecode_add_alu(ctx->bc, &alu);
1590 if (r)
1591 return r;
1592 }
1593 } else {
1594 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1595 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1596 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1597
1598 alu.src[0].sel = ctx->temp_reg;
1599 alu.src[0].chan = 0;
1600 alu.last = 1;
1601 r = r600_bytecode_add_alu(ctx->bc, &alu);
1602 if (r)
1603 return r;
1604 }
1605 }
1606
1607 /* dst.y = SIN */
1608 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1609 if (ctx->bc->chip_class == CAYMAN) {
1610 for (i = 0 ; i < 3; i++) {
1611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1612 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1613 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1614 if (i == 1)
1615 alu.dst.write = 1;
1616 else
1617 alu.dst.write = 0;
1618 alu.src[0].sel = ctx->temp_reg;
1619 alu.src[0].chan = 0;
1620 if (i == 2)
1621 alu.last = 1;
1622 r = r600_bytecode_add_alu(ctx->bc, &alu);
1623 if (r)
1624 return r;
1625 }
1626 } else {
1627 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1628 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1629 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1630
1631 alu.src[0].sel = ctx->temp_reg;
1632 alu.src[0].chan = 0;
1633 alu.last = 1;
1634 r = r600_bytecode_add_alu(ctx->bc, &alu);
1635 if (r)
1636 return r;
1637 }
1638 }
1639
1640 /* dst.z = 0.0; */
1641 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1642 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1643
1644 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1645
1646 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1647
1648 alu.src[0].sel = V_SQ_ALU_SRC_0;
1649 alu.src[0].chan = 0;
1650
1651 alu.last = 1;
1652
1653 r = r600_bytecode_add_alu(ctx->bc, &alu);
1654 if (r)
1655 return r;
1656 }
1657
1658 /* dst.w = 1.0; */
1659 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1660 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1661
1662 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1663
1664 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1665
1666 alu.src[0].sel = V_SQ_ALU_SRC_1;
1667 alu.src[0].chan = 0;
1668
1669 alu.last = 1;
1670
1671 r = r600_bytecode_add_alu(ctx->bc, &alu);
1672 if (r)
1673 return r;
1674 }
1675
1676 return 0;
1677 }
1678
1679 static int tgsi_kill(struct r600_shader_ctx *ctx)
1680 {
1681 struct r600_bytecode_alu alu;
1682 int i, r;
1683
1684 for (i = 0; i < 4; i++) {
1685 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1686 alu.inst = ctx->inst_info->r600_opcode;
1687
1688 alu.dst.chan = i;
1689
1690 alu.src[0].sel = V_SQ_ALU_SRC_0;
1691
1692 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1693 alu.src[1].sel = V_SQ_ALU_SRC_1;
1694 alu.src[1].neg = 1;
1695 } else {
1696 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
1697 }
1698 if (i == 3) {
1699 alu.last = 1;
1700 }
1701 r = r600_bytecode_add_alu(ctx->bc, &alu);
1702 if (r)
1703 return r;
1704 }
1705
1706 /* kill must be last in ALU */
1707 ctx->bc->force_add_cf = 1;
1708 ctx->shader->uses_kill = TRUE;
1709 return 0;
1710 }
1711
1712 static int tgsi_lit(struct r600_shader_ctx *ctx)
1713 {
1714 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1715 struct r600_bytecode_alu alu;
1716 int r;
1717
1718 /* tmp.x = max(src.y, 0.0) */
1719 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1720 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1721 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
1722 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1723 alu.src[1].chan = 1;
1724
1725 alu.dst.sel = ctx->temp_reg;
1726 alu.dst.chan = 0;
1727 alu.dst.write = 1;
1728
1729 alu.last = 1;
1730 r = r600_bytecode_add_alu(ctx->bc, &alu);
1731 if (r)
1732 return r;
1733
1734 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1735 {
1736 int chan;
1737 int sel;
1738 int i;
1739
1740 if (ctx->bc->chip_class == CAYMAN) {
1741 for (i = 0; i < 3; i++) {
1742 /* tmp.z = log(tmp.x) */
1743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1744 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1745 alu.src[0].sel = ctx->temp_reg;
1746 alu.src[0].chan = 0;
1747 alu.dst.sel = ctx->temp_reg;
1748 alu.dst.chan = i;
1749 if (i == 2) {
1750 alu.dst.write = 1;
1751 alu.last = 1;
1752 } else
1753 alu.dst.write = 0;
1754
1755 r = r600_bytecode_add_alu(ctx->bc, &alu);
1756 if (r)
1757 return r;
1758 }
1759 } else {
1760 /* tmp.z = log(tmp.x) */
1761 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1762 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1763 alu.src[0].sel = ctx->temp_reg;
1764 alu.src[0].chan = 0;
1765 alu.dst.sel = ctx->temp_reg;
1766 alu.dst.chan = 2;
1767 alu.dst.write = 1;
1768 alu.last = 1;
1769 r = r600_bytecode_add_alu(ctx->bc, &alu);
1770 if (r)
1771 return r;
1772 }
1773
1774 chan = alu.dst.chan;
1775 sel = alu.dst.sel;
1776
1777 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
1778 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1779 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1780 alu.src[0].sel = sel;
1781 alu.src[0].chan = chan;
1782 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
1783 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
1784 alu.dst.sel = ctx->temp_reg;
1785 alu.dst.chan = 0;
1786 alu.dst.write = 1;
1787 alu.is_op3 = 1;
1788 alu.last = 1;
1789 r = r600_bytecode_add_alu(ctx->bc, &alu);
1790 if (r)
1791 return r;
1792
1793 if (ctx->bc->chip_class == CAYMAN) {
1794 for (i = 0; i < 3; i++) {
1795 /* dst.z = exp(tmp.x) */
1796 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1797 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1798 alu.src[0].sel = ctx->temp_reg;
1799 alu.src[0].chan = 0;
1800 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1801 if (i == 2) {
1802 alu.dst.write = 1;
1803 alu.last = 1;
1804 } else
1805 alu.dst.write = 0;
1806 r = r600_bytecode_add_alu(ctx->bc, &alu);
1807 if (r)
1808 return r;
1809 }
1810 } else {
1811 /* dst.z = exp(tmp.x) */
1812 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1813 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1814 alu.src[0].sel = ctx->temp_reg;
1815 alu.src[0].chan = 0;
1816 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1817 alu.last = 1;
1818 r = r600_bytecode_add_alu(ctx->bc, &alu);
1819 if (r)
1820 return r;
1821 }
1822 }
1823
1824 /* dst.x, <- 1.0 */
1825 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1826 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1827 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1828 alu.src[0].chan = 0;
1829 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1830 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1831 r = r600_bytecode_add_alu(ctx->bc, &alu);
1832 if (r)
1833 return r;
1834
1835 /* dst.y = max(src.x, 0.0) */
1836 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1837 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1838 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1839 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1840 alu.src[1].chan = 0;
1841 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1842 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1843 r = r600_bytecode_add_alu(ctx->bc, &alu);
1844 if (r)
1845 return r;
1846
1847 /* dst.w, <- 1.0 */
1848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1849 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1850 alu.src[0].sel = V_SQ_ALU_SRC_1;
1851 alu.src[0].chan = 0;
1852 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1853 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1854 alu.last = 1;
1855 r = r600_bytecode_add_alu(ctx->bc, &alu);
1856 if (r)
1857 return r;
1858
1859 return 0;
1860 }
1861
1862 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1863 {
1864 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1865 struct r600_bytecode_alu alu;
1866 int i, r;
1867
1868 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1869
1870 /* FIXME:
1871 * For state trackers other than OpenGL, we'll want to use
1872 * _RECIPSQRT_IEEE instead.
1873 */
1874 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1875
1876 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1877 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
1878 r600_bytecode_src_set_abs(&alu.src[i]);
1879 }
1880 alu.dst.sel = ctx->temp_reg;
1881 alu.dst.write = 1;
1882 alu.last = 1;
1883 r = r600_bytecode_add_alu(ctx->bc, &alu);
1884 if (r)
1885 return r;
1886 /* replicate result */
1887 return tgsi_helper_tempx_replicate(ctx);
1888 }
1889
1890 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1891 {
1892 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1893 struct r600_bytecode_alu alu;
1894 int i, r;
1895
1896 for (i = 0; i < 4; i++) {
1897 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1898 alu.src[0].sel = ctx->temp_reg;
1899 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1900 alu.dst.chan = i;
1901 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1902 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1903 if (i == 3)
1904 alu.last = 1;
1905 r = r600_bytecode_add_alu(ctx->bc, &alu);
1906 if (r)
1907 return r;
1908 }
1909 return 0;
1910 }
1911
1912 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1913 {
1914 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1915 struct r600_bytecode_alu alu;
1916 int i, r;
1917
1918 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1919 alu.inst = ctx->inst_info->r600_opcode;
1920 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1921 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
1922 }
1923 alu.dst.sel = ctx->temp_reg;
1924 alu.dst.write = 1;
1925 alu.last = 1;
1926 r = r600_bytecode_add_alu(ctx->bc, &alu);
1927 if (r)
1928 return r;
1929 /* replicate result */
1930 return tgsi_helper_tempx_replicate(ctx);
1931 }
1932
1933 static int cayman_pow(struct r600_shader_ctx *ctx)
1934 {
1935 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1936 int i, r;
1937 struct r600_bytecode_alu alu;
1938 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
1939
1940 for (i = 0; i < 3; i++) {
1941 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1942 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1943 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1944 alu.dst.sel = ctx->temp_reg;
1945 alu.dst.chan = i;
1946 alu.dst.write = 1;
1947 if (i == 2)
1948 alu.last = 1;
1949 r = r600_bytecode_add_alu(ctx->bc, &alu);
1950 if (r)
1951 return r;
1952 }
1953
1954 /* b * LOG2(a) */
1955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1956 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1957 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
1958 alu.src[1].sel = ctx->temp_reg;
1959 alu.dst.sel = ctx->temp_reg;
1960 alu.dst.write = 1;
1961 alu.last = 1;
1962 r = r600_bytecode_add_alu(ctx->bc, &alu);
1963 if (r)
1964 return r;
1965
1966 for (i = 0; i < last_slot; i++) {
1967 /* POW(a,b) = EXP2(b * LOG2(a))*/
1968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1969 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1970 alu.src[0].sel = ctx->temp_reg;
1971
1972 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1973 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1974 if (i == last_slot - 1)
1975 alu.last = 1;
1976 r = r600_bytecode_add_alu(ctx->bc, &alu);
1977 if (r)
1978 return r;
1979 }
1980 return 0;
1981 }
1982
1983 static int tgsi_pow(struct r600_shader_ctx *ctx)
1984 {
1985 struct r600_bytecode_alu alu;
1986 int r;
1987
1988 /* LOG2(a) */
1989 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1990 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1991 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
1992 alu.dst.sel = ctx->temp_reg;
1993 alu.dst.write = 1;
1994 alu.last = 1;
1995 r = r600_bytecode_add_alu(ctx->bc, &alu);
1996 if (r)
1997 return r;
1998 /* b * LOG2(a) */
1999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2000 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2001 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
2002 alu.src[1].sel = ctx->temp_reg;
2003 alu.dst.sel = ctx->temp_reg;
2004 alu.dst.write = 1;
2005 alu.last = 1;
2006 r = r600_bytecode_add_alu(ctx->bc, &alu);
2007 if (r)
2008 return r;
2009 /* POW(a,b) = EXP2(b * LOG2(a))*/
2010 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2011 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2012 alu.src[0].sel = ctx->temp_reg;
2013 alu.dst.sel = ctx->temp_reg;
2014 alu.dst.write = 1;
2015 alu.last = 1;
2016 r = r600_bytecode_add_alu(ctx->bc, &alu);
2017 if (r)
2018 return r;
2019 return tgsi_helper_tempx_replicate(ctx);
2020 }
2021
2022 static int tgsi_idiv(struct r600_shader_ctx *ctx)
2023 {
2024 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2025 struct r600_bytecode_alu alu;
2026 int i, r;
2027 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2028 int last_inst = tgsi_last_instruction(write_mask);
2029 int tmp0 = ctx->temp_reg;
2030 int tmp1 = r600_get_temp(ctx);
2031 int unsigned_op = (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_UDIV);
2032
2033 /* tmp0 = float(src0) */
2034 for (i = 0; i < 4; i++) {
2035 if (!(write_mask & (1<<i)))
2036 continue;
2037
2038 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2039
2040 if (unsigned_op)
2041 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
2042 else
2043 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
2044
2045 alu.dst.sel = tmp0;
2046 alu.dst.chan = i;
2047 alu.dst.write = 1;
2048
2049 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2050 alu.last = 1;
2051 r = r600_bytecode_add_alu(ctx->bc, &alu);
2052 if (r)
2053 return r;
2054 }
2055
2056 if (!unsigned_op) {
2057 /* tmp1 = tmp0>=0 ? 0.5 : -0.5 for int*/
2058 for (i = 0; i < 4; i++) {
2059 if (!(write_mask & (1<<i)))
2060 continue;
2061
2062 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2063 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2064 alu.is_op3 = 1;
2065
2066 alu.dst.sel = tmp1;
2067 alu.dst.chan = i;
2068 alu.dst.write = 1;
2069
2070 alu.src[0].sel = tmp0;
2071 alu.src[0].chan = i;
2072
2073 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
2074
2075 if (unsigned_op)
2076 alu.src[2].sel = V_SQ_ALU_SRC_0;
2077 else {
2078 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2079 alu.src[2].neg = 1;
2080 }
2081
2082 if (i == last_inst)
2083 alu.last = 1;
2084 r = r600_bytecode_add_alu(ctx->bc, &alu);
2085 if (r)
2086 return r;
2087 }
2088 }
2089
2090 /* tmp0 = tmp0 + tmp1 for int */
2091 /* tmp0 = tmp0 + 0.5 for uint */
2092 for (i = 0; i < 4; i++) {
2093 if (!(write_mask & (1<<i)))
2094 continue;
2095
2096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2097 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
2098
2099 alu.dst.sel = tmp0;
2100 alu.dst.chan = i;
2101 alu.dst.write = 1;
2102
2103 alu.src[0].sel = tmp0;
2104 alu.src[0].chan = i;
2105
2106 if (unsigned_op)
2107 alu.src[1].sel = V_SQ_ALU_SRC_0_5;
2108 else {
2109 alu.src[1].sel = tmp1;
2110 alu.src[1].chan = i;
2111 }
2112
2113 if (i == last_inst)
2114 alu.last = 1;
2115 r = r600_bytecode_add_alu(ctx->bc, &alu);
2116 if (r)
2117 return r;
2118 }
2119
2120 /* tmp1 = float(src1) */
2121 for (i = 0; i < 4; i++) {
2122 if (!(write_mask & (1<<i)))
2123 continue;
2124
2125 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2126
2127 if (unsigned_op)
2128 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
2129 else
2130 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
2131
2132 alu.dst.sel = tmp1;
2133 alu.dst.chan = i;
2134 alu.dst.write = 1;
2135
2136 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2137 alu.last = 1;
2138 r = r600_bytecode_add_alu(ctx->bc, &alu);
2139 if (r)
2140 return r;
2141 }
2142
2143 /* tmp1 = 1.0/src1 */
2144 for (i = 0; i < 4; i++) {
2145 if (!(write_mask & (1<<i)))
2146 continue;
2147
2148 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2149 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2150
2151 alu.dst.sel = tmp1;
2152 alu.dst.chan = i;
2153 alu.dst.write = 1;
2154
2155 alu.src[0].sel = tmp1;
2156 alu.src[0].chan = i;
2157
2158 alu.last = 1;
2159 r = r600_bytecode_add_alu(ctx->bc, &alu);
2160 if (r)
2161 return r;
2162 }
2163
2164 /* tmp1 = tmp0 * tmp1 */
2165 for (i = 0; i < 4; i++) {
2166 if (!(write_mask & (1<<i)))
2167 continue;
2168
2169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2170 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2171
2172 alu.dst.sel = tmp1;
2173 alu.dst.chan = i;
2174 alu.dst.write = 1;
2175
2176 alu.src[0].sel = ctx->temp_reg;
2177 alu.src[0].chan = i;
2178
2179 alu.src[1].sel = tmp1;
2180 alu.src[1].chan = i;
2181
2182 if (i == last_inst)
2183 alu.last = 1;
2184 r = r600_bytecode_add_alu(ctx->bc, &alu);
2185 if (r)
2186 return r;
2187 }
2188
2189 /* tmp1 = trunc(tmp1) for evergreen+ */
2190 if (ctx->bc->chip_class >= EVERGREEN) {
2191 for (i = 0; i < 4; i++) {
2192 if (!(write_mask & (1<<i)))
2193 continue;
2194
2195 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2196 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
2197
2198 alu.dst.sel = tmp1;
2199 alu.dst.chan = i;
2200 alu.dst.write = 1;
2201
2202 alu.src[0].sel = tmp1;
2203 alu.src[0].chan = i;
2204
2205 if (i == last_inst)
2206 alu.last = 1;
2207 r = r600_bytecode_add_alu(ctx->bc, &alu);
2208 if (r)
2209 return r;
2210 }
2211 }
2212
2213 /* dst = int(tmp1) */
2214 for (i = 0; i < 4; i++) {
2215 if (!(write_mask & (1<<i)))
2216 continue;
2217
2218 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2219
2220 if (unsigned_op)
2221 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
2222 else
2223 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT);
2224
2225 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2226
2227 alu.src[0].sel = tmp1;
2228 alu.src[0].chan = i;
2229
2230 if ((ctx->bc->chip_class < EVERGREEN || unsigned_op) || i == last_inst)
2231 alu.last = 1;
2232 r = r600_bytecode_add_alu(ctx->bc, &alu);
2233 if (r)
2234 return r;
2235 }
2236
2237 return 0;
2238 }
2239
2240 static int tgsi_f2i(struct r600_shader_ctx *ctx)
2241 {
2242 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2243 struct r600_bytecode_alu alu;
2244 int i, r;
2245 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2246 int last_inst = tgsi_last_instruction(write_mask);
2247
2248 for (i = 0; i < 4; i++) {
2249 if (!(write_mask & (1<<i)))
2250 continue;
2251
2252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2253 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
2254
2255 alu.dst.sel = ctx->temp_reg;
2256 alu.dst.chan = i;
2257 alu.dst.write = 1;
2258
2259 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2260 if (i == last_inst)
2261 alu.last = 1;
2262 r = r600_bytecode_add_alu(ctx->bc, &alu);
2263 if (r)
2264 return r;
2265 }
2266
2267 for (i = 0; i < 4; i++) {
2268 if (!(write_mask & (1<<i)))
2269 continue;
2270
2271 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2272 alu.inst = ctx->inst_info->r600_opcode;
2273
2274 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2275
2276 alu.src[0].sel = ctx->temp_reg;
2277 alu.src[0].chan = i;
2278
2279 if (i == last_inst)
2280 alu.last = 1;
2281 r = r600_bytecode_add_alu(ctx->bc, &alu);
2282 if (r)
2283 return r;
2284 }
2285
2286 return 0;
2287 }
2288
2289 static int tgsi_iabs(struct r600_shader_ctx *ctx)
2290 {
2291 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2292 struct r600_bytecode_alu alu;
2293 int i, r;
2294 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2295 int last_inst = tgsi_last_instruction(write_mask);
2296
2297 /* tmp = -src */
2298 for (i = 0; i < 4; i++) {
2299 if (!(write_mask & (1<<i)))
2300 continue;
2301
2302 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2303 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT);
2304
2305 alu.dst.sel = ctx->temp_reg;
2306 alu.dst.chan = i;
2307 alu.dst.write = 1;
2308
2309 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2310 alu.src[0].sel = V_SQ_ALU_SRC_0;
2311
2312 if (i == last_inst)
2313 alu.last = 1;
2314 r = r600_bytecode_add_alu(ctx->bc, &alu);
2315 if (r)
2316 return r;
2317 }
2318
2319 /* dst = (src >= 0 ? src : tmp) */
2320 for (i = 0; i < 4; i++) {
2321 if (!(write_mask & (1<<i)))
2322 continue;
2323
2324 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2325 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2326 alu.is_op3 = 1;
2327 alu.dst.write = 1;
2328
2329 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2330
2331 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2332 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2333 alu.src[2].sel = ctx->temp_reg;
2334 alu.src[2].chan = i;
2335
2336 if (i == last_inst)
2337 alu.last = 1;
2338 r = r600_bytecode_add_alu(ctx->bc, &alu);
2339 if (r)
2340 return r;
2341 }
2342 return 0;
2343 }
2344
2345 static int tgsi_issg(struct r600_shader_ctx *ctx)
2346 {
2347 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2348 struct r600_bytecode_alu alu;
2349 int i, r;
2350 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2351 int last_inst = tgsi_last_instruction(write_mask);
2352
2353 /* tmp = (src >= 0 ? src : -1) */
2354 for (i = 0; i < 4; i++) {
2355 if (!(write_mask & (1<<i)))
2356 continue;
2357
2358 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2359 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE_INT);
2360 alu.is_op3 = 1;
2361
2362 alu.dst.sel = ctx->temp_reg;
2363 alu.dst.chan = i;
2364 alu.dst.write = 1;
2365
2366 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2367 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2368 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
2369
2370 if (i == last_inst)
2371 alu.last = 1;
2372 r = r600_bytecode_add_alu(ctx->bc, &alu);
2373 if (r)
2374 return r;
2375 }
2376
2377 /* dst = (tmp > 0 ? 1 : tmp) */
2378 for (i = 0; i < 4; i++) {
2379 if (!(write_mask & (1<<i)))
2380 continue;
2381
2382 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2383 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT_INT);
2384 alu.is_op3 = 1;
2385 alu.dst.write = 1;
2386
2387 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2388
2389 alu.src[0].sel = ctx->temp_reg;
2390 alu.src[0].chan = i;
2391
2392 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
2393
2394 alu.src[2].sel = ctx->temp_reg;
2395 alu.src[2].chan = i;
2396
2397 if (i == last_inst)
2398 alu.last = 1;
2399 r = r600_bytecode_add_alu(ctx->bc, &alu);
2400 if (r)
2401 return r;
2402 }
2403 return 0;
2404 }
2405
2406
2407
2408 static int tgsi_ssg(struct r600_shader_ctx *ctx)
2409 {
2410 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2411 struct r600_bytecode_alu alu;
2412 int i, r;
2413
2414 /* tmp = (src > 0 ? 1 : src) */
2415 for (i = 0; i < 4; i++) {
2416 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2417 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
2418 alu.is_op3 = 1;
2419
2420 alu.dst.sel = ctx->temp_reg;
2421 alu.dst.chan = i;
2422
2423 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2424 alu.src[1].sel = V_SQ_ALU_SRC_1;
2425 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
2426
2427 if (i == 3)
2428 alu.last = 1;
2429 r = r600_bytecode_add_alu(ctx->bc, &alu);
2430 if (r)
2431 return r;
2432 }
2433
2434 /* dst = (-tmp > 0 ? -1 : tmp) */
2435 for (i = 0; i < 4; i++) {
2436 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2437 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
2438 alu.is_op3 = 1;
2439 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2440
2441 alu.src[0].sel = ctx->temp_reg;
2442 alu.src[0].chan = i;
2443 alu.src[0].neg = 1;
2444
2445 alu.src[1].sel = V_SQ_ALU_SRC_1;
2446 alu.src[1].neg = 1;
2447
2448 alu.src[2].sel = ctx->temp_reg;
2449 alu.src[2].chan = i;
2450
2451 if (i == 3)
2452 alu.last = 1;
2453 r = r600_bytecode_add_alu(ctx->bc, &alu);
2454 if (r)
2455 return r;
2456 }
2457 return 0;
2458 }
2459
2460 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
2461 {
2462 struct r600_bytecode_alu alu;
2463 int i, r;
2464
2465 for (i = 0; i < 4; i++) {
2466 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2467 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
2468 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
2469 alu.dst.chan = i;
2470 } else {
2471 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2472 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2473 alu.src[0].sel = ctx->temp_reg;
2474 alu.src[0].chan = i;
2475 }
2476 if (i == 3) {
2477 alu.last = 1;
2478 }
2479 r = r600_bytecode_add_alu(ctx->bc, &alu);
2480 if (r)
2481 return r;
2482 }
2483 return 0;
2484 }
2485
2486 static int tgsi_op3(struct r600_shader_ctx *ctx)
2487 {
2488 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2489 struct r600_bytecode_alu alu;
2490 int i, j, r;
2491 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2492
2493 for (i = 0; i < lasti + 1; i++) {
2494 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2495 continue;
2496
2497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2498 alu.inst = ctx->inst_info->r600_opcode;
2499 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2500 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2501 }
2502
2503 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2504 alu.dst.chan = i;
2505 alu.dst.write = 1;
2506 alu.is_op3 = 1;
2507 if (i == lasti) {
2508 alu.last = 1;
2509 }
2510 r = r600_bytecode_add_alu(ctx->bc, &alu);
2511 if (r)
2512 return r;
2513 }
2514 return 0;
2515 }
2516
2517 static int tgsi_dp(struct r600_shader_ctx *ctx)
2518 {
2519 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2520 struct r600_bytecode_alu alu;
2521 int i, j, r;
2522
2523 for (i = 0; i < 4; i++) {
2524 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2525 alu.inst = ctx->inst_info->r600_opcode;
2526 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2527 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2528 }
2529
2530 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2531 alu.dst.chan = i;
2532 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2533 /* handle some special cases */
2534 switch (ctx->inst_info->tgsi_opcode) {
2535 case TGSI_OPCODE_DP2:
2536 if (i > 1) {
2537 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
2538 alu.src[0].chan = alu.src[1].chan = 0;
2539 }
2540 break;
2541 case TGSI_OPCODE_DP3:
2542 if (i > 2) {
2543 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
2544 alu.src[0].chan = alu.src[1].chan = 0;
2545 }
2546 break;
2547 case TGSI_OPCODE_DPH:
2548 if (i == 3) {
2549 alu.src[0].sel = V_SQ_ALU_SRC_1;
2550 alu.src[0].chan = 0;
2551 alu.src[0].neg = 0;
2552 }
2553 break;
2554 default:
2555 break;
2556 }
2557 if (i == 3) {
2558 alu.last = 1;
2559 }
2560 r = r600_bytecode_add_alu(ctx->bc, &alu);
2561 if (r)
2562 return r;
2563 }
2564 return 0;
2565 }
2566
2567 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
2568 unsigned index)
2569 {
2570 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2571 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
2572 inst->Src[index].Register.File != TGSI_FILE_INPUT) ||
2573 ctx->src[index].neg || ctx->src[index].abs;
2574 }
2575
2576 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
2577 unsigned index)
2578 {
2579 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2580 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
2581 }
2582
2583 static int tgsi_tex(struct r600_shader_ctx *ctx)
2584 {
2585 static float one_point_five = 1.5f;
2586 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2587 struct r600_bytecode_tex tex;
2588 struct r600_bytecode_alu alu;
2589 unsigned src_gpr;
2590 int r, i, j;
2591 int opcode;
2592 /* Texture fetch instructions can only use gprs as source.
2593 * Also they cannot negate the source or take the absolute value */
2594 const boolean src_requires_loading = tgsi_tex_src_requires_loading(ctx, 0);
2595 boolean src_loaded = FALSE;
2596 unsigned sampler_src_reg = 1;
2597 u8 offset_x = 0, offset_y = 0, offset_z = 0;
2598
2599 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
2600
2601 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
2602 /* get offset values */
2603 if (inst->Texture.NumOffsets) {
2604 assert(inst->Texture.NumOffsets == 1);
2605
2606 offset_x = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
2607 offset_y = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
2608 offset_z = ctx->literals[inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
2609 }
2610 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
2611 /* TGSI moves the sampler to src reg 3 for TXD */
2612 sampler_src_reg = 3;
2613
2614 for (i = 1; i < 3; i++) {
2615 /* set gradients h/v */
2616 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
2617 tex.inst = (i == 1) ? SQ_TEX_INST_SET_GRADIENTS_H :
2618 SQ_TEX_INST_SET_GRADIENTS_V;
2619 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
2620 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
2621
2622 if (tgsi_tex_src_requires_loading(ctx, i)) {
2623 tex.src_gpr = r600_get_temp(ctx);
2624 tex.src_sel_x = 0;
2625 tex.src_sel_y = 1;
2626 tex.src_sel_z = 2;
2627 tex.src_sel_w = 3;
2628
2629 for (j = 0; j < 4; j++) {
2630 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2631 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2632 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
2633 alu.dst.sel = tex.src_gpr;
2634 alu.dst.chan = j;
2635 if (j == 3)
2636 alu.last = 1;
2637 alu.dst.write = 1;
2638 r = r600_bytecode_add_alu(ctx->bc, &alu);
2639 if (r)
2640 return r;
2641 }
2642
2643 } else {
2644 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
2645 tex.src_sel_x = ctx->src[i].swizzle[0];
2646 tex.src_sel_y = ctx->src[i].swizzle[1];
2647 tex.src_sel_z = ctx->src[i].swizzle[2];
2648 tex.src_sel_w = ctx->src[i].swizzle[3];
2649 tex.src_rel = ctx->src[i].rel;
2650 }
2651 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
2652 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
2653 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
2654 tex.coord_type_x = 1;
2655 tex.coord_type_y = 1;
2656 tex.coord_type_z = 1;
2657 tex.coord_type_w = 1;
2658 }
2659 r = r600_bytecode_add_tex(ctx->bc, &tex);
2660 if (r)
2661 return r;
2662 }
2663 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
2664 int out_chan;
2665 /* Add perspective divide */
2666 if (ctx->bc->chip_class == CAYMAN) {
2667 out_chan = 2;
2668 for (i = 0; i < 3; i++) {
2669 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2670 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2671 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
2672
2673 alu.dst.sel = ctx->temp_reg;
2674 alu.dst.chan = i;
2675 if (i == 2)
2676 alu.last = 1;
2677 if (out_chan == i)
2678 alu.dst.write = 1;
2679 r = r600_bytecode_add_alu(ctx->bc, &alu);
2680 if (r)
2681 return r;
2682 }
2683
2684 } else {
2685 out_chan = 3;
2686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2687 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2688 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
2689
2690 alu.dst.sel = ctx->temp_reg;
2691 alu.dst.chan = out_chan;
2692 alu.last = 1;
2693 alu.dst.write = 1;
2694 r = r600_bytecode_add_alu(ctx->bc, &alu);
2695 if (r)
2696 return r;
2697 }
2698
2699 for (i = 0; i < 3; i++) {
2700 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2701 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2702 alu.src[0].sel = ctx->temp_reg;
2703 alu.src[0].chan = out_chan;
2704 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2705 alu.dst.sel = ctx->temp_reg;
2706 alu.dst.chan = i;
2707 alu.dst.write = 1;
2708 r = r600_bytecode_add_alu(ctx->bc, &alu);
2709 if (r)
2710 return r;
2711 }
2712 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2713 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2714 alu.src[0].sel = V_SQ_ALU_SRC_1;
2715 alu.src[0].chan = 0;
2716 alu.dst.sel = ctx->temp_reg;
2717 alu.dst.chan = 3;
2718 alu.last = 1;
2719 alu.dst.write = 1;
2720 r = r600_bytecode_add_alu(ctx->bc, &alu);
2721 if (r)
2722 return r;
2723 src_loaded = TRUE;
2724 src_gpr = ctx->temp_reg;
2725 }
2726
2727 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
2728 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
2729 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
2730
2731 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
2732 for (i = 0; i < 4; i++) {
2733 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2734 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
2735 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
2736 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
2737 alu.dst.sel = ctx->temp_reg;
2738 alu.dst.chan = i;
2739 if (i == 3)
2740 alu.last = 1;
2741 alu.dst.write = 1;
2742 r = r600_bytecode_add_alu(ctx->bc, &alu);
2743 if (r)
2744 return r;
2745 }
2746
2747 /* tmp1.z = RCP_e(|tmp1.z|) */
2748 if (ctx->bc->chip_class == CAYMAN) {
2749 for (i = 0; i < 3; i++) {
2750 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2751 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2752 alu.src[0].sel = ctx->temp_reg;
2753 alu.src[0].chan = 2;
2754 alu.src[0].abs = 1;
2755 alu.dst.sel = ctx->temp_reg;
2756 alu.dst.chan = i;
2757 if (i == 2)
2758 alu.dst.write = 1;
2759 if (i == 2)
2760 alu.last = 1;
2761 r = r600_bytecode_add_alu(ctx->bc, &alu);
2762 if (r)
2763 return r;
2764 }
2765 } else {
2766 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2767 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2768 alu.src[0].sel = ctx->temp_reg;
2769 alu.src[0].chan = 2;
2770 alu.src[0].abs = 1;
2771 alu.dst.sel = ctx->temp_reg;
2772 alu.dst.chan = 2;
2773 alu.dst.write = 1;
2774 alu.last = 1;
2775 r = r600_bytecode_add_alu(ctx->bc, &alu);
2776 if (r)
2777 return r;
2778 }
2779
2780 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
2781 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
2782 * muladd has no writemask, have to use another temp
2783 */
2784 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2785 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2786 alu.is_op3 = 1;
2787
2788 alu.src[0].sel = ctx->temp_reg;
2789 alu.src[0].chan = 0;
2790 alu.src[1].sel = ctx->temp_reg;
2791 alu.src[1].chan = 2;
2792
2793 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2794 alu.src[2].chan = 0;
2795 alu.src[2].value = *(uint32_t *)&one_point_five;
2796
2797 alu.dst.sel = ctx->temp_reg;
2798 alu.dst.chan = 0;
2799 alu.dst.write = 1;
2800
2801 r = r600_bytecode_add_alu(ctx->bc, &alu);
2802 if (r)
2803 return r;
2804
2805 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2806 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2807 alu.is_op3 = 1;
2808
2809 alu.src[0].sel = ctx->temp_reg;
2810 alu.src[0].chan = 1;
2811 alu.src[1].sel = ctx->temp_reg;
2812 alu.src[1].chan = 2;
2813
2814 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2815 alu.src[2].chan = 0;
2816 alu.src[2].value = *(uint32_t *)&one_point_five;
2817
2818 alu.dst.sel = ctx->temp_reg;
2819 alu.dst.chan = 1;
2820 alu.dst.write = 1;
2821
2822 alu.last = 1;
2823 r = r600_bytecode_add_alu(ctx->bc, &alu);
2824 if (r)
2825 return r;
2826
2827 src_loaded = TRUE;
2828 src_gpr = ctx->temp_reg;
2829 }
2830
2831 if (src_requires_loading && !src_loaded) {
2832 for (i = 0; i < 4; i++) {
2833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2834 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2835 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
2836 alu.dst.sel = ctx->temp_reg;
2837 alu.dst.chan = i;
2838 if (i == 3)
2839 alu.last = 1;
2840 alu.dst.write = 1;
2841 r = r600_bytecode_add_alu(ctx->bc, &alu);
2842 if (r)
2843 return r;
2844 }
2845 src_loaded = TRUE;
2846 src_gpr = ctx->temp_reg;
2847 }
2848
2849 opcode = ctx->inst_info->r600_opcode;
2850 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
2851 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
2852 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
2853 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2854 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) {
2855 switch (opcode) {
2856 case SQ_TEX_INST_SAMPLE:
2857 opcode = SQ_TEX_INST_SAMPLE_C;
2858 break;
2859 case SQ_TEX_INST_SAMPLE_L:
2860 opcode = SQ_TEX_INST_SAMPLE_C_L;
2861 break;
2862 case SQ_TEX_INST_SAMPLE_LB:
2863 opcode = SQ_TEX_INST_SAMPLE_C_LB;
2864 break;
2865 case SQ_TEX_INST_SAMPLE_G:
2866 opcode = SQ_TEX_INST_SAMPLE_C_G;
2867 break;
2868 }
2869 }
2870
2871 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
2872 tex.inst = opcode;
2873
2874 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
2875 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
2876 tex.src_gpr = src_gpr;
2877 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
2878 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
2879 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
2880 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
2881 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
2882 if (src_loaded) {
2883 tex.src_sel_x = 0;
2884 tex.src_sel_y = 1;
2885 tex.src_sel_z = 2;
2886 tex.src_sel_w = 3;
2887 } else {
2888 tex.src_sel_x = ctx->src[0].swizzle[0];
2889 tex.src_sel_y = ctx->src[0].swizzle[1];
2890 tex.src_sel_z = ctx->src[0].swizzle[2];
2891 tex.src_sel_w = ctx->src[0].swizzle[3];
2892 tex.src_rel = ctx->src[0].rel;
2893 }
2894
2895 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
2896 tex.src_sel_x = 1;
2897 tex.src_sel_y = 0;
2898 tex.src_sel_z = 3;
2899 tex.src_sel_w = 1;
2900 }
2901
2902 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
2903 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
2904 tex.coord_type_x = 1;
2905 tex.coord_type_y = 1;
2906 }
2907 tex.coord_type_z = 1;
2908 tex.coord_type_w = 1;
2909
2910 tex.offset_x = offset_x;
2911 tex.offset_y = offset_y;
2912 tex.offset_z = offset_z;
2913
2914 /* Put the depth for comparison in W.
2915 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
2916 * Some instructions expect the depth in Z. */
2917 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
2918 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
2919 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
2920 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
2921 opcode != SQ_TEX_INST_SAMPLE_C_L &&
2922 opcode != SQ_TEX_INST_SAMPLE_C_LB) {
2923 tex.src_sel_w = tex.src_sel_z;
2924 }
2925
2926 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
2927 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
2928 if (opcode == SQ_TEX_INST_SAMPLE_C_L ||
2929 opcode == SQ_TEX_INST_SAMPLE_C_LB) {
2930 /* the array index is read from Y */
2931 tex.coord_type_y = 0;
2932 } else {
2933 /* the array index is read from Z */
2934 tex.coord_type_z = 0;
2935 tex.src_sel_z = tex.src_sel_y;
2936 }
2937 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
2938 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
2939 /* the array index is read from Z */
2940 tex.coord_type_z = 0;
2941
2942 r = r600_bytecode_add_tex(ctx->bc, &tex);
2943 if (r)
2944 return r;
2945
2946 /* add shadow ambient support - gallium doesn't do it yet */
2947 return 0;
2948 }
2949
2950 static int tgsi_lrp(struct r600_shader_ctx *ctx)
2951 {
2952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2953 struct r600_bytecode_alu alu;
2954 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2955 unsigned i;
2956 int r;
2957
2958 /* optimize if it's just an equal balance */
2959 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
2960 for (i = 0; i < lasti + 1; i++) {
2961 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2962 continue;
2963
2964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2965 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
2966 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2967 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
2968 alu.omod = 3;
2969 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2970 alu.dst.chan = i;
2971 if (i == lasti) {
2972 alu.last = 1;
2973 }
2974 r = r600_bytecode_add_alu(ctx->bc, &alu);
2975 if (r)
2976 return r;
2977 }
2978 return 0;
2979 }
2980
2981 /* 1 - src0 */
2982 for (i = 0; i < lasti + 1; i++) {
2983 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2984 continue;
2985
2986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2987 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
2988 alu.src[0].sel = V_SQ_ALU_SRC_1;
2989 alu.src[0].chan = 0;
2990 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2991 r600_bytecode_src_toggle_neg(&alu.src[1]);
2992 alu.dst.sel = ctx->temp_reg;
2993 alu.dst.chan = i;
2994 if (i == lasti) {
2995 alu.last = 1;
2996 }
2997 alu.dst.write = 1;
2998 r = r600_bytecode_add_alu(ctx->bc, &alu);
2999 if (r)
3000 return r;
3001 }
3002
3003 /* (1 - src0) * src2 */
3004 for (i = 0; i < lasti + 1; i++) {
3005 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3006 continue;
3007
3008 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3009 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3010 alu.src[0].sel = ctx->temp_reg;
3011 alu.src[0].chan = i;
3012 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
3013 alu.dst.sel = ctx->temp_reg;
3014 alu.dst.chan = i;
3015 if (i == lasti) {
3016 alu.last = 1;
3017 }
3018 alu.dst.write = 1;
3019 r = r600_bytecode_add_alu(ctx->bc, &alu);
3020 if (r)
3021 return r;
3022 }
3023
3024 /* src0 * src1 + (1 - src0) * src2 */
3025 for (i = 0; i < lasti + 1; i++) {
3026 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3027 continue;
3028
3029 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3030 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3031 alu.is_op3 = 1;
3032 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3033 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3034 alu.src[2].sel = ctx->temp_reg;
3035 alu.src[2].chan = i;
3036
3037 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3038 alu.dst.chan = i;
3039 if (i == lasti) {
3040 alu.last = 1;
3041 }
3042 r = r600_bytecode_add_alu(ctx->bc, &alu);
3043 if (r)
3044 return r;
3045 }
3046 return 0;
3047 }
3048
3049 static int tgsi_cmp(struct r600_shader_ctx *ctx)
3050 {
3051 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3052 struct r600_bytecode_alu alu;
3053 int i, r;
3054 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3055
3056 for (i = 0; i < lasti + 1; i++) {
3057 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3058 continue;
3059
3060 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3061 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
3062 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3063 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
3064 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
3065 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3066 alu.dst.chan = i;
3067 alu.dst.write = 1;
3068 alu.is_op3 = 1;
3069 if (i == lasti)
3070 alu.last = 1;
3071 r = r600_bytecode_add_alu(ctx->bc, &alu);
3072 if (r)
3073 return r;
3074 }
3075 return 0;
3076 }
3077
3078 static int tgsi_xpd(struct r600_shader_ctx *ctx)
3079 {
3080 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3081 static const unsigned int src0_swizzle[] = {2, 0, 1};
3082 static const unsigned int src1_swizzle[] = {1, 2, 0};
3083 struct r600_bytecode_alu alu;
3084 uint32_t use_temp = 0;
3085 int i, r;
3086
3087 if (inst->Dst[0].Register.WriteMask != 0xf)
3088 use_temp = 1;
3089
3090 for (i = 0; i < 4; i++) {
3091 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3092 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3093 if (i < 3) {
3094 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
3095 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
3096 } else {
3097 alu.src[0].sel = V_SQ_ALU_SRC_0;
3098 alu.src[0].chan = i;
3099 alu.src[1].sel = V_SQ_ALU_SRC_0;
3100 alu.src[1].chan = i;
3101 }
3102
3103 alu.dst.sel = ctx->temp_reg;
3104 alu.dst.chan = i;
3105 alu.dst.write = 1;
3106
3107 if (i == 3)
3108 alu.last = 1;
3109 r = r600_bytecode_add_alu(ctx->bc, &alu);
3110 if (r)
3111 return r;
3112 }
3113
3114 for (i = 0; i < 4; i++) {
3115 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3116 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
3117
3118 if (i < 3) {
3119 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
3120 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
3121 } else {
3122 alu.src[0].sel = V_SQ_ALU_SRC_0;
3123 alu.src[0].chan = i;
3124 alu.src[1].sel = V_SQ_ALU_SRC_0;
3125 alu.src[1].chan = i;
3126 }
3127
3128 alu.src[2].sel = ctx->temp_reg;
3129 alu.src[2].neg = 1;
3130 alu.src[2].chan = i;
3131
3132 if (use_temp)
3133 alu.dst.sel = ctx->temp_reg;
3134 else
3135 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3136 alu.dst.chan = i;
3137 alu.dst.write = 1;
3138 alu.is_op3 = 1;
3139 if (i == 3)
3140 alu.last = 1;
3141 r = r600_bytecode_add_alu(ctx->bc, &alu);
3142 if (r)
3143 return r;
3144 }
3145 if (use_temp)
3146 return tgsi_helper_copy(ctx, inst);
3147 return 0;
3148 }
3149
3150 static int tgsi_exp(struct r600_shader_ctx *ctx)
3151 {
3152 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3153 struct r600_bytecode_alu alu;
3154 int r;
3155 int i;
3156
3157 /* result.x = 2^floor(src); */
3158 if (inst->Dst[0].Register.WriteMask & 1) {
3159 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3160
3161 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
3162 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3163
3164 alu.dst.sel = ctx->temp_reg;
3165 alu.dst.chan = 0;
3166 alu.dst.write = 1;
3167 alu.last = 1;
3168 r = r600_bytecode_add_alu(ctx->bc, &alu);
3169 if (r)
3170 return r;
3171
3172 if (ctx->bc->chip_class == CAYMAN) {
3173 for (i = 0; i < 3; i++) {
3174 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3175 alu.src[0].sel = ctx->temp_reg;
3176 alu.src[0].chan = 0;
3177
3178 alu.dst.sel = ctx->temp_reg;
3179 alu.dst.chan = i;
3180 if (i == 0)
3181 alu.dst.write = 1;
3182 if (i == 2)
3183 alu.last = 1;
3184 r = r600_bytecode_add_alu(ctx->bc, &alu);
3185 if (r)
3186 return r;
3187 }
3188 } else {
3189 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3190 alu.src[0].sel = ctx->temp_reg;
3191 alu.src[0].chan = 0;
3192
3193 alu.dst.sel = ctx->temp_reg;
3194 alu.dst.chan = 0;
3195 alu.dst.write = 1;
3196 alu.last = 1;
3197 r = r600_bytecode_add_alu(ctx->bc, &alu);
3198 if (r)
3199 return r;
3200 }
3201 }
3202
3203 /* result.y = tmp - floor(tmp); */
3204 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
3205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3206
3207 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
3208 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3209
3210 alu.dst.sel = ctx->temp_reg;
3211 #if 0
3212 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3213 if (r)
3214 return r;
3215 #endif
3216 alu.dst.write = 1;
3217 alu.dst.chan = 1;
3218
3219 alu.last = 1;
3220
3221 r = r600_bytecode_add_alu(ctx->bc, &alu);
3222 if (r)
3223 return r;
3224 }
3225
3226 /* result.z = RoughApprox2ToX(tmp);*/
3227 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
3228 if (ctx->bc->chip_class == CAYMAN) {
3229 for (i = 0; i < 3; i++) {
3230 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3231 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3232 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3233
3234 alu.dst.sel = ctx->temp_reg;
3235 alu.dst.chan = i;
3236 if (i == 2) {
3237 alu.dst.write = 1;
3238 alu.last = 1;
3239 }
3240
3241 r = r600_bytecode_add_alu(ctx->bc, &alu);
3242 if (r)
3243 return r;
3244 }
3245 } else {
3246 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3247 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3248 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3249
3250 alu.dst.sel = ctx->temp_reg;
3251 alu.dst.write = 1;
3252 alu.dst.chan = 2;
3253
3254 alu.last = 1;
3255
3256 r = r600_bytecode_add_alu(ctx->bc, &alu);
3257 if (r)
3258 return r;
3259 }
3260 }
3261
3262 /* result.w = 1.0;*/
3263 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
3264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3265
3266 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3267 alu.src[0].sel = V_SQ_ALU_SRC_1;
3268 alu.src[0].chan = 0;
3269
3270 alu.dst.sel = ctx->temp_reg;
3271 alu.dst.chan = 3;
3272 alu.dst.write = 1;
3273 alu.last = 1;
3274 r = r600_bytecode_add_alu(ctx->bc, &alu);
3275 if (r)
3276 return r;
3277 }
3278 return tgsi_helper_copy(ctx, inst);
3279 }
3280
3281 static int tgsi_log(struct r600_shader_ctx *ctx)
3282 {
3283 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3284 struct r600_bytecode_alu alu;
3285 int r;
3286 int i;
3287
3288 /* result.x = floor(log2(|src|)); */
3289 if (inst->Dst[0].Register.WriteMask & 1) {
3290 if (ctx->bc->chip_class == CAYMAN) {
3291 for (i = 0; i < 3; i++) {
3292 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3293
3294 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3295 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3296 r600_bytecode_src_set_abs(&alu.src[0]);
3297
3298 alu.dst.sel = ctx->temp_reg;
3299 alu.dst.chan = i;
3300 if (i == 0)
3301 alu.dst.write = 1;
3302 if (i == 2)
3303 alu.last = 1;
3304 r = r600_bytecode_add_alu(ctx->bc, &alu);
3305 if (r)
3306 return r;
3307 }
3308
3309 } else {
3310 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3311
3312 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3313 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3314 r600_bytecode_src_set_abs(&alu.src[0]);
3315
3316 alu.dst.sel = ctx->temp_reg;
3317 alu.dst.chan = 0;
3318 alu.dst.write = 1;
3319 alu.last = 1;
3320 r = r600_bytecode_add_alu(ctx->bc, &alu);
3321 if (r)
3322 return r;
3323 }
3324
3325 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
3326 alu.src[0].sel = ctx->temp_reg;
3327 alu.src[0].chan = 0;
3328
3329 alu.dst.sel = ctx->temp_reg;
3330 alu.dst.chan = 0;
3331 alu.dst.write = 1;
3332 alu.last = 1;
3333
3334 r = r600_bytecode_add_alu(ctx->bc, &alu);
3335 if (r)
3336 return r;
3337 }
3338
3339 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
3340 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
3341
3342 if (ctx->bc->chip_class == CAYMAN) {
3343 for (i = 0; i < 3; i++) {
3344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3345
3346 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3347 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3348 r600_bytecode_src_set_abs(&alu.src[0]);
3349
3350 alu.dst.sel = ctx->temp_reg;
3351 alu.dst.chan = i;
3352 if (i == 1)
3353 alu.dst.write = 1;
3354 if (i == 2)
3355 alu.last = 1;
3356
3357 r = r600_bytecode_add_alu(ctx->bc, &alu);
3358 if (r)
3359 return r;
3360 }
3361 } else {
3362 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3363
3364 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3365 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3366 r600_bytecode_src_set_abs(&alu.src[0]);
3367
3368 alu.dst.sel = ctx->temp_reg;
3369 alu.dst.chan = 1;
3370 alu.dst.write = 1;
3371 alu.last = 1;
3372
3373 r = r600_bytecode_add_alu(ctx->bc, &alu);
3374 if (r)
3375 return r;
3376 }
3377
3378 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3379
3380 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
3381 alu.src[0].sel = ctx->temp_reg;
3382 alu.src[0].chan = 1;
3383
3384 alu.dst.sel = ctx->temp_reg;
3385 alu.dst.chan = 1;
3386 alu.dst.write = 1;
3387 alu.last = 1;
3388
3389 r = r600_bytecode_add_alu(ctx->bc, &alu);
3390 if (r)
3391 return r;
3392
3393 if (ctx->bc->chip_class == CAYMAN) {
3394 for (i = 0; i < 3; i++) {
3395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3396 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3397 alu.src[0].sel = ctx->temp_reg;
3398 alu.src[0].chan = 1;
3399
3400 alu.dst.sel = ctx->temp_reg;
3401 alu.dst.chan = i;
3402 if (i == 1)
3403 alu.dst.write = 1;
3404 if (i == 2)
3405 alu.last = 1;
3406
3407 r = r600_bytecode_add_alu(ctx->bc, &alu);
3408 if (r)
3409 return r;
3410 }
3411 } else {
3412 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3413 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
3414 alu.src[0].sel = ctx->temp_reg;
3415 alu.src[0].chan = 1;
3416
3417 alu.dst.sel = ctx->temp_reg;
3418 alu.dst.chan = 1;
3419 alu.dst.write = 1;
3420 alu.last = 1;
3421
3422 r = r600_bytecode_add_alu(ctx->bc, &alu);
3423 if (r)
3424 return r;
3425 }
3426
3427 if (ctx->bc->chip_class == CAYMAN) {
3428 for (i = 0; i < 3; i++) {
3429 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3430 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3431 alu.src[0].sel = ctx->temp_reg;
3432 alu.src[0].chan = 1;
3433
3434 alu.dst.sel = ctx->temp_reg;
3435 alu.dst.chan = i;
3436 if (i == 1)
3437 alu.dst.write = 1;
3438 if (i == 2)
3439 alu.last = 1;
3440
3441 r = r600_bytecode_add_alu(ctx->bc, &alu);
3442 if (r)
3443 return r;
3444 }
3445 } else {
3446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3447 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
3448 alu.src[0].sel = ctx->temp_reg;
3449 alu.src[0].chan = 1;
3450
3451 alu.dst.sel = ctx->temp_reg;
3452 alu.dst.chan = 1;
3453 alu.dst.write = 1;
3454 alu.last = 1;
3455
3456 r = r600_bytecode_add_alu(ctx->bc, &alu);
3457 if (r)
3458 return r;
3459 }
3460
3461 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3462
3463 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3464
3465 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3466 r600_bytecode_src_set_abs(&alu.src[0]);
3467
3468 alu.src[1].sel = ctx->temp_reg;
3469 alu.src[1].chan = 1;
3470
3471 alu.dst.sel = ctx->temp_reg;
3472 alu.dst.chan = 1;
3473 alu.dst.write = 1;
3474 alu.last = 1;
3475
3476 r = r600_bytecode_add_alu(ctx->bc, &alu);
3477 if (r)
3478 return r;
3479 }
3480
3481 /* result.z = log2(|src|);*/
3482 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
3483 if (ctx->bc->chip_class == CAYMAN) {
3484 for (i = 0; i < 3; i++) {
3485 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3486
3487 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3488 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3489 r600_bytecode_src_set_abs(&alu.src[0]);
3490
3491 alu.dst.sel = ctx->temp_reg;
3492 if (i == 2)
3493 alu.dst.write = 1;
3494 alu.dst.chan = i;
3495 if (i == 2)
3496 alu.last = 1;
3497
3498 r = r600_bytecode_add_alu(ctx->bc, &alu);
3499 if (r)
3500 return r;
3501 }
3502 } else {
3503 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3504
3505 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
3506 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3507 r600_bytecode_src_set_abs(&alu.src[0]);
3508
3509 alu.dst.sel = ctx->temp_reg;
3510 alu.dst.write = 1;
3511 alu.dst.chan = 2;
3512 alu.last = 1;
3513
3514 r = r600_bytecode_add_alu(ctx->bc, &alu);
3515 if (r)
3516 return r;
3517 }
3518 }
3519
3520 /* result.w = 1.0; */
3521 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
3522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3523
3524 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
3525 alu.src[0].sel = V_SQ_ALU_SRC_1;
3526 alu.src[0].chan = 0;
3527
3528 alu.dst.sel = ctx->temp_reg;
3529 alu.dst.chan = 3;
3530 alu.dst.write = 1;
3531 alu.last = 1;
3532
3533 r = r600_bytecode_add_alu(ctx->bc, &alu);
3534 if (r)
3535 return r;
3536 }
3537
3538 return tgsi_helper_copy(ctx, inst);
3539 }
3540
3541 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
3542 {
3543 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3544 struct r600_bytecode_alu alu;
3545 int r;
3546
3547 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3548
3549 switch (inst->Instruction.Opcode) {
3550 case TGSI_OPCODE_ARL:
3551 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
3552 break;
3553 case TGSI_OPCODE_ARR:
3554 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
3555 break;
3556 case TGSI_OPCODE_UARL:
3557 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
3558 break;
3559 default:
3560 assert(0);
3561 return -1;
3562 }
3563
3564 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3565 alu.last = 1;
3566 alu.dst.sel = ctx->bc->ar_reg;
3567 alu.dst.write = 1;
3568 r = r600_bytecode_add_alu(ctx->bc, &alu);
3569 if (r)
3570 return r;
3571
3572 ctx->bc->ar_loaded = 0;
3573 return 0;
3574 }
3575 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
3576 {
3577 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3578 struct r600_bytecode_alu alu;
3579 int r;
3580
3581 switch (inst->Instruction.Opcode) {
3582 case TGSI_OPCODE_ARL:
3583 memset(&alu, 0, sizeof(alu));
3584 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
3585 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3586 alu.dst.sel = ctx->bc->ar_reg;
3587 alu.dst.write = 1;
3588 alu.last = 1;
3589
3590 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3591 return r;
3592
3593 memset(&alu, 0, sizeof(alu));
3594 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
3595 alu.src[0].sel = ctx->bc->ar_reg;
3596 alu.dst.sel = ctx->bc->ar_reg;
3597 alu.dst.write = 1;
3598 alu.last = 1;
3599
3600 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3601 return r;
3602 break;
3603 case TGSI_OPCODE_ARR:
3604 memset(&alu, 0, sizeof(alu));
3605 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
3606 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3607 alu.dst.sel = ctx->bc->ar_reg;
3608 alu.dst.write = 1;
3609 alu.last = 1;
3610
3611 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3612 return r;
3613 break;
3614 case TGSI_OPCODE_UARL:
3615 memset(&alu, 0, sizeof(alu));
3616 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
3617 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3618 alu.dst.sel = ctx->bc->ar_reg;
3619 alu.dst.write = 1;
3620 alu.last = 1;
3621
3622 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3623 return r;
3624 break;
3625 default:
3626 assert(0);
3627 return -1;
3628 }
3629
3630 ctx->bc->ar_loaded = 0;
3631 return 0;
3632 }
3633
3634 static int tgsi_opdst(struct r600_shader_ctx *ctx)
3635 {
3636 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3637 struct r600_bytecode_alu alu;
3638 int i, r = 0;
3639
3640 for (i = 0; i < 4; i++) {
3641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3642
3643 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
3644 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3645
3646 if (i == 0 || i == 3) {
3647 alu.src[0].sel = V_SQ_ALU_SRC_1;
3648 } else {
3649 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3650 }
3651
3652 if (i == 0 || i == 2) {
3653 alu.src[1].sel = V_SQ_ALU_SRC_1;
3654 } else {
3655 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3656 }
3657 if (i == 3)
3658 alu.last = 1;
3659 r = r600_bytecode_add_alu(ctx->bc, &alu);
3660 if (r)
3661 return r;
3662 }
3663 return 0;
3664 }
3665
3666 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
3667 {
3668 struct r600_bytecode_alu alu;
3669 int r;
3670
3671 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3672 alu.inst = opcode;
3673 alu.predicate = 1;
3674
3675 alu.dst.sel = ctx->temp_reg;
3676 alu.dst.write = 1;
3677 alu.dst.chan = 0;
3678
3679 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3680 alu.src[1].sel = V_SQ_ALU_SRC_0;
3681 alu.src[1].chan = 0;
3682
3683 alu.last = 1;
3684
3685 r = r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
3686 if (r)
3687 return r;
3688 return 0;
3689 }
3690
3691 static int pops(struct r600_shader_ctx *ctx, int pops)
3692 {
3693 unsigned force_pop = ctx->bc->force_add_cf;
3694
3695 if (!force_pop) {
3696 int alu_pop = 3;
3697 if (ctx->bc->cf_last) {
3698 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU))
3699 alu_pop = 0;
3700 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER))
3701 alu_pop = 1;
3702 }
3703 alu_pop += pops;
3704 if (alu_pop == 1) {
3705 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER);
3706 ctx->bc->force_add_cf = 1;
3707 } else if (alu_pop == 2) {
3708 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER);
3709 ctx->bc->force_add_cf = 1;
3710 } else {
3711 force_pop = 1;
3712 }
3713 }
3714
3715 if (force_pop) {
3716 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
3717 ctx->bc->cf_last->pop_count = pops;
3718 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
3719 }
3720
3721 return 0;
3722 }
3723
3724 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
3725 {
3726 switch(reason) {
3727 case FC_PUSH_VPM:
3728 ctx->bc->callstack[ctx->bc->call_sp].current--;
3729 break;
3730 case FC_PUSH_WQM:
3731 case FC_LOOP:
3732 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
3733 break;
3734 case FC_REP:
3735 /* TOODO : for 16 vp asic should -= 2; */
3736 ctx->bc->callstack[ctx->bc->call_sp].current --;
3737 break;
3738 }
3739 }
3740
3741 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
3742 {
3743 if (check_max_only) {
3744 int diff;
3745 switch (reason) {
3746 case FC_PUSH_VPM:
3747 diff = 1;
3748 break;
3749 case FC_PUSH_WQM:
3750 diff = 4;
3751 break;
3752 default:
3753 assert(0);
3754 diff = 0;
3755 }
3756 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
3757 ctx->bc->callstack[ctx->bc->call_sp].max) {
3758 ctx->bc->callstack[ctx->bc->call_sp].max =
3759 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
3760 }
3761 return;
3762 }
3763 switch (reason) {
3764 case FC_PUSH_VPM:
3765 ctx->bc->callstack[ctx->bc->call_sp].current++;
3766 break;
3767 case FC_PUSH_WQM:
3768 case FC_LOOP:
3769 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
3770 break;
3771 case FC_REP:
3772 ctx->bc->callstack[ctx->bc->call_sp].current++;
3773 break;
3774 }
3775
3776 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
3777 ctx->bc->callstack[ctx->bc->call_sp].max) {
3778 ctx->bc->callstack[ctx->bc->call_sp].max =
3779 ctx->bc->callstack[ctx->bc->call_sp].current;
3780 }
3781 }
3782
3783 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
3784 {
3785 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
3786
3787 sp->mid = (struct r600_bytecode_cf **)realloc((void *)sp->mid,
3788 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
3789 sp->mid[sp->num_mid] = ctx->bc->cf_last;
3790 sp->num_mid++;
3791 }
3792
3793 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
3794 {
3795 ctx->bc->fc_sp++;
3796 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
3797 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
3798 }
3799
3800 static void fc_poplevel(struct r600_shader_ctx *ctx)
3801 {
3802 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
3803 if (sp->mid) {
3804 free(sp->mid);
3805 sp->mid = NULL;
3806 }
3807 sp->num_mid = 0;
3808 sp->start = NULL;
3809 sp->type = 0;
3810 ctx->bc->fc_sp--;
3811 }
3812
3813 #if 0
3814 static int emit_return(struct r600_shader_ctx *ctx)
3815 {
3816 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_RETURN));
3817 return 0;
3818 }
3819
3820 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
3821 {
3822
3823 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
3824 ctx->bc->cf_last->pop_count = pops;
3825 /* TODO work out offset */
3826 return 0;
3827 }
3828
3829 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
3830 {
3831 return 0;
3832 }
3833
3834 static void emit_testflag(struct r600_shader_ctx *ctx)
3835 {
3836
3837 }
3838
3839 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
3840 {
3841 emit_testflag(ctx);
3842 emit_jump_to_offset(ctx, 1, 4);
3843 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
3844 pops(ctx, ifidx + 1);
3845 emit_return(ctx);
3846 }
3847
3848 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
3849 {
3850 emit_testflag(ctx);
3851
3852 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
3853 ctx->bc->cf_last->pop_count = 1;
3854
3855 fc_set_mid(ctx, fc_sp);
3856
3857 pops(ctx, 1);
3858 }
3859 #endif
3860
3861 static int tgsi_if(struct r600_shader_ctx *ctx)
3862 {
3863 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
3864
3865 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
3866
3867 fc_pushlevel(ctx, FC_IF);
3868
3869 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
3870 return 0;
3871 }
3872
3873 static int tgsi_else(struct r600_shader_ctx *ctx)
3874 {
3875 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
3876 ctx->bc->cf_last->pop_count = 1;
3877
3878 fc_set_mid(ctx, ctx->bc->fc_sp);
3879 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
3880 return 0;
3881 }
3882
3883 static int tgsi_endif(struct r600_shader_ctx *ctx)
3884 {
3885 pops(ctx, 1);
3886 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
3887 R600_ERR("if/endif unbalanced in shader\n");
3888 return -1;
3889 }
3890
3891 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
3892 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
3893 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
3894 } else {
3895 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
3896 }
3897 fc_poplevel(ctx);
3898
3899 callstack_decrease_current(ctx, FC_PUSH_VPM);
3900 return 0;
3901 }
3902
3903 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
3904 {
3905 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
3906
3907 fc_pushlevel(ctx, FC_LOOP);
3908
3909 /* check stack depth */
3910 callstack_check_depth(ctx, FC_LOOP, 0);
3911 return 0;
3912 }
3913
3914 static int tgsi_endloop(struct r600_shader_ctx *ctx)
3915 {
3916 int i;
3917
3918 r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
3919
3920 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
3921 R600_ERR("loop/endloop in shader code are not paired.\n");
3922 return -EINVAL;
3923 }
3924
3925 /* fixup loop pointers - from r600isa
3926 LOOP END points to CF after LOOP START,
3927 LOOP START point to CF after LOOP END
3928 BRK/CONT point to LOOP END CF
3929 */
3930 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
3931
3932 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
3933
3934 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
3935 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
3936 }
3937 /* TODO add LOOPRET support */
3938 fc_poplevel(ctx);
3939 callstack_decrease_current(ctx, FC_LOOP);
3940 return 0;
3941 }
3942
3943 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
3944 {
3945 unsigned int fscp;
3946
3947 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
3948 {
3949 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
3950 break;
3951 }
3952
3953 if (fscp == 0) {
3954 R600_ERR("Break not inside loop/endloop pair\n");
3955 return -EINVAL;
3956 }
3957
3958 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
3959 ctx->bc->cf_last->pop_count = 1;
3960
3961 fc_set_mid(ctx, fscp);
3962
3963 pops(ctx, 1);
3964 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
3965 return 0;
3966 }
3967
3968 static int tgsi_umad(struct r600_shader_ctx *ctx)
3969 {
3970 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3971 struct r600_bytecode_alu alu;
3972 int i, j, r;
3973 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
3974
3975 /* src0 * src1 */
3976 for (i = 0; i < lasti + 1; i++) {
3977 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
3978 continue;
3979
3980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3981
3982 alu.dst.chan = i;
3983 alu.dst.sel = ctx->temp_reg;
3984 alu.dst.write = 1;
3985
3986 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT);
3987 for (j = 0; j < 2; j++) {
3988 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
3989 }
3990
3991 alu.last = 1;
3992 r = r600_bytecode_add_alu(ctx->bc, &alu);
3993 if (r)
3994 return r;
3995 }
3996
3997
3998 for (i = 0; i < lasti + 1; i++) {
3999 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4000 continue;
4001
4002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4003 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4004
4005 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
4006
4007 alu.src[0].sel = ctx->temp_reg;
4008 alu.src[0].chan = i;
4009
4010 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
4011 if (i == lasti) {
4012 alu.last = 1;
4013 }
4014 r = r600_bytecode_add_alu(ctx->bc, &alu);
4015 if (r)
4016 return r;
4017 }
4018 return 0;
4019 }
4020
4021 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
4022 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
4023 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4024 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
4025
4026 /* FIXME:
4027 * For state trackers other than OpenGL, we'll want to use
4028 * _RECIP_IEEE instead.
4029 */
4030 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
4031
4032 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
4033 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
4034 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
4035 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
4036 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4037 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4038 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4039 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
4040 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
4041 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
4042 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
4043 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
4044 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
4045 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4046 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
4047 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4048 /* gap */
4049 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4050 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4051 /* gap */
4052 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4053 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4054 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
4055 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4056 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
4057 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
4058 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
4059 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
4060 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
4061 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
4062 /* gap */
4063 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4064 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4065 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4066 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4067 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
4068 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
4069 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
4070 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
4071 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4072 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4073 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4074 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4075 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4076 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
4077 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4078 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
4079 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
4080 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
4081 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
4082 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4083 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4084 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
4085 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4086 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4087 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4088 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4089 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4090 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4091 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4092 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
4093 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4094 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4095 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4096 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
4097 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
4098 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
4099 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
4100 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4101 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4102 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4103 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
4104 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
4105 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
4106 /* gap */
4107 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4108 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4109 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
4110 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
4111 /* gap */
4112 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4113 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4114 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4115 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4116 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4117 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
4118 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
4119 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
4120 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2_trans},
4121 /* gap */
4122 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4123 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
4124 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
4125 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4126 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
4127 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4128 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
4129 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
4130 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
4131 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4132 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4133 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
4134 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4135 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
4136 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4137 /* gap */
4138 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4139 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4140 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4141 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4142 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4143 /* gap */
4144 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4145 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4146 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4147 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4148 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4149 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4150 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4151 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4152 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
4153 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
4154 /* gap */
4155 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4156 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_op2_trans},
4157 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
4158 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
4159 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
4160 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_op2},
4161 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
4162 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2_trans},
4163 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2},
4164 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
4165 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
4166 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
4167 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
4168 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
4169 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
4170 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
4171 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4172 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
4173 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
4174 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
4175 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2_trans},
4176 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
4177 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2_swap},
4178 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4179 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4180 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4181 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4182 {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4183 {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4184 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4185 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4186 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4187 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4188 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4189 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4190 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4191 {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
4192 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
4193 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
4194 {TGSI_OPCODE_UARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
4195 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
4196 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
4197 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
4198 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4199 };
4200
4201 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
4202 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4203 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4204 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
4205 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
4206 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_rsq},
4207 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
4208 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
4209 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
4210 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4211 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4212 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4213 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
4214 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
4215 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
4216 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
4217 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
4218 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
4219 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4220 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
4221 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4222 /* gap */
4223 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4224 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4225 /* gap */
4226 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4227 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4228 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
4229 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4230 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
4231 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
4232 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
4233 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
4234 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
4235 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
4236 /* gap */
4237 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4238 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4239 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4240 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4241 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
4242 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
4243 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
4244 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
4245 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4246 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4247 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4248 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4249 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4250 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
4251 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4252 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
4253 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
4254 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
4255 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
4256 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4257 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4258 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
4259 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4260 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4261 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4262 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4263 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4264 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4265 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4266 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4267 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4268 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4269 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4270 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
4271 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
4272 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
4273 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
4274 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4275 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4276 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4277 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
4278 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
4279 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
4280 /* gap */
4281 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4282 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4283 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
4284 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
4285 /* gap */
4286 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4287 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4288 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4289 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4290 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4291 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
4292 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
4293 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
4294 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT, tgsi_op2},
4295 /* gap */
4296 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4297 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT, tgsi_op2},
4298 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT, tgsi_op2},
4299 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4300 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
4301 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4302 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
4303 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
4304 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
4305 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4306 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4307 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
4308 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4309 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
4310 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4311 /* gap */
4312 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4313 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4314 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4315 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4316 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4317 /* gap */
4318 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4319 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4320 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4321 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4322 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4323 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4324 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4325 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4326 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
4327 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
4328 /* gap */
4329 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4330 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT, tgsi_f2i},
4331 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
4332 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
4333 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
4334 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT, tgsi_ineg},
4335 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
4336 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2},
4337 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
4338 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_f2i},
4339 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2},
4340 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
4341 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_idiv},
4342 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_umad},
4343 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT, tgsi_op2},
4344 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT, tgsi_op2},
4345 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4346 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT, tgsi_op2_trans},
4347 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT, tgsi_op2},
4348 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT, tgsi_op2},
4349 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT, tgsi_op2},
4350 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
4351 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT, tgsi_op2},
4352 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4353 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4354 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4355 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4356 {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4357 {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4358 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4359 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4360 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4361 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4362 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4363 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4364 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4365 {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
4366 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
4367 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
4368 {TGSI_OPCODE_UARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
4369 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
4370 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
4371 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
4372 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4373 };
4374
4375 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
4376 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4377 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4378 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
4379 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, cayman_emit_float_instr},
4380 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, cayman_emit_float_instr},
4381 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
4382 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
4383 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
4384 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4385 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4386 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4387 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
4388 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
4389 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
4390 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
4391 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
4392 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
4393 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
4394 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
4395 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4396 /* gap */
4397 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4398 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4399 /* gap */
4400 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4401 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4402 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
4403 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4404 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
4405 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
4406 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, cayman_emit_float_instr},
4407 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, cayman_emit_float_instr},
4408 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, cayman_pow},
4409 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
4410 /* gap */
4411 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4412 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
4413 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4414 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4415 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, cayman_trig},
4416 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
4417 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
4418 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
4419 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4420 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4421 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4422 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4423 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4424 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
4425 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4426 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
4427 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, cayman_trig},
4428 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
4429 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
4430 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4431 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4432 {TGSI_OPCODE_TXD, 0, SQ_TEX_INST_SAMPLE_G, tgsi_tex},
4433 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
4434 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4435 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4436 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4437 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4438 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4439 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4440 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
4441 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4442 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4443 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4444 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
4445 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
4446 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
4447 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_LB, tgsi_tex},
4448 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4449 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4450 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
4451 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
4452 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
4453 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
4454 /* gap */
4455 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4456 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4457 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
4458 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
4459 /* gap */
4460 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4461 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4462 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4463 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4464 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4465 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4466 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
4467 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
4468 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4469 /* gap */
4470 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4471 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4472 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4473 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4474 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT, tgsi_op2},
4475 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4476 {TGSI_OPCODE_TXF, 0, SQ_TEX_INST_LD, tgsi_tex},
4477 {TGSI_OPCODE_TXQ, 0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
4478 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
4479 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4480 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4481 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
4482 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4483 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
4484 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4485 /* gap */
4486 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4487 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4488 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4489 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4490 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4491 /* gap */
4492 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4493 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4494 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4495 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4496 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4497 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4498 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4499 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4500 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
4501 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
4502 /* gap */
4503 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4504 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4505 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4506 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT, tgsi_op2},
4507 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT, tgsi_op2},
4508 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4509 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4510 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4511 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4512 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4513 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4514 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4515 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4516 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4517 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4518 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4519 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4520 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4521 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4522 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4523 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4524 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4525 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4526 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4527 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4528 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4529 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4530 {TGSI_OPCODE_LOAD, 0, 0, tgsi_unsupported},
4531 {TGSI_OPCODE_LOAD_MS, 0, 0, tgsi_unsupported},
4532 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
4533 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
4534 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
4535 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
4536 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
4537 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
4538 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
4539 {TGSI_OPCODE_RESINFO, 0, 0, tgsi_unsupported},
4540 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
4541 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
4542 {TGSI_OPCODE_UARL, 0, 0, tgsi_unsupported},
4543 {TGSI_OPCODE_UCMP, 0, 0, tgsi_unsupported},
4544 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
4545 };