projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
r600g: switch SNORM conversion to DX and GLES behavior
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_llvm.h"
25 #include "r600_formats.h"
26 #include "r600_opcodes.h"
27 #include "r600_shader.h"
28 #include "r600d.h"
29
30 #include "sb/sb_public.h"
31
32 #include "pipe/p_shader_tokens.h"
33 #include "tgsi/tgsi_info.h"
34 #include "tgsi/tgsi_parse.h"
35 #include "tgsi/tgsi_scan.h"
36 #include "tgsi/tgsi_dump.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 static int r600_shader_from_tgsi(struct r600_context *rctx,
64 struct r600_pipe_shader *pipeshader,
65 struct r600_shader_key key);
66
67 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
68 int size, unsigned comp_mask) {
69
70 if (!size)
71 return;
72
73 if (ps->num_arrays == ps->max_arrays) {
74 ps->max_arrays += 64;
75 ps->arrays = realloc(ps->arrays, ps->max_arrays *
76 sizeof(struct r600_shader_array));
77 }
78
79 int n = ps->num_arrays;
80 ++ps->num_arrays;
81
82 ps->arrays[n].comp_mask = comp_mask;
83 ps->arrays[n].gpr_start = start_gpr;
84 ps->arrays[n].gpr_count = size;
85 }
86
87 static void r600_dump_streamout(struct pipe_stream_output_info *so)
88 {
89 unsigned i;
90
91 fprintf(stderr, "STREAMOUT\n");
92 for (i = 0; i < so->num_outputs; i++) {
93 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
94 so->output[i].start_component;
95 fprintf(stderr, " %i: MEM_STREAM0_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
96 i, so->output[i].output_buffer,
97 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
98 so->output[i].register_index,
99 mask & 1 ? "x" : "",
100 mask & 2 ? "y" : "",
101 mask & 4 ? "z" : "",
102 mask & 8 ? "w" : "",
103 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
104 }
105 }
106
107 static int store_shader(struct pipe_context *ctx,
108 struct r600_pipe_shader *shader)
109 {
110 struct r600_context *rctx = (struct r600_context *)ctx;
111 uint32_t *ptr, i;
112
113 if (shader->bo == NULL) {
114 shader->bo = (struct r600_resource*)
115 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
116 if (shader->bo == NULL) {
117 return -ENOMEM;
118 }
119 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
120 if (R600_BIG_ENDIAN) {
121 for (i = 0; i < shader->shader.bc.ndw; ++i) {
122 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
123 }
124 } else {
125 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
126 }
127 rctx->b.ws->buffer_unmap(shader->bo->cs_buf);
128 }
129
130 return 0;
131 }
132
133 int r600_pipe_shader_create(struct pipe_context *ctx,
134 struct r600_pipe_shader *shader,
135 struct r600_shader_key key)
136 {
137 struct r600_context *rctx = (struct r600_context *)ctx;
138 struct r600_pipe_shader_selector *sel = shader->selector;
139 int r;
140 bool dump = r600_can_dump_shader(&rctx->screen->b, sel->tokens);
141 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
142 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
143 unsigned export_shader = key.vs_as_es;
144
145 shader->shader.bc.isa = rctx->isa;
146
147 if (dump) {
148 fprintf(stderr, "--------------------------------------------------------------\n");
149 tgsi_dump(sel->tokens, 0);
150
151 if (sel->so.num_outputs) {
152 r600_dump_streamout(&sel->so);
153 }
154 }
155 r = r600_shader_from_tgsi(rctx, shader, key);
156 if (r) {
157 R600_ERR("translation from TGSI failed !\n");
158 goto error;
159 }
160
161 /* disable SB for geom shaders - it can't handle the CF_EMIT instructions */
162 use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_GEOMETRY);
163
164 /* Check if the bytecode has already been built. When using the llvm
165 * backend, r600_shader_from_tgsi() will take care of building the
166 * bytecode.
167 */
168 if (!shader->shader.bc.bytecode) {
169 r = r600_bytecode_build(&shader->shader.bc);
170 if (r) {
171 R600_ERR("building bytecode failed !\n");
172 goto error;
173 }
174 }
175
176 if (dump && !sb_disasm) {
177 fprintf(stderr, "--------------------------------------------------------------\n");
178 r600_bytecode_disasm(&shader->shader.bc);
179 fprintf(stderr, "______________________________________________________________\n");
180 } else if ((dump && sb_disasm) || use_sb) {
181 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
182 dump, use_sb);
183 if (r) {
184 R600_ERR("r600_sb_bytecode_process failed !\n");
185 goto error;
186 }
187 }
188
189 if (shader->gs_copy_shader) {
190 if (dump) {
191 // dump copy shader
192 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
193 &shader->gs_copy_shader->shader, dump, 0);
194 if (r)
195 goto error;
196 }
197
198 if ((r = store_shader(ctx, shader->gs_copy_shader)))
199 goto error;
200 }
201
202 /* Store the shader in a buffer. */
203 if ((r = store_shader(ctx, shader)))
204 goto error;
205
206 /* Build state. */
207 switch (shader->shader.processor_type) {
208 case TGSI_PROCESSOR_GEOMETRY:
209 if (rctx->b.chip_class >= EVERGREEN) {
210 evergreen_update_gs_state(ctx, shader);
211 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
212 } else {
213 r600_update_gs_state(ctx, shader);
214 r600_update_vs_state(ctx, shader->gs_copy_shader);
215 }
216 break;
217 case TGSI_PROCESSOR_VERTEX:
218 if (rctx->b.chip_class >= EVERGREEN) {
219 if (export_shader)
220 evergreen_update_es_state(ctx, shader);
221 else
222 evergreen_update_vs_state(ctx, shader);
223 } else {
224 if (export_shader)
225 r600_update_es_state(ctx, shader);
226 else
227 r600_update_vs_state(ctx, shader);
228 }
229 break;
230 case TGSI_PROCESSOR_FRAGMENT:
231 if (rctx->b.chip_class >= EVERGREEN) {
232 evergreen_update_ps_state(ctx, shader);
233 } else {
234 r600_update_ps_state(ctx, shader);
235 }
236 break;
237 default:
238 r = -EINVAL;
239 goto error;
240 }
241 return 0;
242
243 error:
244 r600_pipe_shader_destroy(ctx, shader);
245 return r;
246 }
247
248 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
249 {
250 pipe_resource_reference((struct pipe_resource**)&shader->bo, NULL);
251 r600_bytecode_clear(&shader->shader.bc);
252 r600_release_command_buffer(&shader->command_buffer);
253 }
254
255 /*
256 * tgsi -> r600 shader
257 */
258 struct r600_shader_tgsi_instruction;
259
260 struct r600_shader_src {
261 unsigned sel;
262 unsigned swizzle[4];
263 unsigned neg;
264 unsigned abs;
265 unsigned rel;
266 unsigned kc_bank;
267 uint32_t value[4];
268 };
269
270 struct r600_shader_ctx {
271 struct tgsi_shader_info info;
272 struct tgsi_parse_context parse;
273 const struct tgsi_token *tokens;
274 unsigned type;
275 unsigned file_offset[TGSI_FILE_COUNT];
276 unsigned temp_reg;
277 struct r600_shader_tgsi_instruction *inst_info;
278 struct r600_bytecode *bc;
279 struct r600_shader *shader;
280 struct r600_shader_src src[4];
281 uint32_t *literals;
282 uint32_t nliterals;
283 uint32_t max_driver_temp_used;
284 boolean use_llvm;
285 /* needed for evergreen interpolation */
286 boolean input_centroid;
287 boolean input_linear;
288 boolean input_perspective;
289 int num_interp_gpr;
290 int face_gpr;
291 int colors_used;
292 boolean clip_vertex_write;
293 unsigned cv_output;
294 unsigned edgeflag_output;
295 int fragcoord_input;
296 int native_integers;
297 int next_ring_offset;
298 int gs_out_ring_offset;
299 int gs_next_vertex;
300 struct r600_shader *gs_for_vs;
301 int gs_export_gpr_treg;
302 };
303
304 struct r600_shader_tgsi_instruction {
305 unsigned tgsi_opcode;
306 unsigned is_op3;
307 unsigned op;
308 int (*process)(struct r600_shader_ctx *ctx);
309 };
310
311 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind);
312 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
313 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
314 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
315 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
316 static int tgsi_else(struct r600_shader_ctx *ctx);
317 static int tgsi_endif(struct r600_shader_ctx *ctx);
318 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
319 static int tgsi_endloop(struct r600_shader_ctx *ctx);
320 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
321
322 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
323 {
324 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
325 int j;
326
327 if (i->Instruction.NumDstRegs > 1) {
328 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
329 return -EINVAL;
330 }
331 if (i->Instruction.Predicate) {
332 R600_ERR("predicate unsupported\n");
333 return -EINVAL;
334 }
335 #if 0
336 if (i->Instruction.Label) {
337 R600_ERR("label unsupported\n");
338 return -EINVAL;
339 }
340 #endif
341 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
342 if (i->Src[j].Register.Dimension) {
343 switch (i->Src[j].Register.File) {
344 case TGSI_FILE_CONSTANT:
345 break;
346 case TGSI_FILE_INPUT:
347 if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
348 break;
349 default:
350 R600_ERR("unsupported src %d (dimension %d)\n", j,
351 i->Src[j].Register.Dimension);
352 return -EINVAL;
353 }
354 }
355 }
356 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
357 if (i->Dst[j].Register.Dimension) {
358 R600_ERR("unsupported dst (dimension)\n");
359 return -EINVAL;
360 }
361 }
362 return 0;
363 }
364
365 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
366 int input)
367 {
368 int ij_index = 0;
369
370 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
371 if (ctx->shader->input[input].centroid)
372 ij_index++;
373 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
374 /* if we have perspective add one */
375 if (ctx->input_perspective) {
376 ij_index++;
377 /* if we have perspective centroid */
378 if (ctx->input_centroid)
379 ij_index++;
380 }
381 if (ctx->shader->input[input].centroid)
382 ij_index++;
383 }
384
385 ctx->shader->input[input].ij_index = ij_index;
386 }
387
388 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
389 {
390 int i, r;
391 struct r600_bytecode_alu alu;
392 int gpr = 0, base_chan = 0;
393 int ij_index = ctx->shader->input[input].ij_index;
394
395 /* work out gpr and base_chan from index */
396 gpr = ij_index / 2;
397 base_chan = (2 * (ij_index % 2)) + 1;
398
399 for (i = 0; i < 8; i++) {
400 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
401
402 if (i < 4)
403 alu.op = ALU_OP2_INTERP_ZW;
404 else
405 alu.op = ALU_OP2_INTERP_XY;
406
407 if ((i > 1) && (i < 6)) {
408 alu.dst.sel = ctx->shader->input[input].gpr;
409 alu.dst.write = 1;
410 }
411
412 alu.dst.chan = i % 4;
413
414 alu.src[0].sel = gpr;
415 alu.src[0].chan = (base_chan - (i % 2));
416
417 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
418
419 alu.bank_swizzle_force = SQ_ALU_VEC_210;
420 if ((i % 4) == 3)
421 alu.last = 1;
422 r = r600_bytecode_add_alu(ctx->bc, &alu);
423 if (r)
424 return r;
425 }
426 return 0;
427 }
428
429 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
430 {
431 int i, r;
432 struct r600_bytecode_alu alu;
433
434 for (i = 0; i < 4; i++) {
435 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
436
437 alu.op = ALU_OP1_INTERP_LOAD_P0;
438
439 alu.dst.sel = ctx->shader->input[input].gpr;
440 alu.dst.write = 1;
441
442 alu.dst.chan = i;
443
444 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
445 alu.src[0].chan = i;
446
447 if (i == 3)
448 alu.last = 1;
449 r = r600_bytecode_add_alu(ctx->bc, &alu);
450 if (r)
451 return r;
452 }
453 return 0;
454 }
455
456 /*
457 * Special export handling in shaders
458 *
459 * shader export ARRAY_BASE for EXPORT_POS:
460 * 60 is position
461 * 61 is misc vector
462 * 62, 63 are clip distance vectors
463 *
464 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
465 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
466 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
467 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
468 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
469 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
470 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
471 * exclusive from render target index)
472 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
473 *
474 *
475 * shader export ARRAY_BASE for EXPORT_PIXEL:
476 * 0-7 CB targets
477 * 61 computed Z vector
478 *
479 * The use of the values exported in the computed Z vector are controlled
480 * by DB_SHADER_CONTROL:
481 * Z_EXPORT_ENABLE - Z as a float in RED
482 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
483 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
484 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
485 * DB_SOURCE_FORMAT - export control restrictions
486 *
487 */
488
489
490 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
491 static int r600_spi_sid(struct r600_shader_io * io)
492 {
493 int index, name = io->name;
494
495 /* These params are handled differently, they don't need
496 * semantic indices, so we'll use 0 for them.
497 */
498 if (name == TGSI_SEMANTIC_POSITION ||
499 name == TGSI_SEMANTIC_PSIZE ||
500 name == TGSI_SEMANTIC_EDGEFLAG ||
501 name == TGSI_SEMANTIC_FACE)
502 index = 0;
503 else {
504 if (name == TGSI_SEMANTIC_GENERIC) {
505 /* For generic params simply use sid from tgsi */
506 index = io->sid;
507 } else {
508 /* For non-generic params - pack name and sid into 8 bits */
509 index = 0x80 | (name<<3) | (io->sid);
510 }
511
512 /* Make sure that all really used indices have nonzero value, so
513 * we can just compare it to 0 later instead of comparing the name
514 * with different values to detect special cases. */
515 index++;
516 }
517
518 return index;
519 };
520
521 /* turn input into interpolate on EG */
522 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
523 {
524 int r = 0;
525
526 if (ctx->shader->input[index].spi_sid) {
527 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
528 if (ctx->shader->input[index].interpolate > 0) {
529 evergreen_interp_assign_ij_index(ctx, index);
530 if (!ctx->use_llvm)
531 r = evergreen_interp_alu(ctx, index);
532 } else {
533 if (!ctx->use_llvm)
534 r = evergreen_interp_flat(ctx, index);
535 }
536 }
537 return r;
538 }
539
540 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
541 {
542 struct r600_bytecode_alu alu;
543 int i, r;
544 int gpr_front = ctx->shader->input[front].gpr;
545 int gpr_back = ctx->shader->input[back].gpr;
546
547 for (i = 0; i < 4; i++) {
548 memset(&alu, 0, sizeof(alu));
549 alu.op = ALU_OP3_CNDGT;
550 alu.is_op3 = 1;
551 alu.dst.write = 1;
552 alu.dst.sel = gpr_front;
553 alu.src[0].sel = ctx->face_gpr;
554 alu.src[1].sel = gpr_front;
555 alu.src[2].sel = gpr_back;
556
557 alu.dst.chan = i;
558 alu.src[1].chan = i;
559 alu.src[2].chan = i;
560 alu.last = (i==3);
561
562 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
563 return r;
564 }
565
566 return 0;
567 }
568
569 static int tgsi_declaration(struct r600_shader_ctx *ctx)
570 {
571 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
572 int r, i, j, count = d->Range.Last - d->Range.First + 1;
573
574 switch (d->Declaration.File) {
575 case TGSI_FILE_INPUT:
576 i = ctx->shader->ninput;
577 assert(i < Elements(ctx->shader->input));
578 ctx->shader->ninput += count;
579 ctx->shader->input[i].name = d->Semantic.Name;
580 ctx->shader->input[i].sid = d->Semantic.Index;
581 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
582 ctx->shader->input[i].centroid = d->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID;
583 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
584 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
585 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
586 switch (ctx->shader->input[i].name) {
587 case TGSI_SEMANTIC_FACE:
588 ctx->face_gpr = ctx->shader->input[i].gpr;
589 break;
590 case TGSI_SEMANTIC_COLOR:
591 ctx->colors_used++;
592 break;
593 case TGSI_SEMANTIC_POSITION:
594 ctx->fragcoord_input = i;
595 break;
596 }
597 if (ctx->bc->chip_class >= EVERGREEN) {
598 if ((r = evergreen_interp_input(ctx, i)))
599 return r;
600 }
601 } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
602 /* FIXME probably skip inputs if they aren't passed in the ring */
603 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
604 ctx->next_ring_offset += 16;
605 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
606 ctx->shader->gs_prim_id_input = true;
607 }
608 for (j = 1; j < count; ++j) {
609 ctx->shader->input[i + j] = ctx->shader->input[i];
610 ctx->shader->input[i + j].gpr += j;
611 }
612 break;
613 case TGSI_FILE_OUTPUT:
614 i = ctx->shader->noutput++;
615 assert(i < Elements(ctx->shader->output));
616 ctx->shader->output[i].name = d->Semantic.Name;
617 ctx->shader->output[i].sid = d->Semantic.Index;
618 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
619 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
620 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
621 if (ctx->type == TGSI_PROCESSOR_VERTEX ||
622 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
623 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
624 switch (d->Semantic.Name) {
625 case TGSI_SEMANTIC_CLIPDIST:
626 ctx->shader->clip_dist_write |= d->Declaration.UsageMask << (d->Semantic.Index << 2);
627 break;
628 case TGSI_SEMANTIC_PSIZE:
629 ctx->shader->vs_out_misc_write = 1;
630 ctx->shader->vs_out_point_size = 1;
631 break;
632 case TGSI_SEMANTIC_EDGEFLAG:
633 ctx->shader->vs_out_misc_write = 1;
634 ctx->shader->vs_out_edgeflag = 1;
635 ctx->edgeflag_output = i;
636 break;
637 case TGSI_SEMANTIC_VIEWPORT_INDEX:
638 ctx->shader->vs_out_misc_write = 1;
639 ctx->shader->vs_out_viewport = 1;
640 break;
641 case TGSI_SEMANTIC_LAYER:
642 ctx->shader->vs_out_misc_write = 1;
643 ctx->shader->vs_out_layer = 1;
644 break;
645 case TGSI_SEMANTIC_CLIPVERTEX:
646 ctx->clip_vertex_write = TRUE;
647 ctx->cv_output = i;
648 break;
649 }
650 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
651 ctx->gs_out_ring_offset += 16;
652 }
653 } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
654 switch (d->Semantic.Name) {
655 case TGSI_SEMANTIC_COLOR:
656 ctx->shader->nr_ps_max_color_exports++;
657 break;
658 }
659 }
660 break;
661 case TGSI_FILE_TEMPORARY:
662 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
663 if (d->Array.ArrayID) {
664 r600_add_gpr_array(ctx->shader,
665 ctx->file_offset[TGSI_FILE_TEMPORARY] +
666 d->Range.First,
667 d->Range.Last - d->Range.First + 1, 0x0F);
668 }
669 }
670 break;
671
672 case TGSI_FILE_CONSTANT:
673 case TGSI_FILE_SAMPLER:
674 case TGSI_FILE_ADDRESS:
675 break;
676
677 case TGSI_FILE_SYSTEM_VALUE:
678 if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
679 if (!ctx->native_integers) {
680 struct r600_bytecode_alu alu;
681 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
682
683 alu.op = ALU_OP1_INT_TO_FLT;
684 alu.src[0].sel = 0;
685 alu.src[0].chan = 3;
686
687 alu.dst.sel = 0;
688 alu.dst.chan = 3;
689 alu.dst.write = 1;
690 alu.last = 1;
691
692 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
693 return r;
694 }
695 break;
696 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
697 break;
698 default:
699 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
700 return -EINVAL;
701 }
702 return 0;
703 }
704
705 static int r600_get_temp(struct r600_shader_ctx *ctx)
706 {
707 return ctx->temp_reg + ctx->max_driver_temp_used++;
708 }
709
710 /*
711 * for evergreen we need to scan the shader to find the number of GPRs we need to
712 * reserve for interpolation.
713 *
714 * we need to know if we are going to emit
715 * any centroid inputs
716 * if perspective and linear are required
717 */
718 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
719 {
720 int i;
721 int num_baryc;
722
723 ctx->input_linear = FALSE;
724 ctx->input_perspective = FALSE;
725 ctx->input_centroid = FALSE;
726 ctx->num_interp_gpr = 1;
727
728 /* any centroid inputs */
729 for (i = 0; i < ctx->info.num_inputs; i++) {
730 /* skip position/face */
731 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
732 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
733 continue;
734 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
735 ctx->input_linear = TRUE;
736 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
737 ctx->input_perspective = TRUE;
738 if (ctx->info.input_interpolate_loc[i] == TGSI_INTERPOLATE_LOC_CENTROID)
739 ctx->input_centroid = TRUE;
740 }
741
742 num_baryc = 0;
743 /* ignoring sample for now */
744 if (ctx->input_perspective)
745 num_baryc++;
746 if (ctx->input_linear)
747 num_baryc++;
748 if (ctx->input_centroid)
749 num_baryc *= 2;
750
751 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
752
753 /* XXX PULL MODEL and LINE STIPPLE, FIXED PT POS */
754 return ctx->num_interp_gpr;
755 }
756
757 static void tgsi_src(struct r600_shader_ctx *ctx,
758 const struct tgsi_full_src_register *tgsi_src,
759 struct r600_shader_src *r600_src)
760 {
761 memset(r600_src, 0, sizeof(*r600_src));
762 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
763 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
764 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
765 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
766 r600_src->neg = tgsi_src->Register.Negate;
767 r600_src->abs = tgsi_src->Register.Absolute;
768
769 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
770 int index;
771 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
772 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
773 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
774
775 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
776 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
777 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
778 return;
779 }
780 index = tgsi_src->Register.Index;
781 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
782 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
783 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
784 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
785 r600_src->swizzle[0] = 3;
786 r600_src->swizzle[1] = 3;
787 r600_src->swizzle[2] = 3;
788 r600_src->swizzle[3] = 3;
789 r600_src->sel = 0;
790 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
791 r600_src->swizzle[0] = 0;
792 r600_src->swizzle[1] = 0;
793 r600_src->swizzle[2] = 0;
794 r600_src->swizzle[3] = 0;
795 r600_src->sel = 0;
796 }
797 } else {
798 if (tgsi_src->Register.Indirect)
799 r600_src->rel = V_SQ_REL_RELATIVE;
800 r600_src->sel = tgsi_src->Register.Index;
801 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
802 }
803 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
804 if (tgsi_src->Register.Dimension) {
805 r600_src->kc_bank = tgsi_src->Dimension.Index;
806 }
807 }
808 }
809
810 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
811 unsigned int cb_idx, unsigned int offset, unsigned ar_chan,
812 unsigned int dst_reg)
813 {
814 struct r600_bytecode_vtx vtx;
815 unsigned int ar_reg;
816 int r;
817
818 if (offset) {
819 struct r600_bytecode_alu alu;
820
821 memset(&alu, 0, sizeof(alu));
822
823 alu.op = ALU_OP2_ADD_INT;
824 alu.src[0].sel = ctx->bc->ar_reg;
825 alu.src[0].chan = ar_chan;
826
827 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
828 alu.src[1].value = offset;
829
830 alu.dst.sel = dst_reg;
831 alu.dst.chan = ar_chan;
832 alu.dst.write = 1;
833 alu.last = 1;
834
835 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
836 return r;
837
838 ar_reg = dst_reg;
839 } else {
840 ar_reg = ctx->bc->ar_reg;
841 }
842
843 memset(&vtx, 0, sizeof(vtx));
844 vtx.buffer_id = cb_idx;
845 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
846 vtx.src_gpr = ar_reg;
847 vtx.src_sel_x = ar_chan;
848 vtx.mega_fetch_count = 16;
849 vtx.dst_gpr = dst_reg;
850 vtx.dst_sel_x = 0; /* SEL_X */
851 vtx.dst_sel_y = 1; /* SEL_Y */
852 vtx.dst_sel_z = 2; /* SEL_Z */
853 vtx.dst_sel_w = 3; /* SEL_W */
854 vtx.data_format = FMT_32_32_32_32_FLOAT;
855 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
856 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
857 vtx.endian = r600_endian_swap(32);
858
859 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
860 return r;
861
862 return 0;
863 }
864
865 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
866 {
867 struct r600_bytecode_vtx vtx;
868 int r;
869 unsigned index = src->Register.Index;
870 unsigned vtx_id = src->Dimension.Index;
871 int offset_reg = vtx_id / 3;
872 int offset_chan = vtx_id % 3;
873
874 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
875 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
876
877 if (offset_reg == 0 && offset_chan == 2)
878 offset_chan = 3;
879
880 if (src->Dimension.Indirect) {
881 int treg[3];
882 int t2;
883 struct r600_bytecode_alu alu;
884 int r, i;
885
886 /* you have got to be shitting me -
887 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
888 at least this is what fglrx seems to do. */
889 for (i = 0; i < 3; i++) {
890 treg[i] = r600_get_temp(ctx);
891 }
892 t2 = r600_get_temp(ctx);
893 for (i = 0; i < 3; i++) {
894 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
895 alu.op = ALU_OP1_MOV;
896 alu.src[0].sel = 0;
897 alu.src[0].chan = i == 2 ? 3 : i;
898 alu.dst.sel = treg[i];
899 alu.dst.chan = 0;
900 alu.dst.write = 1;
901 alu.last = 1;
902 r = r600_bytecode_add_alu(ctx->bc, &alu);
903 if (r)
904 return r;
905 }
906 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
907 alu.op = ALU_OP1_MOV;
908 alu.src[0].sel = treg[0];
909 alu.src[0].rel = 1;
910 alu.dst.sel = t2;
911 alu.dst.write = 1;
912 alu.last = 1;
913 r = r600_bytecode_add_alu(ctx->bc, &alu);
914 if (r)
915 return r;
916 offset_reg = t2;
917 }
918
919
920 memset(&vtx, 0, sizeof(vtx));
921 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
922 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
923 vtx.src_gpr = offset_reg;
924 vtx.src_sel_x = offset_chan;
925 vtx.offset = index * 16; /*bytes*/
926 vtx.mega_fetch_count = 16;
927 vtx.dst_gpr = dst_reg;
928 vtx.dst_sel_x = 0; /* SEL_X */
929 vtx.dst_sel_y = 1; /* SEL_Y */
930 vtx.dst_sel_z = 2; /* SEL_Z */
931 vtx.dst_sel_w = 3; /* SEL_W */
932 if (ctx->bc->chip_class >= EVERGREEN) {
933 vtx.use_const_fields = 1;
934 } else {
935 vtx.data_format = FMT_32_32_32_32_FLOAT;
936 }
937
938 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
939 return r;
940
941 return 0;
942 }
943
944 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
945 {
946 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
947 int i;
948
949 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
950 struct tgsi_full_src_register *src = &inst->Src[i];
951
952 if (src->Register.File == TGSI_FILE_INPUT) {
953 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
954 /* primitive id is in R0.z */
955 ctx->src[i].sel = 0;
956 ctx->src[i].swizzle[0] = 2;
957 }
958 }
959 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
960 int treg = r600_get_temp(ctx);
961
962 fetch_gs_input(ctx, src, treg);
963 ctx->src[i].sel = treg;
964 }
965 }
966 return 0;
967 }
968
969 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
970 {
971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
972 struct r600_bytecode_alu alu;
973 int i, j, k, nconst, r;
974
975 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
976 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
977 nconst++;
978 }
979 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
980 }
981 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
982 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
983 continue;
984 }
985
986 if (ctx->src[i].rel) {
987 int chan = inst->Src[i].Indirect.Swizzle;
988 int treg = r600_get_temp(ctx);
989 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].sel - 512, chan, treg)))
990 return r;
991
992 ctx->src[i].kc_bank = 0;
993 ctx->src[i].sel = treg;
994 ctx->src[i].rel = 0;
995 j--;
996 } else if (j > 0) {
997 int treg = r600_get_temp(ctx);
998 for (k = 0; k < 4; k++) {
999 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1000 alu.op = ALU_OP1_MOV;
1001 alu.src[0].sel = ctx->src[i].sel;
1002 alu.src[0].chan = k;
1003 alu.src[0].rel = ctx->src[i].rel;
1004 alu.dst.sel = treg;
1005 alu.dst.chan = k;
1006 alu.dst.write = 1;
1007 if (k == 3)
1008 alu.last = 1;
1009 r = r600_bytecode_add_alu(ctx->bc, &alu);
1010 if (r)
1011 return r;
1012 }
1013 ctx->src[i].sel = treg;
1014 ctx->src[i].rel =0;
1015 j--;
1016 }
1017 }
1018 return 0;
1019 }
1020
1021 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
1022 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
1023 {
1024 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1025 struct r600_bytecode_alu alu;
1026 int i, j, k, nliteral, r;
1027
1028 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
1029 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1030 nliteral++;
1031 }
1032 }
1033 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
1034 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
1035 int treg = r600_get_temp(ctx);
1036 for (k = 0; k < 4; k++) {
1037 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1038 alu.op = ALU_OP1_MOV;
1039 alu.src[0].sel = ctx->src[i].sel;
1040 alu.src[0].chan = k;
1041 alu.src[0].value = ctx->src[i].value[k];
1042 alu.dst.sel = treg;
1043 alu.dst.chan = k;
1044 alu.dst.write = 1;
1045 if (k == 3)
1046 alu.last = 1;
1047 r = r600_bytecode_add_alu(ctx->bc, &alu);
1048 if (r)
1049 return r;
1050 }
1051 ctx->src[i].sel = treg;
1052 j--;
1053 }
1054 }
1055 return 0;
1056 }
1057
1058 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
1059 {
1060 int i, r, count = ctx->shader->ninput;
1061
1062 for (i = 0; i < count; i++) {
1063 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1064 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
1065 if (r)
1066 return r;
1067 }
1068 }
1069 return 0;
1070 }
1071
1072 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so)
1073 {
1074 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
1075 int i, j, r;
1076
1077 /* Sanity checking. */
1078 if (so->num_outputs > PIPE_MAX_SHADER_OUTPUTS) {
1079 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
1080 r = -EINVAL;
1081 goto out_err;
1082 }
1083 for (i = 0; i < so->num_outputs; i++) {
1084 if (so->output[i].output_buffer >= 4) {
1085 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
1086 so->output[i].output_buffer);
1087 r = -EINVAL;
1088 goto out_err;
1089 }
1090 }
1091
1092 /* Initialize locations where the outputs are stored. */
1093 for (i = 0; i < so->num_outputs; i++) {
1094 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
1095
1096 /* Lower outputs with dst_offset < start_component.
1097 *
1098 * We can only output 4D vectors with a write mask, e.g. we can
1099 * only output the W component at offset 3, etc. If we want
1100 * to store Y, Z, or W at buffer offset 0, we need to use MOV
1101 * to move it to X and output X. */
1102 if (so->output[i].dst_offset < so->output[i].start_component) {
1103 unsigned tmp = r600_get_temp(ctx);
1104
1105 for (j = 0; j < so->output[i].num_components; j++) {
1106 struct r600_bytecode_alu alu;
1107 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1108 alu.op = ALU_OP1_MOV;
1109 alu.src[0].sel = so_gpr[i];
1110 alu.src[0].chan = so->output[i].start_component + j;
1111
1112 alu.dst.sel = tmp;
1113 alu.dst.chan = j;
1114 alu.dst.write = 1;
1115 if (j == so->output[i].num_components - 1)
1116 alu.last = 1;
1117 r = r600_bytecode_add_alu(ctx->bc, &alu);
1118 if (r)
1119 return r;
1120 }
1121 so->output[i].start_component = 0;
1122 so_gpr[i] = tmp;
1123 }
1124 }
1125
1126 /* Write outputs to buffers. */
1127 for (i = 0; i < so->num_outputs; i++) {
1128 struct r600_bytecode_output output;
1129
1130 memset(&output, 0, sizeof(struct r600_bytecode_output));
1131 output.gpr = so_gpr[i];
1132 output.elem_size = so->output[i].num_components;
1133 output.array_base = so->output[i].dst_offset - so->output[i].start_component;
1134 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1135 output.burst_count = 1;
1136 /* array_size is an upper limit for the burst_count
1137 * with MEM_STREAM instructions */
1138 output.array_size = 0xFFF;
1139 output.comp_mask = ((1 << so->output[i].num_components) - 1) << so->output[i].start_component;
1140 if (ctx->bc->chip_class >= EVERGREEN) {
1141 switch (so->output[i].output_buffer) {
1142 case 0:
1143 output.op = CF_OP_MEM_STREAM0_BUF0;
1144 break;
1145 case 1:
1146 output.op = CF_OP_MEM_STREAM0_BUF1;
1147 break;
1148 case 2:
1149 output.op = CF_OP_MEM_STREAM0_BUF2;
1150 break;
1151 case 3:
1152 output.op = CF_OP_MEM_STREAM0_BUF3;
1153 break;
1154 }
1155 } else {
1156 switch (so->output[i].output_buffer) {
1157 case 0:
1158 output.op = CF_OP_MEM_STREAM0;
1159 break;
1160 case 1:
1161 output.op = CF_OP_MEM_STREAM1;
1162 break;
1163 case 2:
1164 output.op = CF_OP_MEM_STREAM2;
1165 break;
1166 case 3:
1167 output.op = CF_OP_MEM_STREAM3;
1168 break;
1169 }
1170 }
1171 r = r600_bytecode_add_output(ctx->bc, &output);
1172 if (r)
1173 goto out_err;
1174 }
1175 return 0;
1176 out_err:
1177 return r;
1178 }
1179
1180 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
1181 {
1182 struct r600_bytecode_alu alu;
1183 unsigned reg;
1184
1185 if (!ctx->shader->vs_out_edgeflag)
1186 return;
1187
1188 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
1189
1190 /* clamp(x, 0, 1) */
1191 memset(&alu, 0, sizeof(alu));
1192 alu.op = ALU_OP1_MOV;
1193 alu.src[0].sel = reg;
1194 alu.dst.sel = reg;
1195 alu.dst.write = 1;
1196 alu.dst.clamp = 1;
1197 alu.last = 1;
1198 r600_bytecode_add_alu(ctx->bc, &alu);
1199
1200 memset(&alu, 0, sizeof(alu));
1201 alu.op = ALU_OP1_FLT_TO_INT;
1202 alu.src[0].sel = reg;
1203 alu.dst.sel = reg;
1204 alu.dst.write = 1;
1205 alu.last = 1;
1206 r600_bytecode_add_alu(ctx->bc, &alu);
1207 }
1208
1209 static int generate_gs_copy_shader(struct r600_context *rctx,
1210 struct r600_pipe_shader *gs,
1211 struct pipe_stream_output_info *so)
1212 {
1213 struct r600_shader_ctx ctx = {};
1214 struct r600_shader *gs_shader = &gs->shader;
1215 struct r600_pipe_shader *cshader;
1216 int ocnt = gs_shader->noutput;
1217 struct r600_bytecode_alu alu;
1218 struct r600_bytecode_vtx vtx;
1219 struct r600_bytecode_output output;
1220 struct r600_bytecode_cf *cf_jump, *cf_pop,
1221 *last_exp_pos = NULL, *last_exp_param = NULL;
1222 int i, next_clip_pos = 61, next_param = 0;
1223
1224 cshader = calloc(1, sizeof(struct r600_pipe_shader));
1225 if (!cshader)
1226 return 0;
1227
1228 memcpy(cshader->shader.output, gs_shader->output, ocnt *
1229 sizeof(struct r600_shader_io));
1230
1231 cshader->shader.noutput = ocnt;
1232
1233 ctx.shader = &cshader->shader;
1234 ctx.bc = &ctx.shader->bc;
1235 ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX;
1236
1237 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
1238 rctx->screen->has_compressed_msaa_texturing);
1239
1240 ctx.bc->isa = rctx->isa;
1241
1242 /* R0.x = R0.x & 0x3fffffff */
1243 memset(&alu, 0, sizeof(alu));
1244 alu.op = ALU_OP2_AND_INT;
1245 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1246 alu.src[1].value = 0x3fffffff;
1247 alu.dst.write = 1;
1248 r600_bytecode_add_alu(ctx.bc, &alu);
1249
1250 /* R0.y = R0.x >> 30 */
1251 memset(&alu, 0, sizeof(alu));
1252 alu.op = ALU_OP2_LSHR_INT;
1253 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1254 alu.src[1].value = 0x1e;
1255 alu.dst.chan = 1;
1256 alu.dst.write = 1;
1257 alu.last = 1;
1258 r600_bytecode_add_alu(ctx.bc, &alu);
1259
1260 /* PRED_SETE_INT __, R0.y, 0 */
1261 memset(&alu, 0, sizeof(alu));
1262 alu.op = ALU_OP2_PRED_SETE_INT;
1263 alu.src[0].chan = 1;
1264 alu.src[1].sel = V_SQ_ALU_SRC_0;
1265 alu.execute_mask = 1;
1266 alu.update_pred = 1;
1267 alu.last = 1;
1268 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
1269
1270 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
1271 cf_jump = ctx.bc->cf_last;
1272
1273 /* fetch vertex data from GSVS ring */
1274 for (i = 0; i < ocnt; ++i) {
1275 struct r600_shader_io *out = &ctx.shader->output[i];
1276 out->gpr = i + 1;
1277 out->ring_offset = i * 16;
1278
1279 memset(&vtx, 0, sizeof(vtx));
1280 vtx.op = FETCH_OP_VFETCH;
1281 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1282 vtx.fetch_type = 2;
1283 vtx.offset = out->ring_offset;
1284 vtx.dst_gpr = out->gpr;
1285 vtx.dst_sel_x = 0;
1286 vtx.dst_sel_y = 1;
1287 vtx.dst_sel_z = 2;
1288 vtx.dst_sel_w = 3;
1289 if (rctx->b.chip_class >= EVERGREEN) {
1290 vtx.use_const_fields = 1;
1291 } else {
1292 vtx.data_format = FMT_32_32_32_32_FLOAT;
1293 }
1294
1295 r600_bytecode_add_vtx(ctx.bc, &vtx);
1296 }
1297
1298 /* XXX handle clipvertex, streamout? */
1299 emit_streamout(&ctx, so);
1300
1301 /* export vertex data */
1302 /* XXX factor out common code with r600_shader_from_tgsi ? */
1303 for (i = 0; i < ocnt; ++i) {
1304 struct r600_shader_io *out = &ctx.shader->output[i];
1305
1306 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
1307 continue;
1308
1309 memset(&output, 0, sizeof(output));
1310 output.gpr = out->gpr;
1311 output.elem_size = 3;
1312 output.swizzle_x = 0;
1313 output.swizzle_y = 1;
1314 output.swizzle_z = 2;
1315 output.swizzle_w = 3;
1316 output.burst_count = 1;
1317 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1318 output.op = CF_OP_EXPORT;
1319 switch (out->name) {
1320 case TGSI_SEMANTIC_POSITION:
1321 output.array_base = 60;
1322 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1323 break;
1324
1325 case TGSI_SEMANTIC_PSIZE:
1326 output.array_base = 61;
1327 if (next_clip_pos == 61)
1328 next_clip_pos = 62;
1329 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1330 output.swizzle_y = 7;
1331 output.swizzle_z = 7;
1332 output.swizzle_w = 7;
1333 ctx.shader->vs_out_misc_write = 1;
1334 ctx.shader->vs_out_point_size = 1;
1335 break;
1336 case TGSI_SEMANTIC_LAYER:
1337 if (out->spi_sid) {
1338 /* duplicate it as PARAM to pass to the pixel shader */
1339 output.array_base = next_param++;
1340 r600_bytecode_add_output(ctx.bc, &output);
1341 last_exp_param = ctx.bc->cf_last;
1342 }
1343 output.array_base = 61;
1344 if (next_clip_pos == 61)
1345 next_clip_pos = 62;
1346 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1347 output.swizzle_x = 7;
1348 output.swizzle_y = 7;
1349 output.swizzle_z = 0;
1350 output.swizzle_w = 7;
1351 ctx.shader->vs_out_misc_write = 1;
1352 ctx.shader->vs_out_layer = 1;
1353 break;
1354 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1355 if (out->spi_sid) {
1356 /* duplicate it as PARAM to pass to the pixel shader */
1357 output.array_base = next_param++;
1358 r600_bytecode_add_output(ctx.bc, &output);
1359 last_exp_param = ctx.bc->cf_last;
1360 }
1361 output.array_base = 61;
1362 if (next_clip_pos == 61)
1363 next_clip_pos = 62;
1364 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1365 ctx.shader->vs_out_misc_write = 1;
1366 ctx.shader->vs_out_viewport = 1;
1367 output.swizzle_x = 7;
1368 output.swizzle_y = 7;
1369 output.swizzle_z = 7;
1370 output.swizzle_w = 0;
1371 break;
1372 case TGSI_SEMANTIC_CLIPDIST:
1373 /* spi_sid is 0 for clipdistance outputs that were generated
1374 * for clipvertex - we don't need to pass them to PS */
1375 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
1376 if (out->spi_sid) {
1377 /* duplicate it as PARAM to pass to the pixel shader */
1378 output.array_base = next_param++;
1379 r600_bytecode_add_output(ctx.bc, &output);
1380 last_exp_param = ctx.bc->cf_last;
1381 }
1382 output.array_base = next_clip_pos++;
1383 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1384 break;
1385 case TGSI_SEMANTIC_FOG:
1386 output.swizzle_y = 4; /* 0 */
1387 output.swizzle_z = 4; /* 0 */
1388 output.swizzle_w = 5; /* 1 */
1389 break;
1390 default:
1391 output.array_base = next_param++;
1392 break;
1393 }
1394 r600_bytecode_add_output(ctx.bc, &output);
1395 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
1396 last_exp_param = ctx.bc->cf_last;
1397 else
1398 last_exp_pos = ctx.bc->cf_last;
1399 }
1400
1401 if (!last_exp_pos) {
1402 memset(&output, 0, sizeof(output));
1403 output.gpr = 0;
1404 output.elem_size = 3;
1405 output.swizzle_x = 7;
1406 output.swizzle_y = 7;
1407 output.swizzle_z = 7;
1408 output.swizzle_w = 7;
1409 output.burst_count = 1;
1410 output.type = 2;
1411 output.op = CF_OP_EXPORT;
1412 output.array_base = 60;
1413 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
1414 r600_bytecode_add_output(ctx.bc, &output);
1415 last_exp_pos = ctx.bc->cf_last;
1416 }
1417
1418 if (!last_exp_param) {
1419 memset(&output, 0, sizeof(output));
1420 output.gpr = 0;
1421 output.elem_size = 3;
1422 output.swizzle_x = 7;
1423 output.swizzle_y = 7;
1424 output.swizzle_z = 7;
1425 output.swizzle_w = 7;
1426 output.burst_count = 1;
1427 output.type = 2;
1428 output.op = CF_OP_EXPORT;
1429 output.array_base = next_param++;
1430 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
1431 r600_bytecode_add_output(ctx.bc, &output);
1432 last_exp_param = ctx.bc->cf_last;
1433 }
1434
1435 last_exp_pos->op = CF_OP_EXPORT_DONE;
1436 last_exp_param->op = CF_OP_EXPORT_DONE;
1437
1438 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
1439 cf_pop = ctx.bc->cf_last;
1440
1441 cf_jump->cf_addr = cf_pop->id + 2;
1442 cf_jump->pop_count = 1;
1443 cf_pop->cf_addr = cf_pop->id + 2;
1444 cf_pop->pop_count = 1;
1445
1446 if (ctx.bc->chip_class == CAYMAN)
1447 cm_bytecode_add_cf_end(ctx.bc);
1448 else {
1449 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
1450 ctx.bc->cf_last->end_of_program = 1;
1451 }
1452
1453 gs->gs_copy_shader = cshader;
1454
1455 ctx.bc->nstack = 1;
1456 cshader->shader.ring_item_size = ocnt * 16;
1457
1458 return r600_bytecode_build(ctx.bc);
1459 }
1460
1461 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, bool ind)
1462 {
1463 struct r600_bytecode_output output;
1464 int i, k, ring_offset;
1465
1466 for (i = 0; i < ctx->shader->noutput; i++) {
1467 if (ctx->gs_for_vs) {
1468 /* for ES we need to lookup corresponding ring offset expected by GS
1469 * (map this output to GS input by name and sid) */
1470 /* FIXME precompute offsets */
1471 ring_offset = -1;
1472 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
1473 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
1474 struct r600_shader_io *out = &ctx->shader->output[i];
1475 if (in->name == out->name && in->sid == out->sid)
1476 ring_offset = in->ring_offset;
1477 }
1478
1479 if (ring_offset == -1)
1480 continue;
1481 } else
1482 ring_offset = i * 16;
1483
1484 /* next_ring_offset after parsing input decls contains total size of
1485 * single vertex data, gs_next_vertex - current vertex index */
1486 if (!ind)
1487 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
1488
1489 /* get a temp and add the ring offset to the next vertex base in the shader */
1490 memset(&output, 0, sizeof(struct r600_bytecode_output));
1491 output.gpr = ctx->shader->output[i].gpr;
1492 output.elem_size = 3;
1493 output.comp_mask = 0xF;
1494 output.burst_count = 1;
1495
1496 if (ind)
1497 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
1498 else
1499 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
1500 output.op = CF_OP_MEM_RING;
1501
1502
1503 if (ind) {
1504 output.array_base = ring_offset >> 2; /* in dwords */
1505 output.array_size = 0xfff;
1506 output.index_gpr = ctx->gs_export_gpr_treg;
1507 } else
1508 output.array_base = ring_offset >> 2; /* in dwords */
1509 r600_bytecode_add_output(ctx->bc, &output);
1510 }
1511
1512 if (ind) {
1513 struct r600_bytecode_alu alu;
1514 int r;
1515
1516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1517 alu.op = ALU_OP2_ADD_INT;
1518 alu.src[0].sel = ctx->gs_export_gpr_treg;
1519 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1520 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
1521 alu.dst.sel = ctx->gs_export_gpr_treg;
1522 alu.dst.write = 1;
1523 alu.last = 1;
1524 r = r600_bytecode_add_alu(ctx->bc, &alu);
1525 if (r)
1526 return r;
1527 }
1528 ++ctx->gs_next_vertex;
1529 return 0;
1530 }
1531
1532 static int r600_shader_from_tgsi(struct r600_context *rctx,
1533 struct r600_pipe_shader *pipeshader,
1534 struct r600_shader_key key)
1535 {
1536 struct r600_screen *rscreen = rctx->screen;
1537 struct r600_shader *shader = &pipeshader->shader;
1538 struct tgsi_token *tokens = pipeshader->selector->tokens;
1539 struct pipe_stream_output_info so = pipeshader->selector->so;
1540 struct tgsi_full_immediate *immediate;
1541 struct tgsi_full_property *property;
1542 struct r600_shader_ctx ctx;
1543 struct r600_bytecode_output output[32];
1544 unsigned output_done, noutput;
1545 unsigned opcode;
1546 int i, j, k, r = 0;
1547 int next_param_base = 0, next_clip_base;
1548 int max_color_exports = MAX2(key.nr_cbufs, 1);
1549 /* Declarations used by llvm code */
1550 bool use_llvm = false;
1551 bool indirect_gprs;
1552 bool ring_outputs = false;
1553 bool pos_emitted = false;
1554
1555 #ifdef R600_USE_LLVM
1556 use_llvm = rscreen->b.debug_flags & DBG_LLVM;
1557 #endif
1558 ctx.bc = &shader->bc;
1559 ctx.shader = shader;
1560 ctx.native_integers = true;
1561
1562 shader->vs_as_es = key.vs_as_es;
1563
1564 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
1565 rscreen->has_compressed_msaa_texturing);
1566 ctx.tokens = tokens;
1567 tgsi_scan_shader(tokens, &ctx.info);
1568 shader->indirect_files = ctx.info.indirect_files;
1569 indirect_gprs = ctx.info.indirect_files & ~(1 << TGSI_FILE_CONSTANT);
1570 tgsi_parse_init(&ctx.parse, tokens);
1571 ctx.type = ctx.parse.FullHeader.Processor.Processor;
1572 shader->processor_type = ctx.type;
1573 ctx.bc->type = shader->processor_type;
1574
1575 ring_outputs = key.vs_as_es || (ctx.type == TGSI_PROCESSOR_GEOMETRY);
1576
1577 if (key.vs_as_es) {
1578 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
1579 } else {
1580 ctx.gs_for_vs = NULL;
1581 }
1582
1583 ctx.next_ring_offset = 0;
1584 ctx.gs_out_ring_offset = 0;
1585 ctx.gs_next_vertex = 0;
1586
1587 ctx.face_gpr = -1;
1588 ctx.fragcoord_input = -1;
1589 ctx.colors_used = 0;
1590 ctx.clip_vertex_write = 0;
1591
1592 shader->nr_ps_color_exports = 0;
1593 shader->nr_ps_max_color_exports = 0;
1594
1595 shader->two_side = key.color_two_side;
1596
1597 /* register allocations */
1598 /* Values [0,127] correspond to GPR[0..127].
1599 * Values [128,159] correspond to constant buffer bank 0
1600 * Values [160,191] correspond to constant buffer bank 1
1601 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
1602 * Values [256,287] correspond to constant buffer bank 2 (EG)
1603 * Values [288,319] correspond to constant buffer bank 3 (EG)
1604 * Other special values are shown in the list below.
1605 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
1606 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
1607 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
1608 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
1609 * 248 SQ_ALU_SRC_0: special constant 0.0.
1610 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
1611 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
1612 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
1613 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
1614 * 253 SQ_ALU_SRC_LITERAL: literal constant.
1615 * 254 SQ_ALU_SRC_PV: previous vector result.
1616 * 255 SQ_ALU_SRC_PS: previous scalar result.
1617 */
1618 for (i = 0; i < TGSI_FILE_COUNT; i++) {
1619 ctx.file_offset[i] = 0;
1620 }
1621
1622 #ifdef R600_USE_LLVM
1623 if (use_llvm && ctx.info.indirect_files && (ctx.info.indirect_files & (1 << TGSI_FILE_CONSTANT)) != ctx.info.indirect_files) {
1624 fprintf(stderr, "Warning: R600 LLVM backend does not support "
1625 "indirect adressing. Falling back to TGSI "
1626 "backend.\n");
1627 use_llvm = 0;
1628 }
1629 #endif
1630 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
1631 ctx.file_offset[TGSI_FILE_INPUT] = 1;
1632 if (!use_llvm) {
1633 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
1634 }
1635 }
1636 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
1637 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
1638 }
1639 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1640 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
1641 ctx.file_offset[TGSI_FILE_INPUT] = 2;
1642 }
1643 ctx.use_llvm = use_llvm;
1644
1645 if (use_llvm) {
1646 ctx.file_offset[TGSI_FILE_OUTPUT] =
1647 ctx.file_offset[TGSI_FILE_INPUT];
1648 } else {
1649 ctx.file_offset[TGSI_FILE_OUTPUT] =
1650 ctx.file_offset[TGSI_FILE_INPUT] +
1651 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1652 }
1653 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
1654 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
1655
1656 /* Outside the GPR range. This will be translated to one of the
1657 * kcache banks later. */
1658 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
1659
1660 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
1661 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
1662 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
1663 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1664 ctx.gs_export_gpr_treg = ctx.bc->ar_reg + 1;
1665 ctx.temp_reg = ctx.bc->ar_reg + 2;
1666 } else
1667 ctx.temp_reg = ctx.bc->ar_reg + 1;
1668
1669 if (indirect_gprs) {
1670 shader->max_arrays = 0;
1671 shader->num_arrays = 0;
1672
1673 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
1674 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
1675 ctx.file_offset[TGSI_FILE_OUTPUT] -
1676 ctx.file_offset[TGSI_FILE_INPUT],
1677 0x0F);
1678 }
1679 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
1680 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
1681 ctx.file_offset[TGSI_FILE_TEMPORARY] -
1682 ctx.file_offset[TGSI_FILE_OUTPUT],
1683 0x0F);
1684 }
1685 }
1686
1687 ctx.nliterals = 0;
1688 ctx.literals = NULL;
1689 shader->fs_write_all = FALSE;
1690 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1691 tgsi_parse_token(&ctx.parse);
1692 switch (ctx.parse.FullToken.Token.Type) {
1693 case TGSI_TOKEN_TYPE_IMMEDIATE:
1694 immediate = &ctx.parse.FullToken.FullImmediate;
1695 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
1696 if(ctx.literals == NULL) {
1697 r = -ENOMEM;
1698 goto out_err;
1699 }
1700 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
1701 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
1702 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
1703 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
1704 ctx.nliterals++;
1705 break;
1706 case TGSI_TOKEN_TYPE_DECLARATION:
1707 r = tgsi_declaration(&ctx);
1708 if (r)
1709 goto out_err;
1710 break;
1711 case TGSI_TOKEN_TYPE_INSTRUCTION:
1712 break;
1713 case TGSI_TOKEN_TYPE_PROPERTY:
1714 property = &ctx.parse.FullToken.FullProperty;
1715 switch (property->Property.PropertyName) {
1716 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
1717 if (property->u[0].Data == 1)
1718 shader->fs_write_all = TRUE;
1719 break;
1720 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
1721 if (property->u[0].Data == 1)
1722 shader->vs_position_window_space = TRUE;
1723 break;
1724 case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
1725 /* we don't need this one */
1726 break;
1727 case TGSI_PROPERTY_GS_INPUT_PRIM:
1728 shader->gs_input_prim = property->u[0].Data;
1729 break;
1730 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1731 shader->gs_output_prim = property->u[0].Data;
1732 break;
1733 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1734 shader->gs_max_out_vertices = property->u[0].Data;
1735 break;
1736 }
1737 break;
1738 default:
1739 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
1740 r = -EINVAL;
1741 goto out_err;
1742 }
1743 }
1744
1745 shader->ring_item_size = ctx.next_ring_offset;
1746
1747 /* Process two side if needed */
1748 if (shader->two_side && ctx.colors_used) {
1749 int i, count = ctx.shader->ninput;
1750 unsigned next_lds_loc = ctx.shader->nlds;
1751
1752 /* additional inputs will be allocated right after the existing inputs,
1753 * we won't need them after the color selection, so we don't need to
1754 * reserve these gprs for the rest of the shader code and to adjust
1755 * output offsets etc. */
1756 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
1757 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
1758
1759 if (ctx.face_gpr == -1) {
1760 i = ctx.shader->ninput++;
1761 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
1762 ctx.shader->input[i].spi_sid = 0;
1763 ctx.shader->input[i].gpr = gpr++;
1764 ctx.face_gpr = ctx.shader->input[i].gpr;
1765 }
1766
1767 for (i = 0; i < count; i++) {
1768 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
1769 int ni = ctx.shader->ninput++;
1770 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
1771 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
1772 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
1773 ctx.shader->input[ni].gpr = gpr++;
1774 // TGSI to LLVM needs to know the lds position of inputs.
1775 // Non LLVM path computes it later (in process_twoside_color)
1776 ctx.shader->input[ni].lds_pos = next_lds_loc++;
1777 ctx.shader->input[i].back_color_input = ni;
1778 if (ctx.bc->chip_class >= EVERGREEN) {
1779 if ((r = evergreen_interp_input(&ctx, ni)))
1780 return r;
1781 }
1782 }
1783 }
1784 }
1785
1786 /* LLVM backend setup */
1787 #ifdef R600_USE_LLVM
1788 if (use_llvm) {
1789 struct radeon_llvm_context radeon_llvm_ctx;
1790 LLVMModuleRef mod;
1791 bool dump = r600_can_dump_shader(&rscreen->b, tokens);
1792 boolean use_kill = false;
1793
1794 memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
1795 radeon_llvm_ctx.type = ctx.type;
1796 radeon_llvm_ctx.two_side = shader->two_side;
1797 radeon_llvm_ctx.face_gpr = ctx.face_gpr;
1798 radeon_llvm_ctx.inputs_count = ctx.shader->ninput + 1;
1799 radeon_llvm_ctx.r600_inputs = ctx.shader->input;
1800 radeon_llvm_ctx.r600_outputs = ctx.shader->output;
1801 radeon_llvm_ctx.color_buffer_count = max_color_exports;
1802 radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
1803 radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN);
1804 radeon_llvm_ctx.stream_outputs = &so;
1805 radeon_llvm_ctx.clip_vertex = ctx.cv_output;
1806 radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
1807 radeon_llvm_ctx.has_compressed_msaa_texturing =
1808 ctx.bc->has_compressed_msaa_texturing;
1809 mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
1810 ctx.shader->has_txq_cube_array_z_comp = radeon_llvm_ctx.has_txq_cube_array_z_comp;
1811 ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
1812
1813 if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, &use_kill, dump)) {
1814 radeon_llvm_dispose(&radeon_llvm_ctx);
1815 use_llvm = 0;
1816 fprintf(stderr, "R600 LLVM backend failed to compile "
1817 "shader. Falling back to TGSI\n");
1818 } else {
1819 ctx.file_offset[TGSI_FILE_OUTPUT] =
1820 ctx.file_offset[TGSI_FILE_INPUT];
1821 }
1822 if (use_kill)
1823 ctx.shader->uses_kill = use_kill;
1824 radeon_llvm_dispose(&radeon_llvm_ctx);
1825 }
1826 #endif
1827 /* End of LLVM backend setup */
1828
1829 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
1830 shader->nr_ps_max_color_exports = 8;
1831
1832 if (!use_llvm) {
1833 if (ctx.fragcoord_input >= 0) {
1834 if (ctx.bc->chip_class == CAYMAN) {
1835 for (j = 0 ; j < 4; j++) {
1836 struct r600_bytecode_alu alu;
1837 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1838 alu.op = ALU_OP1_RECIP_IEEE;
1839 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1840 alu.src[0].chan = 3;
1841
1842 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1843 alu.dst.chan = j;
1844 alu.dst.write = (j == 3);
1845 alu.last = 1;
1846 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1847 return r;
1848 }
1849 } else {
1850 struct r600_bytecode_alu alu;
1851 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1852 alu.op = ALU_OP1_RECIP_IEEE;
1853 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
1854 alu.src[0].chan = 3;
1855
1856 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
1857 alu.dst.chan = 3;
1858 alu.dst.write = 1;
1859 alu.last = 1;
1860 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
1861 return r;
1862 }
1863 }
1864
1865 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
1866 struct r600_bytecode_alu alu;
1867 int r;
1868
1869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1870 alu.op = ALU_OP1_MOV;
1871 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
1872 alu.src[0].value = 0;
1873 alu.dst.sel = ctx.gs_export_gpr_treg;
1874 alu.dst.write = 1;
1875 alu.last = 1;
1876 r = r600_bytecode_add_alu(ctx.bc, &alu);
1877 if (r)
1878 return r;
1879 }
1880 if (shader->two_side && ctx.colors_used) {
1881 if ((r = process_twoside_color_inputs(&ctx)))
1882 return r;
1883 }
1884
1885 tgsi_parse_init(&ctx.parse, tokens);
1886 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
1887 tgsi_parse_token(&ctx.parse);
1888 switch (ctx.parse.FullToken.Token.Type) {
1889 case TGSI_TOKEN_TYPE_INSTRUCTION:
1890 r = tgsi_is_supported(&ctx);
1891 if (r)
1892 goto out_err;
1893 ctx.max_driver_temp_used = 0;
1894 /* reserve first tmp for everyone */
1895 r600_get_temp(&ctx);
1896
1897 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1898 if ((r = tgsi_split_constant(&ctx)))
1899 goto out_err;
1900 if ((r = tgsi_split_literal_constant(&ctx)))
1901 goto out_err;
1902 if (ctx.type == TGSI_PROCESSOR_GEOMETRY)
1903 if ((r = tgsi_split_gs_inputs(&ctx)))
1904 goto out_err;
1905 if (ctx.bc->chip_class == CAYMAN)
1906 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1907 else if (ctx.bc->chip_class >= EVERGREEN)
1908 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1909 else
1910 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1911 r = ctx.inst_info->process(&ctx);
1912 if (r)
1913 goto out_err;
1914 break;
1915 default:
1916 break;
1917 }
1918 }
1919 }
1920
1921 /* Reset the temporary register counter. */
1922 ctx.max_driver_temp_used = 0;
1923
1924 noutput = shader->noutput;
1925
1926 if (!ring_outputs && ctx.clip_vertex_write) {
1927 unsigned clipdist_temp[2];
1928
1929 clipdist_temp[0] = r600_get_temp(&ctx);
1930 clipdist_temp[1] = r600_get_temp(&ctx);
1931
1932 /* need to convert a clipvertex write into clipdistance writes and not export
1933 the clip vertex anymore */
1934
1935 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
1936 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1937 shader->output[noutput].gpr = clipdist_temp[0];
1938 noutput++;
1939 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
1940 shader->output[noutput].gpr = clipdist_temp[1];
1941 noutput++;
1942
1943 /* reset spi_sid for clipvertex output to avoid confusing spi */
1944 shader->output[ctx.cv_output].spi_sid = 0;
1945
1946 shader->clip_dist_write = 0xFF;
1947
1948 for (i = 0; i < 8; i++) {
1949 int oreg = i >> 2;
1950 int ochan = i & 3;
1951
1952 for (j = 0; j < 4; j++) {
1953 struct r600_bytecode_alu alu;
1954 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1955 alu.op = ALU_OP2_DOT4;
1956 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
1957 alu.src[0].chan = j;
1958
1959 alu.src[1].sel = 512 + i;
1960 alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
1961 alu.src[1].chan = j;
1962
1963 alu.dst.sel = clipdist_temp[oreg];
1964 alu.dst.chan = j;
1965 alu.dst.write = (j == ochan);
1966 if (j == 3)
1967 alu.last = 1;
1968 if (!use_llvm)
1969 r = r600_bytecode_add_alu(ctx.bc, &alu);
1970 if (r)
1971 return r;
1972 }
1973 }
1974 }
1975
1976 /* Add stream outputs. */
1977 if (!ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX &&
1978 so.num_outputs && !use_llvm)
1979 emit_streamout(&ctx, &so);
1980
1981 convert_edgeflag_to_int(&ctx);
1982
1983 if (ring_outputs) {
1984 if (key.vs_as_es)
1985 emit_gs_ring_writes(&ctx, FALSE);
1986 } else {
1987 /* Export output */
1988 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
1989
1990 for (i = 0, j = 0; i < noutput; i++, j++) {
1991 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
1992 output[j].gpr = shader->output[i].gpr;
1993 output[j].elem_size = 3;
1994 output[j].swizzle_x = 0;
1995 output[j].swizzle_y = 1;
1996 output[j].swizzle_z = 2;
1997 output[j].swizzle_w = 3;
1998 output[j].burst_count = 1;
1999 output[j].type = -1;
2000 output[j].op = CF_OP_EXPORT;
2001 switch (ctx.type) {
2002 case TGSI_PROCESSOR_VERTEX:
2003 switch (shader->output[i].name) {
2004 case TGSI_SEMANTIC_POSITION:
2005 output[j].array_base = 60;
2006 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2007 pos_emitted = true;
2008 break;
2009
2010 case TGSI_SEMANTIC_PSIZE:
2011 output[j].array_base = 61;
2012 output[j].swizzle_y = 7;
2013 output[j].swizzle_z = 7;
2014 output[j].swizzle_w = 7;
2015 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2016 pos_emitted = true;
2017 break;
2018 case TGSI_SEMANTIC_EDGEFLAG:
2019 output[j].array_base = 61;
2020 output[j].swizzle_x = 7;
2021 output[j].swizzle_y = 0;
2022 output[j].swizzle_z = 7;
2023 output[j].swizzle_w = 7;
2024 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2025 pos_emitted = true;
2026 break;
2027 case TGSI_SEMANTIC_LAYER:
2028 /* spi_sid is 0 for outputs that are
2029 * not consumed by PS */
2030 if (shader->output[i].spi_sid) {
2031 output[j].array_base = next_param_base++;
2032 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2033 j++;
2034 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2035 }
2036 output[j].array_base = 61;
2037 output[j].swizzle_x = 7;
2038 output[j].swizzle_y = 7;
2039 output[j].swizzle_z = 0;
2040 output[j].swizzle_w = 7;
2041 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2042 pos_emitted = true;
2043 break;
2044 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2045 /* spi_sid is 0 for outputs that are
2046 * not consumed by PS */
2047 if (shader->output[i].spi_sid) {
2048 output[j].array_base = next_param_base++;
2049 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2050 j++;
2051 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2052 }
2053 output[j].array_base = 61;
2054 output[j].swizzle_x = 7;
2055 output[j].swizzle_y = 7;
2056 output[j].swizzle_z = 7;
2057 output[j].swizzle_w = 0;
2058 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2059 pos_emitted = true;
2060 break;
2061 case TGSI_SEMANTIC_CLIPVERTEX:
2062 j--;
2063 break;
2064 case TGSI_SEMANTIC_CLIPDIST:
2065 output[j].array_base = next_clip_base++;
2066 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2067 pos_emitted = true;
2068 /* spi_sid is 0 for clipdistance outputs that were generated
2069 * for clipvertex - we don't need to pass them to PS */
2070 if (shader->output[i].spi_sid) {
2071 j++;
2072 /* duplicate it as PARAM to pass to the pixel shader */
2073 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
2074 output[j].array_base = next_param_base++;
2075 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2076 }
2077 break;
2078 case TGSI_SEMANTIC_FOG:
2079 output[j].swizzle_y = 4; /* 0 */
2080 output[j].swizzle_z = 4; /* 0 */
2081 output[j].swizzle_w = 5; /* 1 */
2082 break;
2083 }
2084 break;
2085 case TGSI_PROCESSOR_FRAGMENT:
2086 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
2087 /* never export more colors than the number of CBs */
2088 if (shader->output[i].sid >= max_color_exports) {
2089 /* skip export */
2090 j--;
2091 continue;
2092 }
2093 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
2094 output[j].array_base = shader->output[i].sid;
2095 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2096 shader->nr_ps_color_exports++;
2097 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
2098 for (k = 1; k < max_color_exports; k++) {
2099 j++;
2100 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2101 output[j].gpr = shader->output[i].gpr;
2102 output[j].elem_size = 3;
2103 output[j].swizzle_x = 0;
2104 output[j].swizzle_y = 1;
2105 output[j].swizzle_z = 2;
2106 output[j].swizzle_w = key.alpha_to_one ? 5 : 3;
2107 output[j].burst_count = 1;
2108 output[j].array_base = k;
2109 output[j].op = CF_OP_EXPORT;
2110 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2111 shader->nr_ps_color_exports++;
2112 }
2113 }
2114 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
2115 output[j].array_base = 61;
2116 output[j].swizzle_x = 2;
2117 output[j].swizzle_y = 7;
2118 output[j].swizzle_z = output[j].swizzle_w = 7;
2119 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2120 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2121 output[j].array_base = 61;
2122 output[j].swizzle_x = 7;
2123 output[j].swizzle_y = 1;
2124 output[j].swizzle_z = output[j].swizzle_w = 7;
2125 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2126 } else {
2127 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
2128 r = -EINVAL;
2129 goto out_err;
2130 }
2131 break;
2132 default:
2133 R600_ERR("unsupported processor type %d\n", ctx.type);
2134 r = -EINVAL;
2135 goto out_err;
2136 }
2137
2138 if (output[j].type==-1) {
2139 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2140 output[j].array_base = next_param_base++;
2141 }
2142 }
2143
2144 /* add fake position export */
2145 if (ctx.type == TGSI_PROCESSOR_VERTEX && pos_emitted == false) {
2146 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2147 output[j].gpr = 0;
2148 output[j].elem_size = 3;
2149 output[j].swizzle_x = 7;
2150 output[j].swizzle_y = 7;
2151 output[j].swizzle_z = 7;
2152 output[j].swizzle_w = 7;
2153 output[j].burst_count = 1;
2154 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2155 output[j].array_base = 60;
2156 output[j].op = CF_OP_EXPORT;
2157 j++;
2158 }
2159
2160 /* add fake param output for vertex shader if no param is exported */
2161 if (ctx.type == TGSI_PROCESSOR_VERTEX && next_param_base == 0) {
2162 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2163 output[j].gpr = 0;
2164 output[j].elem_size = 3;
2165 output[j].swizzle_x = 7;
2166 output[j].swizzle_y = 7;
2167 output[j].swizzle_z = 7;
2168 output[j].swizzle_w = 7;
2169 output[j].burst_count = 1;
2170 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2171 output[j].array_base = 0;
2172 output[j].op = CF_OP_EXPORT;
2173 j++;
2174 }
2175
2176 /* add fake pixel export */
2177 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) {
2178 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
2179 output[j].gpr = 0;
2180 output[j].elem_size = 3;
2181 output[j].swizzle_x = 7;
2182 output[j].swizzle_y = 7;
2183 output[j].swizzle_z = 7;
2184 output[j].swizzle_w = 7;
2185 output[j].burst_count = 1;
2186 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
2187 output[j].array_base = 0;
2188 output[j].op = CF_OP_EXPORT;
2189 j++;
2190 }
2191
2192 noutput = j;
2193
2194 /* set export done on last export of each type */
2195 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
2196 if (!(output_done & (1 << output[i].type))) {
2197 output_done |= (1 << output[i].type);
2198 output[i].op = CF_OP_EXPORT_DONE;
2199 }
2200 }
2201 /* add output to bytecode */
2202 if (!use_llvm) {
2203 for (i = 0; i < noutput; i++) {
2204 r = r600_bytecode_add_output(ctx.bc, &output[i]);
2205 if (r)
2206 goto out_err;
2207 }
2208 }
2209 }
2210
2211 /* add program end */
2212 if (!use_llvm) {
2213 if (ctx.bc->chip_class == CAYMAN)
2214 cm_bytecode_add_cf_end(ctx.bc);
2215 else {
2216 const struct cf_op_info *last = NULL;
2217
2218 if (ctx.bc->cf_last)
2219 last = r600_isa_cf(ctx.bc->cf_last->op);
2220
2221 /* alu clause instructions don't have EOP bit, so add NOP */
2222 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_CALL_FS)
2223 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2224
2225 ctx.bc->cf_last->end_of_program = 1;
2226 }
2227 }
2228
2229 /* check GPR limit - we have 124 = 128 - 4
2230 * (4 are reserved as alu clause temporary registers) */
2231 if (ctx.bc->ngpr > 124) {
2232 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
2233 r = -ENOMEM;
2234 goto out_err;
2235 }
2236
2237 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2238 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
2239 return r;
2240 }
2241
2242 free(ctx.literals);
2243 tgsi_parse_free(&ctx.parse);
2244 return 0;
2245 out_err:
2246 free(ctx.literals);
2247 tgsi_parse_free(&ctx.parse);
2248 return r;
2249 }
2250
2251 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
2252 {
2253 R600_ERR("%s tgsi opcode unsupported\n",
2254 tgsi_get_opcode_name(ctx->inst_info->tgsi_opcode));
2255 return -EINVAL;
2256 }
2257
2258 static int tgsi_end(struct r600_shader_ctx *ctx)
2259 {
2260 return 0;
2261 }
2262
2263 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
2264 const struct r600_shader_src *shader_src,
2265 unsigned chan)
2266 {
2267 bc_src->sel = shader_src->sel;
2268 bc_src->chan = shader_src->swizzle[chan];
2269 bc_src->neg = shader_src->neg;
2270 bc_src->abs = shader_src->abs;
2271 bc_src->rel = shader_src->rel;
2272 bc_src->value = shader_src->value[bc_src->chan];
2273 bc_src->kc_bank = shader_src->kc_bank;
2274 }
2275
2276 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
2277 {
2278 bc_src->abs = 1;
2279 bc_src->neg = 0;
2280 }
2281
2282 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
2283 {
2284 bc_src->neg = !bc_src->neg;
2285 }
2286
2287 static void tgsi_dst(struct r600_shader_ctx *ctx,
2288 const struct tgsi_full_dst_register *tgsi_dst,
2289 unsigned swizzle,
2290 struct r600_bytecode_alu_dst *r600_dst)
2291 {
2292 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2293
2294 r600_dst->sel = tgsi_dst->Register.Index;
2295 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
2296 r600_dst->chan = swizzle;
2297 r600_dst->write = 1;
2298 if (tgsi_dst->Register.Indirect)
2299 r600_dst->rel = V_SQ_REL_RELATIVE;
2300 if (inst->Instruction.Saturate) {
2301 r600_dst->clamp = 1;
2302 }
2303 }
2304
2305 static int tgsi_last_instruction(unsigned writemask)
2306 {
2307 int i, lasti = 0;
2308
2309 for (i = 0; i < 4; i++) {
2310 if (writemask & (1 << i)) {
2311 lasti = i;
2312 }
2313 }
2314 return lasti;
2315 }
2316
2317 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
2318 {
2319 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2320 struct r600_bytecode_alu alu;
2321 unsigned write_mask = inst->Dst[0].Register.WriteMask;
2322 int i, j, r, lasti = tgsi_last_instruction(write_mask);
2323 /* use temp register if trans_only and more than one dst component */
2324 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
2325
2326 for (i = 0; i <= lasti; i++) {
2327 if (!(write_mask & (1 << i)))
2328 continue;
2329
2330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2331 if (use_tmp) {
2332 alu.dst.sel = ctx->temp_reg;
2333 alu.dst.chan = i;
2334 alu.dst.write = 1;
2335 } else
2336 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2337
2338 alu.op = ctx->inst_info->op;
2339 if (!swap) {
2340 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2341 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
2342 }
2343 } else {
2344 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
2345 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2346 }
2347 /* handle some special cases */
2348 switch (ctx->inst_info->tgsi_opcode) {
2349 case TGSI_OPCODE_SUB:
2350 r600_bytecode_src_toggle_neg(&alu.src[1]);
2351 break;
2352 case TGSI_OPCODE_ABS:
2353 r600_bytecode_src_set_abs(&alu.src[0]);
2354 break;
2355 default:
2356 break;
2357 }
2358 if (i == lasti || trans_only) {
2359 alu.last = 1;
2360 }
2361 r = r600_bytecode_add_alu(ctx->bc, &alu);
2362 if (r)
2363 return r;
2364 }
2365
2366 if (use_tmp) {
2367 /* move result from temp to dst */
2368 for (i = 0; i <= lasti; i++) {
2369 if (!(write_mask & (1 << i)))
2370 continue;
2371
2372 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2373 alu.op = ALU_OP1_MOV;
2374 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2375 alu.src[0].sel = ctx->temp_reg;
2376 alu.src[0].chan = i;
2377 alu.last = (i == lasti);
2378
2379 r = r600_bytecode_add_alu(ctx->bc, &alu);
2380 if (r)
2381 return r;
2382 }
2383 }
2384 return 0;
2385 }
2386
2387 static int tgsi_op2(struct r600_shader_ctx *ctx)
2388 {
2389 return tgsi_op2_s(ctx, 0, 0);
2390 }
2391
2392 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
2393 {
2394 return tgsi_op2_s(ctx, 1, 0);
2395 }
2396
2397 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
2398 {
2399 return tgsi_op2_s(ctx, 0, 1);
2400 }
2401
2402 static int tgsi_ineg(struct r600_shader_ctx *ctx)
2403 {
2404 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2405 struct r600_bytecode_alu alu;
2406 int i, r;
2407 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2408
2409 for (i = 0; i < lasti + 1; i++) {
2410
2411 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2412 continue;
2413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2414 alu.op = ctx->inst_info->op;
2415
2416 alu.src[0].sel = V_SQ_ALU_SRC_0;
2417
2418 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2419
2420 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2421
2422 if (i == lasti) {
2423 alu.last = 1;
2424 }
2425 r = r600_bytecode_add_alu(ctx->bc, &alu);
2426 if (r)
2427 return r;
2428 }
2429 return 0;
2430
2431 }
2432
2433 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
2434 {
2435 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2436 int i, j, r;
2437 struct r600_bytecode_alu alu;
2438 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2439
2440 for (i = 0 ; i < last_slot; i++) {
2441 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2442 alu.op = ctx->inst_info->op;
2443 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2444 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
2445
2446 /* RSQ should take the absolute value of src */
2447 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_RSQ) {
2448 r600_bytecode_src_set_abs(&alu.src[j]);
2449 }
2450 }
2451 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2452 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2453
2454 if (i == last_slot - 1)
2455 alu.last = 1;
2456 r = r600_bytecode_add_alu(ctx->bc, &alu);
2457 if (r)
2458 return r;
2459 }
2460 return 0;
2461 }
2462
2463 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
2464 {
2465 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2466 int i, j, k, r;
2467 struct r600_bytecode_alu alu;
2468 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2469 for (k = 0; k < last_slot; k++) {
2470 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
2471 continue;
2472
2473 for (i = 0 ; i < 4; i++) {
2474 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2475 alu.op = ctx->inst_info->op;
2476 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
2477 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
2478 }
2479 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2480 alu.dst.write = (i == k);
2481 if (i == 3)
2482 alu.last = 1;
2483 r = r600_bytecode_add_alu(ctx->bc, &alu);
2484 if (r)
2485 return r;
2486 }
2487 }
2488 return 0;
2489 }
2490
2491 /*
2492 * r600 - trunc to -PI..PI range
2493 * r700 - normalize by dividing by 2PI
2494 * see fdo bug 27901
2495 */
2496 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
2497 {
2498 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
2499 static float double_pi = 3.1415926535 * 2;
2500 static float neg_pi = -3.1415926535;
2501
2502 int r;
2503 struct r600_bytecode_alu alu;
2504
2505 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2506 alu.op = ALU_OP3_MULADD;
2507 alu.is_op3 = 1;
2508
2509 alu.dst.chan = 0;
2510 alu.dst.sel = ctx->temp_reg;
2511 alu.dst.write = 1;
2512
2513 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2514
2515 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2516 alu.src[1].chan = 0;
2517 alu.src[1].value = *(uint32_t *)&half_inv_pi;
2518 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2519 alu.src[2].chan = 0;
2520 alu.last = 1;
2521 r = r600_bytecode_add_alu(ctx->bc, &alu);
2522 if (r)
2523 return r;
2524
2525 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2526 alu.op = ALU_OP1_FRACT;
2527
2528 alu.dst.chan = 0;
2529 alu.dst.sel = ctx->temp_reg;
2530 alu.dst.write = 1;
2531
2532 alu.src[0].sel = ctx->temp_reg;
2533 alu.src[0].chan = 0;
2534 alu.last = 1;
2535 r = r600_bytecode_add_alu(ctx->bc, &alu);
2536 if (r)
2537 return r;
2538
2539 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2540 alu.op = ALU_OP3_MULADD;
2541 alu.is_op3 = 1;
2542
2543 alu.dst.chan = 0;
2544 alu.dst.sel = ctx->temp_reg;
2545 alu.dst.write = 1;
2546
2547 alu.src[0].sel = ctx->temp_reg;
2548 alu.src[0].chan = 0;
2549
2550 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2551 alu.src[1].chan = 0;
2552 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
2553 alu.src[2].chan = 0;
2554
2555 if (ctx->bc->chip_class == R600) {
2556 alu.src[1].value = *(uint32_t *)&double_pi;
2557 alu.src[2].value = *(uint32_t *)&neg_pi;
2558 } else {
2559 alu.src[1].sel = V_SQ_ALU_SRC_1;
2560 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
2561 alu.src[2].neg = 1;
2562 }
2563
2564 alu.last = 1;
2565 r = r600_bytecode_add_alu(ctx->bc, &alu);
2566 if (r)
2567 return r;
2568 return 0;
2569 }
2570
2571 static int cayman_trig(struct r600_shader_ctx *ctx)
2572 {
2573 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2574 struct r600_bytecode_alu alu;
2575 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
2576 int i, r;
2577
2578 r = tgsi_setup_trig(ctx);
2579 if (r)
2580 return r;
2581
2582
2583 for (i = 0; i < last_slot; i++) {
2584 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2585 alu.op = ctx->inst_info->op;
2586 alu.dst.chan = i;
2587
2588 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2589 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2590
2591 alu.src[0].sel = ctx->temp_reg;
2592 alu.src[0].chan = 0;
2593 if (i == last_slot - 1)
2594 alu.last = 1;
2595 r = r600_bytecode_add_alu(ctx->bc, &alu);
2596 if (r)
2597 return r;
2598 }
2599 return 0;
2600 }
2601
2602 static int tgsi_trig(struct r600_shader_ctx *ctx)
2603 {
2604 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2605 struct r600_bytecode_alu alu;
2606 int i, r;
2607 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2608
2609 r = tgsi_setup_trig(ctx);
2610 if (r)
2611 return r;
2612
2613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2614 alu.op = ctx->inst_info->op;
2615 alu.dst.chan = 0;
2616 alu.dst.sel = ctx->temp_reg;
2617 alu.dst.write = 1;
2618
2619 alu.src[0].sel = ctx->temp_reg;
2620 alu.src[0].chan = 0;
2621 alu.last = 1;
2622 r = r600_bytecode_add_alu(ctx->bc, &alu);
2623 if (r)
2624 return r;
2625
2626 /* replicate result */
2627 for (i = 0; i < lasti + 1; i++) {
2628 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2629 continue;
2630
2631 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2632 alu.op = ALU_OP1_MOV;
2633
2634 alu.src[0].sel = ctx->temp_reg;
2635 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2636 if (i == lasti)
2637 alu.last = 1;
2638 r = r600_bytecode_add_alu(ctx->bc, &alu);
2639 if (r)
2640 return r;
2641 }
2642 return 0;
2643 }
2644
2645 static int tgsi_scs(struct r600_shader_ctx *ctx)
2646 {
2647 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2648 struct r600_bytecode_alu alu;
2649 int i, r;
2650
2651 /* We'll only need the trig stuff if we are going to write to the
2652 * X or Y components of the destination vector.
2653 */
2654 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
2655 r = tgsi_setup_trig(ctx);
2656 if (r)
2657 return r;
2658 }
2659
2660 /* dst.x = COS */
2661 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2662 if (ctx->bc->chip_class == CAYMAN) {
2663 for (i = 0 ; i < 3; i++) {
2664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2665 alu.op = ALU_OP1_COS;
2666 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2667
2668 if (i == 0)
2669 alu.dst.write = 1;
2670 else
2671 alu.dst.write = 0;
2672 alu.src[0].sel = ctx->temp_reg;
2673 alu.src[0].chan = 0;
2674 if (i == 2)
2675 alu.last = 1;
2676 r = r600_bytecode_add_alu(ctx->bc, &alu);
2677 if (r)
2678 return r;
2679 }
2680 } else {
2681 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2682 alu.op = ALU_OP1_COS;
2683 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2684
2685 alu.src[0].sel = ctx->temp_reg;
2686 alu.src[0].chan = 0;
2687 alu.last = 1;
2688 r = r600_bytecode_add_alu(ctx->bc, &alu);
2689 if (r)
2690 return r;
2691 }
2692 }
2693
2694 /* dst.y = SIN */
2695 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2696 if (ctx->bc->chip_class == CAYMAN) {
2697 for (i = 0 ; i < 3; i++) {
2698 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2699 alu.op = ALU_OP1_SIN;
2700 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2701 if (i == 1)
2702 alu.dst.write = 1;
2703 else
2704 alu.dst.write = 0;
2705 alu.src[0].sel = ctx->temp_reg;
2706 alu.src[0].chan = 0;
2707 if (i == 2)
2708 alu.last = 1;
2709 r = r600_bytecode_add_alu(ctx->bc, &alu);
2710 if (r)
2711 return r;
2712 }
2713 } else {
2714 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2715 alu.op = ALU_OP1_SIN;
2716 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2717
2718 alu.src[0].sel = ctx->temp_reg;
2719 alu.src[0].chan = 0;
2720 alu.last = 1;
2721 r = r600_bytecode_add_alu(ctx->bc, &alu);
2722 if (r)
2723 return r;
2724 }
2725 }
2726
2727 /* dst.z = 0.0; */
2728 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2729 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2730
2731 alu.op = ALU_OP1_MOV;
2732
2733 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2734
2735 alu.src[0].sel = V_SQ_ALU_SRC_0;
2736 alu.src[0].chan = 0;
2737
2738 alu.last = 1;
2739
2740 r = r600_bytecode_add_alu(ctx->bc, &alu);
2741 if (r)
2742 return r;
2743 }
2744
2745 /* dst.w = 1.0; */
2746 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2747 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2748
2749 alu.op = ALU_OP1_MOV;
2750
2751 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2752
2753 alu.src[0].sel = V_SQ_ALU_SRC_1;
2754 alu.src[0].chan = 0;
2755
2756 alu.last = 1;
2757
2758 r = r600_bytecode_add_alu(ctx->bc, &alu);
2759 if (r)
2760 return r;
2761 }
2762
2763 return 0;
2764 }
2765
2766 static int tgsi_kill(struct r600_shader_ctx *ctx)
2767 {
2768 struct r600_bytecode_alu alu;
2769 int i, r;
2770
2771 for (i = 0; i < 4; i++) {
2772 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2773 alu.op = ctx->inst_info->op;
2774
2775 alu.dst.chan = i;
2776
2777 alu.src[0].sel = V_SQ_ALU_SRC_0;
2778
2779 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILL) {
2780 alu.src[1].sel = V_SQ_ALU_SRC_1;
2781 alu.src[1].neg = 1;
2782 } else {
2783 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
2784 }
2785 if (i == 3) {
2786 alu.last = 1;
2787 }
2788 r = r600_bytecode_add_alu(ctx->bc, &alu);
2789 if (r)
2790 return r;
2791 }
2792
2793 /* kill must be last in ALU */
2794 ctx->bc->force_add_cf = 1;
2795 ctx->shader->uses_kill = TRUE;
2796 return 0;
2797 }
2798
2799 static int tgsi_lit(struct r600_shader_ctx *ctx)
2800 {
2801 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2802 struct r600_bytecode_alu alu;
2803 int r;
2804
2805 /* tmp.x = max(src.y, 0.0) */
2806 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2807 alu.op = ALU_OP2_MAX;
2808 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
2809 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2810 alu.src[1].chan = 1;
2811
2812 alu.dst.sel = ctx->temp_reg;
2813 alu.dst.chan = 0;
2814 alu.dst.write = 1;
2815
2816 alu.last = 1;
2817 r = r600_bytecode_add_alu(ctx->bc, &alu);
2818 if (r)
2819 return r;
2820
2821 if (inst->Dst[0].Register.WriteMask & (1 << 2))
2822 {
2823 int chan;
2824 int sel;
2825 int i;
2826
2827 if (ctx->bc->chip_class == CAYMAN) {
2828 for (i = 0; i < 3; i++) {
2829 /* tmp.z = log(tmp.x) */
2830 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2831 alu.op = ALU_OP1_LOG_CLAMPED;
2832 alu.src[0].sel = ctx->temp_reg;
2833 alu.src[0].chan = 0;
2834 alu.dst.sel = ctx->temp_reg;
2835 alu.dst.chan = i;
2836 if (i == 2) {
2837 alu.dst.write = 1;
2838 alu.last = 1;
2839 } else
2840 alu.dst.write = 0;
2841
2842 r = r600_bytecode_add_alu(ctx->bc, &alu);
2843 if (r)
2844 return r;
2845 }
2846 } else {
2847 /* tmp.z = log(tmp.x) */
2848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2849 alu.op = ALU_OP1_LOG_CLAMPED;
2850 alu.src[0].sel = ctx->temp_reg;
2851 alu.src[0].chan = 0;
2852 alu.dst.sel = ctx->temp_reg;
2853 alu.dst.chan = 2;
2854 alu.dst.write = 1;
2855 alu.last = 1;
2856 r = r600_bytecode_add_alu(ctx->bc, &alu);
2857 if (r)
2858 return r;
2859 }
2860
2861 chan = alu.dst.chan;
2862 sel = alu.dst.sel;
2863
2864 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
2865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2866 alu.op = ALU_OP3_MUL_LIT;
2867 alu.src[0].sel = sel;
2868 alu.src[0].chan = chan;
2869 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
2870 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
2871 alu.dst.sel = ctx->temp_reg;
2872 alu.dst.chan = 0;
2873 alu.dst.write = 1;
2874 alu.is_op3 = 1;
2875 alu.last = 1;
2876 r = r600_bytecode_add_alu(ctx->bc, &alu);
2877 if (r)
2878 return r;
2879
2880 if (ctx->bc->chip_class == CAYMAN) {
2881 for (i = 0; i < 3; i++) {
2882 /* dst.z = exp(tmp.x) */
2883 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2884 alu.op = ALU_OP1_EXP_IEEE;
2885 alu.src[0].sel = ctx->temp_reg;
2886 alu.src[0].chan = 0;
2887 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2888 if (i == 2) {
2889 alu.dst.write = 1;
2890 alu.last = 1;
2891 } else
2892 alu.dst.write = 0;
2893 r = r600_bytecode_add_alu(ctx->bc, &alu);
2894 if (r)
2895 return r;
2896 }
2897 } else {
2898 /* dst.z = exp(tmp.x) */
2899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2900 alu.op = ALU_OP1_EXP_IEEE;
2901 alu.src[0].sel = ctx->temp_reg;
2902 alu.src[0].chan = 0;
2903 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
2904 alu.last = 1;
2905 r = r600_bytecode_add_alu(ctx->bc, &alu);
2906 if (r)
2907 return r;
2908 }
2909 }
2910
2911 /* dst.x, <- 1.0 */
2912 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2913 alu.op = ALU_OP1_MOV;
2914 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
2915 alu.src[0].chan = 0;
2916 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
2917 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
2918 r = r600_bytecode_add_alu(ctx->bc, &alu);
2919 if (r)
2920 return r;
2921
2922 /* dst.y = max(src.x, 0.0) */
2923 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2924 alu.op = ALU_OP2_MAX;
2925 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
2926 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
2927 alu.src[1].chan = 0;
2928 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
2929 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
2930 r = r600_bytecode_add_alu(ctx->bc, &alu);
2931 if (r)
2932 return r;
2933
2934 /* dst.w, <- 1.0 */
2935 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2936 alu.op = ALU_OP1_MOV;
2937 alu.src[0].sel = V_SQ_ALU_SRC_1;
2938 alu.src[0].chan = 0;
2939 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
2940 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
2941 alu.last = 1;
2942 r = r600_bytecode_add_alu(ctx->bc, &alu);
2943 if (r)
2944 return r;
2945
2946 return 0;
2947 }
2948
2949 static int tgsi_rsq(struct r600_shader_ctx *ctx)
2950 {
2951 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2952 struct r600_bytecode_alu alu;
2953 int i, r;
2954
2955 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2956
2957 /* XXX:
2958 * For state trackers other than OpenGL, we'll want to use
2959 * _RECIPSQRT_IEEE instead.
2960 */
2961 alu.op = ALU_OP1_RECIPSQRT_CLAMPED;
2962
2963 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2964 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
2965 r600_bytecode_src_set_abs(&alu.src[i]);
2966 }
2967 alu.dst.sel = ctx->temp_reg;
2968 alu.dst.write = 1;
2969 alu.last = 1;
2970 r = r600_bytecode_add_alu(ctx->bc, &alu);
2971 if (r)
2972 return r;
2973 /* replicate result */
2974 return tgsi_helper_tempx_replicate(ctx);
2975 }
2976
2977 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
2978 {
2979 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2980 struct r600_bytecode_alu alu;
2981 int i, r;
2982
2983 for (i = 0; i < 4; i++) {
2984 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2985 alu.src[0].sel = ctx->temp_reg;
2986 alu.op = ALU_OP1_MOV;
2987 alu.dst.chan = i;
2988 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2989 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
2990 if (i == 3)
2991 alu.last = 1;
2992 r = r600_bytecode_add_alu(ctx->bc, &alu);
2993 if (r)
2994 return r;
2995 }
2996 return 0;
2997 }
2998
2999 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
3000 {
3001 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3002 struct r600_bytecode_alu alu;
3003 int i, r;
3004
3005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3006 alu.op = ctx->inst_info->op;
3007 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
3008 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
3009 }
3010 alu.dst.sel = ctx->temp_reg;
3011 alu.dst.write = 1;
3012 alu.last = 1;
3013 r = r600_bytecode_add_alu(ctx->bc, &alu);
3014 if (r)
3015 return r;
3016 /* replicate result */
3017 return tgsi_helper_tempx_replicate(ctx);
3018 }
3019
3020 static int cayman_pow(struct r600_shader_ctx *ctx)
3021 {
3022 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3023 int i, r;
3024 struct r600_bytecode_alu alu;
3025 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
3026
3027 for (i = 0; i < 3; i++) {
3028 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3029 alu.op = ALU_OP1_LOG_IEEE;
3030 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3031 alu.dst.sel = ctx->temp_reg;
3032 alu.dst.chan = i;
3033 alu.dst.write = 1;
3034 if (i == 2)
3035 alu.last = 1;
3036 r = r600_bytecode_add_alu(ctx->bc, &alu);
3037 if (r)
3038 return r;
3039 }
3040
3041 /* b * LOG2(a) */
3042 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3043 alu.op = ALU_OP2_MUL;
3044 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3045 alu.src[1].sel = ctx->temp_reg;
3046 alu.dst.sel = ctx->temp_reg;
3047 alu.dst.write = 1;
3048 alu.last = 1;
3049 r = r600_bytecode_add_alu(ctx->bc, &alu);
3050 if (r)
3051 return r;
3052
3053 for (i = 0; i < last_slot; i++) {
3054 /* POW(a,b) = EXP2(b * LOG2(a))*/
3055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3056 alu.op = ALU_OP1_EXP_IEEE;
3057 alu.src[0].sel = ctx->temp_reg;
3058
3059 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3060 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
3061 if (i == last_slot - 1)
3062 alu.last = 1;
3063 r = r600_bytecode_add_alu(ctx->bc, &alu);
3064 if (r)
3065 return r;
3066 }
3067 return 0;
3068 }
3069
3070 static int tgsi_pow(struct r600_shader_ctx *ctx)
3071 {
3072 struct r600_bytecode_alu alu;
3073 int r;
3074
3075 /* LOG2(a) */
3076 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3077 alu.op = ALU_OP1_LOG_IEEE;
3078 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
3079 alu.dst.sel = ctx->temp_reg;
3080 alu.dst.write = 1;
3081 alu.last = 1;
3082 r = r600_bytecode_add_alu(ctx->bc, &alu);
3083 if (r)
3084 return r;
3085 /* b * LOG2(a) */
3086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3087 alu.op = ALU_OP2_MUL;
3088 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
3089 alu.src[1].sel = ctx->temp_reg;
3090 alu.dst.sel = ctx->temp_reg;
3091 alu.dst.write = 1;
3092 alu.last = 1;
3093 r = r600_bytecode_add_alu(ctx->bc, &alu);
3094 if (r)
3095 return r;
3096 /* POW(a,b) = EXP2(b * LOG2(a))*/
3097 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3098 alu.op = ALU_OP1_EXP_IEEE;
3099 alu.src[0].sel = ctx->temp_reg;
3100 alu.dst.sel = ctx->temp_reg;
3101 alu.dst.write = 1;
3102 alu.last = 1;
3103 r = r600_bytecode_add_alu(ctx->bc, &alu);
3104 if (r)
3105 return r;
3106 return tgsi_helper_tempx_replicate(ctx);
3107 }
3108
3109 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
3110 {
3111 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3112 struct r600_bytecode_alu alu;
3113 int i, r, j;
3114 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3115 int tmp0 = ctx->temp_reg;
3116 int tmp1 = r600_get_temp(ctx);
3117 int tmp2 = r600_get_temp(ctx);
3118 int tmp3 = r600_get_temp(ctx);
3119 /* Unsigned path:
3120 *
3121 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
3122 *
3123 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
3124 * 2. tmp0.z = lo (tmp0.x * src2)
3125 * 3. tmp0.w = -tmp0.z
3126 * 4. tmp0.y = hi (tmp0.x * src2)
3127 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
3128 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
3129 * 7. tmp1.x = tmp0.x - tmp0.w
3130 * 8. tmp1.y = tmp0.x + tmp0.w
3131 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
3132 * 10. tmp0.z = hi(tmp0.x * src1) = q
3133 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
3134 *
3135 * 12. tmp0.w = src1 - tmp0.y = r
3136 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
3137 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
3138 *
3139 * if DIV
3140 *
3141 * 15. tmp1.z = tmp0.z + 1 = q + 1
3142 * 16. tmp1.w = tmp0.z - 1 = q - 1
3143 *
3144 * else MOD
3145 *
3146 * 15. tmp1.z = tmp0.w - src2 = r - src2
3147 * 16. tmp1.w = tmp0.w + src2 = r + src2
3148 *
3149 * endif
3150 *
3151 * 17. tmp1.x = tmp1.x & tmp1.y
3152 *
3153 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
3154 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
3155 *
3156 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
3157 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
3158 *
3159 * Signed path:
3160 *
3161 * Same as unsigned, using abs values of the operands,
3162 * and fixing the sign of the result in the end.
3163 */
3164
3165 for (i = 0; i < 4; i++) {
3166 if (!(write_mask & (1<<i)))
3167 continue;
3168
3169 if (signed_op) {
3170
3171 /* tmp2.x = -src0 */
3172 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3173 alu.op = ALU_OP2_SUB_INT;
3174
3175 alu.dst.sel = tmp2;
3176 alu.dst.chan = 0;
3177 alu.dst.write = 1;
3178
3179 alu.src[0].sel = V_SQ_ALU_SRC_0;
3180
3181 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3182
3183 alu.last = 1;
3184 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3185 return r;
3186
3187 /* tmp2.y = -src1 */
3188 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3189 alu.op = ALU_OP2_SUB_INT;
3190
3191 alu.dst.sel = tmp2;
3192 alu.dst.chan = 1;
3193 alu.dst.write = 1;
3194
3195 alu.src[0].sel = V_SQ_ALU_SRC_0;
3196
3197 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3198
3199 alu.last = 1;
3200 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3201 return r;
3202
3203 /* tmp2.z sign bit is set if src0 and src2 signs are different */
3204 /* it will be a sign of the quotient */
3205 if (!mod) {
3206
3207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3208 alu.op = ALU_OP2_XOR_INT;
3209
3210 alu.dst.sel = tmp2;
3211 alu.dst.chan = 2;
3212 alu.dst.write = 1;
3213
3214 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3215 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3216
3217 alu.last = 1;
3218 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3219 return r;
3220 }
3221
3222 /* tmp2.x = |src0| */
3223 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3224 alu.op = ALU_OP3_CNDGE_INT;
3225 alu.is_op3 = 1;
3226
3227 alu.dst.sel = tmp2;
3228 alu.dst.chan = 0;
3229 alu.dst.write = 1;
3230
3231 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3232 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3233 alu.src[2].sel = tmp2;
3234 alu.src[2].chan = 0;
3235
3236 alu.last = 1;
3237 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3238 return r;
3239
3240 /* tmp2.y = |src1| */
3241 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3242 alu.op = ALU_OP3_CNDGE_INT;
3243 alu.is_op3 = 1;
3244
3245 alu.dst.sel = tmp2;
3246 alu.dst.chan = 1;
3247 alu.dst.write = 1;
3248
3249 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3250 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3251 alu.src[2].sel = tmp2;
3252 alu.src[2].chan = 1;
3253
3254 alu.last = 1;
3255 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3256 return r;
3257
3258 }
3259
3260 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
3261 if (ctx->bc->chip_class == CAYMAN) {
3262 /* tmp3.x = u2f(src2) */
3263 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3264 alu.op = ALU_OP1_UINT_TO_FLT;
3265
3266 alu.dst.sel = tmp3;
3267 alu.dst.chan = 0;
3268 alu.dst.write = 1;
3269
3270 if (signed_op) {
3271 alu.src[0].sel = tmp2;
3272 alu.src[0].chan = 1;
3273 } else {
3274 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3275 }
3276
3277 alu.last = 1;
3278 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3279 return r;
3280
3281 /* tmp0.x = recip(tmp3.x) */
3282 for (j = 0 ; j < 3; j++) {
3283 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3284 alu.op = ALU_OP1_RECIP_IEEE;
3285
3286 alu.dst.sel = tmp0;
3287 alu.dst.chan = j;
3288 alu.dst.write = (j == 0);
3289
3290 alu.src[0].sel = tmp3;
3291 alu.src[0].chan = 0;
3292
3293 if (j == 2)
3294 alu.last = 1;
3295 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3296 return r;
3297 }
3298
3299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3300 alu.op = ALU_OP2_MUL;
3301
3302 alu.src[0].sel = tmp0;
3303 alu.src[0].chan = 0;
3304
3305 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3306 alu.src[1].value = 0x4f800000;
3307
3308 alu.dst.sel = tmp3;
3309 alu.dst.write = 1;
3310 alu.last = 1;
3311 r = r600_bytecode_add_alu(ctx->bc, &alu);
3312 if (r)
3313 return r;
3314
3315 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3316 alu.op = ALU_OP1_FLT_TO_UINT;
3317
3318 alu.dst.sel = tmp0;
3319 alu.dst.chan = 0;
3320 alu.dst.write = 1;
3321
3322 alu.src[0].sel = tmp3;
3323 alu.src[0].chan = 0;
3324
3325 alu.last = 1;
3326 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3327 return r;
3328
3329 } else {
3330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3331 alu.op = ALU_OP1_RECIP_UINT;
3332
3333 alu.dst.sel = tmp0;
3334 alu.dst.chan = 0;
3335 alu.dst.write = 1;
3336
3337 if (signed_op) {
3338 alu.src[0].sel = tmp2;
3339 alu.src[0].chan = 1;
3340 } else {
3341 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3342 }
3343
3344 alu.last = 1;
3345 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3346 return r;
3347 }
3348
3349 /* 2. tmp0.z = lo (tmp0.x * src2) */
3350 if (ctx->bc->chip_class == CAYMAN) {
3351 for (j = 0 ; j < 4; j++) {
3352 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3353 alu.op = ALU_OP2_MULLO_UINT;
3354
3355 alu.dst.sel = tmp0;
3356 alu.dst.chan = j;
3357 alu.dst.write = (j == 2);
3358
3359 alu.src[0].sel = tmp0;
3360 alu.src[0].chan = 0;
3361 if (signed_op) {
3362 alu.src[1].sel = tmp2;
3363 alu.src[1].chan = 1;
3364 } else {
3365 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3366 }
3367
3368 alu.last = (j == 3);
3369 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3370 return r;
3371 }
3372 } else {
3373 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3374 alu.op = ALU_OP2_MULLO_UINT;
3375
3376 alu.dst.sel = tmp0;
3377 alu.dst.chan = 2;
3378 alu.dst.write = 1;
3379
3380 alu.src[0].sel = tmp0;
3381 alu.src[0].chan = 0;
3382 if (signed_op) {
3383 alu.src[1].sel = tmp2;
3384 alu.src[1].chan = 1;
3385 } else {
3386 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3387 }
3388
3389 alu.last = 1;
3390 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3391 return r;
3392 }
3393
3394 /* 3. tmp0.w = -tmp0.z */
3395 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3396 alu.op = ALU_OP2_SUB_INT;
3397
3398 alu.dst.sel = tmp0;
3399 alu.dst.chan = 3;
3400 alu.dst.write = 1;
3401
3402 alu.src[0].sel = V_SQ_ALU_SRC_0;
3403 alu.src[1].sel = tmp0;
3404 alu.src[1].chan = 2;
3405
3406 alu.last = 1;
3407 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3408 return r;
3409
3410 /* 4. tmp0.y = hi (tmp0.x * src2) */
3411 if (ctx->bc->chip_class == CAYMAN) {
3412 for (j = 0 ; j < 4; j++) {
3413 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3414 alu.op = ALU_OP2_MULHI_UINT;
3415
3416 alu.dst.sel = tmp0;
3417 alu.dst.chan = j;
3418 alu.dst.write = (j == 1);
3419
3420 alu.src[0].sel = tmp0;
3421 alu.src[0].chan = 0;
3422
3423 if (signed_op) {
3424 alu.src[1].sel = tmp2;
3425 alu.src[1].chan = 1;
3426 } else {
3427 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3428 }
3429 alu.last = (j == 3);
3430 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3431 return r;
3432 }
3433 } else {
3434 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3435 alu.op = ALU_OP2_MULHI_UINT;
3436
3437 alu.dst.sel = tmp0;
3438 alu.dst.chan = 1;
3439 alu.dst.write = 1;
3440
3441 alu.src[0].sel = tmp0;
3442 alu.src[0].chan = 0;
3443
3444 if (signed_op) {
3445 alu.src[1].sel = tmp2;
3446 alu.src[1].chan = 1;
3447 } else {
3448 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3449 }
3450
3451 alu.last = 1;
3452 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3453 return r;
3454 }
3455
3456 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
3457 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3458 alu.op = ALU_OP3_CNDE_INT;
3459 alu.is_op3 = 1;
3460
3461 alu.dst.sel = tmp0;
3462 alu.dst.chan = 2;
3463 alu.dst.write = 1;
3464
3465 alu.src[0].sel = tmp0;
3466 alu.src[0].chan = 1;
3467 alu.src[1].sel = tmp0;
3468 alu.src[1].chan = 3;
3469 alu.src[2].sel = tmp0;
3470 alu.src[2].chan = 2;
3471
3472 alu.last = 1;
3473 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3474 return r;
3475
3476 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
3477 if (ctx->bc->chip_class == CAYMAN) {
3478 for (j = 0 ; j < 4; j++) {
3479 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3480 alu.op = ALU_OP2_MULHI_UINT;
3481
3482 alu.dst.sel = tmp0;
3483 alu.dst.chan = j;
3484 alu.dst.write = (j == 3);
3485
3486 alu.src[0].sel = tmp0;
3487 alu.src[0].chan = 2;
3488
3489 alu.src[1].sel = tmp0;
3490 alu.src[1].chan = 0;
3491
3492 alu.last = (j == 3);
3493 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3494 return r;
3495 }
3496 } else {
3497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3498 alu.op = ALU_OP2_MULHI_UINT;
3499
3500 alu.dst.sel = tmp0;
3501 alu.dst.chan = 3;
3502 alu.dst.write = 1;
3503
3504 alu.src[0].sel = tmp0;
3505 alu.src[0].chan = 2;
3506
3507 alu.src[1].sel = tmp0;
3508 alu.src[1].chan = 0;
3509
3510 alu.last = 1;
3511 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3512 return r;
3513 }
3514
3515 /* 7. tmp1.x = tmp0.x - tmp0.w */
3516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3517 alu.op = ALU_OP2_SUB_INT;
3518
3519 alu.dst.sel = tmp1;
3520 alu.dst.chan = 0;
3521 alu.dst.write = 1;
3522
3523 alu.src[0].sel = tmp0;
3524 alu.src[0].chan = 0;
3525 alu.src[1].sel = tmp0;
3526 alu.src[1].chan = 3;
3527
3528 alu.last = 1;
3529 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3530 return r;
3531
3532 /* 8. tmp1.y = tmp0.x + tmp0.w */
3533 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3534 alu.op = ALU_OP2_ADD_INT;
3535
3536 alu.dst.sel = tmp1;
3537 alu.dst.chan = 1;
3538 alu.dst.write = 1;
3539
3540 alu.src[0].sel = tmp0;
3541 alu.src[0].chan = 0;
3542 alu.src[1].sel = tmp0;
3543 alu.src[1].chan = 3;
3544
3545 alu.last = 1;
3546 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3547 return r;
3548
3549 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
3550 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3551 alu.op = ALU_OP3_CNDE_INT;
3552 alu.is_op3 = 1;
3553
3554 alu.dst.sel = tmp0;
3555 alu.dst.chan = 0;
3556 alu.dst.write = 1;
3557
3558 alu.src[0].sel = tmp0;
3559 alu.src[0].chan = 1;
3560 alu.src[1].sel = tmp1;
3561 alu.src[1].chan = 1;
3562 alu.src[2].sel = tmp1;
3563 alu.src[2].chan = 0;
3564
3565 alu.last = 1;
3566 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3567 return r;
3568
3569 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
3570 if (ctx->bc->chip_class == CAYMAN) {
3571 for (j = 0 ; j < 4; j++) {
3572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3573 alu.op = ALU_OP2_MULHI_UINT;
3574
3575 alu.dst.sel = tmp0;
3576 alu.dst.chan = j;
3577 alu.dst.write = (j == 2);
3578
3579 alu.src[0].sel = tmp0;
3580 alu.src[0].chan = 0;
3581
3582 if (signed_op) {
3583 alu.src[1].sel = tmp2;
3584 alu.src[1].chan = 0;
3585 } else {
3586 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3587 }
3588
3589 alu.last = (j == 3);
3590 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3591 return r;
3592 }
3593 } else {
3594 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3595 alu.op = ALU_OP2_MULHI_UINT;
3596
3597 alu.dst.sel = tmp0;
3598 alu.dst.chan = 2;
3599 alu.dst.write = 1;
3600
3601 alu.src[0].sel = tmp0;
3602 alu.src[0].chan = 0;
3603
3604 if (signed_op) {
3605 alu.src[1].sel = tmp2;
3606 alu.src[1].chan = 0;
3607 } else {
3608 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
3609 }
3610
3611 alu.last = 1;
3612 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3613 return r;
3614 }
3615
3616 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
3617 if (ctx->bc->chip_class == CAYMAN) {
3618 for (j = 0 ; j < 4; j++) {
3619 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3620 alu.op = ALU_OP2_MULLO_UINT;
3621
3622 alu.dst.sel = tmp0;
3623 alu.dst.chan = j;
3624 alu.dst.write = (j == 1);
3625
3626 if (signed_op) {
3627 alu.src[0].sel = tmp2;
3628 alu.src[0].chan = 1;
3629 } else {
3630 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3631 }
3632
3633 alu.src[1].sel = tmp0;
3634 alu.src[1].chan = 2;
3635
3636 alu.last = (j == 3);
3637 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3638 return r;
3639 }
3640 } else {
3641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3642 alu.op = ALU_OP2_MULLO_UINT;
3643
3644 alu.dst.sel = tmp0;
3645 alu.dst.chan = 1;
3646 alu.dst.write = 1;
3647
3648 if (signed_op) {
3649 alu.src[0].sel = tmp2;
3650 alu.src[0].chan = 1;
3651 } else {
3652 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
3653 }
3654
3655 alu.src[1].sel = tmp0;
3656 alu.src[1].chan = 2;
3657
3658 alu.last = 1;
3659 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3660 return r;
3661 }
3662
3663 /* 12. tmp0.w = src1 - tmp0.y = r */
3664 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3665 alu.op = ALU_OP2_SUB_INT;
3666
3667 alu.dst.sel = tmp0;
3668 alu.dst.chan = 3;
3669 alu.dst.write = 1;
3670
3671 if (signed_op) {
3672 alu.src[0].sel = tmp2;
3673 alu.src[0].chan = 0;
3674 } else {
3675 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3676 }
3677
3678 alu.src[1].sel = tmp0;
3679 alu.src[1].chan = 1;
3680
3681 alu.last = 1;
3682 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3683 return r;
3684
3685 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
3686 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3687 alu.op = ALU_OP2_SETGE_UINT;
3688
3689 alu.dst.sel = tmp1;
3690 alu.dst.chan = 0;
3691 alu.dst.write = 1;
3692
3693 alu.src[0].sel = tmp0;
3694 alu.src[0].chan = 3;
3695 if (signed_op) {
3696 alu.src[1].sel = tmp2;
3697 alu.src[1].chan = 1;
3698 } else {
3699 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3700 }
3701
3702 alu.last = 1;
3703 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3704 return r;
3705
3706 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
3707 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3708 alu.op = ALU_OP2_SETGE_UINT;
3709
3710 alu.dst.sel = tmp1;
3711 alu.dst.chan = 1;
3712 alu.dst.write = 1;
3713
3714 if (signed_op) {
3715 alu.src[0].sel = tmp2;
3716 alu.src[0].chan = 0;
3717 } else {
3718 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3719 }
3720
3721 alu.src[1].sel = tmp0;
3722 alu.src[1].chan = 1;
3723
3724 alu.last = 1;
3725 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3726 return r;
3727
3728 if (mod) { /* UMOD */
3729
3730 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
3731 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3732 alu.op = ALU_OP2_SUB_INT;
3733
3734 alu.dst.sel = tmp1;
3735 alu.dst.chan = 2;
3736 alu.dst.write = 1;
3737
3738 alu.src[0].sel = tmp0;
3739 alu.src[0].chan = 3;
3740
3741 if (signed_op) {
3742 alu.src[1].sel = tmp2;
3743 alu.src[1].chan = 1;
3744 } else {
3745 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3746 }
3747
3748 alu.last = 1;
3749 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3750 return r;
3751
3752 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
3753 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3754 alu.op = ALU_OP2_ADD_INT;
3755
3756 alu.dst.sel = tmp1;
3757 alu.dst.chan = 3;
3758 alu.dst.write = 1;
3759
3760 alu.src[0].sel = tmp0;
3761 alu.src[0].chan = 3;
3762 if (signed_op) {
3763 alu.src[1].sel = tmp2;
3764 alu.src[1].chan = 1;
3765 } else {
3766 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
3767 }
3768
3769 alu.last = 1;
3770 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3771 return r;
3772
3773 } else { /* UDIV */
3774
3775 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
3776 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3777 alu.op = ALU_OP2_ADD_INT;
3778
3779 alu.dst.sel = tmp1;
3780 alu.dst.chan = 2;
3781 alu.dst.write = 1;
3782
3783 alu.src[0].sel = tmp0;
3784 alu.src[0].chan = 2;
3785 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
3786
3787 alu.last = 1;
3788 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3789 return r;
3790
3791 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
3792 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3793 alu.op = ALU_OP2_ADD_INT;
3794
3795 alu.dst.sel = tmp1;
3796 alu.dst.chan = 3;
3797 alu.dst.write = 1;
3798
3799 alu.src[0].sel = tmp0;
3800 alu.src[0].chan = 2;
3801 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
3802
3803 alu.last = 1;
3804 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3805 return r;
3806
3807 }
3808
3809 /* 17. tmp1.x = tmp1.x & tmp1.y */
3810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3811 alu.op = ALU_OP2_AND_INT;
3812
3813 alu.dst.sel = tmp1;
3814 alu.dst.chan = 0;
3815 alu.dst.write = 1;
3816
3817 alu.src[0].sel = tmp1;
3818 alu.src[0].chan = 0;
3819 alu.src[1].sel = tmp1;
3820 alu.src[1].chan = 1;
3821
3822 alu.last = 1;
3823 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3824 return r;
3825
3826 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
3827 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
3828 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3829 alu.op = ALU_OP3_CNDE_INT;
3830 alu.is_op3 = 1;
3831
3832 alu.dst.sel = tmp0;
3833 alu.dst.chan = 2;
3834 alu.dst.write = 1;
3835
3836 alu.src[0].sel = tmp1;
3837 alu.src[0].chan = 0;
3838 alu.src[1].sel = tmp0;
3839 alu.src[1].chan = mod ? 3 : 2;
3840 alu.src[2].sel = tmp1;
3841 alu.src[2].chan = 2;
3842
3843 alu.last = 1;
3844 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3845 return r;
3846
3847 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
3848 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3849 alu.op = ALU_OP3_CNDE_INT;
3850 alu.is_op3 = 1;
3851
3852 if (signed_op) {
3853 alu.dst.sel = tmp0;
3854 alu.dst.chan = 2;
3855 alu.dst.write = 1;
3856 } else {
3857 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3858 }
3859
3860 alu.src[0].sel = tmp1;
3861 alu.src[0].chan = 1;
3862 alu.src[1].sel = tmp1;
3863 alu.src[1].chan = 3;
3864 alu.src[2].sel = tmp0;
3865 alu.src[2].chan = 2;
3866
3867 alu.last = 1;
3868 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3869 return r;
3870
3871 if (signed_op) {
3872
3873 /* fix the sign of the result */
3874
3875 if (mod) {
3876
3877 /* tmp0.x = -tmp0.z */
3878 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3879 alu.op = ALU_OP2_SUB_INT;
3880
3881 alu.dst.sel = tmp0;
3882 alu.dst.chan = 0;
3883 alu.dst.write = 1;
3884
3885 alu.src[0].sel = V_SQ_ALU_SRC_0;
3886 alu.src[1].sel = tmp0;
3887 alu.src[1].chan = 2;
3888
3889 alu.last = 1;
3890 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3891 return r;
3892
3893 /* sign of the remainder is the same as the sign of src0 */
3894 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
3895 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3896 alu.op = ALU_OP3_CNDGE_INT;
3897 alu.is_op3 = 1;
3898
3899 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3900
3901 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3902 alu.src[1].sel = tmp0;
3903 alu.src[1].chan = 2;
3904 alu.src[2].sel = tmp0;
3905 alu.src[2].chan = 0;
3906
3907 alu.last = 1;
3908 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3909 return r;
3910
3911 } else {
3912
3913 /* tmp0.x = -tmp0.z */
3914 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3915 alu.op = ALU_OP2_SUB_INT;
3916
3917 alu.dst.sel = tmp0;
3918 alu.dst.chan = 0;
3919 alu.dst.write = 1;
3920
3921 alu.src[0].sel = V_SQ_ALU_SRC_0;
3922 alu.src[1].sel = tmp0;
3923 alu.src[1].chan = 2;
3924
3925 alu.last = 1;
3926 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3927 return r;
3928
3929 /* fix the quotient sign (same as the sign of src0*src1) */
3930 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
3931 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3932 alu.op = ALU_OP3_CNDGE_INT;
3933 alu.is_op3 = 1;
3934
3935 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
3936
3937 alu.src[0].sel = tmp2;
3938 alu.src[0].chan = 2;
3939 alu.src[1].sel = tmp0;
3940 alu.src[1].chan = 2;
3941 alu.src[2].sel = tmp0;
3942 alu.src[2].chan = 0;
3943
3944 alu.last = 1;
3945 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
3946 return r;
3947 }
3948 }
3949 }
3950 return 0;
3951 }
3952
3953 static int tgsi_udiv(struct r600_shader_ctx *ctx)
3954 {
3955 return tgsi_divmod(ctx, 0, 0);
3956 }
3957
3958 static int tgsi_umod(struct r600_shader_ctx *ctx)
3959 {
3960 return tgsi_divmod(ctx, 1, 0);
3961 }
3962
3963 static int tgsi_idiv(struct r600_shader_ctx *ctx)
3964 {
3965 return tgsi_divmod(ctx, 0, 1);
3966 }
3967
3968 static int tgsi_imod(struct r600_shader_ctx *ctx)
3969 {
3970 return tgsi_divmod(ctx, 1, 1);
3971 }
3972
3973
3974 static int tgsi_f2i(struct r600_shader_ctx *ctx)
3975 {
3976 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3977 struct r600_bytecode_alu alu;
3978 int i, r;
3979 unsigned write_mask = inst->Dst[0].Register.WriteMask;
3980 int last_inst = tgsi_last_instruction(write_mask);
3981
3982 for (i = 0; i < 4; i++) {
3983 if (!(write_mask & (1<<i)))
3984 continue;
3985
3986 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3987 alu.op = ALU_OP1_TRUNC;
3988
3989 alu.dst.sel = ctx->temp_reg;
3990 alu.dst.chan = i;
3991 alu.dst.write = 1;
3992
3993 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
3994 if (i == last_inst)
3995 alu.last = 1;
3996 r = r600_bytecode_add_alu(ctx->bc, &alu);
3997 if (r)
3998 return r;
3999 }
4000
4001 for (i = 0; i < 4; i++) {
4002 if (!(write_mask & (1<<i)))
4003 continue;
4004
4005 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4006 alu.op = ctx->inst_info->op;
4007
4008 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4009
4010 alu.src[0].sel = ctx->temp_reg;
4011 alu.src[0].chan = i;
4012
4013 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
4014 alu.last = 1;
4015 r = r600_bytecode_add_alu(ctx->bc, &alu);
4016 if (r)
4017 return r;
4018 }
4019
4020 return 0;
4021 }
4022
4023 static int tgsi_iabs(struct r600_shader_ctx *ctx)
4024 {
4025 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4026 struct r600_bytecode_alu alu;
4027 int i, r;
4028 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4029 int last_inst = tgsi_last_instruction(write_mask);
4030
4031 /* tmp = -src */
4032 for (i = 0; i < 4; i++) {
4033 if (!(write_mask & (1<<i)))
4034 continue;
4035
4036 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4037 alu.op = ALU_OP2_SUB_INT;
4038
4039 alu.dst.sel = ctx->temp_reg;
4040 alu.dst.chan = i;
4041 alu.dst.write = 1;
4042
4043 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4044 alu.src[0].sel = V_SQ_ALU_SRC_0;
4045
4046 if (i == last_inst)
4047 alu.last = 1;
4048 r = r600_bytecode_add_alu(ctx->bc, &alu);
4049 if (r)
4050 return r;
4051 }
4052
4053 /* dst = (src >= 0 ? src : tmp) */
4054 for (i = 0; i < 4; i++) {
4055 if (!(write_mask & (1<<i)))
4056 continue;
4057
4058 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4059 alu.op = ALU_OP3_CNDGE_INT;
4060 alu.is_op3 = 1;
4061 alu.dst.write = 1;
4062
4063 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4064
4065 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4066 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4067 alu.src[2].sel = ctx->temp_reg;
4068 alu.src[2].chan = i;
4069
4070 if (i == last_inst)
4071 alu.last = 1;
4072 r = r600_bytecode_add_alu(ctx->bc, &alu);
4073 if (r)
4074 return r;
4075 }
4076 return 0;
4077 }
4078
4079 static int tgsi_issg(struct r600_shader_ctx *ctx)
4080 {
4081 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4082 struct r600_bytecode_alu alu;
4083 int i, r;
4084 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4085 int last_inst = tgsi_last_instruction(write_mask);
4086
4087 /* tmp = (src >= 0 ? src : -1) */
4088 for (i = 0; i < 4; i++) {
4089 if (!(write_mask & (1<<i)))
4090 continue;
4091
4092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4093 alu.op = ALU_OP3_CNDGE_INT;
4094 alu.is_op3 = 1;
4095
4096 alu.dst.sel = ctx->temp_reg;
4097 alu.dst.chan = i;
4098 alu.dst.write = 1;
4099
4100 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4101 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4102 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
4103
4104 if (i == last_inst)
4105 alu.last = 1;
4106 r = r600_bytecode_add_alu(ctx->bc, &alu);
4107 if (r)
4108 return r;
4109 }
4110
4111 /* dst = (tmp > 0 ? 1 : tmp) */
4112 for (i = 0; i < 4; i++) {
4113 if (!(write_mask & (1<<i)))
4114 continue;
4115
4116 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4117 alu.op = ALU_OP3_CNDGT_INT;
4118 alu.is_op3 = 1;
4119 alu.dst.write = 1;
4120
4121 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4122
4123 alu.src[0].sel = ctx->temp_reg;
4124 alu.src[0].chan = i;
4125
4126 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
4127
4128 alu.src[2].sel = ctx->temp_reg;
4129 alu.src[2].chan = i;
4130
4131 if (i == last_inst)
4132 alu.last = 1;
4133 r = r600_bytecode_add_alu(ctx->bc, &alu);
4134 if (r)
4135 return r;
4136 }
4137 return 0;
4138 }
4139
4140
4141
4142 static int tgsi_ssg(struct r600_shader_ctx *ctx)
4143 {
4144 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4145 struct r600_bytecode_alu alu;
4146 int i, r;
4147
4148 /* tmp = (src > 0 ? 1 : src) */
4149 for (i = 0; i < 4; i++) {
4150 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4151 alu.op = ALU_OP3_CNDGT;
4152 alu.is_op3 = 1;
4153
4154 alu.dst.sel = ctx->temp_reg;
4155 alu.dst.chan = i;
4156
4157 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4158 alu.src[1].sel = V_SQ_ALU_SRC_1;
4159 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
4160
4161 if (i == 3)
4162 alu.last = 1;
4163 r = r600_bytecode_add_alu(ctx->bc, &alu);
4164 if (r)
4165 return r;
4166 }
4167
4168 /* dst = (-tmp > 0 ? -1 : tmp) */
4169 for (i = 0; i < 4; i++) {
4170 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4171 alu.op = ALU_OP3_CNDGT;
4172 alu.is_op3 = 1;
4173 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4174
4175 alu.src[0].sel = ctx->temp_reg;
4176 alu.src[0].chan = i;
4177 alu.src[0].neg = 1;
4178
4179 alu.src[1].sel = V_SQ_ALU_SRC_1;
4180 alu.src[1].neg = 1;
4181
4182 alu.src[2].sel = ctx->temp_reg;
4183 alu.src[2].chan = i;
4184
4185 if (i == 3)
4186 alu.last = 1;
4187 r = r600_bytecode_add_alu(ctx->bc, &alu);
4188 if (r)
4189 return r;
4190 }
4191 return 0;
4192 }
4193
4194 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
4195 {
4196 struct r600_bytecode_alu alu;
4197 int i, r;
4198
4199 for (i = 0; i < 4; i++) {
4200 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4201 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
4202 alu.op = ALU_OP0_NOP;
4203 alu.dst.chan = i;
4204 } else {
4205 alu.op = ALU_OP1_MOV;
4206 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4207 alu.src[0].sel = ctx->temp_reg;
4208 alu.src[0].chan = i;
4209 }
4210 if (i == 3) {
4211 alu.last = 1;
4212 }
4213 r = r600_bytecode_add_alu(ctx->bc, &alu);
4214 if (r)
4215 return r;
4216 }
4217 return 0;
4218 }
4219
4220 static int tgsi_op3(struct r600_shader_ctx *ctx)
4221 {
4222 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4223 struct r600_bytecode_alu alu;
4224 int i, j, r;
4225 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4226
4227 for (i = 0; i < lasti + 1; i++) {
4228 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4229 continue;
4230
4231 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4232 alu.op = ctx->inst_info->op;
4233 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4234 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4235 }
4236
4237 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4238 alu.dst.chan = i;
4239 alu.dst.write = 1;
4240 alu.is_op3 = 1;
4241 if (i == lasti) {
4242 alu.last = 1;
4243 }
4244 r = r600_bytecode_add_alu(ctx->bc, &alu);
4245 if (r)
4246 return r;
4247 }
4248 return 0;
4249 }
4250
4251 static int tgsi_dp(struct r600_shader_ctx *ctx)
4252 {
4253 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4254 struct r600_bytecode_alu alu;
4255 int i, j, r;
4256
4257 for (i = 0; i < 4; i++) {
4258 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4259 alu.op = ctx->inst_info->op;
4260 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4261 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4262 }
4263
4264 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4265 alu.dst.chan = i;
4266 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4267 /* handle some special cases */
4268 switch (ctx->inst_info->tgsi_opcode) {
4269 case TGSI_OPCODE_DP2:
4270 if (i > 1) {
4271 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4272 alu.src[0].chan = alu.src[1].chan = 0;
4273 }
4274 break;
4275 case TGSI_OPCODE_DP3:
4276 if (i > 2) {
4277 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
4278 alu.src[0].chan = alu.src[1].chan = 0;
4279 }
4280 break;
4281 case TGSI_OPCODE_DPH:
4282 if (i == 3) {
4283 alu.src[0].sel = V_SQ_ALU_SRC_1;
4284 alu.src[0].chan = 0;
4285 alu.src[0].neg = 0;
4286 }
4287 break;
4288 default:
4289 break;
4290 }
4291 if (i == 3) {
4292 alu.last = 1;
4293 }
4294 r = r600_bytecode_add_alu(ctx->bc, &alu);
4295 if (r)
4296 return r;
4297 }
4298 return 0;
4299 }
4300
4301 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
4302 unsigned index)
4303 {
4304 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4305 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
4306 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
4307 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
4308 ctx->src[index].neg || ctx->src[index].abs;
4309 }
4310
4311 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
4312 unsigned index)
4313 {
4314 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4315 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
4316 }
4317
4318 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
4319 {
4320 struct r600_bytecode_vtx vtx;
4321 struct r600_bytecode_alu alu;
4322 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4323 int src_gpr, r, i;
4324 int id = tgsi_tex_get_src_gpr(ctx, 1);
4325
4326 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4327 if (src_requires_loading) {
4328 for (i = 0; i < 4; i++) {
4329 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4330 alu.op = ALU_OP1_MOV;
4331 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4332 alu.dst.sel = ctx->temp_reg;
4333 alu.dst.chan = i;
4334 if (i == 3)
4335 alu.last = 1;
4336 alu.dst.write = 1;
4337 r = r600_bytecode_add_alu(ctx->bc, &alu);
4338 if (r)
4339 return r;
4340 }
4341 src_gpr = ctx->temp_reg;
4342 }
4343
4344 memset(&vtx, 0, sizeof(vtx));
4345 vtx.op = FETCH_OP_VFETCH;
4346 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
4347 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
4348 vtx.src_gpr = src_gpr;
4349 vtx.mega_fetch_count = 16;
4350 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
4351 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
4352 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
4353 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
4354 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
4355 vtx.use_const_fields = 1;
4356
4357 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
4358 return r;
4359
4360 if (ctx->bc->chip_class >= EVERGREEN)
4361 return 0;
4362
4363 for (i = 0; i < 4; i++) {
4364 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4365 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4366 continue;
4367
4368 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4369 alu.op = ALU_OP2_AND_INT;
4370
4371 alu.dst.chan = i;
4372 alu.dst.sel = vtx.dst_gpr;
4373 alu.dst.write = 1;
4374
4375 alu.src[0].sel = vtx.dst_gpr;
4376 alu.src[0].chan = i;
4377
4378 alu.src[1].sel = 512 + (id * 2);
4379 alu.src[1].chan = i % 4;
4380 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4381
4382 if (i == lasti)
4383 alu.last = 1;
4384 r = r600_bytecode_add_alu(ctx->bc, &alu);
4385 if (r)
4386 return r;
4387 }
4388
4389 if (inst->Dst[0].Register.WriteMask & 3) {
4390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4391 alu.op = ALU_OP2_OR_INT;
4392
4393 alu.dst.chan = 3;
4394 alu.dst.sel = vtx.dst_gpr;
4395 alu.dst.write = 1;
4396
4397 alu.src[0].sel = vtx.dst_gpr;
4398 alu.src[0].chan = 3;
4399
4400 alu.src[1].sel = 512 + (id * 2) + 1;
4401 alu.src[1].chan = 0;
4402 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4403
4404 alu.last = 1;
4405 r = r600_bytecode_add_alu(ctx->bc, &alu);
4406 if (r)
4407 return r;
4408 }
4409 return 0;
4410 }
4411
4412 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
4413 {
4414 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4415 struct r600_bytecode_alu alu;
4416 int r;
4417 int id = tgsi_tex_get_src_gpr(ctx, 1);
4418
4419 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4420 alu.op = ALU_OP1_MOV;
4421
4422 if (ctx->bc->chip_class >= EVERGREEN) {
4423 alu.src[0].sel = 512 + (id / 4);
4424 alu.src[0].chan = id % 4;
4425 } else {
4426 /* r600 we have them at channel 2 of the second dword */
4427 alu.src[0].sel = 512 + (id * 2) + 1;
4428 alu.src[0].chan = 1;
4429 }
4430 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
4431 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
4432 alu.last = 1;
4433 r = r600_bytecode_add_alu(ctx->bc, &alu);
4434 if (r)
4435 return r;
4436 return 0;
4437 }
4438
4439 static int tgsi_tex(struct r600_shader_ctx *ctx)
4440 {
4441 static float one_point_five = 1.5f;
4442 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4443 struct r600_bytecode_tex tex;
4444 struct r600_bytecode_alu alu;
4445 unsigned src_gpr;
4446 int r, i, j;
4447 int opcode;
4448 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
4449 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4450 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
4451 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
4452
4453 bool txf_add_offsets = inst->Texture.NumOffsets &&
4454 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
4455 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
4456
4457 /* Texture fetch instructions can only use gprs as source.
4458 * Also they cannot negate the source or take the absolute value */
4459 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
4460 tgsi_tex_src_requires_loading(ctx, 0)) ||
4461 read_compressed_msaa || txf_add_offsets;
4462
4463 boolean src_loaded = FALSE;
4464 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
4465 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
4466 boolean has_txq_cube_array_z = false;
4467
4468 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
4469 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4470 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
4471 if (inst->Dst[0].Register.WriteMask & 4) {
4472 ctx->shader->has_txq_cube_array_z_comp = true;
4473 has_txq_cube_array_z = true;
4474 }
4475
4476 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
4477 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4478 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
4479 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
4480 sampler_src_reg = 2;
4481
4482 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
4483
4484 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
4485 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
4486 ctx->shader->uses_tex_buffers = true;
4487 return r600_do_buffer_txq(ctx);
4488 }
4489 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
4490 if (ctx->bc->chip_class < EVERGREEN)
4491 ctx->shader->uses_tex_buffers = true;
4492 return do_vtx_fetch_inst(ctx, src_requires_loading);
4493 }
4494 }
4495
4496 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
4497 /* TGSI moves the sampler to src reg 3 for TXD */
4498 sampler_src_reg = 3;
4499
4500 for (i = 1; i < 3; i++) {
4501 /* set gradients h/v */
4502 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4503 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
4504 FETCH_OP_SET_GRADIENTS_V;
4505 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4506 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4507
4508 if (tgsi_tex_src_requires_loading(ctx, i)) {
4509 tex.src_gpr = r600_get_temp(ctx);
4510 tex.src_sel_x = 0;
4511 tex.src_sel_y = 1;
4512 tex.src_sel_z = 2;
4513 tex.src_sel_w = 3;
4514
4515 for (j = 0; j < 4; j++) {
4516 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4517 alu.op = ALU_OP1_MOV;
4518 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
4519 alu.dst.sel = tex.src_gpr;
4520 alu.dst.chan = j;
4521 if (j == 3)
4522 alu.last = 1;
4523 alu.dst.write = 1;
4524 r = r600_bytecode_add_alu(ctx->bc, &alu);
4525 if (r)
4526 return r;
4527 }
4528
4529 } else {
4530 tex.src_gpr = tgsi_tex_get_src_gpr(ctx, i);
4531 tex.src_sel_x = ctx->src[i].swizzle[0];
4532 tex.src_sel_y = ctx->src[i].swizzle[1];
4533 tex.src_sel_z = ctx->src[i].swizzle[2];
4534 tex.src_sel_w = ctx->src[i].swizzle[3];
4535 tex.src_rel = ctx->src[i].rel;
4536 }
4537 tex.dst_gpr = ctx->temp_reg; /* just to avoid confusing the asm scheduler */
4538 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4539 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
4540 tex.coord_type_x = 1;
4541 tex.coord_type_y = 1;
4542 tex.coord_type_z = 1;
4543 tex.coord_type_w = 1;
4544 }
4545 r = r600_bytecode_add_tex(ctx->bc, &tex);
4546 if (r)
4547 return r;
4548 }
4549 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
4550 int out_chan;
4551 /* Add perspective divide */
4552 if (ctx->bc->chip_class == CAYMAN) {
4553 out_chan = 2;
4554 for (i = 0; i < 3; i++) {
4555 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4556 alu.op = ALU_OP1_RECIP_IEEE;
4557 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4558
4559 alu.dst.sel = ctx->temp_reg;
4560 alu.dst.chan = i;
4561 if (i == 2)
4562 alu.last = 1;
4563 if (out_chan == i)
4564 alu.dst.write = 1;
4565 r = r600_bytecode_add_alu(ctx->bc, &alu);
4566 if (r)
4567 return r;
4568 }
4569
4570 } else {
4571 out_chan = 3;
4572 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4573 alu.op = ALU_OP1_RECIP_IEEE;
4574 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4575
4576 alu.dst.sel = ctx->temp_reg;
4577 alu.dst.chan = out_chan;
4578 alu.last = 1;
4579 alu.dst.write = 1;
4580 r = r600_bytecode_add_alu(ctx->bc, &alu);
4581 if (r)
4582 return r;
4583 }
4584
4585 for (i = 0; i < 3; i++) {
4586 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4587 alu.op = ALU_OP2_MUL;
4588 alu.src[0].sel = ctx->temp_reg;
4589 alu.src[0].chan = out_chan;
4590 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4591 alu.dst.sel = ctx->temp_reg;
4592 alu.dst.chan = i;
4593 alu.dst.write = 1;
4594 r = r600_bytecode_add_alu(ctx->bc, &alu);
4595 if (r)
4596 return r;
4597 }
4598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4599 alu.op = ALU_OP1_MOV;
4600 alu.src[0].sel = V_SQ_ALU_SRC_1;
4601 alu.src[0].chan = 0;
4602 alu.dst.sel = ctx->temp_reg;
4603 alu.dst.chan = 3;
4604 alu.last = 1;
4605 alu.dst.write = 1;
4606 r = r600_bytecode_add_alu(ctx->bc, &alu);
4607 if (r)
4608 return r;
4609 src_loaded = TRUE;
4610 src_gpr = ctx->temp_reg;
4611 }
4612
4613 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
4614 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4615 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4616 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
4617 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
4618 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4619
4620 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
4621 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
4622
4623 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
4624 for (i = 0; i < 4; i++) {
4625 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4626 alu.op = ALU_OP2_CUBE;
4627 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
4628 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
4629 alu.dst.sel = ctx->temp_reg;
4630 alu.dst.chan = i;
4631 if (i == 3)
4632 alu.last = 1;
4633 alu.dst.write = 1;
4634 r = r600_bytecode_add_alu(ctx->bc, &alu);
4635 if (r)
4636 return r;
4637 }
4638
4639 /* tmp1.z = RCP_e(|tmp1.z|) */
4640 if (ctx->bc->chip_class == CAYMAN) {
4641 for (i = 0; i < 3; i++) {
4642 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4643 alu.op = ALU_OP1_RECIP_IEEE;
4644 alu.src[0].sel = ctx->temp_reg;
4645 alu.src[0].chan = 2;
4646 alu.src[0].abs = 1;
4647 alu.dst.sel = ctx->temp_reg;
4648 alu.dst.chan = i;
4649 if (i == 2)
4650 alu.dst.write = 1;
4651 if (i == 2)
4652 alu.last = 1;
4653 r = r600_bytecode_add_alu(ctx->bc, &alu);
4654 if (r)
4655 return r;
4656 }
4657 } else {
4658 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4659 alu.op = ALU_OP1_RECIP_IEEE;
4660 alu.src[0].sel = ctx->temp_reg;
4661 alu.src[0].chan = 2;
4662 alu.src[0].abs = 1;
4663 alu.dst.sel = ctx->temp_reg;
4664 alu.dst.chan = 2;
4665 alu.dst.write = 1;
4666 alu.last = 1;
4667 r = r600_bytecode_add_alu(ctx->bc, &alu);
4668 if (r)
4669 return r;
4670 }
4671
4672 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
4673 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
4674 * muladd has no writemask, have to use another temp
4675 */
4676 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4677 alu.op = ALU_OP3_MULADD;
4678 alu.is_op3 = 1;
4679
4680 alu.src[0].sel = ctx->temp_reg;
4681 alu.src[0].chan = 0;
4682 alu.src[1].sel = ctx->temp_reg;
4683 alu.src[1].chan = 2;
4684
4685 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4686 alu.src[2].chan = 0;
4687 alu.src[2].value = *(uint32_t *)&one_point_five;
4688
4689 alu.dst.sel = ctx->temp_reg;
4690 alu.dst.chan = 0;
4691 alu.dst.write = 1;
4692
4693 r = r600_bytecode_add_alu(ctx->bc, &alu);
4694 if (r)
4695 return r;
4696
4697 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4698 alu.op = ALU_OP3_MULADD;
4699 alu.is_op3 = 1;
4700
4701 alu.src[0].sel = ctx->temp_reg;
4702 alu.src[0].chan = 1;
4703 alu.src[1].sel = ctx->temp_reg;
4704 alu.src[1].chan = 2;
4705
4706 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4707 alu.src[2].chan = 0;
4708 alu.src[2].value = *(uint32_t *)&one_point_five;
4709
4710 alu.dst.sel = ctx->temp_reg;
4711 alu.dst.chan = 1;
4712 alu.dst.write = 1;
4713
4714 alu.last = 1;
4715 r = r600_bytecode_add_alu(ctx->bc, &alu);
4716 if (r)
4717 return r;
4718 /* write initial compare value into Z component
4719 - W src 0 for shadow cube
4720 - X src 1 for shadow cube array */
4721 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
4722 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4723 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4724 alu.op = ALU_OP1_MOV;
4725 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4726 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4727 else
4728 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4729 alu.dst.sel = ctx->temp_reg;
4730 alu.dst.chan = 2;
4731 alu.dst.write = 1;
4732 alu.last = 1;
4733 r = r600_bytecode_add_alu(ctx->bc, &alu);
4734 if (r)
4735 return r;
4736 }
4737
4738 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
4739 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4740 if (ctx->bc->chip_class >= EVERGREEN) {
4741 int mytmp = r600_get_temp(ctx);
4742 static const float eight = 8.0f;
4743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4744 alu.op = ALU_OP1_MOV;
4745 alu.src[0].sel = ctx->temp_reg;
4746 alu.src[0].chan = 3;
4747 alu.dst.sel = mytmp;
4748 alu.dst.chan = 0;
4749 alu.dst.write = 1;
4750 alu.last = 1;
4751 r = r600_bytecode_add_alu(ctx->bc, &alu);
4752 if (r)
4753 return r;
4754
4755 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
4756 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4757 alu.op = ALU_OP3_MULADD;
4758 alu.is_op3 = 1;
4759 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4760 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4761 alu.src[1].chan = 0;
4762 alu.src[1].value = *(uint32_t *)&eight;
4763 alu.src[2].sel = mytmp;
4764 alu.src[2].chan = 0;
4765 alu.dst.sel = ctx->temp_reg;
4766 alu.dst.chan = 3;
4767 alu.dst.write = 1;
4768 alu.last = 1;
4769 r = r600_bytecode_add_alu(ctx->bc, &alu);
4770 if (r)
4771 return r;
4772 } else if (ctx->bc->chip_class < EVERGREEN) {
4773 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4774 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
4775 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4776 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4777 tex.src_gpr = r600_get_temp(ctx);
4778 tex.src_sel_x = 0;
4779 tex.src_sel_y = 0;
4780 tex.src_sel_z = 0;
4781 tex.src_sel_w = 0;
4782 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
4783 tex.coord_type_x = 1;
4784 tex.coord_type_y = 1;
4785 tex.coord_type_z = 1;
4786 tex.coord_type_w = 1;
4787 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4788 alu.op = ALU_OP1_MOV;
4789 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4790 alu.dst.sel = tex.src_gpr;
4791 alu.dst.chan = 0;
4792 alu.last = 1;
4793 alu.dst.write = 1;
4794 r = r600_bytecode_add_alu(ctx->bc, &alu);
4795 if (r)
4796 return r;
4797
4798 r = r600_bytecode_add_tex(ctx->bc, &tex);
4799 if (r)
4800 return r;
4801 }
4802
4803 }
4804
4805 /* for cube forms of lod and bias we need to route things */
4806 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4807 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
4808 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4809 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
4810 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4811 alu.op = ALU_OP1_MOV;
4812 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
4813 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
4814 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
4815 else
4816 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
4817 alu.dst.sel = ctx->temp_reg;
4818 alu.dst.chan = 2;
4819 alu.last = 1;
4820 alu.dst.write = 1;
4821 r = r600_bytecode_add_alu(ctx->bc, &alu);
4822 if (r)
4823 return r;
4824 }
4825
4826 src_loaded = TRUE;
4827 src_gpr = ctx->temp_reg;
4828 }
4829
4830 if (src_requires_loading && !src_loaded) {
4831 for (i = 0; i < 4; i++) {
4832 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4833 alu.op = ALU_OP1_MOV;
4834 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4835 alu.dst.sel = ctx->temp_reg;
4836 alu.dst.chan = i;
4837 if (i == 3)
4838 alu.last = 1;
4839 alu.dst.write = 1;
4840 r = r600_bytecode_add_alu(ctx->bc, &alu);
4841 if (r)
4842 return r;
4843 }
4844 src_loaded = TRUE;
4845 src_gpr = ctx->temp_reg;
4846 }
4847
4848 /* get offset values */
4849 if (inst->Texture.NumOffsets) {
4850 assert(inst->Texture.NumOffsets == 1);
4851
4852 /* The texture offset feature doesn't work with the TXF instruction
4853 * and must be emulated by adding the offset to the texture coordinates. */
4854 if (txf_add_offsets) {
4855 const struct tgsi_texture_offset *off = inst->TexOffsets;
4856
4857 switch (inst->Texture.Texture) {
4858 case TGSI_TEXTURE_3D:
4859 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4860 alu.op = ALU_OP2_ADD_INT;
4861 alu.src[0].sel = src_gpr;
4862 alu.src[0].chan = 2;
4863 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4864 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
4865 alu.dst.sel = src_gpr;
4866 alu.dst.chan = 2;
4867 alu.dst.write = 1;
4868 alu.last = 1;
4869 r = r600_bytecode_add_alu(ctx->bc, &alu);
4870 if (r)
4871 return r;
4872 /* fall through */
4873
4874 case TGSI_TEXTURE_2D:
4875 case TGSI_TEXTURE_SHADOW2D:
4876 case TGSI_TEXTURE_RECT:
4877 case TGSI_TEXTURE_SHADOWRECT:
4878 case TGSI_TEXTURE_2D_ARRAY:
4879 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4880 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4881 alu.op = ALU_OP2_ADD_INT;
4882 alu.src[0].sel = src_gpr;
4883 alu.src[0].chan = 1;
4884 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4885 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
4886 alu.dst.sel = src_gpr;
4887 alu.dst.chan = 1;
4888 alu.dst.write = 1;
4889 alu.last = 1;
4890 r = r600_bytecode_add_alu(ctx->bc, &alu);
4891 if (r)
4892 return r;
4893 /* fall through */
4894
4895 case TGSI_TEXTURE_1D:
4896 case TGSI_TEXTURE_SHADOW1D:
4897 case TGSI_TEXTURE_1D_ARRAY:
4898 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4900 alu.op = ALU_OP2_ADD_INT;
4901 alu.src[0].sel = src_gpr;
4902 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4903 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
4904 alu.dst.sel = src_gpr;
4905 alu.dst.write = 1;
4906 alu.last = 1;
4907 r = r600_bytecode_add_alu(ctx->bc, &alu);
4908 if (r)
4909 return r;
4910 break;
4911 /* texture offsets do not apply to other texture targets */
4912 }
4913 } else {
4914 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
4915 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
4916 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
4917 }
4918 }
4919
4920 /* Obtain the sample index for reading a compressed MSAA color texture.
4921 * To read the FMASK, we use the ldfptr instruction, which tells us
4922 * where the samples are stored.
4923 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
4924 * which is the identity mapping. Each nibble says which physical sample
4925 * should be fetched to get that sample.
4926 *
4927 * Assume src.z contains the sample index. It should be modified like this:
4928 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
4929 * Then fetch the texel with src.
4930 */
4931 if (read_compressed_msaa) {
4932 unsigned sample_chan = 3;
4933 unsigned temp = r600_get_temp(ctx);
4934 assert(src_loaded);
4935
4936 /* temp.w = ldfptr() */
4937 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
4938 tex.op = FETCH_OP_LD;
4939 tex.inst_mod = 1; /* to indicate this is ldfptr */
4940 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
4941 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
4942 tex.src_gpr = src_gpr;
4943 tex.dst_gpr = temp;
4944 tex.dst_sel_x = 7; /* mask out these components */
4945 tex.dst_sel_y = 7;
4946 tex.dst_sel_z = 7;
4947 tex.dst_sel_w = 0; /* store X */
4948 tex.src_sel_x = 0;
4949 tex.src_sel_y = 1;
4950 tex.src_sel_z = 2;
4951 tex.src_sel_w = 3;
4952 tex.offset_x = offset_x;
4953 tex.offset_y = offset_y;
4954 tex.offset_z = offset_z;
4955 r = r600_bytecode_add_tex(ctx->bc, &tex);
4956 if (r)
4957 return r;
4958
4959 /* temp.x = sample_index*4 */
4960 if (ctx->bc->chip_class == CAYMAN) {
4961 for (i = 0 ; i < 4; i++) {
4962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4963 alu.op = ALU_OP2_MULLO_INT;
4964 alu.src[0].sel = src_gpr;
4965 alu.src[0].chan = sample_chan;
4966 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4967 alu.src[1].value = 4;
4968 alu.dst.sel = temp;
4969 alu.dst.chan = i;
4970 alu.dst.write = i == 0;
4971 if (i == 3)
4972 alu.last = 1;
4973 r = r600_bytecode_add_alu(ctx->bc, &alu);
4974 if (r)
4975 return r;
4976 }
4977 } else {
4978 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4979 alu.op = ALU_OP2_MULLO_INT;
4980 alu.src[0].sel = src_gpr;
4981 alu.src[0].chan = sample_chan;
4982 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4983 alu.src[1].value = 4;
4984 alu.dst.sel = temp;
4985 alu.dst.chan = 0;
4986 alu.dst.write = 1;
4987 alu.last = 1;
4988 r = r600_bytecode_add_alu(ctx->bc, &alu);
4989 if (r)
4990 return r;
4991 }
4992
4993 /* sample_index = temp.w >> temp.x */
4994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4995 alu.op = ALU_OP2_LSHR_INT;
4996 alu.src[0].sel = temp;
4997 alu.src[0].chan = 3;
4998 alu.src[1].sel = temp;
4999 alu.src[1].chan = 0;
5000 alu.dst.sel = src_gpr;
5001 alu.dst.chan = sample_chan;
5002 alu.dst.write = 1;
5003 alu.last = 1;
5004 r = r600_bytecode_add_alu(ctx->bc, &alu);
5005 if (r)
5006 return r;
5007
5008 /* sample_index & 0xF */
5009 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5010 alu.op = ALU_OP2_AND_INT;
5011 alu.src[0].sel = src_gpr;
5012 alu.src[0].chan = sample_chan;
5013 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5014 alu.src[1].value = 0xF;
5015 alu.dst.sel = src_gpr;
5016 alu.dst.chan = sample_chan;
5017 alu.dst.write = 1;
5018 alu.last = 1;
5019 r = r600_bytecode_add_alu(ctx->bc, &alu);
5020 if (r)
5021 return r;
5022 #if 0
5023 /* visualize the FMASK */
5024 for (i = 0; i < 4; i++) {
5025 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5026 alu.op = ALU_OP1_INT_TO_FLT;
5027 alu.src[0].sel = src_gpr;
5028 alu.src[0].chan = sample_chan;
5029 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5030 alu.dst.chan = i;
5031 alu.dst.write = 1;
5032 alu.last = 1;
5033 r = r600_bytecode_add_alu(ctx->bc, &alu);
5034 if (r)
5035 return r;
5036 }
5037 return 0;
5038 #endif
5039 }
5040
5041 /* does this shader want a num layers from TXQ for a cube array? */
5042 if (has_txq_cube_array_z) {
5043 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5044
5045 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5046 alu.op = ALU_OP1_MOV;
5047
5048 alu.src[0].sel = 512 + (id / 4);
5049 alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
5050 alu.src[0].chan = id % 4;
5051 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5052 alu.last = 1;
5053 r = r600_bytecode_add_alu(ctx->bc, &alu);
5054 if (r)
5055 return r;
5056 /* disable writemask from texture instruction */
5057 inst->Dst[0].Register.WriteMask &= ~4;
5058 }
5059
5060 opcode = ctx->inst_info->op;
5061 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
5062 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
5063 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
5064 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5065 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
5066 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
5067 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5068 switch (opcode) {
5069 case FETCH_OP_SAMPLE:
5070 opcode = FETCH_OP_SAMPLE_C;
5071 break;
5072 case FETCH_OP_SAMPLE_L:
5073 opcode = FETCH_OP_SAMPLE_C_L;
5074 break;
5075 case FETCH_OP_SAMPLE_LB:
5076 opcode = FETCH_OP_SAMPLE_C_LB;
5077 break;
5078 case FETCH_OP_SAMPLE_G:
5079 opcode = FETCH_OP_SAMPLE_C_G;
5080 break;
5081 /* Texture gather variants */
5082 case FETCH_OP_GATHER4:
5083 tex.op = FETCH_OP_GATHER4_C;
5084 break;
5085 case FETCH_OP_GATHER4_O:
5086 tex.op = FETCH_OP_GATHER4_C_O;
5087 break;
5088 }
5089 }
5090
5091 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
5092 tex.op = opcode;
5093
5094 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
5095 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
5096 tex.src_gpr = src_gpr;
5097 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
5098
5099 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
5100 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
5101 tex.inst_mod = texture_component_select;
5102
5103 /* GATHER4 result order is different from TGSI TG4 */
5104 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5105 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
5106 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5107 }
5108 else {
5109 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
5110 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
5111 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
5112 }
5113 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
5114
5115 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
5116 tex.src_sel_x = 4;
5117 tex.src_sel_y = 4;
5118 tex.src_sel_z = 4;
5119 tex.src_sel_w = 4;
5120 } else if (src_loaded) {
5121 tex.src_sel_x = 0;
5122 tex.src_sel_y = 1;
5123 tex.src_sel_z = 2;
5124 tex.src_sel_w = 3;
5125 } else {
5126 tex.src_sel_x = ctx->src[0].swizzle[0];
5127 tex.src_sel_y = ctx->src[0].swizzle[1];
5128 tex.src_sel_z = ctx->src[0].swizzle[2];
5129 tex.src_sel_w = ctx->src[0].swizzle[3];
5130 tex.src_rel = ctx->src[0].rel;
5131 }
5132
5133 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
5134 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
5135 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5136 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
5137 tex.src_sel_x = 1;
5138 tex.src_sel_y = 0;
5139 tex.src_sel_z = 3;
5140 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
5141 }
5142
5143 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
5144 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
5145 tex.coord_type_x = 1;
5146 tex.coord_type_y = 1;
5147 }
5148 tex.coord_type_z = 1;
5149 tex.coord_type_w = 1;
5150
5151 tex.offset_x = offset_x;
5152 tex.offset_y = offset_y;
5153 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
5154 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY) {
5155 tex.offset_z = 0;
5156 }
5157 else {
5158 tex.offset_z = offset_z;
5159 }
5160
5161 /* Put the depth for comparison in W.
5162 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
5163 * Some instructions expect the depth in Z. */
5164 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
5165 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
5166 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
5167 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
5168 opcode != FETCH_OP_SAMPLE_C_L &&
5169 opcode != FETCH_OP_SAMPLE_C_LB) {
5170 tex.src_sel_w = tex.src_sel_z;
5171 }
5172
5173 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
5174 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
5175 if (opcode == FETCH_OP_SAMPLE_C_L ||
5176 opcode == FETCH_OP_SAMPLE_C_LB) {
5177 /* the array index is read from Y */
5178 tex.coord_type_y = 0;
5179 } else {
5180 /* the array index is read from Z */
5181 tex.coord_type_z = 0;
5182 tex.src_sel_z = tex.src_sel_y;
5183 }
5184 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
5185 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
5186 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
5187 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
5188 (ctx->bc->chip_class >= EVERGREEN)))
5189 /* the array index is read from Z */
5190 tex.coord_type_z = 0;
5191
5192 /* mask unused source components */
5193 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
5194 switch (inst->Texture.Texture) {
5195 case TGSI_TEXTURE_2D:
5196 case TGSI_TEXTURE_RECT:
5197 tex.src_sel_z = 7;
5198 tex.src_sel_w = 7;
5199 break;
5200 case TGSI_TEXTURE_1D_ARRAY:
5201 tex.src_sel_y = 7;
5202 tex.src_sel_w = 7;
5203 break;
5204 case TGSI_TEXTURE_1D:
5205 tex.src_sel_y = 7;
5206 tex.src_sel_z = 7;
5207 tex.src_sel_w = 7;
5208 break;
5209 }
5210 }
5211
5212 r = r600_bytecode_add_tex(ctx->bc, &tex);
5213 if (r)
5214 return r;
5215
5216 /* add shadow ambient support - gallium doesn't do it yet */
5217 return 0;
5218 }
5219
5220 static int tgsi_lrp(struct r600_shader_ctx *ctx)
5221 {
5222 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5223 struct r600_bytecode_alu alu;
5224 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5225 unsigned i;
5226 int r;
5227
5228 /* optimize if it's just an equal balance */
5229 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
5230 for (i = 0; i < lasti + 1; i++) {
5231 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5232 continue;
5233
5234 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5235 alu.op = ALU_OP2_ADD;
5236 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5237 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5238 alu.omod = 3;
5239 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5240 alu.dst.chan = i;
5241 if (i == lasti) {
5242 alu.last = 1;
5243 }
5244 r = r600_bytecode_add_alu(ctx->bc, &alu);
5245 if (r)
5246 return r;
5247 }
5248 return 0;
5249 }
5250
5251 /* 1 - src0 */
5252 for (i = 0; i < lasti + 1; i++) {
5253 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5254 continue;
5255
5256 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5257 alu.op = ALU_OP2_ADD;
5258 alu.src[0].sel = V_SQ_ALU_SRC_1;
5259 alu.src[0].chan = 0;
5260 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5261 r600_bytecode_src_toggle_neg(&alu.src[1]);
5262 alu.dst.sel = ctx->temp_reg;
5263 alu.dst.chan = i;
5264 if (i == lasti) {
5265 alu.last = 1;
5266 }
5267 alu.dst.write = 1;
5268 r = r600_bytecode_add_alu(ctx->bc, &alu);
5269 if (r)
5270 return r;
5271 }
5272
5273 /* (1 - src0) * src2 */
5274 for (i = 0; i < lasti + 1; i++) {
5275 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5276 continue;
5277
5278 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5279 alu.op = ALU_OP2_MUL;
5280 alu.src[0].sel = ctx->temp_reg;
5281 alu.src[0].chan = i;
5282 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5283 alu.dst.sel = ctx->temp_reg;
5284 alu.dst.chan = i;
5285 if (i == lasti) {
5286 alu.last = 1;
5287 }
5288 alu.dst.write = 1;
5289 r = r600_bytecode_add_alu(ctx->bc, &alu);
5290 if (r)
5291 return r;
5292 }
5293
5294 /* src0 * src1 + (1 - src0) * src2 */
5295 for (i = 0; i < lasti + 1; i++) {
5296 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5297 continue;
5298
5299 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5300 alu.op = ALU_OP3_MULADD;
5301 alu.is_op3 = 1;
5302 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5303 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5304 alu.src[2].sel = ctx->temp_reg;
5305 alu.src[2].chan = i;
5306
5307 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5308 alu.dst.chan = i;
5309 if (i == lasti) {
5310 alu.last = 1;
5311 }
5312 r = r600_bytecode_add_alu(ctx->bc, &alu);
5313 if (r)
5314 return r;
5315 }
5316 return 0;
5317 }
5318
5319 static int tgsi_cmp(struct r600_shader_ctx *ctx)
5320 {
5321 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5322 struct r600_bytecode_alu alu;
5323 int i, r;
5324 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5325
5326 for (i = 0; i < lasti + 1; i++) {
5327 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5328 continue;
5329
5330 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5331 alu.op = ALU_OP3_CNDGE;
5332 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5333 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5334 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
5335 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5336 alu.dst.chan = i;
5337 alu.dst.write = 1;
5338 alu.is_op3 = 1;
5339 if (i == lasti)
5340 alu.last = 1;
5341 r = r600_bytecode_add_alu(ctx->bc, &alu);
5342 if (r)
5343 return r;
5344 }
5345 return 0;
5346 }
5347
5348 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
5349 {
5350 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5351 struct r600_bytecode_alu alu;
5352 int i, r;
5353 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5354
5355 for (i = 0; i < lasti + 1; i++) {
5356 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5357 continue;
5358
5359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5360 alu.op = ALU_OP3_CNDGE_INT;
5361 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5362 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
5363 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
5364 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5365 alu.dst.chan = i;
5366 alu.dst.write = 1;
5367 alu.is_op3 = 1;
5368 if (i == lasti)
5369 alu.last = 1;
5370 r = r600_bytecode_add_alu(ctx->bc, &alu);
5371 if (r)
5372 return r;
5373 }
5374 return 0;
5375 }
5376
5377 static int tgsi_xpd(struct r600_shader_ctx *ctx)
5378 {
5379 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5380 static const unsigned int src0_swizzle[] = {2, 0, 1};
5381 static const unsigned int src1_swizzle[] = {1, 2, 0};
5382 struct r600_bytecode_alu alu;
5383 uint32_t use_temp = 0;
5384 int i, r;
5385
5386 if (inst->Dst[0].Register.WriteMask != 0xf)
5387 use_temp = 1;
5388
5389 for (i = 0; i < 4; i++) {
5390 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5391 alu.op = ALU_OP2_MUL;
5392 if (i < 3) {
5393 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
5394 r600_bytecode_src(&alu.src[1], &ctx->src[1], src1_swizzle[i]);
5395 } else {
5396 alu.src[0].sel = V_SQ_ALU_SRC_0;
5397 alu.src[0].chan = i;
5398 alu.src[1].sel = V_SQ_ALU_SRC_0;
5399 alu.src[1].chan = i;
5400 }
5401
5402 alu.dst.sel = ctx->temp_reg;
5403 alu.dst.chan = i;
5404 alu.dst.write = 1;
5405
5406 if (i == 3)
5407 alu.last = 1;
5408 r = r600_bytecode_add_alu(ctx->bc, &alu);
5409 if (r)
5410 return r;
5411 }
5412
5413 for (i = 0; i < 4; i++) {
5414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5415 alu.op = ALU_OP3_MULADD;
5416
5417 if (i < 3) {
5418 r600_bytecode_src(&alu.src[0], &ctx->src[0], src1_swizzle[i]);
5419 r600_bytecode_src(&alu.src[1], &ctx->src[1], src0_swizzle[i]);
5420 } else {
5421 alu.src[0].sel = V_SQ_ALU_SRC_0;
5422 alu.src[0].chan = i;
5423 alu.src[1].sel = V_SQ_ALU_SRC_0;
5424 alu.src[1].chan = i;
5425 }
5426
5427 alu.src[2].sel = ctx->temp_reg;
5428 alu.src[2].neg = 1;
5429 alu.src[2].chan = i;
5430
5431 if (use_temp)
5432 alu.dst.sel = ctx->temp_reg;
5433 else
5434 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5435 alu.dst.chan = i;
5436 alu.dst.write = 1;
5437 alu.is_op3 = 1;
5438 if (i == 3)
5439 alu.last = 1;
5440 r = r600_bytecode_add_alu(ctx->bc, &alu);
5441 if (r)
5442 return r;
5443 }
5444 if (use_temp)
5445 return tgsi_helper_copy(ctx, inst);
5446 return 0;
5447 }
5448
5449 static int tgsi_exp(struct r600_shader_ctx *ctx)
5450 {
5451 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5452 struct r600_bytecode_alu alu;
5453 int r;
5454 int i;
5455
5456 /* result.x = 2^floor(src); */
5457 if (inst->Dst[0].Register.WriteMask & 1) {
5458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5459
5460 alu.op = ALU_OP1_FLOOR;
5461 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5462
5463 alu.dst.sel = ctx->temp_reg;
5464 alu.dst.chan = 0;
5465 alu.dst.write = 1;
5466 alu.last = 1;
5467 r = r600_bytecode_add_alu(ctx->bc, &alu);
5468 if (r)
5469 return r;
5470
5471 if (ctx->bc->chip_class == CAYMAN) {
5472 for (i = 0; i < 3; i++) {
5473 alu.op = ALU_OP1_EXP_IEEE;
5474 alu.src[0].sel = ctx->temp_reg;
5475 alu.src[0].chan = 0;
5476
5477 alu.dst.sel = ctx->temp_reg;
5478 alu.dst.chan = i;
5479 alu.dst.write = i == 0;
5480 alu.last = i == 2;
5481 r = r600_bytecode_add_alu(ctx->bc, &alu);
5482 if (r)
5483 return r;
5484 }
5485 } else {
5486 alu.op = ALU_OP1_EXP_IEEE;
5487 alu.src[0].sel = ctx->temp_reg;
5488 alu.src[0].chan = 0;
5489
5490 alu.dst.sel = ctx->temp_reg;
5491 alu.dst.chan = 0;
5492 alu.dst.write = 1;
5493 alu.last = 1;
5494 r = r600_bytecode_add_alu(ctx->bc, &alu);
5495 if (r)
5496 return r;
5497 }
5498 }
5499
5500 /* result.y = tmp - floor(tmp); */
5501 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5502 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5503
5504 alu.op = ALU_OP1_FRACT;
5505 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5506
5507 alu.dst.sel = ctx->temp_reg;
5508 #if 0
5509 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5510 if (r)
5511 return r;
5512 #endif
5513 alu.dst.write = 1;
5514 alu.dst.chan = 1;
5515
5516 alu.last = 1;
5517
5518 r = r600_bytecode_add_alu(ctx->bc, &alu);
5519 if (r)
5520 return r;
5521 }
5522
5523 /* result.z = RoughApprox2ToX(tmp);*/
5524 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
5525 if (ctx->bc->chip_class == CAYMAN) {
5526 for (i = 0; i < 3; i++) {
5527 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5528 alu.op = ALU_OP1_EXP_IEEE;
5529 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5530
5531 alu.dst.sel = ctx->temp_reg;
5532 alu.dst.chan = i;
5533 if (i == 2) {
5534 alu.dst.write = 1;
5535 alu.last = 1;
5536 }
5537
5538 r = r600_bytecode_add_alu(ctx->bc, &alu);
5539 if (r)
5540 return r;
5541 }
5542 } else {
5543 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5544 alu.op = ALU_OP1_EXP_IEEE;
5545 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5546
5547 alu.dst.sel = ctx->temp_reg;
5548 alu.dst.write = 1;
5549 alu.dst.chan = 2;
5550
5551 alu.last = 1;
5552
5553 r = r600_bytecode_add_alu(ctx->bc, &alu);
5554 if (r)
5555 return r;
5556 }
5557 }
5558
5559 /* result.w = 1.0;*/
5560 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
5561 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5562
5563 alu.op = ALU_OP1_MOV;
5564 alu.src[0].sel = V_SQ_ALU_SRC_1;
5565 alu.src[0].chan = 0;
5566
5567 alu.dst.sel = ctx->temp_reg;
5568 alu.dst.chan = 3;
5569 alu.dst.write = 1;
5570 alu.last = 1;
5571 r = r600_bytecode_add_alu(ctx->bc, &alu);
5572 if (r)
5573 return r;
5574 }
5575 return tgsi_helper_copy(ctx, inst);
5576 }
5577
5578 static int tgsi_log(struct r600_shader_ctx *ctx)
5579 {
5580 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5581 struct r600_bytecode_alu alu;
5582 int r;
5583 int i;
5584
5585 /* result.x = floor(log2(|src|)); */
5586 if (inst->Dst[0].Register.WriteMask & 1) {
5587 if (ctx->bc->chip_class == CAYMAN) {
5588 for (i = 0; i < 3; i++) {
5589 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5590
5591 alu.op = ALU_OP1_LOG_IEEE;
5592 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5593 r600_bytecode_src_set_abs(&alu.src[0]);
5594
5595 alu.dst.sel = ctx->temp_reg;
5596 alu.dst.chan = i;
5597 if (i == 0)
5598 alu.dst.write = 1;
5599 if (i == 2)
5600 alu.last = 1;
5601 r = r600_bytecode_add_alu(ctx->bc, &alu);
5602 if (r)
5603 return r;
5604 }
5605
5606 } else {
5607 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5608
5609 alu.op = ALU_OP1_LOG_IEEE;
5610 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5611 r600_bytecode_src_set_abs(&alu.src[0]);
5612
5613 alu.dst.sel = ctx->temp_reg;
5614 alu.dst.chan = 0;
5615 alu.dst.write = 1;
5616 alu.last = 1;
5617 r = r600_bytecode_add_alu(ctx->bc, &alu);
5618 if (r)
5619 return r;
5620 }
5621
5622 alu.op = ALU_OP1_FLOOR;
5623 alu.src[0].sel = ctx->temp_reg;
5624 alu.src[0].chan = 0;
5625
5626 alu.dst.sel = ctx->temp_reg;
5627 alu.dst.chan = 0;
5628 alu.dst.write = 1;
5629 alu.last = 1;
5630
5631 r = r600_bytecode_add_alu(ctx->bc, &alu);
5632 if (r)
5633 return r;
5634 }
5635
5636 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
5637 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
5638
5639 if (ctx->bc->chip_class == CAYMAN) {
5640 for (i = 0; i < 3; i++) {
5641 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5642
5643 alu.op = ALU_OP1_LOG_IEEE;
5644 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5645 r600_bytecode_src_set_abs(&alu.src[0]);
5646
5647 alu.dst.sel = ctx->temp_reg;
5648 alu.dst.chan = i;
5649 if (i == 1)
5650 alu.dst.write = 1;
5651 if (i == 2)
5652 alu.last = 1;
5653
5654 r = r600_bytecode_add_alu(ctx->bc, &alu);
5655 if (r)
5656 return r;
5657 }
5658 } else {
5659 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5660
5661 alu.op = ALU_OP1_LOG_IEEE;
5662 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5663 r600_bytecode_src_set_abs(&alu.src[0]);
5664
5665 alu.dst.sel = ctx->temp_reg;
5666 alu.dst.chan = 1;
5667 alu.dst.write = 1;
5668 alu.last = 1;
5669
5670 r = r600_bytecode_add_alu(ctx->bc, &alu);
5671 if (r)
5672 return r;
5673 }
5674
5675 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5676
5677 alu.op = ALU_OP1_FLOOR;
5678 alu.src[0].sel = ctx->temp_reg;
5679 alu.src[0].chan = 1;
5680
5681 alu.dst.sel = ctx->temp_reg;
5682 alu.dst.chan = 1;
5683 alu.dst.write = 1;
5684 alu.last = 1;
5685
5686 r = r600_bytecode_add_alu(ctx->bc, &alu);
5687 if (r)
5688 return r;
5689
5690 if (ctx->bc->chip_class == CAYMAN) {
5691 for (i = 0; i < 3; i++) {
5692 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5693 alu.op = ALU_OP1_EXP_IEEE;
5694 alu.src[0].sel = ctx->temp_reg;
5695 alu.src[0].chan = 1;
5696
5697 alu.dst.sel = ctx->temp_reg;
5698 alu.dst.chan = i;
5699 if (i == 1)
5700 alu.dst.write = 1;
5701 if (i == 2)
5702 alu.last = 1;
5703
5704 r = r600_bytecode_add_alu(ctx->bc, &alu);
5705 if (r)
5706 return r;
5707 }
5708 } else {
5709 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5710 alu.op = ALU_OP1_EXP_IEEE;
5711 alu.src[0].sel = ctx->temp_reg;
5712 alu.src[0].chan = 1;
5713
5714 alu.dst.sel = ctx->temp_reg;
5715 alu.dst.chan = 1;
5716 alu.dst.write = 1;
5717 alu.last = 1;
5718
5719 r = r600_bytecode_add_alu(ctx->bc, &alu);
5720 if (r)
5721 return r;
5722 }
5723
5724 if (ctx->bc->chip_class == CAYMAN) {
5725 for (i = 0; i < 3; i++) {
5726 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5727 alu.op = ALU_OP1_RECIP_IEEE;
5728 alu.src[0].sel = ctx->temp_reg;
5729 alu.src[0].chan = 1;
5730
5731 alu.dst.sel = ctx->temp_reg;
5732 alu.dst.chan = i;
5733 if (i == 1)
5734 alu.dst.write = 1;
5735 if (i == 2)
5736 alu.last = 1;
5737
5738 r = r600_bytecode_add_alu(ctx->bc, &alu);
5739 if (r)
5740 return r;
5741 }
5742 } else {
5743 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5744 alu.op = ALU_OP1_RECIP_IEEE;
5745 alu.src[0].sel = ctx->temp_reg;
5746 alu.src[0].chan = 1;
5747
5748 alu.dst.sel = ctx->temp_reg;
5749 alu.dst.chan = 1;
5750 alu.dst.write = 1;
5751 alu.last = 1;
5752
5753 r = r600_bytecode_add_alu(ctx->bc, &alu);
5754 if (r)
5755 return r;
5756 }
5757
5758 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5759
5760 alu.op = ALU_OP2_MUL;
5761
5762 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5763 r600_bytecode_src_set_abs(&alu.src[0]);
5764
5765 alu.src[1].sel = ctx->temp_reg;
5766 alu.src[1].chan = 1;
5767
5768 alu.dst.sel = ctx->temp_reg;
5769 alu.dst.chan = 1;
5770 alu.dst.write = 1;
5771 alu.last = 1;
5772
5773 r = r600_bytecode_add_alu(ctx->bc, &alu);
5774 if (r)
5775 return r;
5776 }
5777
5778 /* result.z = log2(|src|);*/
5779 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
5780 if (ctx->bc->chip_class == CAYMAN) {
5781 for (i = 0; i < 3; i++) {
5782 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5783
5784 alu.op = ALU_OP1_LOG_IEEE;
5785 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5786 r600_bytecode_src_set_abs(&alu.src[0]);
5787
5788 alu.dst.sel = ctx->temp_reg;
5789 if (i == 2)
5790 alu.dst.write = 1;
5791 alu.dst.chan = i;
5792 if (i == 2)
5793 alu.last = 1;
5794
5795 r = r600_bytecode_add_alu(ctx->bc, &alu);
5796 if (r)
5797 return r;
5798 }
5799 } else {
5800 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5801
5802 alu.op = ALU_OP1_LOG_IEEE;
5803 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5804 r600_bytecode_src_set_abs(&alu.src[0]);
5805
5806 alu.dst.sel = ctx->temp_reg;
5807 alu.dst.write = 1;
5808 alu.dst.chan = 2;
5809 alu.last = 1;
5810
5811 r = r600_bytecode_add_alu(ctx->bc, &alu);
5812 if (r)
5813 return r;
5814 }
5815 }
5816
5817 /* result.w = 1.0; */
5818 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
5819 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5820
5821 alu.op = ALU_OP1_MOV;
5822 alu.src[0].sel = V_SQ_ALU_SRC_1;
5823 alu.src[0].chan = 0;
5824
5825 alu.dst.sel = ctx->temp_reg;
5826 alu.dst.chan = 3;
5827 alu.dst.write = 1;
5828 alu.last = 1;
5829
5830 r = r600_bytecode_add_alu(ctx->bc, &alu);
5831 if (r)
5832 return r;
5833 }
5834
5835 return tgsi_helper_copy(ctx, inst);
5836 }
5837
5838 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
5839 {
5840 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5841 struct r600_bytecode_alu alu;
5842 int r;
5843 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5844
5845 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5846
5847 switch (inst->Instruction.Opcode) {
5848 case TGSI_OPCODE_ARL:
5849 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
5850 break;
5851 case TGSI_OPCODE_ARR:
5852 alu.op = ALU_OP1_FLT_TO_INT;
5853 break;
5854 case TGSI_OPCODE_UARL:
5855 alu.op = ALU_OP1_MOV;
5856 break;
5857 default:
5858 assert(0);
5859 return -1;
5860 }
5861
5862 for (i = 0; i <= lasti; ++i) {
5863 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5864 continue;
5865 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5866 alu.last = i == lasti;
5867 alu.dst.sel = ctx->bc->ar_reg;
5868 alu.dst.chan = i;
5869 alu.dst.write = 1;
5870 r = r600_bytecode_add_alu(ctx->bc, &alu);
5871 if (r)
5872 return r;
5873 }
5874
5875 ctx->bc->ar_loaded = 0;
5876 return 0;
5877 }
5878 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
5879 {
5880 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5881 struct r600_bytecode_alu alu;
5882 int r;
5883 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5884
5885 switch (inst->Instruction.Opcode) {
5886 case TGSI_OPCODE_ARL:
5887 memset(&alu, 0, sizeof(alu));
5888 alu.op = ALU_OP1_FLOOR;
5889 alu.dst.sel = ctx->bc->ar_reg;
5890 alu.dst.write = 1;
5891 for (i = 0; i <= lasti; ++i) {
5892 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
5893 alu.dst.chan = i;
5894 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5895 alu.last = i == lasti;
5896 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5897 return r;
5898 }
5899 }
5900
5901 memset(&alu, 0, sizeof(alu));
5902 alu.op = ALU_OP1_FLT_TO_INT;
5903 alu.src[0].sel = ctx->bc->ar_reg;
5904 alu.dst.sel = ctx->bc->ar_reg;
5905 alu.dst.write = 1;
5906 /* FLT_TO_INT is trans-only on r600/r700 */
5907 alu.last = TRUE;
5908 for (i = 0; i <= lasti; ++i) {
5909 alu.dst.chan = i;
5910 alu.src[0].chan = i;
5911 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5912 return r;
5913 }
5914 break;
5915 case TGSI_OPCODE_ARR:
5916 memset(&alu, 0, sizeof(alu));
5917 alu.op = ALU_OP1_FLT_TO_INT;
5918 alu.dst.sel = ctx->bc->ar_reg;
5919 alu.dst.write = 1;
5920 /* FLT_TO_INT is trans-only on r600/r700 */
5921 alu.last = TRUE;
5922 for (i = 0; i <= lasti; ++i) {
5923 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
5924 alu.dst.chan = i;
5925 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5926 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5927 return r;
5928 }
5929 }
5930 break;
5931 case TGSI_OPCODE_UARL:
5932 memset(&alu, 0, sizeof(alu));
5933 alu.op = ALU_OP1_MOV;
5934 alu.dst.sel = ctx->bc->ar_reg;
5935 alu.dst.write = 1;
5936 for (i = 0; i <= lasti; ++i) {
5937 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
5938 alu.dst.chan = i;
5939 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5940 alu.last = i == lasti;
5941 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5942 return r;
5943 }
5944 }
5945 break;
5946 default:
5947 assert(0);
5948 return -1;
5949 }
5950
5951 ctx->bc->ar_loaded = 0;
5952 return 0;
5953 }
5954
5955 static int tgsi_opdst(struct r600_shader_ctx *ctx)
5956 {
5957 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5958 struct r600_bytecode_alu alu;
5959 int i, r = 0;
5960
5961 for (i = 0; i < 4; i++) {
5962 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5963
5964 alu.op = ALU_OP2_MUL;
5965 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5966
5967 if (i == 0 || i == 3) {
5968 alu.src[0].sel = V_SQ_ALU_SRC_1;
5969 } else {
5970 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5971 }
5972
5973 if (i == 0 || i == 2) {
5974 alu.src[1].sel = V_SQ_ALU_SRC_1;
5975 } else {
5976 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5977 }
5978 if (i == 3)
5979 alu.last = 1;
5980 r = r600_bytecode_add_alu(ctx->bc, &alu);
5981 if (r)
5982 return r;
5983 }
5984 return 0;
5985 }
5986
5987 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
5988 {
5989 struct r600_bytecode_alu alu;
5990 int r;
5991
5992 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5993 alu.op = opcode;
5994 alu.execute_mask = 1;
5995 alu.update_pred = 1;
5996
5997 alu.dst.sel = ctx->temp_reg;
5998 alu.dst.write = 1;
5999 alu.dst.chan = 0;
6000
6001 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
6002 alu.src[1].sel = V_SQ_ALU_SRC_0;
6003 alu.src[1].chan = 0;
6004
6005 alu.last = 1;
6006
6007 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
6008 if (r)
6009 return r;
6010 return 0;
6011 }
6012
6013 static int pops(struct r600_shader_ctx *ctx, int pops)
6014 {
6015 unsigned force_pop = ctx->bc->force_add_cf;
6016
6017 if (!force_pop) {
6018 int alu_pop = 3;
6019 if (ctx->bc->cf_last) {
6020 if (ctx->bc->cf_last->op == CF_OP_ALU)
6021 alu_pop = 0;
6022 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
6023 alu_pop = 1;
6024 }
6025 alu_pop += pops;
6026 if (alu_pop == 1) {
6027 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
6028 ctx->bc->force_add_cf = 1;
6029 } else if (alu_pop == 2) {
6030 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
6031 ctx->bc->force_add_cf = 1;
6032 } else {
6033 force_pop = 1;
6034 }
6035 }
6036
6037 if (force_pop) {
6038 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
6039 ctx->bc->cf_last->pop_count = pops;
6040 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
6041 }
6042
6043 return 0;
6044 }
6045
6046 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
6047 unsigned reason)
6048 {
6049 struct r600_stack_info *stack = &ctx->bc->stack;
6050 unsigned elements, entries;
6051
6052 unsigned entry_size = stack->entry_size;
6053
6054 elements = (stack->loop + stack->push_wqm ) * entry_size;
6055 elements += stack->push;
6056
6057 switch (ctx->bc->chip_class) {
6058 case R600:
6059 case R700:
6060 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
6061 * the stack must be reserved to hold the current active/continue
6062 * masks */
6063 if (reason == FC_PUSH_VPM) {
6064 elements += 2;
6065 }
6066 break;
6067
6068 case CAYMAN:
6069 /* r9xx: any stack operation on empty stack consumes 2 additional
6070 * elements */
6071 elements += 2;
6072
6073 /* fallthrough */
6074 /* FIXME: do the two elements added above cover the cases for the
6075 * r8xx+ below? */
6076
6077 case EVERGREEN:
6078 /* r8xx+: 2 extra elements are not always required, but one extra
6079 * element must be added for each of the following cases:
6080 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
6081 * stack usage.
6082 * (Currently we don't use ALU_ELSE_AFTER.)
6083 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
6084 * PUSH instruction executed.
6085 *
6086 * NOTE: it seems we also need to reserve additional element in some
6087 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
6088 * then STACK_SIZE should be 2 instead of 1 */
6089 if (reason == FC_PUSH_VPM) {
6090 elements += 1;
6091 }
6092 break;
6093
6094 default:
6095 assert(0);
6096 break;
6097 }
6098
6099 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
6100 * for all chips, so we use 4 in the final formula, not the real entry_size
6101 * for the chip */
6102 entry_size = 4;
6103
6104 entries = (elements + (entry_size - 1)) / entry_size;
6105
6106 if (entries > stack->max_entries)
6107 stack->max_entries = entries;
6108 }
6109
6110 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
6111 {
6112 switch(reason) {
6113 case FC_PUSH_VPM:
6114 --ctx->bc->stack.push;
6115 assert(ctx->bc->stack.push >= 0);
6116 break;
6117 case FC_PUSH_WQM:
6118 --ctx->bc->stack.push_wqm;
6119 assert(ctx->bc->stack.push_wqm >= 0);
6120 break;
6121 case FC_LOOP:
6122 --ctx->bc->stack.loop;
6123 assert(ctx->bc->stack.loop >= 0);
6124 break;
6125 default:
6126 assert(0);
6127 break;
6128 }
6129 }
6130
6131 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
6132 {
6133 switch (reason) {
6134 case FC_PUSH_VPM:
6135 ++ctx->bc->stack.push;
6136 break;
6137 case FC_PUSH_WQM:
6138 ++ctx->bc->stack.push_wqm;
6139 case FC_LOOP:
6140 ++ctx->bc->stack.loop;
6141 break;
6142 default:
6143 assert(0);
6144 }
6145
6146 callstack_update_max_depth(ctx, reason);
6147 }
6148
6149 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
6150 {
6151 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
6152
6153 sp->mid = realloc((void *)sp->mid,
6154 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
6155 sp->mid[sp->num_mid] = ctx->bc->cf_last;
6156 sp->num_mid++;
6157 }
6158
6159 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
6160 {
6161 ctx->bc->fc_sp++;
6162 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
6163 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
6164 }
6165
6166 static void fc_poplevel(struct r600_shader_ctx *ctx)
6167 {
6168 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
6169 free(sp->mid);
6170 sp->mid = NULL;
6171 sp->num_mid = 0;
6172 sp->start = NULL;
6173 sp->type = 0;
6174 ctx->bc->fc_sp--;
6175 }
6176
6177 #if 0
6178 static int emit_return(struct r600_shader_ctx *ctx)
6179 {
6180 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
6181 return 0;
6182 }
6183
6184 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
6185 {
6186
6187 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
6188 ctx->bc->cf_last->pop_count = pops;
6189 /* XXX work out offset */
6190 return 0;
6191 }
6192
6193 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
6194 {
6195 return 0;
6196 }
6197
6198 static void emit_testflag(struct r600_shader_ctx *ctx)
6199 {
6200
6201 }
6202
6203 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
6204 {
6205 emit_testflag(ctx);
6206 emit_jump_to_offset(ctx, 1, 4);
6207 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
6208 pops(ctx, ifidx + 1);
6209 emit_return(ctx);
6210 }
6211
6212 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
6213 {
6214 emit_testflag(ctx);
6215
6216 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6217 ctx->bc->cf_last->pop_count = 1;
6218
6219 fc_set_mid(ctx, fc_sp);
6220
6221 pops(ctx, 1);
6222 }
6223 #endif
6224
6225 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
6226 {
6227 int alu_type = CF_OP_ALU_PUSH_BEFORE;
6228
6229 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
6230 * LOOP_STARTxxx for nested loops may put the branch stack into a state
6231 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
6232 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
6233 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
6234 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
6235 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
6236 alu_type = CF_OP_ALU;
6237 }
6238
6239 emit_logic_pred(ctx, opcode, alu_type);
6240
6241 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
6242
6243 fc_pushlevel(ctx, FC_IF);
6244
6245 callstack_push(ctx, FC_PUSH_VPM);
6246 return 0;
6247 }
6248
6249 static int tgsi_if(struct r600_shader_ctx *ctx)
6250 {
6251 return emit_if(ctx, ALU_OP2_PRED_SETNE);
6252 }
6253
6254 static int tgsi_uif(struct r600_shader_ctx *ctx)
6255 {
6256 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
6257 }
6258
6259 static int tgsi_else(struct r600_shader_ctx *ctx)
6260 {
6261 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
6262 ctx->bc->cf_last->pop_count = 1;
6263
6264 fc_set_mid(ctx, ctx->bc->fc_sp);
6265 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
6266 return 0;
6267 }
6268
6269 static int tgsi_endif(struct r600_shader_ctx *ctx)
6270 {
6271 pops(ctx, 1);
6272 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
6273 R600_ERR("if/endif unbalanced in shader\n");
6274 return -1;
6275 }
6276
6277 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
6278 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
6279 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
6280 } else {
6281 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
6282 }
6283 fc_poplevel(ctx);
6284
6285 callstack_pop(ctx, FC_PUSH_VPM);
6286 return 0;
6287 }
6288
6289 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
6290 {
6291 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
6292 * limited to 4096 iterations, like the other LOOP_* instructions. */
6293 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
6294
6295 fc_pushlevel(ctx, FC_LOOP);
6296
6297 /* check stack depth */
6298 callstack_push(ctx, FC_LOOP);
6299 return 0;
6300 }
6301
6302 static int tgsi_endloop(struct r600_shader_ctx *ctx)
6303 {
6304 int i;
6305
6306 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
6307
6308 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
6309 R600_ERR("loop/endloop in shader code are not paired.\n");
6310 return -EINVAL;
6311 }
6312
6313 /* fixup loop pointers - from r600isa
6314 LOOP END points to CF after LOOP START,
6315 LOOP START point to CF after LOOP END
6316 BRK/CONT point to LOOP END CF
6317 */
6318 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
6319
6320 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
6321
6322 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
6323 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
6324 }
6325 /* XXX add LOOPRET support */
6326 fc_poplevel(ctx);
6327 callstack_pop(ctx, FC_LOOP);
6328 return 0;
6329 }
6330
6331 static int tgsi_loop_breakc(struct r600_shader_ctx *ctx)
6332 {
6333 int r;
6334 unsigned int fscp;
6335
6336 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
6337 {
6338 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
6339 break;
6340 }
6341 if (fscp == 0) {
6342 R600_ERR("BREAKC not inside loop/endloop pair\n");
6343 return -EINVAL;
6344 }
6345
6346 if (ctx->bc->chip_class == EVERGREEN &&
6347 ctx->bc->family != CHIP_CYPRESS &&
6348 ctx->bc->family != CHIP_JUNIPER) {
6349 /* HW bug: ALU_BREAK does not save the active mask correctly */
6350 r = tgsi_uif(ctx);
6351 if (r)
6352 return r;
6353
6354 r = r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_BREAK);
6355 if (r)
6356 return r;
6357 fc_set_mid(ctx, fscp);
6358
6359 return tgsi_endif(ctx);
6360 } else {
6361 r = emit_logic_pred(ctx, ALU_OP2_PRED_SETE_INT, CF_OP_ALU_BREAK);
6362 if (r)
6363 return r;
6364 fc_set_mid(ctx, fscp);
6365 }
6366
6367 return 0;
6368 }
6369
6370 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
6371 {
6372 unsigned int fscp;
6373
6374 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
6375 {
6376 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
6377 break;
6378 }
6379
6380 if (fscp == 0) {
6381 R600_ERR("Break not inside loop/endloop pair\n");
6382 return -EINVAL;
6383 }
6384
6385 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6386
6387 fc_set_mid(ctx, fscp);
6388
6389 return 0;
6390 }
6391
6392 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
6393 {
6394 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
6395 emit_gs_ring_writes(ctx, TRUE);
6396
6397 return r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
6398 }
6399
6400 static int tgsi_umad(struct r600_shader_ctx *ctx)
6401 {
6402 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6403 struct r600_bytecode_alu alu;
6404 int i, j, k, r;
6405 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6406
6407 /* src0 * src1 */
6408 for (i = 0; i < lasti + 1; i++) {
6409 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6410 continue;
6411
6412 if (ctx->bc->chip_class == CAYMAN) {
6413 for (j = 0 ; j < 4; j++) {
6414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6415
6416 alu.op = ALU_OP2_MULLO_UINT;
6417 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
6418 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
6419 }
6420 tgsi_dst(ctx, &inst->Dst[0], j, &alu.dst);
6421 alu.dst.sel = ctx->temp_reg;
6422 alu.dst.write = (j == i);
6423 if (j == 3)
6424 alu.last = 1;
6425 r = r600_bytecode_add_alu(ctx->bc, &alu);
6426 if (r)
6427 return r;
6428 }
6429 } else {
6430 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6431
6432 alu.dst.chan = i;
6433 alu.dst.sel = ctx->temp_reg;
6434 alu.dst.write = 1;
6435
6436 alu.op = ALU_OP2_MULLO_UINT;
6437 for (j = 0; j < 2; j++) {
6438 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6439 }
6440
6441 alu.last = 1;
6442 r = r600_bytecode_add_alu(ctx->bc, &alu);
6443 if (r)
6444 return r;
6445 }
6446 }
6447
6448
6449 for (i = 0; i < lasti + 1; i++) {
6450 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6451 continue;
6452
6453 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6454 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6455
6456 alu.op = ALU_OP2_ADD_INT;
6457
6458 alu.src[0].sel = ctx->temp_reg;
6459 alu.src[0].chan = i;
6460
6461 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6462 if (i == lasti) {
6463 alu.last = 1;
6464 }
6465 r = r600_bytecode_add_alu(ctx->bc, &alu);
6466 if (r)
6467 return r;
6468 }
6469 return 0;
6470 }
6471
6472 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
6473 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_r600_arl},
6474 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6475 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6476
6477 /* XXX:
6478 * For state trackers other than OpenGL, we'll want to use
6479 * _RECIP_IEEE instead.
6480 */
6481 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
6482
6483 {TGSI_OPCODE_RSQ, 0, ALU_OP0_NOP, tgsi_rsq},
6484 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6485 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6486 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6487 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6488 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6489 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6490 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6491 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6492 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6493 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6494 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6495 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6496 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6497 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6498 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6499 {TGSI_OPCODE_SQRT, 0, ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
6500 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6501 /* gap */
6502 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6503 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6504 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6505 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6506 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6507 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6508 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6509 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6510 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6511 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6512 /* gap */
6513 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6514 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6515 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6516 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6517 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6518 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6519 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6520 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6521 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6522 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6523 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6524 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6525 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6526 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6527 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6528 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6529 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6530 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6531 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6532 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6533 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6534 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6535 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6536 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6537 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6538 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6539 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6540 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6541 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6542 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_r600_arl},
6543 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6544 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6545 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6546 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6547 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6548 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6549 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6550 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6551 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6552 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6553 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6554 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6555 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6556 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6557 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6558 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6559 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6560 /* gap */
6561 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6562 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6563 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6564 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6565 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6566 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6567 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6568 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6569 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2_trans},
6570 /* gap */
6571 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6572 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6573 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6574 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6575 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6576 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6577 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6578 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6579 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6580 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6581 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6582 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6583 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6584 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6585 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6586 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6587 /* gap */
6588 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6589 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6590 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6591 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6592 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6593 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6594 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6595 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6596 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6597 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6598 /* gap */
6599 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6600 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_loop_breakc},
6601 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6602 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6603 /* gap */
6604 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6605 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
6606 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6607 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6608 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6609 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6610 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6611 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2_trans},
6612 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6613 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
6614 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6615 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6616 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6617 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6618 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6619 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6620 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6621 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6622 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6623 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6624 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2_trans},
6625 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6626 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2_swap},
6627 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6628 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6629 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6630 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6631 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6632 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6633 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6634 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6635 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6636 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6637 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6638 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6639 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6640 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6641 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6642 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6643 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_r600_arl},
6644 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6645 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6646 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6647 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6648 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6649 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6650 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6651 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6652 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6653 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6654 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6655 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6656 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6657 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6658 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6659 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6660 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6661 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6662 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6663 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6664 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6665 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6666 {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
6667 {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
6668 {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_unsupported},
6669 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6670 };
6671
6672 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
6673 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6674 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6675 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6676 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
6677 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, tgsi_rsq},
6678 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6679 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6680 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6681 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6682 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6683 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6684 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6685 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6686 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6687 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6688 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6689 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6690 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6691 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6692 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6693 {TGSI_OPCODE_SQRT, 0, ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
6694 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6695 /* gap */
6696 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6697 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6698 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6699 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6700 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6701 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6702 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
6703 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
6704 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, tgsi_pow},
6705 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6706 /* gap */
6707 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6708 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6709 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6710 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6711 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, tgsi_trig},
6712 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6713 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6714 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6715 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6716 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6717 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6718 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6719 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6720 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6721 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6722 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6723 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, tgsi_trig},
6724 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6725 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6726 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6727 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6728 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6729 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6730 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6731 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6732 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6733 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6734 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6735 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6736 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6737 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6738 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6739 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6740 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6741 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6742 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6743 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6744 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6745 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6746 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6747 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6748 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6749 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6750 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6751 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6752 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6753 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6754 /* gap */
6755 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6756 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6757 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6758 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6759 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6760 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
6761 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6762 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6763 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6764 /* gap */
6765 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6766 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6767 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6768 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6769 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6770 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6771 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6772 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6773 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6774 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6775 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6776 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6777 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6778 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6779 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6780 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6781 /* gap */
6782 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6783 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6784 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6785 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6786 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6787 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6788 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6789 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6790 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6791 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6792 /* gap */
6793 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6794 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6795 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6796 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6797 /* gap */
6798 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6799 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_f2i},
6800 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6801 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6802 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6803 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6804 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
6805 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
6806 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
6807 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_f2i},
6808 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
6809 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
6810 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
6811 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
6812 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
6813 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
6814 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
6815 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_UINT, tgsi_op2_trans},
6816 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
6817 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
6818 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
6819 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
6820 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
6821 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6822 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
6823 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
6824 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
6825 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
6826 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
6827 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
6828 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
6829 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
6830 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
6831 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
6832 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
6833 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
6834 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
6835 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
6836 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
6837 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
6838 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
6839 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
6840 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
6841 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6842 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
6843 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6844 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6845 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
6846 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
6847 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
6848 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
6849 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
6850 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
6851 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6852 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
6853 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6854 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6855 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
6856 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
6857 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
6858 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6859 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6860 {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
6861 {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
6862 {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_tex},
6863 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
6864 };
6865
6866 static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
6867 {TGSI_OPCODE_ARL, 0, ALU_OP0_NOP, tgsi_eg_arl},
6868 {TGSI_OPCODE_MOV, 0, ALU_OP1_MOV, tgsi_op2},
6869 {TGSI_OPCODE_LIT, 0, ALU_OP0_NOP, tgsi_lit},
6870 {TGSI_OPCODE_RCP, 0, ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
6871 {TGSI_OPCODE_RSQ, 0, ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
6872 {TGSI_OPCODE_EXP, 0, ALU_OP0_NOP, tgsi_exp},
6873 {TGSI_OPCODE_LOG, 0, ALU_OP0_NOP, tgsi_log},
6874 {TGSI_OPCODE_MUL, 0, ALU_OP2_MUL, tgsi_op2},
6875 {TGSI_OPCODE_ADD, 0, ALU_OP2_ADD, tgsi_op2},
6876 {TGSI_OPCODE_DP3, 0, ALU_OP2_DOT4, tgsi_dp},
6877 {TGSI_OPCODE_DP4, 0, ALU_OP2_DOT4, tgsi_dp},
6878 {TGSI_OPCODE_DST, 0, ALU_OP0_NOP, tgsi_opdst},
6879 {TGSI_OPCODE_MIN, 0, ALU_OP2_MIN, tgsi_op2},
6880 {TGSI_OPCODE_MAX, 0, ALU_OP2_MAX, tgsi_op2},
6881 {TGSI_OPCODE_SLT, 0, ALU_OP2_SETGT, tgsi_op2_swap},
6882 {TGSI_OPCODE_SGE, 0, ALU_OP2_SETGE, tgsi_op2},
6883 {TGSI_OPCODE_MAD, 1, ALU_OP3_MULADD, tgsi_op3},
6884 {TGSI_OPCODE_SUB, 0, ALU_OP2_ADD, tgsi_op2},
6885 {TGSI_OPCODE_LRP, 0, ALU_OP0_NOP, tgsi_lrp},
6886 {TGSI_OPCODE_CND, 0, ALU_OP0_NOP, tgsi_unsupported},
6887 {TGSI_OPCODE_SQRT, 0, ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
6888 {TGSI_OPCODE_DP2A, 0, ALU_OP0_NOP, tgsi_unsupported},
6889 /* gap */
6890 {22, 0, ALU_OP0_NOP, tgsi_unsupported},
6891 {23, 0, ALU_OP0_NOP, tgsi_unsupported},
6892 {TGSI_OPCODE_FRC, 0, ALU_OP1_FRACT, tgsi_op2},
6893 {TGSI_OPCODE_CLAMP, 0, ALU_OP0_NOP, tgsi_unsupported},
6894 {TGSI_OPCODE_FLR, 0, ALU_OP1_FLOOR, tgsi_op2},
6895 {TGSI_OPCODE_ROUND, 0, ALU_OP1_RNDNE, tgsi_op2},
6896 {TGSI_OPCODE_EX2, 0, ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
6897 {TGSI_OPCODE_LG2, 0, ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
6898 {TGSI_OPCODE_POW, 0, ALU_OP0_NOP, cayman_pow},
6899 {TGSI_OPCODE_XPD, 0, ALU_OP0_NOP, tgsi_xpd},
6900 /* gap */
6901 {32, 0, ALU_OP0_NOP, tgsi_unsupported},
6902 {TGSI_OPCODE_ABS, 0, ALU_OP1_MOV, tgsi_op2},
6903 {TGSI_OPCODE_RCC, 0, ALU_OP0_NOP, tgsi_unsupported},
6904 {TGSI_OPCODE_DPH, 0, ALU_OP2_DOT4, tgsi_dp},
6905 {TGSI_OPCODE_COS, 0, ALU_OP1_COS, cayman_trig},
6906 {TGSI_OPCODE_DDX, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
6907 {TGSI_OPCODE_DDY, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
6908 {TGSI_OPCODE_KILL, 0, ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
6909 {TGSI_OPCODE_PK2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6910 {TGSI_OPCODE_PK2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6911 {TGSI_OPCODE_PK4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6912 {TGSI_OPCODE_PK4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6913 {TGSI_OPCODE_RFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6914 {TGSI_OPCODE_SEQ, 0, ALU_OP2_SETE, tgsi_op2},
6915 {TGSI_OPCODE_SFL, 0, ALU_OP0_NOP, tgsi_unsupported},
6916 {TGSI_OPCODE_SGT, 0, ALU_OP2_SETGT, tgsi_op2},
6917 {TGSI_OPCODE_SIN, 0, ALU_OP1_SIN, cayman_trig},
6918 {TGSI_OPCODE_SLE, 0, ALU_OP2_SETGE, tgsi_op2_swap},
6919 {TGSI_OPCODE_SNE, 0, ALU_OP2_SETNE, tgsi_op2},
6920 {TGSI_OPCODE_STR, 0, ALU_OP0_NOP, tgsi_unsupported},
6921 {TGSI_OPCODE_TEX, 0, FETCH_OP_SAMPLE, tgsi_tex},
6922 {TGSI_OPCODE_TXD, 0, FETCH_OP_SAMPLE_G, tgsi_tex},
6923 {TGSI_OPCODE_TXP, 0, FETCH_OP_SAMPLE, tgsi_tex},
6924 {TGSI_OPCODE_UP2H, 0, ALU_OP0_NOP, tgsi_unsupported},
6925 {TGSI_OPCODE_UP2US, 0, ALU_OP0_NOP, tgsi_unsupported},
6926 {TGSI_OPCODE_UP4B, 0, ALU_OP0_NOP, tgsi_unsupported},
6927 {TGSI_OPCODE_UP4UB, 0, ALU_OP0_NOP, tgsi_unsupported},
6928 {TGSI_OPCODE_X2D, 0, ALU_OP0_NOP, tgsi_unsupported},
6929 {TGSI_OPCODE_ARA, 0, ALU_OP0_NOP, tgsi_unsupported},
6930 {TGSI_OPCODE_ARR, 0, ALU_OP0_NOP, tgsi_eg_arl},
6931 {TGSI_OPCODE_BRA, 0, ALU_OP0_NOP, tgsi_unsupported},
6932 {TGSI_OPCODE_CAL, 0, ALU_OP0_NOP, tgsi_unsupported},
6933 {TGSI_OPCODE_RET, 0, ALU_OP0_NOP, tgsi_unsupported},
6934 {TGSI_OPCODE_SSG, 0, ALU_OP0_NOP, tgsi_ssg},
6935 {TGSI_OPCODE_CMP, 0, ALU_OP0_NOP, tgsi_cmp},
6936 {TGSI_OPCODE_SCS, 0, ALU_OP0_NOP, tgsi_scs},
6937 {TGSI_OPCODE_TXB, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
6938 {TGSI_OPCODE_NRM, 0, ALU_OP0_NOP, tgsi_unsupported},
6939 {TGSI_OPCODE_DIV, 0, ALU_OP0_NOP, tgsi_unsupported},
6940 {TGSI_OPCODE_DP2, 0, ALU_OP2_DOT4, tgsi_dp},
6941 {TGSI_OPCODE_TXL, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
6942 {TGSI_OPCODE_BRK, 0, CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
6943 {TGSI_OPCODE_IF, 0, ALU_OP0_NOP, tgsi_if},
6944 {TGSI_OPCODE_UIF, 0, ALU_OP0_NOP, tgsi_uif},
6945 {76, 0, ALU_OP0_NOP, tgsi_unsupported},
6946 {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else},
6947 {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif},
6948 /* gap */
6949 {79, 0, ALU_OP0_NOP, tgsi_unsupported},
6950 {80, 0, ALU_OP0_NOP, tgsi_unsupported},
6951 {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported},
6952 {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported},
6953 {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},
6954 {TGSI_OPCODE_I2F, 0, ALU_OP1_INT_TO_FLT, tgsi_op2},
6955 {TGSI_OPCODE_NOT, 0, ALU_OP1_NOT_INT, tgsi_op2},
6956 {TGSI_OPCODE_TRUNC, 0, ALU_OP1_TRUNC, tgsi_op2},
6957 {TGSI_OPCODE_SHL, 0, ALU_OP2_LSHL_INT, tgsi_op2},
6958 /* gap */
6959 {88, 0, ALU_OP0_NOP, tgsi_unsupported},
6960 {TGSI_OPCODE_AND, 0, ALU_OP2_AND_INT, tgsi_op2},
6961 {TGSI_OPCODE_OR, 0, ALU_OP2_OR_INT, tgsi_op2},
6962 {TGSI_OPCODE_MOD, 0, ALU_OP0_NOP, tgsi_imod},
6963 {TGSI_OPCODE_XOR, 0, ALU_OP2_XOR_INT, tgsi_op2},
6964 {TGSI_OPCODE_SAD, 0, ALU_OP0_NOP, tgsi_unsupported},
6965 {TGSI_OPCODE_TXF, 0, FETCH_OP_LD, tgsi_tex},
6966 {TGSI_OPCODE_TXQ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6967 {TGSI_OPCODE_CONT, 0, CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
6968 {TGSI_OPCODE_EMIT, 0, CF_OP_EMIT_VERTEX, tgsi_gs_emit},
6969 {TGSI_OPCODE_ENDPRIM, 0, CF_OP_CUT_VERTEX, tgsi_gs_emit},
6970 {TGSI_OPCODE_BGNLOOP, 0, ALU_OP0_NOP, tgsi_bgnloop},
6971 {TGSI_OPCODE_BGNSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6972 {TGSI_OPCODE_ENDLOOP, 0, ALU_OP0_NOP, tgsi_endloop},
6973 {TGSI_OPCODE_ENDSUB, 0, ALU_OP0_NOP, tgsi_unsupported},
6974 {TGSI_OPCODE_TXQ_LZ, 0, FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
6975 /* gap */
6976 {104, 0, ALU_OP0_NOP, tgsi_unsupported},
6977 {105, 0, ALU_OP0_NOP, tgsi_unsupported},
6978 {106, 0, ALU_OP0_NOP, tgsi_unsupported},
6979 {TGSI_OPCODE_NOP, 0, ALU_OP0_NOP, tgsi_unsupported},
6980 /* gap */
6981 {TGSI_OPCODE_FSEQ, 0, ALU_OP2_SETE_DX10, tgsi_op2},
6982 {TGSI_OPCODE_FSGE, 0, ALU_OP2_SETGE_DX10, tgsi_op2},
6983 {TGSI_OPCODE_FSLT, 0, ALU_OP2_SETGT_DX10, tgsi_op2_swap},
6984 {TGSI_OPCODE_FSNE, 0, ALU_OP2_SETNE_DX10, tgsi_op2_swap},
6985 {TGSI_OPCODE_NRM4, 0, ALU_OP0_NOP, tgsi_unsupported},
6986 {TGSI_OPCODE_CALLNZ, 0, ALU_OP0_NOP, tgsi_unsupported},
6987 /* gap */
6988 {114, 0, ALU_OP0_NOP, tgsi_unsupported},
6989 {TGSI_OPCODE_BREAKC, 0, ALU_OP0_NOP, tgsi_unsupported},
6990 {TGSI_OPCODE_KILL_IF, 0, ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
6991 {TGSI_OPCODE_END, 0, ALU_OP0_NOP, tgsi_end}, /* aka HALT */
6992 /* gap */
6993 {118, 0, ALU_OP0_NOP, tgsi_unsupported},
6994 {TGSI_OPCODE_F2I, 0, ALU_OP1_FLT_TO_INT, tgsi_op2},
6995 {TGSI_OPCODE_IDIV, 0, ALU_OP0_NOP, tgsi_idiv},
6996 {TGSI_OPCODE_IMAX, 0, ALU_OP2_MAX_INT, tgsi_op2},
6997 {TGSI_OPCODE_IMIN, 0, ALU_OP2_MIN_INT, tgsi_op2},
6998 {TGSI_OPCODE_INEG, 0, ALU_OP2_SUB_INT, tgsi_ineg},
6999 {TGSI_OPCODE_ISGE, 0, ALU_OP2_SETGE_INT, tgsi_op2},
7000 {TGSI_OPCODE_ISHR, 0, ALU_OP2_ASHR_INT, tgsi_op2},
7001 {TGSI_OPCODE_ISLT, 0, ALU_OP2_SETGT_INT, tgsi_op2_swap},
7002 {TGSI_OPCODE_F2U, 0, ALU_OP1_FLT_TO_UINT, tgsi_op2},
7003 {TGSI_OPCODE_U2F, 0, ALU_OP1_UINT_TO_FLT, tgsi_op2},
7004 {TGSI_OPCODE_UADD, 0, ALU_OP2_ADD_INT, tgsi_op2},
7005 {TGSI_OPCODE_UDIV, 0, ALU_OP0_NOP, tgsi_udiv},
7006 {TGSI_OPCODE_UMAD, 0, ALU_OP0_NOP, tgsi_umad},
7007 {TGSI_OPCODE_UMAX, 0, ALU_OP2_MAX_UINT, tgsi_op2},
7008 {TGSI_OPCODE_UMIN, 0, ALU_OP2_MIN_UINT, tgsi_op2},
7009 {TGSI_OPCODE_UMOD, 0, ALU_OP0_NOP, tgsi_umod},
7010 {TGSI_OPCODE_UMUL, 0, ALU_OP2_MULLO_INT, cayman_mul_int_instr},
7011 {TGSI_OPCODE_USEQ, 0, ALU_OP2_SETE_INT, tgsi_op2},
7012 {TGSI_OPCODE_USGE, 0, ALU_OP2_SETGE_UINT, tgsi_op2},
7013 {TGSI_OPCODE_USHR, 0, ALU_OP2_LSHR_INT, tgsi_op2},
7014 {TGSI_OPCODE_USLT, 0, ALU_OP2_SETGT_UINT, tgsi_op2_swap},
7015 {TGSI_OPCODE_USNE, 0, ALU_OP2_SETNE_INT, tgsi_op2},
7016 {TGSI_OPCODE_SWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
7017 {TGSI_OPCODE_CASE, 0, ALU_OP0_NOP, tgsi_unsupported},
7018 {TGSI_OPCODE_DEFAULT, 0, ALU_OP0_NOP, tgsi_unsupported},
7019 {TGSI_OPCODE_ENDSWITCH, 0, ALU_OP0_NOP, tgsi_unsupported},
7020 {TGSI_OPCODE_SAMPLE, 0, 0, tgsi_unsupported},
7021 {TGSI_OPCODE_SAMPLE_I, 0, 0, tgsi_unsupported},
7022 {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
7023 {TGSI_OPCODE_SAMPLE_B, 0, 0, tgsi_unsupported},
7024 {TGSI_OPCODE_SAMPLE_C, 0, 0, tgsi_unsupported},
7025 {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
7026 {TGSI_OPCODE_SAMPLE_D, 0, 0, tgsi_unsupported},
7027 {TGSI_OPCODE_SAMPLE_L, 0, 0, tgsi_unsupported},
7028 {TGSI_OPCODE_GATHER4, 0, 0, tgsi_unsupported},
7029 {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
7030 {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
7031 {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
7032 {TGSI_OPCODE_UARL, 0, ALU_OP1_MOVA_INT, tgsi_eg_arl},
7033 {TGSI_OPCODE_UCMP, 0, ALU_OP0_NOP, tgsi_ucmp},
7034 {TGSI_OPCODE_IABS, 0, 0, tgsi_iabs},
7035 {TGSI_OPCODE_ISSG, 0, 0, tgsi_issg},
7036 {TGSI_OPCODE_LOAD, 0, ALU_OP0_NOP, tgsi_unsupported},
7037 {TGSI_OPCODE_STORE, 0, ALU_OP0_NOP, tgsi_unsupported},
7038 {TGSI_OPCODE_MFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7039 {TGSI_OPCODE_LFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7040 {TGSI_OPCODE_SFENCE, 0, ALU_OP0_NOP, tgsi_unsupported},
7041 {TGSI_OPCODE_BARRIER, 0, ALU_OP0_NOP, tgsi_unsupported},
7042 {TGSI_OPCODE_ATOMUADD, 0, ALU_OP0_NOP, tgsi_unsupported},
7043 {TGSI_OPCODE_ATOMXCHG, 0, ALU_OP0_NOP, tgsi_unsupported},
7044 {TGSI_OPCODE_ATOMCAS, 0, ALU_OP0_NOP, tgsi_unsupported},
7045 {TGSI_OPCODE_ATOMAND, 0, ALU_OP0_NOP, tgsi_unsupported},
7046 {TGSI_OPCODE_ATOMOR, 0, ALU_OP0_NOP, tgsi_unsupported},
7047 {TGSI_OPCODE_ATOMXOR, 0, ALU_OP0_NOP, tgsi_unsupported},
7048 {TGSI_OPCODE_ATOMUMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
7049 {TGSI_OPCODE_ATOMUMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
7050 {TGSI_OPCODE_ATOMIMIN, 0, ALU_OP0_NOP, tgsi_unsupported},
7051 {TGSI_OPCODE_ATOMIMAX, 0, ALU_OP0_NOP, tgsi_unsupported},
7052 {TGSI_OPCODE_TEX2, 0, FETCH_OP_SAMPLE, tgsi_tex},
7053 {TGSI_OPCODE_TXB2, 0, FETCH_OP_SAMPLE_LB, tgsi_tex},
7054 {TGSI_OPCODE_TXL2, 0, FETCH_OP_SAMPLE_L, tgsi_tex},
7055 {TGSI_OPCODE_IMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
7056 {TGSI_OPCODE_UMUL_HI, 0, ALU_OP0_NOP, tgsi_unsupported},
7057 {TGSI_OPCODE_TG4, 0, FETCH_OP_GATHER4, tgsi_tex},
7058 {TGSI_OPCODE_LAST, 0, ALU_OP0_NOP, tgsi_unsupported},
7059 };