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r600g: fix constant & literal src splitting, also fix mplayer gl2 shader
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 for (i = 0; i < 10; i++) {
48 spi_vs_out_id[i] = 0;
49 }
50 for (i = 0; i < 32; i++) {
51 tmp = i << ((i & 3) * 8);
52 spi_vs_out_id[i / 4] |= tmp;
53 }
54 for (i = 0; i < 10; i++) {
55 r600_pipe_state_add_reg(rstate,
56 R_028614_SPI_VS_OUT_ID_0 + i * 4,
57 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
58 }
59
60 r600_pipe_state_add_reg(rstate,
61 R_0286C4_SPI_VS_OUT_CONFIG,
62 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
63 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate,
65 R_028868_SQ_PGM_RESOURCES_VS,
66 S_028868_NUM_GPRS(rshader->bc.ngpr) |
67 S_028868_STACK_SIZE(rshader->bc.nstack),
68 0xFFFFFFFF, NULL);
69 r600_pipe_state_add_reg(rstate,
70 R_0288A4_SQ_PGM_RESOURCES_FS,
71 0x00000000, 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_0288DC_SQ_PGM_CF_OFFSET_FS,
77 0x00000000, 0xFFFFFFFF, NULL);
78 r600_pipe_state_add_reg(rstate,
79 R_028858_SQ_PGM_START_VS,
80 0x00000000, 0xFFFFFFFF, shader->bo);
81 r600_pipe_state_add_reg(rstate,
82 R_028894_SQ_PGM_START_FS,
83 0x00000000, 0xFFFFFFFF, shader->bo);
84 }
85
86 int r600_find_vs_semantic_index(struct r600_shader *vs,
87 struct r600_shader *ps, int id)
88 {
89 struct r600_shader_io *input = &ps->input[id];
90
91 for (int i = 0; i < vs->noutput; i++) {
92 if (input->name == vs->output[i].name &&
93 input->sid == vs->output[i].sid) {
94 return i - 1;
95 }
96 }
97 return 0;
98 }
99
100 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
101 {
102 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
103 struct r600_pipe_state *rstate = &shader->rstate;
104 struct r600_shader *rshader = &shader->shader;
105 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
106 boolean have_pos = FALSE, have_face = FALSE;
107
108 /* clear previous register */
109 rstate->nregs = 0;
110
111 for (i = 0; i < rshader->ninput; i++) {
112 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
113 tmp |= S_028644_SEL_CENTROID(1);
114 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
115 have_pos = TRUE;
116 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
117 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
118 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
119 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
120 }
121 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
122 have_face = TRUE;
123 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
124 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
125 tmp |= S_028644_PT_SPRITE_TEX(1);
126 }
127 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
128 }
129 for (i = 0; i < rshader->noutput; i++) {
130 r600_pipe_state_add_reg(rstate,
131 R_02880C_DB_SHADER_CONTROL,
132 S_02880C_Z_EXPORT_ENABLE(1),
133 S_02880C_Z_EXPORT_ENABLE(1), NULL);
134 }
135
136 exports_ps = 0;
137 num_cout = 0;
138 for (i = 0; i < rshader->noutput; i++) {
139 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
140 exports_ps |= 1;
141 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
142 num_cout++;
143 }
144 }
145 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
146 if (!exports_ps) {
147 /* always at least export 1 component per pixel */
148 exports_ps = 2;
149 }
150
151 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
152 S_0286CC_PERSP_GRADIENT_ENA(1);
153 spi_input_z = 0;
154 if (have_pos) {
155 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
156 S_0286CC_BARYC_SAMPLE_CNTL(1);
157 spi_input_z |= 1;
158 }
159 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
160 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, S_0286D0_FRONT_FACE_ENA(have_face), 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate,
163 R_028840_SQ_PGM_START_PS,
164 0x00000000, 0xFFFFFFFF, shader->bo);
165 r600_pipe_state_add_reg(rstate,
166 R_028850_SQ_PGM_RESOURCES_PS,
167 S_028868_NUM_GPRS(rshader->bc.ngpr) |
168 S_028868_STACK_SIZE(rshader->bc.nstack),
169 0xFFFFFFFF, NULL);
170 r600_pipe_state_add_reg(rstate,
171 R_028854_SQ_PGM_EXPORTS_PS,
172 exports_ps, 0xFFFFFFFF, NULL);
173 r600_pipe_state_add_reg(rstate,
174 R_0288CC_SQ_PGM_CF_OFFSET_PS,
175 0x00000000, 0xFFFFFFFF, NULL);
176
177 if (rshader->uses_kill) {
178 /* only set some bits here, the other bits are set in the dsa state */
179 r600_pipe_state_add_reg(rstate,
180 R_02880C_DB_SHADER_CONTROL,
181 S_02880C_KILL_ENABLE(1),
182 S_02880C_KILL_ENABLE(1), NULL);
183 }
184 }
185
186 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
187 {
188 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
189 struct r600_shader *rshader = &shader->shader;
190 void *ptr;
191
192 /* copy new shader */
193 if (shader->bo == NULL) {
194 shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
195 if (shader->bo == NULL) {
196 return -ENOMEM;
197 }
198 ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
199 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
200 radeon_ws_bo_unmap(rctx->radeon, shader->bo);
201 }
202 /* build state */
203 rshader->flat_shade = rctx->flatshade;
204 switch (rshader->processor_type) {
205 case TGSI_PROCESSOR_VERTEX:
206 if (rshader->family >= CHIP_CEDAR) {
207 evergreen_pipe_shader_vs(ctx, shader);
208 } else {
209 r600_pipe_shader_vs(ctx, shader);
210 }
211 break;
212 case TGSI_PROCESSOR_FRAGMENT:
213 if (rshader->family >= CHIP_CEDAR) {
214 evergreen_pipe_shader_ps(ctx, shader);
215 } else {
216 r600_pipe_shader_ps(ctx, shader);
217 }
218 break;
219 default:
220 return -EINVAL;
221 }
222 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
223 return 0;
224 }
225
226 static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
227 {
228 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
229 struct r600_shader *shader = &rshader->shader;
230 const struct util_format_description *desc;
231 enum pipe_format resource_format[160];
232 unsigned i, nresources = 0;
233 struct r600_bc *bc = &shader->bc;
234 struct r600_bc_cf *cf;
235 struct r600_bc_vtx *vtx;
236
237 if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
238 return 0;
239 if (!memcmp(&rshader->vertex_elements, rctx->vertex_elements, sizeof(struct r600_vertex_element))) {
240 return 0;
241 }
242 rshader->vertex_elements = *rctx->vertex_elements;
243 for (i = 0; i < rctx->vertex_elements->count; i++) {
244 resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
245 }
246 radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
247 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
248 switch (cf->inst) {
249 case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
250 case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
251 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
252 desc = util_format_description(resource_format[vtx->buffer_id]);
253 if (desc == NULL) {
254 R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
255 return -EINVAL;
256 }
257 vtx->dst_sel_x = desc->swizzle[0];
258 vtx->dst_sel_y = desc->swizzle[1];
259 vtx->dst_sel_z = desc->swizzle[2];
260 vtx->dst_sel_w = desc->swizzle[3];
261 }
262 break;
263 default:
264 break;
265 }
266 }
267 return r600_bc_build(&shader->bc);
268 }
269
270 int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
271 {
272 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
273 int r;
274
275 if (shader == NULL)
276 return -EINVAL;
277 /* there should be enough input */
278 if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
279 R600_ERR("%d resources provided, expecting %d\n",
280 rctx->vertex_elements->count, shader->shader.bc.nresource);
281 return -EINVAL;
282 }
283 r = r600_shader_update(ctx, shader);
284 if (r)
285 return r;
286 return r600_pipe_shader(ctx, shader);
287 }
288
289 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
290 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
291 {
292 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
293 int r;
294
295 //fprintf(stderr, "--------------------------------------------------------------\n");
296 //tgsi_dump(tokens, 0);
297 shader->shader.family = r600_get_family(rctx->radeon);
298 r = r600_shader_from_tgsi(tokens, &shader->shader);
299 if (r) {
300 R600_ERR("translation from TGSI failed !\n");
301 return r;
302 }
303 r = r600_bc_build(&shader->shader.bc);
304 if (r) {
305 R600_ERR("building bytecode failed !\n");
306 return r;
307 }
308 //fprintf(stderr, "______________________________________________________________\n");
309 return 0;
310 }
311
312 /*
313 * tgsi -> r600 shader
314 */
315 struct r600_shader_tgsi_instruction;
316
317 struct r600_shader_ctx {
318 struct tgsi_shader_info info;
319 struct tgsi_parse_context parse;
320 const struct tgsi_token *tokens;
321 unsigned type;
322 unsigned file_offset[TGSI_FILE_COUNT];
323 unsigned temp_reg;
324 struct r600_shader_tgsi_instruction *inst_info;
325 struct r600_bc *bc;
326 struct r600_shader *shader;
327 u32 value[4];
328 u32 *literals;
329 u32 nliterals;
330 u32 max_driver_temp_used;
331 };
332
333 struct r600_shader_tgsi_instruction {
334 unsigned tgsi_opcode;
335 unsigned is_op3;
336 unsigned r600_opcode;
337 int (*process)(struct r600_shader_ctx *ctx);
338 };
339
340 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
341 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
342
343 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
344 {
345 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
346 int j;
347
348 if (i->Instruction.NumDstRegs > 1) {
349 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
350 return -EINVAL;
351 }
352 if (i->Instruction.Predicate) {
353 R600_ERR("predicate unsupported\n");
354 return -EINVAL;
355 }
356 #if 0
357 if (i->Instruction.Label) {
358 R600_ERR("label unsupported\n");
359 return -EINVAL;
360 }
361 #endif
362 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
363 if (i->Src[j].Register.Dimension ||
364 i->Src[j].Register.Absolute) {
365 R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
366 i->Src[j].Register.Dimension,
367 i->Src[j].Register.Absolute);
368 return -EINVAL;
369 }
370 }
371 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
372 if (i->Dst[j].Register.Dimension) {
373 R600_ERR("unsupported dst (dimension)\n");
374 return -EINVAL;
375 }
376 }
377 return 0;
378 }
379
380 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
381 {
382 int i, r;
383 struct r600_bc_alu alu;
384
385 for (i = 0; i < 8; i++) {
386 memset(&alu, 0, sizeof(struct r600_bc_alu));
387
388 if (i < 4)
389 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
390 else
391 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
392
393 if ((i > 1) && (i < 6)) {
394 alu.dst.sel = ctx->shader->input[gpr].gpr;
395 alu.dst.write = 1;
396 }
397
398 alu.dst.chan = i % 4;
399 alu.src[0].chan = (1 - (i % 2));
400 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
401
402 alu.bank_swizzle_force = SQ_ALU_VEC_210;
403 if ((i % 4) == 3)
404 alu.last = 1;
405 r = r600_bc_add_alu(ctx->bc, &alu);
406 if (r)
407 return r;
408 }
409 return 0;
410 }
411
412
413 static int tgsi_declaration(struct r600_shader_ctx *ctx)
414 {
415 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
416 struct r600_bc_vtx vtx;
417 unsigned i;
418 int r;
419
420 switch (d->Declaration.File) {
421 case TGSI_FILE_INPUT:
422 i = ctx->shader->ninput++;
423 ctx->shader->input[i].name = d->Semantic.Name;
424 ctx->shader->input[i].sid = d->Semantic.Index;
425 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
426 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
427 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
428 /* turn input into fetch */
429 memset(&vtx, 0, sizeof(struct r600_bc_vtx));
430 vtx.inst = 0;
431 vtx.fetch_type = 0;
432 vtx.buffer_id = i;
433 /* register containing the index into the buffer */
434 vtx.src_gpr = 0;
435 vtx.src_sel_x = 0;
436 vtx.mega_fetch_count = 0x1F;
437 vtx.dst_gpr = ctx->shader->input[i].gpr;
438 vtx.dst_sel_x = 0;
439 vtx.dst_sel_y = 1;
440 vtx.dst_sel_z = 2;
441 vtx.dst_sel_w = 3;
442 r = r600_bc_add_vtx(ctx->bc, &vtx);
443 if (r)
444 return r;
445 }
446 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
447 /* turn input into interpolate on EG */
448 evergreen_interp_alu(ctx, i);
449 }
450 break;
451 case TGSI_FILE_OUTPUT:
452 i = ctx->shader->noutput++;
453 ctx->shader->output[i].name = d->Semantic.Name;
454 ctx->shader->output[i].sid = d->Semantic.Index;
455 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
456 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
457 break;
458 case TGSI_FILE_CONSTANT:
459 case TGSI_FILE_TEMPORARY:
460 case TGSI_FILE_SAMPLER:
461 case TGSI_FILE_ADDRESS:
462 break;
463 default:
464 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
465 return -EINVAL;
466 }
467 return 0;
468 }
469
470 static int r600_get_temp(struct r600_shader_ctx *ctx)
471 {
472 return ctx->temp_reg + ctx->max_driver_temp_used++;
473 }
474
475 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
476 {
477 struct tgsi_full_immediate *immediate;
478 struct r600_shader_ctx ctx;
479 struct r600_bc_output output[32];
480 unsigned output_done, noutput;
481 unsigned opcode;
482 int i, r = 0, pos0;
483
484 ctx.bc = &shader->bc;
485 ctx.shader = shader;
486 r = r600_bc_init(ctx.bc, shader->family);
487 if (r)
488 return r;
489 ctx.bc->use_mem_constant = shader->use_mem_constant;
490 ctx.tokens = tokens;
491 tgsi_scan_shader(tokens, &ctx.info);
492 tgsi_parse_init(&ctx.parse, tokens);
493 ctx.type = ctx.parse.FullHeader.Processor.Processor;
494 shader->processor_type = ctx.type;
495
496 /* register allocations */
497 /* Values [0,127] correspond to GPR[0..127].
498 * Values [128,159] correspond to constant buffer bank 0
499 * Values [160,191] correspond to constant buffer bank 1
500 * Values [256,511] correspond to cfile constants c[0..255].
501 * Other special values are shown in the list below.
502 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
503 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
504 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
505 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
506 * 248 SQ_ALU_SRC_0: special constant 0.0.
507 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
508 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
509 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
510 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
511 * 253 SQ_ALU_SRC_LITERAL: literal constant.
512 * 254 SQ_ALU_SRC_PV: previous vector result.
513 * 255 SQ_ALU_SRC_PS: previous scalar result.
514 */
515 for (i = 0; i < TGSI_FILE_COUNT; i++) {
516 ctx.file_offset[i] = 0;
517 }
518 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
519 ctx.file_offset[TGSI_FILE_INPUT] = 1;
520 }
521 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
522 ctx.info.file_count[TGSI_FILE_INPUT];
523 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
524 ctx.info.file_count[TGSI_FILE_OUTPUT];
525 if (ctx.shader->use_mem_constant)
526 ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
527 else
528 ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
529
530 ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
531 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
532 ctx.info.file_count[TGSI_FILE_TEMPORARY];
533
534 ctx.nliterals = 0;
535 ctx.literals = NULL;
536
537 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
538 tgsi_parse_token(&ctx.parse);
539 switch (ctx.parse.FullToken.Token.Type) {
540 case TGSI_TOKEN_TYPE_IMMEDIATE:
541 immediate = &ctx.parse.FullToken.FullImmediate;
542 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
543 if(ctx.literals == NULL) {
544 r = -ENOMEM;
545 goto out_err;
546 }
547 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
548 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
549 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
550 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
551 ctx.nliterals++;
552 break;
553 case TGSI_TOKEN_TYPE_DECLARATION:
554 r = tgsi_declaration(&ctx);
555 if (r)
556 goto out_err;
557 break;
558 case TGSI_TOKEN_TYPE_INSTRUCTION:
559 r = tgsi_is_supported(&ctx);
560 if (r)
561 goto out_err;
562 ctx.max_driver_temp_used = 0;
563 /* reserve first tmp for everyone */
564 r600_get_temp(&ctx);
565 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
566 if (ctx.bc->chiprev == 2)
567 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
568 else
569 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
570 r = ctx.inst_info->process(&ctx);
571 if (r)
572 goto out_err;
573 r = r600_bc_add_literal(ctx.bc, ctx.value);
574 if (r)
575 goto out_err;
576 break;
577 default:
578 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
579 r = -EINVAL;
580 goto out_err;
581 }
582 }
583 /* export output */
584 noutput = shader->noutput;
585 for (i = 0, pos0 = 0; i < noutput; i++) {
586 memset(&output[i], 0, sizeof(struct r600_bc_output));
587 output[i].gpr = shader->output[i].gpr;
588 output[i].elem_size = 3;
589 output[i].swizzle_x = 0;
590 output[i].swizzle_y = 1;
591 output[i].swizzle_z = 2;
592 output[i].swizzle_w = 3;
593 output[i].barrier = 1;
594 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
595 output[i].array_base = i - pos0;
596 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
597 switch (ctx.type) {
598 case TGSI_PROCESSOR_VERTEX:
599 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
600 output[i].array_base = 60;
601 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
602 /* position doesn't count in array_base */
603 pos0++;
604 }
605 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
606 output[i].array_base = 61;
607 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
608 /* position doesn't count in array_base */
609 pos0++;
610 }
611 break;
612 case TGSI_PROCESSOR_FRAGMENT:
613 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
614 output[i].array_base = shader->output[i].sid;
615 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
616 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
617 output[i].array_base = 61;
618 output[i].swizzle_x = 2;
619 output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
620 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
621 } else {
622 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
623 r = -EINVAL;
624 goto out_err;
625 }
626 break;
627 default:
628 R600_ERR("unsupported processor type %d\n", ctx.type);
629 r = -EINVAL;
630 goto out_err;
631 }
632 }
633 /* add fake param output for vertex shader if no param is exported */
634 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
635 for (i = 0, pos0 = 0; i < noutput; i++) {
636 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
637 pos0 = 1;
638 break;
639 }
640 }
641 if (!pos0) {
642 memset(&output[i], 0, sizeof(struct r600_bc_output));
643 output[i].gpr = 0;
644 output[i].elem_size = 3;
645 output[i].swizzle_x = 0;
646 output[i].swizzle_y = 1;
647 output[i].swizzle_z = 2;
648 output[i].swizzle_w = 3;
649 output[i].barrier = 1;
650 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
651 output[i].array_base = 0;
652 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
653 noutput++;
654 }
655 }
656 /* add fake pixel export */
657 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
658 memset(&output[0], 0, sizeof(struct r600_bc_output));
659 output[0].gpr = 0;
660 output[0].elem_size = 3;
661 output[0].swizzle_x = 7;
662 output[0].swizzle_y = 7;
663 output[0].swizzle_z = 7;
664 output[0].swizzle_w = 7;
665 output[0].barrier = 1;
666 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
667 output[0].array_base = 0;
668 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
669 noutput++;
670 }
671 /* set export done on last export of each type */
672 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
673 if (i == (noutput - 1)) {
674 output[i].end_of_program = 1;
675 }
676 if (!(output_done & (1 << output[i].type))) {
677 output_done |= (1 << output[i].type);
678 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
679 }
680 }
681 /* add output to bytecode */
682 for (i = 0; i < noutput; i++) {
683 r = r600_bc_add_output(ctx.bc, &output[i]);
684 if (r)
685 goto out_err;
686 }
687 free(ctx.literals);
688 tgsi_parse_free(&ctx.parse);
689 return 0;
690 out_err:
691 free(ctx.literals);
692 tgsi_parse_free(&ctx.parse);
693 return r;
694 }
695
696 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
697 {
698 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
699 return -EINVAL;
700 }
701
702 static int tgsi_end(struct r600_shader_ctx *ctx)
703 {
704 return 0;
705 }
706
707 static int tgsi_src(struct r600_shader_ctx *ctx,
708 const struct tgsi_full_src_register *tgsi_src,
709 struct r600_bc_alu_src *r600_src)
710 {
711 int index;
712 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
713 r600_src->sel = tgsi_src->Register.Index;
714 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
715 r600_src->sel = 0;
716 index = tgsi_src->Register.Index;
717 ctx->value[0] = ctx->literals[index * 4 + 0];
718 ctx->value[1] = ctx->literals[index * 4 + 1];
719 ctx->value[2] = ctx->literals[index * 4 + 2];
720 ctx->value[3] = ctx->literals[index * 4 + 3];
721 }
722 if (tgsi_src->Register.Indirect)
723 r600_src->rel = V_SQ_REL_RELATIVE;
724 r600_src->neg = tgsi_src->Register.Negate;
725 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
726 return 0;
727 }
728
729 static int tgsi_dst(struct r600_shader_ctx *ctx,
730 const struct tgsi_full_dst_register *tgsi_dst,
731 unsigned swizzle,
732 struct r600_bc_alu_dst *r600_dst)
733 {
734 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
735
736 r600_dst->sel = tgsi_dst->Register.Index;
737 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
738 r600_dst->chan = swizzle;
739 r600_dst->write = 1;
740 if (tgsi_dst->Register.Indirect)
741 r600_dst->rel = V_SQ_REL_RELATIVE;
742 if (inst->Instruction.Saturate) {
743 r600_dst->clamp = 1;
744 }
745 return 0;
746 }
747
748 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
749 {
750 switch (swizzle) {
751 case 0:
752 return tgsi_src->Register.SwizzleX;
753 case 1:
754 return tgsi_src->Register.SwizzleY;
755 case 2:
756 return tgsi_src->Register.SwizzleZ;
757 case 3:
758 return tgsi_src->Register.SwizzleW;
759 default:
760 return 0;
761 }
762 }
763
764 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
765 {
766 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
767 struct r600_bc_alu alu;
768 int i, j, k, nconst, r;
769
770 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
771 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
772 nconst++;
773 }
774 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
775 if (r) {
776 return r;
777 }
778 }
779 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
780 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
781 int treg = r600_get_temp(ctx);
782 for (k = 0; k < 4; k++) {
783 memset(&alu, 0, sizeof(struct r600_bc_alu));
784 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
785 alu.src[0].sel = r600_src[i].sel;
786 alu.src[0].chan = k;
787 alu.dst.sel = treg;
788 alu.dst.chan = k;
789 alu.dst.write = 1;
790 if (k == 3)
791 alu.last = 1;
792 r = r600_bc_add_alu(ctx->bc, &alu);
793 if (r)
794 return r;
795 }
796 r600_src[i].sel = treg;
797 j--;
798 }
799 }
800 return 0;
801 }
802
803 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
804 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
805 {
806 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
807 struct r600_bc_alu alu;
808 int i, j, k, nliteral, r, index;
809
810 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
811 if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
812 nliteral++;
813 }
814 }
815 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
816 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
817 int treg = r600_get_temp(ctx);
818 for (k = 0; k < 4; k++) {
819 memset(&alu, 0, sizeof(struct r600_bc_alu));
820 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
821 alu.src[0].sel = r600_src[i].sel;
822 alu.src[0].chan = k;
823 alu.dst.sel = treg;
824 alu.dst.chan = k;
825 alu.dst.write = 1;
826 if (k == 3)
827 alu.last = 1;
828 r = r600_bc_add_alu(ctx->bc, &alu);
829 if (r)
830 return r;
831 }
832 r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
833 if (r)
834 return r;
835 r600_src[i].sel = treg;
836 j--;
837 }
838 }
839 return 0;
840 }
841
842 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
843 {
844 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
845 struct r600_bc_alu_src r600_src[3];
846 struct r600_bc_alu alu;
847 int i, j, r;
848 int lasti = 0;
849
850 for (i = 0; i < 4; i++) {
851 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
852 lasti = i;
853 }
854 }
855
856 r = tgsi_split_constant(ctx, r600_src);
857 if (r)
858 return r;
859 r = tgsi_split_literal_constant(ctx, r600_src);
860 if (r)
861 return r;
862 for (i = 0; i < lasti + 1; i++) {
863 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
864 continue;
865
866 memset(&alu, 0, sizeof(struct r600_bc_alu));
867 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
868 if (r)
869 return r;
870
871 alu.inst = ctx->inst_info->r600_opcode;
872 if (!swap) {
873 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
874 alu.src[j] = r600_src[j];
875 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
876 }
877 } else {
878 alu.src[0] = r600_src[1];
879 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
880
881 alu.src[1] = r600_src[0];
882 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
883 }
884 /* handle some special cases */
885 switch (ctx->inst_info->tgsi_opcode) {
886 case TGSI_OPCODE_SUB:
887 alu.src[1].neg = 1;
888 break;
889 case TGSI_OPCODE_ABS:
890 alu.src[0].abs = 1;
891 break;
892 default:
893 break;
894 }
895 if (i == lasti) {
896 alu.last = 1;
897 }
898 r = r600_bc_add_alu(ctx->bc, &alu);
899 if (r)
900 return r;
901 }
902 return 0;
903 }
904
905 static int tgsi_op2(struct r600_shader_ctx *ctx)
906 {
907 return tgsi_op2_s(ctx, 0);
908 }
909
910 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
911 {
912 return tgsi_op2_s(ctx, 1);
913 }
914
915 /*
916 * r600 - trunc to -PI..PI range
917 * r700 - normalize by dividing by 2PI
918 * see fdo bug 27901
919 */
920 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
921 struct r600_bc_alu_src r600_src[3])
922 {
923 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
924 int r;
925 uint32_t lit_vals[4];
926 struct r600_bc_alu alu;
927
928 memset(lit_vals, 0, 4*4);
929 r = tgsi_split_constant(ctx, r600_src);
930 if (r)
931 return r;
932 r = tgsi_split_literal_constant(ctx, r600_src);
933 if (r)
934 return r;
935
936 r = tgsi_split_literal_constant(ctx, r600_src);
937 if (r)
938 return r;
939
940 lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
941 lit_vals[1] = fui(0.5f);
942
943 memset(&alu, 0, sizeof(struct r600_bc_alu));
944 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
945 alu.is_op3 = 1;
946
947 alu.dst.chan = 0;
948 alu.dst.sel = ctx->temp_reg;
949 alu.dst.write = 1;
950
951 alu.src[0] = r600_src[0];
952 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
953
954 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
955 alu.src[1].chan = 0;
956 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
957 alu.src[2].chan = 1;
958 alu.last = 1;
959 r = r600_bc_add_alu(ctx->bc, &alu);
960 if (r)
961 return r;
962 r = r600_bc_add_literal(ctx->bc, lit_vals);
963 if (r)
964 return r;
965
966 memset(&alu, 0, sizeof(struct r600_bc_alu));
967 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
968
969 alu.dst.chan = 0;
970 alu.dst.sel = ctx->temp_reg;
971 alu.dst.write = 1;
972
973 alu.src[0].sel = ctx->temp_reg;
974 alu.src[0].chan = 0;
975 alu.last = 1;
976 r = r600_bc_add_alu(ctx->bc, &alu);
977 if (r)
978 return r;
979
980 if (ctx->bc->chiprev == 0) {
981 lit_vals[0] = fui(3.1415926535897f * 2.0f);
982 lit_vals[1] = fui(-3.1415926535897f);
983 } else {
984 lit_vals[0] = fui(1.0f);
985 lit_vals[1] = fui(-0.5f);
986 }
987
988 memset(&alu, 0, sizeof(struct r600_bc_alu));
989 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
990 alu.is_op3 = 1;
991
992 alu.dst.chan = 0;
993 alu.dst.sel = ctx->temp_reg;
994 alu.dst.write = 1;
995
996 alu.src[0].sel = ctx->temp_reg;
997 alu.src[0].chan = 0;
998
999 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1000 alu.src[1].chan = 0;
1001 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1002 alu.src[2].chan = 1;
1003 alu.last = 1;
1004 r = r600_bc_add_alu(ctx->bc, &alu);
1005 if (r)
1006 return r;
1007 r = r600_bc_add_literal(ctx->bc, lit_vals);
1008 if (r)
1009 return r;
1010 return 0;
1011 }
1012
1013 static int tgsi_trig(struct r600_shader_ctx *ctx)
1014 {
1015 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1016 struct r600_bc_alu_src r600_src[3];
1017 struct r600_bc_alu alu;
1018 int i, r;
1019 int lasti = 0;
1020
1021 r = tgsi_setup_trig(ctx, r600_src);
1022 if (r)
1023 return r;
1024
1025 memset(&alu, 0, sizeof(struct r600_bc_alu));
1026 alu.inst = ctx->inst_info->r600_opcode;
1027 alu.dst.chan = 0;
1028 alu.dst.sel = ctx->temp_reg;
1029 alu.dst.write = 1;
1030
1031 alu.src[0].sel = ctx->temp_reg;
1032 alu.src[0].chan = 0;
1033 alu.last = 1;
1034 r = r600_bc_add_alu(ctx->bc, &alu);
1035 if (r)
1036 return r;
1037
1038 /* replicate result */
1039 for (i = 0; i < 4; i++) {
1040 if (inst->Dst[0].Register.WriteMask & (1 << i))
1041 lasti = i;
1042 }
1043 for (i = 0; i < lasti + 1; i++) {
1044 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1045 continue;
1046
1047 memset(&alu, 0, sizeof(struct r600_bc_alu));
1048 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1049
1050 alu.src[0].sel = ctx->temp_reg;
1051 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1052 if (r)
1053 return r;
1054 if (i == lasti)
1055 alu.last = 1;
1056 r = r600_bc_add_alu(ctx->bc, &alu);
1057 if (r)
1058 return r;
1059 }
1060 return 0;
1061 }
1062
1063 static int tgsi_scs(struct r600_shader_ctx *ctx)
1064 {
1065 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1066 struct r600_bc_alu_src r600_src[3];
1067 struct r600_bc_alu alu;
1068 int r;
1069
1070 /* We'll only need the trig stuff if we are going to write to the
1071 * X or Y components of the destination vector.
1072 */
1073 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1074 r = tgsi_setup_trig(ctx, r600_src);
1075 if (r)
1076 return r;
1077 }
1078
1079 /* dst.x = COS */
1080 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1081 memset(&alu, 0, sizeof(struct r600_bc_alu));
1082 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1083 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1084 if (r)
1085 return r;
1086
1087 alu.src[0].sel = ctx->temp_reg;
1088 alu.src[0].chan = 0;
1089 alu.last = 1;
1090 r = r600_bc_add_alu(ctx->bc, &alu);
1091 if (r)
1092 return r;
1093 }
1094
1095 /* dst.y = SIN */
1096 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1097 memset(&alu, 0, sizeof(struct r600_bc_alu));
1098 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1099 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1100 if (r)
1101 return r;
1102
1103 alu.src[0].sel = ctx->temp_reg;
1104 alu.src[0].chan = 0;
1105 alu.last = 1;
1106 r = r600_bc_add_alu(ctx->bc, &alu);
1107 if (r)
1108 return r;
1109 }
1110
1111 /* dst.z = 0.0; */
1112 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1113 memset(&alu, 0, sizeof(struct r600_bc_alu));
1114
1115 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1116
1117 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1118 if (r)
1119 return r;
1120
1121 alu.src[0].sel = V_SQ_ALU_SRC_0;
1122 alu.src[0].chan = 0;
1123
1124 alu.last = 1;
1125
1126 r = r600_bc_add_alu(ctx->bc, &alu);
1127 if (r)
1128 return r;
1129
1130 r = r600_bc_add_literal(ctx->bc, ctx->value);
1131 if (r)
1132 return r;
1133 }
1134
1135 /* dst.w = 1.0; */
1136 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1137 memset(&alu, 0, sizeof(struct r600_bc_alu));
1138
1139 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1140
1141 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1142 if (r)
1143 return r;
1144
1145 alu.src[0].sel = V_SQ_ALU_SRC_1;
1146 alu.src[0].chan = 0;
1147
1148 alu.last = 1;
1149
1150 r = r600_bc_add_alu(ctx->bc, &alu);
1151 if (r)
1152 return r;
1153
1154 r = r600_bc_add_literal(ctx->bc, ctx->value);
1155 if (r)
1156 return r;
1157 }
1158
1159 return 0;
1160 }
1161
1162 static int tgsi_kill(struct r600_shader_ctx *ctx)
1163 {
1164 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1165 struct r600_bc_alu alu;
1166 int i, r;
1167
1168 for (i = 0; i < 4; i++) {
1169 memset(&alu, 0, sizeof(struct r600_bc_alu));
1170 alu.inst = ctx->inst_info->r600_opcode;
1171
1172 alu.dst.chan = i;
1173
1174 alu.src[0].sel = V_SQ_ALU_SRC_0;
1175
1176 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1177 alu.src[1].sel = V_SQ_ALU_SRC_1;
1178 alu.src[1].neg = 1;
1179 } else {
1180 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1181 if (r)
1182 return r;
1183 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1184 }
1185 if (i == 3) {
1186 alu.last = 1;
1187 }
1188 r = r600_bc_add_alu(ctx->bc, &alu);
1189 if (r)
1190 return r;
1191 }
1192 r = r600_bc_add_literal(ctx->bc, ctx->value);
1193 if (r)
1194 return r;
1195
1196 /* kill must be last in ALU */
1197 ctx->bc->force_add_cf = 1;
1198 ctx->shader->uses_kill = TRUE;
1199 return 0;
1200 }
1201
1202 static int tgsi_lit(struct r600_shader_ctx *ctx)
1203 {
1204 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1205 struct r600_bc_alu alu;
1206 struct r600_bc_alu_src r600_src[3];
1207 int r;
1208
1209 r = tgsi_split_constant(ctx, r600_src);
1210 if (r)
1211 return r;
1212 r = tgsi_split_literal_constant(ctx, r600_src);
1213 if (r)
1214 return r;
1215
1216 /* dst.x, <- 1.0 */
1217 memset(&alu, 0, sizeof(struct r600_bc_alu));
1218 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1219 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1220 alu.src[0].chan = 0;
1221 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1222 if (r)
1223 return r;
1224 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1225 r = r600_bc_add_alu(ctx->bc, &alu);
1226 if (r)
1227 return r;
1228
1229 /* dst.y = max(src.x, 0.0) */
1230 memset(&alu, 0, sizeof(struct r600_bc_alu));
1231 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1232 alu.src[0] = r600_src[0];
1233 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1234 alu.src[1].chan = 0;
1235 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1236 if (r)
1237 return r;
1238 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1239 r = r600_bc_add_alu(ctx->bc, &alu);
1240 if (r)
1241 return r;
1242
1243 /* dst.w, <- 1.0 */
1244 memset(&alu, 0, sizeof(struct r600_bc_alu));
1245 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1246 alu.src[0].sel = V_SQ_ALU_SRC_1;
1247 alu.src[0].chan = 0;
1248 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1249 if (r)
1250 return r;
1251 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1252 alu.last = 1;
1253 r = r600_bc_add_alu(ctx->bc, &alu);
1254 if (r)
1255 return r;
1256
1257 r = r600_bc_add_literal(ctx->bc, ctx->value);
1258 if (r)
1259 return r;
1260
1261 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1262 {
1263 int chan;
1264 int sel;
1265
1266 /* dst.z = log(src.y) */
1267 memset(&alu, 0, sizeof(struct r600_bc_alu));
1268 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1269 alu.src[0] = r600_src[0];
1270 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1271 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1272 if (r)
1273 return r;
1274 alu.last = 1;
1275 r = r600_bc_add_alu(ctx->bc, &alu);
1276 if (r)
1277 return r;
1278
1279 r = r600_bc_add_literal(ctx->bc, ctx->value);
1280 if (r)
1281 return r;
1282
1283 chan = alu.dst.chan;
1284 sel = alu.dst.sel;
1285
1286 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1287 memset(&alu, 0, sizeof(struct r600_bc_alu));
1288 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1289 alu.src[0] = r600_src[0];
1290 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1291 alu.src[1].sel = sel;
1292 alu.src[1].chan = chan;
1293
1294 alu.src[2] = r600_src[0];
1295 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1296 alu.dst.sel = ctx->temp_reg;
1297 alu.dst.chan = 0;
1298 alu.dst.write = 1;
1299 alu.is_op3 = 1;
1300 alu.last = 1;
1301 r = r600_bc_add_alu(ctx->bc, &alu);
1302 if (r)
1303 return r;
1304
1305 r = r600_bc_add_literal(ctx->bc, ctx->value);
1306 if (r)
1307 return r;
1308 /* dst.z = exp(tmp.x) */
1309 memset(&alu, 0, sizeof(struct r600_bc_alu));
1310 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1311 alu.src[0].sel = ctx->temp_reg;
1312 alu.src[0].chan = 0;
1313 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1314 if (r)
1315 return r;
1316 alu.last = 1;
1317 r = r600_bc_add_alu(ctx->bc, &alu);
1318 if (r)
1319 return r;
1320 }
1321 return 0;
1322 }
1323
1324 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1325 {
1326 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1327 struct r600_bc_alu alu;
1328 int i, r;
1329
1330 memset(&alu, 0, sizeof(struct r600_bc_alu));
1331
1332 /* FIXME:
1333 * For state trackers other than OpenGL, we'll want to use
1334 * _RECIPSQRT_IEEE instead.
1335 */
1336 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1337
1338 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1339 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1340 if (r)
1341 return r;
1342 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1343 alu.src[i].abs = 1;
1344 }
1345 alu.dst.sel = ctx->temp_reg;
1346 alu.dst.write = 1;
1347 alu.last = 1;
1348 r = r600_bc_add_alu(ctx->bc, &alu);
1349 if (r)
1350 return r;
1351 r = r600_bc_add_literal(ctx->bc, ctx->value);
1352 if (r)
1353 return r;
1354 /* replicate result */
1355 return tgsi_helper_tempx_replicate(ctx);
1356 }
1357
1358 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1359 {
1360 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1361 struct r600_bc_alu alu;
1362 int i, r;
1363
1364 for (i = 0; i < 4; i++) {
1365 memset(&alu, 0, sizeof(struct r600_bc_alu));
1366 alu.src[0].sel = ctx->temp_reg;
1367 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1368 alu.dst.chan = i;
1369 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1370 if (r)
1371 return r;
1372 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1373 if (i == 3)
1374 alu.last = 1;
1375 r = r600_bc_add_alu(ctx->bc, &alu);
1376 if (r)
1377 return r;
1378 }
1379 return 0;
1380 }
1381
1382 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1383 {
1384 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1385 struct r600_bc_alu alu;
1386 int i, r;
1387
1388 memset(&alu, 0, sizeof(struct r600_bc_alu));
1389 alu.inst = ctx->inst_info->r600_opcode;
1390 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1391 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1392 if (r)
1393 return r;
1394 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1395 }
1396 alu.dst.sel = ctx->temp_reg;
1397 alu.dst.write = 1;
1398 alu.last = 1;
1399 r = r600_bc_add_alu(ctx->bc, &alu);
1400 if (r)
1401 return r;
1402 r = r600_bc_add_literal(ctx->bc, ctx->value);
1403 if (r)
1404 return r;
1405 /* replicate result */
1406 return tgsi_helper_tempx_replicate(ctx);
1407 }
1408
1409 static int tgsi_pow(struct r600_shader_ctx *ctx)
1410 {
1411 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1412 struct r600_bc_alu alu;
1413 int r;
1414
1415 /* LOG2(a) */
1416 memset(&alu, 0, sizeof(struct r600_bc_alu));
1417 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1418 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1419 if (r)
1420 return r;
1421 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1422 alu.dst.sel = ctx->temp_reg;
1423 alu.dst.write = 1;
1424 alu.last = 1;
1425 r = r600_bc_add_alu(ctx->bc, &alu);
1426 if (r)
1427 return r;
1428 r = r600_bc_add_literal(ctx->bc,ctx->value);
1429 if (r)
1430 return r;
1431 /* b * LOG2(a) */
1432 memset(&alu, 0, sizeof(struct r600_bc_alu));
1433 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE);
1434 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1435 if (r)
1436 return r;
1437 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1438 alu.src[1].sel = ctx->temp_reg;
1439 alu.dst.sel = ctx->temp_reg;
1440 alu.dst.write = 1;
1441 alu.last = 1;
1442 r = r600_bc_add_alu(ctx->bc, &alu);
1443 if (r)
1444 return r;
1445 r = r600_bc_add_literal(ctx->bc,ctx->value);
1446 if (r)
1447 return r;
1448 /* POW(a,b) = EXP2(b * LOG2(a))*/
1449 memset(&alu, 0, sizeof(struct r600_bc_alu));
1450 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1451 alu.src[0].sel = ctx->temp_reg;
1452 alu.dst.sel = ctx->temp_reg;
1453 alu.dst.write = 1;
1454 alu.last = 1;
1455 r = r600_bc_add_alu(ctx->bc, &alu);
1456 if (r)
1457 return r;
1458 r = r600_bc_add_literal(ctx->bc,ctx->value);
1459 if (r)
1460 return r;
1461 return tgsi_helper_tempx_replicate(ctx);
1462 }
1463
1464 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1465 {
1466 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1467 struct r600_bc_alu alu;
1468 struct r600_bc_alu_src r600_src[3];
1469 int i, r;
1470
1471 r = tgsi_split_constant(ctx, r600_src);
1472 if (r)
1473 return r;
1474 r = tgsi_split_literal_constant(ctx, r600_src);
1475 if (r)
1476 return r;
1477
1478 /* tmp = (src > 0 ? 1 : src) */
1479 for (i = 0; i < 4; i++) {
1480 memset(&alu, 0, sizeof(struct r600_bc_alu));
1481 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1482 alu.is_op3 = 1;
1483
1484 alu.dst.sel = ctx->temp_reg;
1485 alu.dst.chan = i;
1486
1487 alu.src[0] = r600_src[0];
1488 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1489
1490 alu.src[1].sel = V_SQ_ALU_SRC_1;
1491
1492 alu.src[2] = r600_src[0];
1493 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1494 if (i == 3)
1495 alu.last = 1;
1496 r = r600_bc_add_alu(ctx->bc, &alu);
1497 if (r)
1498 return r;
1499 }
1500 r = r600_bc_add_literal(ctx->bc, ctx->value);
1501 if (r)
1502 return r;
1503
1504 /* dst = (-tmp > 0 ? -1 : tmp) */
1505 for (i = 0; i < 4; i++) {
1506 memset(&alu, 0, sizeof(struct r600_bc_alu));
1507 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1508 alu.is_op3 = 1;
1509 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1510 if (r)
1511 return r;
1512
1513 alu.src[0].sel = ctx->temp_reg;
1514 alu.src[0].chan = i;
1515 alu.src[0].neg = 1;
1516
1517 alu.src[1].sel = V_SQ_ALU_SRC_1;
1518 alu.src[1].neg = 1;
1519
1520 alu.src[2].sel = ctx->temp_reg;
1521 alu.src[2].chan = i;
1522
1523 if (i == 3)
1524 alu.last = 1;
1525 r = r600_bc_add_alu(ctx->bc, &alu);
1526 if (r)
1527 return r;
1528 }
1529 return 0;
1530 }
1531
1532 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1533 {
1534 struct r600_bc_alu alu;
1535 int i, r;
1536
1537 r = r600_bc_add_literal(ctx->bc, ctx->value);
1538 if (r)
1539 return r;
1540 for (i = 0; i < 4; i++) {
1541 memset(&alu, 0, sizeof(struct r600_bc_alu));
1542 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1543 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1544 alu.dst.chan = i;
1545 } else {
1546 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1547 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1548 if (r)
1549 return r;
1550 alu.src[0].sel = ctx->temp_reg;
1551 alu.src[0].chan = i;
1552 }
1553 if (i == 3) {
1554 alu.last = 1;
1555 }
1556 r = r600_bc_add_alu(ctx->bc, &alu);
1557 if (r)
1558 return r;
1559 }
1560 return 0;
1561 }
1562
1563 static int tgsi_op3(struct r600_shader_ctx *ctx)
1564 {
1565 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1566 struct r600_bc_alu_src r600_src[3];
1567 struct r600_bc_alu alu;
1568 int i, j, r;
1569
1570 r = tgsi_split_constant(ctx, r600_src);
1571 if (r)
1572 return r;
1573 r = tgsi_split_literal_constant(ctx, r600_src);
1574 if (r)
1575 return r;
1576 /* do it in 2 step as op3 doesn't support writemask */
1577 for (i = 0; i < 4; i++) {
1578 memset(&alu, 0, sizeof(struct r600_bc_alu));
1579 alu.inst = ctx->inst_info->r600_opcode;
1580 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1581 alu.src[j] = r600_src[j];
1582 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1583 }
1584 alu.dst.sel = ctx->temp_reg;
1585 alu.dst.chan = i;
1586 alu.dst.write = 1;
1587 alu.is_op3 = 1;
1588 if (i == 3) {
1589 alu.last = 1;
1590 }
1591 r = r600_bc_add_alu(ctx->bc, &alu);
1592 if (r)
1593 return r;
1594 }
1595 return tgsi_helper_copy(ctx, inst);
1596 }
1597
1598 static int tgsi_dp(struct r600_shader_ctx *ctx)
1599 {
1600 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1601 struct r600_bc_alu_src r600_src[3];
1602 struct r600_bc_alu alu;
1603 int i, j, r;
1604
1605 r = tgsi_split_constant(ctx, r600_src);
1606 if (r)
1607 return r;
1608 r = tgsi_split_literal_constant(ctx, r600_src);
1609 if (r)
1610 return r;
1611 for (i = 0; i < 4; i++) {
1612 memset(&alu, 0, sizeof(struct r600_bc_alu));
1613 alu.inst = ctx->inst_info->r600_opcode;
1614 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1615 alu.src[j] = r600_src[j];
1616 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1617 }
1618 alu.dst.sel = ctx->temp_reg;
1619 alu.dst.chan = i;
1620 alu.dst.write = 1;
1621 /* handle some special cases */
1622 switch (ctx->inst_info->tgsi_opcode) {
1623 case TGSI_OPCODE_DP2:
1624 if (i > 1) {
1625 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1626 alu.src[0].chan = alu.src[1].chan = 0;
1627 }
1628 break;
1629 case TGSI_OPCODE_DP3:
1630 if (i > 2) {
1631 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1632 alu.src[0].chan = alu.src[1].chan = 0;
1633 }
1634 break;
1635 case TGSI_OPCODE_DPH:
1636 if (i == 3) {
1637 alu.src[0].sel = V_SQ_ALU_SRC_1;
1638 alu.src[0].chan = 0;
1639 alu.src[0].neg = 0;
1640 }
1641 break;
1642 default:
1643 break;
1644 }
1645 if (i == 3) {
1646 alu.last = 1;
1647 }
1648 r = r600_bc_add_alu(ctx->bc, &alu);
1649 if (r)
1650 return r;
1651 }
1652 return tgsi_helper_copy(ctx, inst);
1653 }
1654
1655 static int tgsi_tex(struct r600_shader_ctx *ctx)
1656 {
1657 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1658 struct r600_bc_tex tex;
1659 struct r600_bc_alu alu;
1660 unsigned src_gpr;
1661 int r, i;
1662 int opcode;
1663 boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
1664 uint32_t lit_vals[4];
1665
1666 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1667
1668 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1669 /* Add perspective divide */
1670 memset(&alu, 0, sizeof(struct r600_bc_alu));
1671 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1672 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1673 if (r)
1674 return r;
1675
1676 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1677 alu.dst.sel = ctx->temp_reg;
1678 alu.dst.chan = 3;
1679 alu.last = 1;
1680 alu.dst.write = 1;
1681 r = r600_bc_add_alu(ctx->bc, &alu);
1682 if (r)
1683 return r;
1684
1685 for (i = 0; i < 3; i++) {
1686 memset(&alu, 0, sizeof(struct r600_bc_alu));
1687 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1688 alu.src[0].sel = ctx->temp_reg;
1689 alu.src[0].chan = 3;
1690 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1691 if (r)
1692 return r;
1693 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1694 alu.dst.sel = ctx->temp_reg;
1695 alu.dst.chan = i;
1696 alu.dst.write = 1;
1697 r = r600_bc_add_alu(ctx->bc, &alu);
1698 if (r)
1699 return r;
1700 }
1701 memset(&alu, 0, sizeof(struct r600_bc_alu));
1702 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1703 alu.src[0].sel = V_SQ_ALU_SRC_1;
1704 alu.src[0].chan = 0;
1705 alu.dst.sel = ctx->temp_reg;
1706 alu.dst.chan = 3;
1707 alu.last = 1;
1708 alu.dst.write = 1;
1709 r = r600_bc_add_alu(ctx->bc, &alu);
1710 if (r)
1711 return r;
1712 src_not_temp = FALSE;
1713 src_gpr = ctx->temp_reg;
1714 }
1715
1716 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1717 int src_chan, src2_chan;
1718
1719 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1720 for (i = 0; i < 4; i++) {
1721 memset(&alu, 0, sizeof(struct r600_bc_alu));
1722 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1723 switch (i) {
1724 case 0:
1725 src_chan = 2;
1726 src2_chan = 1;
1727 break;
1728 case 1:
1729 src_chan = 2;
1730 src2_chan = 0;
1731 break;
1732 case 2:
1733 src_chan = 0;
1734 src2_chan = 2;
1735 break;
1736 case 3:
1737 src_chan = 1;
1738 src2_chan = 2;
1739 break;
1740 default:
1741 assert(0);
1742 src_chan = 0;
1743 src2_chan = 0;
1744 break;
1745 }
1746 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1747 if (r)
1748 return r;
1749 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1750 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1751 if (r)
1752 return r;
1753 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1754 alu.dst.sel = ctx->temp_reg;
1755 alu.dst.chan = i;
1756 if (i == 3)
1757 alu.last = 1;
1758 alu.dst.write = 1;
1759 r = r600_bc_add_alu(ctx->bc, &alu);
1760 if (r)
1761 return r;
1762 }
1763
1764 /* tmp1.z = RCP_e(|tmp1.z|) */
1765 memset(&alu, 0, sizeof(struct r600_bc_alu));
1766 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1767 alu.src[0].sel = ctx->temp_reg;
1768 alu.src[0].chan = 2;
1769 alu.src[0].abs = 1;
1770 alu.dst.sel = ctx->temp_reg;
1771 alu.dst.chan = 2;
1772 alu.dst.write = 1;
1773 alu.last = 1;
1774 r = r600_bc_add_alu(ctx->bc, &alu);
1775 if (r)
1776 return r;
1777
1778 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1779 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1780 * muladd has no writemask, have to use another temp
1781 */
1782 memset(&alu, 0, sizeof(struct r600_bc_alu));
1783 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1784 alu.is_op3 = 1;
1785
1786 alu.src[0].sel = ctx->temp_reg;
1787 alu.src[0].chan = 0;
1788 alu.src[1].sel = ctx->temp_reg;
1789 alu.src[1].chan = 2;
1790
1791 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1792 alu.src[2].chan = 0;
1793
1794 alu.dst.sel = ctx->temp_reg;
1795 alu.dst.chan = 0;
1796 alu.dst.write = 1;
1797
1798 r = r600_bc_add_alu(ctx->bc, &alu);
1799 if (r)
1800 return r;
1801
1802 memset(&alu, 0, sizeof(struct r600_bc_alu));
1803 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1804 alu.is_op3 = 1;
1805
1806 alu.src[0].sel = ctx->temp_reg;
1807 alu.src[0].chan = 1;
1808 alu.src[1].sel = ctx->temp_reg;
1809 alu.src[1].chan = 2;
1810
1811 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1812 alu.src[2].chan = 0;
1813
1814 alu.dst.sel = ctx->temp_reg;
1815 alu.dst.chan = 1;
1816 alu.dst.write = 1;
1817
1818 alu.last = 1;
1819 r = r600_bc_add_alu(ctx->bc, &alu);
1820 if (r)
1821 return r;
1822
1823 lit_vals[0] = fui(1.5f);
1824
1825 r = r600_bc_add_literal(ctx->bc, lit_vals);
1826 if (r)
1827 return r;
1828 src_not_temp = FALSE;
1829 src_gpr = ctx->temp_reg;
1830 }
1831
1832 if (src_not_temp) {
1833 for (i = 0; i < 4; i++) {
1834 memset(&alu, 0, sizeof(struct r600_bc_alu));
1835 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1836 alu.src[0].sel = src_gpr;
1837 alu.src[0].chan = i;
1838 alu.dst.sel = ctx->temp_reg;
1839 alu.dst.chan = i;
1840 if (i == 3)
1841 alu.last = 1;
1842 alu.dst.write = 1;
1843 r = r600_bc_add_alu(ctx->bc, &alu);
1844 if (r)
1845 return r;
1846 }
1847 src_gpr = ctx->temp_reg;
1848 }
1849
1850 opcode = ctx->inst_info->r600_opcode;
1851 if (opcode == SQ_TEX_INST_SAMPLE &&
1852 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1853 opcode = SQ_TEX_INST_SAMPLE_C;
1854
1855 memset(&tex, 0, sizeof(struct r600_bc_tex));
1856 tex.inst = opcode;
1857 tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1858 tex.sampler_id = tex.resource_id;
1859 tex.src_gpr = src_gpr;
1860 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1861 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1862 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1863 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1864 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1865 tex.src_sel_x = 0;
1866 tex.src_sel_y = 1;
1867 tex.src_sel_z = 2;
1868 tex.src_sel_w = 3;
1869
1870 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1871 tex.src_sel_x = 1;
1872 tex.src_sel_y = 0;
1873 tex.src_sel_z = 3;
1874 tex.src_sel_w = 1;
1875 }
1876
1877 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1878 tex.coord_type_x = 1;
1879 tex.coord_type_y = 1;
1880 tex.coord_type_z = 1;
1881 tex.coord_type_w = 1;
1882 }
1883
1884 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1885 tex.src_sel_w = 2;
1886
1887 r = r600_bc_add_tex(ctx->bc, &tex);
1888 if (r)
1889 return r;
1890
1891 /* add shadow ambient support - gallium doesn't do it yet */
1892 return 0;
1893
1894 }
1895
1896 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1897 {
1898 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1899 struct r600_bc_alu_src r600_src[3];
1900 struct r600_bc_alu alu;
1901 unsigned i;
1902 int r;
1903
1904 r = tgsi_split_constant(ctx, r600_src);
1905 if (r)
1906 return r;
1907 r = tgsi_split_literal_constant(ctx, r600_src);
1908 if (r)
1909 return r;
1910 /* 1 - src0 */
1911 for (i = 0; i < 4; i++) {
1912 memset(&alu, 0, sizeof(struct r600_bc_alu));
1913 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1914 alu.src[0].sel = V_SQ_ALU_SRC_1;
1915 alu.src[0].chan = 0;
1916 alu.src[1] = r600_src[0];
1917 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1918 alu.src[1].neg = 1;
1919 alu.dst.sel = ctx->temp_reg;
1920 alu.dst.chan = i;
1921 if (i == 3) {
1922 alu.last = 1;
1923 }
1924 alu.dst.write = 1;
1925 r = r600_bc_add_alu(ctx->bc, &alu);
1926 if (r)
1927 return r;
1928 }
1929 r = r600_bc_add_literal(ctx->bc, ctx->value);
1930 if (r)
1931 return r;
1932
1933 /* (1 - src0) * src2 */
1934 for (i = 0; i < 4; i++) {
1935 memset(&alu, 0, sizeof(struct r600_bc_alu));
1936 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1937 alu.src[0].sel = ctx->temp_reg;
1938 alu.src[0].chan = i;
1939 alu.src[1] = r600_src[2];
1940 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1941 alu.dst.sel = ctx->temp_reg;
1942 alu.dst.chan = i;
1943 if (i == 3) {
1944 alu.last = 1;
1945 }
1946 alu.dst.write = 1;
1947 r = r600_bc_add_alu(ctx->bc, &alu);
1948 if (r)
1949 return r;
1950 }
1951 r = r600_bc_add_literal(ctx->bc, ctx->value);
1952 if (r)
1953 return r;
1954
1955 /* src0 * src1 + (1 - src0) * src2 */
1956 for (i = 0; i < 4; i++) {
1957 memset(&alu, 0, sizeof(struct r600_bc_alu));
1958 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1959 alu.is_op3 = 1;
1960 alu.src[0] = r600_src[0];
1961 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1962 alu.src[1] = r600_src[1];
1963 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1964 alu.src[2].sel = ctx->temp_reg;
1965 alu.src[2].chan = i;
1966 alu.dst.sel = ctx->temp_reg;
1967 alu.dst.chan = i;
1968 if (i == 3) {
1969 alu.last = 1;
1970 }
1971 r = r600_bc_add_alu(ctx->bc, &alu);
1972 if (r)
1973 return r;
1974 }
1975 return tgsi_helper_copy(ctx, inst);
1976 }
1977
1978 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1979 {
1980 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1981 struct r600_bc_alu_src r600_src[3];
1982 struct r600_bc_alu alu;
1983 int use_temp = 0;
1984 int i, r;
1985
1986 r = tgsi_split_constant(ctx, r600_src);
1987 if (r)
1988 return r;
1989 r = tgsi_split_literal_constant(ctx, r600_src);
1990 if (r)
1991 return r;
1992
1993 if (inst->Dst[0].Register.WriteMask != 0xf)
1994 use_temp = 1;
1995
1996 for (i = 0; i < 4; i++) {
1997 memset(&alu, 0, sizeof(struct r600_bc_alu));
1998 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1999 alu.src[0] = r600_src[0];
2000 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2001
2002 alu.src[1] = r600_src[2];
2003 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2004
2005 alu.src[2] = r600_src[1];
2006 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2007
2008 if (use_temp)
2009 alu.dst.sel = ctx->temp_reg;
2010 else {
2011 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2012 if (r)
2013 return r;
2014 }
2015 alu.dst.chan = i;
2016 alu.dst.write = 1;
2017 alu.is_op3 = 1;
2018 if (i == 3)
2019 alu.last = 1;
2020 r = r600_bc_add_alu(ctx->bc, &alu);
2021 if (r)
2022 return r;
2023 }
2024 if (use_temp)
2025 return tgsi_helper_copy(ctx, inst);
2026 return 0;
2027 }
2028
2029 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2030 {
2031 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2032 struct r600_bc_alu_src r600_src[3];
2033 struct r600_bc_alu alu;
2034 uint32_t use_temp = 0;
2035 int i, r;
2036
2037 if (inst->Dst[0].Register.WriteMask != 0xf)
2038 use_temp = 1;
2039
2040 r = tgsi_split_constant(ctx, r600_src);
2041 if (r)
2042 return r;
2043 r = tgsi_split_literal_constant(ctx, r600_src);
2044 if (r)
2045 return r;
2046
2047 for (i = 0; i < 4; i++) {
2048 memset(&alu, 0, sizeof(struct r600_bc_alu));
2049 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2050
2051 alu.src[0] = r600_src[0];
2052 switch (i) {
2053 case 0:
2054 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2055 break;
2056 case 1:
2057 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2058 break;
2059 case 2:
2060 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2061 break;
2062 case 3:
2063 alu.src[0].sel = V_SQ_ALU_SRC_0;
2064 alu.src[0].chan = i;
2065 }
2066
2067 alu.src[1] = r600_src[1];
2068 switch (i) {
2069 case 0:
2070 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2071 break;
2072 case 1:
2073 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2074 break;
2075 case 2:
2076 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2077 break;
2078 case 3:
2079 alu.src[1].sel = V_SQ_ALU_SRC_0;
2080 alu.src[1].chan = i;
2081 }
2082
2083 alu.dst.sel = ctx->temp_reg;
2084 alu.dst.chan = i;
2085 alu.dst.write = 1;
2086
2087 if (i == 3)
2088 alu.last = 1;
2089 r = r600_bc_add_alu(ctx->bc, &alu);
2090 if (r)
2091 return r;
2092
2093 r = r600_bc_add_literal(ctx->bc, ctx->value);
2094 if (r)
2095 return r;
2096 }
2097
2098 for (i = 0; i < 4; i++) {
2099 memset(&alu, 0, sizeof(struct r600_bc_alu));
2100 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2101
2102 alu.src[0] = r600_src[0];
2103 switch (i) {
2104 case 0:
2105 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2106 break;
2107 case 1:
2108 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2109 break;
2110 case 2:
2111 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2112 break;
2113 case 3:
2114 alu.src[0].sel = V_SQ_ALU_SRC_0;
2115 alu.src[0].chan = i;
2116 }
2117
2118 alu.src[1] = r600_src[1];
2119 switch (i) {
2120 case 0:
2121 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2122 break;
2123 case 1:
2124 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2125 break;
2126 case 2:
2127 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2128 break;
2129 case 3:
2130 alu.src[1].sel = V_SQ_ALU_SRC_0;
2131 alu.src[1].chan = i;
2132 }
2133
2134 alu.src[2].sel = ctx->temp_reg;
2135 alu.src[2].neg = 1;
2136 alu.src[2].chan = i;
2137
2138 if (use_temp)
2139 alu.dst.sel = ctx->temp_reg;
2140 else {
2141 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2142 if (r)
2143 return r;
2144 }
2145 alu.dst.chan = i;
2146 alu.dst.write = 1;
2147 alu.is_op3 = 1;
2148 if (i == 3)
2149 alu.last = 1;
2150 r = r600_bc_add_alu(ctx->bc, &alu);
2151 if (r)
2152 return r;
2153
2154 r = r600_bc_add_literal(ctx->bc, ctx->value);
2155 if (r)
2156 return r;
2157 }
2158 if (use_temp)
2159 return tgsi_helper_copy(ctx, inst);
2160 return 0;
2161 }
2162
2163 static int tgsi_exp(struct r600_shader_ctx *ctx)
2164 {
2165 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2166 struct r600_bc_alu_src r600_src[3];
2167 struct r600_bc_alu alu;
2168 int r;
2169
2170 /* result.x = 2^floor(src); */
2171 if (inst->Dst[0].Register.WriteMask & 1) {
2172 memset(&alu, 0, sizeof(struct r600_bc_alu));
2173
2174 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2175 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2176 if (r)
2177 return r;
2178
2179 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2180
2181 alu.dst.sel = ctx->temp_reg;
2182 alu.dst.chan = 0;
2183 alu.dst.write = 1;
2184 alu.last = 1;
2185 r = r600_bc_add_alu(ctx->bc, &alu);
2186 if (r)
2187 return r;
2188
2189 r = r600_bc_add_literal(ctx->bc, ctx->value);
2190 if (r)
2191 return r;
2192
2193 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2194 alu.src[0].sel = ctx->temp_reg;
2195 alu.src[0].chan = 0;
2196
2197 alu.dst.sel = ctx->temp_reg;
2198 alu.dst.chan = 0;
2199 alu.dst.write = 1;
2200 alu.last = 1;
2201 r = r600_bc_add_alu(ctx->bc, &alu);
2202 if (r)
2203 return r;
2204
2205 r = r600_bc_add_literal(ctx->bc, ctx->value);
2206 if (r)
2207 return r;
2208 }
2209
2210 /* result.y = tmp - floor(tmp); */
2211 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2212 memset(&alu, 0, sizeof(struct r600_bc_alu));
2213
2214 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2215 alu.src[0] = r600_src[0];
2216 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2217 if (r)
2218 return r;
2219 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2220
2221 alu.dst.sel = ctx->temp_reg;
2222 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2223 // if (r)
2224 // return r;
2225 alu.dst.write = 1;
2226 alu.dst.chan = 1;
2227
2228 alu.last = 1;
2229
2230 r = r600_bc_add_alu(ctx->bc, &alu);
2231 if (r)
2232 return r;
2233 r = r600_bc_add_literal(ctx->bc, ctx->value);
2234 if (r)
2235 return r;
2236 }
2237
2238 /* result.z = RoughApprox2ToX(tmp);*/
2239 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2240 memset(&alu, 0, sizeof(struct r600_bc_alu));
2241 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2242 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2243 if (r)
2244 return r;
2245 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2246
2247 alu.dst.sel = ctx->temp_reg;
2248 alu.dst.write = 1;
2249 alu.dst.chan = 2;
2250
2251 alu.last = 1;
2252
2253 r = r600_bc_add_alu(ctx->bc, &alu);
2254 if (r)
2255 return r;
2256 r = r600_bc_add_literal(ctx->bc, ctx->value);
2257 if (r)
2258 return r;
2259 }
2260
2261 /* result.w = 1.0;*/
2262 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2263 memset(&alu, 0, sizeof(struct r600_bc_alu));
2264
2265 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2266 alu.src[0].sel = V_SQ_ALU_SRC_1;
2267 alu.src[0].chan = 0;
2268
2269 alu.dst.sel = ctx->temp_reg;
2270 alu.dst.chan = 3;
2271 alu.dst.write = 1;
2272 alu.last = 1;
2273 r = r600_bc_add_alu(ctx->bc, &alu);
2274 if (r)
2275 return r;
2276 r = r600_bc_add_literal(ctx->bc, ctx->value);
2277 if (r)
2278 return r;
2279 }
2280 return tgsi_helper_copy(ctx, inst);
2281 }
2282
2283 static int tgsi_log(struct r600_shader_ctx *ctx)
2284 {
2285 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2286 struct r600_bc_alu alu;
2287 int r;
2288
2289 /* result.x = floor(log2(src)); */
2290 if (inst->Dst[0].Register.WriteMask & 1) {
2291 memset(&alu, 0, sizeof(struct r600_bc_alu));
2292
2293 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2294 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2295 if (r)
2296 return r;
2297
2298 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2299
2300 alu.dst.sel = ctx->temp_reg;
2301 alu.dst.chan = 0;
2302 alu.dst.write = 1;
2303 alu.last = 1;
2304 r = r600_bc_add_alu(ctx->bc, &alu);
2305 if (r)
2306 return r;
2307
2308 r = r600_bc_add_literal(ctx->bc, ctx->value);
2309 if (r)
2310 return r;
2311
2312 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2313 alu.src[0].sel = ctx->temp_reg;
2314 alu.src[0].chan = 0;
2315
2316 alu.dst.sel = ctx->temp_reg;
2317 alu.dst.chan = 0;
2318 alu.dst.write = 1;
2319 alu.last = 1;
2320
2321 r = r600_bc_add_alu(ctx->bc, &alu);
2322 if (r)
2323 return r;
2324
2325 r = r600_bc_add_literal(ctx->bc, ctx->value);
2326 if (r)
2327 return r;
2328 }
2329
2330 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2331 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2332 memset(&alu, 0, sizeof(struct r600_bc_alu));
2333
2334 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2335 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2336 if (r)
2337 return r;
2338
2339 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2340
2341 alu.dst.sel = ctx->temp_reg;
2342 alu.dst.chan = 1;
2343 alu.dst.write = 1;
2344 alu.last = 1;
2345
2346 r = r600_bc_add_alu(ctx->bc, &alu);
2347 if (r)
2348 return r;
2349
2350 r = r600_bc_add_literal(ctx->bc, ctx->value);
2351 if (r)
2352 return r;
2353
2354 memset(&alu, 0, sizeof(struct r600_bc_alu));
2355
2356 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2357 alu.src[0].sel = ctx->temp_reg;
2358 alu.src[0].chan = 1;
2359
2360 alu.dst.sel = ctx->temp_reg;
2361 alu.dst.chan = 1;
2362 alu.dst.write = 1;
2363 alu.last = 1;
2364
2365 r = r600_bc_add_alu(ctx->bc, &alu);
2366 if (r)
2367 return r;
2368
2369 r = r600_bc_add_literal(ctx->bc, ctx->value);
2370 if (r)
2371 return r;
2372
2373 memset(&alu, 0, sizeof(struct r600_bc_alu));
2374
2375 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2376 alu.src[0].sel = ctx->temp_reg;
2377 alu.src[0].chan = 1;
2378
2379 alu.dst.sel = ctx->temp_reg;
2380 alu.dst.chan = 1;
2381 alu.dst.write = 1;
2382 alu.last = 1;
2383
2384 r = r600_bc_add_alu(ctx->bc, &alu);
2385 if (r)
2386 return r;
2387
2388 r = r600_bc_add_literal(ctx->bc, ctx->value);
2389 if (r)
2390 return r;
2391
2392 memset(&alu, 0, sizeof(struct r600_bc_alu));
2393
2394 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2395 alu.src[0].sel = ctx->temp_reg;
2396 alu.src[0].chan = 1;
2397
2398 alu.dst.sel = ctx->temp_reg;
2399 alu.dst.chan = 1;
2400 alu.dst.write = 1;
2401 alu.last = 1;
2402
2403 r = r600_bc_add_alu(ctx->bc, &alu);
2404 if (r)
2405 return r;
2406
2407 r = r600_bc_add_literal(ctx->bc, ctx->value);
2408 if (r)
2409 return r;
2410
2411 memset(&alu, 0, sizeof(struct r600_bc_alu));
2412
2413 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2414
2415 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2416 if (r)
2417 return r;
2418
2419 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2420
2421 alu.src[1].sel = ctx->temp_reg;
2422 alu.src[1].chan = 1;
2423
2424 alu.dst.sel = ctx->temp_reg;
2425 alu.dst.chan = 1;
2426 alu.dst.write = 1;
2427 alu.last = 1;
2428
2429 r = r600_bc_add_alu(ctx->bc, &alu);
2430 if (r)
2431 return r;
2432
2433 r = r600_bc_add_literal(ctx->bc, ctx->value);
2434 if (r)
2435 return r;
2436 }
2437
2438 /* result.z = log2(src);*/
2439 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2440 memset(&alu, 0, sizeof(struct r600_bc_alu));
2441
2442 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2443 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2444 if (r)
2445 return r;
2446
2447 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2448
2449 alu.dst.sel = ctx->temp_reg;
2450 alu.dst.write = 1;
2451 alu.dst.chan = 2;
2452 alu.last = 1;
2453
2454 r = r600_bc_add_alu(ctx->bc, &alu);
2455 if (r)
2456 return r;
2457
2458 r = r600_bc_add_literal(ctx->bc, ctx->value);
2459 if (r)
2460 return r;
2461 }
2462
2463 /* result.w = 1.0; */
2464 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2465 memset(&alu, 0, sizeof(struct r600_bc_alu));
2466
2467 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2468 alu.src[0].sel = V_SQ_ALU_SRC_1;
2469 alu.src[0].chan = 0;
2470
2471 alu.dst.sel = ctx->temp_reg;
2472 alu.dst.chan = 3;
2473 alu.dst.write = 1;
2474 alu.last = 1;
2475
2476 r = r600_bc_add_alu(ctx->bc, &alu);
2477 if (r)
2478 return r;
2479
2480 r = r600_bc_add_literal(ctx->bc, ctx->value);
2481 if (r)
2482 return r;
2483 }
2484
2485 return tgsi_helper_copy(ctx, inst);
2486 }
2487
2488 /* r6/7 only for now */
2489 static int tgsi_arl(struct r600_shader_ctx *ctx)
2490 {
2491 /* TODO from r600c, ar values don't persist between clauses */
2492 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2493 struct r600_bc_alu alu;
2494 int r;
2495 memset(&alu, 0, sizeof(struct r600_bc_alu));
2496
2497 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2498
2499 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2500 if (r)
2501 return r;
2502 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2503
2504 alu.last = 1;
2505
2506 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2507 if (r)
2508 return r;
2509 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2510 return 0;
2511 }
2512
2513 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2514 {
2515 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2516 struct r600_bc_alu alu;
2517 int i, r = 0;
2518
2519 for (i = 0; i < 4; i++) {
2520 memset(&alu, 0, sizeof(struct r600_bc_alu));
2521
2522 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2523 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2524 if (r)
2525 return r;
2526
2527 if (i == 0 || i == 3) {
2528 alu.src[0].sel = V_SQ_ALU_SRC_1;
2529 } else {
2530 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2531 if (r)
2532 return r;
2533 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2534 }
2535
2536 if (i == 0 || i == 2) {
2537 alu.src[1].sel = V_SQ_ALU_SRC_1;
2538 } else {
2539 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2540 if (r)
2541 return r;
2542 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2543 }
2544 if (i == 3)
2545 alu.last = 1;
2546 r = r600_bc_add_alu(ctx->bc, &alu);
2547 if (r)
2548 return r;
2549 }
2550 return 0;
2551 }
2552
2553 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2554 {
2555 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2556 struct r600_bc_alu alu;
2557 int r;
2558
2559 memset(&alu, 0, sizeof(struct r600_bc_alu));
2560 alu.inst = opcode;
2561 alu.predicate = 1;
2562
2563 alu.dst.sel = ctx->temp_reg;
2564 alu.dst.write = 1;
2565 alu.dst.chan = 0;
2566
2567 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2568 if (r)
2569 return r;
2570 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2571 alu.src[1].sel = V_SQ_ALU_SRC_0;
2572 alu.src[1].chan = 0;
2573
2574 alu.last = 1;
2575
2576 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2577 if (r)
2578 return r;
2579 return 0;
2580 }
2581
2582 static int pops(struct r600_shader_ctx *ctx, int pops)
2583 {
2584 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2585 ctx->bc->cf_last->pop_count = pops;
2586 return 0;
2587 }
2588
2589 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2590 {
2591 switch(reason) {
2592 case FC_PUSH_VPM:
2593 ctx->bc->callstack[ctx->bc->call_sp].current--;
2594 break;
2595 case FC_PUSH_WQM:
2596 case FC_LOOP:
2597 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2598 break;
2599 case FC_REP:
2600 /* TOODO : for 16 vp asic should -= 2; */
2601 ctx->bc->callstack[ctx->bc->call_sp].current --;
2602 break;
2603 }
2604 }
2605
2606 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2607 {
2608 if (check_max_only) {
2609 int diff;
2610 switch (reason) {
2611 case FC_PUSH_VPM:
2612 diff = 1;
2613 break;
2614 case FC_PUSH_WQM:
2615 diff = 4;
2616 break;
2617 default:
2618 assert(0);
2619 diff = 0;
2620 }
2621 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2622 ctx->bc->callstack[ctx->bc->call_sp].max) {
2623 ctx->bc->callstack[ctx->bc->call_sp].max =
2624 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2625 }
2626 return;
2627 }
2628 switch (reason) {
2629 case FC_PUSH_VPM:
2630 ctx->bc->callstack[ctx->bc->call_sp].current++;
2631 break;
2632 case FC_PUSH_WQM:
2633 case FC_LOOP:
2634 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2635 break;
2636 case FC_REP:
2637 ctx->bc->callstack[ctx->bc->call_sp].current++;
2638 break;
2639 }
2640
2641 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2642 ctx->bc->callstack[ctx->bc->call_sp].max) {
2643 ctx->bc->callstack[ctx->bc->call_sp].max =
2644 ctx->bc->callstack[ctx->bc->call_sp].current;
2645 }
2646 }
2647
2648 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2649 {
2650 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2651
2652 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2653 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2654 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2655 sp->num_mid++;
2656 }
2657
2658 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2659 {
2660 ctx->bc->fc_sp++;
2661 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2662 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2663 }
2664
2665 static void fc_poplevel(struct r600_shader_ctx *ctx)
2666 {
2667 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2668 if (sp->mid) {
2669 free(sp->mid);
2670 sp->mid = NULL;
2671 }
2672 sp->num_mid = 0;
2673 sp->start = NULL;
2674 sp->type = 0;
2675 ctx->bc->fc_sp--;
2676 }
2677
2678 #if 0
2679 static int emit_return(struct r600_shader_ctx *ctx)
2680 {
2681 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2682 return 0;
2683 }
2684
2685 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2686 {
2687
2688 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2689 ctx->bc->cf_last->pop_count = pops;
2690 /* TODO work out offset */
2691 return 0;
2692 }
2693
2694 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2695 {
2696 return 0;
2697 }
2698
2699 static void emit_testflag(struct r600_shader_ctx *ctx)
2700 {
2701
2702 }
2703
2704 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2705 {
2706 emit_testflag(ctx);
2707 emit_jump_to_offset(ctx, 1, 4);
2708 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2709 pops(ctx, ifidx + 1);
2710 emit_return(ctx);
2711 }
2712
2713 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2714 {
2715 emit_testflag(ctx);
2716
2717 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2718 ctx->bc->cf_last->pop_count = 1;
2719
2720 fc_set_mid(ctx, fc_sp);
2721
2722 pops(ctx, 1);
2723 }
2724 #endif
2725
2726 static int tgsi_if(struct r600_shader_ctx *ctx)
2727 {
2728 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2729
2730 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2731
2732 fc_pushlevel(ctx, FC_IF);
2733
2734 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2735 return 0;
2736 }
2737
2738 static int tgsi_else(struct r600_shader_ctx *ctx)
2739 {
2740 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2741 ctx->bc->cf_last->pop_count = 1;
2742
2743 fc_set_mid(ctx, ctx->bc->fc_sp);
2744 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2745 return 0;
2746 }
2747
2748 static int tgsi_endif(struct r600_shader_ctx *ctx)
2749 {
2750 pops(ctx, 1);
2751 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2752 R600_ERR("if/endif unbalanced in shader\n");
2753 return -1;
2754 }
2755
2756 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2757 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2758 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2759 } else {
2760 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2761 }
2762 fc_poplevel(ctx);
2763
2764 callstack_decrease_current(ctx, FC_PUSH_VPM);
2765 return 0;
2766 }
2767
2768 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2769 {
2770 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2771
2772 fc_pushlevel(ctx, FC_LOOP);
2773
2774 /* check stack depth */
2775 callstack_check_depth(ctx, FC_LOOP, 0);
2776 return 0;
2777 }
2778
2779 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2780 {
2781 int i;
2782
2783 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2784
2785 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2786 R600_ERR("loop/endloop in shader code are not paired.\n");
2787 return -EINVAL;
2788 }
2789
2790 /* fixup loop pointers - from r600isa
2791 LOOP END points to CF after LOOP START,
2792 LOOP START point to CF after LOOP END
2793 BRK/CONT point to LOOP END CF
2794 */
2795 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2796
2797 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2798
2799 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2800 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2801 }
2802 /* TODO add LOOPRET support */
2803 fc_poplevel(ctx);
2804 callstack_decrease_current(ctx, FC_LOOP);
2805 return 0;
2806 }
2807
2808 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2809 {
2810 unsigned int fscp;
2811
2812 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2813 {
2814 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2815 break;
2816 }
2817
2818 if (fscp == 0) {
2819 R600_ERR("Break not inside loop/endloop pair\n");
2820 return -EINVAL;
2821 }
2822
2823 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2824 ctx->bc->cf_last->pop_count = 1;
2825
2826 fc_set_mid(ctx, fscp);
2827
2828 pops(ctx, 1);
2829 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2830 return 0;
2831 }
2832
2833 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2834 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
2835 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2836 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2837
2838 /* FIXME:
2839 * For state trackers other than OpenGL, we'll want to use
2840 * _RECIP_IEEE instead.
2841 */
2842 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2843
2844 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2845 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2846 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2847 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2848 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2849 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2850 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2851 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2852 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2853 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2854 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2855 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2856 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2857 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2858 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2859 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2860 /* gap */
2861 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2862 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2863 /* gap */
2864 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2865 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2866 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2867 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2868 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2869 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2870 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2871 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2872 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2873 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2874 /* gap */
2875 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2876 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2877 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2878 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2879 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2880 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2881 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2882 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2883 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2884 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2885 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2886 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2889 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2891 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2892 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2893 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2894 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2895 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2896 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2898 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2900 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2901 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2902 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2909 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2910 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2911 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2912 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2915 {TGSI_OPCODE_TXL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2917 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2918 /* gap */
2919 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2920 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2922 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2923 /* gap */
2924 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2932 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 /* gap */
2934 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2943 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2944 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2945 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2946 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2947 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2948 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 /* gap */
2950 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2952 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2953 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 /* gap */
2956 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2961 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2963 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2965 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2966 /* gap */
2967 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2975 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2977 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2979 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2985 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2995 };
2996
2997 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2998 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3000 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3001 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3002 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3003 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3004 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3006 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3007 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3008 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3009 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3010 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3011 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3012 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3013 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3014 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3015 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3016 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3017 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 /* gap */
3019 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 /* gap */
3022 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3025 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3026 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3027 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3028 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3029 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3030 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3031 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3032 /* gap */
3033 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3035 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3036 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3037 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3038 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3039 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3040 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3041 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3042 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3043 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3047 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3049 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3050 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3051 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3052 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3054 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3056 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3060 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3067 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3068 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3069 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3070 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3073 {TGSI_OPCODE_TXL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3075 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3076 /* gap */
3077 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3078 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3080 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3081 /* gap */
3082 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3090 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 /* gap */
3092 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3101 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3102 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3103 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3104 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3105 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3106 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 /* gap */
3108 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3109 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3110 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3111 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3113 /* gap */
3114 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3119 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3121 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3123 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3124 /* gap */
3125 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3130 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3133 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3135 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3137 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3143 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3152 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3153 };