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[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_formats.h"
25 #include "r600_opcodes.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include "pipe/p_shader_tokens.h"
32 #include "tgsi/tgsi_info.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_scan.h"
35 #include "tgsi/tgsi_dump.h"
36 #include "util/u_bitcast.h"
37 #include "util/u_memory.h"
38 #include "util/u_math.h"
39 #include <stdio.h>
40 #include <errno.h>
41
42 /* CAYMAN notes
43 Why CAYMAN got loops for lots of instructions is explained here.
44
45 -These 8xx t-slot only ops are implemented in all vector slots.
46 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
47 These 8xx t-slot only opcodes become vector ops, with all four
48 slots expecting the arguments on sources a and b. Result is
49 broadcast to all channels.
50 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
52 x slots.
53 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
54 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
55 SQRT_IEEE/_64
56 SIN/COS
57 The w slot may have an independent co-issued operation, or if the
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
60 The compiler must issue the source argument to slots z, y, and x
61 */
62
63 /* Contents of r0 on entry to various shaders
64
65 VS - .x = VertexID
66 .y = RelVertexID (??)
67 .w = InstanceID
68
69 GS - r0.xyw, r1.xyz = per-vertex offsets
70 r0.z = PrimitiveID
71
72 TCS - .x = PatchID
73 .y = RelPatchID (??)
74 .z = InvocationID
75 .w = tess factor base.
76
77 TES - .x = TessCoord.x
78 - .y = TessCoord.y
79 - .z = RelPatchID (??)
80 - .w = PrimitiveID
81
82 PS - face_gpr.z = SampleMask
83 face_gpr.w = SampleID
84 */
85 #define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
86 static int r600_shader_from_tgsi(struct r600_context *rctx,
87 struct r600_pipe_shader *pipeshader,
88 union r600_shader_key key);
89
90 static void r600_add_gpr_array(struct r600_shader *ps, int start_gpr,
91 int size, unsigned comp_mask) {
92
93 if (!size)
94 return;
95
96 if (ps->num_arrays == ps->max_arrays) {
97 ps->max_arrays += 64;
98 ps->arrays = realloc(ps->arrays, ps->max_arrays *
99 sizeof(struct r600_shader_array));
100 }
101
102 int n = ps->num_arrays;
103 ++ps->num_arrays;
104
105 ps->arrays[n].comp_mask = comp_mask;
106 ps->arrays[n].gpr_start = start_gpr;
107 ps->arrays[n].gpr_count = size;
108 }
109
110 static void r600_dump_streamout(struct pipe_stream_output_info *so)
111 {
112 unsigned i;
113
114 fprintf(stderr, "STREAMOUT\n");
115 for (i = 0; i < so->num_outputs; i++) {
116 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
117 so->output[i].start_component;
118 fprintf(stderr, " %i: MEM_STREAM%d_BUF%i[%i..%i] <- OUT[%i].%s%s%s%s%s\n",
119 i,
120 so->output[i].stream,
121 so->output[i].output_buffer,
122 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
123 so->output[i].register_index,
124 mask & 1 ? "x" : "",
125 mask & 2 ? "y" : "",
126 mask & 4 ? "z" : "",
127 mask & 8 ? "w" : "",
128 so->output[i].dst_offset < so->output[i].start_component ? " (will lower)" : "");
129 }
130 }
131
132 static int store_shader(struct pipe_context *ctx,
133 struct r600_pipe_shader *shader)
134 {
135 struct r600_context *rctx = (struct r600_context *)ctx;
136 uint32_t *ptr, i;
137
138 if (shader->bo == NULL) {
139 shader->bo = (struct r600_resource*)
140 pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
141 if (shader->bo == NULL) {
142 return -ENOMEM;
143 }
144 ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo, PIPE_TRANSFER_WRITE);
145 if (R600_BIG_ENDIAN) {
146 for (i = 0; i < shader->shader.bc.ndw; ++i) {
147 ptr[i] = util_cpu_to_le32(shader->shader.bc.bytecode[i]);
148 }
149 } else {
150 memcpy(ptr, shader->shader.bc.bytecode, shader->shader.bc.ndw * sizeof(*ptr));
151 }
152 rctx->b.ws->buffer_unmap(shader->bo->buf);
153 }
154
155 return 0;
156 }
157
158 int r600_pipe_shader_create(struct pipe_context *ctx,
159 struct r600_pipe_shader *shader,
160 union r600_shader_key key)
161 {
162 struct r600_context *rctx = (struct r600_context *)ctx;
163 struct r600_pipe_shader_selector *sel = shader->selector;
164 int r;
165 bool dump = r600_can_dump_shader(&rctx->screen->b,
166 tgsi_get_processor_type(sel->tokens));
167 unsigned use_sb = !(rctx->screen->b.debug_flags & DBG_NO_SB);
168 unsigned sb_disasm = use_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
169 unsigned export_shader;
170
171 shader->shader.bc.isa = rctx->isa;
172
173 if (dump) {
174 fprintf(stderr, "--------------------------------------------------------------\n");
175 tgsi_dump(sel->tokens, 0);
176
177 if (sel->so.num_outputs) {
178 r600_dump_streamout(&sel->so);
179 }
180 }
181 r = r600_shader_from_tgsi(rctx, shader, key);
182 if (r) {
183 R600_ERR("translation from TGSI failed !\n");
184 goto error;
185 }
186 if (shader->shader.processor_type == PIPE_SHADER_VERTEX) {
187 /* only disable for vertex shaders in tess paths */
188 if (key.vs.as_ls)
189 use_sb = 0;
190 }
191 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
192 use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
193 use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
194
195 /* disable SB for shaders using doubles */
196 use_sb &= !shader->shader.uses_doubles;
197
198 use_sb &= !shader->shader.uses_atomics;
199 use_sb &= !shader->shader.uses_images;
200
201 /* Check if the bytecode has already been built. */
202 if (!shader->shader.bc.bytecode) {
203 r = r600_bytecode_build(&shader->shader.bc);
204 if (r) {
205 R600_ERR("building bytecode failed !\n");
206 goto error;
207 }
208 }
209
210 if (dump && !sb_disasm) {
211 fprintf(stderr, "--------------------------------------------------------------\n");
212 r600_bytecode_disasm(&shader->shader.bc);
213 fprintf(stderr, "______________________________________________________________\n");
214 } else if ((dump && sb_disasm) || use_sb) {
215 r = r600_sb_bytecode_process(rctx, &shader->shader.bc, &shader->shader,
216 dump, use_sb);
217 if (r) {
218 R600_ERR("r600_sb_bytecode_process failed !\n");
219 goto error;
220 }
221 }
222
223 if (shader->gs_copy_shader) {
224 if (dump) {
225 // dump copy shader
226 r = r600_sb_bytecode_process(rctx, &shader->gs_copy_shader->shader.bc,
227 &shader->gs_copy_shader->shader, dump, 0);
228 if (r)
229 goto error;
230 }
231
232 if ((r = store_shader(ctx, shader->gs_copy_shader)))
233 goto error;
234 }
235
236 /* Store the shader in a buffer. */
237 if ((r = store_shader(ctx, shader)))
238 goto error;
239
240 /* Build state. */
241 switch (shader->shader.processor_type) {
242 case PIPE_SHADER_TESS_CTRL:
243 evergreen_update_hs_state(ctx, shader);
244 break;
245 case PIPE_SHADER_TESS_EVAL:
246 if (key.tes.as_es)
247 evergreen_update_es_state(ctx, shader);
248 else
249 evergreen_update_vs_state(ctx, shader);
250 break;
251 case PIPE_SHADER_GEOMETRY:
252 if (rctx->b.chip_class >= EVERGREEN) {
253 evergreen_update_gs_state(ctx, shader);
254 evergreen_update_vs_state(ctx, shader->gs_copy_shader);
255 } else {
256 r600_update_gs_state(ctx, shader);
257 r600_update_vs_state(ctx, shader->gs_copy_shader);
258 }
259 break;
260 case PIPE_SHADER_VERTEX:
261 export_shader = key.vs.as_es;
262 if (rctx->b.chip_class >= EVERGREEN) {
263 if (key.vs.as_ls)
264 evergreen_update_ls_state(ctx, shader);
265 else if (key.vs.as_es)
266 evergreen_update_es_state(ctx, shader);
267 else
268 evergreen_update_vs_state(ctx, shader);
269 } else {
270 if (export_shader)
271 r600_update_es_state(ctx, shader);
272 else
273 r600_update_vs_state(ctx, shader);
274 }
275 break;
276 case PIPE_SHADER_FRAGMENT:
277 if (rctx->b.chip_class >= EVERGREEN) {
278 evergreen_update_ps_state(ctx, shader);
279 } else {
280 r600_update_ps_state(ctx, shader);
281 }
282 break;
283 case PIPE_SHADER_COMPUTE:
284 evergreen_update_ls_state(ctx, shader);
285 break;
286 default:
287 r = -EINVAL;
288 goto error;
289 }
290 return 0;
291
292 error:
293 r600_pipe_shader_destroy(ctx, shader);
294 return r;
295 }
296
297 void r600_pipe_shader_destroy(struct pipe_context *ctx UNUSED, struct r600_pipe_shader *shader)
298 {
299 r600_resource_reference(&shader->bo, NULL);
300 r600_bytecode_clear(&shader->shader.bc);
301 r600_release_command_buffer(&shader->command_buffer);
302 }
303
304 /*
305 * tgsi -> r600 shader
306 */
307 struct r600_shader_tgsi_instruction;
308
309 struct r600_shader_src {
310 unsigned sel;
311 unsigned swizzle[4];
312 unsigned neg;
313 unsigned abs;
314 unsigned rel;
315 unsigned kc_bank;
316 boolean kc_rel; /* true if cache bank is indexed */
317 uint32_t value[4];
318 };
319
320 struct eg_interp {
321 boolean enabled;
322 unsigned ij_index;
323 };
324
325 struct r600_shader_ctx {
326 struct tgsi_shader_info info;
327 struct tgsi_parse_context parse;
328 const struct tgsi_token *tokens;
329 unsigned type;
330 unsigned file_offset[TGSI_FILE_COUNT];
331 unsigned temp_reg;
332 const struct r600_shader_tgsi_instruction *inst_info;
333 struct r600_bytecode *bc;
334 struct r600_shader *shader;
335 struct r600_shader_src src[4];
336 uint32_t *literals;
337 uint32_t nliterals;
338 uint32_t max_driver_temp_used;
339 /* needed for evergreen interpolation */
340 struct eg_interp eg_interpolators[6]; // indexed by Persp/Linear * 3 + sample/center/centroid
341 /* evergreen/cayman also store sample mask in face register */
342 int face_gpr;
343 /* sample id is .w component stored in fixed point position register */
344 int fixed_pt_position_gpr;
345 int colors_used;
346 boolean clip_vertex_write;
347 unsigned cv_output;
348 unsigned edgeflag_output;
349 int cs_block_size_reg;
350 int cs_grid_size_reg;
351 bool cs_block_size_loaded, cs_grid_size_loaded;
352 int fragcoord_input;
353 int next_ring_offset;
354 int gs_out_ring_offset;
355 int gs_next_vertex;
356 struct r600_shader *gs_for_vs;
357 int gs_export_gpr_tregs[4];
358 int gs_rotated_input[2];
359 const struct pipe_stream_output_info *gs_stream_output_info;
360 unsigned enabled_stream_buffers_mask;
361 unsigned tess_input_info; /* temp with tess input offsets */
362 unsigned tess_output_info; /* temp with tess input offsets */
363 unsigned thread_id_gpr; /* temp with thread id calculated for images */
364 bool thread_id_gpr_loaded;
365 };
366
367 struct r600_shader_tgsi_instruction {
368 unsigned op;
369 int (*process)(struct r600_shader_ctx *ctx);
370 };
371
372 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so, int stream, bool ind);
373 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], cm_shader_tgsi_instruction[];
374 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
375 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
376 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
377 static int tgsi_else(struct r600_shader_ctx *ctx);
378 static int tgsi_endif(struct r600_shader_ctx *ctx);
379 static int tgsi_bgnloop(struct r600_shader_ctx *ctx);
380 static int tgsi_endloop(struct r600_shader_ctx *ctx);
381 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx);
382 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
383 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
384 unsigned int dst_reg);
385 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
386 const struct r600_shader_src *shader_src,
387 unsigned chan);
388 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
389 unsigned dst_reg, unsigned mask);
390
391 static int tgsi_last_instruction(unsigned writemask)
392 {
393 int i, lasti = 0;
394
395 for (i = 0; i < 4; i++) {
396 if (writemask & (1 << i)) {
397 lasti = i;
398 }
399 }
400 return lasti;
401 }
402
403 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
404 {
405 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
406 unsigned j;
407
408 if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) {
409 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
410 return -EINVAL;
411 }
412 #if 0
413 if (i->Instruction.Label) {
414 R600_ERR("label unsupported\n");
415 return -EINVAL;
416 }
417 #endif
418 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
419 if (i->Src[j].Register.Dimension) {
420 switch (i->Src[j].Register.File) {
421 case TGSI_FILE_CONSTANT:
422 case TGSI_FILE_HW_ATOMIC:
423 break;
424 case TGSI_FILE_INPUT:
425 if (ctx->type == PIPE_SHADER_GEOMETRY ||
426 ctx->type == PIPE_SHADER_TESS_CTRL ||
427 ctx->type == PIPE_SHADER_TESS_EVAL)
428 break;
429 case TGSI_FILE_OUTPUT:
430 if (ctx->type == PIPE_SHADER_TESS_CTRL)
431 break;
432 default:
433 R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
434 i->Src[j].Register.File,
435 i->Src[j].Register.Dimension);
436 return -EINVAL;
437 }
438 }
439 }
440 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
441 if (i->Dst[j].Register.Dimension) {
442 if (ctx->type == PIPE_SHADER_TESS_CTRL)
443 continue;
444 R600_ERR("unsupported dst (dimension)\n");
445 return -EINVAL;
446 }
447 }
448 return 0;
449 }
450
451 int eg_get_interpolator_index(unsigned interpolate, unsigned location)
452 {
453 if (interpolate == TGSI_INTERPOLATE_COLOR ||
454 interpolate == TGSI_INTERPOLATE_LINEAR ||
455 interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
456 {
457 int is_linear = interpolate == TGSI_INTERPOLATE_LINEAR;
458 int loc;
459
460 switch(location) {
461 case TGSI_INTERPOLATE_LOC_CENTER:
462 loc = 1;
463 break;
464 case TGSI_INTERPOLATE_LOC_CENTROID:
465 loc = 2;
466 break;
467 case TGSI_INTERPOLATE_LOC_SAMPLE:
468 default:
469 loc = 0; break;
470 }
471
472 return is_linear * 3 + loc;
473 }
474
475 return -1;
476 }
477
478 static void evergreen_interp_assign_ij_index(struct r600_shader_ctx *ctx,
479 int input)
480 {
481 int i = eg_get_interpolator_index(
482 ctx->shader->input[input].interpolate,
483 ctx->shader->input[input].interpolate_location);
484 assert(i >= 0);
485 ctx->shader->input[input].ij_index = ctx->eg_interpolators[i].ij_index;
486 }
487
488 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
489 {
490 int i, r;
491 struct r600_bytecode_alu alu;
492 int gpr = 0, base_chan = 0;
493 int ij_index = ctx->shader->input[input].ij_index;
494
495 /* work out gpr and base_chan from index */
496 gpr = ij_index / 2;
497 base_chan = (2 * (ij_index % 2)) + 1;
498
499 for (i = 0; i < 8; i++) {
500 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
501
502 if (i < 4)
503 alu.op = ALU_OP2_INTERP_ZW;
504 else
505 alu.op = ALU_OP2_INTERP_XY;
506
507 if ((i > 1) && (i < 6)) {
508 alu.dst.sel = ctx->shader->input[input].gpr;
509 alu.dst.write = 1;
510 }
511
512 alu.dst.chan = i % 4;
513
514 alu.src[0].sel = gpr;
515 alu.src[0].chan = (base_chan - (i % 2));
516
517 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
518
519 alu.bank_swizzle_force = SQ_ALU_VEC_210;
520 if ((i % 4) == 3)
521 alu.last = 1;
522 r = r600_bytecode_add_alu(ctx->bc, &alu);
523 if (r)
524 return r;
525 }
526 return 0;
527 }
528
529 static int evergreen_interp_flat(struct r600_shader_ctx *ctx, int input)
530 {
531 int i, r;
532 struct r600_bytecode_alu alu;
533
534 for (i = 0; i < 4; i++) {
535 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
536
537 alu.op = ALU_OP1_INTERP_LOAD_P0;
538
539 alu.dst.sel = ctx->shader->input[input].gpr;
540 alu.dst.write = 1;
541
542 alu.dst.chan = i;
543
544 alu.src[0].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
545 alu.src[0].chan = i;
546
547 if (i == 3)
548 alu.last = 1;
549 r = r600_bytecode_add_alu(ctx->bc, &alu);
550 if (r)
551 return r;
552 }
553 return 0;
554 }
555
556 /*
557 * Special export handling in shaders
558 *
559 * shader export ARRAY_BASE for EXPORT_POS:
560 * 60 is position
561 * 61 is misc vector
562 * 62, 63 are clip distance vectors
563 *
564 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
565 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
566 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
567 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
568 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
569 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
570 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
571 * exclusive from render target index)
572 * VS_OUT_CCDIST0_VEC_ENA/VS_OUT_CCDIST1_VEC_ENA - enable clip distance vectors
573 *
574 *
575 * shader export ARRAY_BASE for EXPORT_PIXEL:
576 * 0-7 CB targets
577 * 61 computed Z vector
578 *
579 * The use of the values exported in the computed Z vector are controlled
580 * by DB_SHADER_CONTROL:
581 * Z_EXPORT_ENABLE - Z as a float in RED
582 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
583 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
584 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
585 * DB_SOURCE_FORMAT - export control restrictions
586 *
587 */
588
589
590 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
591 static int r600_spi_sid(struct r600_shader_io * io)
592 {
593 int index, name = io->name;
594
595 /* These params are handled differently, they don't need
596 * semantic indices, so we'll use 0 for them.
597 */
598 if (name == TGSI_SEMANTIC_POSITION ||
599 name == TGSI_SEMANTIC_PSIZE ||
600 name == TGSI_SEMANTIC_EDGEFLAG ||
601 name == TGSI_SEMANTIC_FACE ||
602 name == TGSI_SEMANTIC_SAMPLEMASK)
603 index = 0;
604 else {
605 if (name == TGSI_SEMANTIC_GENERIC) {
606 /* For generic params simply use sid from tgsi */
607 index = io->sid;
608 } else {
609 /* For non-generic params - pack name and sid into 8 bits */
610 index = 0x80 | (name<<3) | (io->sid);
611 }
612
613 /* Make sure that all really used indices have nonzero value, so
614 * we can just compare it to 0 later instead of comparing the name
615 * with different values to detect special cases. */
616 index++;
617 }
618
619 return index;
620 };
621
622 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
623 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
624 {
625 switch (semantic_name) {
626 case TGSI_SEMANTIC_POSITION:
627 return 0;
628 case TGSI_SEMANTIC_PSIZE:
629 return 1;
630 case TGSI_SEMANTIC_CLIPDIST:
631 assert(index <= 1);
632 return 2 + index;
633 case TGSI_SEMANTIC_GENERIC:
634 if (index <= 63-4)
635 return 4 + index - 9;
636 else
637 /* same explanation as in the default statement,
638 * the only user hitting this is st/nine.
639 */
640 return 0;
641
642 /* patch indices are completely separate and thus start from 0 */
643 case TGSI_SEMANTIC_TESSOUTER:
644 return 0;
645 case TGSI_SEMANTIC_TESSINNER:
646 return 1;
647 case TGSI_SEMANTIC_PATCH:
648 return 2 + index;
649
650 default:
651 /* Don't fail here. The result of this function is only used
652 * for LS, TCS, TES, and GS, where legacy GL semantics can't
653 * occur, but this function is called for all vertex shaders
654 * before it's known whether LS will be compiled or not.
655 */
656 return 0;
657 }
658 }
659
660 /* turn input into interpolate on EG */
661 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
662 {
663 int r = 0;
664
665 if (ctx->shader->input[index].spi_sid) {
666 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
667 if (ctx->shader->input[index].interpolate > 0) {
668 evergreen_interp_assign_ij_index(ctx, index);
669 r = evergreen_interp_alu(ctx, index);
670 } else {
671 r = evergreen_interp_flat(ctx, index);
672 }
673 }
674 return r;
675 }
676
677 static int select_twoside_color(struct r600_shader_ctx *ctx, int front, int back)
678 {
679 struct r600_bytecode_alu alu;
680 int i, r;
681 int gpr_front = ctx->shader->input[front].gpr;
682 int gpr_back = ctx->shader->input[back].gpr;
683
684 for (i = 0; i < 4; i++) {
685 memset(&alu, 0, sizeof(alu));
686 alu.op = ALU_OP3_CNDGT;
687 alu.is_op3 = 1;
688 alu.dst.write = 1;
689 alu.dst.sel = gpr_front;
690 alu.src[0].sel = ctx->face_gpr;
691 alu.src[1].sel = gpr_front;
692 alu.src[2].sel = gpr_back;
693
694 alu.dst.chan = i;
695 alu.src[1].chan = i;
696 alu.src[2].chan = i;
697 alu.last = (i==3);
698
699 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
700 return r;
701 }
702
703 return 0;
704 }
705
706 /* execute a single slot ALU calculation */
707 static int single_alu_op2(struct r600_shader_ctx *ctx, int op,
708 int dst_sel, int dst_chan,
709 int src0_sel, unsigned src0_chan_val,
710 int src1_sel, unsigned src1_chan_val)
711 {
712 struct r600_bytecode_alu alu;
713 int r, i;
714
715 if (ctx->bc->chip_class == CAYMAN && op == ALU_OP2_MULLO_INT) {
716 for (i = 0; i < 4; i++) {
717 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
718 alu.op = op;
719 alu.src[0].sel = src0_sel;
720 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
721 alu.src[0].value = src0_chan_val;
722 else
723 alu.src[0].chan = src0_chan_val;
724 alu.src[1].sel = src1_sel;
725 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
726 alu.src[1].value = src1_chan_val;
727 else
728 alu.src[1].chan = src1_chan_val;
729 alu.dst.sel = dst_sel;
730 alu.dst.chan = i;
731 alu.dst.write = i == dst_chan;
732 alu.last = (i == 3);
733 r = r600_bytecode_add_alu(ctx->bc, &alu);
734 if (r)
735 return r;
736 }
737 return 0;
738 }
739
740 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
741 alu.op = op;
742 alu.src[0].sel = src0_sel;
743 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
744 alu.src[0].value = src0_chan_val;
745 else
746 alu.src[0].chan = src0_chan_val;
747 alu.src[1].sel = src1_sel;
748 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
749 alu.src[1].value = src1_chan_val;
750 else
751 alu.src[1].chan = src1_chan_val;
752 alu.dst.sel = dst_sel;
753 alu.dst.chan = dst_chan;
754 alu.dst.write = 1;
755 alu.last = 1;
756 r = r600_bytecode_add_alu(ctx->bc, &alu);
757 if (r)
758 return r;
759 return 0;
760 }
761
762 /* execute a single slot ALU calculation */
763 static int single_alu_op3(struct r600_shader_ctx *ctx, int op,
764 int dst_sel, int dst_chan,
765 int src0_sel, unsigned src0_chan_val,
766 int src1_sel, unsigned src1_chan_val,
767 int src2_sel, unsigned src2_chan_val)
768 {
769 struct r600_bytecode_alu alu;
770 int r;
771
772 /* validate this for other ops */
773 assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
774 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
775 alu.op = op;
776 alu.src[0].sel = src0_sel;
777 if (src0_sel == V_SQ_ALU_SRC_LITERAL)
778 alu.src[0].value = src0_chan_val;
779 else
780 alu.src[0].chan = src0_chan_val;
781 alu.src[1].sel = src1_sel;
782 if (src1_sel == V_SQ_ALU_SRC_LITERAL)
783 alu.src[1].value = src1_chan_val;
784 else
785 alu.src[1].chan = src1_chan_val;
786 alu.src[2].sel = src2_sel;
787 if (src2_sel == V_SQ_ALU_SRC_LITERAL)
788 alu.src[2].value = src2_chan_val;
789 else
790 alu.src[2].chan = src2_chan_val;
791 alu.dst.sel = dst_sel;
792 alu.dst.chan = dst_chan;
793 alu.is_op3 = 1;
794 alu.last = 1;
795 r = r600_bytecode_add_alu(ctx->bc, &alu);
796 if (r)
797 return r;
798 return 0;
799 }
800
801 /* put it in temp_reg.x */
802 static int get_lds_offset0(struct r600_shader_ctx *ctx,
803 int rel_patch_chan,
804 int temp_reg, bool is_patch_var)
805 {
806 int r;
807
808 /* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
809 /* ADD
810 Dimension - patch0_offset (input_vals.z),
811 Non-dim - patch0_data_offset (input_vals.w)
812 */
813 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
814 temp_reg, 0,
815 ctx->tess_output_info, 0,
816 0, rel_patch_chan,
817 ctx->tess_output_info, is_patch_var ? 3 : 2);
818 if (r)
819 return r;
820 return 0;
821 }
822
823 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
824 {
825 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
826 }
827
828 static int r600_get_temp(struct r600_shader_ctx *ctx)
829 {
830 return ctx->temp_reg + ctx->max_driver_temp_used++;
831 }
832
833 static int vs_add_primid_output(struct r600_shader_ctx *ctx, int prim_id_sid)
834 {
835 int i;
836 i = ctx->shader->noutput++;
837 ctx->shader->output[i].name = TGSI_SEMANTIC_PRIMID;
838 ctx->shader->output[i].sid = 0;
839 ctx->shader->output[i].gpr = 0;
840 ctx->shader->output[i].interpolate = TGSI_INTERPOLATE_CONSTANT;
841 ctx->shader->output[i].write_mask = 0x4;
842 ctx->shader->output[i].spi_sid = prim_id_sid;
843
844 return 0;
845 }
846
847 static int tgsi_barrier(struct r600_shader_ctx *ctx)
848 {
849 struct r600_bytecode_alu alu;
850 int r;
851
852 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
853 alu.op = ctx->inst_info->op;
854 alu.last = 1;
855
856 r = r600_bytecode_add_alu(ctx->bc, &alu);
857 if (r)
858 return r;
859 return 0;
860 }
861
862 static int tgsi_declaration(struct r600_shader_ctx *ctx)
863 {
864 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
865 int r, i, j, count = d->Range.Last - d->Range.First + 1;
866
867 switch (d->Declaration.File) {
868 case TGSI_FILE_INPUT:
869 for (j = 0; j < count; j++) {
870 i = ctx->shader->ninput + j;
871 assert(i < ARRAY_SIZE(ctx->shader->input));
872 ctx->shader->input[i].name = d->Semantic.Name;
873 ctx->shader->input[i].sid = d->Semantic.Index + j;
874 ctx->shader->input[i].interpolate = d->Interp.Interpolate;
875 ctx->shader->input[i].interpolate_location = d->Interp.Location;
876 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j;
877 if (ctx->type == PIPE_SHADER_FRAGMENT) {
878 ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
879 switch (ctx->shader->input[i].name) {
880 case TGSI_SEMANTIC_FACE:
881 if (ctx->face_gpr != -1)
882 ctx->shader->input[i].gpr = ctx->face_gpr; /* already allocated by allocate_system_value_inputs */
883 else
884 ctx->face_gpr = ctx->shader->input[i].gpr;
885 break;
886 case TGSI_SEMANTIC_COLOR:
887 ctx->colors_used++;
888 break;
889 case TGSI_SEMANTIC_POSITION:
890 ctx->fragcoord_input = i;
891 break;
892 case TGSI_SEMANTIC_PRIMID:
893 /* set this for now */
894 ctx->shader->gs_prim_id_input = true;
895 ctx->shader->ps_prim_id_input = i;
896 break;
897 }
898 if (ctx->bc->chip_class >= EVERGREEN) {
899 if ((r = evergreen_interp_input(ctx, i)))
900 return r;
901 }
902 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
903 /* FIXME probably skip inputs if they aren't passed in the ring */
904 ctx->shader->input[i].ring_offset = ctx->next_ring_offset;
905 ctx->next_ring_offset += 16;
906 if (ctx->shader->input[i].name == TGSI_SEMANTIC_PRIMID)
907 ctx->shader->gs_prim_id_input = true;
908 }
909 }
910 ctx->shader->ninput += count;
911 break;
912 case TGSI_FILE_OUTPUT:
913 for (j = 0; j < count; j++) {
914 i = ctx->shader->noutput + j;
915 assert(i < ARRAY_SIZE(ctx->shader->output));
916 ctx->shader->output[i].name = d->Semantic.Name;
917 ctx->shader->output[i].sid = d->Semantic.Index + j;
918 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j;
919 ctx->shader->output[i].interpolate = d->Interp.Interpolate;
920 ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
921 if (ctx->type == PIPE_SHADER_VERTEX ||
922 ctx->type == PIPE_SHADER_GEOMETRY ||
923 ctx->type == PIPE_SHADER_TESS_EVAL) {
924 ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
925 switch (d->Semantic.Name) {
926 case TGSI_SEMANTIC_CLIPDIST:
927 break;
928 case TGSI_SEMANTIC_PSIZE:
929 ctx->shader->vs_out_misc_write = 1;
930 ctx->shader->vs_out_point_size = 1;
931 break;
932 case TGSI_SEMANTIC_EDGEFLAG:
933 ctx->shader->vs_out_misc_write = 1;
934 ctx->shader->vs_out_edgeflag = 1;
935 ctx->edgeflag_output = i;
936 break;
937 case TGSI_SEMANTIC_VIEWPORT_INDEX:
938 ctx->shader->vs_out_misc_write = 1;
939 ctx->shader->vs_out_viewport = 1;
940 break;
941 case TGSI_SEMANTIC_LAYER:
942 ctx->shader->vs_out_misc_write = 1;
943 ctx->shader->vs_out_layer = 1;
944 break;
945 case TGSI_SEMANTIC_CLIPVERTEX:
946 ctx->clip_vertex_write = TRUE;
947 ctx->cv_output = i;
948 break;
949 }
950 if (ctx->type == PIPE_SHADER_GEOMETRY) {
951 ctx->gs_out_ring_offset += 16;
952 }
953 } else if (ctx->type == PIPE_SHADER_FRAGMENT) {
954 switch (d->Semantic.Name) {
955 case TGSI_SEMANTIC_COLOR:
956 ctx->shader->nr_ps_max_color_exports++;
957 break;
958 }
959 }
960 }
961 ctx->shader->noutput += count;
962 break;
963 case TGSI_FILE_TEMPORARY:
964 if (ctx->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) {
965 if (d->Array.ArrayID) {
966 r600_add_gpr_array(ctx->shader,
967 ctx->file_offset[TGSI_FILE_TEMPORARY] +
968 d->Range.First,
969 d->Range.Last - d->Range.First + 1, 0x0F);
970 }
971 }
972 break;
973
974 case TGSI_FILE_CONSTANT:
975 case TGSI_FILE_SAMPLER:
976 case TGSI_FILE_SAMPLER_VIEW:
977 case TGSI_FILE_ADDRESS:
978 case TGSI_FILE_BUFFER:
979 case TGSI_FILE_IMAGE:
980 case TGSI_FILE_MEMORY:
981 break;
982
983 case TGSI_FILE_HW_ATOMIC:
984 i = ctx->shader->nhwatomic_ranges;
985 ctx->shader->atomics[i].start = d->Range.First;
986 ctx->shader->atomics[i].end = d->Range.Last;
987 ctx->shader->atomics[i].hw_idx = ctx->shader->atomic_base + ctx->shader->nhwatomic;
988 ctx->shader->atomics[i].array_id = d->Array.ArrayID;
989 ctx->shader->atomics[i].buffer_id = d->Dim.Index2D;
990 ctx->shader->nhwatomic_ranges++;
991 ctx->shader->nhwatomic += count;
992 break;
993
994 case TGSI_FILE_SYSTEM_VALUE:
995 if (d->Semantic.Name == TGSI_SEMANTIC_SAMPLEMASK ||
996 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEID ||
997 d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
998 break; /* Already handled from allocate_system_value_inputs */
999 } else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
1000 break;
1001 } else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
1002 break;
1003 else if (d->Semantic.Name == TGSI_SEMANTIC_INVOCATIONID)
1004 break;
1005 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
1006 d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
1007 int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
1008 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
1009 unsigned temp_reg = r600_get_temp(ctx);
1010
1011 r = get_lds_offset0(ctx, 2, temp_reg, true);
1012 if (r)
1013 return r;
1014
1015 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1016 temp_reg, 0,
1017 temp_reg, 0,
1018 V_SQ_ALU_SRC_LITERAL, param * 16);
1019 if (r)
1020 return r;
1021
1022 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
1023 }
1024 else if (d->Semantic.Name == TGSI_SEMANTIC_TESSCOORD) {
1025 /* MOV r1.x, r0.x;
1026 MOV r1.y, r0.y;
1027 */
1028 for (i = 0; i < 2; i++) {
1029 struct r600_bytecode_alu alu;
1030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1031 alu.op = ALU_OP1_MOV;
1032 alu.src[0].sel = 0;
1033 alu.src[0].chan = 0 + i;
1034 alu.dst.sel = 1;
1035 alu.dst.chan = 0 + i;
1036 alu.dst.write = 1;
1037 alu.last = (i == 1) ? 1 : 0;
1038 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1039 return r;
1040 }
1041 /* ADD r1.z, 1.0f, -r0.x */
1042 struct r600_bytecode_alu alu;
1043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1044 alu.op = ALU_OP2_ADD;
1045 alu.src[0].sel = V_SQ_ALU_SRC_1;
1046 alu.src[1].sel = 1;
1047 alu.src[1].chan = 0;
1048 alu.src[1].neg = 1;
1049 alu.dst.sel = 1;
1050 alu.dst.chan = 2;
1051 alu.dst.write = 1;
1052 alu.last = 1;
1053 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1054 return r;
1055
1056 /* ADD r1.z, r1.z, -r1.y */
1057 alu.op = ALU_OP2_ADD;
1058 alu.src[0].sel = 1;
1059 alu.src[0].chan = 2;
1060 alu.src[1].sel = 1;
1061 alu.src[1].chan = 1;
1062 alu.src[1].neg = 1;
1063 alu.dst.sel = 1;
1064 alu.dst.chan = 2;
1065 alu.dst.write = 1;
1066 alu.last = 1;
1067 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1068 return r;
1069 break;
1070 }
1071 break;
1072 default:
1073 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
1074 return -EINVAL;
1075 }
1076 return 0;
1077 }
1078
1079 static int allocate_system_value_inputs(struct r600_shader_ctx *ctx, int gpr_offset)
1080 {
1081 struct tgsi_parse_context parse;
1082 struct {
1083 boolean enabled;
1084 int *reg;
1085 unsigned name, alternate_name;
1086 } inputs[2] = {
1087 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1088
1089 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1090 };
1091 int num_regs = 0;
1092 unsigned k, i;
1093
1094 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1095 return 0;
1096 }
1097
1098 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1099 while (!tgsi_parse_end_of_tokens(&parse)) {
1100 tgsi_parse_token(&parse);
1101
1102 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1103 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1104 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1105 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1106 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1107 {
1108 int interpolate, location, k;
1109
1110 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1111 location = TGSI_INTERPOLATE_LOC_CENTER;
1112 inputs[1].enabled = true; /* needs SAMPLEID */
1113 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1114 location = TGSI_INTERPOLATE_LOC_CENTER;
1115 /* Needs sample positions, currently those are always available */
1116 } else {
1117 location = TGSI_INTERPOLATE_LOC_CENTROID;
1118 }
1119
1120 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1121 k = eg_get_interpolator_index(interpolate, location);
1122 if (k >= 0)
1123 ctx->eg_interpolators[k].enabled = true;
1124 }
1125 } else if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1126 struct tgsi_full_declaration *d = &parse.FullToken.FullDeclaration;
1127 if (d->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
1128 for (k = 0; k < ARRAY_SIZE(inputs); k++) {
1129 if (d->Semantic.Name == inputs[k].name ||
1130 d->Semantic.Name == inputs[k].alternate_name) {
1131 inputs[k].enabled = true;
1132 }
1133 }
1134 }
1135 }
1136 }
1137
1138 tgsi_parse_free(&parse);
1139
1140 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
1141 boolean enabled = inputs[i].enabled;
1142 int *reg = inputs[i].reg;
1143 unsigned name = inputs[i].name;
1144
1145 if (enabled) {
1146 int gpr = gpr_offset + num_regs++;
1147 ctx->shader->nsys_inputs++;
1148
1149 // add to inputs, allocate a gpr
1150 k = ctx->shader->ninput++;
1151 ctx->shader->input[k].name = name;
1152 ctx->shader->input[k].sid = 0;
1153 ctx->shader->input[k].interpolate = TGSI_INTERPOLATE_CONSTANT;
1154 ctx->shader->input[k].interpolate_location = TGSI_INTERPOLATE_LOC_CENTER;
1155 *reg = ctx->shader->input[k].gpr = gpr;
1156 }
1157 }
1158
1159 return gpr_offset + num_regs;
1160 }
1161
1162 /*
1163 * for evergreen we need to scan the shader to find the number of GPRs we need to
1164 * reserve for interpolation and system values
1165 *
1166 * we need to know if we are going to emit
1167 * any sample or centroid inputs
1168 * if perspective and linear are required
1169 */
1170 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
1171 {
1172 unsigned i;
1173 int num_baryc;
1174 struct tgsi_parse_context parse;
1175
1176 memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
1177
1178 for (i = 0; i < ctx->info.num_inputs; i++) {
1179 int k;
1180 /* skip position/face/mask/sampleid */
1181 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
1182 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE ||
1183 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEMASK ||
1184 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_SAMPLEID)
1185 continue;
1186
1187 k = eg_get_interpolator_index(
1188 ctx->info.input_interpolate[i],
1189 ctx->info.input_interpolate_loc[i]);
1190 if (k >= 0)
1191 ctx->eg_interpolators[k].enabled = TRUE;
1192 }
1193
1194 if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
1195 return 0;
1196 }
1197
1198 /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
1199 while (!tgsi_parse_end_of_tokens(&parse)) {
1200 tgsi_parse_token(&parse);
1201
1202 if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
1203 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1204 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1205 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1206 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1207 {
1208 int interpolate, location, k;
1209
1210 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1211 location = TGSI_INTERPOLATE_LOC_CENTER;
1212 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1213 location = TGSI_INTERPOLATE_LOC_CENTER;
1214 } else {
1215 location = TGSI_INTERPOLATE_LOC_CENTROID;
1216 }
1217
1218 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1219 k = eg_get_interpolator_index(interpolate, location);
1220 if (k >= 0)
1221 ctx->eg_interpolators[k].enabled = true;
1222 }
1223 }
1224 }
1225
1226 tgsi_parse_free(&parse);
1227
1228 /* assign gpr to each interpolator according to priority */
1229 num_baryc = 0;
1230 for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
1231 if (ctx->eg_interpolators[i].enabled) {
1232 ctx->eg_interpolators[i].ij_index = num_baryc;
1233 num_baryc ++;
1234 }
1235 }
1236
1237 /* XXX PULL MODEL and LINE STIPPLE */
1238
1239 num_baryc = (num_baryc + 1) >> 1;
1240 return allocate_system_value_inputs(ctx, num_baryc);
1241 }
1242
1243 /* sample_id_sel == NULL means fetch for current sample */
1244 static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_src *sample_id, int chan_sel)
1245 {
1246 struct r600_bytecode_vtx vtx;
1247 int r, t1;
1248
1249 assert(ctx->fixed_pt_position_gpr != -1);
1250
1251 t1 = r600_get_temp(ctx);
1252
1253 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1254 vtx.op = FETCH_OP_VFETCH;
1255 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1256 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1257 if (sample_id == NULL) {
1258 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1259 vtx.src_sel_x = 3;
1260 }
1261 else {
1262 struct r600_bytecode_alu alu;
1263
1264 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1265 alu.op = ALU_OP1_MOV;
1266 r600_bytecode_src(&alu.src[0], sample_id, chan_sel);
1267 alu.dst.sel = t1;
1268 alu.dst.write = 1;
1269 alu.last = 1;
1270 r = r600_bytecode_add_alu(ctx->bc, &alu);
1271 if (r)
1272 return r;
1273
1274 vtx.src_gpr = t1;
1275 vtx.src_sel_x = 0;
1276 }
1277 vtx.mega_fetch_count = 16;
1278 vtx.dst_gpr = t1;
1279 vtx.dst_sel_x = 0;
1280 vtx.dst_sel_y = 1;
1281 vtx.dst_sel_z = 2;
1282 vtx.dst_sel_w = 3;
1283 vtx.data_format = FMT_32_32_32_32_FLOAT;
1284 vtx.num_format_all = 2;
1285 vtx.format_comp_all = 1;
1286 vtx.use_const_fields = 0;
1287 vtx.offset = 0;
1288 vtx.endian = r600_endian_swap(32);
1289 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1290
1291 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1292 if (r)
1293 return r;
1294
1295 return t1;
1296 }
1297
1298 static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
1299 {
1300 struct r600_bytecode_vtx vtx;
1301 int r, t1;
1302
1303 if (ctx->cs_block_size_loaded)
1304 return ctx->cs_block_size_reg;
1305 if (ctx->cs_grid_size_loaded)
1306 return ctx->cs_grid_size_reg;
1307
1308 t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
1309 struct r600_bytecode_alu alu;
1310 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1311 alu.op = ALU_OP1_MOV;
1312 alu.src[0].sel = V_SQ_ALU_SRC_0;
1313 alu.dst.sel = t1;
1314 alu.dst.write = 1;
1315 alu.last = 1;
1316 r = r600_bytecode_add_alu(ctx->bc, &alu);
1317 if (r)
1318 return r;
1319
1320 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
1321 vtx.op = FETCH_OP_VFETCH;
1322 vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
1323 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1324 vtx.src_gpr = t1;
1325 vtx.src_sel_x = 0;
1326
1327 vtx.mega_fetch_count = 16;
1328 vtx.dst_gpr = t1;
1329 vtx.dst_sel_x = 0;
1330 vtx.dst_sel_y = 1;
1331 vtx.dst_sel_z = 2;
1332 vtx.dst_sel_w = 7;
1333 vtx.data_format = FMT_32_32_32_32;
1334 vtx.num_format_all = 1;
1335 vtx.format_comp_all = 0;
1336 vtx.use_const_fields = 0;
1337 vtx.offset = load_block ? 0 : 16; // first element is size of buffer
1338 vtx.endian = r600_endian_swap(32);
1339 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
1340
1341 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
1342 if (r)
1343 return r;
1344
1345 if (load_block)
1346 ctx->cs_block_size_loaded = true;
1347 else
1348 ctx->cs_grid_size_loaded = true;
1349 return t1;
1350 }
1351
1352 static void tgsi_src(struct r600_shader_ctx *ctx,
1353 const struct tgsi_full_src_register *tgsi_src,
1354 struct r600_shader_src *r600_src)
1355 {
1356 memset(r600_src, 0, sizeof(*r600_src));
1357 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
1358 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
1359 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
1360 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
1361 r600_src->neg = tgsi_src->Register.Negate;
1362 r600_src->abs = tgsi_src->Register.Absolute;
1363
1364 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
1365 int index;
1366 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
1367 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
1368 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
1369
1370 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1371 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg, r600_src->abs);
1372 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
1373 return;
1374 }
1375 index = tgsi_src->Register.Index;
1376 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
1377 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1378 } else if (tgsi_src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
1379 if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEMASK) {
1380 r600_src->swizzle[0] = 2; // Z value
1381 r600_src->swizzle[1] = 2;
1382 r600_src->swizzle[2] = 2;
1383 r600_src->swizzle[3] = 2;
1384 r600_src->sel = ctx->face_gpr;
1385 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEID) {
1386 r600_src->swizzle[0] = 3; // W value
1387 r600_src->swizzle[1] = 3;
1388 r600_src->swizzle[2] = 3;
1389 r600_src->swizzle[3] = 3;
1390 r600_src->sel = ctx->fixed_pt_position_gpr;
1391 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_SAMPLEPOS) {
1392 r600_src->swizzle[0] = 0;
1393 r600_src->swizzle[1] = 1;
1394 r600_src->swizzle[2] = 4;
1395 r600_src->swizzle[3] = 4;
1396 r600_src->sel = load_sample_position(ctx, NULL, -1);
1397 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INSTANCEID) {
1398 r600_src->swizzle[0] = 3;
1399 r600_src->swizzle[1] = 3;
1400 r600_src->swizzle[2] = 3;
1401 r600_src->swizzle[3] = 3;
1402 r600_src->sel = 0;
1403 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTEXID) {
1404 r600_src->swizzle[0] = 0;
1405 r600_src->swizzle[1] = 0;
1406 r600_src->swizzle[2] = 0;
1407 r600_src->swizzle[3] = 0;
1408 r600_src->sel = 0;
1409 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
1410 r600_src->sel = 0;
1411 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
1412 r600_src->sel = 1;
1413 } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1414 r600_src->swizzle[0] = 3;
1415 r600_src->swizzle[1] = 3;
1416 r600_src->swizzle[2] = 3;
1417 r600_src->swizzle[3] = 3;
1418 r600_src->sel = 1;
1419 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
1420 r600_src->swizzle[0] = 2;
1421 r600_src->swizzle[1] = 2;
1422 r600_src->swizzle[2] = 2;
1423 r600_src->swizzle[3] = 2;
1424 r600_src->sel = 0;
1425 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSCOORD) {
1426 r600_src->sel = 1;
1427 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSINNER) {
1428 r600_src->sel = 3;
1429 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) {
1430 r600_src->sel = 2;
1431 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) {
1432 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
1433 r600_src->sel = ctx->tess_input_info;
1434 r600_src->swizzle[0] = 2;
1435 r600_src->swizzle[1] = 2;
1436 r600_src->swizzle[2] = 2;
1437 r600_src->swizzle[3] = 2;
1438 } else {
1439 r600_src->sel = ctx->tess_input_info;
1440 r600_src->swizzle[0] = 3;
1441 r600_src->swizzle[1] = 3;
1442 r600_src->swizzle[2] = 3;
1443 r600_src->swizzle[3] = 3;
1444 }
1445 } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1446 r600_src->sel = 0;
1447 r600_src->swizzle[0] = 0;
1448 r600_src->swizzle[1] = 0;
1449 r600_src->swizzle[2] = 0;
1450 r600_src->swizzle[3] = 0;
1451 } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) {
1452 r600_src->sel = 0;
1453 r600_src->swizzle[0] = 3;
1454 r600_src->swizzle[1] = 3;
1455 r600_src->swizzle[2] = 3;
1456 r600_src->swizzle[3] = 3;
1457 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
1458 r600_src->sel = load_block_grid_size(ctx, false);
1459 } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
1460 r600_src->sel = load_block_grid_size(ctx, true);
1461 }
1462 } else {
1463 if (tgsi_src->Register.Indirect)
1464 r600_src->rel = V_SQ_REL_RELATIVE;
1465 r600_src->sel = tgsi_src->Register.Index;
1466 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
1467 }
1468 if (tgsi_src->Register.File == TGSI_FILE_CONSTANT) {
1469 if (tgsi_src->Register.Dimension) {
1470 r600_src->kc_bank = tgsi_src->Dimension.Index;
1471 if (tgsi_src->Dimension.Indirect) {
1472 r600_src->kc_rel = 1;
1473 }
1474 }
1475 }
1476 }
1477
1478 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx,
1479 unsigned int cb_idx, unsigned cb_rel, unsigned int offset, unsigned ar_chan,
1480 unsigned int dst_reg)
1481 {
1482 struct r600_bytecode_vtx vtx;
1483 unsigned int ar_reg;
1484 int r;
1485
1486 if (offset) {
1487 struct r600_bytecode_alu alu;
1488
1489 memset(&alu, 0, sizeof(alu));
1490
1491 alu.op = ALU_OP2_ADD_INT;
1492 alu.src[0].sel = ctx->bc->ar_reg;
1493 alu.src[0].chan = ar_chan;
1494
1495 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1496 alu.src[1].value = offset;
1497
1498 alu.dst.sel = dst_reg;
1499 alu.dst.chan = ar_chan;
1500 alu.dst.write = 1;
1501 alu.last = 1;
1502
1503 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
1504 return r;
1505
1506 ar_reg = dst_reg;
1507 } else {
1508 ar_reg = ctx->bc->ar_reg;
1509 }
1510
1511 memset(&vtx, 0, sizeof(vtx));
1512 vtx.buffer_id = cb_idx;
1513 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1514 vtx.src_gpr = ar_reg;
1515 vtx.src_sel_x = ar_chan;
1516 vtx.mega_fetch_count = 16;
1517 vtx.dst_gpr = dst_reg;
1518 vtx.dst_sel_x = 0; /* SEL_X */
1519 vtx.dst_sel_y = 1; /* SEL_Y */
1520 vtx.dst_sel_z = 2; /* SEL_Z */
1521 vtx.dst_sel_w = 3; /* SEL_W */
1522 vtx.data_format = FMT_32_32_32_32_FLOAT;
1523 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
1524 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
1525 vtx.endian = r600_endian_swap(32);
1526 vtx.buffer_index_mode = cb_rel; // cb_rel ? V_SQ_CF_INDEX_0 : V_SQ_CF_INDEX_NONE;
1527
1528 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1529 return r;
1530
1531 return 0;
1532 }
1533
1534 static int fetch_gs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1535 {
1536 struct r600_bytecode_vtx vtx;
1537 int r;
1538 unsigned index = src->Register.Index;
1539 unsigned vtx_id = src->Dimension.Index;
1540 int offset_reg = ctx->gs_rotated_input[vtx_id / 3];
1541 int offset_chan = vtx_id % 3;
1542 int t2 = 0;
1543
1544 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1545 * R0.w, R1.x, R1.y, R1.z (it seems R0.z is used for PrimitiveID) */
1546
1547 if (offset_reg == ctx->gs_rotated_input[0] && offset_chan == 2)
1548 offset_chan = 3;
1549
1550 if (src->Dimension.Indirect || src->Register.Indirect)
1551 t2 = r600_get_temp(ctx);
1552
1553 if (src->Dimension.Indirect) {
1554 int treg[3];
1555 struct r600_bytecode_alu alu;
1556 int r, i;
1557 unsigned addr_reg;
1558 addr_reg = get_address_file_reg(ctx, src->DimIndirect.Index);
1559 if (src->DimIndirect.Index > 0) {
1560 r = single_alu_op2(ctx, ALU_OP1_MOV,
1561 ctx->bc->ar_reg, 0,
1562 addr_reg, 0,
1563 0, 0);
1564 if (r)
1565 return r;
1566 }
1567 /*
1568 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1569 at least this is what fglrx seems to do. */
1570 for (i = 0; i < 3; i++) {
1571 treg[i] = r600_get_temp(ctx);
1572 }
1573 r600_add_gpr_array(ctx->shader, treg[0], 3, 0x0F);
1574
1575 for (i = 0; i < 3; i++) {
1576 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1577 alu.op = ALU_OP1_MOV;
1578 alu.src[0].sel = ctx->gs_rotated_input[0];
1579 alu.src[0].chan = i == 2 ? 3 : i;
1580 alu.dst.sel = treg[i];
1581 alu.dst.chan = 0;
1582 alu.dst.write = 1;
1583 alu.last = 1;
1584 r = r600_bytecode_add_alu(ctx->bc, &alu);
1585 if (r)
1586 return r;
1587 }
1588 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
1589 alu.op = ALU_OP1_MOV;
1590 alu.src[0].sel = treg[0];
1591 alu.src[0].rel = 1;
1592 alu.dst.sel = t2;
1593 alu.dst.write = 1;
1594 alu.last = 1;
1595 r = r600_bytecode_add_alu(ctx->bc, &alu);
1596 if (r)
1597 return r;
1598 offset_reg = t2;
1599 offset_chan = 0;
1600 }
1601
1602 if (src->Register.Indirect) {
1603 int addr_reg;
1604 unsigned first = ctx->info.input_array_first[src->Indirect.ArrayID];
1605
1606 addr_reg = get_address_file_reg(ctx, src->Indirect.Index);
1607
1608 /* pull the value from index_reg */
1609 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1610 t2, 1,
1611 addr_reg, 0,
1612 V_SQ_ALU_SRC_LITERAL, first);
1613 if (r)
1614 return r;
1615 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1616 t2, 0,
1617 t2, 1,
1618 V_SQ_ALU_SRC_LITERAL, 4,
1619 offset_reg, offset_chan);
1620 if (r)
1621 return r;
1622 offset_reg = t2;
1623 offset_chan = 0;
1624 index = src->Register.Index - first;
1625 }
1626
1627 memset(&vtx, 0, sizeof(vtx));
1628 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
1629 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
1630 vtx.src_gpr = offset_reg;
1631 vtx.src_sel_x = offset_chan;
1632 vtx.offset = index * 16; /*bytes*/
1633 vtx.mega_fetch_count = 16;
1634 vtx.dst_gpr = dst_reg;
1635 vtx.dst_sel_x = 0; /* SEL_X */
1636 vtx.dst_sel_y = 1; /* SEL_Y */
1637 vtx.dst_sel_z = 2; /* SEL_Z */
1638 vtx.dst_sel_w = 3; /* SEL_W */
1639 if (ctx->bc->chip_class >= EVERGREEN) {
1640 vtx.use_const_fields = 1;
1641 } else {
1642 vtx.data_format = FMT_32_32_32_32_FLOAT;
1643 }
1644
1645 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
1646 return r;
1647
1648 return 0;
1649 }
1650
1651 static int tgsi_split_gs_inputs(struct r600_shader_ctx *ctx)
1652 {
1653 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1654 unsigned i;
1655
1656 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1657 struct tgsi_full_src_register *src = &inst->Src[i];
1658
1659 if (src->Register.File == TGSI_FILE_INPUT) {
1660 if (ctx->shader->input[src->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
1661 /* primitive id is in R0.z */
1662 ctx->src[i].sel = 0;
1663 ctx->src[i].swizzle[0] = 2;
1664 }
1665 }
1666 if (src->Register.File == TGSI_FILE_INPUT && src->Register.Dimension) {
1667 int treg = r600_get_temp(ctx);
1668
1669 fetch_gs_input(ctx, src, treg);
1670 ctx->src[i].sel = treg;
1671 ctx->src[i].rel = 0;
1672 }
1673 }
1674 return 0;
1675 }
1676
1677
1678 /* Tessellation shaders pass outputs to the next shader using LDS.
1679 *
1680 * LS outputs = TCS(HS) inputs
1681 * TCS(HS) outputs = TES(DS) inputs
1682 *
1683 * The LDS layout is:
1684 * - TCS inputs for patch 0
1685 * - TCS inputs for patch 1
1686 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
1687 * - ...
1688 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
1689 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
1690 * - TCS outputs for patch 1
1691 * - Per-patch TCS outputs for patch 1
1692 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
1693 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
1694 * - ...
1695 *
1696 * All three shaders VS(LS), TCS, TES share the same LDS space.
1697 */
1698 /* this will return with the dw address in temp_reg.x */
1699 static int r600_get_byte_address(struct r600_shader_ctx *ctx, int temp_reg,
1700 const struct tgsi_full_dst_register *dst,
1701 const struct tgsi_full_src_register *src,
1702 int stride_bytes_reg, int stride_bytes_chan)
1703 {
1704 struct tgsi_full_dst_register reg;
1705 ubyte *name, *index, *array_first;
1706 int r;
1707 int param;
1708 struct tgsi_shader_info *info = &ctx->info;
1709 /* Set the register description. The address computation is the same
1710 * for sources and destinations. */
1711 if (src) {
1712 reg.Register.File = src->Register.File;
1713 reg.Register.Index = src->Register.Index;
1714 reg.Register.Indirect = src->Register.Indirect;
1715 reg.Register.Dimension = src->Register.Dimension;
1716 reg.Indirect = src->Indirect;
1717 reg.Dimension = src->Dimension;
1718 reg.DimIndirect = src->DimIndirect;
1719 } else
1720 reg = *dst;
1721
1722 /* If the register is 2-dimensional (e.g. an array of vertices
1723 * in a primitive), calculate the base address of the vertex. */
1724 if (reg.Register.Dimension) {
1725 int sel, chan;
1726 if (reg.Dimension.Indirect) {
1727 unsigned addr_reg;
1728 assert (reg.DimIndirect.File == TGSI_FILE_ADDRESS);
1729
1730 addr_reg = get_address_file_reg(ctx, reg.DimIndirect.Index);
1731 /* pull the value from index_reg */
1732 sel = addr_reg;
1733 chan = 0;
1734 } else {
1735 sel = V_SQ_ALU_SRC_LITERAL;
1736 chan = reg.Dimension.Index;
1737 }
1738
1739 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1740 temp_reg, 0,
1741 stride_bytes_reg, stride_bytes_chan,
1742 sel, chan,
1743 temp_reg, 0);
1744 if (r)
1745 return r;
1746 }
1747
1748 if (reg.Register.File == TGSI_FILE_INPUT) {
1749 name = info->input_semantic_name;
1750 index = info->input_semantic_index;
1751 array_first = info->input_array_first;
1752 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1753 name = info->output_semantic_name;
1754 index = info->output_semantic_index;
1755 array_first = info->output_array_first;
1756 } else {
1757 assert(0);
1758 return -1;
1759 }
1760 if (reg.Register.Indirect) {
1761 int addr_reg;
1762 int first;
1763 /* Add the relative address of the element. */
1764 if (reg.Indirect.ArrayID)
1765 first = array_first[reg.Indirect.ArrayID];
1766 else
1767 first = reg.Register.Index;
1768
1769 addr_reg = get_address_file_reg(ctx, reg.Indirect.Index);
1770
1771 /* pull the value from index_reg */
1772 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
1773 temp_reg, 0,
1774 V_SQ_ALU_SRC_LITERAL, 16,
1775 addr_reg, 0,
1776 temp_reg, 0);
1777 if (r)
1778 return r;
1779
1780 param = r600_get_lds_unique_index(name[first],
1781 index[first]);
1782
1783 } else {
1784 param = r600_get_lds_unique_index(name[reg.Register.Index],
1785 index[reg.Register.Index]);
1786 }
1787
1788 /* add to base_addr - passed in temp_reg.x */
1789 if (param) {
1790 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1791 temp_reg, 0,
1792 temp_reg, 0,
1793 V_SQ_ALU_SRC_LITERAL, param * 16);
1794 if (r)
1795 return r;
1796
1797 }
1798 return 0;
1799 }
1800
1801 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
1802 unsigned dst_reg, unsigned mask)
1803 {
1804 struct r600_bytecode_alu alu;
1805 int r, i, lasti;
1806
1807 if ((ctx->bc->cf_last->ndw>>1) >= 0x60)
1808 ctx->bc->force_add_cf = 1;
1809
1810 lasti = tgsi_last_instruction(mask);
1811 for (i = 1; i <= lasti; i++) {
1812 if (!(mask & (1 << i)))
1813 continue;
1814
1815 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
1816 temp_reg, i,
1817 temp_reg, 0,
1818 V_SQ_ALU_SRC_LITERAL, 4 * i);
1819 if (r)
1820 return r;
1821 }
1822 for (i = 0; i <= lasti; i++) {
1823 if (!(mask & (1 << i)))
1824 continue;
1825
1826 /* emit an LDS_READ_RET */
1827 memset(&alu, 0, sizeof(alu));
1828 alu.op = LDS_OP1_LDS_READ_RET;
1829 alu.src[0].sel = temp_reg;
1830 alu.src[0].chan = i;
1831 alu.src[1].sel = V_SQ_ALU_SRC_0;
1832 alu.src[2].sel = V_SQ_ALU_SRC_0;
1833 alu.dst.chan = 0;
1834 alu.is_lds_idx_op = true;
1835 alu.last = 1;
1836 r = r600_bytecode_add_alu(ctx->bc, &alu);
1837 if (r)
1838 return r;
1839 }
1840 for (i = 0; i <= lasti; i++) {
1841 if (!(mask & (1 << i)))
1842 continue;
1843
1844 /* then read from LDS_OQ_A_POP */
1845 memset(&alu, 0, sizeof(alu));
1846
1847 alu.op = ALU_OP1_MOV;
1848 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
1849 alu.src[0].chan = 0;
1850 alu.dst.sel = dst_reg;
1851 alu.dst.chan = i;
1852 alu.dst.write = 1;
1853 alu.last = 1;
1854 r = r600_bytecode_add_alu(ctx->bc, &alu);
1855 if (r)
1856 return r;
1857 }
1858 return 0;
1859 }
1860
1861 static int fetch_mask(struct tgsi_src_register *reg)
1862 {
1863 int mask = 0;
1864 mask |= 1 << reg->SwizzleX;
1865 mask |= 1 << reg->SwizzleY;
1866 mask |= 1 << reg->SwizzleZ;
1867 mask |= 1 << reg->SwizzleW;
1868 return mask;
1869 }
1870
1871 static int fetch_tes_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1872 {
1873 int r;
1874 unsigned temp_reg = r600_get_temp(ctx);
1875
1876 r = get_lds_offset0(ctx, 2, temp_reg,
1877 src->Register.Dimension ? false : true);
1878 if (r)
1879 return r;
1880
1881 /* the base address is now in temp.x */
1882 r = r600_get_byte_address(ctx, temp_reg,
1883 NULL, src, ctx->tess_output_info, 1);
1884 if (r)
1885 return r;
1886
1887 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1888 if (r)
1889 return r;
1890 return 0;
1891 }
1892
1893 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1894 {
1895 int r;
1896 unsigned temp_reg = r600_get_temp(ctx);
1897
1898 /* t.x = ips * r0.y */
1899 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
1900 temp_reg, 0,
1901 ctx->tess_input_info, 0,
1902 0, 1);
1903
1904 if (r)
1905 return r;
1906
1907 /* the base address is now in temp.x */
1908 r = r600_get_byte_address(ctx, temp_reg,
1909 NULL, src, ctx->tess_input_info, 1);
1910 if (r)
1911 return r;
1912
1913 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1914 if (r)
1915 return r;
1916 return 0;
1917 }
1918
1919 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct tgsi_full_src_register *src, unsigned int dst_reg)
1920 {
1921 int r;
1922 unsigned temp_reg = r600_get_temp(ctx);
1923
1924 r = get_lds_offset0(ctx, 1, temp_reg,
1925 src->Register.Dimension ? false : true);
1926 if (r)
1927 return r;
1928 /* the base address is now in temp.x */
1929 r = r600_get_byte_address(ctx, temp_reg,
1930 NULL, src,
1931 ctx->tess_output_info, 1);
1932 if (r)
1933 return r;
1934
1935 r = do_lds_fetch_values(ctx, temp_reg, dst_reg, fetch_mask(&src->Register));
1936 if (r)
1937 return r;
1938 return 0;
1939 }
1940
1941 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
1942 {
1943 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1944 unsigned i;
1945
1946 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1947 struct tgsi_full_src_register *src = &inst->Src[i];
1948
1949 if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) {
1950 int treg = r600_get_temp(ctx);
1951 fetch_tes_input(ctx, src, treg);
1952 ctx->src[i].sel = treg;
1953 ctx->src[i].rel = 0;
1954 }
1955 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) {
1956 int treg = r600_get_temp(ctx);
1957 fetch_tcs_input(ctx, src, treg);
1958 ctx->src[i].sel = treg;
1959 ctx->src[i].rel = 0;
1960 }
1961 if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) {
1962 int treg = r600_get_temp(ctx);
1963 fetch_tcs_output(ctx, src, treg);
1964 ctx->src[i].sel = treg;
1965 ctx->src[i].rel = 0;
1966 }
1967 }
1968 return 0;
1969 }
1970
1971 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
1972 {
1973 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1974 struct r600_bytecode_alu alu;
1975 int i, j, k, nconst, r;
1976
1977 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
1978 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
1979 nconst++;
1980 }
1981 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
1982 }
1983 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
1984 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
1985 continue;
1986 }
1987
1988 if (ctx->src[i].rel) {
1989 int chan = inst->Src[i].Indirect.Swizzle;
1990 int treg = r600_get_temp(ctx);
1991 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].kc_bank, ctx->src[i].kc_rel, ctx->src[i].sel - 512, chan, treg)))
1992 return r;
1993
1994 ctx->src[i].kc_bank = 0;
1995 ctx->src[i].kc_rel = 0;
1996 ctx->src[i].sel = treg;
1997 ctx->src[i].rel = 0;
1998 j--;
1999 } else if (j > 0) {
2000 int treg = r600_get_temp(ctx);
2001 for (k = 0; k < 4; k++) {
2002 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2003 alu.op = ALU_OP1_MOV;
2004 alu.src[0].sel = ctx->src[i].sel;
2005 alu.src[0].chan = k;
2006 alu.src[0].rel = ctx->src[i].rel;
2007 alu.src[0].kc_bank = ctx->src[i].kc_bank;
2008 alu.src[0].kc_rel = ctx->src[i].kc_rel;
2009 alu.dst.sel = treg;
2010 alu.dst.chan = k;
2011 alu.dst.write = 1;
2012 if (k == 3)
2013 alu.last = 1;
2014 r = r600_bytecode_add_alu(ctx->bc, &alu);
2015 if (r)
2016 return r;
2017 }
2018 ctx->src[i].sel = treg;
2019 ctx->src[i].rel =0;
2020 j--;
2021 }
2022 }
2023 return 0;
2024 }
2025
2026 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
2027 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
2028 {
2029 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2030 struct r600_bytecode_alu alu;
2031 int i, j, k, nliteral, r;
2032
2033 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2034 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2035 nliteral++;
2036 }
2037 }
2038 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
2039 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
2040 int treg = r600_get_temp(ctx);
2041 for (k = 0; k < 4; k++) {
2042 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2043 alu.op = ALU_OP1_MOV;
2044 alu.src[0].sel = ctx->src[i].sel;
2045 alu.src[0].chan = k;
2046 alu.src[0].value = ctx->src[i].value[k];
2047 alu.dst.sel = treg;
2048 alu.dst.chan = k;
2049 alu.dst.write = 1;
2050 if (k == 3)
2051 alu.last = 1;
2052 r = r600_bytecode_add_alu(ctx->bc, &alu);
2053 if (r)
2054 return r;
2055 }
2056 ctx->src[i].sel = treg;
2057 j--;
2058 }
2059 }
2060 return 0;
2061 }
2062
2063 static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
2064 {
2065 int i, r, count = ctx->shader->ninput;
2066
2067 for (i = 0; i < count; i++) {
2068 if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
2069 r = select_twoside_color(ctx, i, ctx->shader->input[i].back_color_input);
2070 if (r)
2071 return r;
2072 }
2073 }
2074 return 0;
2075 }
2076
2077 static int emit_streamout(struct r600_shader_ctx *ctx, struct pipe_stream_output_info *so,
2078 int stream, unsigned *stream_item_size UNUSED)
2079 {
2080 unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
2081 unsigned start_comp[PIPE_MAX_SHADER_OUTPUTS];
2082 int j, r;
2083 unsigned i;
2084
2085 /* Sanity checking. */
2086 if (so->num_outputs > PIPE_MAX_SO_OUTPUTS) {
2087 R600_ERR("Too many stream outputs: %d\n", so->num_outputs);
2088 r = -EINVAL;
2089 goto out_err;
2090 }
2091 for (i = 0; i < so->num_outputs; i++) {
2092 if (so->output[i].output_buffer >= 4) {
2093 R600_ERR("Exceeded the max number of stream output buffers, got: %d\n",
2094 so->output[i].output_buffer);
2095 r = -EINVAL;
2096 goto out_err;
2097 }
2098 }
2099
2100 /* Initialize locations where the outputs are stored. */
2101 for (i = 0; i < so->num_outputs; i++) {
2102
2103 so_gpr[i] = ctx->shader->output[so->output[i].register_index].gpr;
2104 start_comp[i] = so->output[i].start_component;
2105 /* Lower outputs with dst_offset < start_component.
2106 *
2107 * We can only output 4D vectors with a write mask, e.g. we can
2108 * only output the W component at offset 3, etc. If we want
2109 * to store Y, Z, or W at buffer offset 0, we need to use MOV
2110 * to move it to X and output X. */
2111 if (so->output[i].dst_offset < so->output[i].start_component) {
2112 unsigned tmp = r600_get_temp(ctx);
2113
2114 for (j = 0; j < so->output[i].num_components; j++) {
2115 struct r600_bytecode_alu alu;
2116 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2117 alu.op = ALU_OP1_MOV;
2118 alu.src[0].sel = so_gpr[i];
2119 alu.src[0].chan = so->output[i].start_component + j;
2120
2121 alu.dst.sel = tmp;
2122 alu.dst.chan = j;
2123 alu.dst.write = 1;
2124 if (j == so->output[i].num_components - 1)
2125 alu.last = 1;
2126 r = r600_bytecode_add_alu(ctx->bc, &alu);
2127 if (r)
2128 return r;
2129 }
2130 start_comp[i] = 0;
2131 so_gpr[i] = tmp;
2132 }
2133 }
2134
2135 /* Write outputs to buffers. */
2136 for (i = 0; i < so->num_outputs; i++) {
2137 struct r600_bytecode_output output;
2138
2139 if (stream != -1 && stream != so->output[i].output_buffer)
2140 continue;
2141
2142 memset(&output, 0, sizeof(struct r600_bytecode_output));
2143 output.gpr = so_gpr[i];
2144 output.elem_size = so->output[i].num_components - 1;
2145 if (output.elem_size == 2)
2146 output.elem_size = 3; // 3 not supported, write 4 with junk at end
2147 output.array_base = so->output[i].dst_offset - start_comp[i];
2148 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2149 output.burst_count = 1;
2150 /* array_size is an upper limit for the burst_count
2151 * with MEM_STREAM instructions */
2152 output.array_size = 0xFFF;
2153 output.comp_mask = ((1 << so->output[i].num_components) - 1) << start_comp[i];
2154
2155 if (ctx->bc->chip_class >= EVERGREEN) {
2156 switch (so->output[i].output_buffer) {
2157 case 0:
2158 output.op = CF_OP_MEM_STREAM0_BUF0;
2159 break;
2160 case 1:
2161 output.op = CF_OP_MEM_STREAM0_BUF1;
2162 break;
2163 case 2:
2164 output.op = CF_OP_MEM_STREAM0_BUF2;
2165 break;
2166 case 3:
2167 output.op = CF_OP_MEM_STREAM0_BUF3;
2168 break;
2169 }
2170 output.op += so->output[i].stream * 4;
2171 assert(output.op >= CF_OP_MEM_STREAM0_BUF0 && output.op <= CF_OP_MEM_STREAM3_BUF3);
2172 ctx->enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << so->output[i].stream * 4;
2173 } else {
2174 switch (so->output[i].output_buffer) {
2175 case 0:
2176 output.op = CF_OP_MEM_STREAM0;
2177 break;
2178 case 1:
2179 output.op = CF_OP_MEM_STREAM1;
2180 break;
2181 case 2:
2182 output.op = CF_OP_MEM_STREAM2;
2183 break;
2184 case 3:
2185 output.op = CF_OP_MEM_STREAM3;
2186 break;
2187 }
2188 ctx->enabled_stream_buffers_mask |= 1 << so->output[i].output_buffer;
2189 }
2190 r = r600_bytecode_add_output(ctx->bc, &output);
2191 if (r)
2192 goto out_err;
2193 }
2194 return 0;
2195 out_err:
2196 return r;
2197 }
2198
2199 static void convert_edgeflag_to_int(struct r600_shader_ctx *ctx)
2200 {
2201 struct r600_bytecode_alu alu;
2202 unsigned reg;
2203
2204 if (!ctx->shader->vs_out_edgeflag)
2205 return;
2206
2207 reg = ctx->shader->output[ctx->edgeflag_output].gpr;
2208
2209 /* clamp(x, 0, 1) */
2210 memset(&alu, 0, sizeof(alu));
2211 alu.op = ALU_OP1_MOV;
2212 alu.src[0].sel = reg;
2213 alu.dst.sel = reg;
2214 alu.dst.write = 1;
2215 alu.dst.clamp = 1;
2216 alu.last = 1;
2217 r600_bytecode_add_alu(ctx->bc, &alu);
2218
2219 memset(&alu, 0, sizeof(alu));
2220 alu.op = ALU_OP1_FLT_TO_INT;
2221 alu.src[0].sel = reg;
2222 alu.dst.sel = reg;
2223 alu.dst.write = 1;
2224 alu.last = 1;
2225 r600_bytecode_add_alu(ctx->bc, &alu);
2226 }
2227
2228 static int generate_gs_copy_shader(struct r600_context *rctx,
2229 struct r600_pipe_shader *gs,
2230 struct pipe_stream_output_info *so)
2231 {
2232 struct r600_shader_ctx ctx = {};
2233 struct r600_shader *gs_shader = &gs->shader;
2234 struct r600_pipe_shader *cshader;
2235 unsigned ocnt = gs_shader->noutput;
2236 struct r600_bytecode_alu alu;
2237 struct r600_bytecode_vtx vtx;
2238 struct r600_bytecode_output output;
2239 struct r600_bytecode_cf *cf_jump, *cf_pop,
2240 *last_exp_pos = NULL, *last_exp_param = NULL;
2241 int next_clip_pos = 61, next_param = 0;
2242 unsigned i, j;
2243 int ring;
2244 bool only_ring_0 = true;
2245 cshader = calloc(1, sizeof(struct r600_pipe_shader));
2246 if (!cshader)
2247 return 0;
2248
2249 memcpy(cshader->shader.output, gs_shader->output, ocnt *
2250 sizeof(struct r600_shader_io));
2251
2252 cshader->shader.noutput = ocnt;
2253
2254 ctx.shader = &cshader->shader;
2255 ctx.bc = &ctx.shader->bc;
2256 ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX;
2257
2258 r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family,
2259 rctx->screen->has_compressed_msaa_texturing);
2260
2261 ctx.bc->isa = rctx->isa;
2262
2263 cf_jump = NULL;
2264 memset(cshader->shader.ring_item_sizes, 0, sizeof(cshader->shader.ring_item_sizes));
2265
2266 /* R0.x = R0.x & 0x3fffffff */
2267 memset(&alu, 0, sizeof(alu));
2268 alu.op = ALU_OP2_AND_INT;
2269 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2270 alu.src[1].value = 0x3fffffff;
2271 alu.dst.write = 1;
2272 r600_bytecode_add_alu(ctx.bc, &alu);
2273
2274 /* R0.y = R0.x >> 30 */
2275 memset(&alu, 0, sizeof(alu));
2276 alu.op = ALU_OP2_LSHR_INT;
2277 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2278 alu.src[1].value = 0x1e;
2279 alu.dst.chan = 1;
2280 alu.dst.write = 1;
2281 alu.last = 1;
2282 r600_bytecode_add_alu(ctx.bc, &alu);
2283
2284 /* fetch vertex data from GSVS ring */
2285 for (i = 0; i < ocnt; ++i) {
2286 struct r600_shader_io *out = &ctx.shader->output[i];
2287
2288 out->gpr = i + 1;
2289 out->ring_offset = i * 16;
2290
2291 memset(&vtx, 0, sizeof(vtx));
2292 vtx.op = FETCH_OP_VFETCH;
2293 vtx.buffer_id = R600_GS_RING_CONST_BUFFER;
2294 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2295 vtx.mega_fetch_count = 16;
2296 vtx.offset = out->ring_offset;
2297 vtx.dst_gpr = out->gpr;
2298 vtx.src_gpr = 0;
2299 vtx.dst_sel_x = 0;
2300 vtx.dst_sel_y = 1;
2301 vtx.dst_sel_z = 2;
2302 vtx.dst_sel_w = 3;
2303 if (rctx->b.chip_class >= EVERGREEN) {
2304 vtx.use_const_fields = 1;
2305 } else {
2306 vtx.data_format = FMT_32_32_32_32_FLOAT;
2307 }
2308
2309 r600_bytecode_add_vtx(ctx.bc, &vtx);
2310 }
2311 ctx.temp_reg = i + 1;
2312 for (ring = 3; ring >= 0; --ring) {
2313 bool enabled = false;
2314 for (i = 0; i < so->num_outputs; i++) {
2315 if (so->output[i].stream == ring) {
2316 enabled = true;
2317 if (ring > 0)
2318 only_ring_0 = false;
2319 break;
2320 }
2321 }
2322 if (ring != 0 && !enabled) {
2323 cshader->shader.ring_item_sizes[ring] = 0;
2324 continue;
2325 }
2326
2327 if (cf_jump) {
2328 // Patch up jump label
2329 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2330 cf_pop = ctx.bc->cf_last;
2331
2332 cf_jump->cf_addr = cf_pop->id + 2;
2333 cf_jump->pop_count = 1;
2334 cf_pop->cf_addr = cf_pop->id + 2;
2335 cf_pop->pop_count = 1;
2336 }
2337
2338 /* PRED_SETE_INT __, R0.y, ring */
2339 memset(&alu, 0, sizeof(alu));
2340 alu.op = ALU_OP2_PRED_SETE_INT;
2341 alu.src[0].chan = 1;
2342 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2343 alu.src[1].value = ring;
2344 alu.execute_mask = 1;
2345 alu.update_pred = 1;
2346 alu.last = 1;
2347 r600_bytecode_add_alu_type(ctx.bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2348
2349 r600_bytecode_add_cfinst(ctx.bc, CF_OP_JUMP);
2350 cf_jump = ctx.bc->cf_last;
2351
2352 if (enabled)
2353 emit_streamout(&ctx, so, only_ring_0 ? -1 : ring, &cshader->shader.ring_item_sizes[ring]);
2354 cshader->shader.ring_item_sizes[ring] = ocnt * 16;
2355 }
2356
2357 /* bc adds nops - copy it */
2358 if (ctx.bc->chip_class == R600) {
2359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2360 alu.op = ALU_OP0_NOP;
2361 alu.last = 1;
2362 r600_bytecode_add_alu(ctx.bc, &alu);
2363
2364 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2365 }
2366
2367 /* export vertex data */
2368 /* XXX factor out common code with r600_shader_from_tgsi ? */
2369 for (i = 0; i < ocnt; ++i) {
2370 struct r600_shader_io *out = &ctx.shader->output[i];
2371 bool instream0 = true;
2372 if (out->name == TGSI_SEMANTIC_CLIPVERTEX)
2373 continue;
2374
2375 for (j = 0; j < so->num_outputs; j++) {
2376 if (so->output[j].register_index == i) {
2377 if (so->output[j].stream == 0)
2378 break;
2379 if (so->output[j].stream > 0)
2380 instream0 = false;
2381 }
2382 }
2383 if (!instream0)
2384 continue;
2385 memset(&output, 0, sizeof(output));
2386 output.gpr = out->gpr;
2387 output.elem_size = 3;
2388 output.swizzle_x = 0;
2389 output.swizzle_y = 1;
2390 output.swizzle_z = 2;
2391 output.swizzle_w = 3;
2392 output.burst_count = 1;
2393 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2394 output.op = CF_OP_EXPORT;
2395 switch (out->name) {
2396 case TGSI_SEMANTIC_POSITION:
2397 output.array_base = 60;
2398 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2399 break;
2400
2401 case TGSI_SEMANTIC_PSIZE:
2402 output.array_base = 61;
2403 if (next_clip_pos == 61)
2404 next_clip_pos = 62;
2405 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2406 output.swizzle_y = 7;
2407 output.swizzle_z = 7;
2408 output.swizzle_w = 7;
2409 ctx.shader->vs_out_misc_write = 1;
2410 ctx.shader->vs_out_point_size = 1;
2411 break;
2412 case TGSI_SEMANTIC_LAYER:
2413 if (out->spi_sid) {
2414 /* duplicate it as PARAM to pass to the pixel shader */
2415 output.array_base = next_param++;
2416 r600_bytecode_add_output(ctx.bc, &output);
2417 last_exp_param = ctx.bc->cf_last;
2418 }
2419 output.array_base = 61;
2420 if (next_clip_pos == 61)
2421 next_clip_pos = 62;
2422 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2423 output.swizzle_x = 7;
2424 output.swizzle_y = 7;
2425 output.swizzle_z = 0;
2426 output.swizzle_w = 7;
2427 ctx.shader->vs_out_misc_write = 1;
2428 ctx.shader->vs_out_layer = 1;
2429 break;
2430 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2431 if (out->spi_sid) {
2432 /* duplicate it as PARAM to pass to the pixel shader */
2433 output.array_base = next_param++;
2434 r600_bytecode_add_output(ctx.bc, &output);
2435 last_exp_param = ctx.bc->cf_last;
2436 }
2437 output.array_base = 61;
2438 if (next_clip_pos == 61)
2439 next_clip_pos = 62;
2440 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2441 ctx.shader->vs_out_misc_write = 1;
2442 ctx.shader->vs_out_viewport = 1;
2443 output.swizzle_x = 7;
2444 output.swizzle_y = 7;
2445 output.swizzle_z = 7;
2446 output.swizzle_w = 0;
2447 break;
2448 case TGSI_SEMANTIC_CLIPDIST:
2449 /* spi_sid is 0 for clipdistance outputs that were generated
2450 * for clipvertex - we don't need to pass them to PS */
2451 ctx.shader->clip_dist_write = gs->shader.clip_dist_write;
2452 ctx.shader->cull_dist_write = gs->shader.cull_dist_write;
2453 ctx.shader->cc_dist_mask = gs->shader.cc_dist_mask;
2454 if (out->spi_sid) {
2455 /* duplicate it as PARAM to pass to the pixel shader */
2456 output.array_base = next_param++;
2457 r600_bytecode_add_output(ctx.bc, &output);
2458 last_exp_param = ctx.bc->cf_last;
2459 }
2460 output.array_base = next_clip_pos++;
2461 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2462 break;
2463 case TGSI_SEMANTIC_FOG:
2464 output.swizzle_y = 4; /* 0 */
2465 output.swizzle_z = 4; /* 0 */
2466 output.swizzle_w = 5; /* 1 */
2467 break;
2468 default:
2469 output.array_base = next_param++;
2470 break;
2471 }
2472 r600_bytecode_add_output(ctx.bc, &output);
2473 if (output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM)
2474 last_exp_param = ctx.bc->cf_last;
2475 else
2476 last_exp_pos = ctx.bc->cf_last;
2477 }
2478
2479 if (!last_exp_pos) {
2480 memset(&output, 0, sizeof(output));
2481 output.gpr = 0;
2482 output.elem_size = 3;
2483 output.swizzle_x = 7;
2484 output.swizzle_y = 7;
2485 output.swizzle_z = 7;
2486 output.swizzle_w = 7;
2487 output.burst_count = 1;
2488 output.type = 2;
2489 output.op = CF_OP_EXPORT;
2490 output.array_base = 60;
2491 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
2492 r600_bytecode_add_output(ctx.bc, &output);
2493 last_exp_pos = ctx.bc->cf_last;
2494 }
2495
2496 if (!last_exp_param) {
2497 memset(&output, 0, sizeof(output));
2498 output.gpr = 0;
2499 output.elem_size = 3;
2500 output.swizzle_x = 7;
2501 output.swizzle_y = 7;
2502 output.swizzle_z = 7;
2503 output.swizzle_w = 7;
2504 output.burst_count = 1;
2505 output.type = 2;
2506 output.op = CF_OP_EXPORT;
2507 output.array_base = next_param++;
2508 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
2509 r600_bytecode_add_output(ctx.bc, &output);
2510 last_exp_param = ctx.bc->cf_last;
2511 }
2512
2513 last_exp_pos->op = CF_OP_EXPORT_DONE;
2514 last_exp_param->op = CF_OP_EXPORT_DONE;
2515
2516 r600_bytecode_add_cfinst(ctx.bc, CF_OP_POP);
2517 cf_pop = ctx.bc->cf_last;
2518
2519 cf_jump->cf_addr = cf_pop->id + 2;
2520 cf_jump->pop_count = 1;
2521 cf_pop->cf_addr = cf_pop->id + 2;
2522 cf_pop->pop_count = 1;
2523
2524 if (ctx.bc->chip_class == CAYMAN)
2525 cm_bytecode_add_cf_end(ctx.bc);
2526 else {
2527 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
2528 ctx.bc->cf_last->end_of_program = 1;
2529 }
2530
2531 gs->gs_copy_shader = cshader;
2532 cshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
2533
2534 ctx.bc->nstack = 1;
2535
2536 return r600_bytecode_build(ctx.bc);
2537 }
2538
2539 static int emit_inc_ring_offset(struct r600_shader_ctx *ctx, int idx, bool ind)
2540 {
2541 if (ind) {
2542 struct r600_bytecode_alu alu;
2543 int r;
2544
2545 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2546 alu.op = ALU_OP2_ADD_INT;
2547 alu.src[0].sel = ctx->gs_export_gpr_tregs[idx];
2548 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2549 alu.src[1].value = ctx->gs_out_ring_offset >> 4;
2550 alu.dst.sel = ctx->gs_export_gpr_tregs[idx];
2551 alu.dst.write = 1;
2552 alu.last = 1;
2553 r = r600_bytecode_add_alu(ctx->bc, &alu);
2554 if (r)
2555 return r;
2556 }
2557 return 0;
2558 }
2559
2560 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct pipe_stream_output_info *so UNUSED, int stream, bool ind)
2561 {
2562 struct r600_bytecode_output output;
2563 int ring_offset;
2564 unsigned i, k;
2565 int effective_stream = stream == -1 ? 0 : stream;
2566 int idx = 0;
2567
2568 for (i = 0; i < ctx->shader->noutput; i++) {
2569 if (ctx->gs_for_vs) {
2570 /* for ES we need to lookup corresponding ring offset expected by GS
2571 * (map this output to GS input by name and sid) */
2572 /* FIXME precompute offsets */
2573 ring_offset = -1;
2574 for(k = 0; k < ctx->gs_for_vs->ninput; ++k) {
2575 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2576 struct r600_shader_io *out = &ctx->shader->output[i];
2577 if (in->name == out->name && in->sid == out->sid)
2578 ring_offset = in->ring_offset;
2579 }
2580
2581 if (ring_offset == -1)
2582 continue;
2583 } else {
2584 ring_offset = idx * 16;
2585 idx++;
2586 }
2587
2588 if (stream > 0 && ctx->shader->output[i].name == TGSI_SEMANTIC_POSITION)
2589 continue;
2590 /* next_ring_offset after parsing input decls contains total size of
2591 * single vertex data, gs_next_vertex - current vertex index */
2592 if (!ind)
2593 ring_offset += ctx->gs_out_ring_offset * ctx->gs_next_vertex;
2594
2595 memset(&output, 0, sizeof(struct r600_bytecode_output));
2596 output.gpr = ctx->shader->output[i].gpr;
2597 output.elem_size = 3;
2598 output.comp_mask = 0xF;
2599 output.burst_count = 1;
2600
2601 if (ind)
2602 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
2603 else
2604 output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE;
2605
2606 switch (stream) {
2607 default:
2608 case 0:
2609 output.op = CF_OP_MEM_RING; break;
2610 case 1:
2611 output.op = CF_OP_MEM_RING1; break;
2612 case 2:
2613 output.op = CF_OP_MEM_RING2; break;
2614 case 3:
2615 output.op = CF_OP_MEM_RING3; break;
2616 }
2617
2618 if (ind) {
2619 output.array_base = ring_offset >> 2; /* in dwords */
2620 output.array_size = 0xfff;
2621 output.index_gpr = ctx->gs_export_gpr_tregs[effective_stream];
2622 } else
2623 output.array_base = ring_offset >> 2; /* in dwords */
2624 r600_bytecode_add_output(ctx->bc, &output);
2625 }
2626
2627 ++ctx->gs_next_vertex;
2628 return 0;
2629 }
2630
2631
2632 static int r600_fetch_tess_io_info(struct r600_shader_ctx *ctx)
2633 {
2634 int r;
2635 struct r600_bytecode_vtx vtx;
2636 int temp_val = ctx->temp_reg;
2637 /* need to store the TCS output somewhere */
2638 r = single_alu_op2(ctx, ALU_OP1_MOV,
2639 temp_val, 0,
2640 V_SQ_ALU_SRC_LITERAL, 0,
2641 0, 0);
2642 if (r)
2643 return r;
2644
2645 /* used by VS/TCS */
2646 if (ctx->tess_input_info) {
2647 /* fetch tcs input values into resv space */
2648 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2649 vtx.op = FETCH_OP_VFETCH;
2650 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2651 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2652 vtx.mega_fetch_count = 16;
2653 vtx.data_format = FMT_32_32_32_32;
2654 vtx.num_format_all = 2;
2655 vtx.format_comp_all = 1;
2656 vtx.use_const_fields = 0;
2657 vtx.endian = r600_endian_swap(32);
2658 vtx.srf_mode_all = 1;
2659 vtx.offset = 0;
2660 vtx.dst_gpr = ctx->tess_input_info;
2661 vtx.dst_sel_x = 0;
2662 vtx.dst_sel_y = 1;
2663 vtx.dst_sel_z = 2;
2664 vtx.dst_sel_w = 3;
2665 vtx.src_gpr = temp_val;
2666 vtx.src_sel_x = 0;
2667
2668 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2669 if (r)
2670 return r;
2671 }
2672
2673 /* used by TCS/TES */
2674 if (ctx->tess_output_info) {
2675 /* fetch tcs output values into resv space */
2676 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
2677 vtx.op = FETCH_OP_VFETCH;
2678 vtx.buffer_id = R600_LDS_INFO_CONST_BUFFER;
2679 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
2680 vtx.mega_fetch_count = 16;
2681 vtx.data_format = FMT_32_32_32_32;
2682 vtx.num_format_all = 2;
2683 vtx.format_comp_all = 1;
2684 vtx.use_const_fields = 0;
2685 vtx.endian = r600_endian_swap(32);
2686 vtx.srf_mode_all = 1;
2687 vtx.offset = 16;
2688 vtx.dst_gpr = ctx->tess_output_info;
2689 vtx.dst_sel_x = 0;
2690 vtx.dst_sel_y = 1;
2691 vtx.dst_sel_z = 2;
2692 vtx.dst_sel_w = 3;
2693 vtx.src_gpr = temp_val;
2694 vtx.src_sel_x = 0;
2695
2696 r = r600_bytecode_add_vtx(ctx->bc, &vtx);
2697 if (r)
2698 return r;
2699 }
2700 return 0;
2701 }
2702
2703 static int emit_lds_vs_writes(struct r600_shader_ctx *ctx)
2704 {
2705 int j, r;
2706 int temp_reg;
2707 unsigned i;
2708
2709 /* fetch tcs input values into input_vals */
2710 ctx->tess_input_info = r600_get_temp(ctx);
2711 ctx->tess_output_info = 0;
2712 r = r600_fetch_tess_io_info(ctx);
2713 if (r)
2714 return r;
2715
2716 temp_reg = r600_get_temp(ctx);
2717 /* dst reg contains LDS address stride * idx */
2718 /* MUL vertexID, vertex_dw_stride */
2719 r = single_alu_op2(ctx, ALU_OP2_MUL_UINT24,
2720 temp_reg, 0,
2721 ctx->tess_input_info, 1,
2722 0, 1); /* rel id in r0.y? */
2723 if (r)
2724 return r;
2725
2726 for (i = 0; i < ctx->shader->noutput; i++) {
2727 struct r600_bytecode_alu alu;
2728 int param = r600_get_lds_unique_index(ctx->shader->output[i].name, ctx->shader->output[i].sid);
2729
2730 if (param) {
2731 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2732 temp_reg, 1,
2733 temp_reg, 0,
2734 V_SQ_ALU_SRC_LITERAL, param * 16);
2735 if (r)
2736 return r;
2737 }
2738
2739 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2740 temp_reg, 2,
2741 temp_reg, param ? 1 : 0,
2742 V_SQ_ALU_SRC_LITERAL, 8);
2743 if (r)
2744 return r;
2745
2746
2747 for (j = 0; j < 2; j++) {
2748 int chan = (j == 1) ? 2 : (param ? 1 : 0);
2749 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2750 alu.op = LDS_OP3_LDS_WRITE_REL;
2751 alu.src[0].sel = temp_reg;
2752 alu.src[0].chan = chan;
2753 alu.src[1].sel = ctx->shader->output[i].gpr;
2754 alu.src[1].chan = j * 2;
2755 alu.src[2].sel = ctx->shader->output[i].gpr;
2756 alu.src[2].chan = (j * 2) + 1;
2757 alu.last = 1;
2758 alu.dst.chan = 0;
2759 alu.lds_idx = 1;
2760 alu.is_lds_idx_op = true;
2761 r = r600_bytecode_add_alu(ctx->bc, &alu);
2762 if (r)
2763 return r;
2764 }
2765 }
2766 return 0;
2767 }
2768
2769 static int r600_store_tcs_output(struct r600_shader_ctx *ctx)
2770 {
2771 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2772 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
2773 int i, r, lasti;
2774 int temp_reg = r600_get_temp(ctx);
2775 struct r600_bytecode_alu alu;
2776 unsigned write_mask = dst->Register.WriteMask;
2777
2778 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
2779 return 0;
2780
2781 r = get_lds_offset0(ctx, 1, temp_reg, dst->Register.Dimension ? false : true);
2782 if (r)
2783 return r;
2784
2785 /* the base address is now in temp.x */
2786 r = r600_get_byte_address(ctx, temp_reg,
2787 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
2788 if (r)
2789 return r;
2790
2791 /* LDS write */
2792 lasti = tgsi_last_instruction(write_mask);
2793 for (i = 1; i <= lasti; i++) {
2794
2795 if (!(write_mask & (1 << i)))
2796 continue;
2797 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2798 temp_reg, i,
2799 temp_reg, 0,
2800 V_SQ_ALU_SRC_LITERAL, 4 * i);
2801 if (r)
2802 return r;
2803 }
2804
2805 for (i = 0; i <= lasti; i++) {
2806 if (!(write_mask & (1 << i)))
2807 continue;
2808
2809 if ((i == 0 && ((write_mask & 3) == 3)) ||
2810 (i == 2 && ((write_mask & 0xc) == 0xc))) {
2811 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2812 alu.op = LDS_OP3_LDS_WRITE_REL;
2813 alu.src[0].sel = temp_reg;
2814 alu.src[0].chan = i;
2815
2816 alu.src[1].sel = dst->Register.Index;
2817 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2818 alu.src[1].chan = i;
2819
2820 alu.src[2].sel = dst->Register.Index;
2821 alu.src[2].sel += ctx->file_offset[dst->Register.File];
2822 alu.src[2].chan = i + 1;
2823 alu.lds_idx = 1;
2824 alu.dst.chan = 0;
2825 alu.last = 1;
2826 alu.is_lds_idx_op = true;
2827 r = r600_bytecode_add_alu(ctx->bc, &alu);
2828 if (r)
2829 return r;
2830 i += 1;
2831 continue;
2832 }
2833 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
2834 alu.op = LDS_OP2_LDS_WRITE;
2835 alu.src[0].sel = temp_reg;
2836 alu.src[0].chan = i;
2837
2838 alu.src[1].sel = dst->Register.Index;
2839 alu.src[1].sel += ctx->file_offset[dst->Register.File];
2840 alu.src[1].chan = i;
2841
2842 alu.src[2].sel = V_SQ_ALU_SRC_0;
2843 alu.dst.chan = 0;
2844 alu.last = 1;
2845 alu.is_lds_idx_op = true;
2846 r = r600_bytecode_add_alu(ctx->bc, &alu);
2847 if (r)
2848 return r;
2849 }
2850 return 0;
2851 }
2852
2853 static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
2854 int output_idx, int nc)
2855 {
2856 int param;
2857 unsigned temp_reg = r600_get_temp(ctx);
2858 unsigned name = ctx->shader->output[output_idx].name;
2859 int dreg = ctx->shader->output[output_idx].gpr;
2860 int r;
2861
2862 param = r600_get_lds_unique_index(name, 0);
2863 r = get_lds_offset0(ctx, 1, temp_reg, true);
2864 if (r)
2865 return r;
2866
2867 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2868 temp_reg, 0,
2869 temp_reg, 0,
2870 V_SQ_ALU_SRC_LITERAL, param * 16);
2871 if (r)
2872 return r;
2873
2874 do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
2875 return 0;
2876 }
2877
2878 static int r600_emit_tess_factor(struct r600_shader_ctx *ctx)
2879 {
2880 int stride, outer_comps, inner_comps;
2881 int tessinner_idx = -1, tessouter_idx = -1;
2882 int i, r;
2883 unsigned j;
2884 int temp_reg = r600_get_temp(ctx);
2885 int treg[3] = {-1, -1, -1};
2886 struct r600_bytecode_alu alu;
2887 struct r600_bytecode_cf *cf_jump, *cf_pop;
2888
2889 /* only execute factor emission for invocation 0 */
2890 /* PRED_SETE_INT __, R0.x, 0 */
2891 memset(&alu, 0, sizeof(alu));
2892 alu.op = ALU_OP2_PRED_SETE_INT;
2893 alu.src[0].chan = 2;
2894 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2895 alu.execute_mask = 1;
2896 alu.update_pred = 1;
2897 alu.last = 1;
2898 r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_PUSH_BEFORE);
2899
2900 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
2901 cf_jump = ctx->bc->cf_last;
2902
2903 treg[0] = r600_get_temp(ctx);
2904 switch (ctx->shader->tcs_prim_mode) {
2905 case PIPE_PRIM_LINES:
2906 stride = 8; /* 2 dwords, 1 vec2 store */
2907 outer_comps = 2;
2908 inner_comps = 0;
2909 break;
2910 case PIPE_PRIM_TRIANGLES:
2911 stride = 16; /* 4 dwords, 1 vec4 store */
2912 outer_comps = 3;
2913 inner_comps = 1;
2914 treg[1] = r600_get_temp(ctx);
2915 break;
2916 case PIPE_PRIM_QUADS:
2917 stride = 24; /* 6 dwords, 2 stores (vec4 + vec2) */
2918 outer_comps = 4;
2919 inner_comps = 2;
2920 treg[1] = r600_get_temp(ctx);
2921 treg[2] = r600_get_temp(ctx);
2922 break;
2923 default:
2924 assert(0);
2925 return -1;
2926 }
2927
2928 /* R0 is InvocationID, RelPatchID, PatchID, tf_base */
2929 /* TF_WRITE takes index in R.x, value in R.y */
2930 for (j = 0; j < ctx->shader->noutput; j++) {
2931 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSINNER)
2932 tessinner_idx = j;
2933 if (ctx->shader->output[j].name == TGSI_SEMANTIC_TESSOUTER)
2934 tessouter_idx = j;
2935 }
2936
2937 if (tessouter_idx == -1)
2938 return -1;
2939
2940 if (tessinner_idx == -1 && inner_comps)
2941 return -1;
2942
2943 if (tessouter_idx != -1) {
2944 r = r600_tess_factor_read(ctx, tessouter_idx, outer_comps);
2945 if (r)
2946 return r;
2947 }
2948
2949 if (tessinner_idx != -1) {
2950 r = r600_tess_factor_read(ctx, tessinner_idx, inner_comps);
2951 if (r)
2952 return r;
2953 }
2954
2955 /* r.x = tf_base(r0.w) + relpatchid(r0.y) * tf_stride */
2956 /* r.x = relpatchid(r0.y) * tf_stride */
2957
2958 /* multiply incoming r0.y * stride - t.x = r0.y * stride */
2959 /* add incoming r0.w to it: t.x = t.x + r0.w */
2960 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
2961 temp_reg, 0,
2962 0, 1,
2963 V_SQ_ALU_SRC_LITERAL, stride,
2964 0, 3);
2965 if (r)
2966 return r;
2967
2968 for (i = 0; i < outer_comps + inner_comps; i++) {
2969 int out_idx = i >= outer_comps ? tessinner_idx : tessouter_idx;
2970 int out_comp = i >= outer_comps ? i - outer_comps : i;
2971
2972 if (ctx->shader->tcs_prim_mode == PIPE_PRIM_LINES) {
2973 if (out_comp == 1)
2974 out_comp = 0;
2975 else if (out_comp == 0)
2976 out_comp = 1;
2977 }
2978
2979 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
2980 treg[i / 2], (2 * (i % 2)),
2981 temp_reg, 0,
2982 V_SQ_ALU_SRC_LITERAL, 4 * i);
2983 if (r)
2984 return r;
2985 r = single_alu_op2(ctx, ALU_OP1_MOV,
2986 treg[i / 2], 1 + (2 * (i%2)),
2987 ctx->shader->output[out_idx].gpr, out_comp,
2988 0, 0);
2989 if (r)
2990 return r;
2991 }
2992 for (i = 0; i < outer_comps + inner_comps; i++) {
2993 struct r600_bytecode_gds gds;
2994
2995 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
2996 gds.src_gpr = treg[i / 2];
2997 gds.src_sel_x = 2 * (i % 2);
2998 gds.src_sel_y = 1 + (2 * (i % 2));
2999 gds.src_sel_z = 4;
3000 gds.dst_sel_x = 7;
3001 gds.dst_sel_y = 7;
3002 gds.dst_sel_z = 7;
3003 gds.dst_sel_w = 7;
3004 gds.op = FETCH_OP_TF_WRITE;
3005 r = r600_bytecode_add_gds(ctx->bc, &gds);
3006 if (r)
3007 return r;
3008 }
3009
3010 // Patch up jump label
3011 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
3012 cf_pop = ctx->bc->cf_last;
3013
3014 cf_jump->cf_addr = cf_pop->id + 2;
3015 cf_jump->pop_count = 1;
3016 cf_pop->cf_addr = cf_pop->id + 2;
3017 cf_pop->pop_count = 1;
3018
3019 return 0;
3020 }
3021
3022 /*
3023 * We have to work out the thread ID for load and atomic
3024 * operations, which store the returned value to an index
3025 * in an intermediate buffer.
3026 * The index is calculated by taking the thread id,
3027 * calculated from the MBCNT instructions.
3028 * Then the shader engine ID is multiplied by 256,
3029 * and the wave id is added.
3030 * Then the result is multipled by 64 and thread id is
3031 * added.
3032 */
3033 static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
3034 {
3035 struct r600_bytecode_alu alu;
3036 int r;
3037
3038 if (ctx->thread_id_gpr_loaded)
3039 return 0;
3040
3041 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3042 alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
3043 alu.dst.sel = ctx->temp_reg;
3044 alu.dst.chan = 0;
3045 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3046 alu.src[0].value = 0xffffffff;
3047 alu.dst.write = 1;
3048 r = r600_bytecode_add_alu(ctx->bc, &alu);
3049 if (r)
3050 return r;
3051
3052 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3053 alu.op = ALU_OP1_MBCNT_32HI_INT;
3054 alu.dst.sel = ctx->temp_reg;
3055 alu.dst.chan = 1;
3056 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3057 alu.src[0].value = 0xffffffff;
3058 alu.dst.write = 1;
3059 r = r600_bytecode_add_alu(ctx->bc, &alu);
3060 if (r)
3061 return r;
3062
3063 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3064 alu.op = ALU_OP3_MULADD_UINT24;
3065 alu.dst.sel = ctx->temp_reg;
3066 alu.dst.chan = 2;
3067 alu.src[0].sel = EG_V_SQ_ALU_SRC_SE_ID;
3068 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
3069 alu.src[1].value = 256;
3070 alu.src[2].sel = EG_V_SQ_ALU_SRC_HW_WAVE_ID;
3071 alu.dst.write = 1;
3072 alu.is_op3 = 1;
3073 alu.last = 1;
3074 r = r600_bytecode_add_alu(ctx->bc, &alu);
3075 if (r)
3076 return r;
3077
3078 r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
3079 ctx->thread_id_gpr, 1,
3080 ctx->temp_reg, 2,
3081 V_SQ_ALU_SRC_LITERAL, 0x40,
3082 ctx->temp_reg, 0);
3083 if (r)
3084 return r;
3085 ctx->thread_id_gpr_loaded = true;
3086 return 0;
3087 }
3088
3089 static int r600_shader_from_tgsi(struct r600_context *rctx,
3090 struct r600_pipe_shader *pipeshader,
3091 union r600_shader_key key)
3092 {
3093 struct r600_screen *rscreen = rctx->screen;
3094 struct r600_shader *shader = &pipeshader->shader;
3095 struct tgsi_token *tokens = pipeshader->selector->tokens;
3096 struct pipe_stream_output_info so = pipeshader->selector->so;
3097 struct tgsi_full_immediate *immediate;
3098 struct r600_shader_ctx ctx;
3099 struct r600_bytecode_output output[ARRAY_SIZE(shader->output)];
3100 unsigned output_done, noutput;
3101 unsigned opcode;
3102 int j, k, r = 0;
3103 unsigned i;
3104 int next_param_base = 0, next_clip_base;
3105 int max_color_exports = MAX2(key.ps.nr_cbufs, 1);
3106 bool indirect_gprs;
3107 bool ring_outputs = false;
3108 bool lds_outputs = false;
3109 bool lds_inputs = false;
3110 bool pos_emitted = false;
3111
3112 ctx.bc = &shader->bc;
3113 ctx.shader = shader;
3114
3115 r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
3116 rscreen->has_compressed_msaa_texturing);
3117 ctx.tokens = tokens;
3118 tgsi_scan_shader(tokens, &ctx.info);
3119 shader->indirect_files = ctx.info.indirect_files;
3120
3121 shader->uses_doubles = ctx.info.uses_doubles;
3122 shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
3123 shader->nsys_inputs = 0;
3124
3125 shader->uses_images = ctx.info.file_count[TGSI_FILE_IMAGE] > 0 ||
3126 ctx.info.file_count[TGSI_FILE_BUFFER] > 0;
3127 indirect_gprs = ctx.info.indirect_files & ~((1 << TGSI_FILE_CONSTANT) | (1 << TGSI_FILE_SAMPLER));
3128 tgsi_parse_init(&ctx.parse, tokens);
3129 ctx.type = ctx.info.processor;
3130 shader->processor_type = ctx.type;
3131 ctx.bc->type = shader->processor_type;
3132
3133 switch (ctx.type) {
3134 case PIPE_SHADER_VERTEX:
3135 shader->vs_as_gs_a = key.vs.as_gs_a;
3136 shader->vs_as_es = key.vs.as_es;
3137 shader->vs_as_ls = key.vs.as_ls;
3138 shader->atomic_base = key.vs.first_atomic_counter;
3139 if (shader->vs_as_es)
3140 ring_outputs = true;
3141 if (shader->vs_as_ls)
3142 lds_outputs = true;
3143 break;
3144 case PIPE_SHADER_GEOMETRY:
3145 ring_outputs = true;
3146 shader->atomic_base = key.gs.first_atomic_counter;
3147 shader->gs_tri_strip_adj_fix = key.gs.tri_strip_adj_fix;
3148 break;
3149 case PIPE_SHADER_TESS_CTRL:
3150 shader->tcs_prim_mode = key.tcs.prim_mode;
3151 shader->atomic_base = key.tcs.first_atomic_counter;
3152 lds_outputs = true;
3153 lds_inputs = true;
3154 break;
3155 case PIPE_SHADER_TESS_EVAL:
3156 shader->tes_as_es = key.tes.as_es;
3157 shader->atomic_base = key.tes.first_atomic_counter;
3158 lds_inputs = true;
3159 if (shader->tes_as_es)
3160 ring_outputs = true;
3161 break;
3162 case PIPE_SHADER_FRAGMENT:
3163 shader->two_side = key.ps.color_two_side;
3164 shader->atomic_base = key.ps.first_atomic_counter;
3165 shader->rat_base = key.ps.nr_cbufs;
3166 shader->image_size_const_offset = key.ps.image_size_const_offset;
3167 break;
3168 case PIPE_SHADER_COMPUTE:
3169 shader->rat_base = 0;
3170 shader->image_size_const_offset = 0;
3171 break;
3172 default:
3173 break;
3174 }
3175
3176 if (shader->vs_as_es || shader->tes_as_es) {
3177 ctx.gs_for_vs = &rctx->gs_shader->current->shader;
3178 } else {
3179 ctx.gs_for_vs = NULL;
3180 }
3181
3182 ctx.next_ring_offset = 0;
3183 ctx.gs_out_ring_offset = 0;
3184 ctx.gs_next_vertex = 0;
3185 ctx.gs_stream_output_info = &so;
3186
3187 ctx.face_gpr = -1;
3188 ctx.fixed_pt_position_gpr = -1;
3189 ctx.fragcoord_input = -1;
3190 ctx.colors_used = 0;
3191 ctx.clip_vertex_write = 0;
3192 ctx.thread_id_gpr_loaded = false;
3193
3194 ctx.cs_block_size_reg = -1;
3195 ctx.cs_grid_size_reg = -1;
3196 ctx.cs_block_size_loaded = false;
3197 ctx.cs_grid_size_loaded = false;
3198
3199 shader->nr_ps_color_exports = 0;
3200 shader->nr_ps_max_color_exports = 0;
3201
3202
3203 /* register allocations */
3204 /* Values [0,127] correspond to GPR[0..127].
3205 * Values [128,159] correspond to constant buffer bank 0
3206 * Values [160,191] correspond to constant buffer bank 1
3207 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
3208 * Values [256,287] correspond to constant buffer bank 2 (EG)
3209 * Values [288,319] correspond to constant buffer bank 3 (EG)
3210 * Other special values are shown in the list below.
3211 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
3212 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
3213 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
3214 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
3215 * 248 SQ_ALU_SRC_0: special constant 0.0.
3216 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
3217 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
3218 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
3219 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
3220 * 253 SQ_ALU_SRC_LITERAL: literal constant.
3221 * 254 SQ_ALU_SRC_PV: previous vector result.
3222 * 255 SQ_ALU_SRC_PS: previous scalar result.
3223 */
3224 for (i = 0; i < TGSI_FILE_COUNT; i++) {
3225 ctx.file_offset[i] = 0;
3226 }
3227
3228 if (ctx.type == PIPE_SHADER_VERTEX) {
3229
3230 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3231 if (ctx.info.num_inputs)
3232 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS);
3233 }
3234 if (ctx.type == PIPE_SHADER_FRAGMENT) {
3235 if (ctx.bc->chip_class >= EVERGREEN)
3236 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
3237 else
3238 ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
3239 }
3240 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3241 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3242 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3243 }
3244 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3245 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3246 if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3247 bool add_tesscoord = false, add_tess_inout = false;
3248 ctx.file_offset[TGSI_FILE_INPUT] = 1;
3249 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3250 /* if we have tesscoord save one reg */
3251 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSCOORD)
3252 add_tesscoord = true;
3253 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSINNER ||
3254 ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_TESSOUTER)
3255 add_tess_inout = true;
3256 }
3257 if (add_tesscoord || add_tess_inout)
3258 ctx.file_offset[TGSI_FILE_INPUT]++;
3259 if (add_tess_inout)
3260 ctx.file_offset[TGSI_FILE_INPUT]+=2;
3261 }
3262 if (ctx.type == PIPE_SHADER_COMPUTE) {
3263 ctx.file_offset[TGSI_FILE_INPUT] = 2;
3264 for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
3265 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
3266 ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3267 if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
3268 ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
3269 }
3270 }
3271
3272 ctx.file_offset[TGSI_FILE_OUTPUT] =
3273 ctx.file_offset[TGSI_FILE_INPUT] +
3274 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3275 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
3276 ctx.info.file_max[TGSI_FILE_OUTPUT] + 1;
3277
3278 /* Outside the GPR range. This will be translated to one of the
3279 * kcache banks later. */
3280 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
3281
3282 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
3283 ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
3284 ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
3285 ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
3286 ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
3287
3288 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3289 ctx.tess_input_info = ctx.bc->ar_reg + 3;
3290 ctx.tess_output_info = ctx.bc->ar_reg + 4;
3291 ctx.temp_reg = ctx.bc->ar_reg + 5;
3292 } else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
3293 ctx.tess_input_info = 0;
3294 ctx.tess_output_info = ctx.bc->ar_reg + 3;
3295 ctx.temp_reg = ctx.bc->ar_reg + 4;
3296 } else if (ctx.type == PIPE_SHADER_GEOMETRY) {
3297 ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
3298 ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
3299 ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
3300 ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
3301 ctx.temp_reg = ctx.bc->ar_reg + 7;
3302 if (ctx.shader->gs_tri_strip_adj_fix) {
3303 ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
3304 ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
3305 ctx.temp_reg += 2;
3306 } else {
3307 ctx.gs_rotated_input[0] = 0;
3308 ctx.gs_rotated_input[1] = 1;
3309 }
3310 } else {
3311 ctx.temp_reg = ctx.bc->ar_reg + 3;
3312 }
3313
3314 if (shader->uses_images) {
3315 ctx.thread_id_gpr = ctx.temp_reg++;
3316 ctx.thread_id_gpr_loaded = false;
3317 }
3318
3319 shader->max_arrays = 0;
3320 shader->num_arrays = 0;
3321 if (indirect_gprs) {
3322
3323 if (ctx.info.indirect_files & (1 << TGSI_FILE_INPUT)) {
3324 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_INPUT],
3325 ctx.file_offset[TGSI_FILE_OUTPUT] -
3326 ctx.file_offset[TGSI_FILE_INPUT],
3327 0x0F);
3328 }
3329 if (ctx.info.indirect_files & (1 << TGSI_FILE_OUTPUT)) {
3330 r600_add_gpr_array(shader, ctx.file_offset[TGSI_FILE_OUTPUT],
3331 ctx.file_offset[TGSI_FILE_TEMPORARY] -
3332 ctx.file_offset[TGSI_FILE_OUTPUT],
3333 0x0F);
3334 }
3335 }
3336
3337 ctx.nliterals = 0;
3338 ctx.literals = NULL;
3339 ctx.max_driver_temp_used = 0;
3340
3341 shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
3342 ctx.info.colors_written == 1;
3343 shader->vs_position_window_space = ctx.info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
3344 shader->ps_conservative_z = (uint8_t)ctx.info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT];
3345
3346 if (ctx.type == PIPE_SHADER_VERTEX ||
3347 ctx.type == PIPE_SHADER_GEOMETRY ||
3348 ctx.type == PIPE_SHADER_TESS_EVAL) {
3349 shader->cc_dist_mask = (1 << (ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED] +
3350 ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED])) - 1;
3351 shader->clip_dist_write = (1 << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED]) - 1;
3352 shader->cull_dist_write = ((1 << ctx.info.properties[TGSI_PROPERTY_NUM_CULLDIST_ENABLED]) - 1) << ctx.info.properties[TGSI_PROPERTY_NUM_CLIPDIST_ENABLED];
3353 }
3354
3355 if (shader->vs_as_gs_a)
3356 vs_add_primid_output(&ctx, key.vs.prim_id_out);
3357
3358 if (ctx.type == PIPE_SHADER_TESS_EVAL)
3359 r600_fetch_tess_io_info(&ctx);
3360
3361 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3362 tgsi_parse_token(&ctx.parse);
3363 switch (ctx.parse.FullToken.Token.Type) {
3364 case TGSI_TOKEN_TYPE_IMMEDIATE:
3365 immediate = &ctx.parse.FullToken.FullImmediate;
3366 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
3367 if(ctx.literals == NULL) {
3368 r = -ENOMEM;
3369 goto out_err;
3370 }
3371 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
3372 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
3373 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
3374 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
3375 ctx.nliterals++;
3376 break;
3377 case TGSI_TOKEN_TYPE_DECLARATION:
3378 r = tgsi_declaration(&ctx);
3379 if (r)
3380 goto out_err;
3381 break;
3382 case TGSI_TOKEN_TYPE_INSTRUCTION:
3383 case TGSI_TOKEN_TYPE_PROPERTY:
3384 break;
3385 default:
3386 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
3387 r = -EINVAL;
3388 goto out_err;
3389 }
3390 }
3391
3392 shader->ring_item_sizes[0] = ctx.next_ring_offset;
3393 shader->ring_item_sizes[1] = 0;
3394 shader->ring_item_sizes[2] = 0;
3395 shader->ring_item_sizes[3] = 0;
3396
3397 /* Process two side if needed */
3398 if (shader->two_side && ctx.colors_used) {
3399 int i, count = ctx.shader->ninput;
3400 unsigned next_lds_loc = ctx.shader->nlds;
3401
3402 /* additional inputs will be allocated right after the existing inputs,
3403 * we won't need them after the color selection, so we don't need to
3404 * reserve these gprs for the rest of the shader code and to adjust
3405 * output offsets etc. */
3406 int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
3407 ctx.info.file_max[TGSI_FILE_INPUT] + 1;
3408
3409 /* if two sided and neither face or sample mask is used by shader, ensure face_gpr is emitted */
3410 if (ctx.face_gpr == -1) {
3411 i = ctx.shader->ninput++;
3412 ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
3413 ctx.shader->input[i].spi_sid = 0;
3414 ctx.shader->input[i].gpr = gpr++;
3415 ctx.face_gpr = ctx.shader->input[i].gpr;
3416 }
3417
3418 for (i = 0; i < count; i++) {
3419 if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
3420 int ni = ctx.shader->ninput++;
3421 memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct r600_shader_io));
3422 ctx.shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
3423 ctx.shader->input[ni].spi_sid = r600_spi_sid(&ctx.shader->input[ni]);
3424 ctx.shader->input[ni].gpr = gpr++;
3425 // TGSI to LLVM needs to know the lds position of inputs.
3426 // Non LLVM path computes it later (in process_twoside_color)
3427 ctx.shader->input[ni].lds_pos = next_lds_loc++;
3428 ctx.shader->input[i].back_color_input = ni;
3429 if (ctx.bc->chip_class >= EVERGREEN) {
3430 if ((r = evergreen_interp_input(&ctx, ni)))
3431 return r;
3432 }
3433 }
3434 }
3435 }
3436
3437 if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
3438 shader->nr_ps_max_color_exports = 8;
3439
3440 if (ctx.fragcoord_input >= 0) {
3441 if (ctx.bc->chip_class == CAYMAN) {
3442 for (j = 0 ; j < 4; j++) {
3443 struct r600_bytecode_alu alu;
3444 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3445 alu.op = ALU_OP1_RECIP_IEEE;
3446 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3447 alu.src[0].chan = 3;
3448
3449 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3450 alu.dst.chan = j;
3451 alu.dst.write = (j == 3);
3452 alu.last = 1;
3453 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3454 return r;
3455 }
3456 } else {
3457 struct r600_bytecode_alu alu;
3458 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3459 alu.op = ALU_OP1_RECIP_IEEE;
3460 alu.src[0].sel = shader->input[ctx.fragcoord_input].gpr;
3461 alu.src[0].chan = 3;
3462
3463 alu.dst.sel = shader->input[ctx.fragcoord_input].gpr;
3464 alu.dst.chan = 3;
3465 alu.dst.write = 1;
3466 alu.last = 1;
3467 if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
3468 return r;
3469 }
3470 }
3471
3472 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3473 struct r600_bytecode_alu alu;
3474 int r;
3475
3476 /* GS thread with no output workaround - emit a cut at start of GS */
3477 if (ctx.bc->chip_class == R600)
3478 r600_bytecode_add_cfinst(ctx.bc, CF_OP_CUT_VERTEX);
3479
3480 for (j = 0; j < 4; j++) {
3481 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3482 alu.op = ALU_OP1_MOV;
3483 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
3484 alu.src[0].value = 0;
3485 alu.dst.sel = ctx.gs_export_gpr_tregs[j];
3486 alu.dst.write = 1;
3487 alu.last = 1;
3488 r = r600_bytecode_add_alu(ctx.bc, &alu);
3489 if (r)
3490 return r;
3491 }
3492
3493 if (ctx.shader->gs_tri_strip_adj_fix) {
3494 r = single_alu_op2(&ctx, ALU_OP2_AND_INT,
3495 ctx.gs_rotated_input[0], 2,
3496 0, 2,
3497 V_SQ_ALU_SRC_LITERAL, 1);
3498 if (r)
3499 return r;
3500
3501 for (i = 0; i < 6; i++) {
3502 int rotated = (i + 4) % 6;
3503 int offset_reg = i / 3;
3504 int offset_chan = i % 3;
3505 int rotated_offset_reg = rotated / 3;
3506 int rotated_offset_chan = rotated % 3;
3507
3508 if (offset_reg == 0 && offset_chan == 2)
3509 offset_chan = 3;
3510 if (rotated_offset_reg == 0 && rotated_offset_chan == 2)
3511 rotated_offset_chan = 3;
3512
3513 r = single_alu_op3(&ctx, ALU_OP3_CNDE_INT,
3514 ctx.gs_rotated_input[offset_reg], offset_chan,
3515 ctx.gs_rotated_input[0], 2,
3516 offset_reg, offset_chan,
3517 rotated_offset_reg, rotated_offset_chan);
3518 if (r)
3519 return r;
3520 }
3521 }
3522 }
3523
3524 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3525 r600_fetch_tess_io_info(&ctx);
3526
3527 if (shader->two_side && ctx.colors_used) {
3528 if ((r = process_twoside_color_inputs(&ctx)))
3529 return r;
3530 }
3531
3532 tgsi_parse_init(&ctx.parse, tokens);
3533 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
3534 tgsi_parse_token(&ctx.parse);
3535 switch (ctx.parse.FullToken.Token.Type) {
3536 case TGSI_TOKEN_TYPE_INSTRUCTION:
3537 r = tgsi_is_supported(&ctx);
3538 if (r)
3539 goto out_err;
3540 ctx.max_driver_temp_used = 0;
3541 /* reserve first tmp for everyone */
3542 r600_get_temp(&ctx);
3543
3544 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
3545 if ((r = tgsi_split_constant(&ctx)))
3546 goto out_err;
3547 if ((r = tgsi_split_literal_constant(&ctx)))
3548 goto out_err;
3549 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3550 if ((r = tgsi_split_gs_inputs(&ctx)))
3551 goto out_err;
3552 } else if (lds_inputs) {
3553 if ((r = tgsi_split_lds_inputs(&ctx)))
3554 goto out_err;
3555 }
3556 if (ctx.bc->chip_class == CAYMAN)
3557 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
3558 else if (ctx.bc->chip_class >= EVERGREEN)
3559 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
3560 else
3561 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
3562 r = ctx.inst_info->process(&ctx);
3563 if (r)
3564 goto out_err;
3565
3566 if (ctx.type == PIPE_SHADER_TESS_CTRL) {
3567 r = r600_store_tcs_output(&ctx);
3568 if (r)
3569 goto out_err;
3570 }
3571 break;
3572 default:
3573 break;
3574 }
3575 }
3576
3577 /* Reset the temporary register counter. */
3578 ctx.max_driver_temp_used = 0;
3579
3580 noutput = shader->noutput;
3581
3582 if (!ring_outputs && ctx.clip_vertex_write) {
3583 unsigned clipdist_temp[2];
3584
3585 clipdist_temp[0] = r600_get_temp(&ctx);
3586 clipdist_temp[1] = r600_get_temp(&ctx);
3587
3588 /* need to convert a clipvertex write into clipdistance writes and not export
3589 the clip vertex anymore */
3590
3591 memset(&shader->output[noutput], 0, 2*sizeof(struct r600_shader_io));
3592 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3593 shader->output[noutput].gpr = clipdist_temp[0];
3594 noutput++;
3595 shader->output[noutput].name = TGSI_SEMANTIC_CLIPDIST;
3596 shader->output[noutput].gpr = clipdist_temp[1];
3597 noutput++;
3598
3599 /* reset spi_sid for clipvertex output to avoid confusing spi */
3600 shader->output[ctx.cv_output].spi_sid = 0;
3601
3602 shader->clip_dist_write = 0xFF;
3603 shader->cc_dist_mask = 0xFF;
3604
3605 for (i = 0; i < 8; i++) {
3606 int oreg = i >> 2;
3607 int ochan = i & 3;
3608
3609 for (j = 0; j < 4; j++) {
3610 struct r600_bytecode_alu alu;
3611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
3612 alu.op = ALU_OP2_DOT4;
3613 alu.src[0].sel = shader->output[ctx.cv_output].gpr;
3614 alu.src[0].chan = j;
3615
3616 alu.src[1].sel = 512 + i;
3617 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
3618 alu.src[1].chan = j;
3619
3620 alu.dst.sel = clipdist_temp[oreg];
3621 alu.dst.chan = j;
3622 alu.dst.write = (j == ochan);
3623 if (j == 3)
3624 alu.last = 1;
3625 r = r600_bytecode_add_alu(ctx.bc, &alu);
3626 if (r)
3627 return r;
3628 }
3629 }
3630 }
3631
3632 /* Add stream outputs. */
3633 if (so.num_outputs) {
3634 bool emit = false;
3635 if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX)
3636 emit = true;
3637 if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL)
3638 emit = true;
3639 if (emit)
3640 emit_streamout(&ctx, &so, -1, NULL);
3641 }
3642 pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask;
3643 convert_edgeflag_to_int(&ctx);
3644
3645 if (ctx.type == PIPE_SHADER_TESS_CTRL)
3646 r600_emit_tess_factor(&ctx);
3647
3648 if (lds_outputs) {
3649 if (ctx.type == PIPE_SHADER_VERTEX) {
3650 if (ctx.shader->noutput)
3651 emit_lds_vs_writes(&ctx);
3652 }
3653 } else if (ring_outputs) {
3654 if (shader->vs_as_es || shader->tes_as_es) {
3655 ctx.gs_export_gpr_tregs[0] = r600_get_temp(&ctx);
3656 ctx.gs_export_gpr_tregs[1] = -1;
3657 ctx.gs_export_gpr_tregs[2] = -1;
3658 ctx.gs_export_gpr_tregs[3] = -1;
3659
3660 emit_gs_ring_writes(&ctx, &so, -1, FALSE);
3661 }
3662 } else {
3663 /* Export output */
3664 next_clip_base = shader->vs_out_misc_write ? 62 : 61;
3665
3666 for (i = 0, j = 0; i < noutput; i++, j++) {
3667 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3668 output[j].gpr = shader->output[i].gpr;
3669 output[j].elem_size = 3;
3670 output[j].swizzle_x = 0;
3671 output[j].swizzle_y = 1;
3672 output[j].swizzle_z = 2;
3673 output[j].swizzle_w = 3;
3674 output[j].burst_count = 1;
3675 output[j].type = 0xffffffff;
3676 output[j].op = CF_OP_EXPORT;
3677 switch (ctx.type) {
3678 case PIPE_SHADER_VERTEX:
3679 case PIPE_SHADER_TESS_EVAL:
3680 switch (shader->output[i].name) {
3681 case TGSI_SEMANTIC_POSITION:
3682 output[j].array_base = 60;
3683 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3684 pos_emitted = true;
3685 break;
3686
3687 case TGSI_SEMANTIC_PSIZE:
3688 output[j].array_base = 61;
3689 output[j].swizzle_y = 7;
3690 output[j].swizzle_z = 7;
3691 output[j].swizzle_w = 7;
3692 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3693 pos_emitted = true;
3694 break;
3695 case TGSI_SEMANTIC_EDGEFLAG:
3696 output[j].array_base = 61;
3697 output[j].swizzle_x = 7;
3698 output[j].swizzle_y = 0;
3699 output[j].swizzle_z = 7;
3700 output[j].swizzle_w = 7;
3701 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3702 pos_emitted = true;
3703 break;
3704 case TGSI_SEMANTIC_LAYER:
3705 /* spi_sid is 0 for outputs that are
3706 * not consumed by PS */
3707 if (shader->output[i].spi_sid) {
3708 output[j].array_base = next_param_base++;
3709 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3710 j++;
3711 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3712 }
3713 output[j].array_base = 61;
3714 output[j].swizzle_x = 7;
3715 output[j].swizzle_y = 7;
3716 output[j].swizzle_z = 0;
3717 output[j].swizzle_w = 7;
3718 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3719 pos_emitted = true;
3720 break;
3721 case TGSI_SEMANTIC_VIEWPORT_INDEX:
3722 /* spi_sid is 0 for outputs that are
3723 * not consumed by PS */
3724 if (shader->output[i].spi_sid) {
3725 output[j].array_base = next_param_base++;
3726 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3727 j++;
3728 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3729 }
3730 output[j].array_base = 61;
3731 output[j].swizzle_x = 7;
3732 output[j].swizzle_y = 7;
3733 output[j].swizzle_z = 7;
3734 output[j].swizzle_w = 0;
3735 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3736 pos_emitted = true;
3737 break;
3738 case TGSI_SEMANTIC_CLIPVERTEX:
3739 j--;
3740 break;
3741 case TGSI_SEMANTIC_CLIPDIST:
3742 output[j].array_base = next_clip_base++;
3743 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3744 pos_emitted = true;
3745 /* spi_sid is 0 for clipdistance outputs that were generated
3746 * for clipvertex - we don't need to pass them to PS */
3747 if (shader->output[i].spi_sid) {
3748 j++;
3749 /* duplicate it as PARAM to pass to the pixel shader */
3750 memcpy(&output[j], &output[j-1], sizeof(struct r600_bytecode_output));
3751 output[j].array_base = next_param_base++;
3752 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3753 }
3754 break;
3755 case TGSI_SEMANTIC_FOG:
3756 output[j].swizzle_y = 4; /* 0 */
3757 output[j].swizzle_z = 4; /* 0 */
3758 output[j].swizzle_w = 5; /* 1 */
3759 break;
3760 case TGSI_SEMANTIC_PRIMID:
3761 output[j].swizzle_x = 2;
3762 output[j].swizzle_y = 4; /* 0 */
3763 output[j].swizzle_z = 4; /* 0 */
3764 output[j].swizzle_w = 4; /* 0 */
3765 break;
3766 }
3767
3768 break;
3769 case PIPE_SHADER_FRAGMENT:
3770 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
3771 /* never export more colors than the number of CBs */
3772 if (shader->output[i].sid >= max_color_exports) {
3773 /* skip export */
3774 j--;
3775 continue;
3776 }
3777 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3778 output[j].array_base = shader->output[i].sid;
3779 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3780 shader->nr_ps_color_exports++;
3781 if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
3782 for (k = 1; k < max_color_exports; k++) {
3783 j++;
3784 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3785 output[j].gpr = shader->output[i].gpr;
3786 output[j].elem_size = 3;
3787 output[j].swizzle_x = 0;
3788 output[j].swizzle_y = 1;
3789 output[j].swizzle_z = 2;
3790 output[j].swizzle_w = key.ps.alpha_to_one ? 5 : 3;
3791 output[j].burst_count = 1;
3792 output[j].array_base = k;
3793 output[j].op = CF_OP_EXPORT;
3794 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3795 shader->nr_ps_color_exports++;
3796 }
3797 }
3798 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
3799 output[j].array_base = 61;
3800 output[j].swizzle_x = 2;
3801 output[j].swizzle_y = 7;
3802 output[j].swizzle_z = output[j].swizzle_w = 7;
3803 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3804 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
3805 output[j].array_base = 61;
3806 output[j].swizzle_x = 7;
3807 output[j].swizzle_y = 1;
3808 output[j].swizzle_z = output[j].swizzle_w = 7;
3809 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3810 } else if (shader->output[i].name == TGSI_SEMANTIC_SAMPLEMASK) {
3811 output[j].array_base = 61;
3812 output[j].swizzle_x = 7;
3813 output[j].swizzle_y = 7;
3814 output[j].swizzle_z = 0;
3815 output[j].swizzle_w = 7;
3816 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3817 } else {
3818 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
3819 r = -EINVAL;
3820 goto out_err;
3821 }
3822 break;
3823 case PIPE_SHADER_TESS_CTRL:
3824 break;
3825 default:
3826 R600_ERR("unsupported processor type %d\n", ctx.type);
3827 r = -EINVAL;
3828 goto out_err;
3829 }
3830
3831 if (output[j].type == 0xffffffff) {
3832 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3833 output[j].array_base = next_param_base++;
3834 }
3835 }
3836
3837 /* add fake position export */
3838 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) {
3839 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3840 output[j].gpr = 0;
3841 output[j].elem_size = 3;
3842 output[j].swizzle_x = 7;
3843 output[j].swizzle_y = 7;
3844 output[j].swizzle_z = 7;
3845 output[j].swizzle_w = 7;
3846 output[j].burst_count = 1;
3847 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
3848 output[j].array_base = 60;
3849 output[j].op = CF_OP_EXPORT;
3850 j++;
3851 }
3852
3853 /* add fake param output for vertex shader if no param is exported */
3854 if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) {
3855 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3856 output[j].gpr = 0;
3857 output[j].elem_size = 3;
3858 output[j].swizzle_x = 7;
3859 output[j].swizzle_y = 7;
3860 output[j].swizzle_z = 7;
3861 output[j].swizzle_w = 7;
3862 output[j].burst_count = 1;
3863 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
3864 output[j].array_base = 0;
3865 output[j].op = CF_OP_EXPORT;
3866 j++;
3867 }
3868
3869 /* add fake pixel export */
3870 if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) {
3871 memset(&output[j], 0, sizeof(struct r600_bytecode_output));
3872 output[j].gpr = 0;
3873 output[j].elem_size = 3;
3874 output[j].swizzle_x = 7;
3875 output[j].swizzle_y = 7;
3876 output[j].swizzle_z = 7;
3877 output[j].swizzle_w = 7;
3878 output[j].burst_count = 1;
3879 output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
3880 output[j].array_base = 0;
3881 output[j].op = CF_OP_EXPORT;
3882 j++;
3883 shader->nr_ps_color_exports++;
3884 }
3885
3886 noutput = j;
3887
3888 /* set export done on last export of each type */
3889 for (k = noutput - 1, output_done = 0; k >= 0; k--) {
3890 if (!(output_done & (1 << output[k].type))) {
3891 output_done |= (1 << output[k].type);
3892 output[k].op = CF_OP_EXPORT_DONE;
3893 }
3894 }
3895 /* add output to bytecode */
3896 for (i = 0; i < noutput; i++) {
3897 r = r600_bytecode_add_output(ctx.bc, &output[i]);
3898 if (r)
3899 goto out_err;
3900 }
3901 }
3902
3903 /* add program end */
3904 if (ctx.bc->chip_class == CAYMAN)
3905 cm_bytecode_add_cf_end(ctx.bc);
3906 else {
3907 const struct cf_op_info *last = NULL;
3908
3909 if (ctx.bc->cf_last)
3910 last = r600_isa_cf(ctx.bc->cf_last->op);
3911
3912 /* alu clause instructions don't have EOP bit, so add NOP */
3913 if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
3914 r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
3915
3916 ctx.bc->cf_last->end_of_program = 1;
3917 }
3918
3919 /* check GPR limit - we have 124 = 128 - 4
3920 * (4 are reserved as alu clause temporary registers) */
3921 if (ctx.bc->ngpr > 124) {
3922 R600_ERR("GPR limit exceeded - shader requires %d registers\n", ctx.bc->ngpr);
3923 r = -ENOMEM;
3924 goto out_err;
3925 }
3926
3927 if (ctx.type == PIPE_SHADER_GEOMETRY) {
3928 if ((r = generate_gs_copy_shader(rctx, pipeshader, &so)))
3929 return r;
3930 }
3931
3932 free(ctx.literals);
3933 tgsi_parse_free(&ctx.parse);
3934 return 0;
3935 out_err:
3936 free(ctx.literals);
3937 tgsi_parse_free(&ctx.parse);
3938 return r;
3939 }
3940
3941 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
3942 {
3943 const unsigned tgsi_opcode =
3944 ctx->parse.FullToken.FullInstruction.Instruction.Opcode;
3945 R600_ERR("%s tgsi opcode unsupported\n",
3946 tgsi_get_opcode_name(tgsi_opcode));
3947 return -EINVAL;
3948 }
3949
3950 static int tgsi_end(struct r600_shader_ctx *ctx UNUSED)
3951 {
3952 return 0;
3953 }
3954
3955 static void r600_bytecode_src(struct r600_bytecode_alu_src *bc_src,
3956 const struct r600_shader_src *shader_src,
3957 unsigned chan)
3958 {
3959 bc_src->sel = shader_src->sel;
3960 bc_src->chan = shader_src->swizzle[chan];
3961 bc_src->neg = shader_src->neg;
3962 bc_src->abs = shader_src->abs;
3963 bc_src->rel = shader_src->rel;
3964 bc_src->value = shader_src->value[bc_src->chan];
3965 bc_src->kc_bank = shader_src->kc_bank;
3966 bc_src->kc_rel = shader_src->kc_rel;
3967 }
3968
3969 static void r600_bytecode_src_set_abs(struct r600_bytecode_alu_src *bc_src)
3970 {
3971 bc_src->abs = 1;
3972 bc_src->neg = 0;
3973 }
3974
3975 static void r600_bytecode_src_toggle_neg(struct r600_bytecode_alu_src *bc_src)
3976 {
3977 bc_src->neg = !bc_src->neg;
3978 }
3979
3980 static void tgsi_dst(struct r600_shader_ctx *ctx,
3981 const struct tgsi_full_dst_register *tgsi_dst,
3982 unsigned swizzle,
3983 struct r600_bytecode_alu_dst *r600_dst)
3984 {
3985 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3986
3987 r600_dst->sel = tgsi_dst->Register.Index;
3988 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
3989 r600_dst->chan = swizzle;
3990 r600_dst->write = 1;
3991 if (inst->Instruction.Saturate) {
3992 r600_dst->clamp = 1;
3993 }
3994 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
3995 if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) {
3996 return;
3997 }
3998 }
3999 if (tgsi_dst->Register.Indirect)
4000 r600_dst->rel = V_SQ_REL_RELATIVE;
4001
4002 }
4003
4004 static int tgsi_op2_64_params(struct r600_shader_ctx *ctx, bool singledest, bool swap, int dest_temp, int op_override)
4005 {
4006 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4007 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4008 struct r600_bytecode_alu alu;
4009 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4010 int use_tmp = 0;
4011 int swizzle_x = inst->Src[0].Register.SwizzleX;
4012
4013 if (singledest) {
4014 switch (write_mask) {
4015 case 0x1:
4016 if (swizzle_x == 2) {
4017 write_mask = 0xc;
4018 use_tmp = 3;
4019 } else
4020 write_mask = 0x3;
4021 break;
4022 case 0x2:
4023 if (swizzle_x == 2) {
4024 write_mask = 0xc;
4025 use_tmp = 3;
4026 } else {
4027 write_mask = 0x3;
4028 use_tmp = 1;
4029 }
4030 break;
4031 case 0x4:
4032 if (swizzle_x == 0) {
4033 write_mask = 0x3;
4034 use_tmp = 1;
4035 } else
4036 write_mask = 0xc;
4037 break;
4038 case 0x8:
4039 if (swizzle_x == 0) {
4040 write_mask = 0x3;
4041 use_tmp = 1;
4042 } else {
4043 write_mask = 0xc;
4044 use_tmp = 3;
4045 }
4046 break;
4047 }
4048 }
4049
4050 lasti = tgsi_last_instruction(write_mask);
4051 for (i = 0; i <= lasti; i++) {
4052
4053 if (!(write_mask & (1 << i)))
4054 continue;
4055
4056 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4057
4058 if (singledest) {
4059 if (use_tmp || dest_temp) {
4060 alu.dst.sel = use_tmp ? ctx->temp_reg : dest_temp;
4061 alu.dst.chan = i;
4062 alu.dst.write = 1;
4063 } else {
4064 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4065 }
4066 if (i == 1 || i == 3)
4067 alu.dst.write = 0;
4068 } else
4069 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4070
4071 alu.op = op_override ? op_override : ctx->inst_info->op;
4072 if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DABS) {
4073 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4074 } else if (!swap) {
4075 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4076 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4077 }
4078 } else {
4079 r600_bytecode_src(&alu.src[0], &ctx->src[1], fp64_switch(i));
4080 r600_bytecode_src(&alu.src[1], &ctx->src[0], fp64_switch(i));
4081 }
4082
4083 /* handle some special cases */
4084 if (i == 1 || i == 3) {
4085 switch (ctx->parse.FullToken.FullInstruction.Instruction.Opcode) {
4086 case TGSI_OPCODE_DABS:
4087 r600_bytecode_src_set_abs(&alu.src[0]);
4088 break;
4089 default:
4090 break;
4091 }
4092 }
4093 if (i == lasti) {
4094 alu.last = 1;
4095 }
4096 r = r600_bytecode_add_alu(ctx->bc, &alu);
4097 if (r)
4098 return r;
4099 }
4100
4101 if (use_tmp) {
4102 write_mask = inst->Dst[0].Register.WriteMask;
4103
4104 lasti = tgsi_last_instruction(write_mask);
4105 /* move result from temp to dst */
4106 for (i = 0; i <= lasti; i++) {
4107 if (!(write_mask & (1 << i)))
4108 continue;
4109
4110 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4111 alu.op = ALU_OP1_MOV;
4112
4113 if (dest_temp) {
4114 alu.dst.sel = dest_temp;
4115 alu.dst.chan = i;
4116 alu.dst.write = 1;
4117 } else
4118 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4119 alu.src[0].sel = ctx->temp_reg;
4120 alu.src[0].chan = use_tmp - 1;
4121 alu.last = (i == lasti);
4122
4123 r = r600_bytecode_add_alu(ctx->bc, &alu);
4124 if (r)
4125 return r;
4126 }
4127 }
4128 return 0;
4129 }
4130
4131 static int tgsi_op2_64(struct r600_shader_ctx *ctx)
4132 {
4133 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4134 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4135 /* confirm writemasking */
4136 if ((write_mask & 0x3) != 0x3 &&
4137 (write_mask & 0xc) != 0xc) {
4138 fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", write_mask);
4139 return -1;
4140 }
4141 return tgsi_op2_64_params(ctx, false, false, 0, 0);
4142 }
4143
4144 static int tgsi_op2_64_single_dest(struct r600_shader_ctx *ctx)
4145 {
4146 return tgsi_op2_64_params(ctx, true, false, 0, 0);
4147 }
4148
4149 static int tgsi_op2_64_single_dest_s(struct r600_shader_ctx *ctx)
4150 {
4151 return tgsi_op2_64_params(ctx, true, true, 0, 0);
4152 }
4153
4154 static int tgsi_op3_64(struct r600_shader_ctx *ctx)
4155 {
4156 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4157 struct r600_bytecode_alu alu;
4158 int i, j, r;
4159 int lasti = 3;
4160 int tmp = r600_get_temp(ctx);
4161
4162 for (i = 0; i < lasti + 1; i++) {
4163
4164 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4165 alu.op = ctx->inst_info->op;
4166 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4167 r600_bytecode_src(&alu.src[j], &ctx->src[j], i == 3 ? 0 : 1);
4168 }
4169
4170 if (inst->Dst[0].Register.WriteMask & (1 << i))
4171 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4172 else
4173 alu.dst.sel = tmp;
4174
4175 alu.dst.chan = i;
4176 alu.is_op3 = 1;
4177 if (i == lasti) {
4178 alu.last = 1;
4179 }
4180 r = r600_bytecode_add_alu(ctx->bc, &alu);
4181 if (r)
4182 return r;
4183 }
4184 return 0;
4185 }
4186
4187 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
4188 {
4189 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4190 struct r600_bytecode_alu alu;
4191 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4192 int i, j, r, lasti = tgsi_last_instruction(write_mask);
4193 /* use temp register if trans_only and more than one dst component */
4194 int use_tmp = trans_only && (write_mask ^ (1 << lasti));
4195 unsigned op = ctx->inst_info->op;
4196
4197 if (op == ALU_OP2_MUL_IEEE &&
4198 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
4199 op = ALU_OP2_MUL;
4200
4201 for (i = 0; i <= lasti; i++) {
4202 if (!(write_mask & (1 << i)))
4203 continue;
4204
4205 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4206 if (use_tmp) {
4207 alu.dst.sel = ctx->temp_reg;
4208 alu.dst.chan = i;
4209 alu.dst.write = 1;
4210 } else
4211 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4212
4213 alu.op = op;
4214 if (!swap) {
4215 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4216 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
4217 }
4218 } else {
4219 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
4220 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4221 }
4222 if (i == lasti || trans_only) {
4223 alu.last = 1;
4224 }
4225 r = r600_bytecode_add_alu(ctx->bc, &alu);
4226 if (r)
4227 return r;
4228 }
4229
4230 if (use_tmp) {
4231 /* move result from temp to dst */
4232 for (i = 0; i <= lasti; i++) {
4233 if (!(write_mask & (1 << i)))
4234 continue;
4235
4236 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4237 alu.op = ALU_OP1_MOV;
4238 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4239 alu.src[0].sel = ctx->temp_reg;
4240 alu.src[0].chan = i;
4241 alu.last = (i == lasti);
4242
4243 r = r600_bytecode_add_alu(ctx->bc, &alu);
4244 if (r)
4245 return r;
4246 }
4247 }
4248 return 0;
4249 }
4250
4251 static int tgsi_op2(struct r600_shader_ctx *ctx)
4252 {
4253 return tgsi_op2_s(ctx, 0, 0);
4254 }
4255
4256 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
4257 {
4258 return tgsi_op2_s(ctx, 1, 0);
4259 }
4260
4261 static int tgsi_op2_trans(struct r600_shader_ctx *ctx)
4262 {
4263 return tgsi_op2_s(ctx, 0, 1);
4264 }
4265
4266 static int tgsi_ineg(struct r600_shader_ctx *ctx)
4267 {
4268 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4269 struct r600_bytecode_alu alu;
4270 int i, r;
4271 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4272
4273 for (i = 0; i < lasti + 1; i++) {
4274
4275 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4276 continue;
4277 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4278 alu.op = ctx->inst_info->op;
4279
4280 alu.src[0].sel = V_SQ_ALU_SRC_0;
4281
4282 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4283
4284 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4285
4286 if (i == lasti) {
4287 alu.last = 1;
4288 }
4289 r = r600_bytecode_add_alu(ctx->bc, &alu);
4290 if (r)
4291 return r;
4292 }
4293 return 0;
4294
4295 }
4296
4297 static int tgsi_dneg(struct r600_shader_ctx *ctx)
4298 {
4299 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4300 struct r600_bytecode_alu alu;
4301 int i, r;
4302 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4303
4304 for (i = 0; i < lasti + 1; i++) {
4305
4306 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4307 continue;
4308 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4309 alu.op = ALU_OP1_MOV;
4310
4311 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4312
4313 if (i == 1 || i == 3)
4314 r600_bytecode_src_toggle_neg(&alu.src[0]);
4315 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4316
4317 if (i == lasti) {
4318 alu.last = 1;
4319 }
4320 r = r600_bytecode_add_alu(ctx->bc, &alu);
4321 if (r)
4322 return r;
4323 }
4324 return 0;
4325
4326 }
4327
4328 static int tgsi_dfracexp(struct r600_shader_ctx *ctx)
4329 {
4330 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4331 struct r600_bytecode_alu alu;
4332 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4333 int i, j, r;
4334
4335 for (i = 0; i <= 3; i++) {
4336 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4337 alu.op = ctx->inst_info->op;
4338
4339 alu.dst.sel = ctx->temp_reg;
4340 alu.dst.chan = i;
4341 alu.dst.write = 1;
4342 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4343 r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i));
4344 }
4345
4346 if (i == 3)
4347 alu.last = 1;
4348
4349 r = r600_bytecode_add_alu(ctx->bc, &alu);
4350 if (r)
4351 return r;
4352 }
4353
4354 /* Replicate significand result across channels. */
4355 for (i = 0; i <= 3; i++) {
4356 if (!(write_mask & (1 << i)))
4357 continue;
4358
4359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4360 alu.op = ALU_OP1_MOV;
4361 alu.src[0].chan = (i & 1) + 2;
4362 alu.src[0].sel = ctx->temp_reg;
4363
4364 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4365 alu.dst.write = 1;
4366 alu.last = 1;
4367 r = r600_bytecode_add_alu(ctx->bc, &alu);
4368 if (r)
4369 return r;
4370 }
4371
4372 for (i = 0; i <= 3; i++) {
4373 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4374 /* MOV third channels to writemask dst1 */
4375 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4376 alu.op = ALU_OP1_MOV;
4377 alu.src[0].chan = 1;
4378 alu.src[0].sel = ctx->temp_reg;
4379
4380 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4381 alu.last = 1;
4382 r = r600_bytecode_add_alu(ctx->bc, &alu);
4383 if (r)
4384 return r;
4385 break;
4386 }
4387 }
4388 return 0;
4389 }
4390
4391
4392 static int egcm_int_to_double(struct r600_shader_ctx *ctx)
4393 {
4394 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4395 struct r600_bytecode_alu alu;
4396 int i, r;
4397 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4398
4399 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4400 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
4401
4402 for (i = 0; i <= (lasti+1)/2; i++) {
4403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4404 alu.op = ctx->inst_info->op;
4405
4406 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
4407 alu.dst.sel = ctx->temp_reg;
4408 alu.dst.chan = i;
4409 alu.dst.write = 1;
4410 alu.last = 1;
4411
4412 r = r600_bytecode_add_alu(ctx->bc, &alu);
4413 if (r)
4414 return r;
4415 }
4416
4417 for (i = 0; i <= lasti; i++) {
4418 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4419 alu.op = ALU_OP1_FLT32_TO_FLT64;
4420
4421 alu.src[0].chan = i/2;
4422 if (i%2 == 0)
4423 alu.src[0].sel = ctx->temp_reg;
4424 else {
4425 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
4426 alu.src[0].value = 0x0;
4427 }
4428 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4429 alu.last = i == lasti;
4430
4431 r = r600_bytecode_add_alu(ctx->bc, &alu);
4432 if (r)
4433 return r;
4434 }
4435
4436 return 0;
4437 }
4438
4439 static int egcm_double_to_int(struct r600_shader_ctx *ctx)
4440 {
4441 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4442 struct r600_bytecode_alu alu;
4443 int i, r;
4444 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4445 int treg = r600_get_temp(ctx);
4446 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
4447 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
4448
4449 /* do a 64->32 into a temp register */
4450 r = tgsi_op2_64_params(ctx, true, false, treg, ALU_OP1_FLT64_TO_FLT32);
4451 if (r)
4452 return r;
4453
4454 for (i = 0; i <= lasti; i++) {
4455 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4456 continue;
4457 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4458 alu.op = ctx->inst_info->op;
4459
4460 alu.src[0].chan = i;
4461 alu.src[0].sel = treg;
4462 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4463 alu.last = (i == lasti);
4464
4465 r = r600_bytecode_add_alu(ctx->bc, &alu);
4466 if (r)
4467 return r;
4468 }
4469
4470 return 0;
4471 }
4472
4473 static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
4474 unsigned op,
4475 int dst_reg,
4476 struct r600_shader_src *src,
4477 bool abs)
4478 {
4479 struct r600_bytecode_alu alu;
4480 const int last_slot = 3;
4481 int r;
4482
4483 /* these have to write the result to X/Y by the looks of it */
4484 for (int i = 0 ; i < last_slot; i++) {
4485 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4486 alu.op = op;
4487
4488 r600_bytecode_src(&alu.src[0], src, 1);
4489 r600_bytecode_src(&alu.src[1], src, 0);
4490
4491 if (abs)
4492 r600_bytecode_src_set_abs(&alu.src[1]);
4493
4494 alu.dst.sel = dst_reg;
4495 alu.dst.chan = i;
4496 alu.dst.write = (i == 0 || i == 1);
4497
4498 if (bc->chip_class != CAYMAN || i == last_slot - 1)
4499 alu.last = 1;
4500 r = r600_bytecode_add_alu(bc, &alu);
4501 if (r)
4502 return r;
4503 }
4504
4505 return 0;
4506 }
4507
4508 static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
4509 {
4510 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4511 int i, r;
4512 struct r600_bytecode_alu alu;
4513 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4514 int t1 = ctx->temp_reg;
4515
4516 /* should only be one src regs */
4517 assert(inst->Instruction.NumSrcRegs == 1);
4518
4519 /* only support one double at a time */
4520 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4521 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4522
4523 r = cayman_emit_unary_double_raw(
4524 ctx->bc, ctx->inst_info->op, t1,
4525 &ctx->src[0],
4526 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DRSQ ||
4527 ctx->parse.FullToken.FullInstruction.Instruction.Opcode == TGSI_OPCODE_DSQRT);
4528 if (r)
4529 return r;
4530
4531 for (i = 0 ; i <= lasti; i++) {
4532 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4533 continue;
4534 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4535 alu.op = ALU_OP1_MOV;
4536 alu.src[0].sel = t1;
4537 alu.src[0].chan = (i == 0 || i == 2) ? 0 : 1;
4538 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4539 alu.dst.write = 1;
4540 if (i == lasti)
4541 alu.last = 1;
4542 r = r600_bytecode_add_alu(ctx->bc, &alu);
4543 if (r)
4544 return r;
4545 }
4546 return 0;
4547 }
4548
4549 static int cayman_emit_float_instr(struct r600_shader_ctx *ctx)
4550 {
4551 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4552 int i, j, r;
4553 struct r600_bytecode_alu alu;
4554 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4555
4556 for (i = 0 ; i < last_slot; i++) {
4557 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4558 alu.op = ctx->inst_info->op;
4559 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4560 r600_bytecode_src(&alu.src[j], &ctx->src[j], 0);
4561
4562 /* RSQ should take the absolute value of src */
4563 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
4564 r600_bytecode_src_set_abs(&alu.src[j]);
4565 }
4566 }
4567 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4568 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4569
4570 if (i == last_slot - 1)
4571 alu.last = 1;
4572 r = r600_bytecode_add_alu(ctx->bc, &alu);
4573 if (r)
4574 return r;
4575 }
4576 return 0;
4577 }
4578
4579 static int cayman_mul_int_instr(struct r600_shader_ctx *ctx)
4580 {
4581 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4582 int i, j, k, r;
4583 struct r600_bytecode_alu alu;
4584 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4585 int t1 = ctx->temp_reg;
4586
4587 for (k = 0; k <= lasti; k++) {
4588 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
4589 continue;
4590
4591 for (i = 0 ; i < 4; i++) {
4592 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4593 alu.op = ctx->inst_info->op;
4594 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4595 r600_bytecode_src(&alu.src[j], &ctx->src[j], k);
4596 }
4597 alu.dst.sel = t1;
4598 alu.dst.chan = i;
4599 alu.dst.write = (i == k);
4600 if (i == 3)
4601 alu.last = 1;
4602 r = r600_bytecode_add_alu(ctx->bc, &alu);
4603 if (r)
4604 return r;
4605 }
4606 }
4607
4608 for (i = 0 ; i <= lasti; i++) {
4609 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4610 continue;
4611 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4612 alu.op = ALU_OP1_MOV;
4613 alu.src[0].sel = t1;
4614 alu.src[0].chan = i;
4615 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4616 alu.dst.write = 1;
4617 if (i == lasti)
4618 alu.last = 1;
4619 r = r600_bytecode_add_alu(ctx->bc, &alu);
4620 if (r)
4621 return r;
4622 }
4623
4624 return 0;
4625 }
4626
4627
4628 static int cayman_mul_double_instr(struct r600_shader_ctx *ctx)
4629 {
4630 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4631 int i, j, k, r;
4632 struct r600_bytecode_alu alu;
4633 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4634 int t1 = ctx->temp_reg;
4635
4636 /* t1 would get overwritten below if we actually tried to
4637 * multiply two pairs of doubles at a time. */
4638 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4639 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4640
4641 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4642
4643 for (i = 0; i < 4; i++) {
4644 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4645 alu.op = ctx->inst_info->op;
4646 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4647 r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + ((i == 3) ? 0 : 1));
4648 }
4649 alu.dst.sel = t1;
4650 alu.dst.chan = i;
4651 alu.dst.write = 1;
4652 if (i == 3)
4653 alu.last = 1;
4654 r = r600_bytecode_add_alu(ctx->bc, &alu);
4655 if (r)
4656 return r;
4657 }
4658
4659 for (i = 0; i <= lasti; i++) {
4660 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4661 continue;
4662 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4663 alu.op = ALU_OP1_MOV;
4664 alu.src[0].sel = t1;
4665 alu.src[0].chan = i;
4666 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4667 alu.dst.write = 1;
4668 if (i == lasti)
4669 alu.last = 1;
4670 r = r600_bytecode_add_alu(ctx->bc, &alu);
4671 if (r)
4672 return r;
4673 }
4674
4675 return 0;
4676 }
4677
4678 /*
4679 * Emit RECIP_64 + MUL_64 to implement division.
4680 */
4681 static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
4682 {
4683 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4684 int r;
4685 struct r600_bytecode_alu alu;
4686 int t1 = ctx->temp_reg;
4687 int k;
4688
4689 /* Only support one double at a time. This is the same constraint as
4690 * in DMUL lowering. */
4691 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
4692 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
4693
4694 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
4695
4696 r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, &ctx->src[1], false);
4697 if (r)
4698 return r;
4699
4700 for (int i = 0; i < 4; i++) {
4701 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4702 alu.op = ALU_OP2_MUL_64;
4703
4704 r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) ? 0 : 1));
4705
4706 alu.src[1].sel = t1;
4707 alu.src[1].chan = (i == 3) ? 0 : 1;
4708
4709 alu.dst.sel = t1;
4710 alu.dst.chan = i;
4711 alu.dst.write = 1;
4712 if (i == 3)
4713 alu.last = 1;
4714 r = r600_bytecode_add_alu(ctx->bc, &alu);
4715 if (r)
4716 return r;
4717 }
4718
4719 for (int i = 0; i < 2; i++) {
4720 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4721 alu.op = ALU_OP1_MOV;
4722 alu.src[0].sel = t1;
4723 alu.src[0].chan = i;
4724 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
4725 alu.dst.write = 1;
4726 if (i == 1)
4727 alu.last = 1;
4728 r = r600_bytecode_add_alu(ctx->bc, &alu);
4729 if (r)
4730 return r;
4731 }
4732 return 0;
4733 }
4734
4735 /*
4736 * r600 - trunc to -PI..PI range
4737 * r700 - normalize by dividing by 2PI
4738 * see fdo bug 27901
4739 */
4740 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
4741 {
4742 int r;
4743 struct r600_bytecode_alu alu;
4744
4745 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4746 alu.op = ALU_OP3_MULADD;
4747 alu.is_op3 = 1;
4748
4749 alu.dst.chan = 0;
4750 alu.dst.sel = ctx->temp_reg;
4751 alu.dst.write = 1;
4752
4753 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
4754
4755 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4756 alu.src[1].chan = 0;
4757 alu.src[1].value = u_bitcast_f2u(0.5f * M_1_PI);
4758 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4759 alu.src[2].chan = 0;
4760 alu.last = 1;
4761 r = r600_bytecode_add_alu(ctx->bc, &alu);
4762 if (r)
4763 return r;
4764
4765 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4766 alu.op = ALU_OP1_FRACT;
4767
4768 alu.dst.chan = 0;
4769 alu.dst.sel = ctx->temp_reg;
4770 alu.dst.write = 1;
4771
4772 alu.src[0].sel = ctx->temp_reg;
4773 alu.src[0].chan = 0;
4774 alu.last = 1;
4775 r = r600_bytecode_add_alu(ctx->bc, &alu);
4776 if (r)
4777 return r;
4778
4779 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4780 alu.op = ALU_OP3_MULADD;
4781 alu.is_op3 = 1;
4782
4783 alu.dst.chan = 0;
4784 alu.dst.sel = ctx->temp_reg;
4785 alu.dst.write = 1;
4786
4787 alu.src[0].sel = ctx->temp_reg;
4788 alu.src[0].chan = 0;
4789
4790 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
4791 alu.src[1].chan = 0;
4792 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
4793 alu.src[2].chan = 0;
4794
4795 if (ctx->bc->chip_class == R600) {
4796 alu.src[1].value = u_bitcast_f2u(2.0f * M_PI);
4797 alu.src[2].value = u_bitcast_f2u(-M_PI);
4798 } else {
4799 alu.src[1].sel = V_SQ_ALU_SRC_1;
4800 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
4801 alu.src[2].neg = 1;
4802 }
4803
4804 alu.last = 1;
4805 r = r600_bytecode_add_alu(ctx->bc, &alu);
4806 if (r)
4807 return r;
4808 return 0;
4809 }
4810
4811 static int cayman_trig(struct r600_shader_ctx *ctx)
4812 {
4813 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4814 struct r600_bytecode_alu alu;
4815 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
4816 int i, r;
4817
4818 r = tgsi_setup_trig(ctx);
4819 if (r)
4820 return r;
4821
4822
4823 for (i = 0; i < last_slot; i++) {
4824 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4825 alu.op = ctx->inst_info->op;
4826 alu.dst.chan = i;
4827
4828 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4829 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
4830
4831 alu.src[0].sel = ctx->temp_reg;
4832 alu.src[0].chan = 0;
4833 if (i == last_slot - 1)
4834 alu.last = 1;
4835 r = r600_bytecode_add_alu(ctx->bc, &alu);
4836 if (r)
4837 return r;
4838 }
4839 return 0;
4840 }
4841
4842 static int tgsi_trig(struct r600_shader_ctx *ctx)
4843 {
4844 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4845 struct r600_bytecode_alu alu;
4846 int i, r;
4847 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4848
4849 r = tgsi_setup_trig(ctx);
4850 if (r)
4851 return r;
4852
4853 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4854 alu.op = ctx->inst_info->op;
4855 alu.dst.chan = 0;
4856 alu.dst.sel = ctx->temp_reg;
4857 alu.dst.write = 1;
4858
4859 alu.src[0].sel = ctx->temp_reg;
4860 alu.src[0].chan = 0;
4861 alu.last = 1;
4862 r = r600_bytecode_add_alu(ctx->bc, &alu);
4863 if (r)
4864 return r;
4865
4866 /* replicate result */
4867 for (i = 0; i < lasti + 1; i++) {
4868 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4869 continue;
4870
4871 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4872 alu.op = ALU_OP1_MOV;
4873
4874 alu.src[0].sel = ctx->temp_reg;
4875 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4876 if (i == lasti)
4877 alu.last = 1;
4878 r = r600_bytecode_add_alu(ctx->bc, &alu);
4879 if (r)
4880 return r;
4881 }
4882 return 0;
4883 }
4884
4885 static int tgsi_kill(struct r600_shader_ctx *ctx)
4886 {
4887 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4888 struct r600_bytecode_alu alu;
4889 int i, r;
4890
4891 for (i = 0; i < 4; i++) {
4892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4893 alu.op = ctx->inst_info->op;
4894
4895 alu.dst.chan = i;
4896
4897 alu.src[0].sel = V_SQ_ALU_SRC_0;
4898
4899 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
4900 alu.src[1].sel = V_SQ_ALU_SRC_1;
4901 alu.src[1].neg = 1;
4902 } else {
4903 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
4904 }
4905 if (i == 3) {
4906 alu.last = 1;
4907 }
4908 r = r600_bytecode_add_alu(ctx->bc, &alu);
4909 if (r)
4910 return r;
4911 }
4912
4913 /* kill must be last in ALU */
4914 ctx->bc->force_add_cf = 1;
4915 ctx->shader->uses_kill = TRUE;
4916 return 0;
4917 }
4918
4919 static int tgsi_lit(struct r600_shader_ctx *ctx)
4920 {
4921 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4922 struct r600_bytecode_alu alu;
4923 int r;
4924
4925 /* tmp.x = max(src.y, 0.0) */
4926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4927 alu.op = ALU_OP2_MAX;
4928 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
4929 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
4930 alu.src[1].chan = 1;
4931
4932 alu.dst.sel = ctx->temp_reg;
4933 alu.dst.chan = 0;
4934 alu.dst.write = 1;
4935
4936 alu.last = 1;
4937 r = r600_bytecode_add_alu(ctx->bc, &alu);
4938 if (r)
4939 return r;
4940
4941 if (inst->Dst[0].Register.WriteMask & (1 << 2))
4942 {
4943 int chan;
4944 int sel;
4945 unsigned i;
4946
4947 if (ctx->bc->chip_class == CAYMAN) {
4948 for (i = 0; i < 3; i++) {
4949 /* tmp.z = log(tmp.x) */
4950 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4951 alu.op = ALU_OP1_LOG_CLAMPED;
4952 alu.src[0].sel = ctx->temp_reg;
4953 alu.src[0].chan = 0;
4954 alu.dst.sel = ctx->temp_reg;
4955 alu.dst.chan = i;
4956 if (i == 2) {
4957 alu.dst.write = 1;
4958 alu.last = 1;
4959 } else
4960 alu.dst.write = 0;
4961
4962 r = r600_bytecode_add_alu(ctx->bc, &alu);
4963 if (r)
4964 return r;
4965 }
4966 } else {
4967 /* tmp.z = log(tmp.x) */
4968 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4969 alu.op = ALU_OP1_LOG_CLAMPED;
4970 alu.src[0].sel = ctx->temp_reg;
4971 alu.src[0].chan = 0;
4972 alu.dst.sel = ctx->temp_reg;
4973 alu.dst.chan = 2;
4974 alu.dst.write = 1;
4975 alu.last = 1;
4976 r = r600_bytecode_add_alu(ctx->bc, &alu);
4977 if (r)
4978 return r;
4979 }
4980
4981 chan = alu.dst.chan;
4982 sel = alu.dst.sel;
4983
4984 /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
4985 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
4986 alu.op = ALU_OP3_MUL_LIT;
4987 alu.src[0].sel = sel;
4988 alu.src[0].chan = chan;
4989 r600_bytecode_src(&alu.src[1], &ctx->src[0], 3);
4990 r600_bytecode_src(&alu.src[2], &ctx->src[0], 0);
4991 alu.dst.sel = ctx->temp_reg;
4992 alu.dst.chan = 0;
4993 alu.dst.write = 1;
4994 alu.is_op3 = 1;
4995 alu.last = 1;
4996 r = r600_bytecode_add_alu(ctx->bc, &alu);
4997 if (r)
4998 return r;
4999
5000 if (ctx->bc->chip_class == CAYMAN) {
5001 for (i = 0; i < 3; i++) {
5002 /* dst.z = exp(tmp.x) */
5003 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5004 alu.op = ALU_OP1_EXP_IEEE;
5005 alu.src[0].sel = ctx->temp_reg;
5006 alu.src[0].chan = 0;
5007 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5008 if (i == 2) {
5009 alu.dst.write = 1;
5010 alu.last = 1;
5011 } else
5012 alu.dst.write = 0;
5013 r = r600_bytecode_add_alu(ctx->bc, &alu);
5014 if (r)
5015 return r;
5016 }
5017 } else {
5018 /* dst.z = exp(tmp.x) */
5019 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5020 alu.op = ALU_OP1_EXP_IEEE;
5021 alu.src[0].sel = ctx->temp_reg;
5022 alu.src[0].chan = 0;
5023 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5024 alu.last = 1;
5025 r = r600_bytecode_add_alu(ctx->bc, &alu);
5026 if (r)
5027 return r;
5028 }
5029 }
5030
5031 /* dst.x, <- 1.0 */
5032 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5033 alu.op = ALU_OP1_MOV;
5034 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
5035 alu.src[0].chan = 0;
5036 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5037 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5038 r = r600_bytecode_add_alu(ctx->bc, &alu);
5039 if (r)
5040 return r;
5041
5042 /* dst.y = max(src.x, 0.0) */
5043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5044 alu.op = ALU_OP2_MAX;
5045 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5046 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
5047 alu.src[1].chan = 0;
5048 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5049 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5050 r = r600_bytecode_add_alu(ctx->bc, &alu);
5051 if (r)
5052 return r;
5053
5054 /* dst.w, <- 1.0 */
5055 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5056 alu.op = ALU_OP1_MOV;
5057 alu.src[0].sel = V_SQ_ALU_SRC_1;
5058 alu.src[0].chan = 0;
5059 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5060 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5061 alu.last = 1;
5062 r = r600_bytecode_add_alu(ctx->bc, &alu);
5063 if (r)
5064 return r;
5065
5066 return 0;
5067 }
5068
5069 static int tgsi_rsq(struct r600_shader_ctx *ctx)
5070 {
5071 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5072 struct r600_bytecode_alu alu;
5073 int i, r;
5074
5075 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5076
5077 alu.op = ALU_OP1_RECIPSQRT_IEEE;
5078
5079 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5080 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5081 r600_bytecode_src_set_abs(&alu.src[i]);
5082 }
5083 alu.dst.sel = ctx->temp_reg;
5084 alu.dst.write = 1;
5085 alu.last = 1;
5086 r = r600_bytecode_add_alu(ctx->bc, &alu);
5087 if (r)
5088 return r;
5089 /* replicate result */
5090 return tgsi_helper_tempx_replicate(ctx);
5091 }
5092
5093 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
5094 {
5095 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5096 struct r600_bytecode_alu alu;
5097 int i, r;
5098
5099 for (i = 0; i < 4; i++) {
5100 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5101 alu.src[0].sel = ctx->temp_reg;
5102 alu.op = ALU_OP1_MOV;
5103 alu.dst.chan = i;
5104 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5105 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5106 if (i == 3)
5107 alu.last = 1;
5108 r = r600_bytecode_add_alu(ctx->bc, &alu);
5109 if (r)
5110 return r;
5111 }
5112 return 0;
5113 }
5114
5115 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
5116 {
5117 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5118 struct r600_bytecode_alu alu;
5119 int i, r;
5120
5121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5122 alu.op = ctx->inst_info->op;
5123 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5124 r600_bytecode_src(&alu.src[i], &ctx->src[i], 0);
5125 }
5126 alu.dst.sel = ctx->temp_reg;
5127 alu.dst.write = 1;
5128 alu.last = 1;
5129 r = r600_bytecode_add_alu(ctx->bc, &alu);
5130 if (r)
5131 return r;
5132 /* replicate result */
5133 return tgsi_helper_tempx_replicate(ctx);
5134 }
5135
5136 static int cayman_pow(struct r600_shader_ctx *ctx)
5137 {
5138 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5139 int i, r;
5140 struct r600_bytecode_alu alu;
5141 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5142
5143 for (i = 0; i < 3; i++) {
5144 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5145 alu.op = ALU_OP1_LOG_IEEE;
5146 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5147 alu.dst.sel = ctx->temp_reg;
5148 alu.dst.chan = i;
5149 alu.dst.write = 1;
5150 if (i == 2)
5151 alu.last = 1;
5152 r = r600_bytecode_add_alu(ctx->bc, &alu);
5153 if (r)
5154 return r;
5155 }
5156
5157 /* b * LOG2(a) */
5158 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5159 alu.op = ALU_OP2_MUL;
5160 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5161 alu.src[1].sel = ctx->temp_reg;
5162 alu.dst.sel = ctx->temp_reg;
5163 alu.dst.write = 1;
5164 alu.last = 1;
5165 r = r600_bytecode_add_alu(ctx->bc, &alu);
5166 if (r)
5167 return r;
5168
5169 for (i = 0; i < last_slot; i++) {
5170 /* POW(a,b) = EXP2(b * LOG2(a))*/
5171 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5172 alu.op = ALU_OP1_EXP_IEEE;
5173 alu.src[0].sel = ctx->temp_reg;
5174
5175 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5176 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5177 if (i == last_slot - 1)
5178 alu.last = 1;
5179 r = r600_bytecode_add_alu(ctx->bc, &alu);
5180 if (r)
5181 return r;
5182 }
5183 return 0;
5184 }
5185
5186 static int tgsi_pow(struct r600_shader_ctx *ctx)
5187 {
5188 struct r600_bytecode_alu alu;
5189 int r;
5190
5191 /* LOG2(a) */
5192 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5193 alu.op = ALU_OP1_LOG_IEEE;
5194 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
5195 alu.dst.sel = ctx->temp_reg;
5196 alu.dst.write = 1;
5197 alu.last = 1;
5198 r = r600_bytecode_add_alu(ctx->bc, &alu);
5199 if (r)
5200 return r;
5201 /* b * LOG2(a) */
5202 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5203 alu.op = ALU_OP2_MUL;
5204 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
5205 alu.src[1].sel = ctx->temp_reg;
5206 alu.dst.sel = ctx->temp_reg;
5207 alu.dst.write = 1;
5208 alu.last = 1;
5209 r = r600_bytecode_add_alu(ctx->bc, &alu);
5210 if (r)
5211 return r;
5212 /* POW(a,b) = EXP2(b * LOG2(a))*/
5213 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5214 alu.op = ALU_OP1_EXP_IEEE;
5215 alu.src[0].sel = ctx->temp_reg;
5216 alu.dst.sel = ctx->temp_reg;
5217 alu.dst.write = 1;
5218 alu.last = 1;
5219 r = r600_bytecode_add_alu(ctx->bc, &alu);
5220 if (r)
5221 return r;
5222 return tgsi_helper_tempx_replicate(ctx);
5223 }
5224
5225 static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
5226 {
5227 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5228 struct r600_bytecode_alu alu;
5229 int i, r, j;
5230 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5231 int tmp0 = ctx->temp_reg;
5232 int tmp1 = r600_get_temp(ctx);
5233 int tmp2 = r600_get_temp(ctx);
5234 int tmp3 = r600_get_temp(ctx);
5235 /* Unsigned path:
5236 *
5237 * we need to represent src1 as src2*q + r, where q - quotient, r - remainder
5238 *
5239 * 1. tmp0.x = rcp (src2) = 2^32/src2 + e, where e is rounding error
5240 * 2. tmp0.z = lo (tmp0.x * src2)
5241 * 3. tmp0.w = -tmp0.z
5242 * 4. tmp0.y = hi (tmp0.x * src2)
5243 * 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src2))
5244 * 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error
5245 * 7. tmp1.x = tmp0.x - tmp0.w
5246 * 8. tmp1.y = tmp0.x + tmp0.w
5247 * 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x)
5248 * 10. tmp0.z = hi(tmp0.x * src1) = q
5249 * 11. tmp0.y = lo (tmp0.z * src2) = src2*q = src1 - r
5250 *
5251 * 12. tmp0.w = src1 - tmp0.y = r
5252 * 13. tmp1.x = tmp0.w >= src2 = r >= src2 (uint comparison)
5253 * 14. tmp1.y = src1 >= tmp0.y = r >= 0 (uint comparison)
5254 *
5255 * if DIV
5256 *
5257 * 15. tmp1.z = tmp0.z + 1 = q + 1
5258 * 16. tmp1.w = tmp0.z - 1 = q - 1
5259 *
5260 * else MOD
5261 *
5262 * 15. tmp1.z = tmp0.w - src2 = r - src2
5263 * 16. tmp1.w = tmp0.w + src2 = r + src2
5264 *
5265 * endif
5266 *
5267 * 17. tmp1.x = tmp1.x & tmp1.y
5268 *
5269 * DIV: 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z
5270 * MOD: 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z
5271 *
5272 * 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z
5273 * 20. dst = src2==0 ? MAX_UINT : tmp0.z
5274 *
5275 * Signed path:
5276 *
5277 * Same as unsigned, using abs values of the operands,
5278 * and fixing the sign of the result in the end.
5279 */
5280
5281 for (i = 0; i < 4; i++) {
5282 if (!(write_mask & (1<<i)))
5283 continue;
5284
5285 if (signed_op) {
5286
5287 /* tmp2.x = -src0 */
5288 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5289 alu.op = ALU_OP2_SUB_INT;
5290
5291 alu.dst.sel = tmp2;
5292 alu.dst.chan = 0;
5293 alu.dst.write = 1;
5294
5295 alu.src[0].sel = V_SQ_ALU_SRC_0;
5296
5297 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5298
5299 alu.last = 1;
5300 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5301 return r;
5302
5303 /* tmp2.y = -src1 */
5304 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5305 alu.op = ALU_OP2_SUB_INT;
5306
5307 alu.dst.sel = tmp2;
5308 alu.dst.chan = 1;
5309 alu.dst.write = 1;
5310
5311 alu.src[0].sel = V_SQ_ALU_SRC_0;
5312
5313 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5314
5315 alu.last = 1;
5316 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5317 return r;
5318
5319 /* tmp2.z sign bit is set if src0 and src2 signs are different */
5320 /* it will be a sign of the quotient */
5321 if (!mod) {
5322
5323 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5324 alu.op = ALU_OP2_XOR_INT;
5325
5326 alu.dst.sel = tmp2;
5327 alu.dst.chan = 2;
5328 alu.dst.write = 1;
5329
5330 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5331 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5332
5333 alu.last = 1;
5334 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5335 return r;
5336 }
5337
5338 /* tmp2.x = |src0| */
5339 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5340 alu.op = ALU_OP3_CNDGE_INT;
5341 alu.is_op3 = 1;
5342
5343 alu.dst.sel = tmp2;
5344 alu.dst.chan = 0;
5345 alu.dst.write = 1;
5346
5347 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5348 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5349 alu.src[2].sel = tmp2;
5350 alu.src[2].chan = 0;
5351
5352 alu.last = 1;
5353 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5354 return r;
5355
5356 /* tmp2.y = |src1| */
5357 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5358 alu.op = ALU_OP3_CNDGE_INT;
5359 alu.is_op3 = 1;
5360
5361 alu.dst.sel = tmp2;
5362 alu.dst.chan = 1;
5363 alu.dst.write = 1;
5364
5365 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5366 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5367 alu.src[2].sel = tmp2;
5368 alu.src[2].chan = 1;
5369
5370 alu.last = 1;
5371 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5372 return r;
5373
5374 }
5375
5376 /* 1. tmp0.x = rcp_u (src2) = 2^32/src2 + e, where e is rounding error */
5377 if (ctx->bc->chip_class == CAYMAN) {
5378 /* tmp3.x = u2f(src2) */
5379 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5380 alu.op = ALU_OP1_UINT_TO_FLT;
5381
5382 alu.dst.sel = tmp3;
5383 alu.dst.chan = 0;
5384 alu.dst.write = 1;
5385
5386 if (signed_op) {
5387 alu.src[0].sel = tmp2;
5388 alu.src[0].chan = 1;
5389 } else {
5390 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5391 }
5392
5393 alu.last = 1;
5394 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5395 return r;
5396
5397 /* tmp0.x = recip(tmp3.x) */
5398 for (j = 0 ; j < 3; j++) {
5399 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5400 alu.op = ALU_OP1_RECIP_IEEE;
5401
5402 alu.dst.sel = tmp0;
5403 alu.dst.chan = j;
5404 alu.dst.write = (j == 0);
5405
5406 alu.src[0].sel = tmp3;
5407 alu.src[0].chan = 0;
5408
5409 if (j == 2)
5410 alu.last = 1;
5411 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5412 return r;
5413 }
5414
5415 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5416 alu.op = ALU_OP2_MUL;
5417
5418 alu.src[0].sel = tmp0;
5419 alu.src[0].chan = 0;
5420
5421 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
5422 alu.src[1].value = 0x4f800000;
5423
5424 alu.dst.sel = tmp3;
5425 alu.dst.write = 1;
5426 alu.last = 1;
5427 r = r600_bytecode_add_alu(ctx->bc, &alu);
5428 if (r)
5429 return r;
5430
5431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5432 alu.op = ALU_OP1_FLT_TO_UINT;
5433
5434 alu.dst.sel = tmp0;
5435 alu.dst.chan = 0;
5436 alu.dst.write = 1;
5437
5438 alu.src[0].sel = tmp3;
5439 alu.src[0].chan = 0;
5440
5441 alu.last = 1;
5442 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5443 return r;
5444
5445 } else {
5446 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5447 alu.op = ALU_OP1_RECIP_UINT;
5448
5449 alu.dst.sel = tmp0;
5450 alu.dst.chan = 0;
5451 alu.dst.write = 1;
5452
5453 if (signed_op) {
5454 alu.src[0].sel = tmp2;
5455 alu.src[0].chan = 1;
5456 } else {
5457 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5458 }
5459
5460 alu.last = 1;
5461 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5462 return r;
5463 }
5464
5465 /* 2. tmp0.z = lo (tmp0.x * src2) */
5466 if (ctx->bc->chip_class == CAYMAN) {
5467 for (j = 0 ; j < 4; j++) {
5468 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5469 alu.op = ALU_OP2_MULLO_UINT;
5470
5471 alu.dst.sel = tmp0;
5472 alu.dst.chan = j;
5473 alu.dst.write = (j == 2);
5474
5475 alu.src[0].sel = tmp0;
5476 alu.src[0].chan = 0;
5477 if (signed_op) {
5478 alu.src[1].sel = tmp2;
5479 alu.src[1].chan = 1;
5480 } else {
5481 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5482 }
5483
5484 alu.last = (j == 3);
5485 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5486 return r;
5487 }
5488 } else {
5489 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5490 alu.op = ALU_OP2_MULLO_UINT;
5491
5492 alu.dst.sel = tmp0;
5493 alu.dst.chan = 2;
5494 alu.dst.write = 1;
5495
5496 alu.src[0].sel = tmp0;
5497 alu.src[0].chan = 0;
5498 if (signed_op) {
5499 alu.src[1].sel = tmp2;
5500 alu.src[1].chan = 1;
5501 } else {
5502 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5503 }
5504
5505 alu.last = 1;
5506 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5507 return r;
5508 }
5509
5510 /* 3. tmp0.w = -tmp0.z */
5511 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5512 alu.op = ALU_OP2_SUB_INT;
5513
5514 alu.dst.sel = tmp0;
5515 alu.dst.chan = 3;
5516 alu.dst.write = 1;
5517
5518 alu.src[0].sel = V_SQ_ALU_SRC_0;
5519 alu.src[1].sel = tmp0;
5520 alu.src[1].chan = 2;
5521
5522 alu.last = 1;
5523 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5524 return r;
5525
5526 /* 4. tmp0.y = hi (tmp0.x * src2) */
5527 if (ctx->bc->chip_class == CAYMAN) {
5528 for (j = 0 ; j < 4; j++) {
5529 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5530 alu.op = ALU_OP2_MULHI_UINT;
5531
5532 alu.dst.sel = tmp0;
5533 alu.dst.chan = j;
5534 alu.dst.write = (j == 1);
5535
5536 alu.src[0].sel = tmp0;
5537 alu.src[0].chan = 0;
5538
5539 if (signed_op) {
5540 alu.src[1].sel = tmp2;
5541 alu.src[1].chan = 1;
5542 } else {
5543 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5544 }
5545 alu.last = (j == 3);
5546 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5547 return r;
5548 }
5549 } else {
5550 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5551 alu.op = ALU_OP2_MULHI_UINT;
5552
5553 alu.dst.sel = tmp0;
5554 alu.dst.chan = 1;
5555 alu.dst.write = 1;
5556
5557 alu.src[0].sel = tmp0;
5558 alu.src[0].chan = 0;
5559
5560 if (signed_op) {
5561 alu.src[1].sel = tmp2;
5562 alu.src[1].chan = 1;
5563 } else {
5564 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5565 }
5566
5567 alu.last = 1;
5568 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5569 return r;
5570 }
5571
5572 /* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
5573 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5574 alu.op = ALU_OP3_CNDE_INT;
5575 alu.is_op3 = 1;
5576
5577 alu.dst.sel = tmp0;
5578 alu.dst.chan = 2;
5579 alu.dst.write = 1;
5580
5581 alu.src[0].sel = tmp0;
5582 alu.src[0].chan = 1;
5583 alu.src[1].sel = tmp0;
5584 alu.src[1].chan = 3;
5585 alu.src[2].sel = tmp0;
5586 alu.src[2].chan = 2;
5587
5588 alu.last = 1;
5589 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5590 return r;
5591
5592 /* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
5593 if (ctx->bc->chip_class == CAYMAN) {
5594 for (j = 0 ; j < 4; j++) {
5595 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5596 alu.op = ALU_OP2_MULHI_UINT;
5597
5598 alu.dst.sel = tmp0;
5599 alu.dst.chan = j;
5600 alu.dst.write = (j == 3);
5601
5602 alu.src[0].sel = tmp0;
5603 alu.src[0].chan = 2;
5604
5605 alu.src[1].sel = tmp0;
5606 alu.src[1].chan = 0;
5607
5608 alu.last = (j == 3);
5609 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5610 return r;
5611 }
5612 } else {
5613 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5614 alu.op = ALU_OP2_MULHI_UINT;
5615
5616 alu.dst.sel = tmp0;
5617 alu.dst.chan = 3;
5618 alu.dst.write = 1;
5619
5620 alu.src[0].sel = tmp0;
5621 alu.src[0].chan = 2;
5622
5623 alu.src[1].sel = tmp0;
5624 alu.src[1].chan = 0;
5625
5626 alu.last = 1;
5627 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5628 return r;
5629 }
5630
5631 /* 7. tmp1.x = tmp0.x - tmp0.w */
5632 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5633 alu.op = ALU_OP2_SUB_INT;
5634
5635 alu.dst.sel = tmp1;
5636 alu.dst.chan = 0;
5637 alu.dst.write = 1;
5638
5639 alu.src[0].sel = tmp0;
5640 alu.src[0].chan = 0;
5641 alu.src[1].sel = tmp0;
5642 alu.src[1].chan = 3;
5643
5644 alu.last = 1;
5645 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5646 return r;
5647
5648 /* 8. tmp1.y = tmp0.x + tmp0.w */
5649 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5650 alu.op = ALU_OP2_ADD_INT;
5651
5652 alu.dst.sel = tmp1;
5653 alu.dst.chan = 1;
5654 alu.dst.write = 1;
5655
5656 alu.src[0].sel = tmp0;
5657 alu.src[0].chan = 0;
5658 alu.src[1].sel = tmp0;
5659 alu.src[1].chan = 3;
5660
5661 alu.last = 1;
5662 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5663 return r;
5664
5665 /* 9. tmp0.x = (tmp0.y == 0 ? tmp1.y : tmp1.x) */
5666 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5667 alu.op = ALU_OP3_CNDE_INT;
5668 alu.is_op3 = 1;
5669
5670 alu.dst.sel = tmp0;
5671 alu.dst.chan = 0;
5672 alu.dst.write = 1;
5673
5674 alu.src[0].sel = tmp0;
5675 alu.src[0].chan = 1;
5676 alu.src[1].sel = tmp1;
5677 alu.src[1].chan = 1;
5678 alu.src[2].sel = tmp1;
5679 alu.src[2].chan = 0;
5680
5681 alu.last = 1;
5682 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5683 return r;
5684
5685 /* 10. tmp0.z = hi(tmp0.x * src1) = q */
5686 if (ctx->bc->chip_class == CAYMAN) {
5687 for (j = 0 ; j < 4; j++) {
5688 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5689 alu.op = ALU_OP2_MULHI_UINT;
5690
5691 alu.dst.sel = tmp0;
5692 alu.dst.chan = j;
5693 alu.dst.write = (j == 2);
5694
5695 alu.src[0].sel = tmp0;
5696 alu.src[0].chan = 0;
5697
5698 if (signed_op) {
5699 alu.src[1].sel = tmp2;
5700 alu.src[1].chan = 0;
5701 } else {
5702 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5703 }
5704
5705 alu.last = (j == 3);
5706 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5707 return r;
5708 }
5709 } else {
5710 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5711 alu.op = ALU_OP2_MULHI_UINT;
5712
5713 alu.dst.sel = tmp0;
5714 alu.dst.chan = 2;
5715 alu.dst.write = 1;
5716
5717 alu.src[0].sel = tmp0;
5718 alu.src[0].chan = 0;
5719
5720 if (signed_op) {
5721 alu.src[1].sel = tmp2;
5722 alu.src[1].chan = 0;
5723 } else {
5724 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
5725 }
5726
5727 alu.last = 1;
5728 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5729 return r;
5730 }
5731
5732 /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
5733 if (ctx->bc->chip_class == CAYMAN) {
5734 for (j = 0 ; j < 4; j++) {
5735 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5736 alu.op = ALU_OP2_MULLO_UINT;
5737
5738 alu.dst.sel = tmp0;
5739 alu.dst.chan = j;
5740 alu.dst.write = (j == 1);
5741
5742 if (signed_op) {
5743 alu.src[0].sel = tmp2;
5744 alu.src[0].chan = 1;
5745 } else {
5746 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5747 }
5748
5749 alu.src[1].sel = tmp0;
5750 alu.src[1].chan = 2;
5751
5752 alu.last = (j == 3);
5753 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5754 return r;
5755 }
5756 } else {
5757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5758 alu.op = ALU_OP2_MULLO_UINT;
5759
5760 alu.dst.sel = tmp0;
5761 alu.dst.chan = 1;
5762 alu.dst.write = 1;
5763
5764 if (signed_op) {
5765 alu.src[0].sel = tmp2;
5766 alu.src[0].chan = 1;
5767 } else {
5768 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
5769 }
5770
5771 alu.src[1].sel = tmp0;
5772 alu.src[1].chan = 2;
5773
5774 alu.last = 1;
5775 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5776 return r;
5777 }
5778
5779 /* 12. tmp0.w = src1 - tmp0.y = r */
5780 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5781 alu.op = ALU_OP2_SUB_INT;
5782
5783 alu.dst.sel = tmp0;
5784 alu.dst.chan = 3;
5785 alu.dst.write = 1;
5786
5787 if (signed_op) {
5788 alu.src[0].sel = tmp2;
5789 alu.src[0].chan = 0;
5790 } else {
5791 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5792 }
5793
5794 alu.src[1].sel = tmp0;
5795 alu.src[1].chan = 1;
5796
5797 alu.last = 1;
5798 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5799 return r;
5800
5801 /* 13. tmp1.x = tmp0.w >= src2 = r >= src2 */
5802 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5803 alu.op = ALU_OP2_SETGE_UINT;
5804
5805 alu.dst.sel = tmp1;
5806 alu.dst.chan = 0;
5807 alu.dst.write = 1;
5808
5809 alu.src[0].sel = tmp0;
5810 alu.src[0].chan = 3;
5811 if (signed_op) {
5812 alu.src[1].sel = tmp2;
5813 alu.src[1].chan = 1;
5814 } else {
5815 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5816 }
5817
5818 alu.last = 1;
5819 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5820 return r;
5821
5822 /* 14. tmp1.y = src1 >= tmp0.y = r >= 0 */
5823 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5824 alu.op = ALU_OP2_SETGE_UINT;
5825
5826 alu.dst.sel = tmp1;
5827 alu.dst.chan = 1;
5828 alu.dst.write = 1;
5829
5830 if (signed_op) {
5831 alu.src[0].sel = tmp2;
5832 alu.src[0].chan = 0;
5833 } else {
5834 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
5835 }
5836
5837 alu.src[1].sel = tmp0;
5838 alu.src[1].chan = 1;
5839
5840 alu.last = 1;
5841 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5842 return r;
5843
5844 if (mod) { /* UMOD */
5845
5846 /* 15. tmp1.z = tmp0.w - src2 = r - src2 */
5847 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5848 alu.op = ALU_OP2_SUB_INT;
5849
5850 alu.dst.sel = tmp1;
5851 alu.dst.chan = 2;
5852 alu.dst.write = 1;
5853
5854 alu.src[0].sel = tmp0;
5855 alu.src[0].chan = 3;
5856
5857 if (signed_op) {
5858 alu.src[1].sel = tmp2;
5859 alu.src[1].chan = 1;
5860 } else {
5861 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5862 }
5863
5864 alu.last = 1;
5865 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5866 return r;
5867
5868 /* 16. tmp1.w = tmp0.w + src2 = r + src2 */
5869 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5870 alu.op = ALU_OP2_ADD_INT;
5871
5872 alu.dst.sel = tmp1;
5873 alu.dst.chan = 3;
5874 alu.dst.write = 1;
5875
5876 alu.src[0].sel = tmp0;
5877 alu.src[0].chan = 3;
5878 if (signed_op) {
5879 alu.src[1].sel = tmp2;
5880 alu.src[1].chan = 1;
5881 } else {
5882 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
5883 }
5884
5885 alu.last = 1;
5886 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5887 return r;
5888
5889 } else { /* UDIV */
5890
5891 /* 15. tmp1.z = tmp0.z + 1 = q + 1 DIV */
5892 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5893 alu.op = ALU_OP2_ADD_INT;
5894
5895 alu.dst.sel = tmp1;
5896 alu.dst.chan = 2;
5897 alu.dst.write = 1;
5898
5899 alu.src[0].sel = tmp0;
5900 alu.src[0].chan = 2;
5901 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
5902
5903 alu.last = 1;
5904 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5905 return r;
5906
5907 /* 16. tmp1.w = tmp0.z - 1 = q - 1 */
5908 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5909 alu.op = ALU_OP2_ADD_INT;
5910
5911 alu.dst.sel = tmp1;
5912 alu.dst.chan = 3;
5913 alu.dst.write = 1;
5914
5915 alu.src[0].sel = tmp0;
5916 alu.src[0].chan = 2;
5917 alu.src[1].sel = V_SQ_ALU_SRC_M_1_INT;
5918
5919 alu.last = 1;
5920 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5921 return r;
5922
5923 }
5924
5925 /* 17. tmp1.x = tmp1.x & tmp1.y */
5926 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5927 alu.op = ALU_OP2_AND_INT;
5928
5929 alu.dst.sel = tmp1;
5930 alu.dst.chan = 0;
5931 alu.dst.write = 1;
5932
5933 alu.src[0].sel = tmp1;
5934 alu.src[0].chan = 0;
5935 alu.src[1].sel = tmp1;
5936 alu.src[1].chan = 1;
5937
5938 alu.last = 1;
5939 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5940 return r;
5941
5942 /* 18. tmp0.z = tmp1.x==0 ? tmp0.z : tmp1.z DIV */
5943 /* 18. tmp0.z = tmp1.x==0 ? tmp0.w : tmp1.z MOD */
5944 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5945 alu.op = ALU_OP3_CNDE_INT;
5946 alu.is_op3 = 1;
5947
5948 alu.dst.sel = tmp0;
5949 alu.dst.chan = 2;
5950 alu.dst.write = 1;
5951
5952 alu.src[0].sel = tmp1;
5953 alu.src[0].chan = 0;
5954 alu.src[1].sel = tmp0;
5955 alu.src[1].chan = mod ? 3 : 2;
5956 alu.src[2].sel = tmp1;
5957 alu.src[2].chan = 2;
5958
5959 alu.last = 1;
5960 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5961 return r;
5962
5963 /* 19. tmp0.z = tmp1.y==0 ? tmp1.w : tmp0.z */
5964 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5965 alu.op = ALU_OP3_CNDE_INT;
5966 alu.is_op3 = 1;
5967
5968 if (signed_op) {
5969 alu.dst.sel = tmp0;
5970 alu.dst.chan = 2;
5971 alu.dst.write = 1;
5972 } else {
5973 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5974 }
5975
5976 alu.src[0].sel = tmp1;
5977 alu.src[0].chan = 1;
5978 alu.src[1].sel = tmp1;
5979 alu.src[1].chan = 3;
5980 alu.src[2].sel = tmp0;
5981 alu.src[2].chan = 2;
5982
5983 alu.last = 1;
5984 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
5985 return r;
5986
5987 if (signed_op) {
5988
5989 /* fix the sign of the result */
5990
5991 if (mod) {
5992
5993 /* tmp0.x = -tmp0.z */
5994 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
5995 alu.op = ALU_OP2_SUB_INT;
5996
5997 alu.dst.sel = tmp0;
5998 alu.dst.chan = 0;
5999 alu.dst.write = 1;
6000
6001 alu.src[0].sel = V_SQ_ALU_SRC_0;
6002 alu.src[1].sel = tmp0;
6003 alu.src[1].chan = 2;
6004
6005 alu.last = 1;
6006 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6007 return r;
6008
6009 /* sign of the remainder is the same as the sign of src0 */
6010 /* tmp0.x = src0>=0 ? tmp0.z : tmp0.x */
6011 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6012 alu.op = ALU_OP3_CNDGE_INT;
6013 alu.is_op3 = 1;
6014
6015 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6016
6017 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6018 alu.src[1].sel = tmp0;
6019 alu.src[1].chan = 2;
6020 alu.src[2].sel = tmp0;
6021 alu.src[2].chan = 0;
6022
6023 alu.last = 1;
6024 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6025 return r;
6026
6027 } else {
6028
6029 /* tmp0.x = -tmp0.z */
6030 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6031 alu.op = ALU_OP2_SUB_INT;
6032
6033 alu.dst.sel = tmp0;
6034 alu.dst.chan = 0;
6035 alu.dst.write = 1;
6036
6037 alu.src[0].sel = V_SQ_ALU_SRC_0;
6038 alu.src[1].sel = tmp0;
6039 alu.src[1].chan = 2;
6040
6041 alu.last = 1;
6042 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6043 return r;
6044
6045 /* fix the quotient sign (same as the sign of src0*src1) */
6046 /* tmp0.x = tmp2.z>=0 ? tmp0.z : tmp0.x */
6047 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6048 alu.op = ALU_OP3_CNDGE_INT;
6049 alu.is_op3 = 1;
6050
6051 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6052
6053 alu.src[0].sel = tmp2;
6054 alu.src[0].chan = 2;
6055 alu.src[1].sel = tmp0;
6056 alu.src[1].chan = 2;
6057 alu.src[2].sel = tmp0;
6058 alu.src[2].chan = 0;
6059
6060 alu.last = 1;
6061 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
6062 return r;
6063 }
6064 }
6065 }
6066 return 0;
6067 }
6068
6069 static int tgsi_udiv(struct r600_shader_ctx *ctx)
6070 {
6071 return tgsi_divmod(ctx, 0, 0);
6072 }
6073
6074 static int tgsi_umod(struct r600_shader_ctx *ctx)
6075 {
6076 return tgsi_divmod(ctx, 1, 0);
6077 }
6078
6079 static int tgsi_idiv(struct r600_shader_ctx *ctx)
6080 {
6081 return tgsi_divmod(ctx, 0, 1);
6082 }
6083
6084 static int tgsi_imod(struct r600_shader_ctx *ctx)
6085 {
6086 return tgsi_divmod(ctx, 1, 1);
6087 }
6088
6089
6090 static int tgsi_f2i(struct r600_shader_ctx *ctx)
6091 {
6092 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6093 struct r600_bytecode_alu alu;
6094 int i, r;
6095 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6096 int last_inst = tgsi_last_instruction(write_mask);
6097
6098 for (i = 0; i < 4; i++) {
6099 if (!(write_mask & (1<<i)))
6100 continue;
6101
6102 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6103 alu.op = ALU_OP1_TRUNC;
6104
6105 alu.dst.sel = ctx->temp_reg;
6106 alu.dst.chan = i;
6107 alu.dst.write = 1;
6108
6109 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6110 if (i == last_inst)
6111 alu.last = 1;
6112 r = r600_bytecode_add_alu(ctx->bc, &alu);
6113 if (r)
6114 return r;
6115 }
6116
6117 for (i = 0; i < 4; i++) {
6118 if (!(write_mask & (1<<i)))
6119 continue;
6120
6121 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6122 alu.op = ctx->inst_info->op;
6123
6124 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6125
6126 alu.src[0].sel = ctx->temp_reg;
6127 alu.src[0].chan = i;
6128
6129 if (i == last_inst || alu.op == ALU_OP1_FLT_TO_UINT)
6130 alu.last = 1;
6131 r = r600_bytecode_add_alu(ctx->bc, &alu);
6132 if (r)
6133 return r;
6134 }
6135
6136 return 0;
6137 }
6138
6139 static int tgsi_iabs(struct r600_shader_ctx *ctx)
6140 {
6141 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6142 struct r600_bytecode_alu alu;
6143 int i, r;
6144 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6145 int last_inst = tgsi_last_instruction(write_mask);
6146
6147 /* tmp = -src */
6148 for (i = 0; i < 4; i++) {
6149 if (!(write_mask & (1<<i)))
6150 continue;
6151
6152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6153 alu.op = ALU_OP2_SUB_INT;
6154
6155 alu.dst.sel = ctx->temp_reg;
6156 alu.dst.chan = i;
6157 alu.dst.write = 1;
6158
6159 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6160 alu.src[0].sel = V_SQ_ALU_SRC_0;
6161
6162 if (i == last_inst)
6163 alu.last = 1;
6164 r = r600_bytecode_add_alu(ctx->bc, &alu);
6165 if (r)
6166 return r;
6167 }
6168
6169 /* dst = (src >= 0 ? src : tmp) */
6170 for (i = 0; i < 4; i++) {
6171 if (!(write_mask & (1<<i)))
6172 continue;
6173
6174 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6175 alu.op = ALU_OP3_CNDGE_INT;
6176 alu.is_op3 = 1;
6177 alu.dst.write = 1;
6178
6179 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6180
6181 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6182 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6183 alu.src[2].sel = ctx->temp_reg;
6184 alu.src[2].chan = i;
6185
6186 if (i == last_inst)
6187 alu.last = 1;
6188 r = r600_bytecode_add_alu(ctx->bc, &alu);
6189 if (r)
6190 return r;
6191 }
6192 return 0;
6193 }
6194
6195 static int tgsi_issg(struct r600_shader_ctx *ctx)
6196 {
6197 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6198 struct r600_bytecode_alu alu;
6199 int i, r;
6200 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6201 int last_inst = tgsi_last_instruction(write_mask);
6202
6203 /* tmp = (src >= 0 ? src : -1) */
6204 for (i = 0; i < 4; i++) {
6205 if (!(write_mask & (1<<i)))
6206 continue;
6207
6208 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6209 alu.op = ALU_OP3_CNDGE_INT;
6210 alu.is_op3 = 1;
6211
6212 alu.dst.sel = ctx->temp_reg;
6213 alu.dst.chan = i;
6214 alu.dst.write = 1;
6215
6216 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6217 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
6218 alu.src[2].sel = V_SQ_ALU_SRC_M_1_INT;
6219
6220 if (i == last_inst)
6221 alu.last = 1;
6222 r = r600_bytecode_add_alu(ctx->bc, &alu);
6223 if (r)
6224 return r;
6225 }
6226
6227 /* dst = (tmp > 0 ? 1 : tmp) */
6228 for (i = 0; i < 4; i++) {
6229 if (!(write_mask & (1<<i)))
6230 continue;
6231
6232 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6233 alu.op = ALU_OP3_CNDGT_INT;
6234 alu.is_op3 = 1;
6235 alu.dst.write = 1;
6236
6237 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6238
6239 alu.src[0].sel = ctx->temp_reg;
6240 alu.src[0].chan = i;
6241
6242 alu.src[1].sel = V_SQ_ALU_SRC_1_INT;
6243
6244 alu.src[2].sel = ctx->temp_reg;
6245 alu.src[2].chan = i;
6246
6247 if (i == last_inst)
6248 alu.last = 1;
6249 r = r600_bytecode_add_alu(ctx->bc, &alu);
6250 if (r)
6251 return r;
6252 }
6253 return 0;
6254 }
6255
6256
6257
6258 static int tgsi_ssg(struct r600_shader_ctx *ctx)
6259 {
6260 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6261 struct r600_bytecode_alu alu;
6262 int i, r;
6263
6264 /* tmp = (src > 0 ? 1 : src) */
6265 for (i = 0; i < 4; i++) {
6266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6267 alu.op = ALU_OP3_CNDGT;
6268 alu.is_op3 = 1;
6269
6270 alu.dst.sel = ctx->temp_reg;
6271 alu.dst.chan = i;
6272
6273 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6274 alu.src[1].sel = V_SQ_ALU_SRC_1;
6275 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6276
6277 if (i == 3)
6278 alu.last = 1;
6279 r = r600_bytecode_add_alu(ctx->bc, &alu);
6280 if (r)
6281 return r;
6282 }
6283
6284 /* dst = (-tmp > 0 ? -1 : tmp) */
6285 for (i = 0; i < 4; i++) {
6286 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6287 alu.op = ALU_OP3_CNDGT;
6288 alu.is_op3 = 1;
6289 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6290
6291 alu.src[0].sel = ctx->temp_reg;
6292 alu.src[0].chan = i;
6293 alu.src[0].neg = 1;
6294
6295 alu.src[1].sel = V_SQ_ALU_SRC_1;
6296 alu.src[1].neg = 1;
6297
6298 alu.src[2].sel = ctx->temp_reg;
6299 alu.src[2].chan = i;
6300
6301 if (i == 3)
6302 alu.last = 1;
6303 r = r600_bytecode_add_alu(ctx->bc, &alu);
6304 if (r)
6305 return r;
6306 }
6307 return 0;
6308 }
6309
6310 static int tgsi_bfi(struct r600_shader_ctx *ctx)
6311 {
6312 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6313 struct r600_bytecode_alu alu;
6314 int i, r, t1, t2;
6315
6316 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6317 int last_inst = tgsi_last_instruction(write_mask);
6318
6319 t1 = r600_get_temp(ctx);
6320
6321 for (i = 0; i < 4; i++) {
6322 if (!(write_mask & (1<<i)))
6323 continue;
6324
6325 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6326 alu.op = ALU_OP2_SETGE_INT;
6327 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6328 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
6329 alu.src[1].value = 32;
6330 alu.dst.sel = ctx->temp_reg;
6331 alu.dst.chan = i;
6332 alu.dst.write = 1;
6333 alu.last = i == last_inst;
6334 r = r600_bytecode_add_alu(ctx->bc, &alu);
6335 if (r)
6336 return r;
6337 }
6338
6339 for (i = 0; i < 4; i++) {
6340 if (!(write_mask & (1<<i)))
6341 continue;
6342
6343 /* create mask tmp */
6344 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6345 alu.op = ALU_OP2_BFM_INT;
6346 alu.dst.sel = t1;
6347 alu.dst.chan = i;
6348 alu.dst.write = 1;
6349 alu.last = i == last_inst;
6350
6351 r600_bytecode_src(&alu.src[0], &ctx->src[3], i);
6352 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6353
6354 r = r600_bytecode_add_alu(ctx->bc, &alu);
6355 if (r)
6356 return r;
6357 }
6358
6359 t2 = r600_get_temp(ctx);
6360
6361 for (i = 0; i < 4; i++) {
6362 if (!(write_mask & (1<<i)))
6363 continue;
6364
6365 /* shift insert left */
6366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6367 alu.op = ALU_OP2_LSHL_INT;
6368 alu.dst.sel = t2;
6369 alu.dst.chan = i;
6370 alu.dst.write = 1;
6371 alu.last = i == last_inst;
6372
6373 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
6374 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
6375
6376 r = r600_bytecode_add_alu(ctx->bc, &alu);
6377 if (r)
6378 return r;
6379 }
6380
6381 for (i = 0; i < 4; i++) {
6382 if (!(write_mask & (1<<i)))
6383 continue;
6384
6385 /* actual bitfield insert */
6386 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6387 alu.op = ALU_OP3_BFI_INT;
6388 alu.is_op3 = 1;
6389 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6390 alu.dst.chan = i;
6391 alu.dst.write = 1;
6392 alu.last = i == last_inst;
6393
6394 alu.src[0].sel = t1;
6395 alu.src[0].chan = i;
6396 alu.src[1].sel = t2;
6397 alu.src[1].chan = i;
6398 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
6399
6400 r = r600_bytecode_add_alu(ctx->bc, &alu);
6401 if (r)
6402 return r;
6403 }
6404
6405 for (i = 0; i < 4; i++) {
6406 if (!(write_mask & (1<<i)))
6407 continue;
6408 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6409 alu.op = ALU_OP3_CNDE_INT;
6410 alu.is_op3 = 1;
6411 alu.src[0].sel = ctx->temp_reg;
6412 alu.src[0].chan = i;
6413 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
6414
6415 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6416
6417 alu.src[1].sel = alu.dst.sel;
6418 alu.src[1].chan = i;
6419
6420 alu.last = i == last_inst;
6421 r = r600_bytecode_add_alu(ctx->bc, &alu);
6422 if (r)
6423 return r;
6424 }
6425 return 0;
6426 }
6427
6428 static int tgsi_msb(struct r600_shader_ctx *ctx)
6429 {
6430 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6431 struct r600_bytecode_alu alu;
6432 int i, r, t1, t2;
6433
6434 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6435 int last_inst = tgsi_last_instruction(write_mask);
6436
6437 assert(ctx->inst_info->op == ALU_OP1_FFBH_INT ||
6438 ctx->inst_info->op == ALU_OP1_FFBH_UINT);
6439
6440 t1 = ctx->temp_reg;
6441
6442 /* bit position is indexed from lsb by TGSI, and from msb by the hardware */
6443 for (i = 0; i < 4; i++) {
6444 if (!(write_mask & (1<<i)))
6445 continue;
6446
6447 /* t1 = FFBH_INT / FFBH_UINT */
6448 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6449 alu.op = ctx->inst_info->op;
6450 alu.dst.sel = t1;
6451 alu.dst.chan = i;
6452 alu.dst.write = 1;
6453 alu.last = i == last_inst;
6454
6455 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6456
6457 r = r600_bytecode_add_alu(ctx->bc, &alu);
6458 if (r)
6459 return r;
6460 }
6461
6462 t2 = r600_get_temp(ctx);
6463
6464 for (i = 0; i < 4; i++) {
6465 if (!(write_mask & (1<<i)))
6466 continue;
6467
6468 /* t2 = 31 - t1 */
6469 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6470 alu.op = ALU_OP2_SUB_INT;
6471 alu.dst.sel = t2;
6472 alu.dst.chan = i;
6473 alu.dst.write = 1;
6474 alu.last = i == last_inst;
6475
6476 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
6477 alu.src[0].value = 31;
6478 alu.src[1].sel = t1;
6479 alu.src[1].chan = i;
6480
6481 r = r600_bytecode_add_alu(ctx->bc, &alu);
6482 if (r)
6483 return r;
6484 }
6485
6486 for (i = 0; i < 4; i++) {
6487 if (!(write_mask & (1<<i)))
6488 continue;
6489
6490 /* result = t1 >= 0 ? t2 : t1 */
6491 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6492 alu.op = ALU_OP3_CNDGE_INT;
6493 alu.is_op3 = 1;
6494 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6495 alu.dst.chan = i;
6496 alu.dst.write = 1;
6497 alu.last = i == last_inst;
6498
6499 alu.src[0].sel = t1;
6500 alu.src[0].chan = i;
6501 alu.src[1].sel = t2;
6502 alu.src[1].chan = i;
6503 alu.src[2].sel = t1;
6504 alu.src[2].chan = i;
6505
6506 r = r600_bytecode_add_alu(ctx->bc, &alu);
6507 if (r)
6508 return r;
6509 }
6510
6511 return 0;
6512 }
6513
6514 static int tgsi_interp_egcm(struct r600_shader_ctx *ctx)
6515 {
6516 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6517 struct r600_bytecode_alu alu;
6518 int r, i = 0, k, interp_gpr, interp_base_chan, tmp, lasti;
6519 unsigned location;
6520 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
6521
6522 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
6523
6524 /* Interpolators have been marked for use already by allocate_system_value_inputs */
6525 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6526 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6527 location = TGSI_INTERPOLATE_LOC_CENTER; /* sample offset will be added explicitly */
6528 }
6529 else {
6530 location = TGSI_INTERPOLATE_LOC_CENTROID;
6531 }
6532
6533 k = eg_get_interpolator_index(ctx->shader->input[input].interpolate, location);
6534 if (k < 0)
6535 k = 0;
6536 interp_gpr = ctx->eg_interpolators[k].ij_index / 2;
6537 interp_base_chan = 2 * (ctx->eg_interpolators[k].ij_index % 2);
6538
6539 /* NOTE: currently offset is not perspective correct */
6540 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6541 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6542 int sample_gpr = -1;
6543 int gradientsH, gradientsV;
6544 struct r600_bytecode_tex tex;
6545
6546 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6547 sample_gpr = load_sample_position(ctx, &ctx->src[1], ctx->src[1].swizzle[0]);
6548 }
6549
6550 gradientsH = r600_get_temp(ctx);
6551 gradientsV = r600_get_temp(ctx);
6552 for (i = 0; i < 2; i++) {
6553 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
6554 tex.op = i == 0 ? FETCH_OP_GET_GRADIENTS_H : FETCH_OP_GET_GRADIENTS_V;
6555 tex.src_gpr = interp_gpr;
6556 tex.src_sel_x = interp_base_chan + 0;
6557 tex.src_sel_y = interp_base_chan + 1;
6558 tex.src_sel_z = 0;
6559 tex.src_sel_w = 0;
6560 tex.dst_gpr = i == 0 ? gradientsH : gradientsV;
6561 tex.dst_sel_x = 0;
6562 tex.dst_sel_y = 1;
6563 tex.dst_sel_z = 7;
6564 tex.dst_sel_w = 7;
6565 tex.inst_mod = 1; // Use per pixel gradient calculation
6566 tex.sampler_id = 0;
6567 tex.resource_id = tex.sampler_id;
6568 r = r600_bytecode_add_tex(ctx->bc, &tex);
6569 if (r)
6570 return r;
6571 }
6572
6573 for (i = 0; i < 2; i++) {
6574 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6575 alu.op = ALU_OP3_MULADD;
6576 alu.is_op3 = 1;
6577 alu.src[0].sel = gradientsH;
6578 alu.src[0].chan = i;
6579 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6580 alu.src[1].sel = sample_gpr;
6581 alu.src[1].chan = 2;
6582 }
6583 else {
6584 r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
6585 }
6586 alu.src[2].sel = interp_gpr;
6587 alu.src[2].chan = interp_base_chan + i;
6588 alu.dst.sel = ctx->temp_reg;
6589 alu.dst.chan = i;
6590 alu.last = i == 1;
6591
6592 r = r600_bytecode_add_alu(ctx->bc, &alu);
6593 if (r)
6594 return r;
6595 }
6596
6597 for (i = 0; i < 2; i++) {
6598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6599 alu.op = ALU_OP3_MULADD;
6600 alu.is_op3 = 1;
6601 alu.src[0].sel = gradientsV;
6602 alu.src[0].chan = i;
6603 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6604 alu.src[1].sel = sample_gpr;
6605 alu.src[1].chan = 3;
6606 }
6607 else {
6608 r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
6609 }
6610 alu.src[2].sel = ctx->temp_reg;
6611 alu.src[2].chan = i;
6612 alu.dst.sel = ctx->temp_reg;
6613 alu.dst.chan = i;
6614 alu.last = i == 1;
6615
6616 r = r600_bytecode_add_alu(ctx->bc, &alu);
6617 if (r)
6618 return r;
6619 }
6620 }
6621
6622 tmp = r600_get_temp(ctx);
6623 for (i = 0; i < 8; i++) {
6624 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6625 alu.op = i < 4 ? ALU_OP2_INTERP_ZW : ALU_OP2_INTERP_XY;
6626
6627 alu.dst.sel = tmp;
6628 if ((i > 1 && i < 6)) {
6629 alu.dst.write = 1;
6630 }
6631 else {
6632 alu.dst.write = 0;
6633 }
6634 alu.dst.chan = i % 4;
6635
6636 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
6637 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
6638 alu.src[0].sel = ctx->temp_reg;
6639 alu.src[0].chan = 1 - (i % 2);
6640 } else {
6641 alu.src[0].sel = interp_gpr;
6642 alu.src[0].chan = interp_base_chan + 1 - (i % 2);
6643 }
6644 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
6645 alu.src[1].chan = 0;
6646
6647 alu.last = i % 4 == 3;
6648 alu.bank_swizzle_force = SQ_ALU_VEC_210;
6649
6650 r = r600_bytecode_add_alu(ctx->bc, &alu);
6651 if (r)
6652 return r;
6653 }
6654
6655 // INTERP can't swizzle dst
6656 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6657 for (i = 0; i <= lasti; i++) {
6658 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6659 continue;
6660
6661 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6662 alu.op = ALU_OP1_MOV;
6663 alu.src[0].sel = tmp;
6664 alu.src[0].chan = ctx->src[0].swizzle[i];
6665 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6666 alu.dst.write = 1;
6667 alu.last = i == lasti;
6668 r = r600_bytecode_add_alu(ctx->bc, &alu);
6669 if (r)
6670 return r;
6671 }
6672
6673 return 0;
6674 }
6675
6676
6677 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
6678 {
6679 struct r600_bytecode_alu alu;
6680 int i, r;
6681
6682 for (i = 0; i < 4; i++) {
6683 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6684 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
6685 alu.op = ALU_OP0_NOP;
6686 alu.dst.chan = i;
6687 } else {
6688 alu.op = ALU_OP1_MOV;
6689 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6690 alu.src[0].sel = ctx->temp_reg;
6691 alu.src[0].chan = i;
6692 }
6693 if (i == 3) {
6694 alu.last = 1;
6695 }
6696 r = r600_bytecode_add_alu(ctx->bc, &alu);
6697 if (r)
6698 return r;
6699 }
6700 return 0;
6701 }
6702
6703 static int tgsi_make_src_for_op3(struct r600_shader_ctx *ctx,
6704 unsigned temp, int chan,
6705 struct r600_bytecode_alu_src *bc_src,
6706 const struct r600_shader_src *shader_src)
6707 {
6708 struct r600_bytecode_alu alu;
6709 int r;
6710
6711 r600_bytecode_src(bc_src, shader_src, chan);
6712
6713 /* op3 operands don't support abs modifier */
6714 if (bc_src->abs) {
6715 assert(temp!=0); /* we actually need the extra register, make sure it is allocated. */
6716 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6717 alu.op = ALU_OP1_MOV;
6718 alu.dst.sel = temp;
6719 alu.dst.chan = chan;
6720 alu.dst.write = 1;
6721
6722 alu.src[0] = *bc_src;
6723 alu.last = true; // sufficient?
6724 r = r600_bytecode_add_alu(ctx->bc, &alu);
6725 if (r)
6726 return r;
6727
6728 memset(bc_src, 0, sizeof(*bc_src));
6729 bc_src->sel = temp;
6730 bc_src->chan = chan;
6731 }
6732 return 0;
6733 }
6734
6735 static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
6736 {
6737 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6738 struct r600_bytecode_alu alu;
6739 int i, j, r;
6740 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6741 int temp_regs[4];
6742 unsigned op = ctx->inst_info->op;
6743
6744 if (op == ALU_OP3_MULADD_IEEE &&
6745 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6746 op = ALU_OP3_MULADD;
6747
6748 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6749 temp_regs[j] = 0;
6750 if (ctx->src[j].abs)
6751 temp_regs[j] = r600_get_temp(ctx);
6752 }
6753 for (i = 0; i < lasti + 1; i++) {
6754 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6755 continue;
6756
6757 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6758 alu.op = op;
6759 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6760 r = tgsi_make_src_for_op3(ctx, temp_regs[j], i, &alu.src[j], &ctx->src[j]);
6761 if (r)
6762 return r;
6763 }
6764
6765 if (dst == -1) {
6766 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6767 } else {
6768 alu.dst.sel = dst;
6769 }
6770 alu.dst.chan = i;
6771 alu.dst.write = 1;
6772 alu.is_op3 = 1;
6773 if (i == lasti) {
6774 alu.last = 1;
6775 }
6776 r = r600_bytecode_add_alu(ctx->bc, &alu);
6777 if (r)
6778 return r;
6779 }
6780 return 0;
6781 }
6782
6783 static int tgsi_op3(struct r600_shader_ctx *ctx)
6784 {
6785 return tgsi_op3_dst(ctx, -1);
6786 }
6787
6788 static int tgsi_dp(struct r600_shader_ctx *ctx)
6789 {
6790 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6791 struct r600_bytecode_alu alu;
6792 int i, j, r;
6793 unsigned op = ctx->inst_info->op;
6794 if (op == ALU_OP2_DOT4_IEEE &&
6795 ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
6796 op = ALU_OP2_DOT4;
6797
6798 for (i = 0; i < 4; i++) {
6799 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6800 alu.op = op;
6801 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
6802 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
6803 }
6804
6805 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6806 alu.dst.chan = i;
6807 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
6808 /* handle some special cases */
6809 switch (inst->Instruction.Opcode) {
6810 case TGSI_OPCODE_DP2:
6811 if (i > 1) {
6812 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6813 alu.src[0].chan = alu.src[1].chan = 0;
6814 }
6815 break;
6816 case TGSI_OPCODE_DP3:
6817 if (i > 2) {
6818 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
6819 alu.src[0].chan = alu.src[1].chan = 0;
6820 }
6821 break;
6822 default:
6823 break;
6824 }
6825 if (i == 3) {
6826 alu.last = 1;
6827 }
6828 r = r600_bytecode_add_alu(ctx->bc, &alu);
6829 if (r)
6830 return r;
6831 }
6832 return 0;
6833 }
6834
6835 static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx,
6836 unsigned index)
6837 {
6838 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6839 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
6840 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
6841 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
6842 ctx->src[index].neg || ctx->src[index].abs ||
6843 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
6844 }
6845
6846 static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
6847 unsigned index)
6848 {
6849 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6850 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
6851 }
6852
6853 static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
6854 {
6855 struct r600_bytecode_vtx vtx;
6856 struct r600_bytecode_alu alu;
6857 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6858 int src_gpr, r, i;
6859 int id = tgsi_tex_get_src_gpr(ctx, 1);
6860 int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6861
6862 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
6863 if (src_requires_loading) {
6864 for (i = 0; i < 4; i++) {
6865 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6866 alu.op = ALU_OP1_MOV;
6867 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
6868 alu.dst.sel = ctx->temp_reg;
6869 alu.dst.chan = i;
6870 if (i == 3)
6871 alu.last = 1;
6872 alu.dst.write = 1;
6873 r = r600_bytecode_add_alu(ctx->bc, &alu);
6874 if (r)
6875 return r;
6876 }
6877 src_gpr = ctx->temp_reg;
6878 }
6879
6880 memset(&vtx, 0, sizeof(vtx));
6881 vtx.op = FETCH_OP_VFETCH;
6882 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6883 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6884 vtx.src_gpr = src_gpr;
6885 vtx.mega_fetch_count = 16;
6886 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6887 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6888 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
6889 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
6890 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
6891 vtx.use_const_fields = 1;
6892 vtx.buffer_index_mode = sampler_index_mode;
6893
6894 if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
6895 return r;
6896
6897 if (ctx->bc->chip_class >= EVERGREEN)
6898 return 0;
6899
6900 for (i = 0; i < 4; i++) {
6901 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
6902 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
6903 continue;
6904
6905 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6906 alu.op = ALU_OP2_AND_INT;
6907
6908 alu.dst.chan = i;
6909 alu.dst.sel = vtx.dst_gpr;
6910 alu.dst.write = 1;
6911
6912 alu.src[0].sel = vtx.dst_gpr;
6913 alu.src[0].chan = i;
6914
6915 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
6916 alu.src[1].sel += (id * 2);
6917 alu.src[1].chan = i % 4;
6918 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6919
6920 if (i == lasti)
6921 alu.last = 1;
6922 r = r600_bytecode_add_alu(ctx->bc, &alu);
6923 if (r)
6924 return r;
6925 }
6926
6927 if (inst->Dst[0].Register.WriteMask & 3) {
6928 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6929 alu.op = ALU_OP2_OR_INT;
6930
6931 alu.dst.chan = 3;
6932 alu.dst.sel = vtx.dst_gpr;
6933 alu.dst.write = 1;
6934
6935 alu.src[0].sel = vtx.dst_gpr;
6936 alu.src[0].chan = 3;
6937
6938 alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
6939 alu.src[1].chan = 0;
6940 alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6941
6942 alu.last = 1;
6943 r = r600_bytecode_add_alu(ctx->bc, &alu);
6944 if (r)
6945 return r;
6946 }
6947 return 0;
6948 }
6949
6950 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset)
6951 {
6952 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6953 int r;
6954 int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
6955 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
6956
6957 if (ctx->bc->chip_class < EVERGREEN) {
6958 struct r600_bytecode_alu alu;
6959 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
6960 alu.op = ALU_OP1_MOV;
6961 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
6962 /* r600 we have them at channel 2 of the second dword */
6963 alu.src[0].sel += (id * 2) + 1;
6964 alu.src[0].chan = 1;
6965 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
6966 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
6967 alu.last = 1;
6968 r = r600_bytecode_add_alu(ctx->bc, &alu);
6969 if (r)
6970 return r;
6971 return 0;
6972 } else {
6973 struct r600_bytecode_vtx vtx;
6974 memset(&vtx, 0, sizeof(vtx));
6975 vtx.op = FETCH_OP_GDS_MIN_UINT; /* aka GET_BUFFER_RESINFO */
6976 vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
6977 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
6978 vtx.src_gpr = 0;
6979 vtx.mega_fetch_count = 16; /* no idea here really... */
6980 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
6981 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
6982 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
6983 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
6984 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
6985 vtx.data_format = FMT_32_32_32_32;
6986 vtx.buffer_index_mode = sampler_index_mode;
6987
6988 if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
6989 return r;
6990 return 0;
6991 }
6992 }
6993
6994
6995 static int tgsi_tex(struct r600_shader_ctx *ctx)
6996 {
6997 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6998 struct r600_bytecode_tex tex;
6999 struct r600_bytecode_alu alu;
7000 unsigned src_gpr;
7001 int r, i, j;
7002 int opcode;
7003 bool read_compressed_msaa = ctx->bc->has_compressed_msaa_texturing &&
7004 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7005 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7006 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7007
7008 bool txf_add_offsets = inst->Texture.NumOffsets &&
7009 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7010 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7011
7012 /* Texture fetch instructions can only use gprs as source.
7013 * Also they cannot negate the source or take the absolute value */
7014 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7015 tgsi_tex_src_requires_loading(ctx, 0)) ||
7016 read_compressed_msaa || txf_add_offsets;
7017
7018 boolean src_loaded = FALSE;
7019 unsigned sampler_src_reg = 1;
7020 int8_t offset_x = 0, offset_y = 0, offset_z = 0;
7021 boolean has_txq_cube_array_z = false;
7022 unsigned sampler_index_mode;
7023
7024 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7025 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7026 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7027 if (inst->Dst[0].Register.WriteMask & 4) {
7028 ctx->shader->has_txq_cube_array_z_comp = true;
7029 has_txq_cube_array_z = true;
7030 }
7031
7032 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7033 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7034 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7035 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7036 sampler_src_reg = 2;
7037
7038 /* TGSI moves the sampler to src reg 3 for TXD */
7039 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7040 sampler_src_reg = 3;
7041
7042 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7043
7044 src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
7045
7046 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7047 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7048 if (ctx->bc->chip_class < EVERGREEN)
7049 ctx->shader->uses_tex_buffers = true;
7050 return r600_do_buffer_txq(ctx, 1, 0);
7051 }
7052 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7053 if (ctx->bc->chip_class < EVERGREEN)
7054 ctx->shader->uses_tex_buffers = true;
7055 return do_vtx_fetch_inst(ctx, src_requires_loading);
7056 }
7057 }
7058
7059 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7060 int out_chan;
7061 /* Add perspective divide */
7062 if (ctx->bc->chip_class == CAYMAN) {
7063 out_chan = 2;
7064 for (i = 0; i < 3; i++) {
7065 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7066 alu.op = ALU_OP1_RECIP_IEEE;
7067 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7068
7069 alu.dst.sel = ctx->temp_reg;
7070 alu.dst.chan = i;
7071 if (i == 2)
7072 alu.last = 1;
7073 if (out_chan == i)
7074 alu.dst.write = 1;
7075 r = r600_bytecode_add_alu(ctx->bc, &alu);
7076 if (r)
7077 return r;
7078 }
7079
7080 } else {
7081 out_chan = 3;
7082 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7083 alu.op = ALU_OP1_RECIP_IEEE;
7084 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7085
7086 alu.dst.sel = ctx->temp_reg;
7087 alu.dst.chan = out_chan;
7088 alu.last = 1;
7089 alu.dst.write = 1;
7090 r = r600_bytecode_add_alu(ctx->bc, &alu);
7091 if (r)
7092 return r;
7093 }
7094
7095 for (i = 0; i < 3; i++) {
7096 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7097 alu.op = ALU_OP2_MUL;
7098 alu.src[0].sel = ctx->temp_reg;
7099 alu.src[0].chan = out_chan;
7100 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
7101 alu.dst.sel = ctx->temp_reg;
7102 alu.dst.chan = i;
7103 alu.dst.write = 1;
7104 r = r600_bytecode_add_alu(ctx->bc, &alu);
7105 if (r)
7106 return r;
7107 }
7108 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7109 alu.op = ALU_OP1_MOV;
7110 alu.src[0].sel = V_SQ_ALU_SRC_1;
7111 alu.src[0].chan = 0;
7112 alu.dst.sel = ctx->temp_reg;
7113 alu.dst.chan = 3;
7114 alu.last = 1;
7115 alu.dst.write = 1;
7116 r = r600_bytecode_add_alu(ctx->bc, &alu);
7117 if (r)
7118 return r;
7119 src_loaded = TRUE;
7120 src_gpr = ctx->temp_reg;
7121 }
7122
7123
7124 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7125 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7126 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7127 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7128 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7129
7130 static const unsigned src0_swizzle[] = {2, 2, 0, 1};
7131 static const unsigned src1_swizzle[] = {1, 0, 2, 2};
7132
7133 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
7134 for (i = 0; i < 4; i++) {
7135 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7136 alu.op = ALU_OP2_CUBE;
7137 r600_bytecode_src(&alu.src[0], &ctx->src[0], src0_swizzle[i]);
7138 r600_bytecode_src(&alu.src[1], &ctx->src[0], src1_swizzle[i]);
7139 alu.dst.sel = ctx->temp_reg;
7140 alu.dst.chan = i;
7141 if (i == 3)
7142 alu.last = 1;
7143 alu.dst.write = 1;
7144 r = r600_bytecode_add_alu(ctx->bc, &alu);
7145 if (r)
7146 return r;
7147 }
7148
7149 /* tmp1.z = RCP_e(|tmp1.z|) */
7150 if (ctx->bc->chip_class == CAYMAN) {
7151 for (i = 0; i < 3; i++) {
7152 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7153 alu.op = ALU_OP1_RECIP_IEEE;
7154 alu.src[0].sel = ctx->temp_reg;
7155 alu.src[0].chan = 2;
7156 alu.src[0].abs = 1;
7157 alu.dst.sel = ctx->temp_reg;
7158 alu.dst.chan = i;
7159 if (i == 2)
7160 alu.dst.write = 1;
7161 if (i == 2)
7162 alu.last = 1;
7163 r = r600_bytecode_add_alu(ctx->bc, &alu);
7164 if (r)
7165 return r;
7166 }
7167 } else {
7168 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7169 alu.op = ALU_OP1_RECIP_IEEE;
7170 alu.src[0].sel = ctx->temp_reg;
7171 alu.src[0].chan = 2;
7172 alu.src[0].abs = 1;
7173 alu.dst.sel = ctx->temp_reg;
7174 alu.dst.chan = 2;
7175 alu.dst.write = 1;
7176 alu.last = 1;
7177 r = r600_bytecode_add_alu(ctx->bc, &alu);
7178 if (r)
7179 return r;
7180 }
7181
7182 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
7183 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
7184 * muladd has no writemask, have to use another temp
7185 */
7186 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7187 alu.op = ALU_OP3_MULADD;
7188 alu.is_op3 = 1;
7189
7190 alu.src[0].sel = ctx->temp_reg;
7191 alu.src[0].chan = 0;
7192 alu.src[1].sel = ctx->temp_reg;
7193 alu.src[1].chan = 2;
7194
7195 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7196 alu.src[2].chan = 0;
7197 alu.src[2].value = u_bitcast_f2u(1.5f);
7198
7199 alu.dst.sel = ctx->temp_reg;
7200 alu.dst.chan = 0;
7201 alu.dst.write = 1;
7202
7203 r = r600_bytecode_add_alu(ctx->bc, &alu);
7204 if (r)
7205 return r;
7206
7207 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7208 alu.op = ALU_OP3_MULADD;
7209 alu.is_op3 = 1;
7210
7211 alu.src[0].sel = ctx->temp_reg;
7212 alu.src[0].chan = 1;
7213 alu.src[1].sel = ctx->temp_reg;
7214 alu.src[1].chan = 2;
7215
7216 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
7217 alu.src[2].chan = 0;
7218 alu.src[2].value = u_bitcast_f2u(1.5f);
7219
7220 alu.dst.sel = ctx->temp_reg;
7221 alu.dst.chan = 1;
7222 alu.dst.write = 1;
7223
7224 alu.last = 1;
7225 r = r600_bytecode_add_alu(ctx->bc, &alu);
7226 if (r)
7227 return r;
7228 /* write initial compare value into Z component
7229 - W src 0 for shadow cube
7230 - X src 1 for shadow cube array */
7231 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7232 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7233 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7234 alu.op = ALU_OP1_MOV;
7235 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7236 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7237 else
7238 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7239 alu.dst.sel = ctx->temp_reg;
7240 alu.dst.chan = 2;
7241 alu.dst.write = 1;
7242 alu.last = 1;
7243 r = r600_bytecode_add_alu(ctx->bc, &alu);
7244 if (r)
7245 return r;
7246 }
7247
7248 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7249 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7250 if (ctx->bc->chip_class >= EVERGREEN) {
7251 int mytmp = r600_get_temp(ctx);
7252 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7253 alu.op = ALU_OP1_MOV;
7254 alu.src[0].sel = ctx->temp_reg;
7255 alu.src[0].chan = 3;
7256 alu.dst.sel = mytmp;
7257 alu.dst.chan = 0;
7258 alu.dst.write = 1;
7259 alu.last = 1;
7260 r = r600_bytecode_add_alu(ctx->bc, &alu);
7261 if (r)
7262 return r;
7263
7264 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7265 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7266 alu.op = ALU_OP3_MULADD;
7267 alu.is_op3 = 1;
7268 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7269 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7270 alu.src[1].chan = 0;
7271 alu.src[1].value = u_bitcast_f2u(8.0f);
7272 alu.src[2].sel = mytmp;
7273 alu.src[2].chan = 0;
7274 alu.dst.sel = ctx->temp_reg;
7275 alu.dst.chan = 3;
7276 alu.dst.write = 1;
7277 alu.last = 1;
7278 r = r600_bytecode_add_alu(ctx->bc, &alu);
7279 if (r)
7280 return r;
7281 } else if (ctx->bc->chip_class < EVERGREEN) {
7282 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7283 tex.op = FETCH_OP_SET_CUBEMAP_INDEX;
7284 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7285 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7286 tex.src_gpr = r600_get_temp(ctx);
7287 tex.src_sel_x = 0;
7288 tex.src_sel_y = 0;
7289 tex.src_sel_z = 0;
7290 tex.src_sel_w = 0;
7291 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7292 tex.coord_type_x = 1;
7293 tex.coord_type_y = 1;
7294 tex.coord_type_z = 1;
7295 tex.coord_type_w = 1;
7296 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7297 alu.op = ALU_OP1_MOV;
7298 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7299 alu.dst.sel = tex.src_gpr;
7300 alu.dst.chan = 0;
7301 alu.last = 1;
7302 alu.dst.write = 1;
7303 r = r600_bytecode_add_alu(ctx->bc, &alu);
7304 if (r)
7305 return r;
7306
7307 r = r600_bytecode_add_tex(ctx->bc, &tex);
7308 if (r)
7309 return r;
7310 }
7311
7312 }
7313
7314 /* for cube forms of lod and bias we need to route things */
7315 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7316 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7317 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7318 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7319 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7320 alu.op = ALU_OP1_MOV;
7321 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7322 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7323 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
7324 else
7325 r600_bytecode_src(&alu.src[0], &ctx->src[0], 3);
7326 alu.dst.sel = ctx->temp_reg;
7327 alu.dst.chan = 2;
7328 alu.last = 1;
7329 alu.dst.write = 1;
7330 r = r600_bytecode_add_alu(ctx->bc, &alu);
7331 if (r)
7332 return r;
7333 }
7334
7335 src_loaded = TRUE;
7336 src_gpr = ctx->temp_reg;
7337 }
7338
7339 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7340 int temp_h = 0, temp_v = 0;
7341 int start_val = 0;
7342
7343 /* if we've already loaded the src (i.e. CUBE don't reload it). */
7344 if (src_loaded == TRUE)
7345 start_val = 1;
7346 else
7347 src_loaded = TRUE;
7348 for (i = start_val; i < 3; i++) {
7349 int treg = r600_get_temp(ctx);
7350
7351 if (i == 0)
7352 src_gpr = treg;
7353 else if (i == 1)
7354 temp_h = treg;
7355 else
7356 temp_v = treg;
7357
7358 for (j = 0; j < 4; j++) {
7359 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7360 alu.op = ALU_OP1_MOV;
7361 r600_bytecode_src(&alu.src[0], &ctx->src[i], j);
7362 alu.dst.sel = treg;
7363 alu.dst.chan = j;
7364 if (j == 3)
7365 alu.last = 1;
7366 alu.dst.write = 1;
7367 r = r600_bytecode_add_alu(ctx->bc, &alu);
7368 if (r)
7369 return r;
7370 }
7371 }
7372 for (i = 1; i < 3; i++) {
7373 /* set gradients h/v */
7374 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7375 tex.op = (i == 1) ? FETCH_OP_SET_GRADIENTS_H :
7376 FETCH_OP_SET_GRADIENTS_V;
7377 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7378 tex.sampler_index_mode = sampler_index_mode;
7379 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7380 tex.resource_index_mode = sampler_index_mode;
7381
7382 tex.src_gpr = (i == 1) ? temp_h : temp_v;
7383 tex.src_sel_x = 0;
7384 tex.src_sel_y = 1;
7385 tex.src_sel_z = 2;
7386 tex.src_sel_w = 3;
7387
7388 tex.dst_gpr = r600_get_temp(ctx); /* just to avoid confusing the asm scheduler */
7389 tex.dst_sel_x = tex.dst_sel_y = tex.dst_sel_z = tex.dst_sel_w = 7;
7390 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7391 tex.coord_type_x = 1;
7392 tex.coord_type_y = 1;
7393 tex.coord_type_z = 1;
7394 tex.coord_type_w = 1;
7395 }
7396 r = r600_bytecode_add_tex(ctx->bc, &tex);
7397 if (r)
7398 return r;
7399 }
7400 }
7401
7402 if (src_requires_loading && !src_loaded) {
7403 for (i = 0; i < 4; i++) {
7404 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7405 alu.op = ALU_OP1_MOV;
7406 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
7407 alu.dst.sel = ctx->temp_reg;
7408 alu.dst.chan = i;
7409 if (i == 3)
7410 alu.last = 1;
7411 alu.dst.write = 1;
7412 r = r600_bytecode_add_alu(ctx->bc, &alu);
7413 if (r)
7414 return r;
7415 }
7416 src_loaded = TRUE;
7417 src_gpr = ctx->temp_reg;
7418 }
7419
7420 /* get offset values */
7421 if (inst->Texture.NumOffsets) {
7422 assert(inst->Texture.NumOffsets == 1);
7423
7424 /* The texture offset feature doesn't work with the TXF instruction
7425 * and must be emulated by adding the offset to the texture coordinates. */
7426 if (txf_add_offsets) {
7427 const struct tgsi_texture_offset *off = inst->TexOffsets;
7428
7429 switch (inst->Texture.Texture) {
7430 case TGSI_TEXTURE_3D:
7431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7432 alu.op = ALU_OP2_ADD_INT;
7433 alu.src[0].sel = src_gpr;
7434 alu.src[0].chan = 2;
7435 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7436 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleZ];
7437 alu.dst.sel = src_gpr;
7438 alu.dst.chan = 2;
7439 alu.dst.write = 1;
7440 alu.last = 1;
7441 r = r600_bytecode_add_alu(ctx->bc, &alu);
7442 if (r)
7443 return r;
7444 /* fall through */
7445
7446 case TGSI_TEXTURE_2D:
7447 case TGSI_TEXTURE_SHADOW2D:
7448 case TGSI_TEXTURE_RECT:
7449 case TGSI_TEXTURE_SHADOWRECT:
7450 case TGSI_TEXTURE_2D_ARRAY:
7451 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7452 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7453 alu.op = ALU_OP2_ADD_INT;
7454 alu.src[0].sel = src_gpr;
7455 alu.src[0].chan = 1;
7456 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7457 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleY];
7458 alu.dst.sel = src_gpr;
7459 alu.dst.chan = 1;
7460 alu.dst.write = 1;
7461 alu.last = 1;
7462 r = r600_bytecode_add_alu(ctx->bc, &alu);
7463 if (r)
7464 return r;
7465 /* fall through */
7466
7467 case TGSI_TEXTURE_1D:
7468 case TGSI_TEXTURE_SHADOW1D:
7469 case TGSI_TEXTURE_1D_ARRAY:
7470 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7471 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7472 alu.op = ALU_OP2_ADD_INT;
7473 alu.src[0].sel = src_gpr;
7474 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7475 alu.src[1].value = ctx->literals[4 * off[0].Index + off[0].SwizzleX];
7476 alu.dst.sel = src_gpr;
7477 alu.dst.write = 1;
7478 alu.last = 1;
7479 r = r600_bytecode_add_alu(ctx->bc, &alu);
7480 if (r)
7481 return r;
7482 break;
7483 /* texture offsets do not apply to other texture targets */
7484 }
7485 } else {
7486 switch (inst->Texture.Texture) {
7487 case TGSI_TEXTURE_3D:
7488 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
7489 /* fallthrough */
7490 case TGSI_TEXTURE_2D:
7491 case TGSI_TEXTURE_SHADOW2D:
7492 case TGSI_TEXTURE_RECT:
7493 case TGSI_TEXTURE_SHADOWRECT:
7494 case TGSI_TEXTURE_2D_ARRAY:
7495 case TGSI_TEXTURE_SHADOW2D_ARRAY:
7496 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
7497 /* fallthrough */
7498 case TGSI_TEXTURE_1D:
7499 case TGSI_TEXTURE_SHADOW1D:
7500 case TGSI_TEXTURE_1D_ARRAY:
7501 case TGSI_TEXTURE_SHADOW1D_ARRAY:
7502 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
7503 }
7504 }
7505 }
7506
7507 /* Obtain the sample index for reading a compressed MSAA color texture.
7508 * To read the FMASK, we use the ldfptr instruction, which tells us
7509 * where the samples are stored.
7510 * For uncompressed 8x MSAA surfaces, ldfptr should return 0x76543210,
7511 * which is the identity mapping. Each nibble says which physical sample
7512 * should be fetched to get that sample.
7513 *
7514 * Assume src.z contains the sample index. It should be modified like this:
7515 * src.z = (ldfptr() >> (src.z * 4)) & 0xF;
7516 * Then fetch the texel with src.
7517 */
7518 if (read_compressed_msaa) {
7519 unsigned sample_chan = 3;
7520 unsigned temp = r600_get_temp(ctx);
7521 assert(src_loaded);
7522
7523 /* temp.w = ldfptr() */
7524 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7525 tex.op = FETCH_OP_LD;
7526 tex.inst_mod = 1; /* to indicate this is ldfptr */
7527 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7528 tex.sampler_index_mode = sampler_index_mode;
7529 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7530 tex.resource_index_mode = sampler_index_mode;
7531 tex.src_gpr = src_gpr;
7532 tex.dst_gpr = temp;
7533 tex.dst_sel_x = 7; /* mask out these components */
7534 tex.dst_sel_y = 7;
7535 tex.dst_sel_z = 7;
7536 tex.dst_sel_w = 0; /* store X */
7537 tex.src_sel_x = 0;
7538 tex.src_sel_y = 1;
7539 tex.src_sel_z = 2;
7540 tex.src_sel_w = 3;
7541 tex.offset_x = offset_x;
7542 tex.offset_y = offset_y;
7543 tex.offset_z = offset_z;
7544 r = r600_bytecode_add_tex(ctx->bc, &tex);
7545 if (r)
7546 return r;
7547
7548 /* temp.x = sample_index*4 */
7549 if (ctx->bc->chip_class == CAYMAN) {
7550 for (i = 0 ; i < 4; i++) {
7551 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7552 alu.op = ALU_OP2_MULLO_INT;
7553 alu.src[0].sel = src_gpr;
7554 alu.src[0].chan = sample_chan;
7555 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7556 alu.src[1].value = 4;
7557 alu.dst.sel = temp;
7558 alu.dst.chan = i;
7559 alu.dst.write = i == 0;
7560 if (i == 3)
7561 alu.last = 1;
7562 r = r600_bytecode_add_alu(ctx->bc, &alu);
7563 if (r)
7564 return r;
7565 }
7566 } else {
7567 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7568 alu.op = ALU_OP2_MULLO_INT;
7569 alu.src[0].sel = src_gpr;
7570 alu.src[0].chan = sample_chan;
7571 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7572 alu.src[1].value = 4;
7573 alu.dst.sel = temp;
7574 alu.dst.chan = 0;
7575 alu.dst.write = 1;
7576 alu.last = 1;
7577 r = r600_bytecode_add_alu(ctx->bc, &alu);
7578 if (r)
7579 return r;
7580 }
7581
7582 /* sample_index = temp.w >> temp.x */
7583 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7584 alu.op = ALU_OP2_LSHR_INT;
7585 alu.src[0].sel = temp;
7586 alu.src[0].chan = 3;
7587 alu.src[1].sel = temp;
7588 alu.src[1].chan = 0;
7589 alu.dst.sel = src_gpr;
7590 alu.dst.chan = sample_chan;
7591 alu.dst.write = 1;
7592 alu.last = 1;
7593 r = r600_bytecode_add_alu(ctx->bc, &alu);
7594 if (r)
7595 return r;
7596
7597 /* sample_index & 0xF */
7598 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7599 alu.op = ALU_OP2_AND_INT;
7600 alu.src[0].sel = src_gpr;
7601 alu.src[0].chan = sample_chan;
7602 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7603 alu.src[1].value = 0xF;
7604 alu.dst.sel = src_gpr;
7605 alu.dst.chan = sample_chan;
7606 alu.dst.write = 1;
7607 alu.last = 1;
7608 r = r600_bytecode_add_alu(ctx->bc, &alu);
7609 if (r)
7610 return r;
7611 #if 0
7612 /* visualize the FMASK */
7613 for (i = 0; i < 4; i++) {
7614 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7615 alu.op = ALU_OP1_INT_TO_FLT;
7616 alu.src[0].sel = src_gpr;
7617 alu.src[0].chan = sample_chan;
7618 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7619 alu.dst.chan = i;
7620 alu.dst.write = 1;
7621 alu.last = 1;
7622 r = r600_bytecode_add_alu(ctx->bc, &alu);
7623 if (r)
7624 return r;
7625 }
7626 return 0;
7627 #endif
7628 }
7629
7630 /* does this shader want a num layers from TXQ for a cube array? */
7631 if (has_txq_cube_array_z) {
7632 int id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7633
7634 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7635 alu.op = ALU_OP1_MOV;
7636
7637 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
7638 if (ctx->bc->chip_class >= EVERGREEN) {
7639 /* with eg each dword is number of cubes */
7640 alu.src[0].sel += id / 4;
7641 alu.src[0].chan = id % 4;
7642 } else {
7643 /* r600 we have them at channel 2 of the second dword */
7644 alu.src[0].sel += (id * 2) + 1;
7645 alu.src[0].chan = 2;
7646 }
7647 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
7648 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
7649 alu.last = 1;
7650 r = r600_bytecode_add_alu(ctx->bc, &alu);
7651 if (r)
7652 return r;
7653 /* disable writemask from texture instruction */
7654 inst->Dst[0].Register.WriteMask &= ~4;
7655 }
7656
7657 opcode = ctx->inst_info->op;
7658 if (opcode == FETCH_OP_GATHER4 &&
7659 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
7660 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
7661 opcode = FETCH_OP_GATHER4_O;
7662
7663 /* GATHER4_O/GATHER4_C_O use offset values loaded by
7664 SET_TEXTURE_OFFSETS instruction. The immediate offset values
7665 encoded in the instruction are ignored. */
7666 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7667 tex.op = FETCH_OP_SET_TEXTURE_OFFSETS;
7668 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7669 tex.sampler_index_mode = sampler_index_mode;
7670 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7671 tex.resource_index_mode = sampler_index_mode;
7672
7673 tex.src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
7674 tex.src_sel_x = inst->TexOffsets[0].SwizzleX;
7675 tex.src_sel_y = inst->TexOffsets[0].SwizzleY;
7676 tex.src_sel_z = inst->TexOffsets[0].SwizzleZ;
7677 tex.src_sel_w = 4;
7678
7679 tex.dst_sel_x = 7;
7680 tex.dst_sel_y = 7;
7681 tex.dst_sel_z = 7;
7682 tex.dst_sel_w = 7;
7683
7684 r = r600_bytecode_add_tex(ctx->bc, &tex);
7685 if (r)
7686 return r;
7687 }
7688
7689 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7690 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7691 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7692 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7693 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
7694 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7695 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7696 switch (opcode) {
7697 case FETCH_OP_SAMPLE:
7698 opcode = FETCH_OP_SAMPLE_C;
7699 break;
7700 case FETCH_OP_SAMPLE_L:
7701 opcode = FETCH_OP_SAMPLE_C_L;
7702 break;
7703 case FETCH_OP_SAMPLE_LB:
7704 opcode = FETCH_OP_SAMPLE_C_LB;
7705 break;
7706 case FETCH_OP_SAMPLE_G:
7707 opcode = FETCH_OP_SAMPLE_C_G;
7708 break;
7709 /* Texture gather variants */
7710 case FETCH_OP_GATHER4:
7711 opcode = FETCH_OP_GATHER4_C;
7712 break;
7713 case FETCH_OP_GATHER4_O:
7714 opcode = FETCH_OP_GATHER4_C_O;
7715 break;
7716 }
7717 }
7718
7719 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
7720 tex.op = opcode;
7721
7722 tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
7723 tex.sampler_index_mode = sampler_index_mode;
7724 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
7725 tex.resource_index_mode = sampler_index_mode;
7726 tex.src_gpr = src_gpr;
7727 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7728
7729 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
7730 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
7731 tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */
7732 }
7733
7734 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
7735 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
7736 tex.inst_mod = texture_component_select;
7737
7738 if (ctx->bc->chip_class == CAYMAN) {
7739 /* GATHER4 result order is different from TGSI TG4 */
7740 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
7741 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
7742 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
7743 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7744 } else {
7745 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7746 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7747 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7748 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7749 }
7750 }
7751 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
7752 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7753 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7754 tex.dst_sel_z = 7;
7755 tex.dst_sel_w = 7;
7756 }
7757 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7758 tex.dst_sel_x = 3;
7759 tex.dst_sel_y = 7;
7760 tex.dst_sel_z = 7;
7761 tex.dst_sel_w = 7;
7762 }
7763 else {
7764 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
7765 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
7766 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
7767 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
7768 }
7769
7770
7771 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
7772 tex.src_sel_x = 4;
7773 tex.src_sel_y = 4;
7774 tex.src_sel_z = 4;
7775 tex.src_sel_w = 4;
7776 } else if (src_loaded) {
7777 tex.src_sel_x = 0;
7778 tex.src_sel_y = 1;
7779 tex.src_sel_z = 2;
7780 tex.src_sel_w = 3;
7781 } else {
7782 tex.src_sel_x = ctx->src[0].swizzle[0];
7783 tex.src_sel_y = ctx->src[0].swizzle[1];
7784 tex.src_sel_z = ctx->src[0].swizzle[2];
7785 tex.src_sel_w = ctx->src[0].swizzle[3];
7786 tex.src_rel = ctx->src[0].rel;
7787 }
7788
7789 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7790 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7791 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7792 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7793 tex.src_sel_x = 1;
7794 tex.src_sel_y = 0;
7795 tex.src_sel_z = 3;
7796 tex.src_sel_w = 2; /* route Z compare or Lod value into W */
7797 }
7798
7799 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
7800 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
7801 tex.coord_type_x = 1;
7802 tex.coord_type_y = 1;
7803 }
7804 tex.coord_type_z = 1;
7805 tex.coord_type_w = 1;
7806
7807 tex.offset_x = offset_x;
7808 tex.offset_y = offset_y;
7809 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
7810 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7811 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
7812 tex.offset_z = 0;
7813 }
7814 else {
7815 tex.offset_z = offset_z;
7816 }
7817
7818 /* Put the depth for comparison in W.
7819 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7820 * Some instructions expect the depth in Z. */
7821 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
7822 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
7823 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
7824 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
7825 opcode != FETCH_OP_SAMPLE_C_L &&
7826 opcode != FETCH_OP_SAMPLE_C_LB) {
7827 tex.src_sel_w = tex.src_sel_z;
7828 }
7829
7830 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
7831 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
7832 if (opcode == FETCH_OP_SAMPLE_C_L ||
7833 opcode == FETCH_OP_SAMPLE_C_LB) {
7834 /* the array index is read from Y */
7835 tex.coord_type_y = 0;
7836 } else {
7837 /* the array index is read from Z */
7838 tex.coord_type_z = 0;
7839 tex.src_sel_z = tex.src_sel_y;
7840 }
7841 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
7842 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
7843 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7844 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7845 (ctx->bc->chip_class >= EVERGREEN)))
7846 /* the array index is read from Z */
7847 tex.coord_type_z = 0;
7848
7849 /* mask unused source components */
7850 if (opcode == FETCH_OP_SAMPLE || opcode == FETCH_OP_GATHER4) {
7851 switch (inst->Texture.Texture) {
7852 case TGSI_TEXTURE_2D:
7853 case TGSI_TEXTURE_RECT:
7854 tex.src_sel_z = 7;
7855 tex.src_sel_w = 7;
7856 break;
7857 case TGSI_TEXTURE_1D_ARRAY:
7858 tex.src_sel_y = 7;
7859 tex.src_sel_w = 7;
7860 break;
7861 case TGSI_TEXTURE_1D:
7862 tex.src_sel_y = 7;
7863 tex.src_sel_z = 7;
7864 tex.src_sel_w = 7;
7865 break;
7866 }
7867 }
7868
7869 r = r600_bytecode_add_tex(ctx->bc, &tex);
7870 if (r)
7871 return r;
7872
7873 /* add shadow ambient support - gallium doesn't do it yet */
7874 return 0;
7875 }
7876
7877 static int find_hw_atomic_counter(struct r600_shader_ctx *ctx,
7878 struct tgsi_full_src_register *src)
7879 {
7880 unsigned i;
7881
7882 if (src->Register.Indirect) {
7883 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7884 if (src->Indirect.ArrayID == ctx->shader->atomics[i].array_id)
7885 return ctx->shader->atomics[i].hw_idx;
7886 }
7887 } else {
7888 uint32_t index = src->Register.Index;
7889 for (i = 0; i < ctx->shader->nhwatomic_ranges; i++) {
7890 if (ctx->shader->atomics[i].buffer_id != (unsigned)src->Dimension.Index)
7891 continue;
7892 if (index > ctx->shader->atomics[i].end)
7893 continue;
7894 if (index < ctx->shader->atomics[i].start)
7895 continue;
7896 uint32_t offset = (index - ctx->shader->atomics[i].start);
7897 return ctx->shader->atomics[i].hw_idx + offset;
7898 }
7899 }
7900 assert(0);
7901 return -1;
7902 }
7903
7904 static int tgsi_set_gds_temp(struct r600_shader_ctx *ctx,
7905 int *uav_id_p, int *uav_index_mode_p)
7906 {
7907 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7908 int uav_id, uav_index_mode = 0;
7909 int r;
7910 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7911
7912 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
7913
7914 if (inst->Src[0].Register.Indirect) {
7915 if (is_cm) {
7916 struct r600_bytecode_alu alu;
7917 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7918 alu.op = ALU_OP2_LSHL_INT;
7919 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
7920 alu.src[0].chan = 0;
7921 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
7922 alu.src[1].value = 2;
7923 alu.dst.sel = ctx->temp_reg;
7924 alu.dst.chan = 0;
7925 alu.dst.write = 1;
7926 alu.last = 1;
7927 r = r600_bytecode_add_alu(ctx->bc, &alu);
7928 if (r)
7929 return r;
7930
7931 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
7932 ctx->temp_reg, 0,
7933 ctx->temp_reg, 0,
7934 V_SQ_ALU_SRC_LITERAL, uav_id * 4);
7935 if (r)
7936 return r;
7937 } else
7938 uav_index_mode = 2;
7939 } else if (is_cm) {
7940 r = single_alu_op2(ctx, ALU_OP1_MOV,
7941 ctx->temp_reg, 0,
7942 V_SQ_ALU_SRC_LITERAL, uav_id * 4,
7943 0, 0);
7944 if (r)
7945 return r;
7946 }
7947 *uav_id_p = uav_id;
7948 *uav_index_mode_p = uav_index_mode;
7949 return 0;
7950 }
7951
7952 static int tgsi_load_gds(struct r600_shader_ctx *ctx)
7953 {
7954 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7955 int r;
7956 struct r600_bytecode_gds gds;
7957 int uav_id = 0;
7958 int uav_index_mode = 0;
7959 bool is_cm = (ctx->bc->chip_class == CAYMAN);
7960
7961 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
7962 if (r)
7963 return r;
7964
7965 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
7966 gds.op = FETCH_OP_GDS_READ_RET;
7967 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7968 gds.uav_id = is_cm ? 0 : uav_id;
7969 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
7970 gds.src_gpr = ctx->temp_reg;
7971 gds.src_sel_x = (is_cm) ? 0 : 4;
7972 gds.src_sel_y = 4;
7973 gds.src_sel_z = 4;
7974 gds.dst_sel_x = 0;
7975 gds.dst_sel_y = 7;
7976 gds.dst_sel_z = 7;
7977 gds.dst_sel_w = 7;
7978 gds.src_gpr2 = 0;
7979 gds.alloc_consume = !is_cm;
7980 r = r600_bytecode_add_gds(ctx->bc, &gds);
7981 if (r)
7982 return r;
7983
7984 ctx->bc->cf_last->vpm = 1;
7985 return 0;
7986 }
7987
7988 /* this fixes up 1D arrays properly */
7989 static int load_index_src(struct r600_shader_ctx *ctx, int src_index, int *idx_gpr)
7990 {
7991 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7992 int r, i;
7993 struct r600_bytecode_alu alu;
7994 int temp_reg = r600_get_temp(ctx);
7995
7996 for (i = 0; i < 4; i++) {
7997 bool def_val = true, write_zero = false;
7998 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
7999 alu.op = ALU_OP1_MOV;
8000 alu.dst.sel = temp_reg;
8001 alu.dst.chan = i;
8002
8003 switch (inst->Memory.Texture) {
8004 case TGSI_TEXTURE_BUFFER:
8005 case TGSI_TEXTURE_1D:
8006 if (i == 1 || i == 2 || i == 3) {
8007 write_zero = true;
8008 }
8009 break;
8010 case TGSI_TEXTURE_1D_ARRAY:
8011 if (i == 1 || i == 3)
8012 write_zero = true;
8013 else if (i == 2) {
8014 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], 1);
8015 def_val = false;
8016 }
8017 break;
8018 case TGSI_TEXTURE_2D:
8019 if (i == 2 || i == 3)
8020 write_zero = true;
8021 break;
8022 default:
8023 if (i == 3)
8024 write_zero = true;
8025 break;
8026 }
8027
8028 if (write_zero) {
8029 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8030 alu.src[0].value = 0;
8031 } else if (def_val) {
8032 r600_bytecode_src(&alu.src[0], &ctx->src[src_index], i);
8033 }
8034
8035 if (i == 3)
8036 alu.last = 1;
8037 alu.dst.write = 1;
8038 r = r600_bytecode_add_alu(ctx->bc, &alu);
8039 if (r)
8040 return r;
8041 }
8042 *idx_gpr = temp_reg;
8043 return 0;
8044 }
8045
8046 static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
8047 int temp_reg)
8048 {
8049 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8050 int r;
8051 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8052 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8053 r = single_alu_op2(ctx, ALU_OP1_MOV,
8054 temp_reg, 0,
8055 V_SQ_ALU_SRC_LITERAL, value >> 2,
8056 0, 0);
8057 if (r)
8058 return r;
8059 } else {
8060 struct r600_bytecode_alu alu;
8061 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8062 alu.op = ALU_OP2_LSHR_INT;
8063 r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
8064 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
8065 alu.src[1].value = 2;
8066 alu.dst.sel = temp_reg;
8067 alu.dst.write = 1;
8068 alu.last = 1;
8069 r = r600_bytecode_add_alu(ctx->bc, &alu);
8070 if (r)
8071 return r;
8072 }
8073 return 0;
8074 }
8075
8076 static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
8077 {
8078 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8079 /* have to work out the offset into the RAT immediate return buffer */
8080 struct r600_bytecode_vtx vtx;
8081 struct r600_bytecode_cf *cf;
8082 int r;
8083 int temp_reg = r600_get_temp(ctx);
8084 unsigned rat_index_mode;
8085 unsigned base;
8086
8087 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8088 base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
8089
8090 r = load_buffer_coord(ctx, 1, temp_reg);
8091 if (r)
8092 return r;
8093 ctx->bc->cf_last->barrier = 1;
8094 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8095 vtx.op = FETCH_OP_VFETCH;
8096 vtx.buffer_id = inst->Src[0].Register.Index + base;
8097 vtx.buffer_index_mode = rat_index_mode;
8098 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8099 vtx.src_gpr = temp_reg;
8100 vtx.src_sel_x = 0;
8101 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8102 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8103 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8104 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8105 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8106 vtx.num_format_all = 1;
8107 vtx.format_comp_all = 1;
8108 vtx.srf_mode_all = 0;
8109
8110 if (inst->Dst[0].Register.WriteMask & 8) {
8111 vtx.data_format = FMT_32_32_32_32;
8112 vtx.use_const_fields = 0;
8113 } else if (inst->Dst[0].Register.WriteMask & 4) {
8114 vtx.data_format = FMT_32_32_32;
8115 vtx.use_const_fields = 0;
8116 } else if (inst->Dst[0].Register.WriteMask & 2) {
8117 vtx.data_format = FMT_32_32;
8118 vtx.use_const_fields = 0;
8119 } else {
8120 vtx.data_format = FMT_32;
8121 vtx.use_const_fields = 0;
8122 }
8123
8124 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8125 if (r)
8126 return r;
8127 cf = ctx->bc->cf_last;
8128 cf->barrier = 1;
8129 return 0;
8130 }
8131
8132 static int tgsi_load_rat(struct r600_shader_ctx *ctx)
8133 {
8134 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8135 /* have to work out the offset into the RAT immediate return buffer */
8136 struct r600_bytecode_vtx vtx;
8137 struct r600_bytecode_cf *cf;
8138 int r;
8139 int idx_gpr;
8140 unsigned format, num_format, format_comp, endian;
8141 const struct util_format_description *desc;
8142 unsigned rat_index_mode;
8143 unsigned immed_base;
8144
8145 r = load_thread_id_gpr(ctx);
8146 if (r)
8147 return r;
8148
8149 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8150
8151 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8152 r = load_index_src(ctx, 1, &idx_gpr);
8153 if (r)
8154 return r;
8155
8156 if (rat_index_mode)
8157 egcm_load_index_reg(ctx->bc, 1, false);
8158
8159 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8160 cf = ctx->bc->cf_last;
8161
8162 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8163 cf->rat.inst = V_RAT_INST_NOP_RTN;
8164 cf->rat.index_mode = rat_index_mode;
8165 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8166 cf->output.gpr = ctx->thread_id_gpr;
8167 cf->output.index_gpr = idx_gpr;
8168 cf->output.comp_mask = 0xf;
8169 cf->output.burst_count = 1;
8170 cf->vpm = 1;
8171 cf->barrier = 1;
8172 cf->mark = 1;
8173 cf->output.elem_size = 0;
8174
8175 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8176 cf = ctx->bc->cf_last;
8177 cf->barrier = 1;
8178
8179 desc = util_format_description(inst->Memory.Format);
8180 r600_vertex_data_type(inst->Memory.Format,
8181 &format, &num_format, &format_comp, &endian);
8182 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8183 vtx.op = FETCH_OP_VFETCH;
8184 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8185 vtx.buffer_index_mode = rat_index_mode;
8186 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8187 vtx.src_gpr = ctx->thread_id_gpr;
8188 vtx.src_sel_x = 1;
8189 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8190 vtx.dst_sel_x = desc->swizzle[0];
8191 vtx.dst_sel_y = desc->swizzle[1];
8192 vtx.dst_sel_z = desc->swizzle[2];
8193 vtx.dst_sel_w = desc->swizzle[3];
8194 vtx.srf_mode_all = 1;
8195 vtx.data_format = format;
8196 vtx.num_format_all = num_format;
8197 vtx.format_comp_all = format_comp;
8198 vtx.endian = endian;
8199 vtx.offset = 0;
8200 vtx.mega_fetch_count = 3;
8201 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8202 if (r)
8203 return r;
8204 cf = ctx->bc->cf_last;
8205 cf->barrier = 1;
8206 return 0;
8207 }
8208
8209 static int tgsi_load_lds(struct r600_shader_ctx *ctx)
8210 {
8211 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8212 struct r600_bytecode_alu alu;
8213 int r;
8214 int temp_reg = r600_get_temp(ctx);
8215
8216 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8217 alu.op = ALU_OP1_MOV;
8218 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8219 alu.dst.sel = temp_reg;
8220 alu.dst.write = 1;
8221 alu.last = 1;
8222 r = r600_bytecode_add_alu(ctx->bc, &alu);
8223 if (r)
8224 return r;
8225
8226 r = do_lds_fetch_values(ctx, temp_reg,
8227 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
8228 if (r)
8229 return r;
8230 return 0;
8231 }
8232
8233 static int tgsi_load(struct r600_shader_ctx *ctx)
8234 {
8235 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8236 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8237 return tgsi_load_rat(ctx);
8238 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8239 return tgsi_load_gds(ctx);
8240 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8241 return tgsi_load_buffer(ctx);
8242 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8243 return tgsi_load_lds(ctx);
8244 return 0;
8245 }
8246
8247 static int tgsi_store_buffer_rat(struct r600_shader_ctx *ctx)
8248 {
8249 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8250 struct r600_bytecode_cf *cf;
8251 int r, i;
8252 unsigned rat_index_mode;
8253 int lasti;
8254 int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
8255
8256 r = load_buffer_coord(ctx, 0, treg2);
8257 if (r)
8258 return r;
8259
8260 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8261 if (rat_index_mode)
8262 egcm_load_index_reg(ctx->bc, 1, false);
8263
8264 for (i = 0; i <= 3; i++) {
8265 struct r600_bytecode_alu alu;
8266 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8267 alu.op = ALU_OP1_MOV;
8268 alu.dst.sel = temp_reg;
8269 alu.dst.chan = i;
8270 alu.src[0].sel = V_SQ_ALU_SRC_0;
8271 alu.last = (i == 3);
8272 alu.dst.write = 1;
8273 r = r600_bytecode_add_alu(ctx->bc, &alu);
8274 if (r)
8275 return r;
8276 }
8277
8278 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8279 for (i = 0; i <= lasti; i++) {
8280 struct r600_bytecode_alu alu;
8281 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
8282 continue;
8283
8284 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8285 temp_reg, 0,
8286 treg2, 0,
8287 V_SQ_ALU_SRC_LITERAL, i);
8288 if (r)
8289 return r;
8290
8291 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8292 alu.op = ALU_OP1_MOV;
8293 alu.dst.sel = ctx->temp_reg;
8294 alu.dst.chan = 0;
8295
8296 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8297 alu.last = 1;
8298 alu.dst.write = 1;
8299 r = r600_bytecode_add_alu(ctx->bc, &alu);
8300 if (r)
8301 return r;
8302
8303 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8304 cf = ctx->bc->cf_last;
8305
8306 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
8307 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8308 cf->rat.index_mode = rat_index_mode;
8309 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8310 cf->output.gpr = ctx->temp_reg;
8311 cf->output.index_gpr = temp_reg;
8312 cf->output.comp_mask = 1;
8313 cf->output.burst_count = 1;
8314 cf->vpm = 1;
8315 cf->barrier = 1;
8316 cf->output.elem_size = 0;
8317 }
8318 return 0;
8319 }
8320
8321 static int tgsi_store_rat(struct r600_shader_ctx *ctx)
8322 {
8323 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8324 struct r600_bytecode_cf *cf;
8325 bool src_requires_loading = false;
8326 int val_gpr, idx_gpr;
8327 int r, i;
8328 unsigned rat_index_mode;
8329
8330 rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8331
8332 r = load_index_src(ctx, 0, &idx_gpr);
8333 if (r)
8334 return r;
8335
8336 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
8337 src_requires_loading = true;
8338
8339 if (src_requires_loading) {
8340 struct r600_bytecode_alu alu;
8341 for (i = 0; i < 4; i++) {
8342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8343 alu.op = ALU_OP1_MOV;
8344 alu.dst.sel = ctx->temp_reg;
8345 alu.dst.chan = i;
8346
8347 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8348 if (i == 3)
8349 alu.last = 1;
8350 alu.dst.write = 1;
8351 r = r600_bytecode_add_alu(ctx->bc, &alu);
8352 if (r)
8353 return r;
8354 }
8355 val_gpr = ctx->temp_reg;
8356 } else
8357 val_gpr = tgsi_tex_get_src_gpr(ctx, 1);
8358 if (rat_index_mode)
8359 egcm_load_index_reg(ctx->bc, 1, false);
8360
8361 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8362 cf = ctx->bc->cf_last;
8363
8364 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
8365 cf->rat.inst = V_RAT_INST_STORE_TYPED;
8366 cf->rat.index_mode = rat_index_mode;
8367 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND;
8368 cf->output.gpr = val_gpr;
8369 cf->output.index_gpr = idx_gpr;
8370 cf->output.comp_mask = 0xf;
8371 cf->output.burst_count = 1;
8372 cf->vpm = 1;
8373 cf->barrier = 1;
8374 cf->output.elem_size = 0;
8375 return 0;
8376 }
8377
8378 static int tgsi_store_lds(struct r600_shader_ctx *ctx)
8379 {
8380 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8381 struct r600_bytecode_alu alu;
8382 int r, i, lasti;
8383 int write_mask = inst->Dst[0].Register.WriteMask;
8384 int temp_reg = r600_get_temp(ctx);
8385
8386 /* LDS write */
8387 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8388 alu.op = ALU_OP1_MOV;
8389 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
8390 alu.dst.sel = temp_reg;
8391 alu.dst.write = 1;
8392 alu.last = 1;
8393 r = r600_bytecode_add_alu(ctx->bc, &alu);
8394 if (r)
8395 return r;
8396
8397 lasti = tgsi_last_instruction(write_mask);
8398 for (i = 1; i <= lasti; i++) {
8399 if (!(write_mask & (1 << i)))
8400 continue;
8401 r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
8402 temp_reg, i,
8403 temp_reg, 0,
8404 V_SQ_ALU_SRC_LITERAL, 4 * i);
8405 if (r)
8406 return r;
8407 }
8408 for (i = 0; i <= lasti; i++) {
8409 if (!(write_mask & (1 << i)))
8410 continue;
8411
8412 if ((i == 0 && ((write_mask & 3) == 3)) ||
8413 (i == 2 && ((write_mask & 0xc) == 0xc))) {
8414 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8415 alu.op = LDS_OP3_LDS_WRITE_REL;
8416
8417 alu.src[0].sel = temp_reg;
8418 alu.src[0].chan = i;
8419 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8420 r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
8421 alu.last = 1;
8422 alu.is_lds_idx_op = true;
8423 alu.lds_idx = 1;
8424 r = r600_bytecode_add_alu(ctx->bc, &alu);
8425 if (r)
8426 return r;
8427 i += 1;
8428 continue;
8429 }
8430 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8431 alu.op = LDS_OP2_LDS_WRITE;
8432
8433 alu.src[0].sel = temp_reg;
8434 alu.src[0].chan = i;
8435 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
8436
8437 alu.last = 1;
8438 alu.is_lds_idx_op = true;
8439
8440 r = r600_bytecode_add_alu(ctx->bc, &alu);
8441 if (r)
8442 return r;
8443 }
8444 return 0;
8445 }
8446
8447 static int tgsi_store(struct r600_shader_ctx *ctx)
8448 {
8449 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8450 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
8451 return tgsi_store_buffer_rat(ctx);
8452 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
8453 return tgsi_store_lds(ctx);
8454 else
8455 return tgsi_store_rat(ctx);
8456 }
8457
8458 static int tgsi_atomic_op_rat(struct r600_shader_ctx *ctx)
8459 {
8460 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8461 /* have to work out the offset into the RAT immediate return buffer */
8462 struct r600_bytecode_alu alu;
8463 struct r600_bytecode_vtx vtx;
8464 struct r600_bytecode_cf *cf;
8465 int r;
8466 int idx_gpr;
8467 unsigned format, num_format, format_comp, endian;
8468 const struct util_format_description *desc;
8469 unsigned rat_index_mode;
8470 unsigned immed_base;
8471 unsigned rat_base;
8472
8473 immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
8474 rat_base = ctx->shader->rat_base;
8475
8476 r = load_thread_id_gpr(ctx);
8477 if (r)
8478 return r;
8479
8480 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
8481 immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8482 rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
8483
8484 r = load_buffer_coord(ctx, 1, ctx->temp_reg);
8485 if (r)
8486 return r;
8487 idx_gpr = ctx->temp_reg;
8488 } else {
8489 r = load_index_src(ctx, 1, &idx_gpr);
8490 if (r)
8491 return r;
8492 }
8493
8494 rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8495
8496 if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
8497 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8498 alu.op = ALU_OP1_MOV;
8499 alu.dst.sel = ctx->thread_id_gpr;
8500 alu.dst.chan = 0;
8501 alu.dst.write = 1;
8502 r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
8503 alu.last = 1;
8504 r = r600_bytecode_add_alu(ctx->bc, &alu);
8505 if (r)
8506 return r;
8507
8508 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8509 alu.op = ALU_OP1_MOV;
8510 alu.dst.sel = ctx->thread_id_gpr;
8511 if (ctx->bc->chip_class == CAYMAN)
8512 alu.dst.chan = 2;
8513 else
8514 alu.dst.chan = 3;
8515 alu.dst.write = 1;
8516 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8517 alu.last = 1;
8518 r = r600_bytecode_add_alu(ctx->bc, &alu);
8519 if (r)
8520 return r;
8521 } else {
8522 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8523 alu.op = ALU_OP1_MOV;
8524 alu.dst.sel = ctx->thread_id_gpr;
8525 alu.dst.chan = 0;
8526 alu.dst.write = 1;
8527 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8528 alu.last = 1;
8529 r = r600_bytecode_add_alu(ctx->bc, &alu);
8530 if (r)
8531 return r;
8532 }
8533
8534 if (rat_index_mode)
8535 egcm_load_index_reg(ctx->bc, 1, false);
8536 r600_bytecode_add_cfinst(ctx->bc, CF_OP_MEM_RAT);
8537 cf = ctx->bc->cf_last;
8538
8539 cf->rat.id = rat_base + inst->Src[0].Register.Index;
8540 cf->rat.inst = ctx->inst_info->op;
8541 cf->rat.index_mode = rat_index_mode;
8542 cf->output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND;
8543 cf->output.gpr = ctx->thread_id_gpr;
8544 cf->output.index_gpr = idx_gpr;
8545 cf->output.comp_mask = 0xf;
8546 cf->output.burst_count = 1;
8547 cf->vpm = 1;
8548 cf->barrier = 1;
8549 cf->mark = 1;
8550 cf->output.elem_size = 0;
8551 r600_bytecode_add_cfinst(ctx->bc, CF_OP_WAIT_ACK);
8552 cf = ctx->bc->cf_last;
8553 cf->barrier = 1;
8554 cf->cf_addr = 1;
8555
8556 memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
8557 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
8558 desc = util_format_description(inst->Memory.Format);
8559 r600_vertex_data_type(inst->Memory.Format,
8560 &format, &num_format, &format_comp, &endian);
8561 vtx.dst_sel_x = desc->swizzle[0];
8562 } else {
8563 format = FMT_32;
8564 num_format = 1;
8565 format_comp = 0;
8566 endian = 0;
8567 vtx.dst_sel_x = 0;
8568 }
8569 vtx.op = FETCH_OP_VFETCH;
8570 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8571 vtx.buffer_index_mode = rat_index_mode;
8572 vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
8573 vtx.src_gpr = ctx->thread_id_gpr;
8574 vtx.src_sel_x = 1;
8575 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8576 vtx.dst_sel_y = 7;
8577 vtx.dst_sel_z = 7;
8578 vtx.dst_sel_w = 7;
8579 vtx.use_const_fields = 0;
8580 vtx.srf_mode_all = 1;
8581 vtx.data_format = format;
8582 vtx.num_format_all = num_format;
8583 vtx.format_comp_all = format_comp;
8584 vtx.endian = endian;
8585 vtx.offset = 0;
8586 vtx.mega_fetch_count = 0xf;
8587 r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
8588 if (r)
8589 return r;
8590 cf = ctx->bc->cf_last;
8591 cf->vpm = 1;
8592 cf->barrier = 1;
8593 return 0;
8594 }
8595
8596 static int get_gds_op(int opcode)
8597 {
8598 switch (opcode) {
8599 case TGSI_OPCODE_ATOMUADD:
8600 return FETCH_OP_GDS_ADD_RET;
8601 case TGSI_OPCODE_ATOMAND:
8602 return FETCH_OP_GDS_AND_RET;
8603 case TGSI_OPCODE_ATOMOR:
8604 return FETCH_OP_GDS_OR_RET;
8605 case TGSI_OPCODE_ATOMXOR:
8606 return FETCH_OP_GDS_XOR_RET;
8607 case TGSI_OPCODE_ATOMUMIN:
8608 return FETCH_OP_GDS_MIN_UINT_RET;
8609 case TGSI_OPCODE_ATOMUMAX:
8610 return FETCH_OP_GDS_MAX_UINT_RET;
8611 case TGSI_OPCODE_ATOMXCHG:
8612 return FETCH_OP_GDS_XCHG_RET;
8613 case TGSI_OPCODE_ATOMCAS:
8614 return FETCH_OP_GDS_CMP_XCHG_RET;
8615 default:
8616 return -1;
8617 }
8618 }
8619
8620 static int tgsi_atomic_op_gds(struct r600_shader_ctx *ctx)
8621 {
8622 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8623 struct r600_bytecode_gds gds;
8624 struct r600_bytecode_alu alu;
8625 int gds_op = get_gds_op(inst->Instruction.Opcode);
8626 int r;
8627 int uav_id = 0;
8628 int uav_index_mode = 0;
8629 bool is_cm = (ctx->bc->chip_class == CAYMAN);
8630
8631 if (gds_op == -1) {
8632 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
8633 return -1;
8634 }
8635
8636 r = tgsi_set_gds_temp(ctx, &uav_id, &uav_index_mode);
8637 if (r)
8638 return r;
8639
8640 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
8641 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
8642 int abs_value = abs(value);
8643 if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
8644 gds_op = FETCH_OP_GDS_SUB_RET;
8645 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8646 alu.op = ALU_OP1_MOV;
8647 alu.dst.sel = ctx->temp_reg;
8648 alu.dst.chan = is_cm ? 1 : 0;
8649 alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
8650 alu.src[0].value = abs_value;
8651 alu.last = 1;
8652 alu.dst.write = 1;
8653 r = r600_bytecode_add_alu(ctx->bc, &alu);
8654 if (r)
8655 return r;
8656 } else {
8657 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8658 alu.op = ALU_OP1_MOV;
8659 alu.dst.sel = ctx->temp_reg;
8660 alu.dst.chan = is_cm ? 1 : 0;
8661 r600_bytecode_src(&alu.src[0], &ctx->src[2], 0);
8662 alu.last = 1;
8663 alu.dst.write = 1;
8664 r = r600_bytecode_add_alu(ctx->bc, &alu);
8665 if (r)
8666 return r;
8667 }
8668
8669
8670 memset(&gds, 0, sizeof(struct r600_bytecode_gds));
8671 gds.op = gds_op;
8672 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8673 gds.uav_id = is_cm ? 0 : uav_id;
8674 gds.uav_index_mode = is_cm ? 0 : uav_index_mode;
8675 gds.src_gpr = ctx->temp_reg;
8676 gds.src_gpr2 = 0;
8677 gds.src_sel_x = is_cm ? 0 : 4;
8678 gds.src_sel_y = is_cm ? 1 : 0;
8679 gds.src_sel_z = 7;
8680 gds.dst_sel_x = 0;
8681 gds.dst_sel_y = 7;
8682 gds.dst_sel_z = 7;
8683 gds.dst_sel_w = 7;
8684 gds.alloc_consume = !is_cm;
8685
8686 r = r600_bytecode_add_gds(ctx->bc, &gds);
8687 if (r)
8688 return r;
8689 ctx->bc->cf_last->vpm = 1;
8690 return 0;
8691 }
8692
8693 static int get_lds_op(int opcode)
8694 {
8695 switch (opcode) {
8696 case TGSI_OPCODE_ATOMUADD:
8697 return LDS_OP2_LDS_ADD_RET;
8698 case TGSI_OPCODE_ATOMAND:
8699 return LDS_OP2_LDS_AND_RET;
8700 case TGSI_OPCODE_ATOMOR:
8701 return LDS_OP2_LDS_OR_RET;
8702 case TGSI_OPCODE_ATOMXOR:
8703 return LDS_OP2_LDS_XOR_RET;
8704 case TGSI_OPCODE_ATOMUMIN:
8705 return LDS_OP2_LDS_MIN_UINT_RET;
8706 case TGSI_OPCODE_ATOMUMAX:
8707 return LDS_OP2_LDS_MAX_UINT_RET;
8708 case TGSI_OPCODE_ATOMIMIN:
8709 return LDS_OP2_LDS_MIN_INT_RET;
8710 case TGSI_OPCODE_ATOMIMAX:
8711 return LDS_OP2_LDS_MAX_INT_RET;
8712 case TGSI_OPCODE_ATOMXCHG:
8713 return LDS_OP2_LDS_XCHG_RET;
8714 case TGSI_OPCODE_ATOMCAS:
8715 return LDS_OP3_LDS_CMP_XCHG_RET;
8716 default:
8717 return -1;
8718 }
8719 }
8720
8721 static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
8722 {
8723 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8724 int lds_op = get_lds_op(inst->Instruction.Opcode);
8725 int r;
8726
8727 struct r600_bytecode_alu alu;
8728 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8729 alu.op = lds_op;
8730 alu.is_lds_idx_op = true;
8731 alu.last = 1;
8732 r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
8733 r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
8734 if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
8735 r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
8736 else
8737 alu.src[2].sel = V_SQ_ALU_SRC_0;
8738 r = r600_bytecode_add_alu(ctx->bc, &alu);
8739 if (r)
8740 return r;
8741
8742 /* then read from LDS_OQ_A_POP */
8743 memset(&alu, 0, sizeof(alu));
8744
8745 alu.op = ALU_OP1_MOV;
8746 alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
8747 alu.src[0].chan = 0;
8748 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
8749 alu.dst.write = 1;
8750 alu.last = 1;
8751 r = r600_bytecode_add_alu(ctx->bc, &alu);
8752 if (r)
8753 return r;
8754
8755 return 0;
8756 }
8757
8758 static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
8759 {
8760 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8761 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
8762 return tgsi_atomic_op_rat(ctx);
8763 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
8764 return tgsi_atomic_op_gds(ctx);
8765 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
8766 return tgsi_atomic_op_rat(ctx);
8767 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
8768 return tgsi_atomic_op_lds(ctx);
8769 return 0;
8770 }
8771
8772 static int tgsi_resq(struct r600_shader_ctx *ctx)
8773 {
8774 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8775 unsigned sampler_index_mode;
8776 struct r600_bytecode_tex tex;
8777 int r;
8778 boolean has_txq_cube_array_z = false;
8779
8780 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
8781 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
8782 if (ctx->bc->chip_class < EVERGREEN)
8783 ctx->shader->uses_tex_buffers = true;
8784 return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset);
8785 }
8786
8787 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
8788 inst->Dst[0].Register.WriteMask & 4) {
8789 ctx->shader->has_txq_cube_array_z_comp = true;
8790 has_txq_cube_array_z = true;
8791 }
8792
8793 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
8794 if (sampler_index_mode)
8795 egcm_load_index_reg(ctx->bc, 1, false);
8796
8797
8798 /* does this shader want a num layers from TXQ for a cube array? */
8799 if (has_txq_cube_array_z) {
8800 int id = tgsi_tex_get_src_gpr(ctx, 0) + ctx->shader->image_size_const_offset;
8801 struct r600_bytecode_alu alu;
8802
8803 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8804 alu.op = ALU_OP1_MOV;
8805
8806 alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
8807 /* with eg each dword is either number of cubes */
8808 alu.src[0].sel += id / 4;
8809 alu.src[0].chan = id % 4;
8810 alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
8811 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8812 alu.last = 1;
8813 r = r600_bytecode_add_alu(ctx->bc, &alu);
8814 if (r)
8815 return r;
8816 /* disable writemask from texture instruction */
8817 inst->Dst[0].Register.WriteMask &= ~4;
8818 }
8819 memset(&tex, 0, sizeof(struct r600_bytecode_tex));
8820 tex.op = ctx->inst_info->op;
8821 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
8822 tex.sampler_index_mode = sampler_index_mode;
8823 tex.resource_id = tex.sampler_id;
8824 tex.resource_index_mode = sampler_index_mode;
8825 tex.src_sel_x = 4;
8826 tex.src_sel_y = 4;
8827 tex.src_sel_z = 4;
8828 tex.src_sel_w = 4;
8829 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8830 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8831 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8832 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8833 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8834 r = r600_bytecode_add_tex(ctx->bc, &tex);
8835 if (r)
8836 return r;
8837
8838 return 0;
8839 }
8840
8841 static int tgsi_lrp(struct r600_shader_ctx *ctx)
8842 {
8843 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8844 struct r600_bytecode_alu alu;
8845 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8846 unsigned i, temp_regs[2];
8847 int r;
8848
8849 /* optimize if it's just an equal balance */
8850 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
8851 for (i = 0; i < lasti + 1; i++) {
8852 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8853 continue;
8854
8855 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8856 alu.op = ALU_OP2_ADD;
8857 r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
8858 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8859 alu.omod = 3;
8860 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8861 alu.dst.chan = i;
8862 if (i == lasti) {
8863 alu.last = 1;
8864 }
8865 r = r600_bytecode_add_alu(ctx->bc, &alu);
8866 if (r)
8867 return r;
8868 }
8869 return 0;
8870 }
8871
8872 /* 1 - src0 */
8873 for (i = 0; i < lasti + 1; i++) {
8874 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8875 continue;
8876
8877 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8878 alu.op = ALU_OP2_ADD;
8879 alu.src[0].sel = V_SQ_ALU_SRC_1;
8880 alu.src[0].chan = 0;
8881 r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
8882 r600_bytecode_src_toggle_neg(&alu.src[1]);
8883 alu.dst.sel = ctx->temp_reg;
8884 alu.dst.chan = i;
8885 if (i == lasti) {
8886 alu.last = 1;
8887 }
8888 alu.dst.write = 1;
8889 r = r600_bytecode_add_alu(ctx->bc, &alu);
8890 if (r)
8891 return r;
8892 }
8893
8894 /* (1 - src0) * src2 */
8895 for (i = 0; i < lasti + 1; i++) {
8896 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8897 continue;
8898
8899 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8900 alu.op = ALU_OP2_MUL;
8901 alu.src[0].sel = ctx->temp_reg;
8902 alu.src[0].chan = i;
8903 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
8904 alu.dst.sel = ctx->temp_reg;
8905 alu.dst.chan = i;
8906 if (i == lasti) {
8907 alu.last = 1;
8908 }
8909 alu.dst.write = 1;
8910 r = r600_bytecode_add_alu(ctx->bc, &alu);
8911 if (r)
8912 return r;
8913 }
8914
8915 /* src0 * src1 + (1 - src0) * src2 */
8916 if (ctx->src[0].abs)
8917 temp_regs[0] = r600_get_temp(ctx);
8918 else
8919 temp_regs[0] = 0;
8920 if (ctx->src[1].abs)
8921 temp_regs[1] = r600_get_temp(ctx);
8922 else
8923 temp_regs[1] = 0;
8924
8925 for (i = 0; i < lasti + 1; i++) {
8926 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8927 continue;
8928
8929 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8930 alu.op = ALU_OP3_MULADD;
8931 alu.is_op3 = 1;
8932 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8933 if (r)
8934 return r;
8935 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[1], &ctx->src[1]);
8936 if (r)
8937 return r;
8938 alu.src[2].sel = ctx->temp_reg;
8939 alu.src[2].chan = i;
8940
8941 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8942 alu.dst.chan = i;
8943 if (i == lasti) {
8944 alu.last = 1;
8945 }
8946 r = r600_bytecode_add_alu(ctx->bc, &alu);
8947 if (r)
8948 return r;
8949 }
8950 return 0;
8951 }
8952
8953 static int tgsi_cmp(struct r600_shader_ctx *ctx)
8954 {
8955 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8956 struct r600_bytecode_alu alu;
8957 int i, r, j;
8958 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
8959 int temp_regs[3];
8960 unsigned op;
8961
8962 if (ctx->src[0].abs && ctx->src[0].neg) {
8963 op = ALU_OP3_CNDE;
8964 ctx->src[0].abs = 0;
8965 ctx->src[0].neg = 0;
8966 } else {
8967 op = ALU_OP3_CNDGE;
8968 }
8969
8970 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
8971 temp_regs[j] = 0;
8972 if (ctx->src[j].abs)
8973 temp_regs[j] = r600_get_temp(ctx);
8974 }
8975
8976 for (i = 0; i < lasti + 1; i++) {
8977 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
8978 continue;
8979
8980 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
8981 alu.op = op;
8982 r = tgsi_make_src_for_op3(ctx, temp_regs[0], i, &alu.src[0], &ctx->src[0]);
8983 if (r)
8984 return r;
8985 r = tgsi_make_src_for_op3(ctx, temp_regs[2], i, &alu.src[1], &ctx->src[2]);
8986 if (r)
8987 return r;
8988 r = tgsi_make_src_for_op3(ctx, temp_regs[1], i, &alu.src[2], &ctx->src[1]);
8989 if (r)
8990 return r;
8991 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
8992 alu.dst.chan = i;
8993 alu.dst.write = 1;
8994 alu.is_op3 = 1;
8995 if (i == lasti)
8996 alu.last = 1;
8997 r = r600_bytecode_add_alu(ctx->bc, &alu);
8998 if (r)
8999 return r;
9000 }
9001 return 0;
9002 }
9003
9004 static int tgsi_ucmp(struct r600_shader_ctx *ctx)
9005 {
9006 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9007 struct r600_bytecode_alu alu;
9008 int i, r;
9009 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9010
9011 for (i = 0; i < lasti + 1; i++) {
9012 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9013 continue;
9014
9015 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9016 alu.op = ALU_OP3_CNDE_INT;
9017 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9018 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
9019 r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
9020 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9021 alu.dst.chan = i;
9022 alu.dst.write = 1;
9023 alu.is_op3 = 1;
9024 if (i == lasti)
9025 alu.last = 1;
9026 r = r600_bytecode_add_alu(ctx->bc, &alu);
9027 if (r)
9028 return r;
9029 }
9030 return 0;
9031 }
9032
9033 static int tgsi_exp(struct r600_shader_ctx *ctx)
9034 {
9035 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9036 struct r600_bytecode_alu alu;
9037 int r;
9038 unsigned i;
9039
9040 /* result.x = 2^floor(src); */
9041 if (inst->Dst[0].Register.WriteMask & 1) {
9042 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9043
9044 alu.op = ALU_OP1_FLOOR;
9045 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9046
9047 alu.dst.sel = ctx->temp_reg;
9048 alu.dst.chan = 0;
9049 alu.dst.write = 1;
9050 alu.last = 1;
9051 r = r600_bytecode_add_alu(ctx->bc, &alu);
9052 if (r)
9053 return r;
9054
9055 if (ctx->bc->chip_class == CAYMAN) {
9056 for (i = 0; i < 3; i++) {
9057 alu.op = ALU_OP1_EXP_IEEE;
9058 alu.src[0].sel = ctx->temp_reg;
9059 alu.src[0].chan = 0;
9060
9061 alu.dst.sel = ctx->temp_reg;
9062 alu.dst.chan = i;
9063 alu.dst.write = i == 0;
9064 alu.last = i == 2;
9065 r = r600_bytecode_add_alu(ctx->bc, &alu);
9066 if (r)
9067 return r;
9068 }
9069 } else {
9070 alu.op = ALU_OP1_EXP_IEEE;
9071 alu.src[0].sel = ctx->temp_reg;
9072 alu.src[0].chan = 0;
9073
9074 alu.dst.sel = ctx->temp_reg;
9075 alu.dst.chan = 0;
9076 alu.dst.write = 1;
9077 alu.last = 1;
9078 r = r600_bytecode_add_alu(ctx->bc, &alu);
9079 if (r)
9080 return r;
9081 }
9082 }
9083
9084 /* result.y = tmp - floor(tmp); */
9085 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9086 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9087
9088 alu.op = ALU_OP1_FRACT;
9089 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9090
9091 alu.dst.sel = ctx->temp_reg;
9092 #if 0
9093 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9094 if (r)
9095 return r;
9096 #endif
9097 alu.dst.write = 1;
9098 alu.dst.chan = 1;
9099
9100 alu.last = 1;
9101
9102 r = r600_bytecode_add_alu(ctx->bc, &alu);
9103 if (r)
9104 return r;
9105 }
9106
9107 /* result.z = RoughApprox2ToX(tmp);*/
9108 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9109 if (ctx->bc->chip_class == CAYMAN) {
9110 for (i = 0; i < 3; i++) {
9111 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9112 alu.op = ALU_OP1_EXP_IEEE;
9113 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9114
9115 alu.dst.sel = ctx->temp_reg;
9116 alu.dst.chan = i;
9117 if (i == 2) {
9118 alu.dst.write = 1;
9119 alu.last = 1;
9120 }
9121
9122 r = r600_bytecode_add_alu(ctx->bc, &alu);
9123 if (r)
9124 return r;
9125 }
9126 } else {
9127 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9128 alu.op = ALU_OP1_EXP_IEEE;
9129 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9130
9131 alu.dst.sel = ctx->temp_reg;
9132 alu.dst.write = 1;
9133 alu.dst.chan = 2;
9134
9135 alu.last = 1;
9136
9137 r = r600_bytecode_add_alu(ctx->bc, &alu);
9138 if (r)
9139 return r;
9140 }
9141 }
9142
9143 /* result.w = 1.0;*/
9144 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9145 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9146
9147 alu.op = ALU_OP1_MOV;
9148 alu.src[0].sel = V_SQ_ALU_SRC_1;
9149 alu.src[0].chan = 0;
9150
9151 alu.dst.sel = ctx->temp_reg;
9152 alu.dst.chan = 3;
9153 alu.dst.write = 1;
9154 alu.last = 1;
9155 r = r600_bytecode_add_alu(ctx->bc, &alu);
9156 if (r)
9157 return r;
9158 }
9159 return tgsi_helper_copy(ctx, inst);
9160 }
9161
9162 static int tgsi_log(struct r600_shader_ctx *ctx)
9163 {
9164 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9165 struct r600_bytecode_alu alu;
9166 int r;
9167 unsigned i;
9168
9169 /* result.x = floor(log2(|src|)); */
9170 if (inst->Dst[0].Register.WriteMask & 1) {
9171 if (ctx->bc->chip_class == CAYMAN) {
9172 for (i = 0; i < 3; i++) {
9173 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9174
9175 alu.op = ALU_OP1_LOG_IEEE;
9176 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9177 r600_bytecode_src_set_abs(&alu.src[0]);
9178
9179 alu.dst.sel = ctx->temp_reg;
9180 alu.dst.chan = i;
9181 if (i == 0)
9182 alu.dst.write = 1;
9183 if (i == 2)
9184 alu.last = 1;
9185 r = r600_bytecode_add_alu(ctx->bc, &alu);
9186 if (r)
9187 return r;
9188 }
9189
9190 } else {
9191 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9192
9193 alu.op = ALU_OP1_LOG_IEEE;
9194 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9195 r600_bytecode_src_set_abs(&alu.src[0]);
9196
9197 alu.dst.sel = ctx->temp_reg;
9198 alu.dst.chan = 0;
9199 alu.dst.write = 1;
9200 alu.last = 1;
9201 r = r600_bytecode_add_alu(ctx->bc, &alu);
9202 if (r)
9203 return r;
9204 }
9205
9206 alu.op = ALU_OP1_FLOOR;
9207 alu.src[0].sel = ctx->temp_reg;
9208 alu.src[0].chan = 0;
9209
9210 alu.dst.sel = ctx->temp_reg;
9211 alu.dst.chan = 0;
9212 alu.dst.write = 1;
9213 alu.last = 1;
9214
9215 r = r600_bytecode_add_alu(ctx->bc, &alu);
9216 if (r)
9217 return r;
9218 }
9219
9220 /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
9221 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9222
9223 if (ctx->bc->chip_class == CAYMAN) {
9224 for (i = 0; i < 3; i++) {
9225 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9226
9227 alu.op = ALU_OP1_LOG_IEEE;
9228 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9229 r600_bytecode_src_set_abs(&alu.src[0]);
9230
9231 alu.dst.sel = ctx->temp_reg;
9232 alu.dst.chan = i;
9233 if (i == 1)
9234 alu.dst.write = 1;
9235 if (i == 2)
9236 alu.last = 1;
9237
9238 r = r600_bytecode_add_alu(ctx->bc, &alu);
9239 if (r)
9240 return r;
9241 }
9242 } else {
9243 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9244
9245 alu.op = ALU_OP1_LOG_IEEE;
9246 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9247 r600_bytecode_src_set_abs(&alu.src[0]);
9248
9249 alu.dst.sel = ctx->temp_reg;
9250 alu.dst.chan = 1;
9251 alu.dst.write = 1;
9252 alu.last = 1;
9253
9254 r = r600_bytecode_add_alu(ctx->bc, &alu);
9255 if (r)
9256 return r;
9257 }
9258
9259 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9260
9261 alu.op = ALU_OP1_FLOOR;
9262 alu.src[0].sel = ctx->temp_reg;
9263 alu.src[0].chan = 1;
9264
9265 alu.dst.sel = ctx->temp_reg;
9266 alu.dst.chan = 1;
9267 alu.dst.write = 1;
9268 alu.last = 1;
9269
9270 r = r600_bytecode_add_alu(ctx->bc, &alu);
9271 if (r)
9272 return r;
9273
9274 if (ctx->bc->chip_class == CAYMAN) {
9275 for (i = 0; i < 3; i++) {
9276 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9277 alu.op = ALU_OP1_EXP_IEEE;
9278 alu.src[0].sel = ctx->temp_reg;
9279 alu.src[0].chan = 1;
9280
9281 alu.dst.sel = ctx->temp_reg;
9282 alu.dst.chan = i;
9283 if (i == 1)
9284 alu.dst.write = 1;
9285 if (i == 2)
9286 alu.last = 1;
9287
9288 r = r600_bytecode_add_alu(ctx->bc, &alu);
9289 if (r)
9290 return r;
9291 }
9292 } else {
9293 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9294 alu.op = ALU_OP1_EXP_IEEE;
9295 alu.src[0].sel = ctx->temp_reg;
9296 alu.src[0].chan = 1;
9297
9298 alu.dst.sel = ctx->temp_reg;
9299 alu.dst.chan = 1;
9300 alu.dst.write = 1;
9301 alu.last = 1;
9302
9303 r = r600_bytecode_add_alu(ctx->bc, &alu);
9304 if (r)
9305 return r;
9306 }
9307
9308 if (ctx->bc->chip_class == CAYMAN) {
9309 for (i = 0; i < 3; i++) {
9310 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9311 alu.op = ALU_OP1_RECIP_IEEE;
9312 alu.src[0].sel = ctx->temp_reg;
9313 alu.src[0].chan = 1;
9314
9315 alu.dst.sel = ctx->temp_reg;
9316 alu.dst.chan = i;
9317 if (i == 1)
9318 alu.dst.write = 1;
9319 if (i == 2)
9320 alu.last = 1;
9321
9322 r = r600_bytecode_add_alu(ctx->bc, &alu);
9323 if (r)
9324 return r;
9325 }
9326 } else {
9327 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9328 alu.op = ALU_OP1_RECIP_IEEE;
9329 alu.src[0].sel = ctx->temp_reg;
9330 alu.src[0].chan = 1;
9331
9332 alu.dst.sel = ctx->temp_reg;
9333 alu.dst.chan = 1;
9334 alu.dst.write = 1;
9335 alu.last = 1;
9336
9337 r = r600_bytecode_add_alu(ctx->bc, &alu);
9338 if (r)
9339 return r;
9340 }
9341
9342 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9343
9344 alu.op = ALU_OP2_MUL;
9345
9346 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9347 r600_bytecode_src_set_abs(&alu.src[0]);
9348
9349 alu.src[1].sel = ctx->temp_reg;
9350 alu.src[1].chan = 1;
9351
9352 alu.dst.sel = ctx->temp_reg;
9353 alu.dst.chan = 1;
9354 alu.dst.write = 1;
9355 alu.last = 1;
9356
9357 r = r600_bytecode_add_alu(ctx->bc, &alu);
9358 if (r)
9359 return r;
9360 }
9361
9362 /* result.z = log2(|src|);*/
9363 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
9364 if (ctx->bc->chip_class == CAYMAN) {
9365 for (i = 0; i < 3; i++) {
9366 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9367
9368 alu.op = ALU_OP1_LOG_IEEE;
9369 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9370 r600_bytecode_src_set_abs(&alu.src[0]);
9371
9372 alu.dst.sel = ctx->temp_reg;
9373 if (i == 2)
9374 alu.dst.write = 1;
9375 alu.dst.chan = i;
9376 if (i == 2)
9377 alu.last = 1;
9378
9379 r = r600_bytecode_add_alu(ctx->bc, &alu);
9380 if (r)
9381 return r;
9382 }
9383 } else {
9384 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9385
9386 alu.op = ALU_OP1_LOG_IEEE;
9387 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9388 r600_bytecode_src_set_abs(&alu.src[0]);
9389
9390 alu.dst.sel = ctx->temp_reg;
9391 alu.dst.write = 1;
9392 alu.dst.chan = 2;
9393 alu.last = 1;
9394
9395 r = r600_bytecode_add_alu(ctx->bc, &alu);
9396 if (r)
9397 return r;
9398 }
9399 }
9400
9401 /* result.w = 1.0; */
9402 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
9403 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9404
9405 alu.op = ALU_OP1_MOV;
9406 alu.src[0].sel = V_SQ_ALU_SRC_1;
9407 alu.src[0].chan = 0;
9408
9409 alu.dst.sel = ctx->temp_reg;
9410 alu.dst.chan = 3;
9411 alu.dst.write = 1;
9412 alu.last = 1;
9413
9414 r = r600_bytecode_add_alu(ctx->bc, &alu);
9415 if (r)
9416 return r;
9417 }
9418
9419 return tgsi_helper_copy(ctx, inst);
9420 }
9421
9422 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
9423 {
9424 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9425 struct r600_bytecode_alu alu;
9426 int r;
9427 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9428 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
9429
9430 assert(inst->Dst[0].Register.Index < 3);
9431 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9432
9433 switch (inst->Instruction.Opcode) {
9434 case TGSI_OPCODE_ARL:
9435 alu.op = ALU_OP1_FLT_TO_INT_FLOOR;
9436 break;
9437 case TGSI_OPCODE_ARR:
9438 alu.op = ALU_OP1_FLT_TO_INT;
9439 break;
9440 case TGSI_OPCODE_UARL:
9441 alu.op = ALU_OP1_MOV;
9442 break;
9443 default:
9444 assert(0);
9445 return -1;
9446 }
9447
9448 for (i = 0; i <= lasti; ++i) {
9449 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9450 continue;
9451 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9452 alu.last = i == lasti;
9453 alu.dst.sel = reg;
9454 alu.dst.chan = i;
9455 alu.dst.write = 1;
9456 r = r600_bytecode_add_alu(ctx->bc, &alu);
9457 if (r)
9458 return r;
9459 }
9460
9461 if (inst->Dst[0].Register.Index > 0)
9462 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
9463 else
9464 ctx->bc->ar_loaded = 0;
9465
9466 return 0;
9467 }
9468 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
9469 {
9470 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9471 struct r600_bytecode_alu alu;
9472 int r;
9473 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9474
9475 switch (inst->Instruction.Opcode) {
9476 case TGSI_OPCODE_ARL:
9477 memset(&alu, 0, sizeof(alu));
9478 alu.op = ALU_OP1_FLOOR;
9479 alu.dst.sel = ctx->bc->ar_reg;
9480 alu.dst.write = 1;
9481 for (i = 0; i <= lasti; ++i) {
9482 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9483 alu.dst.chan = i;
9484 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9485 alu.last = i == lasti;
9486 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9487 return r;
9488 }
9489 }
9490
9491 memset(&alu, 0, sizeof(alu));
9492 alu.op = ALU_OP1_FLT_TO_INT;
9493 alu.src[0].sel = ctx->bc->ar_reg;
9494 alu.dst.sel = ctx->bc->ar_reg;
9495 alu.dst.write = 1;
9496 /* FLT_TO_INT is trans-only on r600/r700 */
9497 alu.last = TRUE;
9498 for (i = 0; i <= lasti; ++i) {
9499 alu.dst.chan = i;
9500 alu.src[0].chan = i;
9501 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9502 return r;
9503 }
9504 break;
9505 case TGSI_OPCODE_ARR:
9506 memset(&alu, 0, sizeof(alu));
9507 alu.op = ALU_OP1_FLT_TO_INT;
9508 alu.dst.sel = ctx->bc->ar_reg;
9509 alu.dst.write = 1;
9510 /* FLT_TO_INT is trans-only on r600/r700 */
9511 alu.last = TRUE;
9512 for (i = 0; i <= lasti; ++i) {
9513 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9514 alu.dst.chan = i;
9515 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9516 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9517 return r;
9518 }
9519 }
9520 break;
9521 case TGSI_OPCODE_UARL:
9522 memset(&alu, 0, sizeof(alu));
9523 alu.op = ALU_OP1_MOV;
9524 alu.dst.sel = ctx->bc->ar_reg;
9525 alu.dst.write = 1;
9526 for (i = 0; i <= lasti; ++i) {
9527 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
9528 alu.dst.chan = i;
9529 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9530 alu.last = i == lasti;
9531 if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
9532 return r;
9533 }
9534 }
9535 break;
9536 default:
9537 assert(0);
9538 return -1;
9539 }
9540
9541 ctx->bc->ar_loaded = 0;
9542 return 0;
9543 }
9544
9545 static int tgsi_opdst(struct r600_shader_ctx *ctx)
9546 {
9547 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9548 struct r600_bytecode_alu alu;
9549 int i, r = 0;
9550
9551 for (i = 0; i < 4; i++) {
9552 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9553
9554 alu.op = ALU_OP2_MUL;
9555 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9556
9557 if (i == 0 || i == 3) {
9558 alu.src[0].sel = V_SQ_ALU_SRC_1;
9559 } else {
9560 r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
9561 }
9562
9563 if (i == 0 || i == 2) {
9564 alu.src[1].sel = V_SQ_ALU_SRC_1;
9565 } else {
9566 r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
9567 }
9568 if (i == 3)
9569 alu.last = 1;
9570 r = r600_bytecode_add_alu(ctx->bc, &alu);
9571 if (r)
9572 return r;
9573 }
9574 return 0;
9575 }
9576
9577 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
9578 {
9579 struct r600_bytecode_alu alu;
9580 int r;
9581
9582 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9583 alu.op = opcode;
9584 alu.execute_mask = 1;
9585 alu.update_pred = 1;
9586
9587 alu.dst.sel = ctx->temp_reg;
9588 alu.dst.write = 1;
9589 alu.dst.chan = 0;
9590
9591 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
9592 alu.src[1].sel = V_SQ_ALU_SRC_0;
9593 alu.src[1].chan = 0;
9594
9595 alu.last = 1;
9596
9597 r = r600_bytecode_add_alu_type(ctx->bc, &alu, alu_type);
9598 if (r)
9599 return r;
9600 return 0;
9601 }
9602
9603 static int pops(struct r600_shader_ctx *ctx, int pops)
9604 {
9605 unsigned force_pop = ctx->bc->force_add_cf;
9606
9607 if (!force_pop) {
9608 int alu_pop = 3;
9609 if (ctx->bc->cf_last) {
9610 if (ctx->bc->cf_last->op == CF_OP_ALU)
9611 alu_pop = 0;
9612 else if (ctx->bc->cf_last->op == CF_OP_ALU_POP_AFTER)
9613 alu_pop = 1;
9614 }
9615 alu_pop += pops;
9616 if (alu_pop == 1) {
9617 ctx->bc->cf_last->op = CF_OP_ALU_POP_AFTER;
9618 ctx->bc->force_add_cf = 1;
9619 } else if (alu_pop == 2) {
9620 ctx->bc->cf_last->op = CF_OP_ALU_POP2_AFTER;
9621 ctx->bc->force_add_cf = 1;
9622 } else {
9623 force_pop = 1;
9624 }
9625 }
9626
9627 if (force_pop) {
9628 r600_bytecode_add_cfinst(ctx->bc, CF_OP_POP);
9629 ctx->bc->cf_last->pop_count = pops;
9630 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9631 }
9632
9633 return 0;
9634 }
9635
9636 static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
9637 unsigned reason)
9638 {
9639 struct r600_stack_info *stack = &ctx->bc->stack;
9640 unsigned elements;
9641 int entries;
9642
9643 unsigned entry_size = stack->entry_size;
9644
9645 elements = (stack->loop + stack->push_wqm ) * entry_size;
9646 elements += stack->push;
9647
9648 switch (ctx->bc->chip_class) {
9649 case R600:
9650 case R700:
9651 /* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 elements on
9652 * the stack must be reserved to hold the current active/continue
9653 * masks */
9654 if (reason == FC_PUSH_VPM) {
9655 elements += 2;
9656 }
9657 break;
9658
9659 case CAYMAN:
9660 /* r9xx: any stack operation on empty stack consumes 2 additional
9661 * elements */
9662 elements += 2;
9663
9664 /* fallthrough */
9665 /* FIXME: do the two elements added above cover the cases for the
9666 * r8xx+ below? */
9667
9668 case EVERGREEN:
9669 /* r8xx+: 2 extra elements are not always required, but one extra
9670 * element must be added for each of the following cases:
9671 * 1. There is an ALU_ELSE_AFTER instruction at the point of greatest
9672 * stack usage.
9673 * (Currently we don't use ALU_ELSE_AFTER.)
9674 * 2. There are LOOP/WQM frames on the stack when any flavor of non-WQM
9675 * PUSH instruction executed.
9676 *
9677 * NOTE: it seems we also need to reserve additional element in some
9678 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
9679 * then STACK_SIZE should be 2 instead of 1 */
9680 if (reason == FC_PUSH_VPM) {
9681 elements += 1;
9682 }
9683 break;
9684
9685 default:
9686 assert(0);
9687 break;
9688 }
9689
9690 /* NOTE: it seems STACK_SIZE is interpreted by hw as if entry_size is 4
9691 * for all chips, so we use 4 in the final formula, not the real entry_size
9692 * for the chip */
9693 entry_size = 4;
9694
9695 entries = (elements + (entry_size - 1)) / entry_size;
9696
9697 if (entries > stack->max_entries)
9698 stack->max_entries = entries;
9699 }
9700
9701 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
9702 {
9703 switch(reason) {
9704 case FC_PUSH_VPM:
9705 --ctx->bc->stack.push;
9706 assert(ctx->bc->stack.push >= 0);
9707 break;
9708 case FC_PUSH_WQM:
9709 --ctx->bc->stack.push_wqm;
9710 assert(ctx->bc->stack.push_wqm >= 0);
9711 break;
9712 case FC_LOOP:
9713 --ctx->bc->stack.loop;
9714 assert(ctx->bc->stack.loop >= 0);
9715 break;
9716 default:
9717 assert(0);
9718 break;
9719 }
9720 }
9721
9722 static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
9723 {
9724 switch (reason) {
9725 case FC_PUSH_VPM:
9726 ++ctx->bc->stack.push;
9727 break;
9728 case FC_PUSH_WQM:
9729 ++ctx->bc->stack.push_wqm;
9730 case FC_LOOP:
9731 ++ctx->bc->stack.loop;
9732 break;
9733 default:
9734 assert(0);
9735 }
9736
9737 callstack_update_max_depth(ctx, reason);
9738 }
9739
9740 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
9741 {
9742 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
9743
9744 sp->mid = realloc((void *)sp->mid,
9745 sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
9746 sp->mid[sp->num_mid] = ctx->bc->cf_last;
9747 sp->num_mid++;
9748 }
9749
9750 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
9751 {
9752 assert(ctx->bc->fc_sp < ARRAY_SIZE(ctx->bc->fc_stack));
9753 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
9754 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
9755 ctx->bc->fc_sp++;
9756 }
9757
9758 static void fc_poplevel(struct r600_shader_ctx *ctx)
9759 {
9760 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp - 1];
9761 free(sp->mid);
9762 sp->mid = NULL;
9763 sp->num_mid = 0;
9764 sp->start = NULL;
9765 sp->type = 0;
9766 ctx->bc->fc_sp--;
9767 }
9768
9769 #if 0
9770 static int emit_return(struct r600_shader_ctx *ctx)
9771 {
9772 r600_bytecode_add_cfinst(ctx->bc, CF_OP_RETURN));
9773 return 0;
9774 }
9775
9776 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
9777 {
9778
9779 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP));
9780 ctx->bc->cf_last->pop_count = pops;
9781 /* XXX work out offset */
9782 return 0;
9783 }
9784
9785 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
9786 {
9787 return 0;
9788 }
9789
9790 static void emit_testflag(struct r600_shader_ctx *ctx)
9791 {
9792
9793 }
9794
9795 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
9796 {
9797 emit_testflag(ctx);
9798 emit_jump_to_offset(ctx, 1, 4);
9799 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
9800 pops(ctx, ifidx + 1);
9801 emit_return(ctx);
9802 }
9803
9804 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
9805 {
9806 emit_testflag(ctx);
9807
9808 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9809 ctx->bc->cf_last->pop_count = 1;
9810
9811 fc_set_mid(ctx, fc_sp);
9812
9813 pops(ctx, 1);
9814 }
9815 #endif
9816
9817 static int emit_if(struct r600_shader_ctx *ctx, int opcode)
9818 {
9819 int alu_type = CF_OP_ALU_PUSH_BEFORE;
9820
9821 /* There is a hardware bug on Cayman where a BREAK/CONTINUE followed by
9822 * LOOP_STARTxxx for nested loops may put the branch stack into a state
9823 * such that ALU_PUSH_BEFORE doesn't work as expected. Workaround this
9824 * by replacing the ALU_PUSH_BEFORE with a PUSH + ALU */
9825 if (ctx->bc->chip_class == CAYMAN && ctx->bc->stack.loop > 1) {
9826 r600_bytecode_add_cfinst(ctx->bc, CF_OP_PUSH);
9827 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
9828 alu_type = CF_OP_ALU;
9829 }
9830
9831 emit_logic_pred(ctx, opcode, alu_type);
9832
9833 r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
9834
9835 fc_pushlevel(ctx, FC_IF);
9836
9837 callstack_push(ctx, FC_PUSH_VPM);
9838 return 0;
9839 }
9840
9841 static int tgsi_if(struct r600_shader_ctx *ctx)
9842 {
9843 return emit_if(ctx, ALU_OP2_PRED_SETNE);
9844 }
9845
9846 static int tgsi_uif(struct r600_shader_ctx *ctx)
9847 {
9848 return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
9849 }
9850
9851 static int tgsi_else(struct r600_shader_ctx *ctx)
9852 {
9853 r600_bytecode_add_cfinst(ctx->bc, CF_OP_ELSE);
9854 ctx->bc->cf_last->pop_count = 1;
9855
9856 fc_set_mid(ctx, ctx->bc->fc_sp - 1);
9857 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id;
9858 return 0;
9859 }
9860
9861 static int tgsi_endif(struct r600_shader_ctx *ctx)
9862 {
9863 pops(ctx, 1);
9864 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
9865 R600_ERR("if/endif unbalanced in shader\n");
9866 return -1;
9867 }
9868
9869 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
9870 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9871 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
9872 } else {
9873 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
9874 }
9875 fc_poplevel(ctx);
9876
9877 callstack_pop(ctx, FC_PUSH_VPM);
9878 return 0;
9879 }
9880
9881 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
9882 {
9883 /* LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not
9884 * limited to 4096 iterations, like the other LOOP_* instructions. */
9885 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_START_DX10);
9886
9887 fc_pushlevel(ctx, FC_LOOP);
9888
9889 /* check stack depth */
9890 callstack_push(ctx, FC_LOOP);
9891 return 0;
9892 }
9893
9894 static int tgsi_endloop(struct r600_shader_ctx *ctx)
9895 {
9896 int i;
9897
9898 r600_bytecode_add_cfinst(ctx->bc, CF_OP_LOOP_END);
9899
9900 if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_LOOP) {
9901 R600_ERR("loop/endloop in shader code are not paired.\n");
9902 return -EINVAL;
9903 }
9904
9905 /* fixup loop pointers - from r600isa
9906 LOOP END points to CF after LOOP START,
9907 LOOP START point to CF after LOOP END
9908 BRK/CONT point to LOOP END CF
9909 */
9910 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->id + 2;
9911
9912 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = ctx->bc->cf_last->id + 2;
9913
9914 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp - 1].num_mid; i++) {
9915 ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[i]->cf_addr = ctx->bc->cf_last->id;
9916 }
9917 /* XXX add LOOPRET support */
9918 fc_poplevel(ctx);
9919 callstack_pop(ctx, FC_LOOP);
9920 return 0;
9921 }
9922
9923 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
9924 {
9925 unsigned int fscp;
9926
9927 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
9928 {
9929 if (FC_LOOP == ctx->bc->fc_stack[fscp - 1].type)
9930 break;
9931 }
9932
9933 if (fscp == 0) {
9934 R600_ERR("Break not inside loop/endloop pair\n");
9935 return -EINVAL;
9936 }
9937
9938 r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9939
9940 fc_set_mid(ctx, fscp - 1);
9941
9942 return 0;
9943 }
9944
9945 static int tgsi_gs_emit(struct r600_shader_ctx *ctx)
9946 {
9947 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9948 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
9949 int r;
9950
9951 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9952 emit_gs_ring_writes(ctx, ctx->gs_stream_output_info, stream, TRUE);
9953
9954 r = r600_bytecode_add_cfinst(ctx->bc, ctx->inst_info->op);
9955 if (!r) {
9956 ctx->bc->cf_last->count = stream; // Count field for CUT/EMIT_VERTEX indicates which stream
9957 if (ctx->inst_info->op == CF_OP_EMIT_VERTEX)
9958 return emit_inc_ring_offset(ctx, stream, TRUE);
9959 }
9960 return r;
9961 }
9962
9963 static int tgsi_umad(struct r600_shader_ctx *ctx)
9964 {
9965 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9966 struct r600_bytecode_alu alu;
9967 int i, j, k, r;
9968 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9969
9970 /* src0 * src1 */
9971 for (i = 0; i < lasti + 1; i++) {
9972 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9973 continue;
9974
9975 if (ctx->bc->chip_class == CAYMAN) {
9976 for (j = 0 ; j < 4; j++) {
9977 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9978
9979 alu.op = ALU_OP2_MULLO_UINT;
9980 for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
9981 r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
9982 }
9983 alu.dst.chan = j;
9984 alu.dst.sel = ctx->temp_reg;
9985 alu.dst.write = (j == i);
9986 if (j == 3)
9987 alu.last = 1;
9988 r = r600_bytecode_add_alu(ctx->bc, &alu);
9989 if (r)
9990 return r;
9991 }
9992 } else {
9993 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
9994
9995 alu.dst.chan = i;
9996 alu.dst.sel = ctx->temp_reg;
9997 alu.dst.write = 1;
9998
9999 alu.op = ALU_OP2_MULLO_UINT;
10000 for (j = 0; j < 2; j++) {
10001 r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
10002 }
10003
10004 alu.last = 1;
10005 r = r600_bytecode_add_alu(ctx->bc, &alu);
10006 if (r)
10007 return r;
10008 }
10009 }
10010
10011
10012 for (i = 0; i < lasti + 1; i++) {
10013 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10014 continue;
10015
10016 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10017 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10018
10019 alu.op = ALU_OP2_ADD_INT;
10020
10021 alu.src[0].sel = ctx->temp_reg;
10022 alu.src[0].chan = i;
10023
10024 r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
10025 if (i == lasti) {
10026 alu.last = 1;
10027 }
10028 r = r600_bytecode_add_alu(ctx->bc, &alu);
10029 if (r)
10030 return r;
10031 }
10032 return 0;
10033 }
10034
10035 static int tgsi_pk2h(struct r600_shader_ctx *ctx)
10036 {
10037 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10038 struct r600_bytecode_alu alu;
10039 int r, i;
10040 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10041
10042 /* temp.xy = f32_to_f16(src) */
10043 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10044 alu.op = ALU_OP1_FLT32_TO_FLT16;
10045 alu.dst.chan = 0;
10046 alu.dst.sel = ctx->temp_reg;
10047 alu.dst.write = 1;
10048 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10049 r = r600_bytecode_add_alu(ctx->bc, &alu);
10050 if (r)
10051 return r;
10052 alu.dst.chan = 1;
10053 r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
10054 alu.last = 1;
10055 r = r600_bytecode_add_alu(ctx->bc, &alu);
10056 if (r)
10057 return r;
10058
10059 /* dst.x = temp.y * 0x10000 + temp.x */
10060 for (i = 0; i < lasti + 1; i++) {
10061 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10062 continue;
10063
10064 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10065 alu.op = ALU_OP3_MULADD_UINT24;
10066 alu.is_op3 = 1;
10067 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10068 alu.last = i == lasti;
10069 alu.src[0].sel = ctx->temp_reg;
10070 alu.src[0].chan = 1;
10071 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10072 alu.src[1].value = 0x10000;
10073 alu.src[2].sel = ctx->temp_reg;
10074 alu.src[2].chan = 0;
10075 r = r600_bytecode_add_alu(ctx->bc, &alu);
10076 if (r)
10077 return r;
10078 }
10079
10080 return 0;
10081 }
10082
10083 static int tgsi_up2h(struct r600_shader_ctx *ctx)
10084 {
10085 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10086 struct r600_bytecode_alu alu;
10087 int r, i;
10088 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10089
10090 /* temp.x = src.x */
10091 /* note: no need to mask out the high bits */
10092 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10093 alu.op = ALU_OP1_MOV;
10094 alu.dst.chan = 0;
10095 alu.dst.sel = ctx->temp_reg;
10096 alu.dst.write = 1;
10097 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10098 r = r600_bytecode_add_alu(ctx->bc, &alu);
10099 if (r)
10100 return r;
10101
10102 /* temp.y = src.x >> 16 */
10103 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10104 alu.op = ALU_OP2_LSHR_INT;
10105 alu.dst.chan = 1;
10106 alu.dst.sel = ctx->temp_reg;
10107 alu.dst.write = 1;
10108 r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
10109 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10110 alu.src[1].value = 16;
10111 alu.last = 1;
10112 r = r600_bytecode_add_alu(ctx->bc, &alu);
10113 if (r)
10114 return r;
10115
10116 /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
10117 for (i = 0; i < lasti + 1; i++) {
10118 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10119 continue;
10120 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10121 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10122 alu.op = ALU_OP1_FLT16_TO_FLT32;
10123 alu.src[0].sel = ctx->temp_reg;
10124 alu.src[0].chan = i % 2;
10125 alu.last = i == lasti;
10126 r = r600_bytecode_add_alu(ctx->bc, &alu);
10127 if (r)
10128 return r;
10129 }
10130
10131 return 0;
10132 }
10133
10134 static int tgsi_bfe(struct r600_shader_ctx *ctx)
10135 {
10136 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10137 struct r600_bytecode_alu alu;
10138 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10139 int r, i;
10140 int dst = -1;
10141
10142 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10143 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10144 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10145 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10146 dst = r600_get_temp(ctx);
10147
10148 r = tgsi_op3_dst(ctx, dst);
10149 if (r)
10150 return r;
10151
10152 for (i = 0; i < lasti + 1; i++) {
10153 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10154 alu.op = ALU_OP2_SETGE_INT;
10155 r600_bytecode_src(&alu.src[0], &ctx->src[2], i);
10156 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
10157 alu.src[1].value = 32;
10158 alu.dst.sel = ctx->temp_reg;
10159 alu.dst.chan = i;
10160 alu.dst.write = 1;
10161 if (i == lasti)
10162 alu.last = 1;
10163 r = r600_bytecode_add_alu(ctx->bc, &alu);
10164 if (r)
10165 return r;
10166 }
10167
10168 for (i = 0; i < lasti + 1; i++) {
10169 memset(&alu, 0, sizeof(struct r600_bytecode_alu));
10170 alu.op = ALU_OP3_CNDE_INT;
10171 alu.is_op3 = 1;
10172 alu.src[0].sel = ctx->temp_reg;
10173 alu.src[0].chan = i;
10174
10175 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10176 if (dst != -1)
10177 alu.src[1].sel = dst;
10178 else
10179 alu.src[1].sel = alu.dst.sel;
10180 alu.src[1].chan = i;
10181 r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
10182 alu.dst.write = 1;
10183 if (i == lasti)
10184 alu.last = 1;
10185 r = r600_bytecode_add_alu(ctx->bc, &alu);
10186 if (r)
10187 return r;
10188 }
10189
10190 return 0;
10191 }
10192
10193 static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
10194 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
10195 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10196 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10197
10198 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
10199
10200 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
10201 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10202 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10203 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10204 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10205 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10206 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10207 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10208 /* MIN_DX10 returns non-nan result if one src is NaN, MIN returns NaN */
10209 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10210 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10211 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10212 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10213 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10214 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10215 [TGSI_OPCODE_FMA] = { ALU_OP0_NOP, tgsi_unsupported},
10216 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
10217 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10218 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10219 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10220 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10221 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10222 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10223 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10224 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
10225 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
10226 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
10227 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10228 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10229 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10230 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10231 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10232 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
10233 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10234 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10235 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10236 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_unsupported},
10237 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10238 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10239 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10240 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10241 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10242 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10243 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10244 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
10245 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10246 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10247 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10248 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10249 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10250 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10251 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_unsupported},
10252 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10253 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10254 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10255 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10256 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10257 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_r600_arl},
10258 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10259 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10260 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10261 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10262 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10263 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10264 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10265 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10266 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10267 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10268 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10269 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10270 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10271 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10272 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10273 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10274 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10275 [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
10276 [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported},
10277 [81] = { ALU_OP0_NOP, tgsi_unsupported},
10278 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10279 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10280 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
10281 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10282 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10283 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2_trans},
10284 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10285 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10286 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10287 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10288 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10289 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10290 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10291 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10292 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10293 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10294 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10295 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10296 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10297 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10298 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10299 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10300 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10301 [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported},
10302 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10303 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10304 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10305 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10306 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10307 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10308 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_NOP, tgsi_unsupported},
10309 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10310 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10311 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10312 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10313 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10314 [TGSI_OPCODE_DFMA] = { ALU_OP0_NOP, tgsi_unsupported},
10315 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2_trans},
10316 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10317 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10318 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10319 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10320 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10321 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2_trans},
10322 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10323 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2_trans},
10324 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
10325 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10326 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10327 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10328 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10329 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10330 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10331 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
10332 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10333 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10334 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2_trans},
10335 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10336 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2_swap},
10337 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10338 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10339 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10340 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10341 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10342 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10343 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10344 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10345 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10346 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10347 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10348 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10349 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10350 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10351 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10352 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10353 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_r600_arl},
10354 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10355 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10356 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10357 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_unsupported},
10358 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_unsupported},
10359 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10360 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10361 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10362 [TGSI_OPCODE_BARRIER] = { ALU_OP0_NOP, tgsi_unsupported},
10363 [TGSI_OPCODE_ATOMUADD] = { ALU_OP0_NOP, tgsi_unsupported},
10364 [TGSI_OPCODE_ATOMXCHG] = { ALU_OP0_NOP, tgsi_unsupported},
10365 [TGSI_OPCODE_ATOMCAS] = { ALU_OP0_NOP, tgsi_unsupported},
10366 [TGSI_OPCODE_ATOMAND] = { ALU_OP0_NOP, tgsi_unsupported},
10367 [TGSI_OPCODE_ATOMOR] = { ALU_OP0_NOP, tgsi_unsupported},
10368 [TGSI_OPCODE_ATOMXOR] = { ALU_OP0_NOP, tgsi_unsupported},
10369 [TGSI_OPCODE_ATOMUMIN] = { ALU_OP0_NOP, tgsi_unsupported},
10370 [TGSI_OPCODE_ATOMUMAX] = { ALU_OP0_NOP, tgsi_unsupported},
10371 [TGSI_OPCODE_ATOMIMIN] = { ALU_OP0_NOP, tgsi_unsupported},
10372 [TGSI_OPCODE_ATOMIMAX] = { ALU_OP0_NOP, tgsi_unsupported},
10373 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10374 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10375 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10376 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
10377 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
10378 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_unsupported},
10379 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_unsupported},
10380 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_unsupported},
10381 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_unsupported},
10382 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_unsupported},
10383 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_unsupported},
10384 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_unsupported},
10385 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_unsupported},
10386 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_unsupported},
10387 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_unsupported},
10388 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_unsupported},
10389 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_unsupported},
10390 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_unsupported},
10391 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10392 };
10393
10394 static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
10395 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10396 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10397 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10398 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, tgsi_trans_srcx_replicate},
10399 [TGSI_OPCODE_RSQ] = { ALU_OP0_NOP, tgsi_rsq},
10400 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10401 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10402 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10403 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10404 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10405 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10406 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10407 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10408 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10409 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10410 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10411 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10412 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10413 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10414 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
10415 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10416 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10417 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10418 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10419 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10420 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10421 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10422 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, tgsi_trans_srcx_replicate},
10423 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, tgsi_trans_srcx_replicate},
10424 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
10425 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10426 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10427 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10428 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10429 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10430 [TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
10431 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10432 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10433 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10434 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10435 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10436 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10437 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10438 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10439 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10440 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10441 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10442 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, tgsi_trig},
10443 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10444 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10445 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10446 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10447 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10448 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10449 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10450 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10451 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10452 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10453 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10454 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10455 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10456 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10457 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10458 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10459 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10460 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10461 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10462 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10463 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10464 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10465 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10466 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10467 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10468 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10469 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10470 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10471 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10472 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10473 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10474 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10475 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10476 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10477 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans},
10478 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10479 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10480 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10481 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10482 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10483 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10484 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10485 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10486 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10487 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10488 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10489 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10490 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10491 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10492 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10493 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10494 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10495 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10496 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10497 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10498 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10499 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10500 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10501 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10502 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10503 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10504 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10505 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10506 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10507 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10508 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10509 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10510 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10511 /* Refer below for TGSI_OPCODE_DFMA */
10512 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_f2i},
10513 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10514 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10515 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10516 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10517 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10518 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10519 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10520 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_f2i},
10521 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2_trans},
10522 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10523 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10524 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10525 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10526 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10527 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10528 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_UINT, tgsi_op2_trans},
10529 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10530 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10531 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10532 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10533 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10534 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10535 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10536 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10537 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10538 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10539 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10540 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10541 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10542 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10543 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10544 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10545 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10546 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10547 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10548 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10549 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10550 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10551 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10552 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10553 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10554 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10555 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10556 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10557 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10558 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10559 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10560 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10561 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10562 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10563 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10564 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10565 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10566 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10567 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10568 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10569 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10570 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10571 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10572 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10573 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, tgsi_op2_trans},
10574 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, tgsi_op2_trans},
10575 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10576 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10577 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10578 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10579 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10580 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10581 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10582 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10583 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10584 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10585 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10586 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10587 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10588 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10589 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10590 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10591 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10592 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10593 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10594 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10595 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10596 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10597 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10598 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10599 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10600 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10601 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10602 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10603 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10604 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10605 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10606 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10607 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10608 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10609 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10610 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10611 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10612 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10613 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10614 };
10615
10616 static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
10617 [TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_eg_arl},
10618 [TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
10619 [TGSI_OPCODE_LIT] = { ALU_OP0_NOP, tgsi_lit},
10620 [TGSI_OPCODE_RCP] = { ALU_OP1_RECIP_IEEE, cayman_emit_float_instr},
10621 [TGSI_OPCODE_RSQ] = { ALU_OP1_RECIPSQRT_IEEE, cayman_emit_float_instr},
10622 [TGSI_OPCODE_EXP] = { ALU_OP0_NOP, tgsi_exp},
10623 [TGSI_OPCODE_LOG] = { ALU_OP0_NOP, tgsi_log},
10624 [TGSI_OPCODE_MUL] = { ALU_OP2_MUL_IEEE, tgsi_op2},
10625 [TGSI_OPCODE_ADD] = { ALU_OP2_ADD, tgsi_op2},
10626 [TGSI_OPCODE_DP3] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10627 [TGSI_OPCODE_DP4] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10628 [TGSI_OPCODE_DST] = { ALU_OP0_NOP, tgsi_opdst},
10629 [TGSI_OPCODE_MIN] = { ALU_OP2_MIN_DX10, tgsi_op2},
10630 [TGSI_OPCODE_MAX] = { ALU_OP2_MAX_DX10, tgsi_op2},
10631 [TGSI_OPCODE_SLT] = { ALU_OP2_SETGT, tgsi_op2_swap},
10632 [TGSI_OPCODE_SGE] = { ALU_OP2_SETGE, tgsi_op2},
10633 [TGSI_OPCODE_MAD] = { ALU_OP3_MULADD_IEEE, tgsi_op3},
10634 [TGSI_OPCODE_LRP] = { ALU_OP0_NOP, tgsi_lrp},
10635 [TGSI_OPCODE_FMA] = { ALU_OP3_FMA, tgsi_op3},
10636 [TGSI_OPCODE_SQRT] = { ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
10637 [21] = { ALU_OP0_NOP, tgsi_unsupported},
10638 [22] = { ALU_OP0_NOP, tgsi_unsupported},
10639 [23] = { ALU_OP0_NOP, tgsi_unsupported},
10640 [TGSI_OPCODE_FRC] = { ALU_OP1_FRACT, tgsi_op2},
10641 [25] = { ALU_OP0_NOP, tgsi_unsupported},
10642 [TGSI_OPCODE_FLR] = { ALU_OP1_FLOOR, tgsi_op2},
10643 [TGSI_OPCODE_ROUND] = { ALU_OP1_RNDNE, tgsi_op2},
10644 [TGSI_OPCODE_EX2] = { ALU_OP1_EXP_IEEE, cayman_emit_float_instr},
10645 [TGSI_OPCODE_LG2] = { ALU_OP1_LOG_IEEE, cayman_emit_float_instr},
10646 [TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
10647 [31] = { ALU_OP0_NOP, tgsi_unsupported},
10648 [32] = { ALU_OP0_NOP, tgsi_unsupported},
10649 [33] = { ALU_OP0_NOP, tgsi_unsupported},
10650 [34] = { ALU_OP0_NOP, tgsi_unsupported},
10651 [35] = { ALU_OP0_NOP, tgsi_unsupported},
10652 [TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
10653 [TGSI_OPCODE_DDX] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10654 [TGSI_OPCODE_DDY] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10655 [TGSI_OPCODE_KILL] = { ALU_OP2_KILLGT, tgsi_kill}, /* unconditional kill */
10656 [TGSI_OPCODE_PK2H] = { ALU_OP0_NOP, tgsi_pk2h},
10657 [TGSI_OPCODE_PK2US] = { ALU_OP0_NOP, tgsi_unsupported},
10658 [TGSI_OPCODE_PK4B] = { ALU_OP0_NOP, tgsi_unsupported},
10659 [TGSI_OPCODE_PK4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10660 [44] = { ALU_OP0_NOP, tgsi_unsupported},
10661 [TGSI_OPCODE_SEQ] = { ALU_OP2_SETE, tgsi_op2},
10662 [46] = { ALU_OP0_NOP, tgsi_unsupported},
10663 [TGSI_OPCODE_SGT] = { ALU_OP2_SETGT, tgsi_op2},
10664 [TGSI_OPCODE_SIN] = { ALU_OP1_SIN, cayman_trig},
10665 [TGSI_OPCODE_SLE] = { ALU_OP2_SETGE, tgsi_op2_swap},
10666 [TGSI_OPCODE_SNE] = { ALU_OP2_SETNE, tgsi_op2},
10667 [51] = { ALU_OP0_NOP, tgsi_unsupported},
10668 [TGSI_OPCODE_TEX] = { FETCH_OP_SAMPLE, tgsi_tex},
10669 [TGSI_OPCODE_TXD] = { FETCH_OP_SAMPLE_G, tgsi_tex},
10670 [TGSI_OPCODE_TXP] = { FETCH_OP_SAMPLE, tgsi_tex},
10671 [TGSI_OPCODE_UP2H] = { ALU_OP0_NOP, tgsi_up2h},
10672 [TGSI_OPCODE_UP2US] = { ALU_OP0_NOP, tgsi_unsupported},
10673 [TGSI_OPCODE_UP4B] = { ALU_OP0_NOP, tgsi_unsupported},
10674 [TGSI_OPCODE_UP4UB] = { ALU_OP0_NOP, tgsi_unsupported},
10675 [59] = { ALU_OP0_NOP, tgsi_unsupported},
10676 [60] = { ALU_OP0_NOP, tgsi_unsupported},
10677 [TGSI_OPCODE_ARR] = { ALU_OP0_NOP, tgsi_eg_arl},
10678 [62] = { ALU_OP0_NOP, tgsi_unsupported},
10679 [TGSI_OPCODE_CAL] = { ALU_OP0_NOP, tgsi_unsupported},
10680 [TGSI_OPCODE_RET] = { ALU_OP0_NOP, tgsi_unsupported},
10681 [TGSI_OPCODE_SSG] = { ALU_OP0_NOP, tgsi_ssg},
10682 [TGSI_OPCODE_CMP] = { ALU_OP0_NOP, tgsi_cmp},
10683 [67] = { ALU_OP0_NOP, tgsi_unsupported},
10684 [TGSI_OPCODE_TXB] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10685 [69] = { ALU_OP0_NOP, tgsi_unsupported},
10686 [TGSI_OPCODE_DIV] = { ALU_OP0_NOP, tgsi_unsupported},
10687 [TGSI_OPCODE_DP2] = { ALU_OP2_DOT4_IEEE, tgsi_dp},
10688 [TGSI_OPCODE_TXL] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10689 [TGSI_OPCODE_BRK] = { CF_OP_LOOP_BREAK, tgsi_loop_brk_cont},
10690 [TGSI_OPCODE_IF] = { ALU_OP0_NOP, tgsi_if},
10691 [TGSI_OPCODE_UIF] = { ALU_OP0_NOP, tgsi_uif},
10692 [76] = { ALU_OP0_NOP, tgsi_unsupported},
10693 [TGSI_OPCODE_ELSE] = { ALU_OP0_NOP, tgsi_else},
10694 [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif},
10695 [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex},
10696 [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex},
10697 [82] = { ALU_OP0_NOP, tgsi_unsupported},
10698 [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2},
10699 [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2},
10700 [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2},
10701 [TGSI_OPCODE_TRUNC] = { ALU_OP1_TRUNC, tgsi_op2},
10702 [TGSI_OPCODE_SHL] = { ALU_OP2_LSHL_INT, tgsi_op2},
10703 [88] = { ALU_OP0_NOP, tgsi_unsupported},
10704 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10705 [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2},
10706 [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod},
10707 [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2},
10708 [93] = { ALU_OP0_NOP, tgsi_unsupported},
10709 [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex},
10710 [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10711 [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont},
10712 [TGSI_OPCODE_EMIT] = { CF_OP_EMIT_VERTEX, tgsi_gs_emit},
10713 [TGSI_OPCODE_ENDPRIM] = { CF_OP_CUT_VERTEX, tgsi_gs_emit},
10714 [TGSI_OPCODE_BGNLOOP] = { ALU_OP0_NOP, tgsi_bgnloop},
10715 [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10716 [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop},
10717 [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported},
10718 [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex},
10719 [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex},
10720 [TGSI_OPCODE_RESQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_resq},
10721 [106] = { ALU_OP0_NOP, tgsi_unsupported},
10722 [TGSI_OPCODE_NOP] = { ALU_OP0_NOP, tgsi_unsupported},
10723 [TGSI_OPCODE_FSEQ] = { ALU_OP2_SETE_DX10, tgsi_op2},
10724 [TGSI_OPCODE_FSGE] = { ALU_OP2_SETGE_DX10, tgsi_op2},
10725 [TGSI_OPCODE_FSLT] = { ALU_OP2_SETGT_DX10, tgsi_op2_swap},
10726 [TGSI_OPCODE_FSNE] = { ALU_OP2_SETNE_DX10, tgsi_op2_swap},
10727 [TGSI_OPCODE_MEMBAR] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10728 [113] = { ALU_OP0_NOP, tgsi_unsupported},
10729 [114] = { ALU_OP0_NOP, tgsi_unsupported},
10730 [115] = { ALU_OP0_NOP, tgsi_unsupported},
10731 [TGSI_OPCODE_KILL_IF] = { ALU_OP2_KILLGT, tgsi_kill}, /* conditional kill */
10732 [TGSI_OPCODE_END] = { ALU_OP0_NOP, tgsi_end}, /* aka HALT */
10733 /* Refer below for TGSI_OPCODE_DFMA */
10734 [TGSI_OPCODE_F2I] = { ALU_OP1_FLT_TO_INT, tgsi_op2},
10735 [TGSI_OPCODE_IDIV] = { ALU_OP0_NOP, tgsi_idiv},
10736 [TGSI_OPCODE_IMAX] = { ALU_OP2_MAX_INT, tgsi_op2},
10737 [TGSI_OPCODE_IMIN] = { ALU_OP2_MIN_INT, tgsi_op2},
10738 [TGSI_OPCODE_INEG] = { ALU_OP2_SUB_INT, tgsi_ineg},
10739 [TGSI_OPCODE_ISGE] = { ALU_OP2_SETGE_INT, tgsi_op2},
10740 [TGSI_OPCODE_ISHR] = { ALU_OP2_ASHR_INT, tgsi_op2},
10741 [TGSI_OPCODE_ISLT] = { ALU_OP2_SETGT_INT, tgsi_op2_swap},
10742 [TGSI_OPCODE_F2U] = { ALU_OP1_FLT_TO_UINT, tgsi_op2},
10743 [TGSI_OPCODE_U2F] = { ALU_OP1_UINT_TO_FLT, tgsi_op2},
10744 [TGSI_OPCODE_UADD] = { ALU_OP2_ADD_INT, tgsi_op2},
10745 [TGSI_OPCODE_UDIV] = { ALU_OP0_NOP, tgsi_udiv},
10746 [TGSI_OPCODE_UMAD] = { ALU_OP0_NOP, tgsi_umad},
10747 [TGSI_OPCODE_UMAX] = { ALU_OP2_MAX_UINT, tgsi_op2},
10748 [TGSI_OPCODE_UMIN] = { ALU_OP2_MIN_UINT, tgsi_op2},
10749 [TGSI_OPCODE_UMOD] = { ALU_OP0_NOP, tgsi_umod},
10750 [TGSI_OPCODE_UMUL] = { ALU_OP2_MULLO_INT, cayman_mul_int_instr},
10751 [TGSI_OPCODE_USEQ] = { ALU_OP2_SETE_INT, tgsi_op2},
10752 [TGSI_OPCODE_USGE] = { ALU_OP2_SETGE_UINT, tgsi_op2},
10753 [TGSI_OPCODE_USHR] = { ALU_OP2_LSHR_INT, tgsi_op2},
10754 [TGSI_OPCODE_USLT] = { ALU_OP2_SETGT_UINT, tgsi_op2_swap},
10755 [TGSI_OPCODE_USNE] = { ALU_OP2_SETNE_INT, tgsi_op2},
10756 [TGSI_OPCODE_SWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10757 [TGSI_OPCODE_CASE] = { ALU_OP0_NOP, tgsi_unsupported},
10758 [TGSI_OPCODE_DEFAULT] = { ALU_OP0_NOP, tgsi_unsupported},
10759 [TGSI_OPCODE_ENDSWITCH] = { ALU_OP0_NOP, tgsi_unsupported},
10760 [TGSI_OPCODE_SAMPLE] = { 0, tgsi_unsupported},
10761 [TGSI_OPCODE_SAMPLE_I] = { 0, tgsi_unsupported},
10762 [TGSI_OPCODE_SAMPLE_I_MS] = { 0, tgsi_unsupported},
10763 [TGSI_OPCODE_SAMPLE_B] = { 0, tgsi_unsupported},
10764 [TGSI_OPCODE_SAMPLE_C] = { 0, tgsi_unsupported},
10765 [TGSI_OPCODE_SAMPLE_C_LZ] = { 0, tgsi_unsupported},
10766 [TGSI_OPCODE_SAMPLE_D] = { 0, tgsi_unsupported},
10767 [TGSI_OPCODE_SAMPLE_L] = { 0, tgsi_unsupported},
10768 [TGSI_OPCODE_GATHER4] = { 0, tgsi_unsupported},
10769 [TGSI_OPCODE_SVIEWINFO] = { 0, tgsi_unsupported},
10770 [TGSI_OPCODE_SAMPLE_POS] = { 0, tgsi_unsupported},
10771 [TGSI_OPCODE_SAMPLE_INFO] = { 0, tgsi_unsupported},
10772 [TGSI_OPCODE_UARL] = { ALU_OP1_MOVA_INT, tgsi_eg_arl},
10773 [TGSI_OPCODE_UCMP] = { ALU_OP0_NOP, tgsi_ucmp},
10774 [TGSI_OPCODE_IABS] = { 0, tgsi_iabs},
10775 [TGSI_OPCODE_ISSG] = { 0, tgsi_issg},
10776 [TGSI_OPCODE_LOAD] = { ALU_OP0_NOP, tgsi_load},
10777 [TGSI_OPCODE_STORE] = { ALU_OP0_NOP, tgsi_store},
10778 [163] = { ALU_OP0_NOP, tgsi_unsupported},
10779 [164] = { ALU_OP0_NOP, tgsi_unsupported},
10780 [165] = { ALU_OP0_NOP, tgsi_unsupported},
10781 [TGSI_OPCODE_BARRIER] = { ALU_OP0_GROUP_BARRIER, tgsi_barrier},
10782 [TGSI_OPCODE_ATOMUADD] = { V_RAT_INST_ADD_RTN, tgsi_atomic_op},
10783 [TGSI_OPCODE_ATOMXCHG] = { V_RAT_INST_XCHG_RTN, tgsi_atomic_op},
10784 [TGSI_OPCODE_ATOMCAS] = { V_RAT_INST_CMPXCHG_INT_RTN, tgsi_atomic_op},
10785 [TGSI_OPCODE_ATOMAND] = { V_RAT_INST_AND_RTN, tgsi_atomic_op},
10786 [TGSI_OPCODE_ATOMOR] = { V_RAT_INST_OR_RTN, tgsi_atomic_op},
10787 [TGSI_OPCODE_ATOMXOR] = { V_RAT_INST_XOR_RTN, tgsi_atomic_op},
10788 [TGSI_OPCODE_ATOMUMIN] = { V_RAT_INST_MIN_UINT_RTN, tgsi_atomic_op},
10789 [TGSI_OPCODE_ATOMUMAX] = { V_RAT_INST_MAX_UINT_RTN, tgsi_atomic_op},
10790 [TGSI_OPCODE_ATOMIMIN] = { V_RAT_INST_MIN_INT_RTN, tgsi_atomic_op},
10791 [TGSI_OPCODE_ATOMIMAX] = { V_RAT_INST_MAX_INT_RTN, tgsi_atomic_op},
10792 [TGSI_OPCODE_TEX2] = { FETCH_OP_SAMPLE, tgsi_tex},
10793 [TGSI_OPCODE_TXB2] = { FETCH_OP_SAMPLE_LB, tgsi_tex},
10794 [TGSI_OPCODE_TXL2] = { FETCH_OP_SAMPLE_L, tgsi_tex},
10795 [TGSI_OPCODE_IMUL_HI] = { ALU_OP2_MULHI_INT, cayman_mul_int_instr},
10796 [TGSI_OPCODE_UMUL_HI] = { ALU_OP2_MULHI_UINT, cayman_mul_int_instr},
10797 [TGSI_OPCODE_TG4] = { FETCH_OP_GATHER4, tgsi_tex},
10798 [TGSI_OPCODE_LODQ] = { FETCH_OP_GET_LOD, tgsi_tex},
10799 [TGSI_OPCODE_IBFE] = { ALU_OP3_BFE_INT, tgsi_bfe},
10800 [TGSI_OPCODE_UBFE] = { ALU_OP3_BFE_UINT, tgsi_bfe},
10801 [TGSI_OPCODE_BFI] = { ALU_OP0_NOP, tgsi_bfi},
10802 [TGSI_OPCODE_BREV] = { ALU_OP1_BFREV_INT, tgsi_op2},
10803 [TGSI_OPCODE_POPC] = { ALU_OP1_BCNT_INT, tgsi_op2},
10804 [TGSI_OPCODE_LSB] = { ALU_OP1_FFBL_INT, tgsi_op2},
10805 [TGSI_OPCODE_IMSB] = { ALU_OP1_FFBH_INT, tgsi_msb},
10806 [TGSI_OPCODE_UMSB] = { ALU_OP1_FFBH_UINT, tgsi_msb},
10807 [TGSI_OPCODE_INTERP_CENTROID] = { ALU_OP0_NOP, tgsi_interp_egcm},
10808 [TGSI_OPCODE_INTERP_SAMPLE] = { ALU_OP0_NOP, tgsi_interp_egcm},
10809 [TGSI_OPCODE_INTERP_OFFSET] = { ALU_OP0_NOP, tgsi_interp_egcm},
10810 [TGSI_OPCODE_F2D] = { ALU_OP1_FLT32_TO_FLT64, tgsi_op2_64},
10811 [TGSI_OPCODE_D2F] = { ALU_OP1_FLT64_TO_FLT32, tgsi_op2_64_single_dest},
10812 [TGSI_OPCODE_DABS] = { ALU_OP1_MOV, tgsi_op2_64},
10813 [TGSI_OPCODE_DNEG] = { ALU_OP2_ADD_64, tgsi_dneg},
10814 [TGSI_OPCODE_DADD] = { ALU_OP2_ADD_64, tgsi_op2_64},
10815 [TGSI_OPCODE_DMUL] = { ALU_OP2_MUL_64, cayman_mul_double_instr},
10816 [TGSI_OPCODE_DDIV] = { 0, cayman_ddiv_instr },
10817 [TGSI_OPCODE_DMAX] = { ALU_OP2_MAX_64, tgsi_op2_64},
10818 [TGSI_OPCODE_DMIN] = { ALU_OP2_MIN_64, tgsi_op2_64},
10819 [TGSI_OPCODE_DSLT] = { ALU_OP2_SETGT_64, tgsi_op2_64_single_dest_s},
10820 [TGSI_OPCODE_DSGE] = { ALU_OP2_SETGE_64, tgsi_op2_64_single_dest},
10821 [TGSI_OPCODE_DSEQ] = { ALU_OP2_SETE_64, tgsi_op2_64_single_dest},
10822 [TGSI_OPCODE_DSNE] = { ALU_OP2_SETNE_64, tgsi_op2_64_single_dest},
10823 [TGSI_OPCODE_DRCP] = { ALU_OP2_RECIP_64, cayman_emit_double_instr},
10824 [TGSI_OPCODE_DSQRT] = { ALU_OP2_SQRT_64, cayman_emit_double_instr},
10825 [TGSI_OPCODE_DMAD] = { ALU_OP3_FMA_64, tgsi_op3_64},
10826 [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64},
10827 [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64},
10828 [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64},
10829 [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp},
10830 [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int},
10831 [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double},
10832 [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
10833 [TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
10834 [TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
10835 [TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
10836 };